drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  43 static __must_check int
  44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  45                                bool readonly);
  46 static void
  47 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  48
  49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  50                                  struct drm_i915_gem_object *obj);
  51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  52                                          struct drm_i915_fence_reg *fence,
  53                                          bool enable);
  54
  55 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  56                                              struct shrink_control *sc);
  57 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  58                                             struct shrink_control *sc);
  59 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  60                                  unsigned long event,
  61                                  void *ptr);
  62 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  63
  64 static bool cpu_cache_is_coherent(struct drm_device *dev,
  65                                   enum i915_cache_level level)
  66 {
  67         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  68 }
  69
  70 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  71 {
  72         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  73                 return true;
  74
  75         return obj->pin_display;
  76 }
  77
  78 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  79 {
  80         if (obj->tiling_mode)
  81                 i915_gem_release_mmap(obj);
  82
  83         /* As we do not have an associated fence register, we will force
  84          * a tiling change if we ever need to acquire one.
  85          */
  86         obj->fence_dirty = false;
  87         obj->fence_reg = I915_FENCE_REG_NONE;
  88 }
  89
  90 /* some bookkeeping */
  91 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  92                                   size_t size)
  93 {
  94         spin_lock(&dev_priv->mm.object_stat_lock);
  95         dev_priv->mm.object_count++;
  96         dev_priv->mm.object_memory += size;
  97         spin_unlock(&dev_priv->mm.object_stat_lock);
  98 }
  99
 100 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 101                                      size_t size)
 102 {
 103         spin_lock(&dev_priv->mm.object_stat_lock);
 104         dev_priv->mm.object_count--;
 105         dev_priv->mm.object_memory -= size;
 106         spin_unlock(&dev_priv->mm.object_stat_lock);
 107 }
 108
 109 static int
 110 i915_gem_wait_for_error(struct i915_gpu_error *error)
 111 {
 112         int ret;
 113
 114 #define EXIT_COND (!i915_reset_in_progress(error) || \
 115                    i915_terminally_wedged(error))
 116         if (EXIT_COND)
 117                 return 0;
 118
 119         /*
 120          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 121          * userspace. If it takes that long something really bad is going on and
 122          * we should simply try to bail out and fail as gracefully as possible.
 123          */
 124         ret = wait_event_interruptible_timeout(error->reset_queue,
 125                                                EXIT_COND,
 126                                                10*HZ);
 127         if (ret == 0) {
 128                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 129                 return -EIO;
 130         } else if (ret < 0) {
 131                 return ret;
 132         }
 133 #undef EXIT_COND
 134
 135         return 0;
 136 }
 137
 138 int i915_mutex_lock_interruptible(struct drm_device *dev)
 139 {
 140         struct drm_i915_private *dev_priv = dev->dev_private;
 141         int ret;
 142
 143         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 144         if (ret)
 145                 return ret;
 146
 147         ret = mutex_lock_interruptible(&dev->struct_mutex);
 148         if (ret)
 149                 return ret;
 150
 151         WARN_ON(i915_verify_lists(dev));
 152         return 0;
 153 }
 154
 155 int
 156 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 157                             struct drm_file *file)
 158 {
 159         struct drm_i915_private *dev_priv = dev->dev_private;
 160         struct drm_i915_gem_get_aperture *args = data;
 161         struct drm_i915_gem_object *obj;
 162         size_t pinned;
 163
 164         pinned = 0;
 165         mutex_lock(&dev->struct_mutex);
 166         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 167                 if (i915_gem_obj_is_pinned(obj))
 168                         pinned += i915_gem_obj_ggtt_size(obj);
 169         mutex_unlock(&dev->struct_mutex);
 170
 171         args->aper_size = dev_priv->gtt.base.total;
 172         args->aper_available_size = args->aper_size - pinned;
 173
 174         return 0;
 175 }
 176
 177 static int
 178 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 179 {
 180         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 181         char *vaddr = obj->phys_handle->vaddr;
 182         struct sg_table *st;
 183         struct scatterlist *sg;
 184         int i;
 185
 186         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 187                 return -EINVAL;
 188
 189         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 190                 struct page *page;
 191                 char *src;
 192
 193                 page = shmem_read_mapping_page(mapping, i);
 194                 if (IS_ERR(page))
 195                         return PTR_ERR(page);
 196
 197                 src = kmap_atomic(page);
 198                 memcpy(vaddr, src, PAGE_SIZE);
 199                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 200                 kunmap_atomic(src);
 201
 202                 page_cache_release(page);
 203                 vaddr += PAGE_SIZE;
 204         }
 205
 206         i915_gem_chipset_flush(obj->base.dev);
 207
 208         st = kmalloc(sizeof(*st), GFP_KERNEL);
 209         if (st == NULL)
 210                 return -ENOMEM;
 211
 212         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 213                 kfree(st);
 214                 return -ENOMEM;
 215         }
 216
 217         sg = st->sgl;
 218         sg->offset = 0;
 219         sg->length = obj->base.size;
 220
 221         sg_dma_address(sg) = obj->phys_handle->busaddr;
 222         sg_dma_len(sg) = obj->base.size;
 223
 224         obj->pages = st;
 225         obj->has_dma_mapping = true;
 226         return 0;
 227 }
 228
 229 static void
 230 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 231 {
 232         int ret;
 233
 234         BUG_ON(obj->madv == __I915_MADV_PURGED);
 235
 236         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 237         if (ret) {
 238                 /* In the event of a disaster, abandon all caches and
 239                  * hope for the best.
 240                  */
 241                 WARN_ON(ret != -EIO);
 242                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 243         }
 244
 245         if (obj->madv == I915_MADV_DONTNEED)
 246                 obj->dirty = 0;
 247
 248         if (obj->dirty) {
 249                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 250                 char *vaddr = obj->phys_handle->vaddr;
 251                 int i;
 252
 253                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 254                         struct page *page;
 255                         char *dst;
 256
 257                         page = shmem_read_mapping_page(mapping, i);
 258                         if (IS_ERR(page))
 259                                 continue;
 260
 261                         dst = kmap_atomic(page);
 262                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 263                         memcpy(dst, vaddr, PAGE_SIZE);
 264                         kunmap_atomic(dst);
 265
 266                         set_page_dirty(page);
 267                         if (obj->madv == I915_MADV_WILLNEED)
 268                                 mark_page_accessed(page);
 269                         page_cache_release(page);
 270                         vaddr += PAGE_SIZE;
 271                 }
 272                 obj->dirty = 0;
 273         }
 274
 275         sg_free_table(obj->pages);
 276         kfree(obj->pages);
 277
 278         obj->has_dma_mapping = false;
 279 }
 280
 281 static void
 282 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 283 {
 284         drm_pci_free(obj->base.dev, obj->phys_handle);
 285 }
 286
 287 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 288         .get_pages = i915_gem_object_get_pages_phys,
 289         .put_pages = i915_gem_object_put_pages_phys,
 290         .release = i915_gem_object_release_phys,
 291 };
 292
 293 static int
 294 drop_pages(struct drm_i915_gem_object *obj)
 295 {
 296         struct i915_vma *vma, *next;
 297         int ret;
 298
 299         drm_gem_object_reference(&obj->base);
 300         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 301                 if (i915_vma_unbind(vma))
 302                         break;
 303
 304         ret = i915_gem_object_put_pages(obj);
 305         drm_gem_object_unreference(&obj->base);
 306
 307         return ret;
 308 }
 309
 310 int
 311 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 312                             int align)
 313 {
 314         drm_dma_handle_t *phys;
 315         int ret;
 316
 317         if (obj->phys_handle) {
 318                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 319                         return -EBUSY;
 320
 321                 return 0;
 322         }
 323
 324         if (obj->madv != I915_MADV_WILLNEED)
 325                 return -EFAULT;
 326
 327         if (obj->base.filp == NULL)
 328                 return -EINVAL;
 329
 330         ret = drop_pages(obj);
 331         if (ret)
 332                 return ret;
 333
 334         /* create a new object */
 335         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 336         if (!phys)
 337                 return -ENOMEM;
 338
 339         obj->phys_handle = phys;
 340         obj->ops = &i915_gem_phys_ops;
 341
 342         return i915_gem_object_get_pages(obj);
 343 }
 344
 345 static int
 346 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 347                      struct drm_i915_gem_pwrite *args,
 348                      struct drm_file *file_priv)
 349 {
 350         struct drm_device *dev = obj->base.dev;
 351         void *vaddr = obj->phys_handle->vaddr + args->offset;
 352         char __user *user_data = to_user_ptr(args->data_ptr);
 353         int ret;
 354
 355         /* We manually control the domain here and pretend that it
 356          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 357          */
 358         ret = i915_gem_object_wait_rendering(obj, false);
 359         if (ret)
 360                 return ret;
 361
 362         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 363                 unsigned long unwritten;
 364
 365                 /* The physical object once assigned is fixed for the lifetime
 366                  * of the obj, so we can safely drop the lock and continue
 367                  * to access vaddr.
 368                  */
 369                 mutex_unlock(&dev->struct_mutex);
 370                 unwritten = copy_from_user(vaddr, user_data, args->size);
 371                 mutex_lock(&dev->struct_mutex);
 372                 if (unwritten)
 373                         return -EFAULT;
 374         }
 375
 376         drm_clflush_virt_range(vaddr, args->size);
 377         i915_gem_chipset_flush(dev);
 378         return 0;
 379 }
 380
 381 void *i915_gem_object_alloc(struct drm_device *dev)
 382 {
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 385 }
 386
 387 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 388 {
 389         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 390         kmem_cache_free(dev_priv->slab, obj);
 391 }
 392
 393 static int
 394 i915_gem_create(struct drm_file *file,
 395                 struct drm_device *dev,
 396                 uint64_t size,
 397                 uint32_t *handle_p)
 398 {
 399         struct drm_i915_gem_object *obj;
 400         int ret;
 401         u32 handle;
 402
 403         size = roundup(size, PAGE_SIZE);
 404         if (size == 0)
 405                 return -EINVAL;
 406
 407         /* Allocate the new object */
 408         obj = i915_gem_alloc_object(dev, size);
 409         if (obj == NULL)
 410                 return -ENOMEM;
 411
 412         ret = drm_gem_handle_create(file, &obj->base, &handle);
 413         /* drop reference from allocate - handle holds it now */
 414         drm_gem_object_unreference_unlocked(&obj->base);
 415         if (ret)
 416                 return ret;
 417
 418         *handle_p = handle;
 419         return 0;
 420 }
 421
 422 int
 423 i915_gem_dumb_create(struct drm_file *file,
 424                      struct drm_device *dev,
 425                      struct drm_mode_create_dumb *args)
 426 {
 427         /* have to work out size/pitch and return them */
 428         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 429         args->size = args->pitch * args->height;
 430         return i915_gem_create(file, dev,
 431                                args->size, &args->handle);
 432 }
 433
 434 /**
 435  * Creates a new mm object and returns a handle to it.
 436  */
 437 int
 438 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 439                       struct drm_file *file)
 440 {
 441         struct drm_i915_gem_create *args = data;
 442
 443         return i915_gem_create(file, dev,
 444                                args->size, &args->handle);
 445 }
 446
 447 static inline int
 448 __copy_to_user_swizzled(char __user *cpu_vaddr,
 449                         const char *gpu_vaddr, int gpu_offset,
 450                         int length)
 451 {
 452         int ret, cpu_offset = 0;
 453
 454         while (length > 0) {
 455                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 456                 int this_length = min(cacheline_end - gpu_offset, length);
 457                 int swizzled_gpu_offset = gpu_offset ^ 64;
 458
 459                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 460                                      gpu_vaddr + swizzled_gpu_offset,
 461                                      this_length);
 462                 if (ret)
 463                         return ret + length;
 464
 465                 cpu_offset += this_length;
 466                 gpu_offset += this_length;
 467                 length -= this_length;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static inline int
 474 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 475                           const char __user *cpu_vaddr,
 476                           int length)
 477 {
 478         int ret, cpu_offset = 0;
 479
 480         while (length > 0) {
 481                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 482                 int this_length = min(cacheline_end - gpu_offset, length);
 483                 int swizzled_gpu_offset = gpu_offset ^ 64;
 484
 485                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 486                                        cpu_vaddr + cpu_offset,
 487                                        this_length);
 488                 if (ret)
 489                         return ret + length;
 490
 491                 cpu_offset += this_length;
 492                 gpu_offset += this_length;
 493                 length -= this_length;
 494         }
 495
 496         return 0;
 497 }
 498
 499 /*
 500  * Pins the specified object's pages and synchronizes the object with
 501  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 502  * flush the object from the CPU cache.
 503  */
 504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 505                                     int *needs_clflush)
 506 {
 507         int ret;
 508
 509         *needs_clflush = 0;
 510
 511         if (!obj->base.filp)
 512                 return -EINVAL;
 513
 514         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 515                 /* If we're not in the cpu read domain, set ourself into the gtt
 516                  * read domain and manually flush cachelines (if required). This
 517                  * optimizes for the case when the gpu will dirty the data
 518                  * anyway again before the next pread happens. */
 519                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 520                                                         obj->cache_level);
 521                 ret = i915_gem_object_wait_rendering(obj, true);
 522                 if (ret)
 523                         return ret;
 524
 525                 i915_gem_object_retire(obj);
 526         }
 527
 528         ret = i915_gem_object_get_pages(obj);
 529         if (ret)
 530                 return ret;
 531
 532         i915_gem_object_pin_pages(obj);
 533
 534         return ret;
 535 }
 536
 537 /* Per-page copy function for the shmem pread fastpath.
 538  * Flushes invalid cachelines before reading the target if
 539  * needs_clflush is set. */
 540 static int
 541 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         if (unlikely(page_do_bit17_swizzling))
 549                 return -EINVAL;
 550
 551         vaddr = kmap_atomic(page);
 552         if (needs_clflush)
 553                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 554                                        page_length);
 555         ret = __copy_to_user_inatomic(user_data,
 556                                       vaddr + shmem_page_offset,
 557                                       page_length);
 558         kunmap_atomic(vaddr);
 559
 560         return ret ? -EFAULT : 0;
 561 }
 562
 563 static void
 564 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 565                              bool swizzled)
 566 {
 567         if (unlikely(swizzled)) {
 568                 unsigned long start = (unsigned long) addr;
 569                 unsigned long end = (unsigned long) addr + length;
 570
 571                 /* For swizzling simply ensure that we always flush both
 572                  * channels. Lame, but simple and it works. Swizzled
 573                  * pwrite/pread is far from a hotpath - current userspace
 574                  * doesn't use it at all. */
 575                 start = round_down(start, 128);
 576                 end = round_up(end, 128);
 577
 578                 drm_clflush_virt_range((void *)start, end - start);
 579         } else {
 580                 drm_clflush_virt_range(addr, length);
 581         }
 582
 583 }
 584
 585 /* Only difference to the fast-path function is that this can handle bit17
 586  * and uses non-atomic copy and kmap functions. */
 587 static int
 588 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 589                  char __user *user_data,
 590                  bool page_do_bit17_swizzling, bool needs_clflush)
 591 {
 592         char *vaddr;
 593         int ret;
 594
 595         vaddr = kmap(page);
 596         if (needs_clflush)
 597                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 598                                              page_length,
 599                                              page_do_bit17_swizzling);
 600
 601         if (page_do_bit17_swizzling)
 602                 ret = __copy_to_user_swizzled(user_data,
 603                                               vaddr, shmem_page_offset,
 604                                               page_length);
 605         else
 606                 ret = __copy_to_user(user_data,
 607                                      vaddr + shmem_page_offset,
 608                                      page_length);
 609         kunmap(page);
 610
 611         return ret ? - EFAULT : 0;
 612 }
 613
 614 static int
 615 i915_gem_shmem_pread(struct drm_device *dev,
 616                      struct drm_i915_gem_object *obj,
 617                      struct drm_i915_gem_pread *args,
 618                      struct drm_file *file)
 619 {
 620         char __user *user_data;
 621         ssize_t remain;
 622         loff_t offset;
 623         int shmem_page_offset, page_length, ret = 0;
 624         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 625         int prefaulted = 0;
 626         int needs_clflush = 0;
 627         struct sg_page_iter sg_iter;
 628
 629         user_data = to_user_ptr(args->data_ptr);
 630         remain = args->size;
 631
 632         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 633
 634         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 635         if (ret)
 636                 return ret;
 637
 638         offset = args->offset;
 639
 640         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 641                          offset >> PAGE_SHIFT) {
 642                 struct page *page = sg_page_iter_page(&sg_iter);
 643
 644                 if (remain <= 0)
 645                         break;
 646
 647                 /* Operation in this page
 648                  *
 649                  * shmem_page_offset = offset within page in shmem file
 650                  * page_length = bytes to copy for this page
 651                  */
 652                 shmem_page_offset = offset_in_page(offset);
 653                 page_length = remain;
 654                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 655                         page_length = PAGE_SIZE - shmem_page_offset;
 656
 657                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 658                         (page_to_phys(page) & (1 << 17)) != 0;
 659
 660                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 661                                        user_data, page_do_bit17_swizzling,
 662                                        needs_clflush);
 663                 if (ret == 0)
 664                         goto next_page;
 665
 666                 mutex_unlock(&dev->struct_mutex);
 667
 668                 if (likely(!i915.prefault_disable) && !prefaulted) {
 669                         ret = fault_in_multipages_writeable(user_data, remain);
 670                         /* Userspace is tricking us, but we've already clobbered
 671                          * its pages with the prefault and promised to write the
 672                          * data up to the first fault. Hence ignore any errors
 673                          * and just continue. */
 674                         (void)ret;
 675                         prefaulted = 1;
 676                 }
 677
 678                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 679                                        user_data, page_do_bit17_swizzling,
 680                                        needs_clflush);
 681
 682                 mutex_lock(&dev->struct_mutex);
 683
 684                 if (ret)
 685                         goto out;
 686
 687 next_page:
 688                 remain -= page_length;
 689                 user_data += page_length;
 690                 offset += page_length;
 691         }
 692
 693 out:
 694         i915_gem_object_unpin_pages(obj);
 695
 696         return ret;
 697 }
 698
 699 /**
 700  * Reads data from the object referenced by handle.
 701  *
 702  * On error, the contents of *data are undefined.
 703  */
 704 int
 705 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 706                      struct drm_file *file)
 707 {
 708         struct drm_i915_gem_pread *args = data;
 709         struct drm_i915_gem_object *obj;
 710         int ret = 0;
 711
 712         if (args->size == 0)
 713                 return 0;
 714
 715         if (!access_ok(VERIFY_WRITE,
 716                        to_user_ptr(args->data_ptr),
 717                        args->size))
 718                 return -EFAULT;
 719
 720         ret = i915_mutex_lock_interruptible(dev);
 721         if (ret)
 722                 return ret;
 723
 724         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 725         if (&obj->base == NULL) {
 726                 ret = -ENOENT;
 727                 goto unlock;
 728         }
 729
 730         /* Bounds check source.  */
 731         if (args->offset > obj->base.size ||
 732             args->size > obj->base.size - args->offset) {
 733                 ret = -EINVAL;
 734                 goto out;
 735         }
 736
 737         /* prime objects have no backing filp to GEM pread/pwrite
 738          * pages from.
 739          */
 740         if (!obj->base.filp) {
 741                 ret = -EINVAL;
 742                 goto out;
 743         }
 744
 745         trace_i915_gem_object_pread(obj, args->offset, args->size);
 746
 747         ret = i915_gem_shmem_pread(dev, obj, args, file);
 748
 749 out:
 750         drm_gem_object_unreference(&obj->base);
 751 unlock:
 752         mutex_unlock(&dev->struct_mutex);
 753         return ret;
 754 }
 755
 756 /* This is the fast write path which cannot handle
 757  * page faults in the source data
 758  */
 759
 760 static inline int
 761 fast_user_write(struct io_mapping *mapping,
 762                 loff_t page_base, int page_offset,
 763                 char __user *user_data,
 764                 int length)
 765 {
 766         void __iomem *vaddr_atomic;
 767         void *vaddr;
 768         unsigned long unwritten;
 769
 770         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 771         /* We can use the cpu mem copy function because this is X86. */
 772         vaddr = (void __force*)vaddr_atomic + page_offset;
 773         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 774                                                       user_data, length);
 775         io_mapping_unmap_atomic(vaddr_atomic);
 776         return unwritten;
 777 }
 778
 779 /**
 780  * This is the fast pwrite path, where we copy the data directly from the
 781  * user into the GTT, uncached.
 782  */
 783 static int
 784 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 785                          struct drm_i915_gem_object *obj,
 786                          struct drm_i915_gem_pwrite *args,
 787                          struct drm_file *file)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         ssize_t remain;
 791         loff_t offset, page_base;
 792         char __user *user_data;
 793         int page_offset, page_length, ret;
 794
 795         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 796         if (ret)
 797                 goto out;
 798
 799         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 800         if (ret)
 801                 goto out_unpin;
 802
 803         ret = i915_gem_object_put_fence(obj);
 804         if (ret)
 805                 goto out_unpin;
 806
 807         user_data = to_user_ptr(args->data_ptr);
 808         remain = args->size;
 809
 810         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 811
 812         while (remain > 0) {
 813                 /* Operation in this page
 814                  *
 815                  * page_base = page offset within aperture
 816                  * page_offset = offset within page
 817                  * page_length = bytes to copy for this page
 818                  */
 819                 page_base = offset & PAGE_MASK;
 820                 page_offset = offset_in_page(offset);
 821                 page_length = remain;
 822                 if ((page_offset + remain) > PAGE_SIZE)
 823                         page_length = PAGE_SIZE - page_offset;
 824
 825                 /* If we get a fault while copying data, then (presumably) our
 826                  * source page isn't available.  Return the error and we'll
 827                  * retry in the slow path.
 828                  */
 829                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 830                                     page_offset, user_data, page_length)) {
 831                         ret = -EFAULT;
 832                         goto out_unpin;
 833                 }
 834
 835                 remain -= page_length;
 836                 user_data += page_length;
 837                 offset += page_length;
 838         }
 839
 840 out_unpin:
 841         i915_gem_object_ggtt_unpin(obj);
 842 out:
 843         return ret;
 844 }
 845
 846 /* Per-page copy function for the shmem pwrite fastpath.
 847  * Flushes invalid cachelines before writing to the target if
 848  * needs_clflush_before is set and flushes out any written cachelines after
 849  * writing if needs_clflush is set. */
 850 static int
 851 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 852                   char __user *user_data,
 853                   bool page_do_bit17_swizzling,
 854                   bool needs_clflush_before,
 855                   bool needs_clflush_after)
 856 {
 857         char *vaddr;
 858         int ret;
 859
 860         if (unlikely(page_do_bit17_swizzling))
 861                 return -EINVAL;
 862
 863         vaddr = kmap_atomic(page);
 864         if (needs_clflush_before)
 865                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 866                                        page_length);
 867         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 868                                         user_data, page_length);
 869         if (needs_clflush_after)
 870                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 871                                        page_length);
 872         kunmap_atomic(vaddr);
 873
 874         return ret ? -EFAULT : 0;
 875 }
 876
 877 /* Only difference to the fast-path function is that this can handle bit17
 878  * and uses non-atomic copy and kmap functions. */
 879 static int
 880 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 881                   char __user *user_data,
 882                   bool page_do_bit17_swizzling,
 883                   bool needs_clflush_before,
 884                   bool needs_clflush_after)
 885 {
 886         char *vaddr;
 887         int ret;
 888
 889         vaddr = kmap(page);
 890         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 891                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 892                                              page_length,
 893                                              page_do_bit17_swizzling);
 894         if (page_do_bit17_swizzling)
 895                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 896                                                 user_data,
 897                                                 page_length);
 898         else
 899                 ret = __copy_from_user(vaddr + shmem_page_offset,
 900                                        user_data,
 901                                        page_length);
 902         if (needs_clflush_after)
 903                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 904                                              page_length,
 905                                              page_do_bit17_swizzling);
 906         kunmap(page);
 907
 908         return ret ? -EFAULT : 0;
 909 }
 910
 911 static int
 912 i915_gem_shmem_pwrite(struct drm_device *dev,
 913                       struct drm_i915_gem_object *obj,
 914                       struct drm_i915_gem_pwrite *args,
 915                       struct drm_file *file)
 916 {
 917         ssize_t remain;
 918         loff_t offset;
 919         char __user *user_data;
 920         int shmem_page_offset, page_length, ret = 0;
 921         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 922         int hit_slowpath = 0;
 923         int needs_clflush_after = 0;
 924         int needs_clflush_before = 0;
 925         struct sg_page_iter sg_iter;
 926
 927         user_data = to_user_ptr(args->data_ptr);
 928         remain = args->size;
 929
 930         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 931
 932         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 933                 /* If we're not in the cpu write domain, set ourself into the gtt
 934                  * write domain and manually flush cachelines (if required). This
 935                  * optimizes for the case when the gpu will use the data
 936                  * right away and we therefore have to clflush anyway. */
 937                 needs_clflush_after = cpu_write_needs_clflush(obj);
 938                 ret = i915_gem_object_wait_rendering(obj, false);
 939                 if (ret)
 940                         return ret;
 941
 942                 i915_gem_object_retire(obj);
 943         }
 944         /* Same trick applies to invalidate partially written cachelines read
 945          * before writing. */
 946         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 947                 needs_clflush_before =
 948                         !cpu_cache_is_coherent(dev, obj->cache_level);
 949
 950         ret = i915_gem_object_get_pages(obj);
 951         if (ret)
 952                 return ret;
 953
 954         i915_gem_object_pin_pages(obj);
 955
 956         offset = args->offset;
 957         obj->dirty = 1;
 958
 959         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 960                          offset >> PAGE_SHIFT) {
 961                 struct page *page = sg_page_iter_page(&sg_iter);
 962                 int partial_cacheline_write;
 963
 964                 if (remain <= 0)
 965                         break;
 966
 967                 /* Operation in this page
 968                  *
 969                  * shmem_page_offset = offset within page in shmem file
 970                  * page_length = bytes to copy for this page
 971                  */
 972                 shmem_page_offset = offset_in_page(offset);
 973
 974                 page_length = remain;
 975                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 976                         page_length = PAGE_SIZE - shmem_page_offset;
 977
 978                 /* If we don't overwrite a cacheline completely we need to be
 979                  * careful to have up-to-date data by first clflushing. Don't
 980                  * overcomplicate things and flush the entire patch. */
 981                 partial_cacheline_write = needs_clflush_before &&
 982                         ((shmem_page_offset | page_length)
 983                                 & (boot_cpu_data.x86_clflush_size - 1));
 984
 985                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 986                         (page_to_phys(page) & (1 << 17)) != 0;
 987
 988                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 989                                         user_data, page_do_bit17_swizzling,
 990                                         partial_cacheline_write,
 991                                         needs_clflush_after);
 992                 if (ret == 0)
 993                         goto next_page;
 994
 995                 hit_slowpath = 1;
 996                 mutex_unlock(&dev->struct_mutex);
 997                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 998                                         user_data, page_do_bit17_swizzling,
 999                                         partial_cacheline_write,
1000                                         needs_clflush_after);
1001
1002                 mutex_lock(&dev->struct_mutex);
1003
1004                 if (ret)
1005                         goto out;
1006
1007 next_page:
1008                 remain -= page_length;
1009                 user_data += page_length;
1010                 offset += page_length;
1011         }
1012
1013 out:
1014         i915_gem_object_unpin_pages(obj);
1015
1016         if (hit_slowpath) {
1017                 /*
1018                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1019                  * cachelines in-line while writing and the object moved
1020                  * out of the cpu write domain while we've dropped the lock.
1021                  */
1022                 if (!needs_clflush_after &&
1023                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1024                         if (i915_gem_clflush_object(obj, obj->pin_display))
1025                                 i915_gem_chipset_flush(dev);
1026                 }
1027         }
1028
1029         if (needs_clflush_after)
1030                 i915_gem_chipset_flush(dev);
1031
1032         return ret;
1033 }
1034
1035 /**
1036  * Writes data to the object referenced by handle.
1037  *
1038  * On error, the contents of the buffer that were to be modified are undefined.
1039  */
1040 int
1041 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1042                       struct drm_file *file)
1043 {
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045         struct drm_i915_gem_pwrite *args = data;
1046         struct drm_i915_gem_object *obj;
1047         int ret;
1048
1049         if (args->size == 0)
1050                 return 0;
1051
1052         if (!access_ok(VERIFY_READ,
1053                        to_user_ptr(args->data_ptr),
1054                        args->size))
1055                 return -EFAULT;
1056
1057         if (likely(!i915.prefault_disable)) {
1058                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1059                                                    args->size);
1060                 if (ret)
1061                         return -EFAULT;
1062         }
1063
1064         intel_runtime_pm_get(dev_priv);
1065
1066         ret = i915_mutex_lock_interruptible(dev);
1067         if (ret)
1068                 goto put_rpm;
1069
1070         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071         if (&obj->base == NULL) {
1072                 ret = -ENOENT;
1073                 goto unlock;
1074         }
1075
1076         /* Bounds check destination. */
1077         if (args->offset > obj->base.size ||
1078             args->size > obj->base.size - args->offset) {
1079                 ret = -EINVAL;
1080                 goto out;
1081         }
1082
1083         /* prime objects have no backing filp to GEM pread/pwrite
1084          * pages from.
1085          */
1086         if (!obj->base.filp) {
1087                 ret = -EINVAL;
1088                 goto out;
1089         }
1090
1091         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1092
1093         ret = -EFAULT;
1094         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095          * it would end up going through the fenced access, and we'll get
1096          * different detiling behavior between reading and writing.
1097          * pread/pwrite currently are reading and writing from the CPU
1098          * perspective, requiring manual detiling by the client.
1099          */
1100         if (obj->tiling_mode == I915_TILING_NONE &&
1101             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102             cpu_write_needs_clflush(obj)) {
1103                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104                 /* Note that the gtt paths might fail with non-page-backed user
1105                  * pointers (e.g. gtt mappings when moving data between
1106                  * textures). Fallback to the shmem path in that case. */
1107         }
1108
1109         if (ret == -EFAULT || ret == -ENOSPC) {
1110                 if (obj->phys_handle)
1111                         ret = i915_gem_phys_pwrite(obj, args, file);
1112                 else
1113                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1114         }
1115
1116 out:
1117         drm_gem_object_unreference(&obj->base);
1118 unlock:
1119         mutex_unlock(&dev->struct_mutex);
1120 put_rpm:
1121         intel_runtime_pm_put(dev_priv);
1122
1123         return ret;
1124 }
1125
1126 int
1127 i915_gem_check_wedge(struct i915_gpu_error *error,
1128                      bool interruptible)
1129 {
1130         if (i915_reset_in_progress(error)) {
1131                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132                  * -EIO unconditionally for these. */
1133                 if (!interruptible)
1134                         return -EIO;
1135
1136                 /* Recovery complete, but the reset failed ... */
1137                 if (i915_terminally_wedged(error))
1138                         return -EIO;
1139
1140                 /*
1141                  * Check if GPU Reset is in progress - we need intel_ring_begin
1142                  * to work properly to reinit the hw state while the gpu is
1143                  * still marked as reset-in-progress. Handle this with a flag.
1144                  */
1145                 if (!error->reload_in_reset)
1146                         return -EAGAIN;
1147         }
1148
1149         return 0;
1150 }
1151
1152 /*
1153  * Compare arbitrary request against outstanding lazy request. Emit on match.
1154  */
1155 int
1156 i915_gem_check_olr(struct drm_i915_gem_request *req)
1157 {
1158         int ret;
1159
1160         WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1161
1162         ret = 0;
1163         if (req == req->ring->outstanding_lazy_request)
1164                 ret = i915_add_request(req->ring);
1165
1166         return ret;
1167 }
1168
1169 static void fake_irq(unsigned long data)
1170 {
1171         wake_up_process((struct task_struct *)data);
1172 }
1173
1174 static bool missed_irq(struct drm_i915_private *dev_priv,
1175                        struct intel_engine_cs *ring)
1176 {
1177         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1178 }
1179
1180 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1181 {
1182         if (file_priv == NULL)
1183                 return true;
1184
1185         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1186 }
1187
1188 /**
1189  * __i915_wait_request - wait until execution of request has finished
1190  * @req: duh!
1191  * @reset_counter: reset sequence associated with the given request
1192  * @interruptible: do an interruptible wait (normally yes)
1193  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1194  *
1195  * Note: It is of utmost importance that the passed in seqno and reset_counter
1196  * values have been read by the caller in an smp safe manner. Where read-side
1197  * locks are involved, it is sufficient to read the reset_counter before
1198  * unlocking the lock that protects the seqno. For lockless tricks, the
1199  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1200  * inserted.
1201  *
1202  * Returns 0 if the request was found within the alloted time. Else returns the
1203  * errno with remaining time filled in timeout argument.
1204  */
1205 int __i915_wait_request(struct drm_i915_gem_request *req,
1206                         unsigned reset_counter,
1207                         bool interruptible,
1208                         s64 *timeout,
1209                         struct drm_i915_file_private *file_priv)
1210 {
1211         struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1212         struct drm_device *dev = ring->dev;
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214         const bool irq_test_in_progress =
1215                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1216         DEFINE_WAIT(wait);
1217         unsigned long timeout_expire;
1218         s64 before, now;
1219         int ret;
1220
1221         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1222
1223         if (i915_gem_request_completed(req, true))
1224                 return 0;
1225
1226         timeout_expire = timeout ?
1227                 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1228
1229         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1230                 gen6_rps_boost(dev_priv);
1231                 if (file_priv)
1232                         mod_delayed_work(dev_priv->wq,
1233                                          &file_priv->mm.idle_work,
1234                                          msecs_to_jiffies(100));
1235         }
1236
1237         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1238                 return -ENODEV;
1239
1240         /* Record current time in case interrupted by signal, or wedged */
1241         trace_i915_gem_request_wait_begin(req);
1242         before = ktime_get_raw_ns();
1243         for (;;) {
1244                 struct timer_list timer;
1245
1246                 prepare_to_wait(&ring->irq_queue, &wait,
1247                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1248
1249                 /* We need to check whether any gpu reset happened in between
1250                  * the caller grabbing the seqno and now ... */
1251                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1252                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1253                          * is truely gone. */
1254                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1255                         if (ret == 0)
1256                                 ret = -EAGAIN;
1257                         break;
1258                 }
1259
1260                 if (i915_gem_request_completed(req, false)) {
1261                         ret = 0;
1262                         break;
1263                 }
1264
1265                 if (interruptible && signal_pending(current)) {
1266                         ret = -ERESTARTSYS;
1267                         break;
1268                 }
1269
1270                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1271                         ret = -ETIME;
1272                         break;
1273                 }
1274
1275                 timer.function = NULL;
1276                 if (timeout || missed_irq(dev_priv, ring)) {
1277                         unsigned long expire;
1278
1279                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1280                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1281                         mod_timer(&timer, expire);
1282                 }
1283
1284                 io_schedule();
1285
1286                 if (timer.function) {
1287                         del_singleshot_timer_sync(&timer);
1288                         destroy_timer_on_stack(&timer);
1289                 }
1290         }
1291         now = ktime_get_raw_ns();
1292         trace_i915_gem_request_wait_end(req);
1293
1294         if (!irq_test_in_progress)
1295                 ring->irq_put(ring);
1296
1297         finish_wait(&ring->irq_queue, &wait);
1298
1299         if (timeout) {
1300                 s64 tres = *timeout - (now - before);
1301
1302                 *timeout = tres < 0 ? 0 : tres;
1303
1304                 /*
1305                  * Apparently ktime isn't accurate enough and occasionally has a
1306                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1307                  * things up to make the test happy. We allow up to 1 jiffy.
1308                  *
1309                  * This is a regrssion from the timespec->ktime conversion.
1310                  */
1311                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1312                         *timeout = 0;
1313         }
1314
1315         return ret;
1316 }
1317
1318 /**
1319  * Waits for a request to be signaled, and cleans up the
1320  * request and object lists appropriately for that event.
1321  */
1322 int
1323 i915_wait_request(struct drm_i915_gem_request *req)
1324 {
1325         struct drm_device *dev;
1326         struct drm_i915_private *dev_priv;
1327         bool interruptible;
1328         unsigned reset_counter;
1329         int ret;
1330
1331         BUG_ON(req == NULL);
1332
1333         dev = req->ring->dev;
1334         dev_priv = dev->dev_private;
1335         interruptible = dev_priv->mm.interruptible;
1336
1337         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1338
1339         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1340         if (ret)
1341                 return ret;
1342
1343         ret = i915_gem_check_olr(req);
1344         if (ret)
1345                 return ret;
1346
1347         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1348         i915_gem_request_reference(req);
1349         ret = __i915_wait_request(req, reset_counter,
1350                                   interruptible, NULL, NULL);
1351         i915_gem_request_unreference(req);
1352         return ret;
1353 }
1354
1355 static int
1356 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1357 {
1358         if (!obj->active)
1359                 return 0;
1360
1361         /* Manually manage the write flush as we may have not yet
1362          * retired the buffer.
1363          *
1364          * Note that the last_write_req is always the earlier of
1365          * the two (read/write) requests, so if we haved successfully waited,
1366          * we know we have passed the last write.
1367          */
1368         i915_gem_request_assign(&obj->last_write_req, NULL);
1369
1370         return 0;
1371 }
1372
1373 /**
1374  * Ensures that all rendering to the object has completed and the object is
1375  * safe to unbind from the GTT or access from the CPU.
1376  */
1377 static __must_check int
1378 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1379                                bool readonly)
1380 {
1381         struct drm_i915_gem_request *req;
1382         int ret;
1383
1384         req = readonly ? obj->last_write_req : obj->last_read_req;
1385         if (!req)
1386                 return 0;
1387
1388         ret = i915_wait_request(req);
1389         if (ret)
1390                 return ret;
1391
1392         return i915_gem_object_wait_rendering__tail(obj);
1393 }
1394
1395 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1396  * as the object state may change during this call.
1397  */
1398 static __must_check int
1399 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1400                                             struct drm_i915_file_private *file_priv,
1401                                             bool readonly)
1402 {
1403         struct drm_i915_gem_request *req;
1404         struct drm_device *dev = obj->base.dev;
1405         struct drm_i915_private *dev_priv = dev->dev_private;
1406         unsigned reset_counter;
1407         int ret;
1408
1409         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1410         BUG_ON(!dev_priv->mm.interruptible);
1411
1412         req = readonly ? obj->last_write_req : obj->last_read_req;
1413         if (!req)
1414                 return 0;
1415
1416         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1417         if (ret)
1418                 return ret;
1419
1420         ret = i915_gem_check_olr(req);
1421         if (ret)
1422                 return ret;
1423
1424         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1425         i915_gem_request_reference(req);
1426         mutex_unlock(&dev->struct_mutex);
1427         ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1428         mutex_lock(&dev->struct_mutex);
1429         i915_gem_request_unreference(req);
1430         if (ret)
1431                 return ret;
1432
1433         return i915_gem_object_wait_rendering__tail(obj);
1434 }
1435
1436 /**
1437  * Called when user space prepares to use an object with the CPU, either
1438  * through the mmap ioctl's mapping or a GTT mapping.
1439  */
1440 int
1441 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1442                           struct drm_file *file)
1443 {
1444         struct drm_i915_gem_set_domain *args = data;
1445         struct drm_i915_gem_object *obj;
1446         uint32_t read_domains = args->read_domains;
1447         uint32_t write_domain = args->write_domain;
1448         int ret;
1449
1450         /* Only handle setting domains to types used by the CPU. */
1451         if (write_domain & I915_GEM_GPU_DOMAINS)
1452                 return -EINVAL;
1453
1454         if (read_domains & I915_GEM_GPU_DOMAINS)
1455                 return -EINVAL;
1456
1457         /* Having something in the write domain implies it's in the read
1458          * domain, and only that read domain.  Enforce that in the request.
1459          */
1460         if (write_domain != 0 && read_domains != write_domain)
1461                 return -EINVAL;
1462
1463         ret = i915_mutex_lock_interruptible(dev);
1464         if (ret)
1465                 return ret;
1466
1467         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1468         if (&obj->base == NULL) {
1469                 ret = -ENOENT;
1470                 goto unlock;
1471         }
1472
1473         /* Try to flush the object off the GPU without holding the lock.
1474          * We will repeat the flush holding the lock in the normal manner
1475          * to catch cases where we are gazumped.
1476          */
1477         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1478                                                           file->driver_priv,
1479                                                           !write_domain);
1480         if (ret)
1481                 goto unref;
1482
1483         if (read_domains & I915_GEM_DOMAIN_GTT)
1484                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1485         else
1486                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1487
1488 unref:
1489         drm_gem_object_unreference(&obj->base);
1490 unlock:
1491         mutex_unlock(&dev->struct_mutex);
1492         return ret;
1493 }
1494
1495 /**
1496  * Called when user space has done writes to this buffer
1497  */
1498 int
1499 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1500                          struct drm_file *file)
1501 {
1502         struct drm_i915_gem_sw_finish *args = data;
1503         struct drm_i915_gem_object *obj;
1504         int ret = 0;
1505
1506         ret = i915_mutex_lock_interruptible(dev);
1507         if (ret)
1508                 return ret;
1509
1510         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1511         if (&obj->base == NULL) {
1512                 ret = -ENOENT;
1513                 goto unlock;
1514         }
1515
1516         /* Pinned buffers may be scanout, so flush the cache */
1517         if (obj->pin_display)
1518                 i915_gem_object_flush_cpu_write_domain(obj);
1519
1520         drm_gem_object_unreference(&obj->base);
1521 unlock:
1522         mutex_unlock(&dev->struct_mutex);
1523         return ret;
1524 }
1525
1526 /**
1527  * Maps the contents of an object, returning the address it is mapped
1528  * into.
1529  *
1530  * While the mapping holds a reference on the contents of the object, it doesn't
1531  * imply a ref on the object itself.
1532  *
1533  * IMPORTANT:
1534  *
1535  * DRM driver writers who look a this function as an example for how to do GEM
1536  * mmap support, please don't implement mmap support like here. The modern way
1537  * to implement DRM mmap support is with an mmap offset ioctl (like
1538  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539  * That way debug tooling like valgrind will understand what's going on, hiding
1540  * the mmap call in a driver private ioctl will break that. The i915 driver only
1541  * does cpu mmaps this way because we didn't know better.
1542  */
1543 int
1544 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1545                     struct drm_file *file)
1546 {
1547         struct drm_i915_gem_mmap *args = data;
1548         struct drm_gem_object *obj;
1549         unsigned long addr;
1550
1551         if (args->flags & ~(I915_MMAP_WC))
1552                 return -EINVAL;
1553
1554         if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1555                 return -ENODEV;
1556
1557         obj = drm_gem_object_lookup(dev, file, args->handle);
1558         if (obj == NULL)
1559                 return -ENOENT;
1560
1561         /* prime objects have no backing filp to GEM mmap
1562          * pages from.
1563          */
1564         if (!obj->filp) {
1565                 drm_gem_object_unreference_unlocked(obj);
1566                 return -EINVAL;
1567         }
1568
1569         addr = vm_mmap(obj->filp, 0, args->size,
1570                        PROT_READ | PROT_WRITE, MAP_SHARED,
1571                        args->offset);
1572         if (args->flags & I915_MMAP_WC) {
1573                 struct mm_struct *mm = current->mm;
1574                 struct vm_area_struct *vma;
1575
1576                 down_write(&mm->mmap_sem);
1577                 vma = find_vma(mm, addr);
1578                 if (vma)
1579                         vma->vm_page_prot =
1580                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1581                 else
1582                         addr = -ENOMEM;
1583                 up_write(&mm->mmap_sem);
1584         }
1585         drm_gem_object_unreference_unlocked(obj);
1586         if (IS_ERR((void *)addr))
1587                 return addr;
1588
1589         args->addr_ptr = (uint64_t) addr;
1590
1591         return 0;
1592 }
1593
1594 /**
1595  * i915_gem_fault - fault a page into the GTT
1596  * vma: VMA in question
1597  * vmf: fault info
1598  *
1599  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1600  * from userspace.  The fault handler takes care of binding the object to
1601  * the GTT (if needed), allocating and programming a fence register (again,
1602  * only if needed based on whether the old reg is still valid or the object
1603  * is tiled) and inserting a new PTE into the faulting process.
1604  *
1605  * Note that the faulting process may involve evicting existing objects
1606  * from the GTT and/or fence registers to make room.  So performance may
1607  * suffer if the GTT working set is large or there are few fence registers
1608  * left.
1609  */
1610 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1611 {
1612         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1613         struct drm_device *dev = obj->base.dev;
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615         pgoff_t page_offset;
1616         unsigned long pfn;
1617         int ret = 0;
1618         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1619
1620         intel_runtime_pm_get(dev_priv);
1621
1622         /* We don't use vmf->pgoff since that has the fake offset */
1623         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1624                 PAGE_SHIFT;
1625
1626         ret = i915_mutex_lock_interruptible(dev);
1627         if (ret)
1628                 goto out;
1629
1630         trace_i915_gem_object_fault(obj, page_offset, true, write);
1631
1632         /* Try to flush the object off the GPU first without holding the lock.
1633          * Upon reacquiring the lock, we will perform our sanity checks and then
1634          * repeat the flush holding the lock in the normal manner to catch cases
1635          * where we are gazumped.
1636          */
1637         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1638         if (ret)
1639                 goto unlock;
1640
1641         /* Access to snoopable pages through the GTT is incoherent. */
1642         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1643                 ret = -EFAULT;
1644                 goto unlock;
1645         }
1646
1647         /* Now bind it into the GTT if needed */
1648         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1649         if (ret)
1650                 goto unlock;
1651
1652         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1653         if (ret)
1654                 goto unpin;
1655
1656         ret = i915_gem_object_get_fence(obj);
1657         if (ret)
1658                 goto unpin;
1659
1660         /* Finally, remap it using the new GTT offset */
1661         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1662         pfn >>= PAGE_SHIFT;
1663
1664         if (!obj->fault_mappable) {
1665                 unsigned long size = min_t(unsigned long,
1666                                            vma->vm_end - vma->vm_start,
1667                                            obj->base.size);
1668                 int i;
1669
1670                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1671                         ret = vm_insert_pfn(vma,
1672                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1673                                             pfn + i);
1674                         if (ret)
1675                                 break;
1676                 }
1677
1678                 obj->fault_mappable = true;
1679         } else
1680                 ret = vm_insert_pfn(vma,
1681                                     (unsigned long)vmf->virtual_address,
1682                                     pfn + page_offset);
1683 unpin:
1684         i915_gem_object_ggtt_unpin(obj);
1685 unlock:
1686         mutex_unlock(&dev->struct_mutex);
1687 out:
1688         switch (ret) {
1689         case -EIO:
1690                 /*
1691                  * We eat errors when the gpu is terminally wedged to avoid
1692                  * userspace unduly crashing (gl has no provisions for mmaps to
1693                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1694                  * and so needs to be reported.
1695                  */
1696                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1697                         ret = VM_FAULT_SIGBUS;
1698                         break;
1699                 }
1700         case -EAGAIN:
1701                 /*
1702                  * EAGAIN means the gpu is hung and we'll wait for the error
1703                  * handler to reset everything when re-faulting in
1704                  * i915_mutex_lock_interruptible.
1705                  */
1706         case 0:
1707         case -ERESTARTSYS:
1708         case -EINTR:
1709         case -EBUSY:
1710                 /*
1711                  * EBUSY is ok: this just means that another thread
1712                  * already did the job.
1713                  */
1714                 ret = VM_FAULT_NOPAGE;
1715                 break;
1716         case -ENOMEM:
1717                 ret = VM_FAULT_OOM;
1718                 break;
1719         case -ENOSPC:
1720         case -EFAULT:
1721                 ret = VM_FAULT_SIGBUS;
1722                 break;
1723         default:
1724                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1725                 ret = VM_FAULT_SIGBUS;
1726                 break;
1727         }
1728
1729         intel_runtime_pm_put(dev_priv);
1730         return ret;
1731 }
1732
1733 /**
1734  * i915_gem_release_mmap - remove physical page mappings
1735  * @obj: obj in question
1736  *
1737  * Preserve the reservation of the mmapping with the DRM core code, but
1738  * relinquish ownership of the pages back to the system.
1739  *
1740  * It is vital that we remove the page mapping if we have mapped a tiled
1741  * object through the GTT and then lose the fence register due to
1742  * resource pressure. Similarly if the object has been moved out of the
1743  * aperture, than pages mapped into userspace must be revoked. Removing the
1744  * mapping will then trigger a page fault on the next user access, allowing
1745  * fixup by i915_gem_fault().
1746  */
1747 void
1748 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1749 {
1750         if (!obj->fault_mappable)
1751                 return;
1752
1753         drm_vma_node_unmap(&obj->base.vma_node,
1754                            obj->base.dev->anon_inode->i_mapping);
1755         obj->fault_mappable = false;
1756 }
1757
1758 void
1759 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1760 {
1761         struct drm_i915_gem_object *obj;
1762
1763         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1764                 i915_gem_release_mmap(obj);
1765 }
1766
1767 uint32_t
1768 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1769 {
1770         uint32_t gtt_size;
1771
1772         if (INTEL_INFO(dev)->gen >= 4 ||
1773             tiling_mode == I915_TILING_NONE)
1774                 return size;
1775
1776         /* Previous chips need a power-of-two fence region when tiling */
1777         if (INTEL_INFO(dev)->gen == 3)
1778                 gtt_size = 1024*1024;
1779         else
1780                 gtt_size = 512*1024;
1781
1782         while (gtt_size < size)
1783                 gtt_size <<= 1;
1784
1785         return gtt_size;
1786 }
1787
1788 /**
1789  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1790  * @obj: object to check
1791  *
1792  * Return the required GTT alignment for an object, taking into account
1793  * potential fence register mapping.
1794  */
1795 uint32_t
1796 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1797                            int tiling_mode, bool fenced)
1798 {
1799         /*
1800          * Minimum alignment is 4k (GTT page size), but might be greater
1801          * if a fence register is needed for the object.
1802          */
1803         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1804             tiling_mode == I915_TILING_NONE)
1805                 return 4096;
1806
1807         /*
1808          * Previous chips need to be aligned to the size of the smallest
1809          * fence register that can contain the object.
1810          */
1811         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1812 }
1813
1814 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1815 {
1816         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1817         int ret;
1818
1819         if (drm_vma_node_has_offset(&obj->base.vma_node))
1820                 return 0;
1821
1822         dev_priv->mm.shrinker_no_lock_stealing = true;
1823
1824         ret = drm_gem_create_mmap_offset(&obj->base);
1825         if (ret != -ENOSPC)
1826                 goto out;
1827
1828         /* Badly fragmented mmap space? The only way we can recover
1829          * space is by destroying unwanted objects. We can't randomly release
1830          * mmap_offsets as userspace expects them to be persistent for the
1831          * lifetime of the objects. The closest we can is to release the
1832          * offsets on purgeable objects by truncating it and marking it purged,
1833          * which prevents userspace from ever using that object again.
1834          */
1835         i915_gem_shrink(dev_priv,
1836                         obj->base.size >> PAGE_SHIFT,
1837                         I915_SHRINK_BOUND |
1838                         I915_SHRINK_UNBOUND |
1839                         I915_SHRINK_PURGEABLE);
1840         ret = drm_gem_create_mmap_offset(&obj->base);
1841         if (ret != -ENOSPC)
1842                 goto out;
1843
1844         i915_gem_shrink_all(dev_priv);
1845         ret = drm_gem_create_mmap_offset(&obj->base);
1846 out:
1847         dev_priv->mm.shrinker_no_lock_stealing = false;
1848
1849         return ret;
1850 }
1851
1852 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1853 {
1854         drm_gem_free_mmap_offset(&obj->base);
1855 }
1856
1857 int
1858 i915_gem_mmap_gtt(struct drm_file *file,
1859                   struct drm_device *dev,
1860                   uint32_t handle,
1861                   uint64_t *offset)
1862 {
1863         struct drm_i915_private *dev_priv = dev->dev_private;
1864         struct drm_i915_gem_object *obj;
1865         int ret;
1866
1867         ret = i915_mutex_lock_interruptible(dev);
1868         if (ret)
1869                 return ret;
1870
1871         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1872         if (&obj->base == NULL) {
1873                 ret = -ENOENT;
1874                 goto unlock;
1875         }
1876
1877         if (obj->base.size > dev_priv->gtt.mappable_end) {
1878                 ret = -E2BIG;
1879                 goto out;
1880         }
1881
1882         if (obj->madv != I915_MADV_WILLNEED) {
1883                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1884                 ret = -EFAULT;
1885                 goto out;
1886         }
1887
1888         ret = i915_gem_object_create_mmap_offset(obj);
1889         if (ret)
1890                 goto out;
1891
1892         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1893
1894 out:
1895         drm_gem_object_unreference(&obj->base);
1896 unlock:
1897         mutex_unlock(&dev->struct_mutex);
1898         return ret;
1899 }
1900
1901 /**
1902  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1903  * @dev: DRM device
1904  * @data: GTT mapping ioctl data
1905  * @file: GEM object info
1906  *
1907  * Simply returns the fake offset to userspace so it can mmap it.
1908  * The mmap call will end up in drm_gem_mmap(), which will set things
1909  * up so we can get faults in the handler above.
1910  *
1911  * The fault handler will take care of binding the object into the GTT
1912  * (since it may have been evicted to make room for something), allocating
1913  * a fence register, and mapping the appropriate aperture address into
1914  * userspace.
1915  */
1916 int
1917 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1918                         struct drm_file *file)
1919 {
1920         struct drm_i915_gem_mmap_gtt *args = data;
1921
1922         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1923 }
1924
1925 static inline int
1926 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1927 {
1928         return obj->madv == I915_MADV_DONTNEED;
1929 }
1930
1931 /* Immediately discard the backing storage */
1932 static void
1933 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1934 {
1935         i915_gem_object_free_mmap_offset(obj);
1936
1937         if (obj->base.filp == NULL)
1938                 return;
1939
1940         /* Our goal here is to return as much of the memory as
1941          * is possible back to the system as we are called from OOM.
1942          * To do this we must instruct the shmfs to drop all of its
1943          * backing pages, *now*.
1944          */
1945         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1946         obj->madv = __I915_MADV_PURGED;
1947 }
1948
1949 /* Try to discard unwanted pages */
1950 static void
1951 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1952 {
1953         struct address_space *mapping;
1954
1955         switch (obj->madv) {
1956         case I915_MADV_DONTNEED:
1957                 i915_gem_object_truncate(obj);
1958         case __I915_MADV_PURGED:
1959                 return;
1960         }
1961
1962         if (obj->base.filp == NULL)
1963                 return;
1964
1965         mapping = file_inode(obj->base.filp)->i_mapping,
1966         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1967 }
1968
1969 static void
1970 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1971 {
1972         struct sg_page_iter sg_iter;
1973         int ret;
1974
1975         BUG_ON(obj->madv == __I915_MADV_PURGED);
1976
1977         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1978         if (ret) {
1979                 /* In the event of a disaster, abandon all caches and
1980                  * hope for the best.
1981                  */
1982                 WARN_ON(ret != -EIO);
1983                 i915_gem_clflush_object(obj, true);
1984                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1985         }
1986
1987         if (i915_gem_object_needs_bit17_swizzle(obj))
1988                 i915_gem_object_save_bit_17_swizzle(obj);
1989
1990         if (obj->madv == I915_MADV_DONTNEED)
1991                 obj->dirty = 0;
1992
1993         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1994                 struct page *page = sg_page_iter_page(&sg_iter);
1995
1996                 if (obj->dirty)
1997                         set_page_dirty(page);
1998
1999                 if (obj->madv == I915_MADV_WILLNEED)
2000                         mark_page_accessed(page);
2001
2002                 page_cache_release(page);
2003         }
2004         obj->dirty = 0;
2005
2006         sg_free_table(obj->pages);
2007         kfree(obj->pages);
2008 }
2009
2010 int
2011 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2012 {
2013         const struct drm_i915_gem_object_ops *ops = obj->ops;
2014
2015         if (obj->pages == NULL)
2016                 return 0;
2017
2018         if (obj->pages_pin_count)
2019                 return -EBUSY;
2020
2021         BUG_ON(i915_gem_obj_bound_any(obj));
2022
2023         /* ->put_pages might need to allocate memory for the bit17 swizzle
2024          * array, hence protect them from being reaped by removing them from gtt
2025          * lists early. */
2026         list_del(&obj->global_list);
2027
2028         ops->put_pages(obj);
2029         obj->pages = NULL;
2030
2031         i915_gem_object_invalidate(obj);
2032
2033         return 0;
2034 }
2035
2036 unsigned long
2037 i915_gem_shrink(struct drm_i915_private *dev_priv,
2038                 long target, unsigned flags)
2039 {
2040         const struct {
2041                 struct list_head *list;
2042                 unsigned int bit;
2043         } phases[] = {
2044                 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2045                 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2046                 { NULL, 0 },
2047         }, *phase;
2048         unsigned long count = 0;
2049
2050         /*
2051          * As we may completely rewrite the (un)bound list whilst unbinding
2052          * (due to retiring requests) we have to strictly process only
2053          * one element of the list at the time, and recheck the list
2054          * on every iteration.
2055          *
2056          * In particular, we must hold a reference whilst removing the
2057          * object as we may end up waiting for and/or retiring the objects.
2058          * This might release the final reference (held by the active list)
2059          * and result in the object being freed from under us. This is
2060          * similar to the precautions the eviction code must take whilst
2061          * removing objects.
2062          *
2063          * Also note that although these lists do not hold a reference to
2064          * the object we can safely grab one here: The final object
2065          * unreferencing and the bound_list are both protected by the
2066          * dev->struct_mutex and so we won't ever be able to observe an
2067          * object on the bound_list with a reference count equals 0.
2068          */
2069         for (phase = phases; phase->list; phase++) {
2070                 struct list_head still_in_list;
2071
2072                 if ((flags & phase->bit) == 0)
2073                         continue;
2074
2075                 INIT_LIST_HEAD(&still_in_list);
2076                 while (count < target && !list_empty(phase->list)) {
2077                         struct drm_i915_gem_object *obj;
2078                         struct i915_vma *vma, *v;
2079
2080                         obj = list_first_entry(phase->list,
2081                                                typeof(*obj), global_list);
2082                         list_move_tail(&obj->global_list, &still_in_list);
2083
2084                         if (flags & I915_SHRINK_PURGEABLE &&
2085                             !i915_gem_object_is_purgeable(obj))
2086                                 continue;
2087
2088                         drm_gem_object_reference(&obj->base);
2089
2090                         /* For the unbound phase, this should be a no-op! */
2091                         list_for_each_entry_safe(vma, v,
2092                                                  &obj->vma_list, vma_link)
2093                                 if (i915_vma_unbind(vma))
2094                                         break;
2095
2096                         if (i915_gem_object_put_pages(obj) == 0)
2097                                 count += obj->base.size >> PAGE_SHIFT;
2098
2099                         drm_gem_object_unreference(&obj->base);
2100                 }
2101                 list_splice(&still_in_list, phase->list);
2102         }
2103
2104         return count;
2105 }
2106
2107 static unsigned long
2108 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2109 {
2110         i915_gem_evict_everything(dev_priv->dev);
2111         return i915_gem_shrink(dev_priv, LONG_MAX,
2112                                I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2113 }
2114
2115 static int
2116 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2117 {
2118         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2119         int page_count, i;
2120         struct address_space *mapping;
2121         struct sg_table *st;
2122         struct scatterlist *sg;
2123         struct sg_page_iter sg_iter;
2124         struct page *page;
2125         unsigned long last_pfn = 0;     /* suppress gcc warning */
2126         gfp_t gfp;
2127
2128         /* Assert that the object is not currently in any GPU domain. As it
2129          * wasn't in the GTT, there shouldn't be any way it could have been in
2130          * a GPU cache
2131          */
2132         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2133         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2134
2135         st = kmalloc(sizeof(*st), GFP_KERNEL);
2136         if (st == NULL)
2137                 return -ENOMEM;
2138
2139         page_count = obj->base.size / PAGE_SIZE;
2140         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2141                 kfree(st);
2142                 return -ENOMEM;
2143         }
2144
2145         /* Get the list of pages out of our struct file.  They'll be pinned
2146          * at this point until we release them.
2147          *
2148          * Fail silently without starting the shrinker
2149          */
2150         mapping = file_inode(obj->base.filp)->i_mapping;
2151         gfp = mapping_gfp_mask(mapping);
2152         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2153         gfp &= ~(__GFP_IO | __GFP_WAIT);
2154         sg = st->sgl;
2155         st->nents = 0;
2156         for (i = 0; i < page_count; i++) {
2157                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2158                 if (IS_ERR(page)) {
2159                         i915_gem_shrink(dev_priv,
2160                                         page_count,
2161                                         I915_SHRINK_BOUND |
2162                                         I915_SHRINK_UNBOUND |
2163                                         I915_SHRINK_PURGEABLE);
2164                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2165                 }
2166                 if (IS_ERR(page)) {
2167                         /* We've tried hard to allocate the memory by reaping
2168                          * our own buffer, now let the real VM do its job and
2169                          * go down in flames if truly OOM.
2170                          */
2171                         i915_gem_shrink_all(dev_priv);
2172                         page = shmem_read_mapping_page(mapping, i);
2173                         if (IS_ERR(page))
2174                                 goto err_pages;
2175                 }
2176 #ifdef CONFIG_SWIOTLB
2177                 if (swiotlb_nr_tbl()) {
2178                         st->nents++;
2179                         sg_set_page(sg, page, PAGE_SIZE, 0);
2180                         sg = sg_next(sg);
2181                         continue;
2182                 }
2183 #endif
2184                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2185                         if (i)
2186                                 sg = sg_next(sg);
2187                         st->nents++;
2188                         sg_set_page(sg, page, PAGE_SIZE, 0);
2189                 } else {
2190                         sg->length += PAGE_SIZE;
2191                 }
2192                 last_pfn = page_to_pfn(page);
2193
2194                 /* Check that the i965g/gm workaround works. */
2195                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2196         }
2197 #ifdef CONFIG_SWIOTLB
2198         if (!swiotlb_nr_tbl())
2199 #endif
2200                 sg_mark_end(sg);
2201         obj->pages = st;
2202
2203         if (i915_gem_object_needs_bit17_swizzle(obj))
2204                 i915_gem_object_do_bit_17_swizzle(obj);
2205
2206         if (obj->tiling_mode != I915_TILING_NONE &&
2207             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2208                 i915_gem_object_pin_pages(obj);
2209
2210         return 0;
2211
2212 err_pages:
2213         sg_mark_end(sg);
2214         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2215                 page_cache_release(sg_page_iter_page(&sg_iter));
2216         sg_free_table(st);
2217         kfree(st);
2218
2219         /* shmemfs first checks if there is enough memory to allocate the page
2220          * and reports ENOSPC should there be insufficient, along with the usual
2221          * ENOMEM for a genuine allocation failure.
2222          *
2223          * We use ENOSPC in our driver to mean that we have run out of aperture
2224          * space and so want to translate the error from shmemfs back to our
2225          * usual understanding of ENOMEM.
2226          */
2227         if (PTR_ERR(page) == -ENOSPC)
2228                 return -ENOMEM;
2229         else
2230                 return PTR_ERR(page);
2231 }
2232
2233 /* Ensure that the associated pages are gathered from the backing storage
2234  * and pinned into our object. i915_gem_object_get_pages() may be called
2235  * multiple times before they are released by a single call to
2236  * i915_gem_object_put_pages() - once the pages are no longer referenced
2237  * either as a result of memory pressure (reaping pages under the shrinker)
2238  * or as the object is itself released.
2239  */
2240 int
2241 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2242 {
2243         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2244         const struct drm_i915_gem_object_ops *ops = obj->ops;
2245         int ret;
2246
2247         if (obj->pages)
2248                 return 0;
2249
2250         if (obj->madv != I915_MADV_WILLNEED) {
2251                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2252                 return -EFAULT;
2253         }
2254
2255         BUG_ON(obj->pages_pin_count);
2256
2257         ret = ops->get_pages(obj);
2258         if (ret)
2259                 return ret;
2260
2261         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2262         return 0;
2263 }
2264
2265 static void
2266 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2267                                struct intel_engine_cs *ring)
2268 {
2269         struct drm_i915_gem_request *req;
2270         struct intel_engine_cs *old_ring;
2271
2272         BUG_ON(ring == NULL);
2273
2274         req = intel_ring_get_request(ring);
2275         old_ring = i915_gem_request_get_ring(obj->last_read_req);
2276
2277         if (old_ring != ring && obj->last_write_req) {
2278                 /* Keep the request relative to the current ring */
2279                 i915_gem_request_assign(&obj->last_write_req, req);
2280         }
2281
2282         /* Add a reference if we're newly entering the active list. */
2283         if (!obj->active) {
2284                 drm_gem_object_reference(&obj->base);
2285                 obj->active = 1;
2286         }
2287
2288         list_move_tail(&obj->ring_list, &ring->active_list);
2289
2290         i915_gem_request_assign(&obj->last_read_req, req);
2291 }
2292
2293 void i915_vma_move_to_active(struct i915_vma *vma,
2294                              struct intel_engine_cs *ring)
2295 {
2296         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2297         return i915_gem_object_move_to_active(vma->obj, ring);
2298 }
2299
2300 static void
2301 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2302 {
2303         struct i915_vma *vma;
2304
2305         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2306         BUG_ON(!obj->active);
2307
2308         list_for_each_entry(vma, &obj->vma_list, vma_link) {
2309                 if (!list_empty(&vma->mm_list))
2310                         list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2311         }
2312
2313         intel_fb_obj_flush(obj, true);
2314
2315         list_del_init(&obj->ring_list);
2316
2317         i915_gem_request_assign(&obj->last_read_req, NULL);
2318         i915_gem_request_assign(&obj->last_write_req, NULL);
2319         obj->base.write_domain = 0;
2320
2321         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2322
2323         obj->active = 0;
2324         drm_gem_object_unreference(&obj->base);
2325
2326         WARN_ON(i915_verify_lists(dev));
2327 }
2328
2329 static void
2330 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2331 {
2332         if (obj->last_read_req == NULL)
2333                 return;
2334
2335         if (i915_gem_request_completed(obj->last_read_req, true))
2336                 i915_gem_object_move_to_inactive(obj);
2337 }
2338
2339 static int
2340 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2341 {
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         struct intel_engine_cs *ring;
2344         int ret, i, j;
2345
2346         /* Carefully retire all requests without writing to the rings */
2347         for_each_ring(ring, dev_priv, i) {
2348                 ret = intel_ring_idle(ring);
2349                 if (ret)
2350                         return ret;
2351         }
2352         i915_gem_retire_requests(dev);
2353
2354         /* Finally reset hw state */
2355         for_each_ring(ring, dev_priv, i) {
2356                 intel_ring_init_seqno(ring, seqno);
2357
2358                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2359                         ring->semaphore.sync_seqno[j] = 0;
2360         }
2361
2362         return 0;
2363 }
2364
2365 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2366 {
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         int ret;
2369
2370         if (seqno == 0)
2371                 return -EINVAL;
2372
2373         /* HWS page needs to be set less than what we
2374          * will inject to ring
2375          */
2376         ret = i915_gem_init_seqno(dev, seqno - 1);
2377         if (ret)
2378                 return ret;
2379
2380         /* Carefully set the last_seqno value so that wrap
2381          * detection still works
2382          */
2383         dev_priv->next_seqno = seqno;
2384         dev_priv->last_seqno = seqno - 1;
2385         if (dev_priv->last_seqno == 0)
2386                 dev_priv->last_seqno--;
2387
2388         return 0;
2389 }
2390
2391 int
2392 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2393 {
2394         struct drm_i915_private *dev_priv = dev->dev_private;
2395
2396         /* reserve 0 for non-seqno */
2397         if (dev_priv->next_seqno == 0) {
2398                 int ret = i915_gem_init_seqno(dev, 0);
2399                 if (ret)
2400                         return ret;
2401
2402                 dev_priv->next_seqno = 1;
2403         }
2404
2405         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2406         return 0;
2407 }
2408
2409 int __i915_add_request(struct intel_engine_cs *ring,
2410                        struct drm_file *file,
2411                        struct drm_i915_gem_object *obj)
2412 {
2413         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2414         struct drm_i915_gem_request *request;
2415         struct intel_ringbuffer *ringbuf;
2416         u32 request_start;
2417         int ret;
2418
2419         request = ring->outstanding_lazy_request;
2420         if (WARN_ON(request == NULL))
2421                 return -ENOMEM;
2422
2423         if (i915.enable_execlists) {
2424                 ringbuf = request->ctx->engine[ring->id].ringbuf;
2425         } else
2426                 ringbuf = ring->buffer;
2427
2428         request_start = intel_ring_get_tail(ringbuf);
2429         /*
2430          * Emit any outstanding flushes - execbuf can fail to emit the flush
2431          * after having emitted the batchbuffer command. Hence we need to fix
2432          * things up similar to emitting the lazy request. The difference here
2433          * is that the flush _must_ happen before the next request, no matter
2434          * what.
2435          */
2436         if (i915.enable_execlists) {
2437                 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2438                 if (ret)
2439                         return ret;
2440         } else {
2441                 ret = intel_ring_flush_all_caches(ring);
2442                 if (ret)
2443                         return ret;
2444         }
2445
2446         /* Record the position of the start of the request so that
2447          * should we detect the updated seqno part-way through the
2448          * GPU processing the request, we never over-estimate the
2449          * position of the head.
2450          */
2451         request->postfix = intel_ring_get_tail(ringbuf);
2452
2453         if (i915.enable_execlists) {
2454                 ret = ring->emit_request(ringbuf, request);
2455                 if (ret)
2456                         return ret;
2457         } else {
2458                 ret = ring->add_request(ring);
2459                 if (ret)
2460                         return ret;
2461         }
2462
2463         request->head = request_start;
2464         request->tail = intel_ring_get_tail(ringbuf);
2465
2466         /* Whilst this request exists, batch_obj will be on the
2467          * active_list, and so will hold the active reference. Only when this
2468          * request is retired will the the batch_obj be moved onto the
2469          * inactive_list and lose its active reference. Hence we do not need
2470          * to explicitly hold another reference here.
2471          */
2472         request->batch_obj = obj;
2473
2474         if (!i915.enable_execlists) {
2475                 /* Hold a reference to the current context so that we can inspect
2476                  * it later in case a hangcheck error event fires.
2477                  */
2478                 request->ctx = ring->last_context;
2479                 if (request->ctx)
2480                         i915_gem_context_reference(request->ctx);
2481         }
2482
2483         request->emitted_jiffies = jiffies;
2484         list_add_tail(&request->list, &ring->request_list);
2485         request->file_priv = NULL;
2486
2487         if (file) {
2488                 struct drm_i915_file_private *file_priv = file->driver_priv;
2489
2490                 spin_lock(&file_priv->mm.lock);
2491                 request->file_priv = file_priv;
2492                 list_add_tail(&request->client_list,
2493                               &file_priv->mm.request_list);
2494                 spin_unlock(&file_priv->mm.lock);
2495         }
2496
2497         trace_i915_gem_request_add(request);
2498         ring->outstanding_lazy_request = NULL;
2499
2500         i915_queue_hangcheck(ring->dev);
2501
2502         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2503         queue_delayed_work(dev_priv->wq,
2504                            &dev_priv->mm.retire_work,
2505                            round_jiffies_up_relative(HZ));
2506         intel_mark_busy(dev_priv->dev);
2507
2508         return 0;
2509 }
2510
2511 static inline void
2512 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2513 {
2514         struct drm_i915_file_private *file_priv = request->file_priv;
2515
2516         if (!file_priv)
2517                 return;
2518
2519         spin_lock(&file_priv->mm.lock);
2520         list_del(&request->client_list);
2521         request->file_priv = NULL;
2522         spin_unlock(&file_priv->mm.lock);
2523 }
2524
2525 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2526                                    const struct intel_context *ctx)
2527 {
2528         unsigned long elapsed;
2529
2530         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2531
2532         if (ctx->hang_stats.banned)
2533                 return true;
2534
2535         if (ctx->hang_stats.ban_period_seconds &&
2536             elapsed <= ctx->hang_stats.ban_period_seconds) {
2537                 if (!i915_gem_context_is_default(ctx)) {
2538                         DRM_DEBUG("context hanging too fast, banning!\n");
2539                         return true;
2540                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2541                         if (i915_stop_ring_allow_warn(dev_priv))
2542                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2543                         return true;
2544                 }
2545         }
2546
2547         return false;
2548 }
2549
2550 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2551                                   struct intel_context *ctx,
2552                                   const bool guilty)
2553 {
2554         struct i915_ctx_hang_stats *hs;
2555
2556         if (WARN_ON(!ctx))
2557                 return;
2558
2559         hs = &ctx->hang_stats;
2560
2561         if (guilty) {
2562                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2563                 hs->batch_active++;
2564                 hs->guilty_ts = get_seconds();
2565         } else {
2566                 hs->batch_pending++;
2567         }
2568 }
2569
2570 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2571 {
2572         list_del(&request->list);
2573         i915_gem_request_remove_from_client(request);
2574
2575         i915_gem_request_unreference(request);
2576 }
2577
2578 void i915_gem_request_free(struct kref *req_ref)
2579 {
2580         struct drm_i915_gem_request *req = container_of(req_ref,
2581                                                  typeof(*req), ref);
2582         struct intel_context *ctx = req->ctx;
2583
2584         if (ctx) {
2585                 if (i915.enable_execlists) {
2586                         struct intel_engine_cs *ring = req->ring;
2587
2588                         if (ctx != ring->default_context)
2589                                 intel_lr_context_unpin(ring, ctx);
2590                 }
2591
2592                 i915_gem_context_unreference(ctx);
2593         }
2594
2595         kfree(req);
2596 }
2597
2598 struct drm_i915_gem_request *
2599 i915_gem_find_active_request(struct intel_engine_cs *ring)
2600 {
2601         struct drm_i915_gem_request *request;
2602
2603         list_for_each_entry(request, &ring->request_list, list) {
2604                 if (i915_gem_request_completed(request, false))
2605                         continue;
2606
2607                 return request;
2608         }
2609
2610         return NULL;
2611 }
2612
2613 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2614                                        struct intel_engine_cs *ring)
2615 {
2616         struct drm_i915_gem_request *request;
2617         bool ring_hung;
2618
2619         request = i915_gem_find_active_request(ring);
2620
2621         if (request == NULL)
2622                 return;
2623
2624         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2625
2626         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2627
2628         list_for_each_entry_continue(request, &ring->request_list, list)
2629                 i915_set_reset_status(dev_priv, request->ctx, false);
2630 }
2631
2632 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2633                                         struct intel_engine_cs *ring)
2634 {
2635         while (!list_empty(&ring->active_list)) {
2636                 struct drm_i915_gem_object *obj;
2637
2638                 obj = list_first_entry(&ring->active_list,
2639                                        struct drm_i915_gem_object,
2640                                        ring_list);
2641
2642                 i915_gem_object_move_to_inactive(obj);
2643         }
2644
2645         /*
2646          * Clear the execlists queue up before freeing the requests, as those
2647          * are the ones that keep the context and ringbuffer backing objects
2648          * pinned in place.
2649          */
2650         while (!list_empty(&ring->execlist_queue)) {
2651                 struct drm_i915_gem_request *submit_req;
2652
2653                 submit_req = list_first_entry(&ring->execlist_queue,
2654                                 struct drm_i915_gem_request,
2655                                 execlist_link);
2656                 list_del(&submit_req->execlist_link);
2657                 intel_runtime_pm_put(dev_priv);
2658
2659                 if (submit_req->ctx != ring->default_context)
2660                         intel_lr_context_unpin(ring, submit_req->ctx);
2661
2662                 i915_gem_request_unreference(submit_req);
2663         }
2664
2665         /*
2666          * We must free the requests after all the corresponding objects have
2667          * been moved off active lists. Which is the same order as the normal
2668          * retire_requests function does. This is important if object hold
2669          * implicit references on things like e.g. ppgtt address spaces through
2670          * the request.
2671          */
2672         while (!list_empty(&ring->request_list)) {
2673                 struct drm_i915_gem_request *request;
2674
2675                 request = list_first_entry(&ring->request_list,
2676                                            struct drm_i915_gem_request,
2677                                            list);
2678
2679                 i915_gem_free_request(request);
2680         }
2681
2682         /* This may not have been flushed before the reset, so clean it now */
2683         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2684 }
2685
2686 void i915_gem_restore_fences(struct drm_device *dev)
2687 {
2688         struct drm_i915_private *dev_priv = dev->dev_private;
2689         int i;
2690
2691         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2692                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2693
2694                 /*
2695                  * Commit delayed tiling changes if we have an object still
2696                  * attached to the fence, otherwise just clear the fence.
2697                  */
2698                 if (reg->obj) {
2699                         i915_gem_object_update_fence(reg->obj, reg,
2700                                                      reg->obj->tiling_mode);
2701                 } else {
2702                         i915_gem_write_fence(dev, i, NULL);
2703                 }
2704         }
2705 }
2706
2707 void i915_gem_reset(struct drm_device *dev)
2708 {
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         struct intel_engine_cs *ring;
2711         int i;
2712
2713         /*
2714          * Before we free the objects from the requests, we need to inspect
2715          * them for finding the guilty party. As the requests only borrow
2716          * their reference to the objects, the inspection must be done first.
2717          */
2718         for_each_ring(ring, dev_priv, i)
2719                 i915_gem_reset_ring_status(dev_priv, ring);
2720
2721         for_each_ring(ring, dev_priv, i)
2722                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2723
2724         i915_gem_context_reset(dev);
2725
2726         i915_gem_restore_fences(dev);
2727 }
2728
2729 /**
2730  * This function clears the request list as sequence numbers are passed.
2731  */
2732 void
2733 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2734 {
2735         if (list_empty(&ring->request_list))
2736                 return;
2737
2738         WARN_ON(i915_verify_lists(ring->dev));
2739
2740         /* Retire requests first as we use it above for the early return.
2741          * If we retire requests last, we may use a later seqno and so clear
2742          * the requests lists without clearing the active list, leading to
2743          * confusion.
2744          */
2745         while (!list_empty(&ring->request_list)) {
2746                 struct drm_i915_gem_request *request;
2747                 struct intel_ringbuffer *ringbuf;
2748
2749                 request = list_first_entry(&ring->request_list,
2750                                            struct drm_i915_gem_request,
2751                                            list);
2752
2753                 if (!i915_gem_request_completed(request, true))
2754                         break;
2755
2756                 trace_i915_gem_request_retire(request);
2757
2758                 /* This is one of the few common intersection points
2759                  * between legacy ringbuffer submission and execlists:
2760                  * we need to tell them apart in order to find the correct
2761                  * ringbuffer to which the request belongs to.
2762                  */
2763                 if (i915.enable_execlists) {
2764                         struct intel_context *ctx = request->ctx;
2765                         ringbuf = ctx->engine[ring->id].ringbuf;
2766                 } else
2767                         ringbuf = ring->buffer;
2768
2769                 /* We know the GPU must have read the request to have
2770                  * sent us the seqno + interrupt, so use the position
2771                  * of tail of the request to update the last known position
2772                  * of the GPU head.
2773                  */
2774                 ringbuf->last_retired_head = request->postfix;
2775
2776                 i915_gem_free_request(request);
2777         }
2778
2779         /* Move any buffers on the active list that are no longer referenced
2780          * by the ringbuffer to the flushing/inactive lists as appropriate,
2781          * before we free the context associated with the requests.
2782          */
2783         while (!list_empty(&ring->active_list)) {
2784                 struct drm_i915_gem_object *obj;
2785
2786                 obj = list_first_entry(&ring->active_list,
2787                                       struct drm_i915_gem_object,
2788                                       ring_list);
2789
2790                 if (!i915_gem_request_completed(obj->last_read_req, true))
2791                         break;
2792
2793                 i915_gem_object_move_to_inactive(obj);
2794         }
2795
2796         if (unlikely(ring->trace_irq_req &&
2797                      i915_gem_request_completed(ring->trace_irq_req, true))) {
2798                 ring->irq_put(ring);
2799                 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2800         }
2801
2802         WARN_ON(i915_verify_lists(ring->dev));
2803 }
2804
2805 bool
2806 i915_gem_retire_requests(struct drm_device *dev)
2807 {
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         struct intel_engine_cs *ring;
2810         bool idle = true;
2811         int i;
2812
2813         for_each_ring(ring, dev_priv, i) {
2814                 i915_gem_retire_requests_ring(ring);
2815                 idle &= list_empty(&ring->request_list);
2816                 if (i915.enable_execlists) {
2817                         unsigned long flags;
2818
2819                         spin_lock_irqsave(&ring->execlist_lock, flags);
2820                         idle &= list_empty(&ring->execlist_queue);
2821                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2822
2823                         intel_execlists_retire_requests(ring);
2824                 }
2825         }
2826
2827         if (idle)
2828                 mod_delayed_work(dev_priv->wq,
2829                                    &dev_priv->mm.idle_work,
2830                                    msecs_to_jiffies(100));
2831
2832         return idle;
2833 }
2834
2835 static void
2836 i915_gem_retire_work_handler(struct work_struct *work)
2837 {
2838         struct drm_i915_private *dev_priv =
2839                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2840         struct drm_device *dev = dev_priv->dev;
2841         bool idle;
2842
2843         /* Come back later if the device is busy... */
2844         idle = false;
2845         if (mutex_trylock(&dev->struct_mutex)) {
2846                 idle = i915_gem_retire_requests(dev);
2847                 mutex_unlock(&dev->struct_mutex);
2848         }
2849         if (!idle)
2850                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2851                                    round_jiffies_up_relative(HZ));
2852 }
2853
2854 static void
2855 i915_gem_idle_work_handler(struct work_struct *work)
2856 {
2857         struct drm_i915_private *dev_priv =
2858                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2859
2860         intel_mark_idle(dev_priv->dev);
2861 }
2862
2863 /**
2864  * Ensures that an object will eventually get non-busy by flushing any required
2865  * write domains, emitting any outstanding lazy request and retiring and
2866  * completed requests.
2867  */
2868 static int
2869 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2870 {
2871         struct intel_engine_cs *ring;
2872         int ret;
2873
2874         if (obj->active) {
2875                 ring = i915_gem_request_get_ring(obj->last_read_req);
2876
2877                 ret = i915_gem_check_olr(obj->last_read_req);
2878                 if (ret)
2879                         return ret;
2880
2881                 i915_gem_retire_requests_ring(ring);
2882         }
2883
2884         return 0;
2885 }
2886
2887 /**
2888  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2889  * @DRM_IOCTL_ARGS: standard ioctl arguments
2890  *
2891  * Returns 0 if successful, else an error is returned with the remaining time in
2892  * the timeout parameter.
2893  *  -ETIME: object is still busy after timeout
2894  *  -ERESTARTSYS: signal interrupted the wait
2895  *  -ENONENT: object doesn't exist
2896  * Also possible, but rare:
2897  *  -EAGAIN: GPU wedged
2898  *  -ENOMEM: damn
2899  *  -ENODEV: Internal IRQ fail
2900  *  -E?: The add request failed
2901  *
2902  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2903  * non-zero timeout parameter the wait ioctl will wait for the given number of
2904  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2905  * without holding struct_mutex the object may become re-busied before this
2906  * function completes. A similar but shorter * race condition exists in the busy
2907  * ioctl
2908  */
2909 int
2910 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2911 {
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         struct drm_i915_gem_wait *args = data;
2914         struct drm_i915_gem_object *obj;
2915         struct drm_i915_gem_request *req;
2916         unsigned reset_counter;
2917         int ret = 0;
2918
2919         if (args->flags != 0)
2920                 return -EINVAL;
2921
2922         ret = i915_mutex_lock_interruptible(dev);
2923         if (ret)
2924                 return ret;
2925
2926         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2927         if (&obj->base == NULL) {
2928                 mutex_unlock(&dev->struct_mutex);
2929                 return -ENOENT;
2930         }
2931
2932         /* Need to make sure the object gets inactive eventually. */
2933         ret = i915_gem_object_flush_active(obj);
2934         if (ret)
2935                 goto out;
2936
2937         if (!obj->active || !obj->last_read_req)
2938                 goto out;
2939
2940         req = obj->last_read_req;
2941
2942         /* Do this after OLR check to make sure we make forward progress polling
2943          * on this IOCTL with a timeout == 0 (like busy ioctl)
2944          */
2945         if (args->timeout_ns == 0) {
2946                 ret = -ETIME;
2947                 goto out;
2948         }
2949
2950         drm_gem_object_unreference(&obj->base);
2951         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2952         i915_gem_request_reference(req);
2953         mutex_unlock(&dev->struct_mutex);
2954
2955         ret = __i915_wait_request(req, reset_counter, true,
2956                                   args->timeout_ns > 0 ? &args->timeout_ns : NULL,
2957                                   file->driver_priv);
2958         mutex_lock(&dev->struct_mutex);
2959         i915_gem_request_unreference(req);
2960         mutex_unlock(&dev->struct_mutex);
2961         return ret;
2962
2963 out:
2964         drm_gem_object_unreference(&obj->base);
2965         mutex_unlock(&dev->struct_mutex);
2966         return ret;
2967 }
2968
2969 /**
2970  * i915_gem_object_sync - sync an object to a ring.
2971  *
2972  * @obj: object which may be in use on another ring.
2973  * @to: ring we wish to use the object on. May be NULL.
2974  *
2975  * This code is meant to abstract object synchronization with the GPU.
2976  * Calling with NULL implies synchronizing the object with the CPU
2977  * rather than a particular GPU ring.
2978  *
2979  * Returns 0 if successful, else propagates up the lower layer error.
2980  */
2981 int
2982 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2983                      struct intel_engine_cs *to)
2984 {
2985         struct intel_engine_cs *from;
2986         u32 seqno;
2987         int ret, idx;
2988
2989         from = i915_gem_request_get_ring(obj->last_read_req);
2990
2991         if (from == NULL || to == from)
2992                 return 0;
2993
2994         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2995                 return i915_gem_object_wait_rendering(obj, false);
2996
2997         idx = intel_ring_sync_index(from, to);
2998
2999         seqno = i915_gem_request_get_seqno(obj->last_read_req);
3000         /* Optimization: Avoid semaphore sync when we are sure we already
3001          * waited for an object with higher seqno */
3002         if (seqno <= from->semaphore.sync_seqno[idx])
3003                 return 0;
3004
3005         ret = i915_gem_check_olr(obj->last_read_req);
3006         if (ret)
3007                 return ret;
3008
3009         trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
3010         ret = to->semaphore.sync_to(to, from, seqno);
3011         if (!ret)
3012                 /* We use last_read_req because sync_to()
3013                  * might have just caused seqno wrap under
3014                  * the radar.
3015                  */
3016                 from->semaphore.sync_seqno[idx] =
3017                                 i915_gem_request_get_seqno(obj->last_read_req);
3018
3019         return ret;
3020 }
3021
3022 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3023 {
3024         u32 old_write_domain, old_read_domains;
3025
3026         /* Force a pagefault for domain tracking on next user access */
3027         i915_gem_release_mmap(obj);
3028
3029         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3030                 return;
3031
3032         /* Wait for any direct GTT access to complete */
3033         mb();
3034
3035         old_read_domains = obj->base.read_domains;
3036         old_write_domain = obj->base.write_domain;
3037
3038         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3039         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3040
3041         trace_i915_gem_object_change_domain(obj,
3042                                             old_read_domains,
3043                                             old_write_domain);
3044 }
3045
3046 int i915_vma_unbind(struct i915_vma *vma)
3047 {
3048         struct drm_i915_gem_object *obj = vma->obj;
3049         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3050         int ret;
3051
3052         if (list_empty(&vma->vma_link))
3053                 return 0;
3054
3055         if (!drm_mm_node_allocated(&vma->node)) {
3056                 i915_gem_vma_destroy(vma);
3057                 return 0;
3058         }
3059
3060         if (vma->pin_count)
3061                 return -EBUSY;
3062
3063         BUG_ON(obj->pages == NULL);
3064
3065         ret = i915_gem_object_finish_gpu(obj);
3066         if (ret)
3067                 return ret;
3068         /* Continue on if we fail due to EIO, the GPU is hung so we
3069          * should be safe and we need to cleanup or else we might
3070          * cause memory corruption through use-after-free.
3071          */
3072
3073         if (i915_is_ggtt(vma->vm) &&
3074             vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3075                 i915_gem_object_finish_gtt(obj);
3076
3077                 /* release the fence reg _after_ flushing */
3078                 ret = i915_gem_object_put_fence(obj);
3079                 if (ret)
3080                         return ret;
3081         }
3082
3083         trace_i915_vma_unbind(vma);
3084
3085         vma->unbind_vma(vma);
3086
3087         list_del_init(&vma->mm_list);
3088         if (i915_is_ggtt(vma->vm)) {
3089                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3090                         obj->map_and_fenceable = false;
3091                 } else if (vma->ggtt_view.pages) {
3092                         sg_free_table(vma->ggtt_view.pages);
3093                         kfree(vma->ggtt_view.pages);
3094                         vma->ggtt_view.pages = NULL;
3095                 }
3096         }
3097
3098         drm_mm_remove_node(&vma->node);
3099         i915_gem_vma_destroy(vma);
3100
3101         /* Since the unbound list is global, only move to that list if
3102          * no more VMAs exist. */
3103         if (list_empty(&obj->vma_list)) {
3104                 /* Throw away the active reference before
3105                  * moving to the unbound list. */
3106                 i915_gem_object_retire(obj);
3107
3108                 i915_gem_gtt_finish_object(obj);
3109                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3110         }
3111
3112         /* And finally now the object is completely decoupled from this vma,
3113          * we can drop its hold on the backing storage and allow it to be
3114          * reaped by the shrinker.
3115          */
3116         i915_gem_object_unpin_pages(obj);
3117
3118         return 0;
3119 }
3120
3121 int i915_gpu_idle(struct drm_device *dev)
3122 {
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct intel_engine_cs *ring;
3125         int ret, i;
3126
3127         /* Flush everything onto the inactive list. */
3128         for_each_ring(ring, dev_priv, i) {
3129                 if (!i915.enable_execlists) {
3130                         ret = i915_switch_context(ring, ring->default_context);
3131                         if (ret)
3132                                 return ret;
3133                 }
3134
3135                 ret = intel_ring_idle(ring);
3136                 if (ret)
3137                         return ret;
3138         }
3139
3140         return 0;
3141 }
3142
3143 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3144                                  struct drm_i915_gem_object *obj)
3145 {
3146         struct drm_i915_private *dev_priv = dev->dev_private;
3147         int fence_reg;
3148         int fence_pitch_shift;
3149
3150         if (INTEL_INFO(dev)->gen >= 6) {
3151                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3152                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3153         } else {
3154                 fence_reg = FENCE_REG_965_0;
3155                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3156         }
3157
3158         fence_reg += reg * 8;
3159
3160         /* To w/a incoherency with non-atomic 64-bit register updates,
3161          * we split the 64-bit update into two 32-bit writes. In order
3162          * for a partial fence not to be evaluated between writes, we
3163          * precede the update with write to turn off the fence register,
3164          * and only enable the fence as the last step.
3165          *
3166          * For extra levels of paranoia, we make sure each step lands
3167          * before applying the next step.
3168          */
3169         I915_WRITE(fence_reg, 0);
3170         POSTING_READ(fence_reg);
3171
3172         if (obj) {
3173                 u32 size = i915_gem_obj_ggtt_size(obj);
3174                 uint64_t val;
3175
3176                 /* Adjust fence size to match tiled area */
3177                 if (obj->tiling_mode != I915_TILING_NONE) {
3178                         uint32_t row_size = obj->stride *
3179                                 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3180                         size = (size / row_size) * row_size;
3181                 }
3182
3183                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3184                                  0xfffff000) << 32;
3185                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3186                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3187                 if (obj->tiling_mode == I915_TILING_Y)
3188                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3189                 val |= I965_FENCE_REG_VALID;
3190
3191                 I915_WRITE(fence_reg + 4, val >> 32);
3192                 POSTING_READ(fence_reg + 4);
3193
3194                 I915_WRITE(fence_reg + 0, val);
3195                 POSTING_READ(fence_reg);
3196         } else {
3197                 I915_WRITE(fence_reg + 4, 0);
3198                 POSTING_READ(fence_reg + 4);
3199         }
3200 }
3201
3202 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3203                                  struct drm_i915_gem_object *obj)
3204 {
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         u32 val;
3207
3208         if (obj) {
3209                 u32 size = i915_gem_obj_ggtt_size(obj);
3210                 int pitch_val;
3211                 int tile_width;
3212
3213                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3214                      (size & -size) != size ||
3215                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3216                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3217                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3218
3219                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3220                         tile_width = 128;
3221                 else
3222                         tile_width = 512;
3223
3224                 /* Note: pitch better be a power of two tile widths */
3225                 pitch_val = obj->stride / tile_width;
3226                 pitch_val = ffs(pitch_val) - 1;
3227
3228                 val = i915_gem_obj_ggtt_offset(obj);
3229                 if (obj->tiling_mode == I915_TILING_Y)
3230                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3231                 val |= I915_FENCE_SIZE_BITS(size);
3232                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3233                 val |= I830_FENCE_REG_VALID;
3234         } else
3235                 val = 0;
3236
3237         if (reg < 8)
3238                 reg = FENCE_REG_830_0 + reg * 4;
3239         else
3240                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3241
3242         I915_WRITE(reg, val);
3243         POSTING_READ(reg);
3244 }
3245
3246 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3247                                 struct drm_i915_gem_object *obj)
3248 {
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250         uint32_t val;
3251
3252         if (obj) {
3253                 u32 size = i915_gem_obj_ggtt_size(obj);
3254                 uint32_t pitch_val;
3255
3256                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3257                      (size & -size) != size ||
3258                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3259                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3260                      i915_gem_obj_ggtt_offset(obj), size);
3261
3262                 pitch_val = obj->stride / 128;
3263                 pitch_val = ffs(pitch_val) - 1;
3264
3265                 val = i915_gem_obj_ggtt_offset(obj);
3266                 if (obj->tiling_mode == I915_TILING_Y)
3267                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3268                 val |= I830_FENCE_SIZE_BITS(size);
3269                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3270                 val |= I830_FENCE_REG_VALID;
3271         } else
3272                 val = 0;
3273
3274         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3275         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3276 }
3277
3278 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3279 {
3280         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3281 }
3282
3283 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3284                                  struct drm_i915_gem_object *obj)
3285 {
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287
3288         /* Ensure that all CPU reads are completed before installing a fence
3289          * and all writes before removing the fence.
3290          */
3291         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3292                 mb();
3293
3294         WARN(obj && (!obj->stride || !obj->tiling_mode),
3295              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3296              obj->stride, obj->tiling_mode);
3297
3298         if (IS_GEN2(dev))
3299                 i830_write_fence_reg(dev, reg, obj);
3300         else if (IS_GEN3(dev))
3301                 i915_write_fence_reg(dev, reg, obj);
3302         else if (INTEL_INFO(dev)->gen >= 4)
3303                 i965_write_fence_reg(dev, reg, obj);
3304
3305         /* And similarly be paranoid that no direct access to this region
3306          * is reordered to before the fence is installed.
3307          */
3308         if (i915_gem_object_needs_mb(obj))
3309                 mb();
3310 }
3311
3312 static inline int fence_number(struct drm_i915_private *dev_priv,
3313                                struct drm_i915_fence_reg *fence)
3314 {
3315         return fence - dev_priv->fence_regs;
3316 }
3317
3318 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3319                                          struct drm_i915_fence_reg *fence,
3320                                          bool enable)
3321 {
3322         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3323         int reg = fence_number(dev_priv, fence);
3324
3325         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3326
3327         if (enable) {
3328                 obj->fence_reg = reg;
3329                 fence->obj = obj;
3330                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3331         } else {
3332                 obj->fence_reg = I915_FENCE_REG_NONE;
3333                 fence->obj = NULL;
3334                 list_del_init(&fence->lru_list);
3335         }
3336         obj->fence_dirty = false;
3337 }
3338
3339 static int
3340 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3341 {
3342         if (obj->last_fenced_req) {
3343                 int ret = i915_wait_request(obj->last_fenced_req);
3344                 if (ret)
3345                         return ret;
3346
3347                 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3348         }
3349
3350         return 0;
3351 }
3352
3353 int
3354 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3355 {
3356         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3357         struct drm_i915_fence_reg *fence;
3358         int ret;
3359
3360         ret = i915_gem_object_wait_fence(obj);
3361         if (ret)
3362                 return ret;
3363
3364         if (obj->fence_reg == I915_FENCE_REG_NONE)
3365                 return 0;
3366
3367         fence = &dev_priv->fence_regs[obj->fence_reg];
3368
3369         if (WARN_ON(fence->pin_count))
3370                 return -EBUSY;
3371
3372         i915_gem_object_fence_lost(obj);
3373         i915_gem_object_update_fence(obj, fence, false);
3374
3375         return 0;
3376 }
3377
3378 static struct drm_i915_fence_reg *
3379 i915_find_fence_reg(struct drm_device *dev)
3380 {
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct drm_i915_fence_reg *reg, *avail;
3383         int i;
3384
3385         /* First try to find a free reg */
3386         avail = NULL;
3387         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3388                 reg = &dev_priv->fence_regs[i];
3389                 if (!reg->obj)
3390                         return reg;
3391
3392                 if (!reg->pin_count)
3393                         avail = reg;
3394         }
3395
3396         if (avail == NULL)
3397                 goto deadlock;
3398
3399         /* None available, try to steal one or wait for a user to finish */
3400         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3401                 if (reg->pin_count)
3402                         continue;
3403
3404                 return reg;
3405         }
3406
3407 deadlock:
3408         /* Wait for completion of pending flips which consume fences */
3409         if (intel_has_pending_fb_unpin(dev))
3410                 return ERR_PTR(-EAGAIN);
3411
3412         return ERR_PTR(-EDEADLK);
3413 }
3414
3415 /**
3416  * i915_gem_object_get_fence - set up fencing for an object
3417  * @obj: object to map through a fence reg
3418  *
3419  * When mapping objects through the GTT, userspace wants to be able to write
3420  * to them without having to worry about swizzling if the object is tiled.
3421  * This function walks the fence regs looking for a free one for @obj,
3422  * stealing one if it can't find any.
3423  *
3424  * It then sets up the reg based on the object's properties: address, pitch
3425  * and tiling format.
3426  *
3427  * For an untiled surface, this removes any existing fence.
3428  */
3429 int
3430 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3431 {
3432         struct drm_device *dev = obj->base.dev;
3433         struct drm_i915_private *dev_priv = dev->dev_private;
3434         bool enable = obj->tiling_mode != I915_TILING_NONE;
3435         struct drm_i915_fence_reg *reg;
3436         int ret;
3437
3438         /* Have we updated the tiling parameters upon the object and so
3439          * will need to serialise the write to the associated fence register?
3440          */
3441         if (obj->fence_dirty) {
3442                 ret = i915_gem_object_wait_fence(obj);
3443                 if (ret)
3444                         return ret;
3445         }
3446
3447         /* Just update our place in the LRU if our fence is getting reused. */
3448         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3449                 reg = &dev_priv->fence_regs[obj->fence_reg];
3450                 if (!obj->fence_dirty) {
3451                         list_move_tail(&reg->lru_list,
3452                                        &dev_priv->mm.fence_list);
3453                         return 0;
3454                 }
3455         } else if (enable) {
3456                 if (WARN_ON(!obj->map_and_fenceable))
3457                         return -EINVAL;
3458
3459                 reg = i915_find_fence_reg(dev);
3460                 if (IS_ERR(reg))
3461                         return PTR_ERR(reg);
3462
3463                 if (reg->obj) {
3464                         struct drm_i915_gem_object *old = reg->obj;
3465
3466                         ret = i915_gem_object_wait_fence(old);
3467                         if (ret)
3468                                 return ret;
3469
3470                         i915_gem_object_fence_lost(old);
3471                 }
3472         } else
3473                 return 0;
3474
3475         i915_gem_object_update_fence(obj, reg, enable);
3476
3477         return 0;
3478 }
3479
3480 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3481                                      unsigned long cache_level)
3482 {
3483         struct drm_mm_node *gtt_space = &vma->node;
3484         struct drm_mm_node *other;
3485
3486         /*
3487          * On some machines we have to be careful when putting differing types
3488          * of snoopable memory together to avoid the prefetcher crossing memory
3489          * domains and dying. During vm initialisation, we decide whether or not
3490          * these constraints apply and set the drm_mm.color_adjust
3491          * appropriately.
3492          */
3493         if (vma->vm->mm.color_adjust == NULL)
3494                 return true;
3495
3496         if (!drm_mm_node_allocated(gtt_space))
3497                 return true;
3498
3499         if (list_empty(&gtt_space->node_list))
3500                 return true;
3501
3502         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3503         if (other->allocated && !other->hole_follows && other->color != cache_level)
3504                 return false;
3505
3506         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3507         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3508                 return false;
3509
3510         return true;
3511 }
3512
3513 /**
3514  * Finds free space in the GTT aperture and binds the object there.
3515  */
3516 static struct i915_vma *
3517 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3518                            struct i915_address_space *vm,
3519                            unsigned alignment,
3520                            uint64_t flags,
3521                            const struct i915_ggtt_view *view)
3522 {
3523         struct drm_device *dev = obj->base.dev;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         u32 size, fence_size, fence_alignment, unfenced_alignment;
3526         unsigned long start =
3527                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3528         unsigned long end =
3529                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3530         struct i915_vma *vma;
3531         int ret;
3532
3533         fence_size = i915_gem_get_gtt_size(dev,
3534                                            obj->base.size,
3535                                            obj->tiling_mode);
3536         fence_alignment = i915_gem_get_gtt_alignment(dev,
3537                                                      obj->base.size,
3538                                                      obj->tiling_mode, true);
3539         unfenced_alignment =
3540                 i915_gem_get_gtt_alignment(dev,
3541                                            obj->base.size,
3542                                            obj->tiling_mode, false);
3543
3544         if (alignment == 0)
3545                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3546                                                 unfenced_alignment;
3547         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3548                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3549                 return ERR_PTR(-EINVAL);
3550         }
3551
3552         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3553
3554         /* If the object is bigger than the entire aperture, reject it early
3555          * before evicting everything in a vain attempt to find space.
3556          */
3557         if (obj->base.size > end) {
3558                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3559                           obj->base.size,
3560                           flags & PIN_MAPPABLE ? "mappable" : "total",
3561                           end);
3562                 return ERR_PTR(-E2BIG);
3563         }
3564
3565         ret = i915_gem_object_get_pages(obj);
3566         if (ret)
3567                 return ERR_PTR(ret);
3568
3569         i915_gem_object_pin_pages(obj);
3570
3571         vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view);
3572         if (IS_ERR(vma))
3573                 goto err_unpin;
3574
3575 search_free:
3576         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3577                                                   size, alignment,
3578                                                   obj->cache_level,
3579                                                   start, end,
3580                                                   DRM_MM_SEARCH_DEFAULT,
3581                                                   DRM_MM_CREATE_DEFAULT);
3582         if (ret) {
3583                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3584                                                obj->cache_level,
3585                                                start, end,
3586                                                flags);
3587                 if (ret == 0)
3588                         goto search_free;
3589
3590                 goto err_free_vma;
3591         }
3592         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3593                 ret = -EINVAL;
3594                 goto err_remove_node;
3595         }
3596
3597         ret = i915_gem_gtt_prepare_object(obj);
3598         if (ret)
3599                 goto err_remove_node;
3600
3601         trace_i915_vma_bind(vma, flags);
3602         ret = i915_vma_bind(vma, obj->cache_level,
3603                             flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3604         if (ret)
3605                 goto err_finish_gtt;
3606
3607         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3608         list_add_tail(&vma->mm_list, &vm->inactive_list);
3609
3610         return vma;
3611
3612 err_finish_gtt:
3613         i915_gem_gtt_finish_object(obj);
3614 err_remove_node:
3615         drm_mm_remove_node(&vma->node);
3616 err_free_vma:
3617         i915_gem_vma_destroy(vma);
3618         vma = ERR_PTR(ret);
3619 err_unpin:
3620         i915_gem_object_unpin_pages(obj);
3621         return vma;
3622 }
3623
3624 bool
3625 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3626                         bool force)
3627 {
3628         /* If we don't have a page list set up, then we're not pinned
3629          * to GPU, and we can ignore the cache flush because it'll happen
3630          * again at bind time.
3631          */
3632         if (obj->pages == NULL)
3633                 return false;
3634
3635         /*
3636          * Stolen memory is always coherent with the GPU as it is explicitly
3637          * marked as wc by the system, or the system is cache-coherent.
3638          */
3639         if (obj->stolen || obj->phys_handle)
3640                 return false;
3641
3642         /* If the GPU is snooping the contents of the CPU cache,
3643          * we do not need to manually clear the CPU cache lines.  However,
3644          * the caches are only snooped when the render cache is
3645          * flushed/invalidated.  As we always have to emit invalidations
3646          * and flushes when moving into and out of the RENDER domain, correct
3647          * snooping behaviour occurs naturally as the result of our domain
3648          * tracking.
3649          */
3650         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3651                 obj->cache_dirty = true;
3652                 return false;
3653         }
3654
3655         trace_i915_gem_object_clflush(obj);
3656         drm_clflush_sg(obj->pages);
3657         obj->cache_dirty = false;
3658
3659         return true;
3660 }
3661
3662 /** Flushes the GTT write domain for the object if it's dirty. */
3663 static void
3664 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3665 {
3666         uint32_t old_write_domain;
3667
3668         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3669                 return;
3670
3671         /* No actual flushing is required for the GTT write domain.  Writes
3672          * to it immediately go to main memory as far as we know, so there's
3673          * no chipset flush.  It also doesn't land in render cache.
3674          *
3675          * However, we do have to enforce the order so that all writes through
3676          * the GTT land before any writes to the device, such as updates to
3677          * the GATT itself.
3678          */
3679         wmb();
3680
3681         old_write_domain = obj->base.write_domain;
3682         obj->base.write_domain = 0;
3683
3684         intel_fb_obj_flush(obj, false);
3685
3686         trace_i915_gem_object_change_domain(obj,
3687                                             obj->base.read_domains,
3688                                             old_write_domain);
3689 }
3690
3691 /** Flushes the CPU write domain for the object if it's dirty. */
3692 static void
3693 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3694 {
3695         uint32_t old_write_domain;
3696
3697         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3698                 return;
3699
3700         if (i915_gem_clflush_object(obj, obj->pin_display))
3701                 i915_gem_chipset_flush(obj->base.dev);
3702
3703         old_write_domain = obj->base.write_domain;
3704         obj->base.write_domain = 0;
3705
3706         intel_fb_obj_flush(obj, false);
3707
3708         trace_i915_gem_object_change_domain(obj,
3709                                             obj->base.read_domains,
3710                                             old_write_domain);
3711 }
3712
3713 /**
3714  * Moves a single object to the GTT read, and possibly write domain.
3715  *
3716  * This function returns when the move is complete, including waiting on
3717  * flushes to occur.
3718  */
3719 int
3720 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3721 {
3722         uint32_t old_write_domain, old_read_domains;
3723         struct i915_vma *vma;
3724         int ret;
3725
3726         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3727                 return 0;
3728
3729         ret = i915_gem_object_wait_rendering(obj, !write);
3730         if (ret)
3731                 return ret;
3732
3733         i915_gem_object_retire(obj);
3734
3735         /* Flush and acquire obj->pages so that we are coherent through
3736          * direct access in memory with previous cached writes through
3737          * shmemfs and that our cache domain tracking remains valid.
3738          * For example, if the obj->filp was moved to swap without us
3739          * being notified and releasing the pages, we would mistakenly
3740          * continue to assume that the obj remained out of the CPU cached
3741          * domain.
3742          */
3743         ret = i915_gem_object_get_pages(obj);
3744         if (ret)
3745                 return ret;
3746
3747         i915_gem_object_flush_cpu_write_domain(obj);
3748
3749         /* Serialise direct access to this object with the barriers for
3750          * coherent writes from the GPU, by effectively invalidating the
3751          * GTT domain upon first access.
3752          */
3753         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3754                 mb();
3755
3756         old_write_domain = obj->base.write_domain;
3757         old_read_domains = obj->base.read_domains;
3758
3759         /* It should now be out of any other write domains, and we can update
3760          * the domain values for our changes.
3761          */
3762         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3763         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3764         if (write) {
3765                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3766                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3767                 obj->dirty = 1;
3768         }
3769
3770         if (write)
3771                 intel_fb_obj_invalidate(obj, NULL);
3772
3773         trace_i915_gem_object_change_domain(obj,
3774                                             old_read_domains,
3775                                             old_write_domain);
3776
3777         /* And bump the LRU for this access */
3778         vma = i915_gem_obj_to_ggtt(obj);
3779         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3780                 list_move_tail(&vma->mm_list,
3781                                &to_i915(obj->base.dev)->gtt.base.inactive_list);
3782
3783         return 0;
3784 }
3785
3786 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3787                                     enum i915_cache_level cache_level)
3788 {
3789         struct drm_device *dev = obj->base.dev;
3790         struct i915_vma *vma, *next;
3791         int ret;
3792
3793         if (obj->cache_level == cache_level)
3794                 return 0;
3795
3796         if (i915_gem_obj_is_pinned(obj)) {
3797                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3798                 return -EBUSY;
3799         }
3800
3801         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3802                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3803                         ret = i915_vma_unbind(vma);
3804                         if (ret)
3805                                 return ret;
3806                 }
3807         }
3808
3809         if (i915_gem_obj_bound_any(obj)) {
3810                 ret = i915_gem_object_finish_gpu(obj);
3811                 if (ret)
3812                         return ret;
3813
3814                 i915_gem_object_finish_gtt(obj);
3815
3816                 /* Before SandyBridge, you could not use tiling or fence
3817                  * registers with snooped memory, so relinquish any fences
3818                  * currently pointing to our region in the aperture.
3819                  */
3820                 if (INTEL_INFO(dev)->gen < 6) {
3821                         ret = i915_gem_object_put_fence(obj);
3822                         if (ret)
3823                                 return ret;
3824                 }
3825
3826                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3827                         if (drm_mm_node_allocated(&vma->node)) {
3828                                 ret = i915_vma_bind(vma, cache_level,
3829                                                     vma->bound & GLOBAL_BIND);
3830                                 if (ret)
3831                                         return ret;
3832                         }
3833         }
3834
3835         list_for_each_entry(vma, &obj->vma_list, vma_link)
3836                 vma->node.color = cache_level;
3837         obj->cache_level = cache_level;
3838
3839         if (obj->cache_dirty &&
3840             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3841             cpu_write_needs_clflush(obj)) {
3842                 if (i915_gem_clflush_object(obj, true))
3843                         i915_gem_chipset_flush(obj->base.dev);
3844         }
3845
3846         return 0;
3847 }
3848
3849 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3850                                struct drm_file *file)
3851 {
3852         struct drm_i915_gem_caching *args = data;
3853         struct drm_i915_gem_object *obj;
3854         int ret;
3855
3856         ret = i915_mutex_lock_interruptible(dev);
3857         if (ret)
3858                 return ret;
3859
3860         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3861         if (&obj->base == NULL) {
3862                 ret = -ENOENT;
3863                 goto unlock;
3864         }
3865
3866         switch (obj->cache_level) {
3867         case I915_CACHE_LLC:
3868         case I915_CACHE_L3_LLC:
3869                 args->caching = I915_CACHING_CACHED;
3870                 break;
3871
3872         case I915_CACHE_WT:
3873                 args->caching = I915_CACHING_DISPLAY;
3874                 break;
3875
3876         default:
3877                 args->caching = I915_CACHING_NONE;
3878                 break;
3879         }
3880
3881         drm_gem_object_unreference(&obj->base);
3882 unlock:
3883         mutex_unlock(&dev->struct_mutex);
3884         return ret;
3885 }
3886
3887 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3888                                struct drm_file *file)
3889 {
3890         struct drm_i915_gem_caching *args = data;
3891         struct drm_i915_gem_object *obj;
3892         enum i915_cache_level level;
3893         int ret;
3894
3895         switch (args->caching) {
3896         case I915_CACHING_NONE:
3897                 level = I915_CACHE_NONE;
3898                 break;
3899         case I915_CACHING_CACHED:
3900                 level = I915_CACHE_LLC;
3901                 break;
3902         case I915_CACHING_DISPLAY:
3903                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3904                 break;
3905         default:
3906                 return -EINVAL;
3907         }
3908
3909         ret = i915_mutex_lock_interruptible(dev);
3910         if (ret)
3911                 return ret;
3912
3913         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3914         if (&obj->base == NULL) {
3915                 ret = -ENOENT;
3916                 goto unlock;
3917         }
3918
3919         ret = i915_gem_object_set_cache_level(obj, level);
3920
3921         drm_gem_object_unreference(&obj->base);
3922 unlock:
3923         mutex_unlock(&dev->struct_mutex);
3924         return ret;
3925 }
3926
3927 static bool is_pin_display(struct drm_i915_gem_object *obj)
3928 {
3929         struct i915_vma *vma;
3930
3931         vma = i915_gem_obj_to_ggtt(obj);
3932         if (!vma)
3933                 return false;
3934
3935         /* There are 2 sources that pin objects:
3936          *   1. The display engine (scanouts, sprites, cursors);
3937          *   2. Reservations for execbuffer;
3938          *
3939          * We can ignore reservations as we hold the struct_mutex and
3940          * are only called outside of the reservation path.
3941          */
3942         return vma->pin_count;
3943 }
3944
3945 /*
3946  * Prepare buffer for display plane (scanout, cursors, etc).
3947  * Can be called from an uninterruptible phase (modesetting) and allows
3948  * any flushes to be pipelined (for pageflips).
3949  */
3950 int
3951 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3952                                      u32 alignment,
3953                                      struct intel_engine_cs *pipelined)
3954 {
3955         u32 old_read_domains, old_write_domain;
3956         bool was_pin_display;
3957         int ret;
3958
3959         if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3960                 ret = i915_gem_object_sync(obj, pipelined);
3961                 if (ret)
3962                         return ret;
3963         }
3964
3965         /* Mark the pin_display early so that we account for the
3966          * display coherency whilst setting up the cache domains.
3967          */
3968         was_pin_display = obj->pin_display;
3969         obj->pin_display = true;
3970
3971         /* The display engine is not coherent with the LLC cache on gen6.  As
3972          * a result, we make sure that the pinning that is about to occur is
3973          * done with uncached PTEs. This is lowest common denominator for all
3974          * chipsets.
3975          *
3976          * However for gen6+, we could do better by using the GFDT bit instead
3977          * of uncaching, which would allow us to flush all the LLC-cached data
3978          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3979          */
3980         ret = i915_gem_object_set_cache_level(obj,
3981                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3982         if (ret)
3983                 goto err_unpin_display;
3984
3985         /* As the user may map the buffer once pinned in the display plane
3986          * (e.g. libkms for the bootup splash), we have to ensure that we
3987          * always use map_and_fenceable for all scanout buffers.
3988          */
3989         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3990         if (ret)
3991                 goto err_unpin_display;
3992
3993         i915_gem_object_flush_cpu_write_domain(obj);
3994
3995         old_write_domain = obj->base.write_domain;
3996         old_read_domains = obj->base.read_domains;
3997
3998         /* It should now be out of any other write domains, and we can update
3999          * the domain values for our changes.
4000          */
4001         obj->base.write_domain = 0;
4002         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4003
4004         trace_i915_gem_object_change_domain(obj,
4005                                             old_read_domains,
4006                                             old_write_domain);
4007
4008         return 0;
4009
4010 err_unpin_display:
4011         WARN_ON(was_pin_display != is_pin_display(obj));
4012         obj->pin_display = was_pin_display;
4013         return ret;
4014 }
4015
4016 void
4017 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4018 {
4019         i915_gem_object_ggtt_unpin(obj);
4020         obj->pin_display = is_pin_display(obj);
4021 }
4022
4023 int
4024 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4025 {
4026         int ret;
4027
4028         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4029                 return 0;
4030
4031         ret = i915_gem_object_wait_rendering(obj, false);
4032         if (ret)
4033                 return ret;
4034
4035         /* Ensure that we invalidate the GPU's caches and TLBs. */
4036         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4037         return 0;
4038 }
4039
4040 /**
4041  * Moves a single object to the CPU read, and possibly write domain.
4042  *
4043  * This function returns when the move is complete, including waiting on
4044  * flushes to occur.
4045  */
4046 int
4047 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4048 {
4049         uint32_t old_write_domain, old_read_domains;
4050         int ret;
4051
4052         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4053                 return 0;
4054
4055         ret = i915_gem_object_wait_rendering(obj, !write);
4056         if (ret)
4057                 return ret;
4058
4059         i915_gem_object_retire(obj);
4060         i915_gem_object_flush_gtt_write_domain(obj);
4061
4062         old_write_domain = obj->base.write_domain;
4063         old_read_domains = obj->base.read_domains;
4064
4065         /* Flush the CPU cache if it's still invalid. */
4066         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4067                 i915_gem_clflush_object(obj, false);
4068
4069                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4070         }
4071
4072         /* It should now be out of any other write domains, and we can update
4073          * the domain values for our changes.
4074          */
4075         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4076
4077         /* If we're writing through the CPU, then the GPU read domains will
4078          * need to be invalidated at next use.
4079          */
4080         if (write) {
4081                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4082                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4083         }
4084
4085         if (write)
4086                 intel_fb_obj_invalidate(obj, NULL);
4087
4088         trace_i915_gem_object_change_domain(obj,
4089                                             old_read_domains,
4090                                             old_write_domain);
4091
4092         return 0;
4093 }
4094
4095 /* Throttle our rendering by waiting until the ring has completed our requests
4096  * emitted over 20 msec ago.
4097  *
4098  * Note that if we were to use the current jiffies each time around the loop,
4099  * we wouldn't escape the function with any frames outstanding if the time to
4100  * render a frame was over 20ms.
4101  *
4102  * This should get us reasonable parallelism between CPU and GPU but also
4103  * relatively low latency when blocking on a particular request to finish.
4104  */
4105 static int
4106 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4107 {
4108         struct drm_i915_private *dev_priv = dev->dev_private;
4109         struct drm_i915_file_private *file_priv = file->driver_priv;
4110         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4111         struct drm_i915_gem_request *request, *target = NULL;
4112         unsigned reset_counter;
4113         int ret;
4114
4115         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4116         if (ret)
4117                 return ret;
4118
4119         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4120         if (ret)
4121                 return ret;
4122
4123         spin_lock(&file_priv->mm.lock);
4124         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4125                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4126                         break;
4127
4128                 target = request;
4129         }
4130         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4131         if (target)
4132                 i915_gem_request_reference(target);
4133         spin_unlock(&file_priv->mm.lock);
4134
4135         if (target == NULL)
4136                 return 0;
4137
4138         ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4139         if (ret == 0)
4140                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4141
4142         mutex_lock(&dev->struct_mutex);
4143         i915_gem_request_unreference(target);
4144         mutex_unlock(&dev->struct_mutex);
4145
4146         return ret;
4147 }
4148
4149 static bool
4150 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4151 {
4152         struct drm_i915_gem_object *obj = vma->obj;
4153
4154         if (alignment &&
4155             vma->node.start & (alignment - 1))
4156                 return true;
4157
4158         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4159                 return true;
4160
4161         if (flags & PIN_OFFSET_BIAS &&
4162             vma->node.start < (flags & PIN_OFFSET_MASK))
4163                 return true;
4164
4165         return false;
4166 }
4167
4168 int
4169 i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
4170                          struct i915_address_space *vm,
4171                          uint32_t alignment,
4172                          uint64_t flags,
4173                          const struct i915_ggtt_view *view)
4174 {
4175         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4176         struct i915_vma *vma;
4177         unsigned bound;
4178         int ret;
4179
4180         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4181                 return -ENODEV;
4182
4183         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4184                 return -EINVAL;
4185
4186         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4187                 return -EINVAL;
4188
4189         vma = i915_gem_obj_to_vma_view(obj, vm, view);
4190         if (vma) {
4191                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4192                         return -EBUSY;
4193
4194                 if (i915_vma_misplaced(vma, alignment, flags)) {
4195                         WARN(vma->pin_count,
4196                              "bo is already pinned with incorrect alignment:"
4197                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4198                              " obj->map_and_fenceable=%d\n",
4199                              i915_gem_obj_offset_view(obj, vm, view->type),
4200                              alignment,
4201                              !!(flags & PIN_MAPPABLE),
4202                              obj->map_and_fenceable);
4203                         ret = i915_vma_unbind(vma);
4204                         if (ret)
4205                                 return ret;
4206
4207                         vma = NULL;
4208                 }
4209         }
4210
4211         bound = vma ? vma->bound : 0;
4212         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4213                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment,
4214                                                  flags, view);
4215                 if (IS_ERR(vma))
4216                         return PTR_ERR(vma);
4217         }
4218
4219         if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) {
4220                 ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
4221                 if (ret)
4222                         return ret;
4223         }
4224
4225         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4226                 bool mappable, fenceable;
4227                 u32 fence_size, fence_alignment;
4228
4229                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4230                                                    obj->base.size,
4231                                                    obj->tiling_mode);
4232                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4233                                                              obj->base.size,
4234                                                              obj->tiling_mode,
4235                                                              true);
4236
4237                 fenceable = (vma->node.size == fence_size &&
4238                              (vma->node.start & (fence_alignment - 1)) == 0);
4239
4240                 mappable = (vma->node.start + obj->base.size <=
4241                             dev_priv->gtt.mappable_end);
4242
4243                 obj->map_and_fenceable = mappable && fenceable;
4244         }
4245
4246         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4247
4248         vma->pin_count++;
4249         if (flags & PIN_MAPPABLE)
4250                 obj->pin_mappable |= true;
4251
4252         return 0;
4253 }
4254
4255 void
4256 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4257 {
4258         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4259
4260         BUG_ON(!vma);
4261         BUG_ON(vma->pin_count == 0);
4262         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4263
4264         if (--vma->pin_count == 0)
4265                 obj->pin_mappable = false;
4266 }
4267
4268 bool
4269 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4270 {
4271         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4272                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4273                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4274
4275                 WARN_ON(!ggtt_vma ||
4276                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4277                         ggtt_vma->pin_count);
4278                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4279                 return true;
4280         } else
4281                 return false;
4282 }
4283
4284 void
4285 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4286 {
4287         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4288                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4289                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4290                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4291         }
4292 }
4293
4294 int
4295 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4296                     struct drm_file *file)
4297 {
4298         struct drm_i915_gem_busy *args = data;
4299         struct drm_i915_gem_object *obj;
4300         int ret;
4301
4302         ret = i915_mutex_lock_interruptible(dev);
4303         if (ret)
4304                 return ret;
4305
4306         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4307         if (&obj->base == NULL) {
4308                 ret = -ENOENT;
4309                 goto unlock;
4310         }
4311
4312         /* Count all active objects as busy, even if they are currently not used
4313          * by the gpu. Users of this interface expect objects to eventually
4314          * become non-busy without any further actions, therefore emit any
4315          * necessary flushes here.
4316          */
4317         ret = i915_gem_object_flush_active(obj);
4318
4319         args->busy = obj->active;
4320         if (obj->last_read_req) {
4321                 struct intel_engine_cs *ring;
4322                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4323                 ring = i915_gem_request_get_ring(obj->last_read_req);
4324                 args->busy |= intel_ring_flag(ring) << 16;
4325         }
4326
4327         drm_gem_object_unreference(&obj->base);
4328 unlock:
4329         mutex_unlock(&dev->struct_mutex);
4330         return ret;
4331 }
4332
4333 int
4334 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4335                         struct drm_file *file_priv)
4336 {
4337         return i915_gem_ring_throttle(dev, file_priv);
4338 }
4339
4340 int
4341 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4342                        struct drm_file *file_priv)
4343 {
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345         struct drm_i915_gem_madvise *args = data;
4346         struct drm_i915_gem_object *obj;
4347         int ret;
4348
4349         switch (args->madv) {
4350         case I915_MADV_DONTNEED:
4351         case I915_MADV_WILLNEED:
4352             break;
4353         default:
4354             return -EINVAL;
4355         }
4356
4357         ret = i915_mutex_lock_interruptible(dev);
4358         if (ret)
4359                 return ret;
4360
4361         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4362         if (&obj->base == NULL) {
4363                 ret = -ENOENT;
4364                 goto unlock;
4365         }
4366
4367         if (i915_gem_obj_is_pinned(obj)) {
4368                 ret = -EINVAL;
4369                 goto out;
4370         }
4371
4372         if (obj->pages &&
4373             obj->tiling_mode != I915_TILING_NONE &&
4374             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4375                 if (obj->madv == I915_MADV_WILLNEED)
4376                         i915_gem_object_unpin_pages(obj);
4377                 if (args->madv == I915_MADV_WILLNEED)
4378                         i915_gem_object_pin_pages(obj);
4379         }
4380
4381         if (obj->madv != __I915_MADV_PURGED)
4382                 obj->madv = args->madv;
4383
4384         /* if the object is no longer attached, discard its backing storage */
4385         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4386                 i915_gem_object_truncate(obj);
4387
4388         args->retained = obj->madv != __I915_MADV_PURGED;
4389
4390 out:
4391         drm_gem_object_unreference(&obj->base);
4392 unlock:
4393         mutex_unlock(&dev->struct_mutex);
4394         return ret;
4395 }
4396
4397 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4398                           const struct drm_i915_gem_object_ops *ops)
4399 {
4400         INIT_LIST_HEAD(&obj->global_list);
4401         INIT_LIST_HEAD(&obj->ring_list);
4402         INIT_LIST_HEAD(&obj->obj_exec_link);
4403         INIT_LIST_HEAD(&obj->vma_list);
4404         INIT_LIST_HEAD(&obj->batch_pool_list);
4405
4406         obj->ops = ops;
4407
4408         obj->fence_reg = I915_FENCE_REG_NONE;
4409         obj->madv = I915_MADV_WILLNEED;
4410
4411         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4412 }
4413
4414 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4415         .get_pages = i915_gem_object_get_pages_gtt,
4416         .put_pages = i915_gem_object_put_pages_gtt,
4417 };
4418
4419 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4420                                                   size_t size)
4421 {
4422         struct drm_i915_gem_object *obj;
4423         struct address_space *mapping;
4424         gfp_t mask;
4425
4426         obj = i915_gem_object_alloc(dev);
4427         if (obj == NULL)
4428                 return NULL;
4429
4430         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4431                 i915_gem_object_free(obj);
4432                 return NULL;
4433         }
4434
4435         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4436         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4437                 /* 965gm cannot relocate objects above 4GiB. */
4438                 mask &= ~__GFP_HIGHMEM;
4439                 mask |= __GFP_DMA32;
4440         }
4441
4442         mapping = file_inode(obj->base.filp)->i_mapping;
4443         mapping_set_gfp_mask(mapping, mask);
4444
4445         i915_gem_object_init(obj, &i915_gem_object_ops);
4446
4447         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4448         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4449
4450         if (HAS_LLC(dev)) {
4451                 /* On some devices, we can have the GPU use the LLC (the CPU
4452                  * cache) for about a 10% performance improvement
4453                  * compared to uncached.  Graphics requests other than
4454                  * display scanout are coherent with the CPU in
4455                  * accessing this cache.  This means in this mode we
4456                  * don't need to clflush on the CPU side, and on the
4457                  * GPU side we only need to flush internal caches to
4458                  * get data visible to the CPU.
4459                  *
4460                  * However, we maintain the display planes as UC, and so
4461                  * need to rebind when first used as such.
4462                  */
4463                 obj->cache_level = I915_CACHE_LLC;
4464         } else
4465                 obj->cache_level = I915_CACHE_NONE;
4466
4467         trace_i915_gem_object_create(obj);
4468
4469         return obj;
4470 }
4471
4472 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4473 {
4474         /* If we are the last user of the backing storage (be it shmemfs
4475          * pages or stolen etc), we know that the pages are going to be
4476          * immediately released. In this case, we can then skip copying
4477          * back the contents from the GPU.
4478          */
4479
4480         if (obj->madv != I915_MADV_WILLNEED)
4481                 return false;
4482
4483         if (obj->base.filp == NULL)
4484                 return true;
4485
4486         /* At first glance, this looks racy, but then again so would be
4487          * userspace racing mmap against close. However, the first external
4488          * reference to the filp can only be obtained through the
4489          * i915_gem_mmap_ioctl() which safeguards us against the user
4490          * acquiring such a reference whilst we are in the middle of
4491          * freeing the object.
4492          */
4493         return atomic_long_read(&obj->base.filp->f_count) == 1;
4494 }
4495
4496 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4497 {
4498         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4499         struct drm_device *dev = obj->base.dev;
4500         struct drm_i915_private *dev_priv = dev->dev_private;
4501         struct i915_vma *vma, *next;
4502
4503         intel_runtime_pm_get(dev_priv);
4504
4505         trace_i915_gem_object_destroy(obj);
4506
4507         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4508                 int ret;
4509
4510                 vma->pin_count = 0;
4511                 ret = i915_vma_unbind(vma);
4512                 if (WARN_ON(ret == -ERESTARTSYS)) {
4513                         bool was_interruptible;
4514
4515                         was_interruptible = dev_priv->mm.interruptible;
4516                         dev_priv->mm.interruptible = false;
4517
4518                         WARN_ON(i915_vma_unbind(vma));
4519
4520                         dev_priv->mm.interruptible = was_interruptible;
4521                 }
4522         }
4523
4524         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4525          * before progressing. */
4526         if (obj->stolen)
4527                 i915_gem_object_unpin_pages(obj);
4528
4529         WARN_ON(obj->frontbuffer_bits);
4530
4531         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4532             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4533             obj->tiling_mode != I915_TILING_NONE)
4534                 i915_gem_object_unpin_pages(obj);
4535
4536         if (WARN_ON(obj->pages_pin_count))
4537                 obj->pages_pin_count = 0;
4538         if (discard_backing_storage(obj))
4539                 obj->madv = I915_MADV_DONTNEED;
4540         i915_gem_object_put_pages(obj);
4541         i915_gem_object_free_mmap_offset(obj);
4542
4543         BUG_ON(obj->pages);
4544
4545         if (obj->base.import_attach)
4546                 drm_prime_gem_destroy(&obj->base, NULL);
4547
4548         if (obj->ops->release)
4549                 obj->ops->release(obj);
4550
4551         drm_gem_object_release(&obj->base);
4552         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4553
4554         kfree(obj->bit_17);
4555         i915_gem_object_free(obj);
4556
4557         intel_runtime_pm_put(dev_priv);
4558 }
4559
4560 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
4561                                           struct i915_address_space *vm,
4562                                           const struct i915_ggtt_view *view)
4563 {
4564         struct i915_vma *vma;
4565         list_for_each_entry(vma, &obj->vma_list, vma_link)
4566                 if (vma->vm == vm && vma->ggtt_view.type == view->type)
4567                         return vma;
4568
4569         return NULL;
4570 }
4571
4572 void i915_gem_vma_destroy(struct i915_vma *vma)
4573 {
4574         struct i915_address_space *vm = NULL;
4575         WARN_ON(vma->node.allocated);
4576
4577         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4578         if (!list_empty(&vma->exec_list))
4579                 return;
4580
4581         vm = vma->vm;
4582
4583         if (!i915_is_ggtt(vm))
4584                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4585
4586         list_del(&vma->vma_link);
4587
4588         kfree(vma);
4589 }
4590
4591 static void
4592 i915_gem_stop_ringbuffers(struct drm_device *dev)
4593 {
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595         struct intel_engine_cs *ring;
4596         int i;
4597
4598         for_each_ring(ring, dev_priv, i)
4599                 dev_priv->gt.stop_ring(ring);
4600 }
4601
4602 int
4603 i915_gem_suspend(struct drm_device *dev)
4604 {
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         int ret = 0;
4607
4608         mutex_lock(&dev->struct_mutex);
4609         ret = i915_gpu_idle(dev);
4610         if (ret)
4611                 goto err;
4612
4613         i915_gem_retire_requests(dev);
4614
4615         /* Under UMS, be paranoid and evict. */
4616         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4617                 i915_gem_evict_everything(dev);
4618
4619         i915_gem_stop_ringbuffers(dev);
4620         mutex_unlock(&dev->struct_mutex);
4621
4622         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4623         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4624         flush_delayed_work(&dev_priv->mm.idle_work);
4625
4626         /* Assert that we sucessfully flushed all the work and
4627          * reset the GPU back to its idle, low power state.
4628          */
4629         WARN_ON(dev_priv->mm.busy);
4630
4631         return 0;
4632
4633 err:
4634         mutex_unlock(&dev->struct_mutex);
4635         return ret;
4636 }
4637
4638 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4639 {
4640         struct drm_device *dev = ring->dev;
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4643         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4644         int i, ret;
4645
4646         if (!HAS_L3_DPF(dev) || !remap_info)
4647                 return 0;
4648
4649         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4650         if (ret)
4651                 return ret;
4652
4653         /*
4654          * Note: We do not worry about the concurrent register cacheline hang
4655          * here because no other code should access these registers other than
4656          * at initialization time.
4657          */
4658         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4659                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4660                 intel_ring_emit(ring, reg_base + i);
4661                 intel_ring_emit(ring, remap_info[i/4]);
4662         }
4663
4664         intel_ring_advance(ring);
4665
4666         return ret;
4667 }
4668
4669 void i915_gem_init_swizzling(struct drm_device *dev)
4670 {
4671         struct drm_i915_private *dev_priv = dev->dev_private;
4672
4673         if (INTEL_INFO(dev)->gen < 5 ||
4674             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4675                 return;
4676
4677         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4678                                  DISP_TILE_SURFACE_SWIZZLING);
4679
4680         if (IS_GEN5(dev))
4681                 return;
4682
4683         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4684         if (IS_GEN6(dev))
4685                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4686         else if (IS_GEN7(dev))
4687                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4688         else if (IS_GEN8(dev))
4689                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4690         else
4691                 BUG();
4692 }
4693
4694 static bool
4695 intel_enable_blt(struct drm_device *dev)
4696 {
4697         if (!HAS_BLT(dev))
4698                 return false;
4699
4700         /* The blitter was dysfunctional on early prototypes */
4701         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4702                 DRM_INFO("BLT not supported on this pre-production hardware;"
4703                          " graphics performance will be degraded.\n");
4704                 return false;
4705         }
4706
4707         return true;
4708 }
4709
4710 static void init_unused_ring(struct drm_device *dev, u32 base)
4711 {
4712         struct drm_i915_private *dev_priv = dev->dev_private;
4713
4714         I915_WRITE(RING_CTL(base), 0);
4715         I915_WRITE(RING_HEAD(base), 0);
4716         I915_WRITE(RING_TAIL(base), 0);
4717         I915_WRITE(RING_START(base), 0);
4718 }
4719
4720 static void init_unused_rings(struct drm_device *dev)
4721 {
4722         if (IS_I830(dev)) {
4723                 init_unused_ring(dev, PRB1_BASE);
4724                 init_unused_ring(dev, SRB0_BASE);
4725                 init_unused_ring(dev, SRB1_BASE);
4726                 init_unused_ring(dev, SRB2_BASE);
4727                 init_unused_ring(dev, SRB3_BASE);
4728         } else if (IS_GEN2(dev)) {
4729                 init_unused_ring(dev, SRB0_BASE);
4730                 init_unused_ring(dev, SRB1_BASE);
4731         } else if (IS_GEN3(dev)) {
4732                 init_unused_ring(dev, PRB1_BASE);
4733                 init_unused_ring(dev, PRB2_BASE);
4734         }
4735 }
4736
4737 int i915_gem_init_rings(struct drm_device *dev)
4738 {
4739         struct drm_i915_private *dev_priv = dev->dev_private;
4740         int ret;
4741
4742         ret = intel_init_render_ring_buffer(dev);
4743         if (ret)
4744                 return ret;
4745
4746         if (HAS_BSD(dev)) {
4747                 ret = intel_init_bsd_ring_buffer(dev);
4748                 if (ret)
4749                         goto cleanup_render_ring;
4750         }
4751
4752         if (intel_enable_blt(dev)) {
4753                 ret = intel_init_blt_ring_buffer(dev);
4754                 if (ret)
4755                         goto cleanup_bsd_ring;
4756         }
4757
4758         if (HAS_VEBOX(dev)) {
4759                 ret = intel_init_vebox_ring_buffer(dev);
4760                 if (ret)
4761                         goto cleanup_blt_ring;
4762         }
4763
4764         if (HAS_BSD2(dev)) {
4765                 ret = intel_init_bsd2_ring_buffer(dev);
4766                 if (ret)
4767                         goto cleanup_vebox_ring;
4768         }
4769
4770         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4771         if (ret)
4772                 goto cleanup_bsd2_ring;
4773
4774         return 0;
4775
4776 cleanup_bsd2_ring:
4777         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4778 cleanup_vebox_ring:
4779         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4780 cleanup_blt_ring:
4781         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4782 cleanup_bsd_ring:
4783         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4784 cleanup_render_ring:
4785         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4786
4787         return ret;
4788 }
4789
4790 int
4791 i915_gem_init_hw(struct drm_device *dev)
4792 {
4793         struct drm_i915_private *dev_priv = dev->dev_private;
4794         struct intel_engine_cs *ring;
4795         int ret, i;
4796
4797         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4798                 return -EIO;
4799
4800         /* Double layer security blanket, see i915_gem_init() */
4801         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4802
4803         if (dev_priv->ellc_size)
4804                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4805
4806         if (IS_HASWELL(dev))
4807                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4808                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4809
4810         if (HAS_PCH_NOP(dev)) {
4811                 if (IS_IVYBRIDGE(dev)) {
4812                         u32 temp = I915_READ(GEN7_MSG_CTL);
4813                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4814                         I915_WRITE(GEN7_MSG_CTL, temp);
4815                 } else if (INTEL_INFO(dev)->gen >= 7) {
4816                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4817                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4818                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4819                 }
4820         }
4821
4822         i915_gem_init_swizzling(dev);
4823
4824         /*
4825          * At least 830 can leave some of the unused rings
4826          * "active" (ie. head != tail) after resume which
4827          * will prevent c3 entry. Makes sure all unused rings
4828          * are totally idle.
4829          */
4830         init_unused_rings(dev);
4831
4832         for_each_ring(ring, dev_priv, i) {
4833                 ret = ring->init_hw(ring);
4834                 if (ret)
4835                         goto out;
4836         }
4837
4838         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4839                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4840
4841         ret = i915_ppgtt_init_hw(dev);
4842         if (ret && ret != -EIO) {
4843                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4844                 i915_gem_cleanup_ringbuffer(dev);
4845         }
4846
4847         ret = i915_gem_context_enable(dev_priv);
4848         if (ret && ret != -EIO) {
4849                 DRM_ERROR("Context enable failed %d\n", ret);
4850                 i915_gem_cleanup_ringbuffer(dev);
4851
4852                 goto out;
4853         }
4854
4855 out:
4856         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4857         return ret;
4858 }
4859
4860 int i915_gem_init(struct drm_device *dev)
4861 {
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         int ret;
4864
4865         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4866                         i915.enable_execlists);
4867
4868         mutex_lock(&dev->struct_mutex);
4869
4870         if (IS_VALLEYVIEW(dev)) {
4871                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4872                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4873                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4874                               VLV_GTLC_ALLOWWAKEACK), 10))
4875                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4876         }
4877
4878         if (!i915.enable_execlists) {
4879                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4880                 dev_priv->gt.init_rings = i915_gem_init_rings;
4881                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4882                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4883         } else {
4884                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4885                 dev_priv->gt.init_rings = intel_logical_rings_init;
4886                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4887                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4888         }
4889
4890         /* This is just a security blanket to placate dragons.
4891          * On some systems, we very sporadically observe that the first TLBs
4892          * used by the CS may be stale, despite us poking the TLB reset. If
4893          * we hold the forcewake during initialisation these problems
4894          * just magically go away.
4895          */
4896         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4897
4898         ret = i915_gem_init_userptr(dev);
4899         if (ret)
4900                 goto out_unlock;
4901
4902         i915_gem_init_global_gtt(dev);
4903
4904         ret = i915_gem_context_init(dev);
4905         if (ret)
4906                 goto out_unlock;
4907
4908         ret = dev_priv->gt.init_rings(dev);
4909         if (ret)
4910                 goto out_unlock;
4911
4912         ret = i915_gem_init_hw(dev);
4913         if (ret == -EIO) {
4914                 /* Allow ring initialisation to fail by marking the GPU as
4915                  * wedged. But we only want to do this where the GPU is angry,
4916                  * for all other failure, such as an allocation failure, bail.
4917                  */
4918                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4919                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4920                 ret = 0;
4921         }
4922
4923 out_unlock:
4924         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4925         mutex_unlock(&dev->struct_mutex);
4926
4927         return ret;
4928 }
4929
4930 void
4931 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4932 {
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934         struct intel_engine_cs *ring;
4935         int i;
4936
4937         for_each_ring(ring, dev_priv, i)
4938                 dev_priv->gt.cleanup_ring(ring);
4939 }
4940
4941 static void
4942 init_ring_lists(struct intel_engine_cs *ring)
4943 {
4944         INIT_LIST_HEAD(&ring->active_list);
4945         INIT_LIST_HEAD(&ring->request_list);
4946 }
4947
4948 void i915_init_vm(struct drm_i915_private *dev_priv,
4949                   struct i915_address_space *vm)
4950 {
4951         if (!i915_is_ggtt(vm))
4952                 drm_mm_init(&vm->mm, vm->start, vm->total);
4953         vm->dev = dev_priv->dev;
4954         INIT_LIST_HEAD(&vm->active_list);
4955         INIT_LIST_HEAD(&vm->inactive_list);
4956         INIT_LIST_HEAD(&vm->global_link);
4957         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4958 }
4959
4960 void
4961 i915_gem_load(struct drm_device *dev)
4962 {
4963         struct drm_i915_private *dev_priv = dev->dev_private;
4964         int i;
4965
4966         dev_priv->slab =
4967                 kmem_cache_create("i915_gem_object",
4968                                   sizeof(struct drm_i915_gem_object), 0,
4969                                   SLAB_HWCACHE_ALIGN,
4970                                   NULL);
4971
4972         INIT_LIST_HEAD(&dev_priv->vm_list);
4973         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4974
4975         INIT_LIST_HEAD(&dev_priv->context_list);
4976         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4977         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4978         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4979         for (i = 0; i < I915_NUM_RINGS; i++)
4980                 init_ring_lists(&dev_priv->ring[i]);
4981         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4982                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4983         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4984                           i915_gem_retire_work_handler);
4985         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4986                           i915_gem_idle_work_handler);
4987         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4988
4989         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4990         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4991                 I915_WRITE(MI_ARB_STATE,
4992                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4993         }
4994
4995         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4996
4997         /* Old X drivers will take 0-2 for front, back, depth buffers */
4998         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4999                 dev_priv->fence_reg_start = 3;
5000
5001         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5002                 dev_priv->num_fence_regs = 32;
5003         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5004                 dev_priv->num_fence_regs = 16;
5005         else
5006                 dev_priv->num_fence_regs = 8;
5007
5008         /* Initialize fence registers to zero */
5009         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5010         i915_gem_restore_fences(dev);
5011
5012         i915_gem_detect_bit_6_swizzle(dev);
5013         init_waitqueue_head(&dev_priv->pending_flip_queue);
5014
5015         dev_priv->mm.interruptible = true;
5016
5017         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5018         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5019         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5020         register_shrinker(&dev_priv->mm.shrinker);
5021
5022         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5023         register_oom_notifier(&dev_priv->mm.oom_notifier);
5024
5025         i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool);
5026
5027         mutex_init(&dev_priv->fb_tracking.lock);
5028 }
5029
5030 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5031 {
5032         struct drm_i915_file_private *file_priv = file->driver_priv;
5033
5034         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5035
5036         /* Clean up our request list when the client is going away, so that
5037          * later retire_requests won't dereference our soon-to-be-gone
5038          * file_priv.
5039          */
5040         spin_lock(&file_priv->mm.lock);
5041         while (!list_empty(&file_priv->mm.request_list)) {
5042                 struct drm_i915_gem_request *request;
5043
5044                 request = list_first_entry(&file_priv->mm.request_list,
5045                                            struct drm_i915_gem_request,
5046                                            client_list);
5047                 list_del(&request->client_list);
5048                 request->file_priv = NULL;
5049         }
5050         spin_unlock(&file_priv->mm.lock);
5051 }
5052
5053 static void
5054 i915_gem_file_idle_work_handler(struct work_struct *work)
5055 {
5056         struct drm_i915_file_private *file_priv =
5057                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5058
5059         atomic_set(&file_priv->rps_wait_boost, false);
5060 }
5061
5062 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5063 {
5064         struct drm_i915_file_private *file_priv;
5065         int ret;
5066
5067         DRM_DEBUG_DRIVER("\n");
5068
5069         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5070         if (!file_priv)
5071                 return -ENOMEM;
5072
5073         file->driver_priv = file_priv;
5074         file_priv->dev_priv = dev->dev_private;
5075         file_priv->file = file;
5076
5077         spin_lock_init(&file_priv->mm.lock);
5078         INIT_LIST_HEAD(&file_priv->mm.request_list);
5079         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5080                           i915_gem_file_idle_work_handler);
5081
5082         ret = i915_gem_context_open(dev, file);
5083         if (ret)
5084                 kfree(file_priv);
5085
5086         return ret;
5087 }
5088
5089 /**
5090  * i915_gem_track_fb - update frontbuffer tracking
5091  * old: current GEM buffer for the frontbuffer slots
5092  * new: new GEM buffer for the frontbuffer slots
5093  * frontbuffer_bits: bitmask of frontbuffer slots
5094  *
5095  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5096  * from @old and setting them in @new. Both @old and @new can be NULL.
5097  */
5098 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5099                        struct drm_i915_gem_object *new,
5100                        unsigned frontbuffer_bits)
5101 {
5102         if (old) {
5103                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5104                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5105                 old->frontbuffer_bits &= ~frontbuffer_bits;
5106         }
5107
5108         if (new) {
5109                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5110                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5111                 new->frontbuffer_bits |= frontbuffer_bits;
5112         }
5113 }
5114
5115 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5116 {
5117         if (!mutex_is_locked(mutex))
5118                 return false;
5119
5120 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5121         return mutex->owner == task;
5122 #else
5123         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5124         return false;
5125 #endif
5126 }
5127
5128 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5129 {
5130         if (!mutex_trylock(&dev->struct_mutex)) {
5131                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5132                         return false;
5133
5134                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5135                         return false;
5136
5137                 *unlock = false;
5138         } else
5139                 *unlock = true;
5140
5141         return true;
5142 }
5143
5144 static int num_vma_bound(struct drm_i915_gem_object *obj)
5145 {
5146         struct i915_vma *vma;
5147         int count = 0;
5148
5149         list_for_each_entry(vma, &obj->vma_list, vma_link)
5150                 if (drm_mm_node_allocated(&vma->node))
5151                         count++;
5152
5153         return count;
5154 }
5155
5156 static unsigned long
5157 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5158 {
5159         struct drm_i915_private *dev_priv =
5160                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5161         struct drm_device *dev = dev_priv->dev;
5162         struct drm_i915_gem_object *obj;
5163         unsigned long count;
5164         bool unlock;
5165
5166         if (!i915_gem_shrinker_lock(dev, &unlock))
5167                 return 0;
5168
5169         count = 0;
5170         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5171                 if (obj->pages_pin_count == 0)
5172                         count += obj->base.size >> PAGE_SHIFT;
5173
5174         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5175                 if (!i915_gem_obj_is_pinned(obj) &&
5176                     obj->pages_pin_count == num_vma_bound(obj))
5177                         count += obj->base.size >> PAGE_SHIFT;
5178         }
5179
5180         if (unlock)
5181                 mutex_unlock(&dev->struct_mutex);
5182
5183         return count;
5184 }
5185
5186 /* All the new VM stuff */
5187 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
5188                                        struct i915_address_space *vm,
5189                                        enum i915_ggtt_view_type view)
5190 {
5191         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5192         struct i915_vma *vma;
5193
5194         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5195
5196         list_for_each_entry(vma, &o->vma_list, vma_link) {
5197                 if (vma->vm == vm && vma->ggtt_view.type == view)
5198                         return vma->node.start;
5199
5200         }
5201         WARN(1, "%s vma for this object not found.\n",
5202              i915_is_ggtt(vm) ? "global" : "ppgtt");
5203         return -1;
5204 }
5205
5206 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
5207                              struct i915_address_space *vm,
5208                              enum i915_ggtt_view_type view)
5209 {
5210         struct i915_vma *vma;
5211
5212         list_for_each_entry(vma, &o->vma_list, vma_link)
5213                 if (vma->vm == vm &&
5214                     vma->ggtt_view.type == view &&
5215                     drm_mm_node_allocated(&vma->node))
5216                         return true;
5217
5218         return false;
5219 }
5220
5221 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5222 {
5223         struct i915_vma *vma;
5224
5225         list_for_each_entry(vma, &o->vma_list, vma_link)
5226                 if (drm_mm_node_allocated(&vma->node))
5227                         return true;
5228
5229         return false;
5230 }
5231
5232 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5233                                 struct i915_address_space *vm)
5234 {
5235         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5236         struct i915_vma *vma;
5237
5238         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5239
5240         BUG_ON(list_empty(&o->vma_list));
5241
5242         list_for_each_entry(vma, &o->vma_list, vma_link)
5243                 if (vma->vm == vm)
5244                         return vma->node.size;
5245
5246         return 0;
5247 }
5248
5249 static unsigned long
5250 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5251 {
5252         struct drm_i915_private *dev_priv =
5253                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5254         struct drm_device *dev = dev_priv->dev;
5255         unsigned long freed;
5256         bool unlock;
5257
5258         if (!i915_gem_shrinker_lock(dev, &unlock))
5259                 return SHRINK_STOP;
5260
5261         freed = i915_gem_shrink(dev_priv,
5262                                 sc->nr_to_scan,
5263                                 I915_SHRINK_BOUND |
5264                                 I915_SHRINK_UNBOUND |
5265                                 I915_SHRINK_PURGEABLE);
5266         if (freed < sc->nr_to_scan)
5267                 freed += i915_gem_shrink(dev_priv,
5268                                          sc->nr_to_scan - freed,
5269                                          I915_SHRINK_BOUND |
5270                                          I915_SHRINK_UNBOUND);
5271         if (unlock)
5272                 mutex_unlock(&dev->struct_mutex);
5273
5274         return freed;
5275 }
5276
5277 static int
5278 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5279 {
5280         struct drm_i915_private *dev_priv =
5281                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5282         struct drm_device *dev = dev_priv->dev;
5283         struct drm_i915_gem_object *obj;
5284         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5285         unsigned long pinned, bound, unbound, freed_pages;
5286         bool was_interruptible;
5287         bool unlock;
5288
5289         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5290                 schedule_timeout_killable(1);
5291                 if (fatal_signal_pending(current))
5292                         return NOTIFY_DONE;
5293         }
5294         if (timeout == 0) {
5295                 pr_err("Unable to purge GPU memory due lock contention.\n");
5296                 return NOTIFY_DONE;
5297         }
5298
5299         was_interruptible = dev_priv->mm.interruptible;
5300         dev_priv->mm.interruptible = false;
5301
5302         freed_pages = i915_gem_shrink_all(dev_priv);
5303
5304         dev_priv->mm.interruptible = was_interruptible;
5305
5306         /* Because we may be allocating inside our own driver, we cannot
5307          * assert that there are no objects with pinned pages that are not
5308          * being pointed to by hardware.
5309          */
5310         unbound = bound = pinned = 0;
5311         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5312                 if (!obj->base.filp) /* not backed by a freeable object */
5313                         continue;
5314
5315                 if (obj->pages_pin_count)
5316                         pinned += obj->base.size;
5317                 else
5318                         unbound += obj->base.size;
5319         }
5320         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5321                 if (!obj->base.filp)
5322                         continue;
5323
5324                 if (obj->pages_pin_count)
5325                         pinned += obj->base.size;
5326                 else
5327                         bound += obj->base.size;
5328         }
5329
5330         if (unlock)
5331                 mutex_unlock(&dev->struct_mutex);
5332
5333         if (freed_pages || unbound || bound)
5334                 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5335                         freed_pages << PAGE_SHIFT, pinned);
5336         if (unbound || bound)
5337                 pr_err("%lu and %lu bytes still available in the "
5338                        "bound and unbound GPU page lists.\n",
5339                        bound, unbound);
5340
5341         *(unsigned long *)ptr += freed_pages;
5342         return NOTIFY_DONE;
5343 }
5344
5345 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5346 {
5347         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5348         struct i915_vma *vma;
5349
5350         list_for_each_entry(vma, &obj->vma_list, vma_link)
5351                 if (vma->vm == ggtt &&
5352                     vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5353                         return vma;
5354
5355         return NULL;
5356 }