2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
40 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
51 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
53 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
57 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
59 static LIST_HEAD(shrink_list);
60 static DEFINE_SPINLOCK(shrink_list_lock);
63 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
65 return obj_priv->gtt_space &&
67 obj_priv->pin_count == 0;
70 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
73 drm_i915_private_t *dev_priv = dev->dev_private;
76 (start & (PAGE_SIZE - 1)) != 0 ||
77 (end & (PAGE_SIZE - 1)) != 0) {
81 drm_mm_init(&dev_priv->mm.gtt_space, start,
84 dev->gtt_total = (uint32_t) (end - start);
90 i915_gem_init_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
93 struct drm_i915_gem_init *args = data;
96 mutex_lock(&dev->struct_mutex);
97 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
98 mutex_unlock(&dev->struct_mutex);
104 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
105 struct drm_file *file_priv)
107 struct drm_i915_gem_get_aperture *args = data;
109 if (!(dev->driver->driver_features & DRIVER_GEM))
112 args->aper_size = dev->gtt_total;
113 args->aper_available_size = (args->aper_size -
114 atomic_read(&dev->pin_memory));
121 * Creates a new mm object and returns a handle to it.
124 i915_gem_create_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv)
127 struct drm_i915_gem_create *args = data;
128 struct drm_gem_object *obj;
132 args->size = roundup(args->size, PAGE_SIZE);
134 /* Allocate the new object */
135 obj = i915_gem_alloc_object(dev, args->size);
139 ret = drm_gem_handle_create(file_priv, obj, &handle);
141 drm_gem_object_unreference_unlocked(obj);
145 /* Sink the floating reference from kref_init(handlecount) */
146 drm_gem_object_handle_unreference_unlocked(obj);
148 args->handle = handle;
153 fast_shmem_read(struct page **pages,
154 loff_t page_base, int page_offset,
161 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
164 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
165 kunmap_atomic(vaddr, KM_USER0);
173 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
175 drm_i915_private_t *dev_priv = obj->dev->dev_private;
176 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
178 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
179 obj_priv->tiling_mode != I915_TILING_NONE;
183 slow_shmem_copy(struct page *dst_page,
185 struct page *src_page,
189 char *dst_vaddr, *src_vaddr;
191 dst_vaddr = kmap(dst_page);
192 src_vaddr = kmap(src_page);
194 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap(gpu_page);
221 cpu_vaddr = kmap(cpu_page);
223 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
224 * XORing with the other bits (A9 for Y, A9 and A10 for X)
227 int cacheline_end = ALIGN(gpu_offset + 1, 64);
228 int this_length = min(cacheline_end - gpu_offset, length);
229 int swizzled_gpu_offset = gpu_offset ^ 64;
232 memcpy(cpu_vaddr + cpu_offset,
233 gpu_vaddr + swizzled_gpu_offset,
236 memcpy(gpu_vaddr + swizzled_gpu_offset,
237 cpu_vaddr + cpu_offset,
240 cpu_offset += this_length;
241 gpu_offset += this_length;
242 length -= this_length;
250 * This is the fast shmem pread path, which attempts to copy_from_user directly
251 * from the backing pages of the object to the user's address space. On a
252 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
255 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
256 struct drm_i915_gem_pread *args,
257 struct drm_file *file_priv)
259 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
261 loff_t offset, page_base;
262 char __user *user_data;
263 int page_offset, page_length;
266 user_data = (char __user *) (uintptr_t) args->data_ptr;
269 mutex_lock(&dev->struct_mutex);
271 ret = i915_gem_object_get_pages(obj, 0);
275 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
280 obj_priv = to_intel_bo(obj);
281 offset = args->offset;
284 /* Operation in this page
286 * page_base = page offset within aperture
287 * page_offset = offset within page
288 * page_length = bytes to copy for this page
290 page_base = (offset & ~(PAGE_SIZE-1));
291 page_offset = offset & (PAGE_SIZE-1);
292 page_length = remain;
293 if ((page_offset + remain) > PAGE_SIZE)
294 page_length = PAGE_SIZE - page_offset;
296 ret = fast_shmem_read(obj_priv->pages,
297 page_base, page_offset,
298 user_data, page_length);
302 remain -= page_length;
303 user_data += page_length;
304 offset += page_length;
308 i915_gem_object_put_pages(obj);
310 mutex_unlock(&dev->struct_mutex);
316 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
320 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
322 /* If we've insufficient memory to map in the pages, attempt
323 * to make some space by throwing out some old buffers.
325 if (ret == -ENOMEM) {
326 struct drm_device *dev = obj->dev;
328 ret = i915_gem_evict_something(dev, obj->size,
329 i915_gem_get_gtt_alignment(obj));
333 ret = i915_gem_object_get_pages(obj, 0);
340 * This is the fallback shmem pread path, which allocates temporary storage
341 * in kernel space to copy_to_user into outside of the struct_mutex, so we
342 * can copy out of the object's backing pages while holding the struct mutex
343 * and not take page faults.
346 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
347 struct drm_i915_gem_pread *args,
348 struct drm_file *file_priv)
350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
351 struct mm_struct *mm = current->mm;
352 struct page **user_pages;
354 loff_t offset, pinned_pages, i;
355 loff_t first_data_page, last_data_page, num_pages;
356 int shmem_page_index, shmem_page_offset;
357 int data_page_index, data_page_offset;
360 uint64_t data_ptr = args->data_ptr;
361 int do_bit17_swizzling;
365 /* Pin the user pages containing the data. We can't fault while
366 * holding the struct mutex, yet we want to hold it while
367 * dereferencing the user data.
369 first_data_page = data_ptr / PAGE_SIZE;
370 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
371 num_pages = last_data_page - first_data_page + 1;
373 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
374 if (user_pages == NULL)
377 down_read(&mm->mmap_sem);
378 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
379 num_pages, 1, 0, user_pages, NULL);
380 up_read(&mm->mmap_sem);
381 if (pinned_pages < num_pages) {
383 goto fail_put_user_pages;
386 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
388 mutex_lock(&dev->struct_mutex);
390 ret = i915_gem_object_get_pages_or_evict(obj);
394 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
399 obj_priv = to_intel_bo(obj);
400 offset = args->offset;
403 /* Operation in this page
405 * shmem_page_index = page number within shmem file
406 * shmem_page_offset = offset within page in shmem file
407 * data_page_index = page number in get_user_pages return
408 * data_page_offset = offset with data_page_index page.
409 * page_length = bytes to copy for this page
411 shmem_page_index = offset / PAGE_SIZE;
412 shmem_page_offset = offset & ~PAGE_MASK;
413 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
414 data_page_offset = data_ptr & ~PAGE_MASK;
416 page_length = remain;
417 if ((shmem_page_offset + page_length) > PAGE_SIZE)
418 page_length = PAGE_SIZE - shmem_page_offset;
419 if ((data_page_offset + page_length) > PAGE_SIZE)
420 page_length = PAGE_SIZE - data_page_offset;
422 if (do_bit17_swizzling) {
423 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
425 user_pages[data_page_index],
430 slow_shmem_copy(user_pages[data_page_index],
432 obj_priv->pages[shmem_page_index],
437 remain -= page_length;
438 data_ptr += page_length;
439 offset += page_length;
443 i915_gem_object_put_pages(obj);
445 mutex_unlock(&dev->struct_mutex);
447 for (i = 0; i < pinned_pages; i++) {
448 SetPageDirty(user_pages[i]);
449 page_cache_release(user_pages[i]);
451 drm_free_large(user_pages);
457 * Reads data from the object referenced by handle.
459 * On error, the contents of *data are undefined.
462 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
463 struct drm_file *file_priv)
465 struct drm_i915_gem_pread *args = data;
466 struct drm_gem_object *obj;
467 struct drm_i915_gem_object *obj_priv;
470 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
473 obj_priv = to_intel_bo(obj);
475 /* Bounds check source.
477 * XXX: This could use review for overflow issues...
479 if (args->offset > obj->size || args->size > obj->size ||
480 args->offset + args->size > obj->size) {
481 drm_gem_object_unreference_unlocked(obj);
485 if (i915_gem_object_needs_bit17_swizzle(obj)) {
486 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
488 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
490 ret = i915_gem_shmem_pread_slow(dev, obj, args,
494 drm_gem_object_unreference_unlocked(obj);
499 /* This is the fast write path which cannot handle
500 * page faults in the source data
504 fast_user_write(struct io_mapping *mapping,
505 loff_t page_base, int page_offset,
506 char __user *user_data,
510 unsigned long unwritten;
512 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
513 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
515 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
521 /* Here's the write path which can sleep for
526 slow_kernel_write(struct io_mapping *mapping,
527 loff_t gtt_base, int gtt_offset,
528 struct page *user_page, int user_offset,
531 char __iomem *dst_vaddr;
534 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
535 src_vaddr = kmap(user_page);
537 memcpy_toio(dst_vaddr + gtt_offset,
538 src_vaddr + user_offset,
542 io_mapping_unmap(dst_vaddr);
546 fast_shmem_write(struct page **pages,
547 loff_t page_base, int page_offset,
552 unsigned long unwritten;
554 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
557 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
558 kunmap_atomic(vaddr, KM_USER0);
566 * This is the fast pwrite path, where we copy the data directly from the
567 * user into the GTT, uncached.
570 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
571 struct drm_i915_gem_pwrite *args,
572 struct drm_file *file_priv)
574 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
575 drm_i915_private_t *dev_priv = dev->dev_private;
577 loff_t offset, page_base;
578 char __user *user_data;
579 int page_offset, page_length;
582 user_data = (char __user *) (uintptr_t) args->data_ptr;
584 if (!access_ok(VERIFY_READ, user_data, remain))
588 mutex_lock(&dev->struct_mutex);
589 ret = i915_gem_object_pin(obj, 0);
591 mutex_unlock(&dev->struct_mutex);
594 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
598 obj_priv = to_intel_bo(obj);
599 offset = obj_priv->gtt_offset + args->offset;
602 /* Operation in this page
604 * page_base = page offset within aperture
605 * page_offset = offset within page
606 * page_length = bytes to copy for this page
608 page_base = (offset & ~(PAGE_SIZE-1));
609 page_offset = offset & (PAGE_SIZE-1);
610 page_length = remain;
611 if ((page_offset + remain) > PAGE_SIZE)
612 page_length = PAGE_SIZE - page_offset;
614 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
615 page_offset, user_data, page_length);
617 /* If we get a fault while copying data, then (presumably) our
618 * source page isn't available. Return the error and we'll
619 * retry in the slow path.
624 remain -= page_length;
625 user_data += page_length;
626 offset += page_length;
630 i915_gem_object_unpin(obj);
631 mutex_unlock(&dev->struct_mutex);
637 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
638 * the memory and maps it using kmap_atomic for copying.
640 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
641 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
644 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
645 struct drm_i915_gem_pwrite *args,
646 struct drm_file *file_priv)
648 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
649 drm_i915_private_t *dev_priv = dev->dev_private;
651 loff_t gtt_page_base, offset;
652 loff_t first_data_page, last_data_page, num_pages;
653 loff_t pinned_pages, i;
654 struct page **user_pages;
655 struct mm_struct *mm = current->mm;
656 int gtt_page_offset, data_page_offset, data_page_index, page_length;
658 uint64_t data_ptr = args->data_ptr;
662 /* Pin the user pages containing the data. We can't fault while
663 * holding the struct mutex, and all of the pwrite implementations
664 * want to hold it while dereferencing the user data.
666 first_data_page = data_ptr / PAGE_SIZE;
667 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
668 num_pages = last_data_page - first_data_page + 1;
670 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
671 if (user_pages == NULL)
674 down_read(&mm->mmap_sem);
675 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
676 num_pages, 0, 0, user_pages, NULL);
677 up_read(&mm->mmap_sem);
678 if (pinned_pages < num_pages) {
680 goto out_unpin_pages;
683 mutex_lock(&dev->struct_mutex);
684 ret = i915_gem_object_pin(obj, 0);
688 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
690 goto out_unpin_object;
692 obj_priv = to_intel_bo(obj);
693 offset = obj_priv->gtt_offset + args->offset;
696 /* Operation in this page
698 * gtt_page_base = page offset within aperture
699 * gtt_page_offset = offset within page in aperture
700 * data_page_index = page number in get_user_pages return
701 * data_page_offset = offset with data_page_index page.
702 * page_length = bytes to copy for this page
704 gtt_page_base = offset & PAGE_MASK;
705 gtt_page_offset = offset & ~PAGE_MASK;
706 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
707 data_page_offset = data_ptr & ~PAGE_MASK;
709 page_length = remain;
710 if ((gtt_page_offset + page_length) > PAGE_SIZE)
711 page_length = PAGE_SIZE - gtt_page_offset;
712 if ((data_page_offset + page_length) > PAGE_SIZE)
713 page_length = PAGE_SIZE - data_page_offset;
715 slow_kernel_write(dev_priv->mm.gtt_mapping,
716 gtt_page_base, gtt_page_offset,
717 user_pages[data_page_index],
721 remain -= page_length;
722 offset += page_length;
723 data_ptr += page_length;
727 i915_gem_object_unpin(obj);
729 mutex_unlock(&dev->struct_mutex);
731 for (i = 0; i < pinned_pages; i++)
732 page_cache_release(user_pages[i]);
733 drm_free_large(user_pages);
739 * This is the fast shmem pwrite path, which attempts to directly
740 * copy_from_user into the kmapped pages backing the object.
743 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
744 struct drm_i915_gem_pwrite *args,
745 struct drm_file *file_priv)
747 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
749 loff_t offset, page_base;
750 char __user *user_data;
751 int page_offset, page_length;
754 user_data = (char __user *) (uintptr_t) args->data_ptr;
757 mutex_lock(&dev->struct_mutex);
759 ret = i915_gem_object_get_pages(obj, 0);
763 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
767 obj_priv = to_intel_bo(obj);
768 offset = args->offset;
772 /* Operation in this page
774 * page_base = page offset within aperture
775 * page_offset = offset within page
776 * page_length = bytes to copy for this page
778 page_base = (offset & ~(PAGE_SIZE-1));
779 page_offset = offset & (PAGE_SIZE-1);
780 page_length = remain;
781 if ((page_offset + remain) > PAGE_SIZE)
782 page_length = PAGE_SIZE - page_offset;
784 ret = fast_shmem_write(obj_priv->pages,
785 page_base, page_offset,
786 user_data, page_length);
790 remain -= page_length;
791 user_data += page_length;
792 offset += page_length;
796 i915_gem_object_put_pages(obj);
798 mutex_unlock(&dev->struct_mutex);
804 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
805 * the memory and maps it using kmap_atomic for copying.
807 * This avoids taking mmap_sem for faulting on the user's address while the
808 * struct_mutex is held.
811 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
812 struct drm_i915_gem_pwrite *args,
813 struct drm_file *file_priv)
815 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
816 struct mm_struct *mm = current->mm;
817 struct page **user_pages;
819 loff_t offset, pinned_pages, i;
820 loff_t first_data_page, last_data_page, num_pages;
821 int shmem_page_index, shmem_page_offset;
822 int data_page_index, data_page_offset;
825 uint64_t data_ptr = args->data_ptr;
826 int do_bit17_swizzling;
830 /* Pin the user pages containing the data. We can't fault while
831 * holding the struct mutex, and all of the pwrite implementations
832 * want to hold it while dereferencing the user data.
834 first_data_page = data_ptr / PAGE_SIZE;
835 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
836 num_pages = last_data_page - first_data_page + 1;
838 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
839 if (user_pages == NULL)
842 down_read(&mm->mmap_sem);
843 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
844 num_pages, 0, 0, user_pages, NULL);
845 up_read(&mm->mmap_sem);
846 if (pinned_pages < num_pages) {
848 goto fail_put_user_pages;
851 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
853 mutex_lock(&dev->struct_mutex);
855 ret = i915_gem_object_get_pages_or_evict(obj);
859 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
863 obj_priv = to_intel_bo(obj);
864 offset = args->offset;
868 /* Operation in this page
870 * shmem_page_index = page number within shmem file
871 * shmem_page_offset = offset within page in shmem file
872 * data_page_index = page number in get_user_pages return
873 * data_page_offset = offset with data_page_index page.
874 * page_length = bytes to copy for this page
876 shmem_page_index = offset / PAGE_SIZE;
877 shmem_page_offset = offset & ~PAGE_MASK;
878 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
879 data_page_offset = data_ptr & ~PAGE_MASK;
881 page_length = remain;
882 if ((shmem_page_offset + page_length) > PAGE_SIZE)
883 page_length = PAGE_SIZE - shmem_page_offset;
884 if ((data_page_offset + page_length) > PAGE_SIZE)
885 page_length = PAGE_SIZE - data_page_offset;
887 if (do_bit17_swizzling) {
888 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
890 user_pages[data_page_index],
895 slow_shmem_copy(obj_priv->pages[shmem_page_index],
897 user_pages[data_page_index],
902 remain -= page_length;
903 data_ptr += page_length;
904 offset += page_length;
908 i915_gem_object_put_pages(obj);
910 mutex_unlock(&dev->struct_mutex);
912 for (i = 0; i < pinned_pages; i++)
913 page_cache_release(user_pages[i]);
914 drm_free_large(user_pages);
920 * Writes data to the object referenced by handle.
922 * On error, the contents of the buffer that were to be modified are undefined.
925 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
926 struct drm_file *file_priv)
928 struct drm_i915_gem_pwrite *args = data;
929 struct drm_gem_object *obj;
930 struct drm_i915_gem_object *obj_priv;
933 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
936 obj_priv = to_intel_bo(obj);
938 /* Bounds check destination.
940 * XXX: This could use review for overflow issues...
942 if (args->offset > obj->size || args->size > obj->size ||
943 args->offset + args->size > obj->size) {
944 drm_gem_object_unreference_unlocked(obj);
948 /* We can only do the GTT pwrite on untiled buffers, as otherwise
949 * it would end up going through the fenced access, and we'll get
950 * different detiling behavior between reading and writing.
951 * pread/pwrite currently are reading and writing from the CPU
952 * perspective, requiring manual detiling by the client.
954 if (obj_priv->phys_obj)
955 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
956 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
957 dev->gtt_total != 0 &&
958 obj->write_domain != I915_GEM_DOMAIN_CPU) {
959 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
960 if (ret == -EFAULT) {
961 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
964 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
965 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
967 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
968 if (ret == -EFAULT) {
969 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
976 DRM_INFO("pwrite failed %d\n", ret);
979 drm_gem_object_unreference_unlocked(obj);
985 * Called when user space prepares to use an object with the CPU, either
986 * through the mmap ioctl's mapping or a GTT mapping.
989 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *file_priv)
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct drm_i915_gem_set_domain *args = data;
994 struct drm_gem_object *obj;
995 struct drm_i915_gem_object *obj_priv;
996 uint32_t read_domains = args->read_domains;
997 uint32_t write_domain = args->write_domain;
1000 if (!(dev->driver->driver_features & DRIVER_GEM))
1003 /* Only handle setting domains to types used by the CPU. */
1004 if (write_domain & I915_GEM_GPU_DOMAINS)
1007 if (read_domains & I915_GEM_GPU_DOMAINS)
1010 /* Having something in the write domain implies it's in the read
1011 * domain, and only that read domain. Enforce that in the request.
1013 if (write_domain != 0 && read_domains != write_domain)
1016 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1019 obj_priv = to_intel_bo(obj);
1021 mutex_lock(&dev->struct_mutex);
1023 intel_mark_busy(dev, obj);
1026 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1027 obj, obj->size, read_domains, write_domain);
1029 if (read_domains & I915_GEM_DOMAIN_GTT) {
1030 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1032 /* Update the LRU on the fence for the CPU access that's
1035 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1036 struct drm_i915_fence_reg *reg =
1037 &dev_priv->fence_regs[obj_priv->fence_reg];
1038 list_move_tail(®->lru_list,
1039 &dev_priv->mm.fence_list);
1042 /* Silently promote "you're not bound, there was nothing to do"
1043 * to success, since the client was just asking us to
1044 * make sure everything was done.
1049 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1053 /* Maintain LRU order of "inactive" objects */
1054 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1055 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1057 drm_gem_object_unreference(obj);
1058 mutex_unlock(&dev->struct_mutex);
1063 * Called when user space has done writes to this buffer
1066 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv)
1069 struct drm_i915_gem_sw_finish *args = data;
1070 struct drm_gem_object *obj;
1071 struct drm_i915_gem_object *obj_priv;
1074 if (!(dev->driver->driver_features & DRIVER_GEM))
1077 mutex_lock(&dev->struct_mutex);
1078 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1080 mutex_unlock(&dev->struct_mutex);
1085 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1086 __func__, args->handle, obj, obj->size);
1088 obj_priv = to_intel_bo(obj);
1090 /* Pinned buffers may be scanout, so flush the cache */
1091 if (obj_priv->pin_count)
1092 i915_gem_object_flush_cpu_write_domain(obj);
1094 drm_gem_object_unreference(obj);
1095 mutex_unlock(&dev->struct_mutex);
1100 * Maps the contents of an object, returning the address it is mapped
1103 * While the mapping holds a reference on the contents of the object, it doesn't
1104 * imply a ref on the object itself.
1107 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1108 struct drm_file *file_priv)
1110 struct drm_i915_gem_mmap *args = data;
1111 struct drm_gem_object *obj;
1115 if (!(dev->driver->driver_features & DRIVER_GEM))
1118 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1122 offset = args->offset;
1124 down_write(¤t->mm->mmap_sem);
1125 addr = do_mmap(obj->filp, 0, args->size,
1126 PROT_READ | PROT_WRITE, MAP_SHARED,
1128 up_write(¤t->mm->mmap_sem);
1129 drm_gem_object_unreference_unlocked(obj);
1130 if (IS_ERR((void *)addr))
1133 args->addr_ptr = (uint64_t) addr;
1139 * i915_gem_fault - fault a page into the GTT
1140 * vma: VMA in question
1143 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1144 * from userspace. The fault handler takes care of binding the object to
1145 * the GTT (if needed), allocating and programming a fence register (again,
1146 * only if needed based on whether the old reg is still valid or the object
1147 * is tiled) and inserting a new PTE into the faulting process.
1149 * Note that the faulting process may involve evicting existing objects
1150 * from the GTT and/or fence registers to make room. So performance may
1151 * suffer if the GTT working set is large or there are few fence registers
1154 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1156 struct drm_gem_object *obj = vma->vm_private_data;
1157 struct drm_device *dev = obj->dev;
1158 drm_i915_private_t *dev_priv = dev->dev_private;
1159 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1160 pgoff_t page_offset;
1163 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1165 /* We don't use vmf->pgoff since that has the fake offset */
1166 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1169 /* Now bind it into the GTT if needed */
1170 mutex_lock(&dev->struct_mutex);
1171 if (!obj_priv->gtt_space) {
1172 ret = i915_gem_object_bind_to_gtt(obj, 0);
1176 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1181 /* Need a new fence register? */
1182 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1183 ret = i915_gem_object_get_fence_reg(obj);
1188 if (i915_gem_object_is_inactive(obj_priv))
1189 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1191 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1194 /* Finally, remap it using the new GTT offset */
1195 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1197 mutex_unlock(&dev->struct_mutex);
1202 return VM_FAULT_NOPAGE;
1205 return VM_FAULT_OOM;
1207 return VM_FAULT_SIGBUS;
1212 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1213 * @obj: obj in question
1215 * GEM memory mapping works by handing back to userspace a fake mmap offset
1216 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1217 * up the object based on the offset and sets up the various memory mapping
1220 * This routine allocates and attaches a fake offset for @obj.
1223 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1225 struct drm_device *dev = obj->dev;
1226 struct drm_gem_mm *mm = dev->mm_private;
1227 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1228 struct drm_map_list *list;
1229 struct drm_local_map *map;
1232 /* Set the object up for mmap'ing */
1233 list = &obj->map_list;
1234 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1239 map->type = _DRM_GEM;
1240 map->size = obj->size;
1243 /* Get a DRM GEM mmap offset allocated... */
1244 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1245 obj->size / PAGE_SIZE, 0, 0);
1246 if (!list->file_offset_node) {
1247 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1252 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1253 obj->size / PAGE_SIZE, 0);
1254 if (!list->file_offset_node) {
1259 list->hash.key = list->file_offset_node->start;
1260 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1261 DRM_ERROR("failed to add to map hash\n");
1266 /* By now we should be all set, any drm_mmap request on the offset
1267 * below will get to our mmap & fault handler */
1268 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1273 drm_mm_put_block(list->file_offset_node);
1281 * i915_gem_release_mmap - remove physical page mappings
1282 * @obj: obj in question
1284 * Preserve the reservation of the mmapping with the DRM core code, but
1285 * relinquish ownership of the pages back to the system.
1287 * It is vital that we remove the page mapping if we have mapped a tiled
1288 * object through the GTT and then lose the fence register due to
1289 * resource pressure. Similarly if the object has been moved out of the
1290 * aperture, than pages mapped into userspace must be revoked. Removing the
1291 * mapping will then trigger a page fault on the next user access, allowing
1292 * fixup by i915_gem_fault().
1295 i915_gem_release_mmap(struct drm_gem_object *obj)
1297 struct drm_device *dev = obj->dev;
1298 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1300 if (dev->dev_mapping)
1301 unmap_mapping_range(dev->dev_mapping,
1302 obj_priv->mmap_offset, obj->size, 1);
1306 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1308 struct drm_device *dev = obj->dev;
1309 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1310 struct drm_gem_mm *mm = dev->mm_private;
1311 struct drm_map_list *list;
1313 list = &obj->map_list;
1314 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1316 if (list->file_offset_node) {
1317 drm_mm_put_block(list->file_offset_node);
1318 list->file_offset_node = NULL;
1326 obj_priv->mmap_offset = 0;
1330 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1331 * @obj: object to check
1333 * Return the required GTT alignment for an object, taking into account
1334 * potential fence register mapping if needed.
1337 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1339 struct drm_device *dev = obj->dev;
1340 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1344 * Minimum alignment is 4k (GTT page size), but might be greater
1345 * if a fence register is needed for the object.
1347 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1351 * Previous chips need to be aligned to the size of the smallest
1352 * fence register that can contain the object.
1359 for (i = start; i < obj->size; i <<= 1)
1366 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1368 * @data: GTT mapping ioctl data
1369 * @file_priv: GEM object info
1371 * Simply returns the fake offset to userspace so it can mmap it.
1372 * The mmap call will end up in drm_gem_mmap(), which will set things
1373 * up so we can get faults in the handler above.
1375 * The fault handler will take care of binding the object into the GTT
1376 * (since it may have been evicted to make room for something), allocating
1377 * a fence register, and mapping the appropriate aperture address into
1381 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1382 struct drm_file *file_priv)
1384 struct drm_i915_gem_mmap_gtt *args = data;
1385 struct drm_gem_object *obj;
1386 struct drm_i915_gem_object *obj_priv;
1389 if (!(dev->driver->driver_features & DRIVER_GEM))
1392 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1396 mutex_lock(&dev->struct_mutex);
1398 obj_priv = to_intel_bo(obj);
1400 if (obj_priv->madv != I915_MADV_WILLNEED) {
1401 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1402 drm_gem_object_unreference(obj);
1403 mutex_unlock(&dev->struct_mutex);
1408 if (!obj_priv->mmap_offset) {
1409 ret = i915_gem_create_mmap_offset(obj);
1411 drm_gem_object_unreference(obj);
1412 mutex_unlock(&dev->struct_mutex);
1417 args->offset = obj_priv->mmap_offset;
1420 * Pull it into the GTT so that we have a page list (makes the
1421 * initial fault faster and any subsequent flushing possible).
1423 if (!obj_priv->agp_mem) {
1424 ret = i915_gem_object_bind_to_gtt(obj, 0);
1426 drm_gem_object_unreference(obj);
1427 mutex_unlock(&dev->struct_mutex);
1432 drm_gem_object_unreference(obj);
1433 mutex_unlock(&dev->struct_mutex);
1439 i915_gem_object_put_pages(struct drm_gem_object *obj)
1441 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1442 int page_count = obj->size / PAGE_SIZE;
1445 BUG_ON(obj_priv->pages_refcount == 0);
1446 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1448 if (--obj_priv->pages_refcount != 0)
1451 if (obj_priv->tiling_mode != I915_TILING_NONE)
1452 i915_gem_object_save_bit_17_swizzle(obj);
1454 if (obj_priv->madv == I915_MADV_DONTNEED)
1455 obj_priv->dirty = 0;
1457 for (i = 0; i < page_count; i++) {
1458 if (obj_priv->dirty)
1459 set_page_dirty(obj_priv->pages[i]);
1461 if (obj_priv->madv == I915_MADV_WILLNEED)
1462 mark_page_accessed(obj_priv->pages[i]);
1464 page_cache_release(obj_priv->pages[i]);
1466 obj_priv->dirty = 0;
1468 drm_free_large(obj_priv->pages);
1469 obj_priv->pages = NULL;
1473 i915_gem_next_request_seqno(struct drm_device *dev,
1474 struct intel_ring_buffer *ring)
1476 drm_i915_private_t *dev_priv = dev->dev_private;
1478 ring->outstanding_lazy_request = true;
1480 return dev_priv->next_seqno;
1484 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1485 struct intel_ring_buffer *ring)
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1490 BUG_ON(ring == NULL);
1491 obj_priv->ring = ring;
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv->active) {
1495 drm_gem_object_reference(obj);
1496 obj_priv->active = 1;
1499 /* Take the seqno of the next request if none is given */
1501 seqno = i915_gem_next_request_seqno(dev, ring);
1503 /* Move from whatever list we were on to the tail of execution. */
1504 spin_lock(&dev_priv->mm.active_list_lock);
1505 list_move_tail(&obj_priv->list, &ring->active_list);
1506 spin_unlock(&dev_priv->mm.active_list_lock);
1507 obj_priv->last_rendering_seqno = seqno;
1511 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1517 BUG_ON(!obj_priv->active);
1518 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519 obj_priv->last_rendering_seqno = 0;
1522 /* Immediately discard the backing storage */
1524 i915_gem_object_truncate(struct drm_gem_object *obj)
1526 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1527 struct inode *inode;
1529 /* Our goal here is to return as much of the memory as
1530 * is possible back to the system as we are called from OOM.
1531 * To do this we must instruct the shmfs to drop all of its
1532 * backing pages, *now*. Here we mirror the actions taken
1533 * when by shmem_delete_inode() to release the backing store.
1535 inode = obj->filp->f_path.dentry->d_inode;
1536 truncate_inode_pages(inode->i_mapping, 0);
1537 if (inode->i_op->truncate_range)
1538 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1540 obj_priv->madv = __I915_MADV_PURGED;
1544 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1546 return obj_priv->madv == I915_MADV_DONTNEED;
1550 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1552 struct drm_device *dev = obj->dev;
1553 drm_i915_private_t *dev_priv = dev->dev_private;
1554 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1557 if (obj_priv->pin_count != 0)
1558 list_del_init(&obj_priv->list);
1560 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1562 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1564 obj_priv->last_rendering_seqno = 0;
1565 obj_priv->ring = NULL;
1566 if (obj_priv->active) {
1567 obj_priv->active = 0;
1568 drm_gem_object_unreference(obj);
1570 i915_verify_inactive(dev, __FILE__, __LINE__);
1574 i915_gem_process_flushing_list(struct drm_device *dev,
1575 uint32_t flush_domains,
1576 struct intel_ring_buffer *ring)
1578 drm_i915_private_t *dev_priv = dev->dev_private;
1579 struct drm_i915_gem_object *obj_priv, *next;
1581 list_for_each_entry_safe(obj_priv, next,
1582 &dev_priv->mm.gpu_write_list,
1584 struct drm_gem_object *obj = &obj_priv->base;
1586 if ((obj->write_domain & flush_domains) ==
1587 obj->write_domain &&
1588 obj_priv->ring->ring_flag == ring->ring_flag) {
1589 uint32_t old_write_domain = obj->write_domain;
1591 obj->write_domain = 0;
1592 list_del_init(&obj_priv->gpu_write_list);
1593 i915_gem_object_move_to_active(obj, 0, ring);
1595 /* update the fence lru list */
1596 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1597 struct drm_i915_fence_reg *reg =
1598 &dev_priv->fence_regs[obj_priv->fence_reg];
1599 list_move_tail(®->lru_list,
1600 &dev_priv->mm.fence_list);
1603 trace_i915_gem_object_change_domain(obj,
1611 i915_add_request(struct drm_device *dev,
1612 struct drm_file *file_priv,
1613 struct intel_ring_buffer *ring)
1615 drm_i915_private_t *dev_priv = dev->dev_private;
1616 struct drm_i915_file_private *i915_file_priv = NULL;
1617 struct drm_i915_gem_request *request;
1621 if (file_priv != NULL)
1622 i915_file_priv = file_priv->driver_priv;
1624 request = kzalloc(sizeof(*request), GFP_KERNEL);
1625 if (request == NULL)
1628 seqno = ring->add_request(dev, ring, file_priv, 0);
1630 request->seqno = seqno;
1631 request->ring = ring;
1632 request->emitted_jiffies = jiffies;
1633 was_empty = list_empty(&ring->request_list);
1634 list_add_tail(&request->list, &ring->request_list);
1636 if (i915_file_priv) {
1637 list_add_tail(&request->client_list,
1638 &i915_file_priv->mm.request_list);
1640 INIT_LIST_HEAD(&request->client_list);
1643 if (!dev_priv->mm.suspended) {
1644 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1646 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1660 uint32_t flush_domains = 0;
1662 /* The sampler always gets flushed on i965 (sigh) */
1664 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1666 ring->flush(dev, ring,
1667 I915_GEM_DOMAIN_COMMAND, flush_domains);
1671 * Moves buffers associated only with the given active seqno from the active
1672 * to inactive list, potentially freeing them.
1675 i915_gem_retire_request(struct drm_device *dev,
1676 struct drm_i915_gem_request *request)
1678 drm_i915_private_t *dev_priv = dev->dev_private;
1680 trace_i915_gem_request_retire(dev, request->seqno);
1682 /* Move any buffers on the active list that are no longer referenced
1683 * by the ringbuffer to the flushing/inactive lists as appropriate.
1685 spin_lock(&dev_priv->mm.active_list_lock);
1686 while (!list_empty(&request->ring->active_list)) {
1687 struct drm_gem_object *obj;
1688 struct drm_i915_gem_object *obj_priv;
1690 obj_priv = list_first_entry(&request->ring->active_list,
1691 struct drm_i915_gem_object,
1693 obj = &obj_priv->base;
1695 /* If the seqno being retired doesn't match the oldest in the
1696 * list, then the oldest in the list must still be newer than
1699 if (obj_priv->last_rendering_seqno != request->seqno)
1703 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1704 __func__, request->seqno, obj);
1707 if (obj->write_domain != 0)
1708 i915_gem_object_move_to_flushing(obj);
1710 /* Take a reference on the object so it won't be
1711 * freed while the spinlock is held. The list
1712 * protection for this spinlock is safe when breaking
1713 * the lock like this since the next thing we do
1714 * is just get the head of the list again.
1716 drm_gem_object_reference(obj);
1717 i915_gem_object_move_to_inactive(obj);
1718 spin_unlock(&dev_priv->mm.active_list_lock);
1719 drm_gem_object_unreference(obj);
1720 spin_lock(&dev_priv->mm.active_list_lock);
1724 spin_unlock(&dev_priv->mm.active_list_lock);
1728 * Returns true if seq1 is later than seq2.
1731 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1733 return (int32_t)(seq1 - seq2) >= 0;
1737 i915_get_gem_seqno(struct drm_device *dev,
1738 struct intel_ring_buffer *ring)
1740 return ring->get_gem_seqno(dev, ring);
1744 * This function clears the request list as sequence numbers are passed.
1747 i915_gem_retire_requests_ring(struct drm_device *dev,
1748 struct intel_ring_buffer *ring)
1750 drm_i915_private_t *dev_priv = dev->dev_private;
1753 if (!ring->status_page.page_addr
1754 || list_empty(&ring->request_list))
1757 seqno = i915_get_gem_seqno(dev, ring);
1759 while (!list_empty(&ring->request_list)) {
1760 struct drm_i915_gem_request *request;
1761 uint32_t retiring_seqno;
1763 request = list_first_entry(&ring->request_list,
1764 struct drm_i915_gem_request,
1766 retiring_seqno = request->seqno;
1768 if (i915_seqno_passed(seqno, retiring_seqno) ||
1769 atomic_read(&dev_priv->mm.wedged)) {
1770 i915_gem_retire_request(dev, request);
1772 list_del(&request->list);
1773 list_del(&request->client_list);
1779 if (unlikely (dev_priv->trace_irq_seqno &&
1780 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1782 ring->user_irq_put(dev, ring);
1783 dev_priv->trace_irq_seqno = 0;
1788 i915_gem_retire_requests(struct drm_device *dev)
1790 drm_i915_private_t *dev_priv = dev->dev_private;
1792 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1793 struct drm_i915_gem_object *obj_priv, *tmp;
1795 /* We must be careful that during unbind() we do not
1796 * accidentally infinitely recurse into retire requests.
1798 * retire -> free -> unbind -> wait -> retire_ring
1800 list_for_each_entry_safe(obj_priv, tmp,
1801 &dev_priv->mm.deferred_free_list,
1803 i915_gem_free_object_tail(&obj_priv->base);
1806 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1808 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1812 i915_gem_retire_work_handler(struct work_struct *work)
1814 drm_i915_private_t *dev_priv;
1815 struct drm_device *dev;
1817 dev_priv = container_of(work, drm_i915_private_t,
1818 mm.retire_work.work);
1819 dev = dev_priv->dev;
1821 mutex_lock(&dev->struct_mutex);
1822 i915_gem_retire_requests(dev);
1824 if (!dev_priv->mm.suspended &&
1825 (!list_empty(&dev_priv->render_ring.request_list) ||
1827 !list_empty(&dev_priv->bsd_ring.request_list))))
1828 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1829 mutex_unlock(&dev->struct_mutex);
1833 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1834 bool interruptible, struct intel_ring_buffer *ring)
1836 drm_i915_private_t *dev_priv = dev->dev_private;
1842 if (seqno == dev_priv->next_seqno) {
1843 seqno = i915_add_request(dev, NULL, ring);
1848 if (atomic_read(&dev_priv->mm.wedged))
1851 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1852 if (HAS_PCH_SPLIT(dev))
1853 ier = I915_READ(DEIER) | I915_READ(GTIER);
1855 ier = I915_READ(IER);
1857 DRM_ERROR("something (likely vbetool) disabled "
1858 "interrupts, re-enabling\n");
1859 i915_driver_irq_preinstall(dev);
1860 i915_driver_irq_postinstall(dev);
1863 trace_i915_gem_request_wait_begin(dev, seqno);
1865 ring->waiting_gem_seqno = seqno;
1866 ring->user_irq_get(dev, ring);
1868 ret = wait_event_interruptible(ring->irq_queue,
1870 ring->get_gem_seqno(dev, ring), seqno)
1871 || atomic_read(&dev_priv->mm.wedged));
1873 wait_event(ring->irq_queue,
1875 ring->get_gem_seqno(dev, ring), seqno)
1876 || atomic_read(&dev_priv->mm.wedged));
1878 ring->user_irq_put(dev, ring);
1879 ring->waiting_gem_seqno = 0;
1881 trace_i915_gem_request_wait_end(dev, seqno);
1883 if (atomic_read(&dev_priv->mm.wedged))
1886 if (ret && ret != -ERESTARTSYS)
1887 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1888 __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1889 dev_priv->next_seqno);
1891 /* Directly dispatch request retiring. While we have the work queue
1892 * to handle this, the waiter on a request often wants an associated
1893 * buffer to have made it to the inactive list, and we would need
1894 * a separate wait queue to handle that.
1897 i915_gem_retire_requests_ring(dev, ring);
1903 * Waits for a sequence number to be signaled, and cleans up the
1904 * request and object lists appropriately for that event.
1907 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1908 struct intel_ring_buffer *ring)
1910 return i915_do_wait_request(dev, seqno, 1, ring);
1914 i915_gem_flush(struct drm_device *dev,
1915 uint32_t invalidate_domains,
1916 uint32_t flush_domains)
1918 drm_i915_private_t *dev_priv = dev->dev_private;
1920 if (flush_domains & I915_GEM_DOMAIN_CPU)
1921 drm_agp_chipset_flush(dev);
1923 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1928 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1934 * Ensures that all rendering to the object has completed and the object is
1935 * safe to unbind from the GTT or access from the CPU.
1938 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1941 struct drm_device *dev = obj->dev;
1942 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1945 /* This function only exists to support waiting for existing rendering,
1946 * not for emitting required flushes.
1948 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1950 /* If there is rendering queued on the buffer being evicted, wait for
1953 if (obj_priv->active) {
1955 DRM_INFO("%s: object %p wait for seqno %08x\n",
1956 __func__, obj, obj_priv->last_rendering_seqno);
1958 ret = i915_do_wait_request(dev,
1959 obj_priv->last_rendering_seqno,
1970 * Unbinds an object from the GTT aperture.
1973 i915_gem_object_unbind(struct drm_gem_object *obj)
1975 struct drm_device *dev = obj->dev;
1976 drm_i915_private_t *dev_priv = dev->dev_private;
1977 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1981 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1982 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1984 if (obj_priv->gtt_space == NULL)
1987 if (obj_priv->pin_count != 0) {
1988 DRM_ERROR("Attempting to unbind pinned buffer\n");
1992 /* blow away mappings if mapped through GTT */
1993 i915_gem_release_mmap(obj);
1995 /* Move the object to the CPU domain to ensure that
1996 * any possible CPU writes while it's not in the GTT
1997 * are flushed when we go to remap it. This will
1998 * also ensure that all pending GPU writes are finished
2001 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2002 if (ret == -ERESTARTSYS)
2004 /* Continue on if we fail due to EIO, the GPU is hung so we
2005 * should be safe and we need to cleanup or else we might
2006 * cause memory corruption through use-after-free.
2009 /* release the fence reg _after_ flushing */
2010 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2011 i915_gem_clear_fence_reg(obj);
2013 if (obj_priv->agp_mem != NULL) {
2014 drm_unbind_agp(obj_priv->agp_mem);
2015 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2016 obj_priv->agp_mem = NULL;
2019 i915_gem_object_put_pages(obj);
2020 BUG_ON(obj_priv->pages_refcount);
2022 if (obj_priv->gtt_space) {
2023 atomic_dec(&dev->gtt_count);
2024 atomic_sub(obj->size, &dev->gtt_memory);
2026 drm_mm_put_block(obj_priv->gtt_space);
2027 obj_priv->gtt_space = NULL;
2030 /* Remove ourselves from the LRU list if present. */
2031 spin_lock(&dev_priv->mm.active_list_lock);
2032 if (!list_empty(&obj_priv->list))
2033 list_del_init(&obj_priv->list);
2034 spin_unlock(&dev_priv->mm.active_list_lock);
2036 if (i915_gem_object_is_purgeable(obj_priv))
2037 i915_gem_object_truncate(obj);
2039 trace_i915_gem_object_unbind(obj);
2045 i915_gpu_idle(struct drm_device *dev)
2047 drm_i915_private_t *dev_priv = dev->dev_private;
2049 uint32_t seqno1, seqno2;
2052 spin_lock(&dev_priv->mm.active_list_lock);
2053 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2054 list_empty(&dev_priv->render_ring.active_list) &&
2056 list_empty(&dev_priv->bsd_ring.active_list)));
2057 spin_unlock(&dev_priv->mm.active_list_lock);
2062 /* Flush everything onto the inactive list. */
2063 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2064 seqno1 = i915_add_request(dev, NULL, &dev_priv->render_ring);
2067 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2072 seqno2 = i915_add_request(dev, NULL, &dev_priv->bsd_ring);
2075 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2084 i915_gem_object_get_pages(struct drm_gem_object *obj,
2087 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2089 struct address_space *mapping;
2090 struct inode *inode;
2093 BUG_ON(obj_priv->pages_refcount
2094 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2096 if (obj_priv->pages_refcount++ != 0)
2099 /* Get the list of pages out of our struct file. They'll be pinned
2100 * at this point until we release them.
2102 page_count = obj->size / PAGE_SIZE;
2103 BUG_ON(obj_priv->pages != NULL);
2104 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2105 if (obj_priv->pages == NULL) {
2106 obj_priv->pages_refcount--;
2110 inode = obj->filp->f_path.dentry->d_inode;
2111 mapping = inode->i_mapping;
2112 for (i = 0; i < page_count; i++) {
2113 page = read_cache_page_gfp(mapping, i,
2121 obj_priv->pages[i] = page;
2124 if (obj_priv->tiling_mode != I915_TILING_NONE)
2125 i915_gem_object_do_bit_17_swizzle(obj);
2131 page_cache_release(obj_priv->pages[i]);
2133 drm_free_large(obj_priv->pages);
2134 obj_priv->pages = NULL;
2135 obj_priv->pages_refcount--;
2136 return PTR_ERR(page);
2139 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2141 struct drm_gem_object *obj = reg->obj;
2142 struct drm_device *dev = obj->dev;
2143 drm_i915_private_t *dev_priv = dev->dev_private;
2144 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2145 int regnum = obj_priv->fence_reg;
2148 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2150 val |= obj_priv->gtt_offset & 0xfffff000;
2151 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2152 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2154 if (obj_priv->tiling_mode == I915_TILING_Y)
2155 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2156 val |= I965_FENCE_REG_VALID;
2158 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2161 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2163 struct drm_gem_object *obj = reg->obj;
2164 struct drm_device *dev = obj->dev;
2165 drm_i915_private_t *dev_priv = dev->dev_private;
2166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2167 int regnum = obj_priv->fence_reg;
2170 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2172 val |= obj_priv->gtt_offset & 0xfffff000;
2173 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2174 if (obj_priv->tiling_mode == I915_TILING_Y)
2175 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2176 val |= I965_FENCE_REG_VALID;
2178 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2181 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2183 struct drm_gem_object *obj = reg->obj;
2184 struct drm_device *dev = obj->dev;
2185 drm_i915_private_t *dev_priv = dev->dev_private;
2186 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2187 int regnum = obj_priv->fence_reg;
2189 uint32_t fence_reg, val;
2192 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2193 (obj_priv->gtt_offset & (obj->size - 1))) {
2194 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2195 __func__, obj_priv->gtt_offset, obj->size);
2199 if (obj_priv->tiling_mode == I915_TILING_Y &&
2200 HAS_128_BYTE_Y_TILING(dev))
2205 /* Note: pitch better be a power of two tile widths */
2206 pitch_val = obj_priv->stride / tile_width;
2207 pitch_val = ffs(pitch_val) - 1;
2209 if (obj_priv->tiling_mode == I915_TILING_Y &&
2210 HAS_128_BYTE_Y_TILING(dev))
2211 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2213 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2215 val = obj_priv->gtt_offset;
2216 if (obj_priv->tiling_mode == I915_TILING_Y)
2217 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2218 val |= I915_FENCE_SIZE_BITS(obj->size);
2219 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2220 val |= I830_FENCE_REG_VALID;
2223 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2225 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2226 I915_WRITE(fence_reg, val);
2229 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2231 struct drm_gem_object *obj = reg->obj;
2232 struct drm_device *dev = obj->dev;
2233 drm_i915_private_t *dev_priv = dev->dev_private;
2234 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2235 int regnum = obj_priv->fence_reg;
2238 uint32_t fence_size_bits;
2240 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2241 (obj_priv->gtt_offset & (obj->size - 1))) {
2242 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2243 __func__, obj_priv->gtt_offset);
2247 pitch_val = obj_priv->stride / 128;
2248 pitch_val = ffs(pitch_val) - 1;
2249 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2251 val = obj_priv->gtt_offset;
2252 if (obj_priv->tiling_mode == I915_TILING_Y)
2253 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2254 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2255 WARN_ON(fence_size_bits & ~0x00000f00);
2256 val |= fence_size_bits;
2257 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2258 val |= I830_FENCE_REG_VALID;
2260 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2263 static int i915_find_fence_reg(struct drm_device *dev)
2265 struct drm_i915_fence_reg *reg = NULL;
2266 struct drm_i915_gem_object *obj_priv = NULL;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct drm_gem_object *obj = NULL;
2271 /* First try to find a free reg */
2273 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2274 reg = &dev_priv->fence_regs[i];
2278 obj_priv = to_intel_bo(reg->obj);
2279 if (!obj_priv->pin_count)
2286 /* None available, try to steal one or wait for a user to finish */
2287 i = I915_FENCE_REG_NONE;
2288 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2291 obj_priv = to_intel_bo(obj);
2293 if (obj_priv->pin_count)
2297 i = obj_priv->fence_reg;
2301 BUG_ON(i == I915_FENCE_REG_NONE);
2303 /* We only have a reference on obj from the active list. put_fence_reg
2304 * might drop that one, causing a use-after-free in it. So hold a
2305 * private reference to obj like the other callers of put_fence_reg
2306 * (set_tiling ioctl) do. */
2307 drm_gem_object_reference(obj);
2308 ret = i915_gem_object_put_fence_reg(obj);
2309 drm_gem_object_unreference(obj);
2317 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2318 * @obj: object to map through a fence reg
2320 * When mapping objects through the GTT, userspace wants to be able to write
2321 * to them without having to worry about swizzling if the object is tiled.
2323 * This function walks the fence regs looking for a free one for @obj,
2324 * stealing one if it can't find any.
2326 * It then sets up the reg based on the object's properties: address, pitch
2327 * and tiling format.
2330 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2332 struct drm_device *dev = obj->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2335 struct drm_i915_fence_reg *reg = NULL;
2338 /* Just update our place in the LRU if our fence is getting used. */
2339 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2340 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2341 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2345 switch (obj_priv->tiling_mode) {
2346 case I915_TILING_NONE:
2347 WARN(1, "allocating a fence for non-tiled object?\n");
2350 if (!obj_priv->stride)
2352 WARN((obj_priv->stride & (512 - 1)),
2353 "object 0x%08x is X tiled but has non-512B pitch\n",
2354 obj_priv->gtt_offset);
2357 if (!obj_priv->stride)
2359 WARN((obj_priv->stride & (128 - 1)),
2360 "object 0x%08x is Y tiled but has non-128B pitch\n",
2361 obj_priv->gtt_offset);
2365 ret = i915_find_fence_reg(dev);
2369 obj_priv->fence_reg = ret;
2370 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2371 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2376 sandybridge_write_fence_reg(reg);
2377 else if (IS_I965G(dev))
2378 i965_write_fence_reg(reg);
2379 else if (IS_I9XX(dev))
2380 i915_write_fence_reg(reg);
2382 i830_write_fence_reg(reg);
2384 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2385 obj_priv->tiling_mode);
2391 * i915_gem_clear_fence_reg - clear out fence register info
2392 * @obj: object to clear
2394 * Zeroes out the fence register itself and clears out the associated
2395 * data structures in dev_priv and obj_priv.
2398 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2400 struct drm_device *dev = obj->dev;
2401 drm_i915_private_t *dev_priv = dev->dev_private;
2402 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2403 struct drm_i915_fence_reg *reg =
2404 &dev_priv->fence_regs[obj_priv->fence_reg];
2407 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2408 (obj_priv->fence_reg * 8), 0);
2409 } else if (IS_I965G(dev)) {
2410 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2414 if (obj_priv->fence_reg < 8)
2415 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2417 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2420 I915_WRITE(fence_reg, 0);
2424 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2425 list_del_init(®->lru_list);
2429 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2430 * to the buffer to finish, and then resets the fence register.
2431 * @obj: tiled object holding a fence register.
2433 * Zeroes out the fence register itself and clears out the associated
2434 * data structures in dev_priv and obj_priv.
2437 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2439 struct drm_device *dev = obj->dev;
2440 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2442 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2445 /* If we've changed tiling, GTT-mappings of the object
2446 * need to re-fault to ensure that the correct fence register
2447 * setup is in place.
2449 i915_gem_release_mmap(obj);
2451 /* On the i915, GPU access to tiled buffers is via a fence,
2452 * therefore we must wait for any outstanding access to complete
2453 * before clearing the fence.
2455 if (!IS_I965G(dev)) {
2458 ret = i915_gem_object_flush_gpu_write_domain(obj);
2462 ret = i915_gem_object_wait_rendering(obj, true);
2467 i915_gem_object_flush_gtt_write_domain(obj);
2468 i915_gem_clear_fence_reg (obj);
2474 * Finds free space in the GTT aperture and binds the object there.
2477 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2479 struct drm_device *dev = obj->dev;
2480 drm_i915_private_t *dev_priv = dev->dev_private;
2481 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2482 struct drm_mm_node *free_space;
2483 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2486 if (obj_priv->madv != I915_MADV_WILLNEED) {
2487 DRM_ERROR("Attempting to bind a purgeable object\n");
2492 alignment = i915_gem_get_gtt_alignment(obj);
2493 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2494 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2498 /* If the object is bigger than the entire aperture, reject it early
2499 * before evicting everything in a vain attempt to find space.
2501 if (obj->size > dev->gtt_total) {
2502 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2507 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2508 obj->size, alignment, 0);
2509 if (free_space != NULL) {
2510 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2512 if (obj_priv->gtt_space != NULL)
2513 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2515 if (obj_priv->gtt_space == NULL) {
2516 /* If the gtt is empty and we're still having trouble
2517 * fitting our object in, we're out of memory.
2520 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2522 ret = i915_gem_evict_something(dev, obj->size, alignment);
2530 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2531 obj->size, obj_priv->gtt_offset);
2533 ret = i915_gem_object_get_pages(obj, gfpmask);
2535 drm_mm_put_block(obj_priv->gtt_space);
2536 obj_priv->gtt_space = NULL;
2538 if (ret == -ENOMEM) {
2539 /* first try to clear up some space from the GTT */
2540 ret = i915_gem_evict_something(dev, obj->size,
2543 /* now try to shrink everyone else */
2558 /* Create an AGP memory structure pointing at our pages, and bind it
2561 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2563 obj->size >> PAGE_SHIFT,
2564 obj_priv->gtt_offset,
2565 obj_priv->agp_type);
2566 if (obj_priv->agp_mem == NULL) {
2567 i915_gem_object_put_pages(obj);
2568 drm_mm_put_block(obj_priv->gtt_space);
2569 obj_priv->gtt_space = NULL;
2571 ret = i915_gem_evict_something(dev, obj->size, alignment);
2577 atomic_inc(&dev->gtt_count);
2578 atomic_add(obj->size, &dev->gtt_memory);
2580 /* keep track of bounds object by adding it to the inactive list */
2581 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2583 /* Assert that the object is not currently in any GPU domain. As it
2584 * wasn't in the GTT, there shouldn't be any way it could have been in
2587 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2588 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2590 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2596 i915_gem_clflush_object(struct drm_gem_object *obj)
2598 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2600 /* If we don't have a page list set up, then we're not pinned
2601 * to GPU, and we can ignore the cache flush because it'll happen
2602 * again at bind time.
2604 if (obj_priv->pages == NULL)
2607 trace_i915_gem_object_clflush(obj);
2609 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2612 /** Flushes any GPU write domain for the object if it's dirty. */
2614 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2616 struct drm_device *dev = obj->dev;
2617 uint32_t old_write_domain;
2618 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2620 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2623 /* Queue the GPU write cache flushing we need. */
2624 old_write_domain = obj->write_domain;
2625 i915_gem_flush(dev, 0, obj->write_domain);
2626 if (i915_add_request(dev, NULL, obj_priv->ring) == 0)
2629 trace_i915_gem_object_change_domain(obj,
2635 /** Flushes the GTT write domain for the object if it's dirty. */
2637 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2639 uint32_t old_write_domain;
2641 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2644 /* No actual flushing is required for the GTT write domain. Writes
2645 * to it immediately go to main memory as far as we know, so there's
2646 * no chipset flush. It also doesn't land in render cache.
2648 old_write_domain = obj->write_domain;
2649 obj->write_domain = 0;
2651 trace_i915_gem_object_change_domain(obj,
2656 /** Flushes the CPU write domain for the object if it's dirty. */
2658 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2660 struct drm_device *dev = obj->dev;
2661 uint32_t old_write_domain;
2663 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2666 i915_gem_clflush_object(obj);
2667 drm_agp_chipset_flush(dev);
2668 old_write_domain = obj->write_domain;
2669 obj->write_domain = 0;
2671 trace_i915_gem_object_change_domain(obj,
2677 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2681 switch (obj->write_domain) {
2682 case I915_GEM_DOMAIN_GTT:
2683 i915_gem_object_flush_gtt_write_domain(obj);
2685 case I915_GEM_DOMAIN_CPU:
2686 i915_gem_object_flush_cpu_write_domain(obj);
2689 ret = i915_gem_object_flush_gpu_write_domain(obj);
2697 * Moves a single object to the GTT read, and possibly write domain.
2699 * This function returns when the move is complete, including waiting on
2703 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2705 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2706 uint32_t old_write_domain, old_read_domains;
2709 /* Not valid to be called on unbound objects. */
2710 if (obj_priv->gtt_space == NULL)
2713 ret = i915_gem_object_flush_gpu_write_domain(obj);
2717 /* Wait on any GPU rendering and flushing to occur. */
2718 ret = i915_gem_object_wait_rendering(obj, true);
2722 old_write_domain = obj->write_domain;
2723 old_read_domains = obj->read_domains;
2725 /* If we're writing through the GTT domain, then CPU and GPU caches
2726 * will need to be invalidated at next use.
2729 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2731 i915_gem_object_flush_cpu_write_domain(obj);
2733 /* It should now be out of any other write domains, and we can update
2734 * the domain values for our changes.
2736 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2737 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2739 obj->write_domain = I915_GEM_DOMAIN_GTT;
2740 obj_priv->dirty = 1;
2743 trace_i915_gem_object_change_domain(obj,
2751 * Prepare buffer for display plane. Use uninterruptible for possible flush
2752 * wait, as in modesetting process we're not supposed to be interrupted.
2755 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2757 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2758 uint32_t old_write_domain, old_read_domains;
2761 /* Not valid to be called on unbound objects. */
2762 if (obj_priv->gtt_space == NULL)
2765 ret = i915_gem_object_flush_gpu_write_domain(obj);
2769 /* Wait on any GPU rendering and flushing to occur. */
2770 ret = i915_gem_object_wait_rendering(obj, false);
2774 i915_gem_object_flush_cpu_write_domain(obj);
2776 old_write_domain = obj->write_domain;
2777 old_read_domains = obj->read_domains;
2779 /* It should now be out of any other write domains, and we can update
2780 * the domain values for our changes.
2782 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2783 obj->read_domains = I915_GEM_DOMAIN_GTT;
2784 obj->write_domain = I915_GEM_DOMAIN_GTT;
2785 obj_priv->dirty = 1;
2787 trace_i915_gem_object_change_domain(obj,
2795 * Moves a single object to the CPU read, and possibly write domain.
2797 * This function returns when the move is complete, including waiting on
2801 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2803 uint32_t old_write_domain, old_read_domains;
2806 ret = i915_gem_object_flush_gpu_write_domain(obj);
2810 /* Wait on any GPU rendering and flushing to occur. */
2811 ret = i915_gem_object_wait_rendering(obj, true);
2815 i915_gem_object_flush_gtt_write_domain(obj);
2817 /* If we have a partially-valid cache of the object in the CPU,
2818 * finish invalidating it and free the per-page flags.
2820 i915_gem_object_set_to_full_cpu_read_domain(obj);
2822 old_write_domain = obj->write_domain;
2823 old_read_domains = obj->read_domains;
2825 /* Flush the CPU cache if it's still invalid. */
2826 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2827 i915_gem_clflush_object(obj);
2829 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2832 /* It should now be out of any other write domains, and we can update
2833 * the domain values for our changes.
2835 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2837 /* If we're writing through the CPU, then the GPU read domains will
2838 * need to be invalidated at next use.
2841 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2842 obj->write_domain = I915_GEM_DOMAIN_CPU;
2845 trace_i915_gem_object_change_domain(obj,
2853 * Set the next domain for the specified object. This
2854 * may not actually perform the necessary flushing/invaliding though,
2855 * as that may want to be batched with other set_domain operations
2857 * This is (we hope) the only really tricky part of gem. The goal
2858 * is fairly simple -- track which caches hold bits of the object
2859 * and make sure they remain coherent. A few concrete examples may
2860 * help to explain how it works. For shorthand, we use the notation
2861 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2862 * a pair of read and write domain masks.
2864 * Case 1: the batch buffer
2870 * 5. Unmapped from GTT
2873 * Let's take these a step at a time
2876 * Pages allocated from the kernel may still have
2877 * cache contents, so we set them to (CPU, CPU) always.
2878 * 2. Written by CPU (using pwrite)
2879 * The pwrite function calls set_domain (CPU, CPU) and
2880 * this function does nothing (as nothing changes)
2882 * This function asserts that the object is not
2883 * currently in any GPU-based read or write domains
2885 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2886 * As write_domain is zero, this function adds in the
2887 * current read domains (CPU+COMMAND, 0).
2888 * flush_domains is set to CPU.
2889 * invalidate_domains is set to COMMAND
2890 * clflush is run to get data out of the CPU caches
2891 * then i915_dev_set_domain calls i915_gem_flush to
2892 * emit an MI_FLUSH and drm_agp_chipset_flush
2893 * 5. Unmapped from GTT
2894 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2895 * flush_domains and invalidate_domains end up both zero
2896 * so no flushing/invalidating happens
2900 * Case 2: The shared render buffer
2904 * 3. Read/written by GPU
2905 * 4. set_domain to (CPU,CPU)
2906 * 5. Read/written by CPU
2907 * 6. Read/written by GPU
2910 * Same as last example, (CPU, CPU)
2912 * Nothing changes (assertions find that it is not in the GPU)
2913 * 3. Read/written by GPU
2914 * execbuffer calls set_domain (RENDER, RENDER)
2915 * flush_domains gets CPU
2916 * invalidate_domains gets GPU
2918 * MI_FLUSH and drm_agp_chipset_flush
2919 * 4. set_domain (CPU, CPU)
2920 * flush_domains gets GPU
2921 * invalidate_domains gets CPU
2922 * wait_rendering (obj) to make sure all drawing is complete.
2923 * This will include an MI_FLUSH to get the data from GPU
2925 * clflush (obj) to invalidate the CPU cache
2926 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2927 * 5. Read/written by CPU
2928 * cache lines are loaded and dirtied
2929 * 6. Read written by GPU
2930 * Same as last GPU access
2932 * Case 3: The constant buffer
2937 * 4. Updated (written) by CPU again
2946 * flush_domains = CPU
2947 * invalidate_domains = RENDER
2950 * drm_agp_chipset_flush
2951 * 4. Updated (written) by CPU again
2953 * flush_domains = 0 (no previous write domain)
2954 * invalidate_domains = 0 (no new read domains)
2957 * flush_domains = CPU
2958 * invalidate_domains = RENDER
2961 * drm_agp_chipset_flush
2964 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2966 struct drm_device *dev = obj->dev;
2967 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2968 uint32_t invalidate_domains = 0;
2969 uint32_t flush_domains = 0;
2970 uint32_t old_read_domains;
2972 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2973 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2975 intel_mark_busy(dev, obj);
2978 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2980 obj->read_domains, obj->pending_read_domains,
2981 obj->write_domain, obj->pending_write_domain);
2984 * If the object isn't moving to a new write domain,
2985 * let the object stay in multiple read domains
2987 if (obj->pending_write_domain == 0)
2988 obj->pending_read_domains |= obj->read_domains;
2990 obj_priv->dirty = 1;
2993 * Flush the current write domain if
2994 * the new read domains don't match. Invalidate
2995 * any read domains which differ from the old
2998 if (obj->write_domain &&
2999 obj->write_domain != obj->pending_read_domains) {
3000 flush_domains |= obj->write_domain;
3001 invalidate_domains |=
3002 obj->pending_read_domains & ~obj->write_domain;
3005 * Invalidate any read caches which may have
3006 * stale data. That is, any new read domains.
3008 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3009 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3011 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3012 __func__, flush_domains, invalidate_domains);
3014 i915_gem_clflush_object(obj);
3017 old_read_domains = obj->read_domains;
3019 /* The actual obj->write_domain will be updated with
3020 * pending_write_domain after we emit the accumulated flush for all
3021 * of our domain changes in execbuffers (which clears objects'
3022 * write_domains). So if we have a current write domain that we
3023 * aren't changing, set pending_write_domain to that.
3025 if (flush_domains == 0 && obj->pending_write_domain == 0)
3026 obj->pending_write_domain = obj->write_domain;
3027 obj->read_domains = obj->pending_read_domains;
3029 dev->invalidate_domains |= invalidate_domains;
3030 dev->flush_domains |= flush_domains;
3032 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3034 obj->read_domains, obj->write_domain,
3035 dev->invalidate_domains, dev->flush_domains);
3038 trace_i915_gem_object_change_domain(obj,
3044 * Moves the object from a partially CPU read to a full one.
3046 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3047 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3050 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3052 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3054 if (!obj_priv->page_cpu_valid)
3057 /* If we're partially in the CPU read domain, finish moving it in.
3059 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3062 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3063 if (obj_priv->page_cpu_valid[i])
3065 drm_clflush_pages(obj_priv->pages + i, 1);
3069 /* Free the page_cpu_valid mappings which are now stale, whether
3070 * or not we've got I915_GEM_DOMAIN_CPU.
3072 kfree(obj_priv->page_cpu_valid);
3073 obj_priv->page_cpu_valid = NULL;
3077 * Set the CPU read domain on a range of the object.
3079 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3080 * not entirely valid. The page_cpu_valid member of the object flags which
3081 * pages have been flushed, and will be respected by
3082 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3083 * of the whole object.
3085 * This function returns when the move is complete, including waiting on
3089 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3090 uint64_t offset, uint64_t size)
3092 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3093 uint32_t old_read_domains;
3096 if (offset == 0 && size == obj->size)
3097 return i915_gem_object_set_to_cpu_domain(obj, 0);
3099 ret = i915_gem_object_flush_gpu_write_domain(obj);
3103 /* Wait on any GPU rendering and flushing to occur. */
3104 ret = i915_gem_object_wait_rendering(obj, true);
3107 i915_gem_object_flush_gtt_write_domain(obj);
3109 /* If we're already fully in the CPU read domain, we're done. */
3110 if (obj_priv->page_cpu_valid == NULL &&
3111 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3114 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3115 * newly adding I915_GEM_DOMAIN_CPU
3117 if (obj_priv->page_cpu_valid == NULL) {
3118 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3120 if (obj_priv->page_cpu_valid == NULL)
3122 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3123 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3125 /* Flush the cache on any pages that are still invalid from the CPU's
3128 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3130 if (obj_priv->page_cpu_valid[i])
3133 drm_clflush_pages(obj_priv->pages + i, 1);
3135 obj_priv->page_cpu_valid[i] = 1;
3138 /* It should now be out of any other write domains, and we can update
3139 * the domain values for our changes.
3141 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3143 old_read_domains = obj->read_domains;
3144 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3146 trace_i915_gem_object_change_domain(obj,
3154 * Pin an object to the GTT and evaluate the relocations landing in it.
3157 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3158 struct drm_file *file_priv,
3159 struct drm_i915_gem_exec_object2 *entry,
3160 struct drm_i915_gem_relocation_entry *relocs)
3162 struct drm_device *dev = obj->dev;
3163 drm_i915_private_t *dev_priv = dev->dev_private;
3164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3166 void __iomem *reloc_page;
3169 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3170 obj_priv->tiling_mode != I915_TILING_NONE;
3172 /* Check fence reg constraints and rebind if necessary */
3174 !i915_gem_object_fence_offset_ok(obj,
3175 obj_priv->tiling_mode)) {
3176 ret = i915_gem_object_unbind(obj);
3181 /* Choose the GTT offset for our buffer and put it there. */
3182 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3187 * Pre-965 chips need a fence register set up in order to
3188 * properly handle blits to/from tiled surfaces.
3191 ret = i915_gem_object_get_fence_reg(obj);
3193 i915_gem_object_unpin(obj);
3198 entry->offset = obj_priv->gtt_offset;
3200 /* Apply the relocations, using the GTT aperture to avoid cache
3201 * flushing requirements.
3203 for (i = 0; i < entry->relocation_count; i++) {
3204 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3205 struct drm_gem_object *target_obj;
3206 struct drm_i915_gem_object *target_obj_priv;
3207 uint32_t reloc_val, reloc_offset;
3208 uint32_t __iomem *reloc_entry;
3210 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3211 reloc->target_handle);
3212 if (target_obj == NULL) {
3213 i915_gem_object_unpin(obj);
3216 target_obj_priv = to_intel_bo(target_obj);
3219 DRM_INFO("%s: obj %p offset %08x target %d "
3220 "read %08x write %08x gtt %08x "
3221 "presumed %08x delta %08x\n",
3224 (int) reloc->offset,
3225 (int) reloc->target_handle,
3226 (int) reloc->read_domains,
3227 (int) reloc->write_domain,
3228 (int) target_obj_priv->gtt_offset,
3229 (int) reloc->presumed_offset,
3233 /* The target buffer should have appeared before us in the
3234 * exec_object list, so it should have a GTT space bound by now.
3236 if (target_obj_priv->gtt_space == NULL) {
3237 DRM_ERROR("No GTT space found for object %d\n",
3238 reloc->target_handle);
3239 drm_gem_object_unreference(target_obj);
3240 i915_gem_object_unpin(obj);
3244 /* Validate that the target is in a valid r/w GPU domain */
3245 if (reloc->write_domain & (reloc->write_domain - 1)) {
3246 DRM_ERROR("reloc with multiple write domains: "
3247 "obj %p target %d offset %d "
3248 "read %08x write %08x",
3249 obj, reloc->target_handle,
3250 (int) reloc->offset,
3251 reloc->read_domains,
3252 reloc->write_domain);
3255 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3256 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3257 DRM_ERROR("reloc with read/write CPU domains: "
3258 "obj %p target %d offset %d "
3259 "read %08x write %08x",
3260 obj, reloc->target_handle,
3261 (int) reloc->offset,
3262 reloc->read_domains,
3263 reloc->write_domain);
3264 drm_gem_object_unreference(target_obj);
3265 i915_gem_object_unpin(obj);
3268 if (reloc->write_domain && target_obj->pending_write_domain &&
3269 reloc->write_domain != target_obj->pending_write_domain) {
3270 DRM_ERROR("Write domain conflict: "
3271 "obj %p target %d offset %d "
3272 "new %08x old %08x\n",
3273 obj, reloc->target_handle,
3274 (int) reloc->offset,
3275 reloc->write_domain,
3276 target_obj->pending_write_domain);
3277 drm_gem_object_unreference(target_obj);
3278 i915_gem_object_unpin(obj);
3282 target_obj->pending_read_domains |= reloc->read_domains;
3283 target_obj->pending_write_domain |= reloc->write_domain;
3285 /* If the relocation already has the right value in it, no
3286 * more work needs to be done.
3288 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3289 drm_gem_object_unreference(target_obj);
3293 /* Check that the relocation address is valid... */
3294 if (reloc->offset > obj->size - 4) {
3295 DRM_ERROR("Relocation beyond object bounds: "
3296 "obj %p target %d offset %d size %d.\n",
3297 obj, reloc->target_handle,
3298 (int) reloc->offset, (int) obj->size);
3299 drm_gem_object_unreference(target_obj);
3300 i915_gem_object_unpin(obj);
3303 if (reloc->offset & 3) {
3304 DRM_ERROR("Relocation not 4-byte aligned: "
3305 "obj %p target %d offset %d.\n",
3306 obj, reloc->target_handle,
3307 (int) reloc->offset);
3308 drm_gem_object_unreference(target_obj);
3309 i915_gem_object_unpin(obj);
3313 /* and points to somewhere within the target object. */
3314 if (reloc->delta >= target_obj->size) {
3315 DRM_ERROR("Relocation beyond target object bounds: "
3316 "obj %p target %d delta %d size %d.\n",
3317 obj, reloc->target_handle,
3318 (int) reloc->delta, (int) target_obj->size);
3319 drm_gem_object_unreference(target_obj);
3320 i915_gem_object_unpin(obj);
3324 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3326 drm_gem_object_unreference(target_obj);
3327 i915_gem_object_unpin(obj);
3331 /* Map the page containing the relocation we're going to
3334 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3335 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3339 reloc_entry = (uint32_t __iomem *)(reloc_page +
3340 (reloc_offset & (PAGE_SIZE - 1)));
3341 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3344 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3345 obj, (unsigned int) reloc->offset,
3346 readl(reloc_entry), reloc_val);
3348 writel(reloc_val, reloc_entry);
3349 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3351 /* The updated presumed offset for this entry will be
3352 * copied back out to the user.
3354 reloc->presumed_offset = target_obj_priv->gtt_offset;
3356 drm_gem_object_unreference(target_obj);
3361 i915_gem_dump_object(obj, 128, __func__, ~0);
3366 /* Throttle our rendering by waiting until the ring has completed our requests
3367 * emitted over 20 msec ago.
3369 * Note that if we were to use the current jiffies each time around the loop,
3370 * we wouldn't escape the function with any frames outstanding if the time to
3371 * render a frame was over 20ms.
3373 * This should get us reasonable parallelism between CPU and GPU but also
3374 * relatively low latency when blocking on a particular request to finish.
3377 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3379 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3381 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3383 mutex_lock(&dev->struct_mutex);
3384 while (!list_empty(&i915_file_priv->mm.request_list)) {
3385 struct drm_i915_gem_request *request;
3387 request = list_first_entry(&i915_file_priv->mm.request_list,
3388 struct drm_i915_gem_request,
3391 if (time_after_eq(request->emitted_jiffies, recent_enough))
3394 ret = i915_wait_request(dev, request->seqno, request->ring);
3398 mutex_unlock(&dev->struct_mutex);
3404 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3405 uint32_t buffer_count,
3406 struct drm_i915_gem_relocation_entry **relocs)
3408 uint32_t reloc_count = 0, reloc_index = 0, i;
3412 for (i = 0; i < buffer_count; i++) {
3413 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3415 reloc_count += exec_list[i].relocation_count;
3418 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3419 if (*relocs == NULL) {
3420 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3424 for (i = 0; i < buffer_count; i++) {
3425 struct drm_i915_gem_relocation_entry __user *user_relocs;
3427 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3429 ret = copy_from_user(&(*relocs)[reloc_index],
3431 exec_list[i].relocation_count *
3434 drm_free_large(*relocs);
3439 reloc_index += exec_list[i].relocation_count;
3446 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3447 uint32_t buffer_count,
3448 struct drm_i915_gem_relocation_entry *relocs)
3450 uint32_t reloc_count = 0, i;
3456 for (i = 0; i < buffer_count; i++) {
3457 struct drm_i915_gem_relocation_entry __user *user_relocs;
3460 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3462 unwritten = copy_to_user(user_relocs,
3463 &relocs[reloc_count],
3464 exec_list[i].relocation_count *
3472 reloc_count += exec_list[i].relocation_count;
3476 drm_free_large(relocs);
3482 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3483 uint64_t exec_offset)
3485 uint32_t exec_start, exec_len;
3487 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3488 exec_len = (uint32_t) exec->batch_len;
3490 if ((exec_start | exec_len) & 0x7)
3500 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3501 struct drm_gem_object **object_list,
3504 drm_i915_private_t *dev_priv = dev->dev_private;
3505 struct drm_i915_gem_object *obj_priv;
3510 prepare_to_wait(&dev_priv->pending_flip_queue,
3511 &wait, TASK_INTERRUPTIBLE);
3512 for (i = 0; i < count; i++) {
3513 obj_priv = to_intel_bo(object_list[i]);
3514 if (atomic_read(&obj_priv->pending_flip) > 0)
3520 if (!signal_pending(current)) {
3521 mutex_unlock(&dev->struct_mutex);
3523 mutex_lock(&dev->struct_mutex);
3529 finish_wait(&dev_priv->pending_flip_queue, &wait);
3536 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3537 struct drm_file *file_priv,
3538 struct drm_i915_gem_execbuffer2 *args,
3539 struct drm_i915_gem_exec_object2 *exec_list)
3541 drm_i915_private_t *dev_priv = dev->dev_private;
3542 struct drm_gem_object **object_list = NULL;
3543 struct drm_gem_object *batch_obj;
3544 struct drm_i915_gem_object *obj_priv;
3545 struct drm_clip_rect *cliprects = NULL;
3546 struct drm_i915_gem_relocation_entry *relocs = NULL;
3547 int ret = 0, ret2, i, pinned = 0;
3548 uint64_t exec_offset;
3549 uint32_t seqno, reloc_index;
3550 int pin_tries, flips;
3552 struct intel_ring_buffer *ring = NULL;
3555 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3556 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3558 if (args->flags & I915_EXEC_BSD) {
3559 if (!HAS_BSD(dev)) {
3560 DRM_ERROR("execbuf with wrong flag\n");
3563 ring = &dev_priv->bsd_ring;
3565 ring = &dev_priv->render_ring;
3568 if (args->buffer_count < 1) {
3569 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3572 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3573 if (object_list == NULL) {
3574 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3575 args->buffer_count);
3580 if (args->num_cliprects != 0) {
3581 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3583 if (cliprects == NULL) {
3588 ret = copy_from_user(cliprects,
3589 (struct drm_clip_rect __user *)
3590 (uintptr_t) args->cliprects_ptr,
3591 sizeof(*cliprects) * args->num_cliprects);
3593 DRM_ERROR("copy %d cliprects failed: %d\n",
3594 args->num_cliprects, ret);
3600 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3605 mutex_lock(&dev->struct_mutex);
3607 i915_verify_inactive(dev, __FILE__, __LINE__);
3609 if (atomic_read(&dev_priv->mm.wedged)) {
3610 mutex_unlock(&dev->struct_mutex);
3615 if (dev_priv->mm.suspended) {
3616 mutex_unlock(&dev->struct_mutex);
3621 /* Look up object handles */
3623 for (i = 0; i < args->buffer_count; i++) {
3624 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3625 exec_list[i].handle);
3626 if (object_list[i] == NULL) {
3627 DRM_ERROR("Invalid object handle %d at index %d\n",
3628 exec_list[i].handle, i);
3629 /* prevent error path from reading uninitialized data */
3630 args->buffer_count = i + 1;
3635 obj_priv = to_intel_bo(object_list[i]);
3636 if (obj_priv->in_execbuffer) {
3637 DRM_ERROR("Object %p appears more than once in object list\n",
3639 /* prevent error path from reading uninitialized data */
3640 args->buffer_count = i + 1;
3644 obj_priv->in_execbuffer = true;
3645 flips += atomic_read(&obj_priv->pending_flip);
3649 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3650 args->buffer_count);
3655 /* Pin and relocate */
3656 for (pin_tries = 0; ; pin_tries++) {
3660 for (i = 0; i < args->buffer_count; i++) {
3661 object_list[i]->pending_read_domains = 0;
3662 object_list[i]->pending_write_domain = 0;
3663 ret = i915_gem_object_pin_and_relocate(object_list[i],
3666 &relocs[reloc_index]);
3670 reloc_index += exec_list[i].relocation_count;
3676 /* error other than GTT full, or we've already tried again */
3677 if (ret != -ENOSPC || pin_tries >= 1) {
3678 if (ret != -ERESTARTSYS) {
3679 unsigned long long total_size = 0;
3681 for (i = 0; i < args->buffer_count; i++) {
3682 obj_priv = to_intel_bo(object_list[i]);
3684 total_size += object_list[i]->size;
3686 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3687 obj_priv->tiling_mode != I915_TILING_NONE;
3689 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3690 pinned+1, args->buffer_count,
3691 total_size, num_fences,
3693 DRM_ERROR("%d objects [%d pinned], "
3694 "%d object bytes [%d pinned], "
3695 "%d/%d gtt bytes\n",
3696 atomic_read(&dev->object_count),
3697 atomic_read(&dev->pin_count),
3698 atomic_read(&dev->object_memory),
3699 atomic_read(&dev->pin_memory),
3700 atomic_read(&dev->gtt_memory),
3706 /* unpin all of our buffers */
3707 for (i = 0; i < pinned; i++)
3708 i915_gem_object_unpin(object_list[i]);
3711 /* evict everyone we can from the aperture */
3712 ret = i915_gem_evict_everything(dev);
3713 if (ret && ret != -ENOSPC)
3717 /* Set the pending read domains for the batch buffer to COMMAND */
3718 batch_obj = object_list[args->buffer_count-1];
3719 if (batch_obj->pending_write_domain) {
3720 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3724 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3726 /* Sanity check the batch buffer, prior to moving objects */
3727 exec_offset = exec_list[args->buffer_count - 1].offset;
3728 ret = i915_gem_check_execbuffer (args, exec_offset);
3730 DRM_ERROR("execbuf with invalid offset/length\n");
3734 i915_verify_inactive(dev, __FILE__, __LINE__);
3736 /* Zero the global flush/invalidate flags. These
3737 * will be modified as new domains are computed
3740 dev->invalidate_domains = 0;
3741 dev->flush_domains = 0;
3743 for (i = 0; i < args->buffer_count; i++) {
3744 struct drm_gem_object *obj = object_list[i];
3746 /* Compute new gpu domains and update invalidate/flush */
3747 i915_gem_object_set_to_gpu_domain(obj);
3750 i915_verify_inactive(dev, __FILE__, __LINE__);
3752 if (dev->invalidate_domains | dev->flush_domains) {
3754 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3756 dev->invalidate_domains,
3757 dev->flush_domains);
3760 dev->invalidate_domains,
3761 dev->flush_domains);
3764 if (dev_priv->render_ring.outstanding_lazy_request) {
3765 (void)i915_add_request(dev, file_priv, &dev_priv->render_ring);
3766 dev_priv->render_ring.outstanding_lazy_request = false;
3768 if (dev_priv->bsd_ring.outstanding_lazy_request) {
3769 (void)i915_add_request(dev, file_priv, &dev_priv->bsd_ring);
3770 dev_priv->bsd_ring.outstanding_lazy_request = false;
3773 for (i = 0; i < args->buffer_count; i++) {
3774 struct drm_gem_object *obj = object_list[i];
3775 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3776 uint32_t old_write_domain = obj->write_domain;
3778 obj->write_domain = obj->pending_write_domain;
3779 if (obj->write_domain)
3780 list_move_tail(&obj_priv->gpu_write_list,
3781 &dev_priv->mm.gpu_write_list);
3783 list_del_init(&obj_priv->gpu_write_list);
3785 trace_i915_gem_object_change_domain(obj,
3790 i915_verify_inactive(dev, __FILE__, __LINE__);
3793 for (i = 0; i < args->buffer_count; i++) {
3794 i915_gem_object_check_coherency(object_list[i],
3795 exec_list[i].handle);
3800 i915_gem_dump_object(batch_obj,
3806 /* Exec the batchbuffer */
3807 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3808 cliprects, exec_offset);
3810 DRM_ERROR("dispatch failed %d\n", ret);
3815 * Ensure that the commands in the batch buffer are
3816 * finished before the interrupt fires
3818 i915_retire_commands(dev, ring);
3820 i915_verify_inactive(dev, __FILE__, __LINE__);
3823 * Get a seqno representing the execution of the current buffer,
3824 * which we can wait on. We would like to mitigate these interrupts,
3825 * likely by only creating seqnos occasionally (so that we have
3826 * *some* interrupts representing completion of buffers that we can
3827 * wait on when trying to clear up gtt space).
3829 seqno = i915_add_request(dev, file_priv, ring);
3830 for (i = 0; i < args->buffer_count; i++) {
3831 struct drm_gem_object *obj = object_list[i];
3832 obj_priv = to_intel_bo(obj);
3834 i915_gem_object_move_to_active(obj, seqno, ring);
3836 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3840 i915_dump_lru(dev, __func__);
3843 i915_verify_inactive(dev, __FILE__, __LINE__);
3846 for (i = 0; i < pinned; i++)
3847 i915_gem_object_unpin(object_list[i]);
3849 for (i = 0; i < args->buffer_count; i++) {
3850 if (object_list[i]) {
3851 obj_priv = to_intel_bo(object_list[i]);
3852 obj_priv->in_execbuffer = false;
3854 drm_gem_object_unreference(object_list[i]);
3857 mutex_unlock(&dev->struct_mutex);
3860 /* Copy the updated relocations out regardless of current error
3861 * state. Failure to update the relocs would mean that the next
3862 * time userland calls execbuf, it would do so with presumed offset
3863 * state that didn't match the actual object state.
3865 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3868 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3874 drm_free_large(object_list);
3881 * Legacy execbuffer just creates an exec2 list from the original exec object
3882 * list array and passes it to the real function.
3885 i915_gem_execbuffer(struct drm_device *dev, void *data,
3886 struct drm_file *file_priv)
3888 struct drm_i915_gem_execbuffer *args = data;
3889 struct drm_i915_gem_execbuffer2 exec2;
3890 struct drm_i915_gem_exec_object *exec_list = NULL;
3891 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3895 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3896 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3899 if (args->buffer_count < 1) {
3900 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3904 /* Copy in the exec list from userland */
3905 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3906 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3907 if (exec_list == NULL || exec2_list == NULL) {
3908 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3909 args->buffer_count);
3910 drm_free_large(exec_list);
3911 drm_free_large(exec2_list);
3914 ret = copy_from_user(exec_list,
3915 (struct drm_i915_relocation_entry __user *)
3916 (uintptr_t) args->buffers_ptr,
3917 sizeof(*exec_list) * args->buffer_count);
3919 DRM_ERROR("copy %d exec entries failed %d\n",
3920 args->buffer_count, ret);
3921 drm_free_large(exec_list);
3922 drm_free_large(exec2_list);
3926 for (i = 0; i < args->buffer_count; i++) {
3927 exec2_list[i].handle = exec_list[i].handle;
3928 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3929 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3930 exec2_list[i].alignment = exec_list[i].alignment;
3931 exec2_list[i].offset = exec_list[i].offset;
3933 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3935 exec2_list[i].flags = 0;
3938 exec2.buffers_ptr = args->buffers_ptr;
3939 exec2.buffer_count = args->buffer_count;
3940 exec2.batch_start_offset = args->batch_start_offset;
3941 exec2.batch_len = args->batch_len;
3942 exec2.DR1 = args->DR1;
3943 exec2.DR4 = args->DR4;
3944 exec2.num_cliprects = args->num_cliprects;
3945 exec2.cliprects_ptr = args->cliprects_ptr;
3946 exec2.flags = I915_EXEC_RENDER;
3948 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3950 /* Copy the new buffer offsets back to the user's exec list. */
3951 for (i = 0; i < args->buffer_count; i++)
3952 exec_list[i].offset = exec2_list[i].offset;
3953 /* ... and back out to userspace */
3954 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3955 (uintptr_t) args->buffers_ptr,
3957 sizeof(*exec_list) * args->buffer_count);
3960 DRM_ERROR("failed to copy %d exec entries "
3961 "back to user (%d)\n",
3962 args->buffer_count, ret);
3966 drm_free_large(exec_list);
3967 drm_free_large(exec2_list);
3972 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3973 struct drm_file *file_priv)
3975 struct drm_i915_gem_execbuffer2 *args = data;
3976 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3980 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3981 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3984 if (args->buffer_count < 1) {
3985 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3989 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3990 if (exec2_list == NULL) {
3991 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3992 args->buffer_count);
3995 ret = copy_from_user(exec2_list,
3996 (struct drm_i915_relocation_entry __user *)
3997 (uintptr_t) args->buffers_ptr,
3998 sizeof(*exec2_list) * args->buffer_count);
4000 DRM_ERROR("copy %d exec entries failed %d\n",
4001 args->buffer_count, ret);
4002 drm_free_large(exec2_list);
4006 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4008 /* Copy the new buffer offsets back to the user's exec list. */
4009 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4010 (uintptr_t) args->buffers_ptr,
4012 sizeof(*exec2_list) * args->buffer_count);
4015 DRM_ERROR("failed to copy %d exec entries "
4016 "back to user (%d)\n",
4017 args->buffer_count, ret);
4021 drm_free_large(exec2_list);
4026 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4028 struct drm_device *dev = obj->dev;
4029 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4032 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4034 i915_verify_inactive(dev, __FILE__, __LINE__);
4036 if (obj_priv->gtt_space != NULL) {
4038 alignment = i915_gem_get_gtt_alignment(obj);
4039 if (obj_priv->gtt_offset & (alignment - 1)) {
4040 WARN(obj_priv->pin_count,
4041 "bo is already pinned with incorrect alignment:"
4042 " offset=%x, req.alignment=%x\n",
4043 obj_priv->gtt_offset, alignment);
4044 ret = i915_gem_object_unbind(obj);
4050 if (obj_priv->gtt_space == NULL) {
4051 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4056 obj_priv->pin_count++;
4058 /* If the object is not active and not pending a flush,
4059 * remove it from the inactive list
4061 if (obj_priv->pin_count == 1) {
4062 atomic_inc(&dev->pin_count);
4063 atomic_add(obj->size, &dev->pin_memory);
4064 if (!obj_priv->active &&
4065 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4066 list_del_init(&obj_priv->list);
4068 i915_verify_inactive(dev, __FILE__, __LINE__);
4074 i915_gem_object_unpin(struct drm_gem_object *obj)
4076 struct drm_device *dev = obj->dev;
4077 drm_i915_private_t *dev_priv = dev->dev_private;
4078 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4080 i915_verify_inactive(dev, __FILE__, __LINE__);
4081 obj_priv->pin_count--;
4082 BUG_ON(obj_priv->pin_count < 0);
4083 BUG_ON(obj_priv->gtt_space == NULL);
4085 /* If the object is no longer pinned, and is
4086 * neither active nor being flushed, then stick it on
4089 if (obj_priv->pin_count == 0) {
4090 if (!obj_priv->active &&
4091 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4092 list_move_tail(&obj_priv->list,
4093 &dev_priv->mm.inactive_list);
4094 atomic_dec(&dev->pin_count);
4095 atomic_sub(obj->size, &dev->pin_memory);
4097 i915_verify_inactive(dev, __FILE__, __LINE__);
4101 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4102 struct drm_file *file_priv)
4104 struct drm_i915_gem_pin *args = data;
4105 struct drm_gem_object *obj;
4106 struct drm_i915_gem_object *obj_priv;
4109 mutex_lock(&dev->struct_mutex);
4111 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4113 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4115 mutex_unlock(&dev->struct_mutex);
4118 obj_priv = to_intel_bo(obj);
4120 if (obj_priv->madv != I915_MADV_WILLNEED) {
4121 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4122 drm_gem_object_unreference(obj);
4123 mutex_unlock(&dev->struct_mutex);
4127 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4128 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4130 drm_gem_object_unreference(obj);
4131 mutex_unlock(&dev->struct_mutex);
4135 obj_priv->user_pin_count++;
4136 obj_priv->pin_filp = file_priv;
4137 if (obj_priv->user_pin_count == 1) {
4138 ret = i915_gem_object_pin(obj, args->alignment);
4140 drm_gem_object_unreference(obj);
4141 mutex_unlock(&dev->struct_mutex);
4146 /* XXX - flush the CPU caches for pinned objects
4147 * as the X server doesn't manage domains yet
4149 i915_gem_object_flush_cpu_write_domain(obj);
4150 args->offset = obj_priv->gtt_offset;
4151 drm_gem_object_unreference(obj);
4152 mutex_unlock(&dev->struct_mutex);
4158 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4159 struct drm_file *file_priv)
4161 struct drm_i915_gem_pin *args = data;
4162 struct drm_gem_object *obj;
4163 struct drm_i915_gem_object *obj_priv;
4165 mutex_lock(&dev->struct_mutex);
4167 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4169 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4171 mutex_unlock(&dev->struct_mutex);
4175 obj_priv = to_intel_bo(obj);
4176 if (obj_priv->pin_filp != file_priv) {
4177 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4179 drm_gem_object_unreference(obj);
4180 mutex_unlock(&dev->struct_mutex);
4183 obj_priv->user_pin_count--;
4184 if (obj_priv->user_pin_count == 0) {
4185 obj_priv->pin_filp = NULL;
4186 i915_gem_object_unpin(obj);
4189 drm_gem_object_unreference(obj);
4190 mutex_unlock(&dev->struct_mutex);
4195 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4196 struct drm_file *file_priv)
4198 struct drm_i915_gem_busy *args = data;
4199 struct drm_gem_object *obj;
4200 struct drm_i915_gem_object *obj_priv;
4202 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4204 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4209 mutex_lock(&dev->struct_mutex);
4211 /* Count all active objects as busy, even if they are currently not used
4212 * by the gpu. Users of this interface expect objects to eventually
4213 * become non-busy without any further actions, therefore emit any
4214 * necessary flushes here.
4216 obj_priv = to_intel_bo(obj);
4217 args->busy = obj_priv->active;
4219 /* Unconditionally flush objects, even when the gpu still uses this
4220 * object. Userspace calling this function indicates that it wants to
4221 * use this buffer rather sooner than later, so issuing the required
4222 * flush earlier is beneficial.
4224 if (obj->write_domain) {
4225 i915_gem_flush(dev, 0, obj->write_domain);
4226 (void)i915_add_request(dev, file_priv, obj_priv->ring);
4229 /* Update the active list for the hardware's current position.
4230 * Otherwise this only updates on a delayed timer or when irqs
4231 * are actually unmasked, and our working set ends up being
4232 * larger than required.
4234 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4236 args->busy = obj_priv->active;
4239 drm_gem_object_unreference(obj);
4240 mutex_unlock(&dev->struct_mutex);
4245 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4246 struct drm_file *file_priv)
4248 return i915_gem_ring_throttle(dev, file_priv);
4252 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4253 struct drm_file *file_priv)
4255 struct drm_i915_gem_madvise *args = data;
4256 struct drm_gem_object *obj;
4257 struct drm_i915_gem_object *obj_priv;
4259 switch (args->madv) {
4260 case I915_MADV_DONTNEED:
4261 case I915_MADV_WILLNEED:
4267 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4269 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4274 mutex_lock(&dev->struct_mutex);
4275 obj_priv = to_intel_bo(obj);
4277 if (obj_priv->pin_count) {
4278 drm_gem_object_unreference(obj);
4279 mutex_unlock(&dev->struct_mutex);
4281 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4285 if (obj_priv->madv != __I915_MADV_PURGED)
4286 obj_priv->madv = args->madv;
4288 /* if the object is no longer bound, discard its backing storage */
4289 if (i915_gem_object_is_purgeable(obj_priv) &&
4290 obj_priv->gtt_space == NULL)
4291 i915_gem_object_truncate(obj);
4293 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4295 drm_gem_object_unreference(obj);
4296 mutex_unlock(&dev->struct_mutex);
4301 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4304 struct drm_i915_gem_object *obj;
4306 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4310 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4315 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4316 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4318 obj->agp_type = AGP_USER_MEMORY;
4319 obj->base.driver_private = NULL;
4320 obj->fence_reg = I915_FENCE_REG_NONE;
4321 INIT_LIST_HEAD(&obj->list);
4322 INIT_LIST_HEAD(&obj->gpu_write_list);
4323 obj->madv = I915_MADV_WILLNEED;
4325 trace_i915_gem_object_create(&obj->base);
4330 int i915_gem_init_object(struct drm_gem_object *obj)
4337 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4339 struct drm_device *dev = obj->dev;
4340 drm_i915_private_t *dev_priv = dev->dev_private;
4341 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4344 ret = i915_gem_object_unbind(obj);
4345 if (ret == -ERESTARTSYS) {
4346 list_move(&obj_priv->list,
4347 &dev_priv->mm.deferred_free_list);
4351 if (obj_priv->mmap_offset)
4352 i915_gem_free_mmap_offset(obj);
4354 drm_gem_object_release(obj);
4356 kfree(obj_priv->page_cpu_valid);
4357 kfree(obj_priv->bit_17);
4361 void i915_gem_free_object(struct drm_gem_object *obj)
4363 struct drm_device *dev = obj->dev;
4364 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4366 trace_i915_gem_object_destroy(obj);
4368 while (obj_priv->pin_count > 0)
4369 i915_gem_object_unpin(obj);
4371 if (obj_priv->phys_obj)
4372 i915_gem_detach_phys_object(dev, obj);
4374 i915_gem_free_object_tail(obj);
4378 i915_gem_idle(struct drm_device *dev)
4380 drm_i915_private_t *dev_priv = dev->dev_private;
4383 mutex_lock(&dev->struct_mutex);
4385 if (dev_priv->mm.suspended ||
4386 (dev_priv->render_ring.gem_object == NULL) ||
4388 dev_priv->bsd_ring.gem_object == NULL)) {
4389 mutex_unlock(&dev->struct_mutex);
4393 ret = i915_gpu_idle(dev);
4395 mutex_unlock(&dev->struct_mutex);
4399 /* Under UMS, be paranoid and evict. */
4400 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4401 ret = i915_gem_evict_inactive(dev);
4403 mutex_unlock(&dev->struct_mutex);
4408 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4409 * We need to replace this with a semaphore, or something.
4410 * And not confound mm.suspended!
4412 dev_priv->mm.suspended = 1;
4413 del_timer_sync(&dev_priv->hangcheck_timer);
4415 i915_kernel_lost_context(dev);
4416 i915_gem_cleanup_ringbuffer(dev);
4418 mutex_unlock(&dev->struct_mutex);
4420 /* Cancel the retire work handler, which should be idle now. */
4421 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4427 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4428 * over cache flushing.
4431 i915_gem_init_pipe_control(struct drm_device *dev)
4433 drm_i915_private_t *dev_priv = dev->dev_private;
4434 struct drm_gem_object *obj;
4435 struct drm_i915_gem_object *obj_priv;
4438 obj = i915_gem_alloc_object(dev, 4096);
4440 DRM_ERROR("Failed to allocate seqno page\n");
4444 obj_priv = to_intel_bo(obj);
4445 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4447 ret = i915_gem_object_pin(obj, 4096);
4451 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4452 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4453 if (dev_priv->seqno_page == NULL)
4456 dev_priv->seqno_obj = obj;
4457 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4462 i915_gem_object_unpin(obj);
4464 drm_gem_object_unreference(obj);
4471 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4473 drm_i915_private_t *dev_priv = dev->dev_private;
4474 struct drm_gem_object *obj;
4475 struct drm_i915_gem_object *obj_priv;
4477 obj = dev_priv->seqno_obj;
4478 obj_priv = to_intel_bo(obj);
4479 kunmap(obj_priv->pages[0]);
4480 i915_gem_object_unpin(obj);
4481 drm_gem_object_unreference(obj);
4482 dev_priv->seqno_obj = NULL;
4484 dev_priv->seqno_page = NULL;
4488 i915_gem_init_ringbuffer(struct drm_device *dev)
4490 drm_i915_private_t *dev_priv = dev->dev_private;
4493 dev_priv->render_ring = render_ring;
4495 if (!I915_NEED_GFX_HWS(dev)) {
4496 dev_priv->render_ring.status_page.page_addr
4497 = dev_priv->status_page_dmah->vaddr;
4498 memset(dev_priv->render_ring.status_page.page_addr,
4502 if (HAS_PIPE_CONTROL(dev)) {
4503 ret = i915_gem_init_pipe_control(dev);
4508 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4510 goto cleanup_pipe_control;
4513 dev_priv->bsd_ring = bsd_ring;
4514 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4516 goto cleanup_render_ring;
4519 dev_priv->next_seqno = 1;
4523 cleanup_render_ring:
4524 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4525 cleanup_pipe_control:
4526 if (HAS_PIPE_CONTROL(dev))
4527 i915_gem_cleanup_pipe_control(dev);
4532 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4534 drm_i915_private_t *dev_priv = dev->dev_private;
4536 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4538 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4539 if (HAS_PIPE_CONTROL(dev))
4540 i915_gem_cleanup_pipe_control(dev);
4544 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4545 struct drm_file *file_priv)
4547 drm_i915_private_t *dev_priv = dev->dev_private;
4550 if (drm_core_check_feature(dev, DRIVER_MODESET))
4553 if (atomic_read(&dev_priv->mm.wedged)) {
4554 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4555 atomic_set(&dev_priv->mm.wedged, 0);
4558 mutex_lock(&dev->struct_mutex);
4559 dev_priv->mm.suspended = 0;
4561 ret = i915_gem_init_ringbuffer(dev);
4563 mutex_unlock(&dev->struct_mutex);
4567 spin_lock(&dev_priv->mm.active_list_lock);
4568 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4569 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4570 spin_unlock(&dev_priv->mm.active_list_lock);
4572 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4573 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4574 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4575 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4576 mutex_unlock(&dev->struct_mutex);
4578 ret = drm_irq_install(dev);
4580 goto cleanup_ringbuffer;
4585 mutex_lock(&dev->struct_mutex);
4586 i915_gem_cleanup_ringbuffer(dev);
4587 dev_priv->mm.suspended = 1;
4588 mutex_unlock(&dev->struct_mutex);
4594 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4595 struct drm_file *file_priv)
4597 if (drm_core_check_feature(dev, DRIVER_MODESET))
4600 drm_irq_uninstall(dev);
4601 return i915_gem_idle(dev);
4605 i915_gem_lastclose(struct drm_device *dev)
4609 if (drm_core_check_feature(dev, DRIVER_MODESET))
4612 ret = i915_gem_idle(dev);
4614 DRM_ERROR("failed to idle hardware: %d\n", ret);
4618 i915_gem_load(struct drm_device *dev)
4621 drm_i915_private_t *dev_priv = dev->dev_private;
4623 spin_lock_init(&dev_priv->mm.active_list_lock);
4624 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4625 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4626 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4627 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4628 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4629 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4630 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4632 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4633 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4635 for (i = 0; i < 16; i++)
4636 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4637 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4638 i915_gem_retire_work_handler);
4639 spin_lock(&shrink_list_lock);
4640 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4641 spin_unlock(&shrink_list_lock);
4643 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4645 u32 tmp = I915_READ(MI_ARB_STATE);
4646 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4647 /* arb state is a masked write, so set bit + bit in mask */
4648 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4649 I915_WRITE(MI_ARB_STATE, tmp);
4653 /* Old X drivers will take 0-2 for front, back, depth buffers */
4654 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4655 dev_priv->fence_reg_start = 3;
4657 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4658 dev_priv->num_fence_regs = 16;
4660 dev_priv->num_fence_regs = 8;
4662 /* Initialize fence registers to zero */
4663 if (IS_I965G(dev)) {
4664 for (i = 0; i < 16; i++)
4665 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4667 for (i = 0; i < 8; i++)
4668 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4669 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4670 for (i = 0; i < 8; i++)
4671 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4673 i915_gem_detect_bit_6_swizzle(dev);
4674 init_waitqueue_head(&dev_priv->pending_flip_queue);
4678 * Create a physically contiguous memory object for this object
4679 * e.g. for cursor + overlay regs
4681 int i915_gem_init_phys_object(struct drm_device *dev,
4682 int id, int size, int align)
4684 drm_i915_private_t *dev_priv = dev->dev_private;
4685 struct drm_i915_gem_phys_object *phys_obj;
4688 if (dev_priv->mm.phys_objs[id - 1] || !size)
4691 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4697 phys_obj->handle = drm_pci_alloc(dev, size, align);
4698 if (!phys_obj->handle) {
4703 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4706 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4714 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4716 drm_i915_private_t *dev_priv = dev->dev_private;
4717 struct drm_i915_gem_phys_object *phys_obj;
4719 if (!dev_priv->mm.phys_objs[id - 1])
4722 phys_obj = dev_priv->mm.phys_objs[id - 1];
4723 if (phys_obj->cur_obj) {
4724 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4728 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4730 drm_pci_free(dev, phys_obj->handle);
4732 dev_priv->mm.phys_objs[id - 1] = NULL;
4735 void i915_gem_free_all_phys_object(struct drm_device *dev)
4739 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4740 i915_gem_free_phys_object(dev, i);
4743 void i915_gem_detach_phys_object(struct drm_device *dev,
4744 struct drm_gem_object *obj)
4746 struct drm_i915_gem_object *obj_priv;
4751 obj_priv = to_intel_bo(obj);
4752 if (!obj_priv->phys_obj)
4755 ret = i915_gem_object_get_pages(obj, 0);
4759 page_count = obj->size / PAGE_SIZE;
4761 for (i = 0; i < page_count; i++) {
4762 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4763 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4765 memcpy(dst, src, PAGE_SIZE);
4766 kunmap_atomic(dst, KM_USER0);
4768 drm_clflush_pages(obj_priv->pages, page_count);
4769 drm_agp_chipset_flush(dev);
4771 i915_gem_object_put_pages(obj);
4773 obj_priv->phys_obj->cur_obj = NULL;
4774 obj_priv->phys_obj = NULL;
4778 i915_gem_attach_phys_object(struct drm_device *dev,
4779 struct drm_gem_object *obj,
4783 drm_i915_private_t *dev_priv = dev->dev_private;
4784 struct drm_i915_gem_object *obj_priv;
4789 if (id > I915_MAX_PHYS_OBJECT)
4792 obj_priv = to_intel_bo(obj);
4794 if (obj_priv->phys_obj) {
4795 if (obj_priv->phys_obj->id == id)
4797 i915_gem_detach_phys_object(dev, obj);
4800 /* create a new object */
4801 if (!dev_priv->mm.phys_objs[id - 1]) {
4802 ret = i915_gem_init_phys_object(dev, id,
4805 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4810 /* bind to the object */
4811 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4812 obj_priv->phys_obj->cur_obj = obj;
4814 ret = i915_gem_object_get_pages(obj, 0);
4816 DRM_ERROR("failed to get page list\n");
4820 page_count = obj->size / PAGE_SIZE;
4822 for (i = 0; i < page_count; i++) {
4823 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4824 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4826 memcpy(dst, src, PAGE_SIZE);
4827 kunmap_atomic(src, KM_USER0);
4830 i915_gem_object_put_pages(obj);
4838 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4839 struct drm_i915_gem_pwrite *args,
4840 struct drm_file *file_priv)
4842 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4845 char __user *user_data;
4847 user_data = (char __user *) (uintptr_t) args->data_ptr;
4848 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4850 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4851 ret = copy_from_user(obj_addr, user_data, args->size);
4855 drm_agp_chipset_flush(dev);
4859 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4861 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4863 /* Clean up our request list when the client is going away, so that
4864 * later retire_requests won't dereference our soon-to-be-gone
4867 mutex_lock(&dev->struct_mutex);
4868 while (!list_empty(&i915_file_priv->mm.request_list))
4869 list_del_init(i915_file_priv->mm.request_list.next);
4870 mutex_unlock(&dev->struct_mutex);
4874 i915_gpu_is_active(struct drm_device *dev)
4876 drm_i915_private_t *dev_priv = dev->dev_private;
4879 spin_lock(&dev_priv->mm.active_list_lock);
4880 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4881 list_empty(&dev_priv->render_ring.active_list);
4883 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4884 spin_unlock(&dev_priv->mm.active_list_lock);
4886 return !lists_empty;
4890 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4892 drm_i915_private_t *dev_priv, *next_dev;
4893 struct drm_i915_gem_object *obj_priv, *next_obj;
4895 int would_deadlock = 1;
4897 /* "fast-path" to count number of available objects */
4898 if (nr_to_scan == 0) {
4899 spin_lock(&shrink_list_lock);
4900 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4901 struct drm_device *dev = dev_priv->dev;
4903 if (mutex_trylock(&dev->struct_mutex)) {
4904 list_for_each_entry(obj_priv,
4905 &dev_priv->mm.inactive_list,
4908 mutex_unlock(&dev->struct_mutex);
4911 spin_unlock(&shrink_list_lock);
4913 return (cnt / 100) * sysctl_vfs_cache_pressure;
4916 spin_lock(&shrink_list_lock);
4919 /* first scan for clean buffers */
4920 list_for_each_entry_safe(dev_priv, next_dev,
4921 &shrink_list, mm.shrink_list) {
4922 struct drm_device *dev = dev_priv->dev;
4924 if (! mutex_trylock(&dev->struct_mutex))
4927 spin_unlock(&shrink_list_lock);
4928 i915_gem_retire_requests(dev);
4930 list_for_each_entry_safe(obj_priv, next_obj,
4931 &dev_priv->mm.inactive_list,
4933 if (i915_gem_object_is_purgeable(obj_priv)) {
4934 i915_gem_object_unbind(&obj_priv->base);
4935 if (--nr_to_scan <= 0)
4940 spin_lock(&shrink_list_lock);
4941 mutex_unlock(&dev->struct_mutex);
4945 if (nr_to_scan <= 0)
4949 /* second pass, evict/count anything still on the inactive list */
4950 list_for_each_entry_safe(dev_priv, next_dev,
4951 &shrink_list, mm.shrink_list) {
4952 struct drm_device *dev = dev_priv->dev;
4954 if (! mutex_trylock(&dev->struct_mutex))
4957 spin_unlock(&shrink_list_lock);
4959 list_for_each_entry_safe(obj_priv, next_obj,
4960 &dev_priv->mm.inactive_list,
4962 if (nr_to_scan > 0) {
4963 i915_gem_object_unbind(&obj_priv->base);
4969 spin_lock(&shrink_list_lock);
4970 mutex_unlock(&dev->struct_mutex);
4979 * We are desperate for pages, so as a last resort, wait
4980 * for the GPU to finish and discard whatever we can.
4981 * This has a dramatic impact to reduce the number of
4982 * OOM-killer events whilst running the GPU aggressively.
4984 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4985 struct drm_device *dev = dev_priv->dev;
4987 if (!mutex_trylock(&dev->struct_mutex))
4990 spin_unlock(&shrink_list_lock);
4992 if (i915_gpu_is_active(dev)) {
4997 spin_lock(&shrink_list_lock);
4998 mutex_unlock(&dev->struct_mutex);
5005 spin_unlock(&shrink_list_lock);
5010 return (cnt / 100) * sysctl_vfs_cache_pressure;
5015 static struct shrinker shrinker = {
5016 .shrink = i915_gem_shrink,
5017 .seeks = DEFAULT_SEEKS,
5021 i915_gem_shrinker_init(void)
5023 register_shrinker(&shrinker);
5027 i915_gem_shrinker_exit(void)
5029 unregister_shrinker(&shrinker);