2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
47 i915_gem_object_retire(struct drm_i915_gem_object *obj);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static bool cpu_cache_is_coherent(struct drm_device *dev,
56 enum i915_cache_level level)
58 return HAS_LLC(dev) || level != I915_CACHE_NONE;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
63 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
66 return obj->pin_display;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
72 i915_gem_release_mmap(obj);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj->fence_dirty = false;
78 obj->fence_reg = I915_FENCE_REG_NONE;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
85 spin_lock(&dev_priv->mm.object_stat_lock);
86 dev_priv->mm.object_count++;
87 dev_priv->mm.object_memory += size;
88 spin_unlock(&dev_priv->mm.object_stat_lock);
91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count--;
96 dev_priv->mm.object_memory -= size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
101 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret = wait_event_interruptible_timeout(error->reset_queue,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret < 0) {
129 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
138 ret = mutex_lock_interruptible(&dev->struct_mutex);
142 WARN_ON(i915_verify_lists(dev));
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_i915_gem_get_aperture *args = data;
152 struct drm_i915_gem_object *obj;
156 mutex_lock(&dev->struct_mutex);
157 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
158 if (i915_gem_obj_is_pinned(obj))
159 pinned += i915_gem_obj_ggtt_size(obj);
160 mutex_unlock(&dev->struct_mutex);
162 args->aper_size = dev_priv->gtt.base.total;
163 args->aper_available_size = args->aper_size - pinned;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
171 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
172 char *vaddr = obj->phys_handle->vaddr;
174 struct scatterlist *sg;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
184 page = shmem_read_mapping_page(mapping, i);
186 return PTR_ERR(page);
188 src = kmap_atomic(page);
189 memcpy(vaddr, src, PAGE_SIZE);
190 drm_clflush_virt_range(vaddr, PAGE_SIZE);
193 page_cache_release(page);
197 i915_gem_chipset_flush(obj->base.dev);
199 st = kmalloc(sizeof(*st), GFP_KERNEL);
203 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 sg->length = obj->base.size;
212 sg_dma_address(sg) = obj->phys_handle->busaddr;
213 sg_dma_len(sg) = obj->base.size;
216 obj->has_dma_mapping = true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
225 BUG_ON(obj->madv == __I915_MADV_PURGED);
227 ret = i915_gem_object_set_to_cpu_domain(obj, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret != -EIO);
233 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
236 if (obj->madv == I915_MADV_DONTNEED)
240 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
241 char *vaddr = obj->phys_handle->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
248 page = shmem_read_mapping_page(mapping, i);
252 dst = kmap_atomic(page);
253 drm_clflush_virt_range(vaddr, PAGE_SIZE);
254 memcpy(dst, vaddr, PAGE_SIZE);
257 set_page_dirty(page);
258 if (obj->madv == I915_MADV_WILLNEED)
259 mark_page_accessed(page);
260 page_cache_release(page);
266 sg_free_table(obj->pages);
269 obj->has_dma_mapping = false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
275 drm_pci_free(obj->base.dev, obj->phys_handle);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
279 .get_pages = i915_gem_object_get_pages_phys,
280 .put_pages = i915_gem_object_put_pages_phys,
281 .release = i915_gem_object_release_phys,
285 drop_pages(struct drm_i915_gem_object *obj)
287 struct i915_vma *vma, *next;
290 drm_gem_object_reference(&obj->base);
291 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
292 if (i915_vma_unbind(vma))
295 ret = i915_gem_object_put_pages(obj);
296 drm_gem_object_unreference(&obj->base);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
305 drm_dma_handle_t *phys;
308 if (obj->phys_handle) {
309 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
315 if (obj->madv != I915_MADV_WILLNEED)
318 if (obj->base.filp == NULL)
321 ret = drop_pages(obj);
325 /* create a new object */
326 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
330 obj->phys_handle = phys;
331 obj->ops = &i915_gem_phys_ops;
333 return i915_gem_object_get_pages(obj);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
338 struct drm_i915_gem_pwrite *args,
339 struct drm_file *file_priv)
341 struct drm_device *dev = obj->base.dev;
342 void *vaddr = obj->phys_handle->vaddr + args->offset;
343 char __user *user_data = to_user_ptr(args->data_ptr);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret = i915_gem_object_wait_rendering(obj, false);
353 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
354 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
355 unsigned long unwritten;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev->struct_mutex);
362 unwritten = copy_from_user(vaddr, user_data, args->size);
363 mutex_lock(&dev->struct_mutex);
370 drm_clflush_virt_range(vaddr, args->size);
371 i915_gem_chipset_flush(dev);
374 intel_fb_obj_flush(obj, false);
378 void *i915_gem_object_alloc(struct drm_device *dev)
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
387 kmem_cache_free(dev_priv->objects, obj);
391 i915_gem_create(struct drm_file *file,
392 struct drm_device *dev,
396 struct drm_i915_gem_object *obj;
400 size = roundup(size, PAGE_SIZE);
404 /* Allocate the new object */
405 obj = i915_gem_alloc_object(dev, size);
409 ret = drm_gem_handle_create(file, &obj->base, &handle);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj->base);
420 i915_gem_dumb_create(struct drm_file *file,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args)
424 /* have to work out size/pitch and return them */
425 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
426 args->size = args->pitch * args->height;
427 return i915_gem_create(file, dev,
428 args->size, &args->handle);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
436 struct drm_file *file)
438 struct drm_i915_gem_create *args = data;
440 return i915_gem_create(file, dev,
441 args->size, &args->handle);
445 __copy_to_user_swizzled(char __user *cpu_vaddr,
446 const char *gpu_vaddr, int gpu_offset,
449 int ret, cpu_offset = 0;
452 int cacheline_end = ALIGN(gpu_offset + 1, 64);
453 int this_length = min(cacheline_end - gpu_offset, length);
454 int swizzled_gpu_offset = gpu_offset ^ 64;
456 ret = __copy_to_user(cpu_vaddr + cpu_offset,
457 gpu_vaddr + swizzled_gpu_offset,
462 cpu_offset += this_length;
463 gpu_offset += this_length;
464 length -= this_length;
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
472 const char __user *cpu_vaddr,
475 int ret, cpu_offset = 0;
478 int cacheline_end = ALIGN(gpu_offset + 1, 64);
479 int this_length = min(cacheline_end - gpu_offset, length);
480 int swizzled_gpu_offset = gpu_offset ^ 64;
482 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
483 cpu_vaddr + cpu_offset,
488 cpu_offset += this_length;
489 gpu_offset += this_length;
490 length -= this_length;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
511 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
518 ret = i915_gem_object_wait_rendering(obj, true);
522 i915_gem_object_retire(obj);
525 ret = i915_gem_object_get_pages(obj);
529 i915_gem_object_pin_pages(obj);
534 /* Per-page copy function for the shmem pread fastpath.
535 * Flushes invalid cachelines before reading the target if
536 * needs_clflush is set. */
538 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
539 char __user *user_data,
540 bool page_do_bit17_swizzling, bool needs_clflush)
545 if (unlikely(page_do_bit17_swizzling))
548 vaddr = kmap_atomic(page);
550 drm_clflush_virt_range(vaddr + shmem_page_offset,
552 ret = __copy_to_user_inatomic(user_data,
553 vaddr + shmem_page_offset,
555 kunmap_atomic(vaddr);
557 return ret ? -EFAULT : 0;
561 shmem_clflush_swizzled_range(char *addr, unsigned long length,
564 if (unlikely(swizzled)) {
565 unsigned long start = (unsigned long) addr;
566 unsigned long end = (unsigned long) addr + length;
568 /* For swizzling simply ensure that we always flush both
569 * channels. Lame, but simple and it works. Swizzled
570 * pwrite/pread is far from a hotpath - current userspace
571 * doesn't use it at all. */
572 start = round_down(start, 128);
573 end = round_up(end, 128);
575 drm_clflush_virt_range((void *)start, end - start);
577 drm_clflush_virt_range(addr, length);
582 /* Only difference to the fast-path function is that this can handle bit17
583 * and uses non-atomic copy and kmap functions. */
585 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
586 char __user *user_data,
587 bool page_do_bit17_swizzling, bool needs_clflush)
594 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
596 page_do_bit17_swizzling);
598 if (page_do_bit17_swizzling)
599 ret = __copy_to_user_swizzled(user_data,
600 vaddr, shmem_page_offset,
603 ret = __copy_to_user(user_data,
604 vaddr + shmem_page_offset,
608 return ret ? - EFAULT : 0;
612 i915_gem_shmem_pread(struct drm_device *dev,
613 struct drm_i915_gem_object *obj,
614 struct drm_i915_gem_pread *args,
615 struct drm_file *file)
617 char __user *user_data;
620 int shmem_page_offset, page_length, ret = 0;
621 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
623 int needs_clflush = 0;
624 struct sg_page_iter sg_iter;
626 user_data = to_user_ptr(args->data_ptr);
629 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
631 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
635 offset = args->offset;
637 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
638 offset >> PAGE_SHIFT) {
639 struct page *page = sg_page_iter_page(&sg_iter);
644 /* Operation in this page
646 * shmem_page_offset = offset within page in shmem file
647 * page_length = bytes to copy for this page
649 shmem_page_offset = offset_in_page(offset);
650 page_length = remain;
651 if ((shmem_page_offset + page_length) > PAGE_SIZE)
652 page_length = PAGE_SIZE - shmem_page_offset;
654 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
655 (page_to_phys(page) & (1 << 17)) != 0;
657 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
658 user_data, page_do_bit17_swizzling,
663 mutex_unlock(&dev->struct_mutex);
665 if (likely(!i915.prefault_disable) && !prefaulted) {
666 ret = fault_in_multipages_writeable(user_data, remain);
667 /* Userspace is tricking us, but we've already clobbered
668 * its pages with the prefault and promised to write the
669 * data up to the first fault. Hence ignore any errors
670 * and just continue. */
675 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
676 user_data, page_do_bit17_swizzling,
679 mutex_lock(&dev->struct_mutex);
685 remain -= page_length;
686 user_data += page_length;
687 offset += page_length;
691 i915_gem_object_unpin_pages(obj);
697 * Reads data from the object referenced by handle.
699 * On error, the contents of *data are undefined.
702 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
703 struct drm_file *file)
705 struct drm_i915_gem_pread *args = data;
706 struct drm_i915_gem_object *obj;
712 if (!access_ok(VERIFY_WRITE,
713 to_user_ptr(args->data_ptr),
717 ret = i915_mutex_lock_interruptible(dev);
721 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
722 if (&obj->base == NULL) {
727 /* Bounds check source. */
728 if (args->offset > obj->base.size ||
729 args->size > obj->base.size - args->offset) {
734 /* prime objects have no backing filp to GEM pread/pwrite
737 if (!obj->base.filp) {
742 trace_i915_gem_object_pread(obj, args->offset, args->size);
744 ret = i915_gem_shmem_pread(dev, obj, args, file);
747 drm_gem_object_unreference(&obj->base);
749 mutex_unlock(&dev->struct_mutex);
753 /* This is the fast write path which cannot handle
754 * page faults in the source data
758 fast_user_write(struct io_mapping *mapping,
759 loff_t page_base, int page_offset,
760 char __user *user_data,
763 void __iomem *vaddr_atomic;
765 unsigned long unwritten;
767 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
768 /* We can use the cpu mem copy function because this is X86. */
769 vaddr = (void __force*)vaddr_atomic + page_offset;
770 unwritten = __copy_from_user_inatomic_nocache(vaddr,
772 io_mapping_unmap_atomic(vaddr_atomic);
777 * This is the fast pwrite path, where we copy the data directly from the
778 * user into the GTT, uncached.
781 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
782 struct drm_i915_gem_object *obj,
783 struct drm_i915_gem_pwrite *args,
784 struct drm_file *file)
786 struct drm_i915_private *dev_priv = dev->dev_private;
788 loff_t offset, page_base;
789 char __user *user_data;
790 int page_offset, page_length, ret;
792 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
796 ret = i915_gem_object_set_to_gtt_domain(obj, true);
800 ret = i915_gem_object_put_fence(obj);
804 user_data = to_user_ptr(args->data_ptr);
807 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
809 intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
812 /* Operation in this page
814 * page_base = page offset within aperture
815 * page_offset = offset within page
816 * page_length = bytes to copy for this page
818 page_base = offset & PAGE_MASK;
819 page_offset = offset_in_page(offset);
820 page_length = remain;
821 if ((page_offset + remain) > PAGE_SIZE)
822 page_length = PAGE_SIZE - page_offset;
824 /* If we get a fault while copying data, then (presumably) our
825 * source page isn't available. Return the error and we'll
826 * retry in the slow path.
828 if (fast_user_write(dev_priv->gtt.mappable, page_base,
829 page_offset, user_data, page_length)) {
834 remain -= page_length;
835 user_data += page_length;
836 offset += page_length;
840 intel_fb_obj_flush(obj, false);
842 i915_gem_object_ggtt_unpin(obj);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
853 char __user *user_data,
854 bool page_do_bit17_swizzling,
855 bool needs_clflush_before,
856 bool needs_clflush_after)
861 if (unlikely(page_do_bit17_swizzling))
864 vaddr = kmap_atomic(page);
865 if (needs_clflush_before)
866 drm_clflush_virt_range(vaddr + shmem_page_offset,
868 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
869 user_data, page_length);
870 if (needs_clflush_after)
871 drm_clflush_virt_range(vaddr + shmem_page_offset,
873 kunmap_atomic(vaddr);
875 return ret ? -EFAULT : 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
882 char __user *user_data,
883 bool page_do_bit17_swizzling,
884 bool needs_clflush_before,
885 bool needs_clflush_after)
891 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
892 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
894 page_do_bit17_swizzling);
895 if (page_do_bit17_swizzling)
896 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
900 ret = __copy_from_user(vaddr + shmem_page_offset,
903 if (needs_clflush_after)
904 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
906 page_do_bit17_swizzling);
909 return ret ? -EFAULT : 0;
913 i915_gem_shmem_pwrite(struct drm_device *dev,
914 struct drm_i915_gem_object *obj,
915 struct drm_i915_gem_pwrite *args,
916 struct drm_file *file)
920 char __user *user_data;
921 int shmem_page_offset, page_length, ret = 0;
922 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
923 int hit_slowpath = 0;
924 int needs_clflush_after = 0;
925 int needs_clflush_before = 0;
926 struct sg_page_iter sg_iter;
928 user_data = to_user_ptr(args->data_ptr);
931 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
933 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after = cpu_write_needs_clflush(obj);
939 ret = i915_gem_object_wait_rendering(obj, false);
943 i915_gem_object_retire(obj);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
948 needs_clflush_before =
949 !cpu_cache_is_coherent(dev, obj->cache_level);
951 ret = i915_gem_object_get_pages(obj);
955 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
957 i915_gem_object_pin_pages(obj);
959 offset = args->offset;
962 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
963 offset >> PAGE_SHIFT) {
964 struct page *page = sg_page_iter_page(&sg_iter);
965 int partial_cacheline_write;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset = offset_in_page(offset);
977 page_length = remain;
978 if ((shmem_page_offset + page_length) > PAGE_SIZE)
979 page_length = PAGE_SIZE - shmem_page_offset;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write = needs_clflush_before &&
985 ((shmem_page_offset | page_length)
986 & (boot_cpu_data.x86_clflush_size - 1));
988 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
989 (page_to_phys(page) & (1 << 17)) != 0;
991 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
992 user_data, page_do_bit17_swizzling,
993 partial_cacheline_write,
994 needs_clflush_after);
999 mutex_unlock(&dev->struct_mutex);
1000 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1001 user_data, page_do_bit17_swizzling,
1002 partial_cacheline_write,
1003 needs_clflush_after);
1005 mutex_lock(&dev->struct_mutex);
1011 remain -= page_length;
1012 user_data += page_length;
1013 offset += page_length;
1017 i915_gem_object_unpin_pages(obj);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after &&
1026 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1027 if (i915_gem_clflush_object(obj, obj->pin_display))
1028 i915_gem_chipset_flush(dev);
1032 if (needs_clflush_after)
1033 i915_gem_chipset_flush(dev);
1035 intel_fb_obj_flush(obj, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1046 struct drm_file *file)
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 struct drm_i915_gem_pwrite *args = data;
1050 struct drm_i915_gem_object *obj;
1053 if (args->size == 0)
1056 if (!access_ok(VERIFY_READ,
1057 to_user_ptr(args->data_ptr),
1061 if (likely(!i915.prefault_disable)) {
1062 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1068 intel_runtime_pm_get(dev_priv);
1070 ret = i915_mutex_lock_interruptible(dev);
1074 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1075 if (&obj->base == NULL) {
1080 /* Bounds check destination. */
1081 if (args->offset > obj->base.size ||
1082 args->size > obj->base.size - args->offset) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj->base.filp) {
1095 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj->tiling_mode == I915_TILING_NONE &&
1105 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1106 cpu_write_needs_clflush(obj)) {
1107 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret == -EFAULT || ret == -ENOSPC) {
1114 if (obj->phys_handle)
1115 ret = i915_gem_phys_pwrite(obj, args, file);
1117 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1121 drm_gem_object_unreference(&obj->base);
1123 mutex_unlock(&dev->struct_mutex);
1125 intel_runtime_pm_put(dev_priv);
1131 i915_gem_check_wedge(struct i915_gpu_error *error,
1134 if (i915_reset_in_progress(error)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error->reload_in_reset)
1157 * Compare arbitrary request against outstanding lazy request. Emit on match.
1160 i915_gem_check_olr(struct drm_i915_gem_request *req)
1164 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1167 if (req == req->ring->outstanding_lazy_request)
1168 ret = i915_add_request(req->ring);
1173 static void fake_irq(unsigned long data)
1175 wake_up_process((struct task_struct *)data);
1178 static bool missed_irq(struct drm_i915_private *dev_priv,
1179 struct intel_engine_cs *ring)
1181 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1184 static int __i915_spin_request(struct drm_i915_gem_request *rq)
1186 unsigned long timeout;
1188 if (i915_gem_request_get_ring(rq)->irq_refcount)
1191 timeout = jiffies + 1;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(rq, true))
1196 if (time_after_eq(jiffies, timeout))
1199 cpu_relax_lowlatency();
1201 if (i915_gem_request_completed(rq, false))
1208 * __i915_wait_request - wait until execution of request has finished
1210 * @reset_counter: reset sequence associated with the given request
1211 * @interruptible: do an interruptible wait (normally yes)
1212 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1214 * Note: It is of utmost importance that the passed in seqno and reset_counter
1215 * values have been read by the caller in an smp safe manner. Where read-side
1216 * locks are involved, it is sufficient to read the reset_counter before
1217 * unlocking the lock that protects the seqno. For lockless tricks, the
1218 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1221 * Returns 0 if the request was found within the alloted time. Else returns the
1222 * errno with remaining time filled in timeout argument.
1224 int __i915_wait_request(struct drm_i915_gem_request *req,
1225 unsigned reset_counter,
1228 struct drm_i915_file_private *file_priv)
1230 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1231 struct drm_device *dev = ring->dev;
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 const bool irq_test_in_progress =
1234 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1236 unsigned long timeout_expire;
1240 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1242 if (i915_gem_request_completed(req, true))
1245 timeout_expire = timeout ?
1246 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1248 if (INTEL_INFO(dev)->gen >= 6)
1249 gen6_rps_boost(dev_priv, file_priv);
1251 /* Record current time in case interrupted by signal, or wedged */
1252 trace_i915_gem_request_wait_begin(req);
1253 before = ktime_get_raw_ns();
1255 /* Optimistic spin for the next jiffie before touching IRQs */
1256 ret = __i915_spin_request(req);
1260 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1266 struct timer_list timer;
1268 prepare_to_wait(&ring->irq_queue, &wait,
1269 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1271 /* We need to check whether any gpu reset happened in between
1272 * the caller grabbing the seqno and now ... */
1273 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1274 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1275 * is truely gone. */
1276 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1282 if (i915_gem_request_completed(req, false)) {
1287 if (interruptible && signal_pending(current)) {
1292 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1297 timer.function = NULL;
1298 if (timeout || missed_irq(dev_priv, ring)) {
1299 unsigned long expire;
1301 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1302 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1303 mod_timer(&timer, expire);
1308 if (timer.function) {
1309 del_singleshot_timer_sync(&timer);
1310 destroy_timer_on_stack(&timer);
1313 if (!irq_test_in_progress)
1314 ring->irq_put(ring);
1316 finish_wait(&ring->irq_queue, &wait);
1319 now = ktime_get_raw_ns();
1320 trace_i915_gem_request_wait_end(req);
1323 s64 tres = *timeout - (now - before);
1325 *timeout = tres < 0 ? 0 : tres;
1328 * Apparently ktime isn't accurate enough and occasionally has a
1329 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1330 * things up to make the test happy. We allow up to 1 jiffy.
1332 * This is a regrssion from the timespec->ktime conversion.
1334 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1342 * Waits for a request to be signaled, and cleans up the
1343 * request and object lists appropriately for that event.
1346 i915_wait_request(struct drm_i915_gem_request *req)
1348 struct drm_device *dev;
1349 struct drm_i915_private *dev_priv;
1351 unsigned reset_counter;
1354 BUG_ON(req == NULL);
1356 dev = req->ring->dev;
1357 dev_priv = dev->dev_private;
1358 interruptible = dev_priv->mm.interruptible;
1360 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1362 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1366 ret = i915_gem_check_olr(req);
1370 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1371 i915_gem_request_reference(req);
1372 ret = __i915_wait_request(req, reset_counter,
1373 interruptible, NULL, NULL);
1374 i915_gem_request_unreference(req);
1379 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1384 /* Manually manage the write flush as we may have not yet
1385 * retired the buffer.
1387 * Note that the last_write_req is always the earlier of
1388 * the two (read/write) requests, so if we haved successfully waited,
1389 * we know we have passed the last write.
1391 i915_gem_request_assign(&obj->last_write_req, NULL);
1397 * Ensures that all rendering to the object has completed and the object is
1398 * safe to unbind from the GTT or access from the CPU.
1400 static __must_check int
1401 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1404 struct drm_i915_gem_request *req;
1407 req = readonly ? obj->last_write_req : obj->last_read_req;
1411 ret = i915_wait_request(req);
1415 return i915_gem_object_wait_rendering__tail(obj);
1418 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1419 * as the object state may change during this call.
1421 static __must_check int
1422 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1423 struct drm_i915_file_private *file_priv,
1426 struct drm_i915_gem_request *req;
1427 struct drm_device *dev = obj->base.dev;
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 unsigned reset_counter;
1432 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1433 BUG_ON(!dev_priv->mm.interruptible);
1435 req = readonly ? obj->last_write_req : obj->last_read_req;
1439 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1443 ret = i915_gem_check_olr(req);
1447 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1448 i915_gem_request_reference(req);
1449 mutex_unlock(&dev->struct_mutex);
1450 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1451 mutex_lock(&dev->struct_mutex);
1452 i915_gem_request_unreference(req);
1456 return i915_gem_object_wait_rendering__tail(obj);
1460 * Called when user space prepares to use an object with the CPU, either
1461 * through the mmap ioctl's mapping or a GTT mapping.
1464 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *file)
1467 struct drm_i915_gem_set_domain *args = data;
1468 struct drm_i915_gem_object *obj;
1469 uint32_t read_domains = args->read_domains;
1470 uint32_t write_domain = args->write_domain;
1473 /* Only handle setting domains to types used by the CPU. */
1474 if (write_domain & I915_GEM_GPU_DOMAINS)
1477 if (read_domains & I915_GEM_GPU_DOMAINS)
1480 /* Having something in the write domain implies it's in the read
1481 * domain, and only that read domain. Enforce that in the request.
1483 if (write_domain != 0 && read_domains != write_domain)
1486 ret = i915_mutex_lock_interruptible(dev);
1490 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1491 if (&obj->base == NULL) {
1496 /* Try to flush the object off the GPU without holding the lock.
1497 * We will repeat the flush holding the lock in the normal manner
1498 * to catch cases where we are gazumped.
1500 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1506 if (read_domains & I915_GEM_DOMAIN_GTT)
1507 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1509 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1512 drm_gem_object_unreference(&obj->base);
1514 mutex_unlock(&dev->struct_mutex);
1519 * Called when user space has done writes to this buffer
1522 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1523 struct drm_file *file)
1525 struct drm_i915_gem_sw_finish *args = data;
1526 struct drm_i915_gem_object *obj;
1529 ret = i915_mutex_lock_interruptible(dev);
1533 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1534 if (&obj->base == NULL) {
1539 /* Pinned buffers may be scanout, so flush the cache */
1540 if (obj->pin_display)
1541 i915_gem_object_flush_cpu_write_domain(obj);
1543 drm_gem_object_unreference(&obj->base);
1545 mutex_unlock(&dev->struct_mutex);
1550 * Maps the contents of an object, returning the address it is mapped
1553 * While the mapping holds a reference on the contents of the object, it doesn't
1554 * imply a ref on the object itself.
1558 * DRM driver writers who look a this function as an example for how to do GEM
1559 * mmap support, please don't implement mmap support like here. The modern way
1560 * to implement DRM mmap support is with an mmap offset ioctl (like
1561 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1562 * That way debug tooling like valgrind will understand what's going on, hiding
1563 * the mmap call in a driver private ioctl will break that. The i915 driver only
1564 * does cpu mmaps this way because we didn't know better.
1567 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1568 struct drm_file *file)
1570 struct drm_i915_gem_mmap *args = data;
1571 struct drm_gem_object *obj;
1574 if (args->flags & ~(I915_MMAP_WC))
1577 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1580 obj = drm_gem_object_lookup(dev, file, args->handle);
1584 /* prime objects have no backing filp to GEM mmap
1588 drm_gem_object_unreference_unlocked(obj);
1592 addr = vm_mmap(obj->filp, 0, args->size,
1593 PROT_READ | PROT_WRITE, MAP_SHARED,
1595 if (args->flags & I915_MMAP_WC) {
1596 struct mm_struct *mm = current->mm;
1597 struct vm_area_struct *vma;
1599 down_write(&mm->mmap_sem);
1600 vma = find_vma(mm, addr);
1603 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1606 up_write(&mm->mmap_sem);
1608 drm_gem_object_unreference_unlocked(obj);
1609 if (IS_ERR((void *)addr))
1612 args->addr_ptr = (uint64_t) addr;
1618 * i915_gem_fault - fault a page into the GTT
1619 * vma: VMA in question
1622 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1623 * from userspace. The fault handler takes care of binding the object to
1624 * the GTT (if needed), allocating and programming a fence register (again,
1625 * only if needed based on whether the old reg is still valid or the object
1626 * is tiled) and inserting a new PTE into the faulting process.
1628 * Note that the faulting process may involve evicting existing objects
1629 * from the GTT and/or fence registers to make room. So performance may
1630 * suffer if the GTT working set is large or there are few fence registers
1633 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1635 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1636 struct drm_device *dev = obj->base.dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 pgoff_t page_offset;
1641 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1643 intel_runtime_pm_get(dev_priv);
1645 /* We don't use vmf->pgoff since that has the fake offset */
1646 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1649 ret = i915_mutex_lock_interruptible(dev);
1653 trace_i915_gem_object_fault(obj, page_offset, true, write);
1655 /* Try to flush the object off the GPU first without holding the lock.
1656 * Upon reacquiring the lock, we will perform our sanity checks and then
1657 * repeat the flush holding the lock in the normal manner to catch cases
1658 * where we are gazumped.
1660 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1664 /* Access to snoopable pages through the GTT is incoherent. */
1665 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1670 /* Now bind it into the GTT if needed */
1671 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1675 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1679 ret = i915_gem_object_get_fence(obj);
1683 /* Finally, remap it using the new GTT offset */
1684 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1687 if (!obj->fault_mappable) {
1688 unsigned long size = min_t(unsigned long,
1689 vma->vm_end - vma->vm_start,
1693 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1694 ret = vm_insert_pfn(vma,
1695 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1701 obj->fault_mappable = true;
1703 ret = vm_insert_pfn(vma,
1704 (unsigned long)vmf->virtual_address,
1707 i915_gem_object_ggtt_unpin(obj);
1709 mutex_unlock(&dev->struct_mutex);
1714 * We eat errors when the gpu is terminally wedged to avoid
1715 * userspace unduly crashing (gl has no provisions for mmaps to
1716 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1717 * and so needs to be reported.
1719 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1720 ret = VM_FAULT_SIGBUS;
1725 * EAGAIN means the gpu is hung and we'll wait for the error
1726 * handler to reset everything when re-faulting in
1727 * i915_mutex_lock_interruptible.
1734 * EBUSY is ok: this just means that another thread
1735 * already did the job.
1737 ret = VM_FAULT_NOPAGE;
1744 ret = VM_FAULT_SIGBUS;
1747 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1748 ret = VM_FAULT_SIGBUS;
1752 intel_runtime_pm_put(dev_priv);
1757 * i915_gem_release_mmap - remove physical page mappings
1758 * @obj: obj in question
1760 * Preserve the reservation of the mmapping with the DRM core code, but
1761 * relinquish ownership of the pages back to the system.
1763 * It is vital that we remove the page mapping if we have mapped a tiled
1764 * object through the GTT and then lose the fence register due to
1765 * resource pressure. Similarly if the object has been moved out of the
1766 * aperture, than pages mapped into userspace must be revoked. Removing the
1767 * mapping will then trigger a page fault on the next user access, allowing
1768 * fixup by i915_gem_fault().
1771 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1773 if (!obj->fault_mappable)
1776 drm_vma_node_unmap(&obj->base.vma_node,
1777 obj->base.dev->anon_inode->i_mapping);
1778 obj->fault_mappable = false;
1782 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1784 struct drm_i915_gem_object *obj;
1786 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1787 i915_gem_release_mmap(obj);
1791 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1795 if (INTEL_INFO(dev)->gen >= 4 ||
1796 tiling_mode == I915_TILING_NONE)
1799 /* Previous chips need a power-of-two fence region when tiling */
1800 if (INTEL_INFO(dev)->gen == 3)
1801 gtt_size = 1024*1024;
1803 gtt_size = 512*1024;
1805 while (gtt_size < size)
1812 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1813 * @obj: object to check
1815 * Return the required GTT alignment for an object, taking into account
1816 * potential fence register mapping.
1819 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1820 int tiling_mode, bool fenced)
1823 * Minimum alignment is 4k (GTT page size), but might be greater
1824 * if a fence register is needed for the object.
1826 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1827 tiling_mode == I915_TILING_NONE)
1831 * Previous chips need to be aligned to the size of the smallest
1832 * fence register that can contain the object.
1834 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1837 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1839 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1842 if (drm_vma_node_has_offset(&obj->base.vma_node))
1845 dev_priv->mm.shrinker_no_lock_stealing = true;
1847 ret = drm_gem_create_mmap_offset(&obj->base);
1851 /* Badly fragmented mmap space? The only way we can recover
1852 * space is by destroying unwanted objects. We can't randomly release
1853 * mmap_offsets as userspace expects them to be persistent for the
1854 * lifetime of the objects. The closest we can is to release the
1855 * offsets on purgeable objects by truncating it and marking it purged,
1856 * which prevents userspace from ever using that object again.
1858 i915_gem_shrink(dev_priv,
1859 obj->base.size >> PAGE_SHIFT,
1861 I915_SHRINK_UNBOUND |
1862 I915_SHRINK_PURGEABLE);
1863 ret = drm_gem_create_mmap_offset(&obj->base);
1867 i915_gem_shrink_all(dev_priv);
1868 ret = drm_gem_create_mmap_offset(&obj->base);
1870 dev_priv->mm.shrinker_no_lock_stealing = false;
1875 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1877 drm_gem_free_mmap_offset(&obj->base);
1881 i915_gem_mmap_gtt(struct drm_file *file,
1882 struct drm_device *dev,
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct drm_i915_gem_object *obj;
1890 ret = i915_mutex_lock_interruptible(dev);
1894 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1895 if (&obj->base == NULL) {
1900 if (obj->base.size > dev_priv->gtt.mappable_end) {
1905 if (obj->madv != I915_MADV_WILLNEED) {
1906 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1911 ret = i915_gem_object_create_mmap_offset(obj);
1915 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1918 drm_gem_object_unreference(&obj->base);
1920 mutex_unlock(&dev->struct_mutex);
1925 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1927 * @data: GTT mapping ioctl data
1928 * @file: GEM object info
1930 * Simply returns the fake offset to userspace so it can mmap it.
1931 * The mmap call will end up in drm_gem_mmap(), which will set things
1932 * up so we can get faults in the handler above.
1934 * The fault handler will take care of binding the object into the GTT
1935 * (since it may have been evicted to make room for something), allocating
1936 * a fence register, and mapping the appropriate aperture address into
1940 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1941 struct drm_file *file)
1943 struct drm_i915_gem_mmap_gtt *args = data;
1945 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1948 /* Immediately discard the backing storage */
1950 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1952 i915_gem_object_free_mmap_offset(obj);
1954 if (obj->base.filp == NULL)
1957 /* Our goal here is to return as much of the memory as
1958 * is possible back to the system as we are called from OOM.
1959 * To do this we must instruct the shmfs to drop all of its
1960 * backing pages, *now*.
1962 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1963 obj->madv = __I915_MADV_PURGED;
1966 /* Try to discard unwanted pages */
1968 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1970 struct address_space *mapping;
1972 switch (obj->madv) {
1973 case I915_MADV_DONTNEED:
1974 i915_gem_object_truncate(obj);
1975 case __I915_MADV_PURGED:
1979 if (obj->base.filp == NULL)
1982 mapping = file_inode(obj->base.filp)->i_mapping,
1983 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1987 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1989 struct sg_page_iter sg_iter;
1992 BUG_ON(obj->madv == __I915_MADV_PURGED);
1994 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1996 /* In the event of a disaster, abandon all caches and
1997 * hope for the best.
1999 WARN_ON(ret != -EIO);
2000 i915_gem_clflush_object(obj, true);
2001 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2004 if (i915_gem_object_needs_bit17_swizzle(obj))
2005 i915_gem_object_save_bit_17_swizzle(obj);
2007 if (obj->madv == I915_MADV_DONTNEED)
2010 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2011 struct page *page = sg_page_iter_page(&sg_iter);
2014 set_page_dirty(page);
2016 if (obj->madv == I915_MADV_WILLNEED)
2017 mark_page_accessed(page);
2019 page_cache_release(page);
2023 sg_free_table(obj->pages);
2028 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2030 const struct drm_i915_gem_object_ops *ops = obj->ops;
2032 if (obj->pages == NULL)
2035 if (obj->pages_pin_count)
2038 BUG_ON(i915_gem_obj_bound_any(obj));
2040 /* ->put_pages might need to allocate memory for the bit17 swizzle
2041 * array, hence protect them from being reaped by removing them from gtt
2043 list_del(&obj->global_list);
2045 ops->put_pages(obj);
2048 i915_gem_object_invalidate(obj);
2054 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2056 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2058 struct address_space *mapping;
2059 struct sg_table *st;
2060 struct scatterlist *sg;
2061 struct sg_page_iter sg_iter;
2063 unsigned long last_pfn = 0; /* suppress gcc warning */
2066 /* Assert that the object is not currently in any GPU domain. As it
2067 * wasn't in the GTT, there shouldn't be any way it could have been in
2070 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2071 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2073 st = kmalloc(sizeof(*st), GFP_KERNEL);
2077 page_count = obj->base.size / PAGE_SIZE;
2078 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2083 /* Get the list of pages out of our struct file. They'll be pinned
2084 * at this point until we release them.
2086 * Fail silently without starting the shrinker
2088 mapping = file_inode(obj->base.filp)->i_mapping;
2089 gfp = mapping_gfp_mask(mapping);
2090 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2091 gfp &= ~(__GFP_IO | __GFP_WAIT);
2094 for (i = 0; i < page_count; i++) {
2095 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2097 i915_gem_shrink(dev_priv,
2100 I915_SHRINK_UNBOUND |
2101 I915_SHRINK_PURGEABLE);
2102 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2105 /* We've tried hard to allocate the memory by reaping
2106 * our own buffer, now let the real VM do its job and
2107 * go down in flames if truly OOM.
2109 i915_gem_shrink_all(dev_priv);
2110 page = shmem_read_mapping_page(mapping, i);
2114 #ifdef CONFIG_SWIOTLB
2115 if (swiotlb_nr_tbl()) {
2117 sg_set_page(sg, page, PAGE_SIZE, 0);
2122 if (!i || page_to_pfn(page) != last_pfn + 1) {
2126 sg_set_page(sg, page, PAGE_SIZE, 0);
2128 sg->length += PAGE_SIZE;
2130 last_pfn = page_to_pfn(page);
2132 /* Check that the i965g/gm workaround works. */
2133 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2135 #ifdef CONFIG_SWIOTLB
2136 if (!swiotlb_nr_tbl())
2141 if (i915_gem_object_needs_bit17_swizzle(obj))
2142 i915_gem_object_do_bit_17_swizzle(obj);
2144 if (obj->tiling_mode != I915_TILING_NONE &&
2145 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2146 i915_gem_object_pin_pages(obj);
2152 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2153 page_cache_release(sg_page_iter_page(&sg_iter));
2157 /* shmemfs first checks if there is enough memory to allocate the page
2158 * and reports ENOSPC should there be insufficient, along with the usual
2159 * ENOMEM for a genuine allocation failure.
2161 * We use ENOSPC in our driver to mean that we have run out of aperture
2162 * space and so want to translate the error from shmemfs back to our
2163 * usual understanding of ENOMEM.
2165 if (PTR_ERR(page) == -ENOSPC)
2168 return PTR_ERR(page);
2171 /* Ensure that the associated pages are gathered from the backing storage
2172 * and pinned into our object. i915_gem_object_get_pages() may be called
2173 * multiple times before they are released by a single call to
2174 * i915_gem_object_put_pages() - once the pages are no longer referenced
2175 * either as a result of memory pressure (reaping pages under the shrinker)
2176 * or as the object is itself released.
2179 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2181 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182 const struct drm_i915_gem_object_ops *ops = obj->ops;
2188 if (obj->madv != I915_MADV_WILLNEED) {
2189 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2193 BUG_ON(obj->pages_pin_count);
2195 ret = ops->get_pages(obj);
2199 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2201 obj->get_page.sg = obj->pages->sgl;
2202 obj->get_page.last = 0;
2208 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2209 struct intel_engine_cs *ring)
2211 struct drm_i915_gem_request *req;
2212 struct intel_engine_cs *old_ring;
2214 BUG_ON(ring == NULL);
2216 req = intel_ring_get_request(ring);
2217 old_ring = i915_gem_request_get_ring(obj->last_read_req);
2219 if (old_ring != ring && obj->last_write_req) {
2220 /* Keep the request relative to the current ring */
2221 i915_gem_request_assign(&obj->last_write_req, req);
2224 /* Add a reference if we're newly entering the active list. */
2226 drm_gem_object_reference(&obj->base);
2230 list_move_tail(&obj->ring_list, &ring->active_list);
2232 i915_gem_request_assign(&obj->last_read_req, req);
2235 void i915_vma_move_to_active(struct i915_vma *vma,
2236 struct intel_engine_cs *ring)
2238 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2239 return i915_gem_object_move_to_active(vma->obj, ring);
2243 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2245 struct i915_vma *vma;
2247 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2248 BUG_ON(!obj->active);
2250 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2251 if (!list_empty(&vma->mm_list))
2252 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2255 intel_fb_obj_flush(obj, true);
2257 list_del_init(&obj->ring_list);
2259 i915_gem_request_assign(&obj->last_read_req, NULL);
2260 i915_gem_request_assign(&obj->last_write_req, NULL);
2261 obj->base.write_domain = 0;
2263 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2266 drm_gem_object_unreference(&obj->base);
2268 WARN_ON(i915_verify_lists(dev));
2272 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2274 if (obj->last_read_req == NULL)
2277 if (i915_gem_request_completed(obj->last_read_req, true))
2278 i915_gem_object_move_to_inactive(obj);
2282 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct intel_engine_cs *ring;
2288 /* Carefully retire all requests without writing to the rings */
2289 for_each_ring(ring, dev_priv, i) {
2290 ret = intel_ring_idle(ring);
2294 i915_gem_retire_requests(dev);
2296 /* Finally reset hw state */
2297 for_each_ring(ring, dev_priv, i) {
2298 intel_ring_init_seqno(ring, seqno);
2300 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2301 ring->semaphore.sync_seqno[j] = 0;
2307 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2315 /* HWS page needs to be set less than what we
2316 * will inject to ring
2318 ret = i915_gem_init_seqno(dev, seqno - 1);
2322 /* Carefully set the last_seqno value so that wrap
2323 * detection still works
2325 dev_priv->next_seqno = seqno;
2326 dev_priv->last_seqno = seqno - 1;
2327 if (dev_priv->last_seqno == 0)
2328 dev_priv->last_seqno--;
2334 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2338 /* reserve 0 for non-seqno */
2339 if (dev_priv->next_seqno == 0) {
2340 int ret = i915_gem_init_seqno(dev, 0);
2344 dev_priv->next_seqno = 1;
2347 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2351 int __i915_add_request(struct intel_engine_cs *ring,
2352 struct drm_file *file,
2353 struct drm_i915_gem_object *obj)
2355 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2356 struct drm_i915_gem_request *request;
2357 struct intel_ringbuffer *ringbuf;
2361 request = ring->outstanding_lazy_request;
2362 if (WARN_ON(request == NULL))
2365 if (i915.enable_execlists) {
2366 ringbuf = request->ctx->engine[ring->id].ringbuf;
2368 ringbuf = ring->buffer;
2370 request_start = intel_ring_get_tail(ringbuf);
2372 * Emit any outstanding flushes - execbuf can fail to emit the flush
2373 * after having emitted the batchbuffer command. Hence we need to fix
2374 * things up similar to emitting the lazy request. The difference here
2375 * is that the flush _must_ happen before the next request, no matter
2378 if (i915.enable_execlists) {
2379 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2383 ret = intel_ring_flush_all_caches(ring);
2388 /* Record the position of the start of the request so that
2389 * should we detect the updated seqno part-way through the
2390 * GPU processing the request, we never over-estimate the
2391 * position of the head.
2393 request->postfix = intel_ring_get_tail(ringbuf);
2395 if (i915.enable_execlists) {
2396 ret = ring->emit_request(ringbuf, request);
2400 ret = ring->add_request(ring);
2404 request->tail = intel_ring_get_tail(ringbuf);
2407 request->head = request_start;
2409 /* Whilst this request exists, batch_obj will be on the
2410 * active_list, and so will hold the active reference. Only when this
2411 * request is retired will the the batch_obj be moved onto the
2412 * inactive_list and lose its active reference. Hence we do not need
2413 * to explicitly hold another reference here.
2415 request->batch_obj = obj;
2417 if (!i915.enable_execlists) {
2418 /* Hold a reference to the current context so that we can inspect
2419 * it later in case a hangcheck error event fires.
2421 request->ctx = ring->last_context;
2423 i915_gem_context_reference(request->ctx);
2426 request->emitted_jiffies = jiffies;
2427 list_add_tail(&request->list, &ring->request_list);
2428 request->file_priv = NULL;
2431 struct drm_i915_file_private *file_priv = file->driver_priv;
2433 spin_lock(&file_priv->mm.lock);
2434 request->file_priv = file_priv;
2435 list_add_tail(&request->client_list,
2436 &file_priv->mm.request_list);
2437 spin_unlock(&file_priv->mm.lock);
2439 request->pid = get_pid(task_pid(current));
2442 trace_i915_gem_request_add(request);
2443 ring->outstanding_lazy_request = NULL;
2445 i915_queue_hangcheck(ring->dev);
2447 queue_delayed_work(dev_priv->wq,
2448 &dev_priv->mm.retire_work,
2449 round_jiffies_up_relative(HZ));
2450 intel_mark_busy(dev_priv->dev);
2456 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2458 struct drm_i915_file_private *file_priv = request->file_priv;
2463 spin_lock(&file_priv->mm.lock);
2464 list_del(&request->client_list);
2465 request->file_priv = NULL;
2466 spin_unlock(&file_priv->mm.lock);
2469 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2470 const struct intel_context *ctx)
2472 unsigned long elapsed;
2474 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2476 if (ctx->hang_stats.banned)
2479 if (ctx->hang_stats.ban_period_seconds &&
2480 elapsed <= ctx->hang_stats.ban_period_seconds) {
2481 if (!i915_gem_context_is_default(ctx)) {
2482 DRM_DEBUG("context hanging too fast, banning!\n");
2484 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2485 if (i915_stop_ring_allow_warn(dev_priv))
2486 DRM_ERROR("gpu hanging too fast, banning!\n");
2494 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2495 struct intel_context *ctx,
2498 struct i915_ctx_hang_stats *hs;
2503 hs = &ctx->hang_stats;
2506 hs->banned = i915_context_is_banned(dev_priv, ctx);
2508 hs->guilty_ts = get_seconds();
2510 hs->batch_pending++;
2514 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2516 list_del(&request->list);
2517 i915_gem_request_remove_from_client(request);
2519 put_pid(request->pid);
2521 i915_gem_request_unreference(request);
2524 void i915_gem_request_free(struct kref *req_ref)
2526 struct drm_i915_gem_request *req = container_of(req_ref,
2528 struct intel_context *ctx = req->ctx;
2531 if (i915.enable_execlists) {
2532 struct intel_engine_cs *ring = req->ring;
2534 if (ctx != ring->default_context)
2535 intel_lr_context_unpin(ring, ctx);
2538 i915_gem_context_unreference(ctx);
2541 kmem_cache_free(req->i915->requests, req);
2544 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2545 struct intel_context *ctx)
2547 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2548 struct drm_i915_gem_request *rq;
2551 if (ring->outstanding_lazy_request)
2554 rq = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2558 kref_init(&rq->ref);
2559 rq->i915 = dev_priv;
2561 ret = i915_gem_get_seqno(ring->dev, &rq->seqno);
2569 if (i915.enable_execlists)
2570 ret = intel_logical_ring_alloc_request_extras(rq, ctx);
2572 ret = intel_ring_alloc_request_extras(rq);
2578 ring->outstanding_lazy_request = rq;
2582 struct drm_i915_gem_request *
2583 i915_gem_find_active_request(struct intel_engine_cs *ring)
2585 struct drm_i915_gem_request *request;
2587 list_for_each_entry(request, &ring->request_list, list) {
2588 if (i915_gem_request_completed(request, false))
2597 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2598 struct intel_engine_cs *ring)
2600 struct drm_i915_gem_request *request;
2603 request = i915_gem_find_active_request(ring);
2605 if (request == NULL)
2608 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2610 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2612 list_for_each_entry_continue(request, &ring->request_list, list)
2613 i915_set_reset_status(dev_priv, request->ctx, false);
2616 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2617 struct intel_engine_cs *ring)
2619 while (!list_empty(&ring->active_list)) {
2620 struct drm_i915_gem_object *obj;
2622 obj = list_first_entry(&ring->active_list,
2623 struct drm_i915_gem_object,
2626 i915_gem_object_move_to_inactive(obj);
2630 * Clear the execlists queue up before freeing the requests, as those
2631 * are the ones that keep the context and ringbuffer backing objects
2634 while (!list_empty(&ring->execlist_queue)) {
2635 struct drm_i915_gem_request *submit_req;
2637 submit_req = list_first_entry(&ring->execlist_queue,
2638 struct drm_i915_gem_request,
2640 list_del(&submit_req->execlist_link);
2642 if (submit_req->ctx != ring->default_context)
2643 intel_lr_context_unpin(ring, submit_req->ctx);
2645 i915_gem_request_unreference(submit_req);
2649 * We must free the requests after all the corresponding objects have
2650 * been moved off active lists. Which is the same order as the normal
2651 * retire_requests function does. This is important if object hold
2652 * implicit references on things like e.g. ppgtt address spaces through
2655 while (!list_empty(&ring->request_list)) {
2656 struct drm_i915_gem_request *request;
2658 request = list_first_entry(&ring->request_list,
2659 struct drm_i915_gem_request,
2662 i915_gem_free_request(request);
2665 /* This may not have been flushed before the reset, so clean it now */
2666 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2669 void i915_gem_restore_fences(struct drm_device *dev)
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2674 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2675 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2678 * Commit delayed tiling changes if we have an object still
2679 * attached to the fence, otherwise just clear the fence.
2682 i915_gem_object_update_fence(reg->obj, reg,
2683 reg->obj->tiling_mode);
2685 i915_gem_write_fence(dev, i, NULL);
2690 void i915_gem_reset(struct drm_device *dev)
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 struct intel_engine_cs *ring;
2697 * Before we free the objects from the requests, we need to inspect
2698 * them for finding the guilty party. As the requests only borrow
2699 * their reference to the objects, the inspection must be done first.
2701 for_each_ring(ring, dev_priv, i)
2702 i915_gem_reset_ring_status(dev_priv, ring);
2704 for_each_ring(ring, dev_priv, i)
2705 i915_gem_reset_ring_cleanup(dev_priv, ring);
2707 i915_gem_context_reset(dev);
2709 i915_gem_restore_fences(dev);
2713 * This function clears the request list as sequence numbers are passed.
2716 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2718 if (list_empty(&ring->request_list))
2721 WARN_ON(i915_verify_lists(ring->dev));
2723 /* Retire requests first as we use it above for the early return.
2724 * If we retire requests last, we may use a later seqno and so clear
2725 * the requests lists without clearing the active list, leading to
2728 while (!list_empty(&ring->request_list)) {
2729 struct drm_i915_gem_request *request;
2731 request = list_first_entry(&ring->request_list,
2732 struct drm_i915_gem_request,
2735 if (!i915_gem_request_completed(request, true))
2738 trace_i915_gem_request_retire(request);
2740 /* We know the GPU must have read the request to have
2741 * sent us the seqno + interrupt, so use the position
2742 * of tail of the request to update the last known position
2745 request->ringbuf->last_retired_head = request->postfix;
2747 i915_gem_free_request(request);
2750 /* Move any buffers on the active list that are no longer referenced
2751 * by the ringbuffer to the flushing/inactive lists as appropriate,
2752 * before we free the context associated with the requests.
2754 while (!list_empty(&ring->active_list)) {
2755 struct drm_i915_gem_object *obj;
2757 obj = list_first_entry(&ring->active_list,
2758 struct drm_i915_gem_object,
2761 if (!i915_gem_request_completed(obj->last_read_req, true))
2764 i915_gem_object_move_to_inactive(obj);
2767 if (unlikely(ring->trace_irq_req &&
2768 i915_gem_request_completed(ring->trace_irq_req, true))) {
2769 ring->irq_put(ring);
2770 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2773 WARN_ON(i915_verify_lists(ring->dev));
2777 i915_gem_retire_requests(struct drm_device *dev)
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 struct intel_engine_cs *ring;
2784 for_each_ring(ring, dev_priv, i) {
2785 i915_gem_retire_requests_ring(ring);
2786 idle &= list_empty(&ring->request_list);
2787 if (i915.enable_execlists) {
2788 unsigned long flags;
2790 spin_lock_irqsave(&ring->execlist_lock, flags);
2791 idle &= list_empty(&ring->execlist_queue);
2792 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2794 intel_execlists_retire_requests(ring);
2799 mod_delayed_work(dev_priv->wq,
2800 &dev_priv->mm.idle_work,
2801 msecs_to_jiffies(100));
2807 i915_gem_retire_work_handler(struct work_struct *work)
2809 struct drm_i915_private *dev_priv =
2810 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2811 struct drm_device *dev = dev_priv->dev;
2814 /* Come back later if the device is busy... */
2816 if (mutex_trylock(&dev->struct_mutex)) {
2817 idle = i915_gem_retire_requests(dev);
2818 mutex_unlock(&dev->struct_mutex);
2821 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2822 round_jiffies_up_relative(HZ));
2826 i915_gem_idle_work_handler(struct work_struct *work)
2828 struct drm_i915_private *dev_priv =
2829 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2830 struct drm_device *dev = dev_priv->dev;
2831 struct intel_engine_cs *ring;
2834 for_each_ring(ring, dev_priv, i)
2835 if (!list_empty(&ring->request_list))
2838 intel_mark_idle(dev);
2840 if (mutex_trylock(&dev->struct_mutex)) {
2841 struct intel_engine_cs *ring;
2844 for_each_ring(ring, dev_priv, i)
2845 i915_gem_batch_pool_fini(&ring->batch_pool);
2847 mutex_unlock(&dev->struct_mutex);
2852 * Ensures that an object will eventually get non-busy by flushing any required
2853 * write domains, emitting any outstanding lazy request and retiring and
2854 * completed requests.
2857 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2859 struct intel_engine_cs *ring;
2863 ring = i915_gem_request_get_ring(obj->last_read_req);
2865 ret = i915_gem_check_olr(obj->last_read_req);
2869 i915_gem_retire_requests_ring(ring);
2876 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2877 * @DRM_IOCTL_ARGS: standard ioctl arguments
2879 * Returns 0 if successful, else an error is returned with the remaining time in
2880 * the timeout parameter.
2881 * -ETIME: object is still busy after timeout
2882 * -ERESTARTSYS: signal interrupted the wait
2883 * -ENONENT: object doesn't exist
2884 * Also possible, but rare:
2885 * -EAGAIN: GPU wedged
2887 * -ENODEV: Internal IRQ fail
2888 * -E?: The add request failed
2890 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2891 * non-zero timeout parameter the wait ioctl will wait for the given number of
2892 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2893 * without holding struct_mutex the object may become re-busied before this
2894 * function completes. A similar but shorter * race condition exists in the busy
2898 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2900 struct drm_i915_private *dev_priv = dev->dev_private;
2901 struct drm_i915_gem_wait *args = data;
2902 struct drm_i915_gem_object *obj;
2903 struct drm_i915_gem_request *req;
2904 unsigned reset_counter;
2907 if (args->flags != 0)
2910 ret = i915_mutex_lock_interruptible(dev);
2914 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2915 if (&obj->base == NULL) {
2916 mutex_unlock(&dev->struct_mutex);
2920 /* Need to make sure the object gets inactive eventually. */
2921 ret = i915_gem_object_flush_active(obj);
2925 if (!obj->active || !obj->last_read_req)
2928 req = obj->last_read_req;
2930 /* Do this after OLR check to make sure we make forward progress polling
2931 * on this IOCTL with a timeout == 0 (like busy ioctl)
2933 if (args->timeout_ns == 0) {
2938 drm_gem_object_unreference(&obj->base);
2939 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2940 i915_gem_request_reference(req);
2941 mutex_unlock(&dev->struct_mutex);
2943 ret = __i915_wait_request(req, reset_counter, true,
2944 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
2946 i915_gem_request_unreference__unlocked(req);
2950 drm_gem_object_unreference(&obj->base);
2951 mutex_unlock(&dev->struct_mutex);
2956 * i915_gem_object_sync - sync an object to a ring.
2958 * @obj: object which may be in use on another ring.
2959 * @to: ring we wish to use the object on. May be NULL.
2961 * This code is meant to abstract object synchronization with the GPU.
2962 * Calling with NULL implies synchronizing the object with the CPU
2963 * rather than a particular GPU ring.
2965 * Returns 0 if successful, else propagates up the lower layer error.
2968 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2969 struct intel_engine_cs *to)
2971 struct intel_engine_cs *from;
2975 from = i915_gem_request_get_ring(obj->last_read_req);
2977 if (from == NULL || to == from)
2980 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2981 return i915_gem_object_wait_rendering(obj, false);
2983 idx = intel_ring_sync_index(from, to);
2985 seqno = i915_gem_request_get_seqno(obj->last_read_req);
2986 /* Optimization: Avoid semaphore sync when we are sure we already
2987 * waited for an object with higher seqno */
2988 if (seqno <= from->semaphore.sync_seqno[idx])
2991 ret = i915_gem_check_olr(obj->last_read_req);
2995 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
2996 ret = to->semaphore.sync_to(to, from, seqno);
2998 /* We use last_read_req because sync_to()
2999 * might have just caused seqno wrap under
3002 from->semaphore.sync_seqno[idx] =
3003 i915_gem_request_get_seqno(obj->last_read_req);
3008 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3010 u32 old_write_domain, old_read_domains;
3012 /* Force a pagefault for domain tracking on next user access */
3013 i915_gem_release_mmap(obj);
3015 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3018 /* Wait for any direct GTT access to complete */
3021 old_read_domains = obj->base.read_domains;
3022 old_write_domain = obj->base.write_domain;
3024 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3025 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3027 trace_i915_gem_object_change_domain(obj,
3032 int i915_vma_unbind(struct i915_vma *vma)
3034 struct drm_i915_gem_object *obj = vma->obj;
3035 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3038 if (list_empty(&vma->vma_link))
3041 if (!drm_mm_node_allocated(&vma->node)) {
3042 i915_gem_vma_destroy(vma);
3049 BUG_ON(obj->pages == NULL);
3051 ret = i915_gem_object_finish_gpu(obj);
3054 /* Continue on if we fail due to EIO, the GPU is hung so we
3055 * should be safe and we need to cleanup or else we might
3056 * cause memory corruption through use-after-free.
3059 if (i915_is_ggtt(vma->vm) &&
3060 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3061 i915_gem_object_finish_gtt(obj);
3063 /* release the fence reg _after_ flushing */
3064 ret = i915_gem_object_put_fence(obj);
3069 trace_i915_vma_unbind(vma);
3071 vma->vm->unbind_vma(vma);
3074 list_del_init(&vma->mm_list);
3075 if (i915_is_ggtt(vma->vm)) {
3076 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3077 obj->map_and_fenceable = false;
3078 } else if (vma->ggtt_view.pages) {
3079 sg_free_table(vma->ggtt_view.pages);
3080 kfree(vma->ggtt_view.pages);
3081 vma->ggtt_view.pages = NULL;
3085 drm_mm_remove_node(&vma->node);
3086 i915_gem_vma_destroy(vma);
3088 /* Since the unbound list is global, only move to that list if
3089 * no more VMAs exist. */
3090 if (list_empty(&obj->vma_list)) {
3091 /* Throw away the active reference before
3092 * moving to the unbound list. */
3093 i915_gem_object_retire(obj);
3095 i915_gem_gtt_finish_object(obj);
3096 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3099 /* And finally now the object is completely decoupled from this vma,
3100 * we can drop its hold on the backing storage and allow it to be
3101 * reaped by the shrinker.
3103 i915_gem_object_unpin_pages(obj);
3108 int i915_gpu_idle(struct drm_device *dev)
3110 struct drm_i915_private *dev_priv = dev->dev_private;
3111 struct intel_engine_cs *ring;
3114 /* Flush everything onto the inactive list. */
3115 for_each_ring(ring, dev_priv, i) {
3116 if (!i915.enable_execlists) {
3117 ret = i915_switch_context(ring, ring->default_context);
3122 ret = intel_ring_idle(ring);
3130 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3131 struct drm_i915_gem_object *obj)
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3135 int fence_pitch_shift;
3137 if (INTEL_INFO(dev)->gen >= 6) {
3138 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3139 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3141 fence_reg = FENCE_REG_965_0;
3142 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3145 fence_reg += reg * 8;
3147 /* To w/a incoherency with non-atomic 64-bit register updates,
3148 * we split the 64-bit update into two 32-bit writes. In order
3149 * for a partial fence not to be evaluated between writes, we
3150 * precede the update with write to turn off the fence register,
3151 * and only enable the fence as the last step.
3153 * For extra levels of paranoia, we make sure each step lands
3154 * before applying the next step.
3156 I915_WRITE(fence_reg, 0);
3157 POSTING_READ(fence_reg);
3160 u32 size = i915_gem_obj_ggtt_size(obj);
3163 /* Adjust fence size to match tiled area */
3164 if (obj->tiling_mode != I915_TILING_NONE) {
3165 uint32_t row_size = obj->stride *
3166 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3167 size = (size / row_size) * row_size;
3170 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3172 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3173 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3174 if (obj->tiling_mode == I915_TILING_Y)
3175 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3176 val |= I965_FENCE_REG_VALID;
3178 I915_WRITE(fence_reg + 4, val >> 32);
3179 POSTING_READ(fence_reg + 4);
3181 I915_WRITE(fence_reg + 0, val);
3182 POSTING_READ(fence_reg);
3184 I915_WRITE(fence_reg + 4, 0);
3185 POSTING_READ(fence_reg + 4);
3189 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3190 struct drm_i915_gem_object *obj)
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3196 u32 size = i915_gem_obj_ggtt_size(obj);
3200 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3201 (size & -size) != size ||
3202 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3203 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3204 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3206 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3211 /* Note: pitch better be a power of two tile widths */
3212 pitch_val = obj->stride / tile_width;
3213 pitch_val = ffs(pitch_val) - 1;
3215 val = i915_gem_obj_ggtt_offset(obj);
3216 if (obj->tiling_mode == I915_TILING_Y)
3217 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3218 val |= I915_FENCE_SIZE_BITS(size);
3219 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3220 val |= I830_FENCE_REG_VALID;
3225 reg = FENCE_REG_830_0 + reg * 4;
3227 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3229 I915_WRITE(reg, val);
3233 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3234 struct drm_i915_gem_object *obj)
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3240 u32 size = i915_gem_obj_ggtt_size(obj);
3243 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3244 (size & -size) != size ||
3245 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3246 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3247 i915_gem_obj_ggtt_offset(obj), size);
3249 pitch_val = obj->stride / 128;
3250 pitch_val = ffs(pitch_val) - 1;
3252 val = i915_gem_obj_ggtt_offset(obj);
3253 if (obj->tiling_mode == I915_TILING_Y)
3254 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3255 val |= I830_FENCE_SIZE_BITS(size);
3256 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3257 val |= I830_FENCE_REG_VALID;
3261 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3262 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3265 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3267 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3270 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3271 struct drm_i915_gem_object *obj)
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3275 /* Ensure that all CPU reads are completed before installing a fence
3276 * and all writes before removing the fence.
3278 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3281 WARN(obj && (!obj->stride || !obj->tiling_mode),
3282 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3283 obj->stride, obj->tiling_mode);
3286 i830_write_fence_reg(dev, reg, obj);
3287 else if (IS_GEN3(dev))
3288 i915_write_fence_reg(dev, reg, obj);
3289 else if (INTEL_INFO(dev)->gen >= 4)
3290 i965_write_fence_reg(dev, reg, obj);
3292 /* And similarly be paranoid that no direct access to this region
3293 * is reordered to before the fence is installed.
3295 if (i915_gem_object_needs_mb(obj))
3299 static inline int fence_number(struct drm_i915_private *dev_priv,
3300 struct drm_i915_fence_reg *fence)
3302 return fence - dev_priv->fence_regs;
3305 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3306 struct drm_i915_fence_reg *fence,
3309 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3310 int reg = fence_number(dev_priv, fence);
3312 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3315 obj->fence_reg = reg;
3317 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3319 obj->fence_reg = I915_FENCE_REG_NONE;
3321 list_del_init(&fence->lru_list);
3323 obj->fence_dirty = false;
3327 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3329 if (obj->last_fenced_req) {
3330 int ret = i915_wait_request(obj->last_fenced_req);
3334 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3341 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3343 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3344 struct drm_i915_fence_reg *fence;
3347 ret = i915_gem_object_wait_fence(obj);
3351 if (obj->fence_reg == I915_FENCE_REG_NONE)
3354 fence = &dev_priv->fence_regs[obj->fence_reg];
3356 if (WARN_ON(fence->pin_count))
3359 i915_gem_object_fence_lost(obj);
3360 i915_gem_object_update_fence(obj, fence, false);
3365 static struct drm_i915_fence_reg *
3366 i915_find_fence_reg(struct drm_device *dev)
3368 struct drm_i915_private *dev_priv = dev->dev_private;
3369 struct drm_i915_fence_reg *reg, *avail;
3372 /* First try to find a free reg */
3374 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3375 reg = &dev_priv->fence_regs[i];
3379 if (!reg->pin_count)
3386 /* None available, try to steal one or wait for a user to finish */
3387 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3395 /* Wait for completion of pending flips which consume fences */
3396 if (intel_has_pending_fb_unpin(dev))
3397 return ERR_PTR(-EAGAIN);
3399 return ERR_PTR(-EDEADLK);
3403 * i915_gem_object_get_fence - set up fencing for an object
3404 * @obj: object to map through a fence reg
3406 * When mapping objects through the GTT, userspace wants to be able to write
3407 * to them without having to worry about swizzling if the object is tiled.
3408 * This function walks the fence regs looking for a free one for @obj,
3409 * stealing one if it can't find any.
3411 * It then sets up the reg based on the object's properties: address, pitch
3412 * and tiling format.
3414 * For an untiled surface, this removes any existing fence.
3417 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3419 struct drm_device *dev = obj->base.dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 bool enable = obj->tiling_mode != I915_TILING_NONE;
3422 struct drm_i915_fence_reg *reg;
3425 /* Have we updated the tiling parameters upon the object and so
3426 * will need to serialise the write to the associated fence register?
3428 if (obj->fence_dirty) {
3429 ret = i915_gem_object_wait_fence(obj);
3434 /* Just update our place in the LRU if our fence is getting reused. */
3435 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3436 reg = &dev_priv->fence_regs[obj->fence_reg];
3437 if (!obj->fence_dirty) {
3438 list_move_tail(®->lru_list,
3439 &dev_priv->mm.fence_list);
3442 } else if (enable) {
3443 if (WARN_ON(!obj->map_and_fenceable))
3446 reg = i915_find_fence_reg(dev);
3448 return PTR_ERR(reg);
3451 struct drm_i915_gem_object *old = reg->obj;
3453 ret = i915_gem_object_wait_fence(old);
3457 i915_gem_object_fence_lost(old);
3462 i915_gem_object_update_fence(obj, reg, enable);
3467 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3468 unsigned long cache_level)
3470 struct drm_mm_node *gtt_space = &vma->node;
3471 struct drm_mm_node *other;
3474 * On some machines we have to be careful when putting differing types
3475 * of snoopable memory together to avoid the prefetcher crossing memory
3476 * domains and dying. During vm initialisation, we decide whether or not
3477 * these constraints apply and set the drm_mm.color_adjust
3480 if (vma->vm->mm.color_adjust == NULL)
3483 if (!drm_mm_node_allocated(gtt_space))
3486 if (list_empty(>t_space->node_list))
3489 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3490 if (other->allocated && !other->hole_follows && other->color != cache_level)
3493 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3494 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3501 * Finds free space in the GTT aperture and binds the object or a view of it
3504 static struct i915_vma *
3505 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3506 struct i915_address_space *vm,
3507 const struct i915_ggtt_view *ggtt_view,
3511 struct drm_device *dev = obj->base.dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 u32 size, fence_size, fence_alignment, unfenced_alignment;
3514 unsigned long start =
3515 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3517 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3518 struct i915_vma *vma;
3521 if (i915_is_ggtt(vm)) {
3524 if (WARN_ON(!ggtt_view))
3525 return ERR_PTR(-EINVAL);
3527 view_size = i915_ggtt_view_size(obj, ggtt_view);
3529 fence_size = i915_gem_get_gtt_size(dev,
3532 fence_alignment = i915_gem_get_gtt_alignment(dev,
3536 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3540 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3542 fence_size = i915_gem_get_gtt_size(dev,
3545 fence_alignment = i915_gem_get_gtt_alignment(dev,
3549 unfenced_alignment =
3550 i915_gem_get_gtt_alignment(dev,
3554 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3558 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3560 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3561 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3562 ggtt_view ? ggtt_view->type : 0,
3564 return ERR_PTR(-EINVAL);
3567 /* If binding the object/GGTT view requires more space than the entire
3568 * aperture has, reject it early before evicting everything in a vain
3569 * attempt to find space.
3572 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3573 ggtt_view ? ggtt_view->type : 0,
3575 flags & PIN_MAPPABLE ? "mappable" : "total",
3577 return ERR_PTR(-E2BIG);
3580 ret = i915_gem_object_get_pages(obj);
3582 return ERR_PTR(ret);
3584 i915_gem_object_pin_pages(obj);
3586 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3587 i915_gem_obj_lookup_or_create_vma(obj, vm);
3593 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3597 DRM_MM_SEARCH_DEFAULT,
3598 DRM_MM_CREATE_DEFAULT);
3600 ret = i915_gem_evict_something(dev, vm, size, alignment,
3609 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3611 goto err_remove_node;
3614 ret = i915_gem_gtt_prepare_object(obj);
3616 goto err_remove_node;
3618 trace_i915_vma_bind(vma, flags);
3619 ret = i915_vma_bind(vma, obj->cache_level, flags);
3621 goto err_finish_gtt;
3623 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3624 list_add_tail(&vma->mm_list, &vm->inactive_list);
3629 i915_gem_gtt_finish_object(obj);
3631 drm_mm_remove_node(&vma->node);
3633 i915_gem_vma_destroy(vma);
3636 i915_gem_object_unpin_pages(obj);
3641 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3644 /* If we don't have a page list set up, then we're not pinned
3645 * to GPU, and we can ignore the cache flush because it'll happen
3646 * again at bind time.
3648 if (obj->pages == NULL)
3652 * Stolen memory is always coherent with the GPU as it is explicitly
3653 * marked as wc by the system, or the system is cache-coherent.
3655 if (obj->stolen || obj->phys_handle)
3658 /* If the GPU is snooping the contents of the CPU cache,
3659 * we do not need to manually clear the CPU cache lines. However,
3660 * the caches are only snooped when the render cache is
3661 * flushed/invalidated. As we always have to emit invalidations
3662 * and flushes when moving into and out of the RENDER domain, correct
3663 * snooping behaviour occurs naturally as the result of our domain
3666 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3667 obj->cache_dirty = true;
3671 trace_i915_gem_object_clflush(obj);
3672 drm_clflush_sg(obj->pages);
3673 obj->cache_dirty = false;
3678 /** Flushes the GTT write domain for the object if it's dirty. */
3680 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3682 uint32_t old_write_domain;
3684 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3687 /* No actual flushing is required for the GTT write domain. Writes
3688 * to it immediately go to main memory as far as we know, so there's
3689 * no chipset flush. It also doesn't land in render cache.
3691 * However, we do have to enforce the order so that all writes through
3692 * the GTT land before any writes to the device, such as updates to
3697 old_write_domain = obj->base.write_domain;
3698 obj->base.write_domain = 0;
3700 intel_fb_obj_flush(obj, false);
3702 trace_i915_gem_object_change_domain(obj,
3703 obj->base.read_domains,
3707 /** Flushes the CPU write domain for the object if it's dirty. */
3709 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3711 uint32_t old_write_domain;
3713 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3716 if (i915_gem_clflush_object(obj, obj->pin_display))
3717 i915_gem_chipset_flush(obj->base.dev);
3719 old_write_domain = obj->base.write_domain;
3720 obj->base.write_domain = 0;
3722 intel_fb_obj_flush(obj, false);
3724 trace_i915_gem_object_change_domain(obj,
3725 obj->base.read_domains,
3730 * Moves a single object to the GTT read, and possibly write domain.
3732 * This function returns when the move is complete, including waiting on
3736 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3738 uint32_t old_write_domain, old_read_domains;
3739 struct i915_vma *vma;
3742 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3745 ret = i915_gem_object_wait_rendering(obj, !write);
3749 i915_gem_object_retire(obj);
3751 /* Flush and acquire obj->pages so that we are coherent through
3752 * direct access in memory with previous cached writes through
3753 * shmemfs and that our cache domain tracking remains valid.
3754 * For example, if the obj->filp was moved to swap without us
3755 * being notified and releasing the pages, we would mistakenly
3756 * continue to assume that the obj remained out of the CPU cached
3759 ret = i915_gem_object_get_pages(obj);
3763 i915_gem_object_flush_cpu_write_domain(obj);
3765 /* Serialise direct access to this object with the barriers for
3766 * coherent writes from the GPU, by effectively invalidating the
3767 * GTT domain upon first access.
3769 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3772 old_write_domain = obj->base.write_domain;
3773 old_read_domains = obj->base.read_domains;
3775 /* It should now be out of any other write domains, and we can update
3776 * the domain values for our changes.
3778 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3779 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3781 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3782 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3787 intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
3789 trace_i915_gem_object_change_domain(obj,
3793 /* And bump the LRU for this access */
3794 vma = i915_gem_obj_to_ggtt(obj);
3795 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3796 list_move_tail(&vma->mm_list,
3797 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3802 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3803 enum i915_cache_level cache_level)
3805 struct drm_device *dev = obj->base.dev;
3806 struct i915_vma *vma, *next;
3809 if (obj->cache_level == cache_level)
3812 if (i915_gem_obj_is_pinned(obj)) {
3813 DRM_DEBUG("can not change the cache level of pinned objects\n");
3817 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3818 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3819 ret = i915_vma_unbind(vma);
3825 if (i915_gem_obj_bound_any(obj)) {
3826 ret = i915_gem_object_finish_gpu(obj);
3830 i915_gem_object_finish_gtt(obj);
3832 /* Before SandyBridge, you could not use tiling or fence
3833 * registers with snooped memory, so relinquish any fences
3834 * currently pointing to our region in the aperture.
3836 if (INTEL_INFO(dev)->gen < 6) {
3837 ret = i915_gem_object_put_fence(obj);
3842 list_for_each_entry(vma, &obj->vma_list, vma_link)
3843 if (drm_mm_node_allocated(&vma->node)) {
3844 ret = i915_vma_bind(vma, cache_level,
3851 list_for_each_entry(vma, &obj->vma_list, vma_link)
3852 vma->node.color = cache_level;
3853 obj->cache_level = cache_level;
3855 if (obj->cache_dirty &&
3856 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3857 cpu_write_needs_clflush(obj)) {
3858 if (i915_gem_clflush_object(obj, true))
3859 i915_gem_chipset_flush(obj->base.dev);
3865 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3866 struct drm_file *file)
3868 struct drm_i915_gem_caching *args = data;
3869 struct drm_i915_gem_object *obj;
3871 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3872 if (&obj->base == NULL)
3875 switch (obj->cache_level) {
3876 case I915_CACHE_LLC:
3877 case I915_CACHE_L3_LLC:
3878 args->caching = I915_CACHING_CACHED;
3882 args->caching = I915_CACHING_DISPLAY;
3886 args->caching = I915_CACHING_NONE;
3890 drm_gem_object_unreference_unlocked(&obj->base);
3894 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3895 struct drm_file *file)
3897 struct drm_i915_gem_caching *args = data;
3898 struct drm_i915_gem_object *obj;
3899 enum i915_cache_level level;
3902 switch (args->caching) {
3903 case I915_CACHING_NONE:
3904 level = I915_CACHE_NONE;
3906 case I915_CACHING_CACHED:
3907 level = I915_CACHE_LLC;
3909 case I915_CACHING_DISPLAY:
3910 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3916 ret = i915_mutex_lock_interruptible(dev);
3920 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3921 if (&obj->base == NULL) {
3926 ret = i915_gem_object_set_cache_level(obj, level);
3928 drm_gem_object_unreference(&obj->base);
3930 mutex_unlock(&dev->struct_mutex);
3935 * Prepare buffer for display plane (scanout, cursors, etc).
3936 * Can be called from an uninterruptible phase (modesetting) and allows
3937 * any flushes to be pipelined (for pageflips).
3940 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3942 struct intel_engine_cs *pipelined,
3943 const struct i915_ggtt_view *view)
3945 u32 old_read_domains, old_write_domain;
3948 if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3949 ret = i915_gem_object_sync(obj, pipelined);
3954 /* Mark the pin_display early so that we account for the
3955 * display coherency whilst setting up the cache domains.
3959 /* The display engine is not coherent with the LLC cache on gen6. As
3960 * a result, we make sure that the pinning that is about to occur is
3961 * done with uncached PTEs. This is lowest common denominator for all
3964 * However for gen6+, we could do better by using the GFDT bit instead
3965 * of uncaching, which would allow us to flush all the LLC-cached data
3966 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3968 ret = i915_gem_object_set_cache_level(obj,
3969 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3971 goto err_unpin_display;
3973 /* As the user may map the buffer once pinned in the display plane
3974 * (e.g. libkms for the bootup splash), we have to ensure that we
3975 * always use map_and_fenceable for all scanout buffers.
3977 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
3978 view->type == I915_GGTT_VIEW_NORMAL ?
3981 goto err_unpin_display;
3983 i915_gem_object_flush_cpu_write_domain(obj);
3985 old_write_domain = obj->base.write_domain;
3986 old_read_domains = obj->base.read_domains;
3988 /* It should now be out of any other write domains, and we can update
3989 * the domain values for our changes.
3991 obj->base.write_domain = 0;
3992 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3994 trace_i915_gem_object_change_domain(obj,
4006 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4007 const struct i915_ggtt_view *view)
4009 if (WARN_ON(obj->pin_display == 0))
4012 i915_gem_object_ggtt_unpin_view(obj, view);
4018 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4022 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4025 ret = i915_gem_object_wait_rendering(obj, false);
4029 /* Ensure that we invalidate the GPU's caches and TLBs. */
4030 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4035 * Moves a single object to the CPU read, and possibly write domain.
4037 * This function returns when the move is complete, including waiting on
4041 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4043 uint32_t old_write_domain, old_read_domains;
4046 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4049 ret = i915_gem_object_wait_rendering(obj, !write);
4053 i915_gem_object_retire(obj);
4054 i915_gem_object_flush_gtt_write_domain(obj);
4056 old_write_domain = obj->base.write_domain;
4057 old_read_domains = obj->base.read_domains;
4059 /* Flush the CPU cache if it's still invalid. */
4060 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4061 i915_gem_clflush_object(obj, false);
4063 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4066 /* It should now be out of any other write domains, and we can update
4067 * the domain values for our changes.
4069 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4071 /* If we're writing through the CPU, then the GPU read domains will
4072 * need to be invalidated at next use.
4075 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4076 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4080 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
4082 trace_i915_gem_object_change_domain(obj,
4089 /* Throttle our rendering by waiting until the ring has completed our requests
4090 * emitted over 20 msec ago.
4092 * Note that if we were to use the current jiffies each time around the loop,
4093 * we wouldn't escape the function with any frames outstanding if the time to
4094 * render a frame was over 20ms.
4096 * This should get us reasonable parallelism between CPU and GPU but also
4097 * relatively low latency when blocking on a particular request to finish.
4100 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct drm_i915_file_private *file_priv = file->driver_priv;
4104 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4105 struct drm_i915_gem_request *request, *target = NULL;
4106 unsigned reset_counter;
4109 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4113 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4117 spin_lock(&file_priv->mm.lock);
4118 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4119 if (time_after_eq(request->emitted_jiffies, recent_enough))
4124 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4126 i915_gem_request_reference(target);
4127 spin_unlock(&file_priv->mm.lock);
4132 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4134 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4136 i915_gem_request_unreference__unlocked(target);
4142 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4144 struct drm_i915_gem_object *obj = vma->obj;
4147 vma->node.start & (alignment - 1))
4150 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4153 if (flags & PIN_OFFSET_BIAS &&
4154 vma->node.start < (flags & PIN_OFFSET_MASK))
4161 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4162 struct i915_address_space *vm,
4163 const struct i915_ggtt_view *ggtt_view,
4167 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4168 struct i915_vma *vma;
4172 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4175 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4178 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4181 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4184 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4185 i915_gem_obj_to_vma(obj, vm);
4188 return PTR_ERR(vma);
4191 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4194 if (i915_vma_misplaced(vma, alignment, flags)) {
4195 unsigned long offset;
4196 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4197 i915_gem_obj_offset(obj, vm);
4198 WARN(vma->pin_count,
4199 "bo is already pinned in %s with incorrect alignment:"
4200 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4201 " obj->map_and_fenceable=%d\n",
4202 ggtt_view ? "ggtt" : "ppgtt",
4205 !!(flags & PIN_MAPPABLE),
4206 obj->map_and_fenceable);
4207 ret = i915_vma_unbind(vma);
4215 bound = vma ? vma->bound : 0;
4216 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4217 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4220 return PTR_ERR(vma);
4222 ret = i915_vma_bind(vma, obj->cache_level, flags);
4227 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4228 (bound ^ vma->bound) & GLOBAL_BIND) {
4229 bool mappable, fenceable;
4230 u32 fence_size, fence_alignment;
4232 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4235 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4240 fenceable = (vma->node.size == fence_size &&
4241 (vma->node.start & (fence_alignment - 1)) == 0);
4243 mappable = (vma->node.start + fence_size <=
4244 dev_priv->gtt.mappable_end);
4246 obj->map_and_fenceable = mappable && fenceable;
4248 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4256 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4257 struct i915_address_space *vm,
4261 return i915_gem_object_do_pin(obj, vm,
4262 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4267 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4268 const struct i915_ggtt_view *view,
4272 if (WARN_ONCE(!view, "no view specified"))
4275 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4276 alignment, flags | PIN_GLOBAL);
4280 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4281 const struct i915_ggtt_view *view)
4283 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4286 WARN_ON(vma->pin_count == 0);
4287 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4293 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4295 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4296 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4297 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4299 WARN_ON(!ggtt_vma ||
4300 dev_priv->fence_regs[obj->fence_reg].pin_count >
4301 ggtt_vma->pin_count);
4302 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4309 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4311 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4312 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4313 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4314 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4319 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4320 struct drm_file *file)
4322 struct drm_i915_gem_busy *args = data;
4323 struct drm_i915_gem_object *obj;
4326 ret = i915_mutex_lock_interruptible(dev);
4330 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4331 if (&obj->base == NULL) {
4336 /* Count all active objects as busy, even if they are currently not used
4337 * by the gpu. Users of this interface expect objects to eventually
4338 * become non-busy without any further actions, therefore emit any
4339 * necessary flushes here.
4341 ret = i915_gem_object_flush_active(obj);
4343 args->busy = obj->active;
4344 if (obj->last_read_req) {
4345 struct intel_engine_cs *ring;
4346 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4347 ring = i915_gem_request_get_ring(obj->last_read_req);
4348 args->busy |= intel_ring_flag(ring) << 16;
4351 drm_gem_object_unreference(&obj->base);
4353 mutex_unlock(&dev->struct_mutex);
4358 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4359 struct drm_file *file_priv)
4361 return i915_gem_ring_throttle(dev, file_priv);
4365 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4366 struct drm_file *file_priv)
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 struct drm_i915_gem_madvise *args = data;
4370 struct drm_i915_gem_object *obj;
4373 switch (args->madv) {
4374 case I915_MADV_DONTNEED:
4375 case I915_MADV_WILLNEED:
4381 ret = i915_mutex_lock_interruptible(dev);
4385 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4386 if (&obj->base == NULL) {
4391 if (i915_gem_obj_is_pinned(obj)) {
4397 obj->tiling_mode != I915_TILING_NONE &&
4398 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4399 if (obj->madv == I915_MADV_WILLNEED)
4400 i915_gem_object_unpin_pages(obj);
4401 if (args->madv == I915_MADV_WILLNEED)
4402 i915_gem_object_pin_pages(obj);
4405 if (obj->madv != __I915_MADV_PURGED)
4406 obj->madv = args->madv;
4408 /* if the object is no longer attached, discard its backing storage */
4409 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4410 i915_gem_object_truncate(obj);
4412 args->retained = obj->madv != __I915_MADV_PURGED;
4415 drm_gem_object_unreference(&obj->base);
4417 mutex_unlock(&dev->struct_mutex);
4421 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4422 const struct drm_i915_gem_object_ops *ops)
4424 INIT_LIST_HEAD(&obj->global_list);
4425 INIT_LIST_HEAD(&obj->ring_list);
4426 INIT_LIST_HEAD(&obj->obj_exec_link);
4427 INIT_LIST_HEAD(&obj->vma_list);
4428 INIT_LIST_HEAD(&obj->batch_pool_link);
4432 obj->fence_reg = I915_FENCE_REG_NONE;
4433 obj->madv = I915_MADV_WILLNEED;
4435 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4438 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4439 .get_pages = i915_gem_object_get_pages_gtt,
4440 .put_pages = i915_gem_object_put_pages_gtt,
4443 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4446 struct drm_i915_gem_object *obj;
4447 struct address_space *mapping;
4450 obj = i915_gem_object_alloc(dev);
4454 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4455 i915_gem_object_free(obj);
4459 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4460 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4461 /* 965gm cannot relocate objects above 4GiB. */
4462 mask &= ~__GFP_HIGHMEM;
4463 mask |= __GFP_DMA32;
4466 mapping = file_inode(obj->base.filp)->i_mapping;
4467 mapping_set_gfp_mask(mapping, mask);
4469 i915_gem_object_init(obj, &i915_gem_object_ops);
4471 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4472 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4475 /* On some devices, we can have the GPU use the LLC (the CPU
4476 * cache) for about a 10% performance improvement
4477 * compared to uncached. Graphics requests other than
4478 * display scanout are coherent with the CPU in
4479 * accessing this cache. This means in this mode we
4480 * don't need to clflush on the CPU side, and on the
4481 * GPU side we only need to flush internal caches to
4482 * get data visible to the CPU.
4484 * However, we maintain the display planes as UC, and so
4485 * need to rebind when first used as such.
4487 obj->cache_level = I915_CACHE_LLC;
4489 obj->cache_level = I915_CACHE_NONE;
4491 trace_i915_gem_object_create(obj);
4496 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4498 /* If we are the last user of the backing storage (be it shmemfs
4499 * pages or stolen etc), we know that the pages are going to be
4500 * immediately released. In this case, we can then skip copying
4501 * back the contents from the GPU.
4504 if (obj->madv != I915_MADV_WILLNEED)
4507 if (obj->base.filp == NULL)
4510 /* At first glance, this looks racy, but then again so would be
4511 * userspace racing mmap against close. However, the first external
4512 * reference to the filp can only be obtained through the
4513 * i915_gem_mmap_ioctl() which safeguards us against the user
4514 * acquiring such a reference whilst we are in the middle of
4515 * freeing the object.
4517 return atomic_long_read(&obj->base.filp->f_count) == 1;
4520 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4522 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4523 struct drm_device *dev = obj->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 struct i915_vma *vma, *next;
4527 intel_runtime_pm_get(dev_priv);
4529 trace_i915_gem_object_destroy(obj);
4531 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4535 ret = i915_vma_unbind(vma);
4536 if (WARN_ON(ret == -ERESTARTSYS)) {
4537 bool was_interruptible;
4539 was_interruptible = dev_priv->mm.interruptible;
4540 dev_priv->mm.interruptible = false;
4542 WARN_ON(i915_vma_unbind(vma));
4544 dev_priv->mm.interruptible = was_interruptible;
4548 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4549 * before progressing. */
4551 i915_gem_object_unpin_pages(obj);
4553 WARN_ON(obj->frontbuffer_bits);
4555 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4556 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4557 obj->tiling_mode != I915_TILING_NONE)
4558 i915_gem_object_unpin_pages(obj);
4560 if (WARN_ON(obj->pages_pin_count))
4561 obj->pages_pin_count = 0;
4562 if (discard_backing_storage(obj))
4563 obj->madv = I915_MADV_DONTNEED;
4564 i915_gem_object_put_pages(obj);
4565 i915_gem_object_free_mmap_offset(obj);
4569 if (obj->base.import_attach)
4570 drm_prime_gem_destroy(&obj->base, NULL);
4572 if (obj->ops->release)
4573 obj->ops->release(obj);
4575 drm_gem_object_release(&obj->base);
4576 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4579 i915_gem_object_free(obj);
4581 intel_runtime_pm_put(dev_priv);
4584 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4585 struct i915_address_space *vm)
4587 struct i915_vma *vma;
4588 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4589 if (i915_is_ggtt(vma->vm) &&
4590 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4598 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4599 const struct i915_ggtt_view *view)
4601 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4602 struct i915_vma *vma;
4604 if (WARN_ONCE(!view, "no view specified"))
4605 return ERR_PTR(-EINVAL);
4607 list_for_each_entry(vma, &obj->vma_list, vma_link)
4608 if (vma->vm == ggtt &&
4609 i915_ggtt_view_equal(&vma->ggtt_view, view))
4614 void i915_gem_vma_destroy(struct i915_vma *vma)
4616 struct i915_address_space *vm = NULL;
4617 WARN_ON(vma->node.allocated);
4619 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4620 if (!list_empty(&vma->exec_list))
4625 if (!i915_is_ggtt(vm))
4626 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4628 list_del(&vma->vma_link);
4630 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4634 i915_gem_stop_ringbuffers(struct drm_device *dev)
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 struct intel_engine_cs *ring;
4640 for_each_ring(ring, dev_priv, i)
4641 dev_priv->gt.stop_ring(ring);
4645 i915_gem_suspend(struct drm_device *dev)
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4650 mutex_lock(&dev->struct_mutex);
4651 ret = i915_gpu_idle(dev);
4655 i915_gem_retire_requests(dev);
4657 i915_gem_stop_ringbuffers(dev);
4658 mutex_unlock(&dev->struct_mutex);
4660 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4661 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4662 flush_delayed_work(&dev_priv->mm.idle_work);
4664 /* Assert that we sucessfully flushed all the work and
4665 * reset the GPU back to its idle, low power state.
4667 WARN_ON(dev_priv->mm.busy);
4672 mutex_unlock(&dev->struct_mutex);
4676 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4678 struct drm_device *dev = ring->dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4681 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4684 if (!HAS_L3_DPF(dev) || !remap_info)
4687 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4692 * Note: We do not worry about the concurrent register cacheline hang
4693 * here because no other code should access these registers other than
4694 * at initialization time.
4696 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4698 intel_ring_emit(ring, reg_base + i);
4699 intel_ring_emit(ring, remap_info[i/4]);
4702 intel_ring_advance(ring);
4707 void i915_gem_init_swizzling(struct drm_device *dev)
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4711 if (INTEL_INFO(dev)->gen < 5 ||
4712 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4715 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4716 DISP_TILE_SURFACE_SWIZZLING);
4721 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4723 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4724 else if (IS_GEN7(dev))
4725 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4726 else if (IS_GEN8(dev))
4727 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4733 intel_enable_blt(struct drm_device *dev)
4738 /* The blitter was dysfunctional on early prototypes */
4739 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4740 DRM_INFO("BLT not supported on this pre-production hardware;"
4741 " graphics performance will be degraded.\n");
4748 static void init_unused_ring(struct drm_device *dev, u32 base)
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4752 I915_WRITE(RING_CTL(base), 0);
4753 I915_WRITE(RING_HEAD(base), 0);
4754 I915_WRITE(RING_TAIL(base), 0);
4755 I915_WRITE(RING_START(base), 0);
4758 static void init_unused_rings(struct drm_device *dev)
4761 init_unused_ring(dev, PRB1_BASE);
4762 init_unused_ring(dev, SRB0_BASE);
4763 init_unused_ring(dev, SRB1_BASE);
4764 init_unused_ring(dev, SRB2_BASE);
4765 init_unused_ring(dev, SRB3_BASE);
4766 } else if (IS_GEN2(dev)) {
4767 init_unused_ring(dev, SRB0_BASE);
4768 init_unused_ring(dev, SRB1_BASE);
4769 } else if (IS_GEN3(dev)) {
4770 init_unused_ring(dev, PRB1_BASE);
4771 init_unused_ring(dev, PRB2_BASE);
4775 int i915_gem_init_rings(struct drm_device *dev)
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4780 ret = intel_init_render_ring_buffer(dev);
4785 ret = intel_init_bsd_ring_buffer(dev);
4787 goto cleanup_render_ring;
4790 if (intel_enable_blt(dev)) {
4791 ret = intel_init_blt_ring_buffer(dev);
4793 goto cleanup_bsd_ring;
4796 if (HAS_VEBOX(dev)) {
4797 ret = intel_init_vebox_ring_buffer(dev);
4799 goto cleanup_blt_ring;
4802 if (HAS_BSD2(dev)) {
4803 ret = intel_init_bsd2_ring_buffer(dev);
4805 goto cleanup_vebox_ring;
4808 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4810 goto cleanup_bsd2_ring;
4815 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4817 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4819 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4821 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4822 cleanup_render_ring:
4823 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4829 i915_gem_init_hw(struct drm_device *dev)
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_engine_cs *ring;
4835 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4838 /* Double layer security blanket, see i915_gem_init() */
4839 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4841 if (dev_priv->ellc_size)
4842 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4844 if (IS_HASWELL(dev))
4845 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4846 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4848 if (HAS_PCH_NOP(dev)) {
4849 if (IS_IVYBRIDGE(dev)) {
4850 u32 temp = I915_READ(GEN7_MSG_CTL);
4851 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4852 I915_WRITE(GEN7_MSG_CTL, temp);
4853 } else if (INTEL_INFO(dev)->gen >= 7) {
4854 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4855 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4856 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4860 i915_gem_init_swizzling(dev);
4863 * At least 830 can leave some of the unused rings
4864 * "active" (ie. head != tail) after resume which
4865 * will prevent c3 entry. Makes sure all unused rings
4868 init_unused_rings(dev);
4870 for_each_ring(ring, dev_priv, i) {
4871 ret = ring->init_hw(ring);
4876 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4877 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4879 ret = i915_ppgtt_init_hw(dev);
4880 if (ret && ret != -EIO) {
4881 DRM_ERROR("PPGTT enable failed %d\n", ret);
4882 i915_gem_cleanup_ringbuffer(dev);
4885 ret = i915_gem_context_enable(dev_priv);
4886 if (ret && ret != -EIO) {
4887 DRM_ERROR("Context enable failed %d\n", ret);
4888 i915_gem_cleanup_ringbuffer(dev);
4894 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4898 int i915_gem_init(struct drm_device *dev)
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4903 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4904 i915.enable_execlists);
4906 mutex_lock(&dev->struct_mutex);
4908 if (IS_VALLEYVIEW(dev)) {
4909 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4910 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4911 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4912 VLV_GTLC_ALLOWWAKEACK), 10))
4913 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4916 if (!i915.enable_execlists) {
4917 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4918 dev_priv->gt.init_rings = i915_gem_init_rings;
4919 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4920 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4922 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4923 dev_priv->gt.init_rings = intel_logical_rings_init;
4924 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4925 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4928 /* This is just a security blanket to placate dragons.
4929 * On some systems, we very sporadically observe that the first TLBs
4930 * used by the CS may be stale, despite us poking the TLB reset. If
4931 * we hold the forcewake during initialisation these problems
4932 * just magically go away.
4934 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4936 ret = i915_gem_init_userptr(dev);
4940 i915_gem_init_global_gtt(dev);
4942 ret = i915_gem_context_init(dev);
4946 ret = dev_priv->gt.init_rings(dev);
4950 ret = i915_gem_init_hw(dev);
4952 /* Allow ring initialisation to fail by marking the GPU as
4953 * wedged. But we only want to do this where the GPU is angry,
4954 * for all other failure, such as an allocation failure, bail.
4956 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4957 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4962 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4963 mutex_unlock(&dev->struct_mutex);
4969 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4971 struct drm_i915_private *dev_priv = dev->dev_private;
4972 struct intel_engine_cs *ring;
4975 for_each_ring(ring, dev_priv, i)
4976 dev_priv->gt.cleanup_ring(ring);
4980 init_ring_lists(struct intel_engine_cs *ring)
4982 INIT_LIST_HEAD(&ring->active_list);
4983 INIT_LIST_HEAD(&ring->request_list);
4986 void i915_init_vm(struct drm_i915_private *dev_priv,
4987 struct i915_address_space *vm)
4989 if (!i915_is_ggtt(vm))
4990 drm_mm_init(&vm->mm, vm->start, vm->total);
4991 vm->dev = dev_priv->dev;
4992 INIT_LIST_HEAD(&vm->active_list);
4993 INIT_LIST_HEAD(&vm->inactive_list);
4994 INIT_LIST_HEAD(&vm->global_link);
4995 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4999 i915_gem_load(struct drm_device *dev)
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5005 kmem_cache_create("i915_gem_object",
5006 sizeof(struct drm_i915_gem_object), 0,
5010 kmem_cache_create("i915_gem_vma",
5011 sizeof(struct i915_vma), 0,
5014 dev_priv->requests =
5015 kmem_cache_create("i915_gem_request",
5016 sizeof(struct drm_i915_gem_request), 0,
5020 INIT_LIST_HEAD(&dev_priv->vm_list);
5021 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5023 INIT_LIST_HEAD(&dev_priv->context_list);
5024 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5025 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5026 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5027 for (i = 0; i < I915_NUM_RINGS; i++)
5028 init_ring_lists(&dev_priv->ring[i]);
5029 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5030 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5031 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5032 i915_gem_retire_work_handler);
5033 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5034 i915_gem_idle_work_handler);
5035 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5037 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5039 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5040 dev_priv->num_fence_regs = 32;
5041 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5042 dev_priv->num_fence_regs = 16;
5044 dev_priv->num_fence_regs = 8;
5046 if (intel_vgpu_active(dev))
5047 dev_priv->num_fence_regs =
5048 I915_READ(vgtif_reg(avail_rs.fence_num));
5050 /* Initialize fence registers to zero */
5051 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5052 i915_gem_restore_fences(dev);
5054 i915_gem_detect_bit_6_swizzle(dev);
5055 init_waitqueue_head(&dev_priv->pending_flip_queue);
5057 dev_priv->mm.interruptible = true;
5059 i915_gem_shrinker_init(dev_priv);
5061 mutex_init(&dev_priv->fb_tracking.lock);
5064 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5066 struct drm_i915_file_private *file_priv = file->driver_priv;
5068 /* Clean up our request list when the client is going away, so that
5069 * later retire_requests won't dereference our soon-to-be-gone
5072 spin_lock(&file_priv->mm.lock);
5073 while (!list_empty(&file_priv->mm.request_list)) {
5074 struct drm_i915_gem_request *request;
5076 request = list_first_entry(&file_priv->mm.request_list,
5077 struct drm_i915_gem_request,
5079 list_del(&request->client_list);
5080 request->file_priv = NULL;
5082 spin_unlock(&file_priv->mm.lock);
5084 if (!list_empty(&file_priv->rps_boost)) {
5085 mutex_lock(&to_i915(dev)->rps.hw_lock);
5086 list_del(&file_priv->rps_boost);
5087 mutex_unlock(&to_i915(dev)->rps.hw_lock);
5091 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5093 struct drm_i915_file_private *file_priv;
5096 DRM_DEBUG_DRIVER("\n");
5098 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5102 file->driver_priv = file_priv;
5103 file_priv->dev_priv = dev->dev_private;
5104 file_priv->file = file;
5105 INIT_LIST_HEAD(&file_priv->rps_boost);
5107 spin_lock_init(&file_priv->mm.lock);
5108 INIT_LIST_HEAD(&file_priv->mm.request_list);
5110 ret = i915_gem_context_open(dev, file);
5118 * i915_gem_track_fb - update frontbuffer tracking
5119 * old: current GEM buffer for the frontbuffer slots
5120 * new: new GEM buffer for the frontbuffer slots
5121 * frontbuffer_bits: bitmask of frontbuffer slots
5123 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5124 * from @old and setting them in @new. Both @old and @new can be NULL.
5126 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5127 struct drm_i915_gem_object *new,
5128 unsigned frontbuffer_bits)
5131 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5132 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5133 old->frontbuffer_bits &= ~frontbuffer_bits;
5137 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5138 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5139 new->frontbuffer_bits |= frontbuffer_bits;
5143 /* All the new VM stuff */
5145 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5146 struct i915_address_space *vm)
5148 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5149 struct i915_vma *vma;
5151 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5153 list_for_each_entry(vma, &o->vma_list, vma_link) {
5154 if (i915_is_ggtt(vma->vm) &&
5155 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5158 return vma->node.start;
5161 WARN(1, "%s vma for this object not found.\n",
5162 i915_is_ggtt(vm) ? "global" : "ppgtt");
5167 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5168 const struct i915_ggtt_view *view)
5170 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5171 struct i915_vma *vma;
5173 list_for_each_entry(vma, &o->vma_list, vma_link)
5174 if (vma->vm == ggtt &&
5175 i915_ggtt_view_equal(&vma->ggtt_view, view))
5176 return vma->node.start;
5178 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5182 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5183 struct i915_address_space *vm)
5185 struct i915_vma *vma;
5187 list_for_each_entry(vma, &o->vma_list, vma_link) {
5188 if (i915_is_ggtt(vma->vm) &&
5189 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5191 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5198 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5199 const struct i915_ggtt_view *view)
5201 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5202 struct i915_vma *vma;
5204 list_for_each_entry(vma, &o->vma_list, vma_link)
5205 if (vma->vm == ggtt &&
5206 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5207 drm_mm_node_allocated(&vma->node))
5213 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5215 struct i915_vma *vma;
5217 list_for_each_entry(vma, &o->vma_list, vma_link)
5218 if (drm_mm_node_allocated(&vma->node))
5224 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5225 struct i915_address_space *vm)
5227 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5228 struct i915_vma *vma;
5230 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5232 BUG_ON(list_empty(&o->vma_list));
5234 list_for_each_entry(vma, &o->vma_list, vma_link) {
5235 if (i915_is_ggtt(vma->vm) &&
5236 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5239 return vma->node.size;
5244 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5246 struct i915_vma *vma;
5247 list_for_each_entry(vma, &obj->vma_list, vma_link) {
5248 if (i915_is_ggtt(vma->vm) &&
5249 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5251 if (vma->pin_count > 0)