2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct i915_gpu_error *error)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret = wait_event_interruptible_timeout(error->reset_queue,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
118 int i915_mutex_lock_interruptible(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
123 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
127 ret = mutex_lock_interruptible(&dev->struct_mutex);
131 WARN_ON(i915_verify_lists(dev));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
138 return i915_gem_obj_ggtt_bound(obj) && !obj->active;
142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file)
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 struct drm_i915_gem_init *args = data;
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
151 if (args->gtt_start >= args->gtt_end ||
152 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev)->gen >= 5)
159 mutex_lock(&dev->struct_mutex);
160 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
162 dev_priv->gtt.mappable_end = args->gtt_end;
163 mutex_unlock(&dev->struct_mutex);
169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_get_aperture *args = data;
174 struct drm_i915_gem_object *obj;
178 mutex_lock(&dev->struct_mutex);
179 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
181 pinned += i915_gem_obj_ggtt_size(obj);
182 mutex_unlock(&dev->struct_mutex);
184 args->aper_size = dev_priv->gtt.base.total;
185 args->aper_available_size = args->aper_size - pinned;
190 void *i915_gem_object_alloc(struct drm_device *dev)
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
198 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
199 kmem_cache_free(dev_priv->slab, obj);
203 i915_gem_create(struct drm_file *file,
204 struct drm_device *dev,
208 struct drm_i915_gem_object *obj;
212 size = roundup(size, PAGE_SIZE);
216 /* Allocate the new object */
217 obj = i915_gem_alloc_object(dev, size);
221 ret = drm_gem_handle_create(file, &obj->base, &handle);
223 drm_gem_object_release(&obj->base);
224 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
225 i915_gem_object_free(obj);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj->base);
231 trace_i915_gem_object_create(obj);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 /* have to work out size/pitch and return them */
243 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
244 args->size = args->pitch * args->height;
245 return i915_gem_create(file, dev,
246 args->size, &args->handle);
249 int i915_gem_dumb_destroy(struct drm_file *file,
250 struct drm_device *dev,
253 return drm_gem_handle_delete(file, handle);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file)
263 struct drm_i915_gem_create *args = data;
265 return i915_gem_create(file, dev,
266 args->size, &args->handle);
270 __copy_to_user_swizzled(char __user *cpu_vaddr,
271 const char *gpu_vaddr, int gpu_offset,
274 int ret, cpu_offset = 0;
277 int cacheline_end = ALIGN(gpu_offset + 1, 64);
278 int this_length = min(cacheline_end - gpu_offset, length);
279 int swizzled_gpu_offset = gpu_offset ^ 64;
281 ret = __copy_to_user(cpu_vaddr + cpu_offset,
282 gpu_vaddr + swizzled_gpu_offset,
287 cpu_offset += this_length;
288 gpu_offset += this_length;
289 length -= this_length;
296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
297 const char __user *cpu_vaddr,
300 int ret, cpu_offset = 0;
303 int cacheline_end = ALIGN(gpu_offset + 1, 64);
304 int this_length = min(cacheline_end - gpu_offset, length);
305 int swizzled_gpu_offset = gpu_offset ^ 64;
307 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
308 cpu_vaddr + cpu_offset,
313 cpu_offset += this_length;
314 gpu_offset += this_length;
315 length -= this_length;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
326 char __user *user_data,
327 bool page_do_bit17_swizzling, bool needs_clflush)
332 if (unlikely(page_do_bit17_swizzling))
335 vaddr = kmap_atomic(page);
337 drm_clflush_virt_range(vaddr + shmem_page_offset,
339 ret = __copy_to_user_inatomic(user_data,
340 vaddr + shmem_page_offset,
342 kunmap_atomic(vaddr);
344 return ret ? -EFAULT : 0;
348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
351 if (unlikely(swizzled)) {
352 unsigned long start = (unsigned long) addr;
353 unsigned long end = (unsigned long) addr + length;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start = round_down(start, 128);
360 end = round_up(end, 128);
362 drm_clflush_virt_range((void *)start, end - start);
364 drm_clflush_virt_range(addr, length);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
373 char __user *user_data,
374 bool page_do_bit17_swizzling, bool needs_clflush)
381 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383 page_do_bit17_swizzling);
385 if (page_do_bit17_swizzling)
386 ret = __copy_to_user_swizzled(user_data,
387 vaddr, shmem_page_offset,
390 ret = __copy_to_user(user_data,
391 vaddr + shmem_page_offset,
395 return ret ? - EFAULT : 0;
399 i915_gem_shmem_pread(struct drm_device *dev,
400 struct drm_i915_gem_object *obj,
401 struct drm_i915_gem_pread *args,
402 struct drm_file *file)
404 char __user *user_data;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int needs_clflush = 0;
411 struct sg_page_iter sg_iter;
413 user_data = to_user_ptr(args->data_ptr);
416 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj->cache_level == I915_CACHE_NONE)
425 if (i915_gem_obj_ggtt_bound(obj)) {
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
432 ret = i915_gem_object_get_pages(obj);
436 i915_gem_object_pin_pages(obj);
438 offset = args->offset;
440 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
441 offset >> PAGE_SHIFT) {
442 struct page *page = sg_page_iter_page(&sg_iter);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset = offset_in_page(offset);
453 page_length = remain;
454 if ((shmem_page_offset + page_length) > PAGE_SIZE)
455 page_length = PAGE_SIZE - shmem_page_offset;
457 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
458 (page_to_phys(page) & (1 << 17)) != 0;
460 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
461 user_data, page_do_bit17_swizzling,
466 mutex_unlock(&dev->struct_mutex);
468 if (likely(!i915_prefault_disable) && !prefaulted) {
469 ret = fault_in_multipages_writeable(user_data, remain);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
479 user_data, page_do_bit17_swizzling,
482 mutex_lock(&dev->struct_mutex);
485 mark_page_accessed(page);
490 remain -= page_length;
491 user_data += page_length;
492 offset += page_length;
496 i915_gem_object_unpin_pages(obj);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
508 struct drm_file *file)
510 struct drm_i915_gem_pread *args = data;
511 struct drm_i915_gem_object *obj;
517 if (!access_ok(VERIFY_WRITE,
518 to_user_ptr(args->data_ptr),
522 ret = i915_mutex_lock_interruptible(dev);
526 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
527 if (&obj->base == NULL) {
532 /* Bounds check source. */
533 if (args->offset > obj->base.size ||
534 args->size > obj->base.size - args->offset) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj->base.filp) {
547 trace_i915_gem_object_pread(obj, args->offset, args->size);
549 ret = i915_gem_shmem_pread(dev, obj, args, file);
552 drm_gem_object_unreference(&obj->base);
554 mutex_unlock(&dev->struct_mutex);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping *mapping,
564 loff_t page_base, int page_offset,
565 char __user *user_data,
568 void __iomem *vaddr_atomic;
570 unsigned long unwritten;
572 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr = (void __force*)vaddr_atomic + page_offset;
575 unwritten = __copy_from_user_inatomic_nocache(vaddr,
577 io_mapping_unmap_atomic(vaddr_atomic);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_pwrite *args,
589 struct drm_file *file)
591 drm_i915_private_t *dev_priv = dev->dev_private;
593 loff_t offset, page_base;
594 char __user *user_data;
595 int page_offset, page_length, ret;
597 ret = i915_gem_object_pin(obj, 0, true, true);
601 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 ret = i915_gem_object_put_fence(obj);
609 user_data = to_user_ptr(args->data_ptr);
612 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base = offset & PAGE_MASK;
622 page_offset = offset_in_page(offset);
623 page_length = remain;
624 if ((page_offset + remain) > PAGE_SIZE)
625 page_length = PAGE_SIZE - page_offset;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv->gtt.mappable, page_base,
632 page_offset, user_data, page_length)) {
637 remain -= page_length;
638 user_data += page_length;
639 offset += page_length;
643 i915_gem_object_unpin(obj);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
654 char __user *user_data,
655 bool page_do_bit17_swizzling,
656 bool needs_clflush_before,
657 bool needs_clflush_after)
662 if (unlikely(page_do_bit17_swizzling))
665 vaddr = kmap_atomic(page);
666 if (needs_clflush_before)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
672 if (needs_clflush_after)
673 drm_clflush_virt_range(vaddr + shmem_page_offset,
675 kunmap_atomic(vaddr);
677 return ret ? -EFAULT : 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
684 char __user *user_data,
685 bool page_do_bit17_swizzling,
686 bool needs_clflush_before,
687 bool needs_clflush_after)
693 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
694 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
696 page_do_bit17_swizzling);
697 if (page_do_bit17_swizzling)
698 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 ret = __copy_from_user(vaddr + shmem_page_offset,
705 if (needs_clflush_after)
706 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708 page_do_bit17_swizzling);
711 return ret ? -EFAULT : 0;
715 i915_gem_shmem_pwrite(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file)
722 char __user *user_data;
723 int shmem_page_offset, page_length, ret = 0;
724 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
725 int hit_slowpath = 0;
726 int needs_clflush_after = 0;
727 int needs_clflush_before = 0;
728 struct sg_page_iter sg_iter;
730 user_data = to_user_ptr(args->data_ptr);
733 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
735 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj->cache_level == I915_CACHE_NONE)
741 needs_clflush_after = 1;
742 if (i915_gem_obj_ggtt_bound(obj)) {
743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
751 && obj->cache_level == I915_CACHE_NONE)
752 needs_clflush_before = 1;
754 ret = i915_gem_object_get_pages(obj);
758 i915_gem_object_pin_pages(obj);
760 offset = args->offset;
763 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
764 offset >> PAGE_SHIFT) {
765 struct page *page = sg_page_iter_page(&sg_iter);
766 int partial_cacheline_write;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset = offset_in_page(offset);
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
789 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
790 (page_to_phys(page) & (1 << 17)) != 0;
792 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
793 user_data, page_do_bit17_swizzling,
794 partial_cacheline_write,
795 needs_clflush_after);
800 mutex_unlock(&dev->struct_mutex);
801 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
806 mutex_lock(&dev->struct_mutex);
809 set_page_dirty(page);
810 mark_page_accessed(page);
815 remain -= page_length;
816 user_data += page_length;
817 offset += page_length;
821 i915_gem_object_unpin_pages(obj);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after &&
830 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
831 i915_gem_clflush_object(obj);
832 i915_gem_chipset_flush(dev);
836 if (needs_clflush_after)
837 i915_gem_chipset_flush(dev);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_gem_pwrite *args = data;
852 struct drm_i915_gem_object *obj;
858 if (!access_ok(VERIFY_READ,
859 to_user_ptr(args->data_ptr),
863 if (likely(!i915_prefault_disable)) {
864 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
870 ret = i915_mutex_lock_interruptible(dev);
874 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
875 if (&obj->base == NULL) {
880 /* Bounds check destination. */
881 if (args->offset > obj->base.size ||
882 args->size > obj->base.size - args->offset) {
887 /* prime objects have no backing filp to GEM pread/pwrite
890 if (!obj->base.filp) {
895 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
898 /* We can only do the GTT pwrite on untiled buffers, as otherwise
899 * it would end up going through the fenced access, and we'll get
900 * different detiling behavior between reading and writing.
901 * pread/pwrite currently are reading and writing from the CPU
902 * perspective, requiring manual detiling by the client.
905 ret = i915_gem_phys_pwrite(dev, obj, args, file);
909 if (obj->cache_level == I915_CACHE_NONE &&
910 obj->tiling_mode == I915_TILING_NONE &&
911 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
912 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
913 /* Note that the gtt paths might fail with non-page-backed user
914 * pointers (e.g. gtt mappings when moving data between
915 * textures). Fallback to the shmem path in that case. */
918 if (ret == -EFAULT || ret == -ENOSPC)
919 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
922 drm_gem_object_unreference(&obj->base);
924 mutex_unlock(&dev->struct_mutex);
929 i915_gem_check_wedge(struct i915_gpu_error *error,
932 if (i915_reset_in_progress(error)) {
933 /* Non-interruptible callers can't handle -EAGAIN, hence return
934 * -EIO unconditionally for these. */
938 /* Recovery complete, but the reset failed ... */
939 if (i915_terminally_wedged(error))
949 * Compare seqno against outstanding lazy request. Emit a request if they are
953 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
957 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
960 if (seqno == ring->outstanding_lazy_request)
961 ret = i915_add_request(ring, NULL);
967 * __wait_seqno - wait until execution of seqno has finished
968 * @ring: the ring expected to report seqno
970 * @reset_counter: reset sequence associated with the given seqno
971 * @interruptible: do an interruptible wait (normally yes)
972 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
974 * Note: It is of utmost importance that the passed in seqno and reset_counter
975 * values have been read by the caller in an smp safe manner. Where read-side
976 * locks are involved, it is sufficient to read the reset_counter before
977 * unlocking the lock that protects the seqno. For lockless tricks, the
978 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
981 * Returns 0 if the seqno was found within the alloted time. Else returns the
982 * errno with remaining time filled in timeout argument.
984 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
985 unsigned reset_counter,
986 bool interruptible, struct timespec *timeout)
988 drm_i915_private_t *dev_priv = ring->dev->dev_private;
989 struct timespec before, now, wait_time={1,0};
990 unsigned long timeout_jiffies;
992 bool wait_forever = true;
995 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
998 trace_i915_gem_request_wait_begin(ring, seqno);
1000 if (timeout != NULL) {
1001 wait_time = *timeout;
1002 wait_forever = false;
1005 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1007 if (WARN_ON(!ring->irq_get(ring)))
1010 /* Record current time in case interrupted by signal, or wedged * */
1011 getrawmonotonic(&before);
1014 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1015 i915_reset_in_progress(&dev_priv->gpu_error) || \
1016 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1019 end = wait_event_interruptible_timeout(ring->irq_queue,
1023 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1026 /* We need to check whether any gpu reset happened in between
1027 * the caller grabbing the seqno and now ... */
1028 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1031 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1033 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1036 } while (end == 0 && wait_forever);
1038 getrawmonotonic(&now);
1040 ring->irq_put(ring);
1041 trace_i915_gem_request_wait_end(ring, seqno);
1045 struct timespec sleep_time = timespec_sub(now, before);
1046 *timeout = timespec_sub(*timeout, sleep_time);
1047 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1048 set_normalized_timespec(timeout, 0, 0);
1053 case -EAGAIN: /* Wedged */
1054 case -ERESTARTSYS: /* Signal */
1056 case 0: /* Timeout */
1058 default: /* Completed */
1059 WARN_ON(end < 0); /* We're not aware of other errors */
1065 * Waits for a sequence number to be signaled, and cleans up the
1066 * request and object lists appropriately for that event.
1069 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1071 struct drm_device *dev = ring->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 bool interruptible = dev_priv->mm.interruptible;
1076 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1079 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1083 ret = i915_gem_check_olr(ring, seqno);
1087 return __wait_seqno(ring, seqno,
1088 atomic_read(&dev_priv->gpu_error.reset_counter),
1089 interruptible, NULL);
1093 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1094 struct intel_ring_buffer *ring)
1096 i915_gem_retire_requests_ring(ring);
1098 /* Manually manage the write flush as we may have not yet
1099 * retired the buffer.
1101 * Note that the last_write_seqno is always the earlier of
1102 * the two (read/write) seqno, so if we haved successfully waited,
1103 * we know we have passed the last write.
1105 obj->last_write_seqno = 0;
1106 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1112 * Ensures that all rendering to the object has completed and the object is
1113 * safe to unbind from the GTT or access from the CPU.
1115 static __must_check int
1116 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1119 struct intel_ring_buffer *ring = obj->ring;
1123 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1127 ret = i915_wait_seqno(ring, seqno);
1131 return i915_gem_object_wait_rendering__tail(obj, ring);
1134 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1135 * as the object state may change during this call.
1137 static __must_check int
1138 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1141 struct drm_device *dev = obj->base.dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 struct intel_ring_buffer *ring = obj->ring;
1144 unsigned reset_counter;
1148 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1149 BUG_ON(!dev_priv->mm.interruptible);
1151 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1155 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1159 ret = i915_gem_check_olr(ring, seqno);
1163 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1164 mutex_unlock(&dev->struct_mutex);
1165 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1166 mutex_lock(&dev->struct_mutex);
1170 return i915_gem_object_wait_rendering__tail(obj, ring);
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file)
1181 struct drm_i915_gem_set_domain *args = data;
1182 struct drm_i915_gem_object *obj;
1183 uint32_t read_domains = args->read_domains;
1184 uint32_t write_domain = args->write_domain;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain & I915_GEM_GPU_DOMAINS)
1191 if (read_domains & I915_GEM_GPU_DOMAINS)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain != 0 && read_domains != write_domain)
1200 ret = i915_mutex_lock_interruptible(dev);
1204 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1205 if (&obj->base == NULL) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218 if (read_domains & I915_GEM_DOMAIN_GTT) {
1219 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 drm_gem_object_unreference(&obj->base);
1234 mutex_unlock(&dev->struct_mutex);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file)
1245 struct drm_i915_gem_sw_finish *args = data;
1246 struct drm_i915_gem_object *obj;
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj);
1263 drm_gem_object_unreference(&obj->base);
1265 mutex_unlock(&dev->struct_mutex);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file)
1280 struct drm_i915_gem_mmap *args = data;
1281 struct drm_gem_object *obj;
1284 obj = drm_gem_object_lookup(dev, file, args->handle);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj);
1296 addr = vm_mmap(obj->filp, 0, args->size,
1297 PROT_READ | PROT_WRITE, MAP_SHARED,
1299 drm_gem_object_unreference_unlocked(obj);
1300 if (IS_ERR((void *)addr))
1303 args->addr_ptr = (uint64_t) addr;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1326 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1327 struct drm_device *dev = obj->base.dev;
1328 drm_i915_private_t *dev_priv = dev->dev_private;
1329 pgoff_t page_offset;
1332 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1338 ret = i915_mutex_lock_interruptible(dev);
1342 trace_i915_gem_object_fault(obj, page_offset, true, write);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1350 /* Now bind it into the GTT if needed */
1351 ret = i915_gem_object_pin(obj, 0, true, false);
1355 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1359 ret = i915_gem_object_get_fence(obj);
1363 obj->fault_mappable = true;
1365 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1369 /* Finally, remap it using the new GTT offset */
1370 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1372 i915_gem_object_unpin(obj);
1374 mutex_unlock(&dev->struct_mutex);
1378 /* If this -EIO is due to a gpu hang, give the reset code a
1379 * chance to clean up the mess. Otherwise return the proper
1381 if (i915_terminally_wedged(&dev_priv->gpu_error))
1382 return VM_FAULT_SIGBUS;
1384 /* Give the error handler a chance to run and move the
1385 * objects off the GPU active list. Next time we service the
1386 * fault, we should be able to transition the page into the
1387 * GTT without touching the GPU (and so avoid further
1388 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1389 * with coherency, just lost writes.
1397 * EBUSY is ok: this just means that another thread
1398 * already did the job.
1400 return VM_FAULT_NOPAGE;
1402 return VM_FAULT_OOM;
1404 return VM_FAULT_SIGBUS;
1406 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1407 return VM_FAULT_SIGBUS;
1412 * i915_gem_release_mmap - remove physical page mappings
1413 * @obj: obj in question
1415 * Preserve the reservation of the mmapping with the DRM core code, but
1416 * relinquish ownership of the pages back to the system.
1418 * It is vital that we remove the page mapping if we have mapped a tiled
1419 * object through the GTT and then lose the fence register due to
1420 * resource pressure. Similarly if the object has been moved out of the
1421 * aperture, than pages mapped into userspace must be revoked. Removing the
1422 * mapping will then trigger a page fault on the next user access, allowing
1423 * fixup by i915_gem_fault().
1426 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1428 if (!obj->fault_mappable)
1431 if (obj->base.dev->dev_mapping)
1432 unmap_mapping_range(obj->base.dev->dev_mapping,
1433 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1436 obj->fault_mappable = false;
1440 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1444 if (INTEL_INFO(dev)->gen >= 4 ||
1445 tiling_mode == I915_TILING_NONE)
1448 /* Previous chips need a power-of-two fence region when tiling */
1449 if (INTEL_INFO(dev)->gen == 3)
1450 gtt_size = 1024*1024;
1452 gtt_size = 512*1024;
1454 while (gtt_size < size)
1461 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1462 * @obj: object to check
1464 * Return the required GTT alignment for an object, taking into account
1465 * potential fence register mapping.
1468 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1469 int tiling_mode, bool fenced)
1472 * Minimum alignment is 4k (GTT page size), but might be greater
1473 * if a fence register is needed for the object.
1475 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1476 tiling_mode == I915_TILING_NONE)
1480 * Previous chips need to be aligned to the size of the smallest
1481 * fence register that can contain the object.
1483 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1486 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1488 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1491 if (obj->base.map_list.map)
1494 dev_priv->mm.shrinker_no_lock_stealing = true;
1496 ret = drm_gem_create_mmap_offset(&obj->base);
1500 /* Badly fragmented mmap space? The only way we can recover
1501 * space is by destroying unwanted objects. We can't randomly release
1502 * mmap_offsets as userspace expects them to be persistent for the
1503 * lifetime of the objects. The closest we can is to release the
1504 * offsets on purgeable objects by truncating it and marking it purged,
1505 * which prevents userspace from ever using that object again.
1507 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1508 ret = drm_gem_create_mmap_offset(&obj->base);
1512 i915_gem_shrink_all(dev_priv);
1513 ret = drm_gem_create_mmap_offset(&obj->base);
1515 dev_priv->mm.shrinker_no_lock_stealing = false;
1520 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1522 if (!obj->base.map_list.map)
1525 drm_gem_free_mmap_offset(&obj->base);
1529 i915_gem_mmap_gtt(struct drm_file *file,
1530 struct drm_device *dev,
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_i915_gem_object *obj;
1538 ret = i915_mutex_lock_interruptible(dev);
1542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1543 if (&obj->base == NULL) {
1548 if (obj->base.size > dev_priv->gtt.mappable_end) {
1553 if (obj->madv != I915_MADV_WILLNEED) {
1554 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1559 ret = i915_gem_object_create_mmap_offset(obj);
1563 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1566 drm_gem_object_unreference(&obj->base);
1568 mutex_unlock(&dev->struct_mutex);
1573 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1575 * @data: GTT mapping ioctl data
1576 * @file: GEM object info
1578 * Simply returns the fake offset to userspace so it can mmap it.
1579 * The mmap call will end up in drm_gem_mmap(), which will set things
1580 * up so we can get faults in the handler above.
1582 * The fault handler will take care of binding the object into the GTT
1583 * (since it may have been evicted to make room for something), allocating
1584 * a fence register, and mapping the appropriate aperture address into
1588 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1589 struct drm_file *file)
1591 struct drm_i915_gem_mmap_gtt *args = data;
1593 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1596 /* Immediately discard the backing storage */
1598 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1600 struct inode *inode;
1602 i915_gem_object_free_mmap_offset(obj);
1604 if (obj->base.filp == NULL)
1607 /* Our goal here is to return as much of the memory as
1608 * is possible back to the system as we are called from OOM.
1609 * To do this we must instruct the shmfs to drop all of its
1610 * backing pages, *now*.
1612 inode = file_inode(obj->base.filp);
1613 shmem_truncate_range(inode, 0, (loff_t)-1);
1615 obj->madv = __I915_MADV_PURGED;
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1621 return obj->madv == I915_MADV_DONTNEED;
1625 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1627 struct sg_page_iter sg_iter;
1630 BUG_ON(obj->madv == __I915_MADV_PURGED);
1632 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1634 /* In the event of a disaster, abandon all caches and
1635 * hope for the best.
1637 WARN_ON(ret != -EIO);
1638 i915_gem_clflush_object(obj);
1639 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1642 if (i915_gem_object_needs_bit17_swizzle(obj))
1643 i915_gem_object_save_bit_17_swizzle(obj);
1645 if (obj->madv == I915_MADV_DONTNEED)
1648 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1649 struct page *page = sg_page_iter_page(&sg_iter);
1652 set_page_dirty(page);
1654 if (obj->madv == I915_MADV_WILLNEED)
1655 mark_page_accessed(page);
1657 page_cache_release(page);
1661 sg_free_table(obj->pages);
1666 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1668 const struct drm_i915_gem_object_ops *ops = obj->ops;
1670 if (obj->pages == NULL)
1673 BUG_ON(i915_gem_obj_ggtt_bound(obj));
1675 if (obj->pages_pin_count)
1678 /* ->put_pages might need to allocate memory for the bit17 swizzle
1679 * array, hence protect them from being reaped by removing them from gtt
1681 list_del(&obj->global_list);
1683 ops->put_pages(obj);
1686 if (i915_gem_object_is_purgeable(obj))
1687 i915_gem_object_truncate(obj);
1693 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1694 bool purgeable_only)
1696 struct drm_i915_gem_object *obj, *next;
1697 struct i915_address_space *vm = &dev_priv->gtt.base;
1700 list_for_each_entry_safe(obj, next,
1701 &dev_priv->mm.unbound_list,
1703 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1704 i915_gem_object_put_pages(obj) == 0) {
1705 count += obj->base.size >> PAGE_SHIFT;
1706 if (count >= target)
1711 list_for_each_entry_safe(obj, next, &vm->inactive_list, mm_list) {
1712 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1713 i915_gem_object_unbind(obj) == 0 &&
1714 i915_gem_object_put_pages(obj) == 0) {
1715 count += obj->base.size >> PAGE_SHIFT;
1716 if (count >= target)
1725 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1727 return __i915_gem_shrink(dev_priv, target, true);
1731 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1733 struct drm_i915_gem_object *obj, *next;
1735 i915_gem_evict_everything(dev_priv->dev);
1737 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1739 i915_gem_object_put_pages(obj);
1743 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1745 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1747 struct address_space *mapping;
1748 struct sg_table *st;
1749 struct scatterlist *sg;
1750 struct sg_page_iter sg_iter;
1752 unsigned long last_pfn = 0; /* suppress gcc warning */
1755 /* Assert that the object is not currently in any GPU domain. As it
1756 * wasn't in the GTT, there shouldn't be any way it could have been in
1759 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1760 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1762 st = kmalloc(sizeof(*st), GFP_KERNEL);
1766 page_count = obj->base.size / PAGE_SIZE;
1767 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1773 /* Get the list of pages out of our struct file. They'll be pinned
1774 * at this point until we release them.
1776 * Fail silently without starting the shrinker
1778 mapping = file_inode(obj->base.filp)->i_mapping;
1779 gfp = mapping_gfp_mask(mapping);
1780 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1781 gfp &= ~(__GFP_IO | __GFP_WAIT);
1784 for (i = 0; i < page_count; i++) {
1785 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1787 i915_gem_purge(dev_priv, page_count);
1788 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1791 /* We've tried hard to allocate the memory by reaping
1792 * our own buffer, now let the real VM do its job and
1793 * go down in flames if truly OOM.
1795 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1796 gfp |= __GFP_IO | __GFP_WAIT;
1798 i915_gem_shrink_all(dev_priv);
1799 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1803 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1804 gfp &= ~(__GFP_IO | __GFP_WAIT);
1806 #ifdef CONFIG_SWIOTLB
1807 if (swiotlb_nr_tbl()) {
1809 sg_set_page(sg, page, PAGE_SIZE, 0);
1814 if (!i || page_to_pfn(page) != last_pfn + 1) {
1818 sg_set_page(sg, page, PAGE_SIZE, 0);
1820 sg->length += PAGE_SIZE;
1822 last_pfn = page_to_pfn(page);
1824 #ifdef CONFIG_SWIOTLB
1825 if (!swiotlb_nr_tbl())
1830 if (i915_gem_object_needs_bit17_swizzle(obj))
1831 i915_gem_object_do_bit_17_swizzle(obj);
1837 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1838 page_cache_release(sg_page_iter_page(&sg_iter));
1841 return PTR_ERR(page);
1844 /* Ensure that the associated pages are gathered from the backing storage
1845 * and pinned into our object. i915_gem_object_get_pages() may be called
1846 * multiple times before they are released by a single call to
1847 * i915_gem_object_put_pages() - once the pages are no longer referenced
1848 * either as a result of memory pressure (reaping pages under the shrinker)
1849 * or as the object is itself released.
1852 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1854 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1855 const struct drm_i915_gem_object_ops *ops = obj->ops;
1861 if (obj->madv != I915_MADV_WILLNEED) {
1862 DRM_ERROR("Attempting to obtain a purgeable object\n");
1866 BUG_ON(obj->pages_pin_count);
1868 ret = ops->get_pages(obj);
1872 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1877 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1878 struct intel_ring_buffer *ring)
1880 struct drm_device *dev = obj->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct i915_address_space *vm = &dev_priv->gtt.base;
1883 u32 seqno = intel_ring_get_seqno(ring);
1885 BUG_ON(ring == NULL);
1888 /* Add a reference if we're newly entering the active list. */
1890 drm_gem_object_reference(&obj->base);
1894 /* Move from whatever list we were on to the tail of execution. */
1895 list_move_tail(&obj->mm_list, &vm->active_list);
1896 list_move_tail(&obj->ring_list, &ring->active_list);
1898 obj->last_read_seqno = seqno;
1900 if (obj->fenced_gpu_access) {
1901 obj->last_fenced_seqno = seqno;
1903 /* Bump MRU to take account of the delayed flush */
1904 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1905 struct drm_i915_fence_reg *reg;
1907 reg = &dev_priv->fence_regs[obj->fence_reg];
1908 list_move_tail(®->lru_list,
1909 &dev_priv->mm.fence_list);
1915 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1917 struct drm_device *dev = obj->base.dev;
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919 struct i915_address_space *vm = &dev_priv->gtt.base;
1921 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1922 BUG_ON(!obj->active);
1924 list_move_tail(&obj->mm_list, &vm->inactive_list);
1926 list_del_init(&obj->ring_list);
1929 obj->last_read_seqno = 0;
1930 obj->last_write_seqno = 0;
1931 obj->base.write_domain = 0;
1933 obj->last_fenced_seqno = 0;
1934 obj->fenced_gpu_access = false;
1937 drm_gem_object_unreference(&obj->base);
1939 WARN_ON(i915_verify_lists(dev));
1943 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_ring_buffer *ring;
1949 /* Carefully retire all requests without writing to the rings */
1950 for_each_ring(ring, dev_priv, i) {
1951 ret = intel_ring_idle(ring);
1955 i915_gem_retire_requests(dev);
1957 /* Finally reset hw state */
1958 for_each_ring(ring, dev_priv, i) {
1959 intel_ring_init_seqno(ring, seqno);
1961 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1962 ring->sync_seqno[j] = 0;
1968 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1976 /* HWS page needs to be set less than what we
1977 * will inject to ring
1979 ret = i915_gem_init_seqno(dev, seqno - 1);
1983 /* Carefully set the last_seqno value so that wrap
1984 * detection still works
1986 dev_priv->next_seqno = seqno;
1987 dev_priv->last_seqno = seqno - 1;
1988 if (dev_priv->last_seqno == 0)
1989 dev_priv->last_seqno--;
1995 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1999 /* reserve 0 for non-seqno */
2000 if (dev_priv->next_seqno == 0) {
2001 int ret = i915_gem_init_seqno(dev, 0);
2005 dev_priv->next_seqno = 1;
2008 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2012 int __i915_add_request(struct intel_ring_buffer *ring,
2013 struct drm_file *file,
2014 struct drm_i915_gem_object *obj,
2017 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2018 struct drm_i915_gem_request *request;
2019 u32 request_ring_position, request_start;
2023 request_start = intel_ring_get_tail(ring);
2025 * Emit any outstanding flushes - execbuf can fail to emit the flush
2026 * after having emitted the batchbuffer command. Hence we need to fix
2027 * things up similar to emitting the lazy request. The difference here
2028 * is that the flush _must_ happen before the next request, no matter
2031 ret = intel_ring_flush_all_caches(ring);
2035 request = kmalloc(sizeof(*request), GFP_KERNEL);
2036 if (request == NULL)
2040 /* Record the position of the start of the request so that
2041 * should we detect the updated seqno part-way through the
2042 * GPU processing the request, we never over-estimate the
2043 * position of the head.
2045 request_ring_position = intel_ring_get_tail(ring);
2047 ret = ring->add_request(ring);
2053 request->seqno = intel_ring_get_seqno(ring);
2054 request->ring = ring;
2055 request->head = request_start;
2056 request->tail = request_ring_position;
2057 request->ctx = ring->last_context;
2058 request->batch_obj = obj;
2060 /* Whilst this request exists, batch_obj will be on the
2061 * active_list, and so will hold the active reference. Only when this
2062 * request is retired will the the batch_obj be moved onto the
2063 * inactive_list and lose its active reference. Hence we do not need
2064 * to explicitly hold another reference here.
2068 i915_gem_context_reference(request->ctx);
2070 request->emitted_jiffies = jiffies;
2071 was_empty = list_empty(&ring->request_list);
2072 list_add_tail(&request->list, &ring->request_list);
2073 request->file_priv = NULL;
2076 struct drm_i915_file_private *file_priv = file->driver_priv;
2078 spin_lock(&file_priv->mm.lock);
2079 request->file_priv = file_priv;
2080 list_add_tail(&request->client_list,
2081 &file_priv->mm.request_list);
2082 spin_unlock(&file_priv->mm.lock);
2085 trace_i915_gem_request_add(ring, request->seqno);
2086 ring->outstanding_lazy_request = 0;
2088 if (!dev_priv->ums.mm_suspended) {
2089 i915_queue_hangcheck(ring->dev);
2092 queue_delayed_work(dev_priv->wq,
2093 &dev_priv->mm.retire_work,
2094 round_jiffies_up_relative(HZ));
2095 intel_mark_busy(dev_priv->dev);
2100 *out_seqno = request->seqno;
2105 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2107 struct drm_i915_file_private *file_priv = request->file_priv;
2112 spin_lock(&file_priv->mm.lock);
2113 if (request->file_priv) {
2114 list_del(&request->client_list);
2115 request->file_priv = NULL;
2117 spin_unlock(&file_priv->mm.lock);
2120 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2122 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
2123 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
2129 static bool i915_head_inside_request(const u32 acthd_unmasked,
2130 const u32 request_start,
2131 const u32 request_end)
2133 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2135 if (request_start < request_end) {
2136 if (acthd >= request_start && acthd < request_end)
2138 } else if (request_start > request_end) {
2139 if (acthd >= request_start || acthd < request_end)
2146 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2147 const u32 acthd, bool *inside)
2149 /* There is a possibility that unmasked head address
2150 * pointing inside the ring, matches the batch_obj address range.
2151 * However this is extremely unlikely.
2154 if (request->batch_obj) {
2155 if (i915_head_inside_object(acthd, request->batch_obj)) {
2161 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2169 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2170 struct drm_i915_gem_request *request,
2173 struct i915_ctx_hang_stats *hs = NULL;
2174 bool inside, guilty;
2176 /* Innocent until proven guilty */
2179 if (ring->hangcheck.action != wait &&
2180 i915_request_guilty(request, acthd, &inside)) {
2181 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2183 inside ? "inside" : "flushing",
2184 request->batch_obj ?
2185 i915_gem_obj_ggtt_offset(request->batch_obj) : 0,
2186 request->ctx ? request->ctx->id : 0,
2192 /* If contexts are disabled or this is the default context, use
2193 * file_priv->reset_state
2195 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2196 hs = &request->ctx->hang_stats;
2197 else if (request->file_priv)
2198 hs = &request->file_priv->hang_stats;
2204 hs->batch_pending++;
2208 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2210 list_del(&request->list);
2211 i915_gem_request_remove_from_client(request);
2214 i915_gem_context_unreference(request->ctx);
2219 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2220 struct intel_ring_buffer *ring)
2222 u32 completed_seqno;
2225 acthd = intel_ring_get_active_head(ring);
2226 completed_seqno = ring->get_seqno(ring, false);
2228 while (!list_empty(&ring->request_list)) {
2229 struct drm_i915_gem_request *request;
2231 request = list_first_entry(&ring->request_list,
2232 struct drm_i915_gem_request,
2235 if (request->seqno > completed_seqno)
2236 i915_set_reset_status(ring, request, acthd);
2238 i915_gem_free_request(request);
2241 while (!list_empty(&ring->active_list)) {
2242 struct drm_i915_gem_object *obj;
2244 obj = list_first_entry(&ring->active_list,
2245 struct drm_i915_gem_object,
2248 i915_gem_object_move_to_inactive(obj);
2252 static void i915_gem_reset_fences(struct drm_device *dev)
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2257 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2258 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2261 i915_gem_object_fence_lost(reg->obj);
2263 i915_gem_write_fence(dev, i, NULL);
2267 INIT_LIST_HEAD(®->lru_list);
2270 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2273 void i915_gem_reset(struct drm_device *dev)
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 struct i915_address_space *vm = &dev_priv->gtt.base;
2277 struct drm_i915_gem_object *obj;
2278 struct intel_ring_buffer *ring;
2281 for_each_ring(ring, dev_priv, i)
2282 i915_gem_reset_ring_lists(dev_priv, ring);
2284 /* Move everything out of the GPU domains to ensure we do any
2285 * necessary invalidation upon reuse.
2287 list_for_each_entry(obj, &vm->inactive_list, mm_list)
2288 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2290 /* The fence registers are invalidated so clear them out */
2291 i915_gem_reset_fences(dev);
2295 * This function clears the request list as sequence numbers are passed.
2298 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2302 if (list_empty(&ring->request_list))
2305 WARN_ON(i915_verify_lists(ring->dev));
2307 seqno = ring->get_seqno(ring, true);
2309 while (!list_empty(&ring->request_list)) {
2310 struct drm_i915_gem_request *request;
2312 request = list_first_entry(&ring->request_list,
2313 struct drm_i915_gem_request,
2316 if (!i915_seqno_passed(seqno, request->seqno))
2319 trace_i915_gem_request_retire(ring, request->seqno);
2320 /* We know the GPU must have read the request to have
2321 * sent us the seqno + interrupt, so use the position
2322 * of tail of the request to update the last known position
2325 ring->last_retired_head = request->tail;
2327 i915_gem_free_request(request);
2330 /* Move any buffers on the active list that are no longer referenced
2331 * by the ringbuffer to the flushing/inactive lists as appropriate.
2333 while (!list_empty(&ring->active_list)) {
2334 struct drm_i915_gem_object *obj;
2336 obj = list_first_entry(&ring->active_list,
2337 struct drm_i915_gem_object,
2340 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2343 i915_gem_object_move_to_inactive(obj);
2346 if (unlikely(ring->trace_irq_seqno &&
2347 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2348 ring->irq_put(ring);
2349 ring->trace_irq_seqno = 0;
2352 WARN_ON(i915_verify_lists(ring->dev));
2356 i915_gem_retire_requests(struct drm_device *dev)
2358 drm_i915_private_t *dev_priv = dev->dev_private;
2359 struct intel_ring_buffer *ring;
2362 for_each_ring(ring, dev_priv, i)
2363 i915_gem_retire_requests_ring(ring);
2367 i915_gem_retire_work_handler(struct work_struct *work)
2369 drm_i915_private_t *dev_priv;
2370 struct drm_device *dev;
2371 struct intel_ring_buffer *ring;
2375 dev_priv = container_of(work, drm_i915_private_t,
2376 mm.retire_work.work);
2377 dev = dev_priv->dev;
2379 /* Come back later if the device is busy... */
2380 if (!mutex_trylock(&dev->struct_mutex)) {
2381 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2382 round_jiffies_up_relative(HZ));
2386 i915_gem_retire_requests(dev);
2388 /* Send a periodic flush down the ring so we don't hold onto GEM
2389 * objects indefinitely.
2392 for_each_ring(ring, dev_priv, i) {
2393 if (ring->gpu_caches_dirty)
2394 i915_add_request(ring, NULL);
2396 idle &= list_empty(&ring->request_list);
2399 if (!dev_priv->ums.mm_suspended && !idle)
2400 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2401 round_jiffies_up_relative(HZ));
2403 intel_mark_idle(dev);
2405 mutex_unlock(&dev->struct_mutex);
2409 * Ensures that an object will eventually get non-busy by flushing any required
2410 * write domains, emitting any outstanding lazy request and retiring and
2411 * completed requests.
2414 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2419 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2423 i915_gem_retire_requests_ring(obj->ring);
2430 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2431 * @DRM_IOCTL_ARGS: standard ioctl arguments
2433 * Returns 0 if successful, else an error is returned with the remaining time in
2434 * the timeout parameter.
2435 * -ETIME: object is still busy after timeout
2436 * -ERESTARTSYS: signal interrupted the wait
2437 * -ENONENT: object doesn't exist
2438 * Also possible, but rare:
2439 * -EAGAIN: GPU wedged
2441 * -ENODEV: Internal IRQ fail
2442 * -E?: The add request failed
2444 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2445 * non-zero timeout parameter the wait ioctl will wait for the given number of
2446 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2447 * without holding struct_mutex the object may become re-busied before this
2448 * function completes. A similar but shorter * race condition exists in the busy
2452 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2454 drm_i915_private_t *dev_priv = dev->dev_private;
2455 struct drm_i915_gem_wait *args = data;
2456 struct drm_i915_gem_object *obj;
2457 struct intel_ring_buffer *ring = NULL;
2458 struct timespec timeout_stack, *timeout = NULL;
2459 unsigned reset_counter;
2463 if (args->timeout_ns >= 0) {
2464 timeout_stack = ns_to_timespec(args->timeout_ns);
2465 timeout = &timeout_stack;
2468 ret = i915_mutex_lock_interruptible(dev);
2472 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2473 if (&obj->base == NULL) {
2474 mutex_unlock(&dev->struct_mutex);
2478 /* Need to make sure the object gets inactive eventually. */
2479 ret = i915_gem_object_flush_active(obj);
2484 seqno = obj->last_read_seqno;
2491 /* Do this after OLR check to make sure we make forward progress polling
2492 * on this IOCTL with a 0 timeout (like busy ioctl)
2494 if (!args->timeout_ns) {
2499 drm_gem_object_unreference(&obj->base);
2500 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2501 mutex_unlock(&dev->struct_mutex);
2503 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2505 args->timeout_ns = timespec_to_ns(timeout);
2509 drm_gem_object_unreference(&obj->base);
2510 mutex_unlock(&dev->struct_mutex);
2515 * i915_gem_object_sync - sync an object to a ring.
2517 * @obj: object which may be in use on another ring.
2518 * @to: ring we wish to use the object on. May be NULL.
2520 * This code is meant to abstract object synchronization with the GPU.
2521 * Calling with NULL implies synchronizing the object with the CPU
2522 * rather than a particular GPU ring.
2524 * Returns 0 if successful, else propagates up the lower layer error.
2527 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2528 struct intel_ring_buffer *to)
2530 struct intel_ring_buffer *from = obj->ring;
2534 if (from == NULL || to == from)
2537 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2538 return i915_gem_object_wait_rendering(obj, false);
2540 idx = intel_ring_sync_index(from, to);
2542 seqno = obj->last_read_seqno;
2543 if (seqno <= from->sync_seqno[idx])
2546 ret = i915_gem_check_olr(obj->ring, seqno);
2550 ret = to->sync_to(to, from, seqno);
2552 /* We use last_read_seqno because sync_to()
2553 * might have just caused seqno wrap under
2556 from->sync_seqno[idx] = obj->last_read_seqno;
2561 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2563 u32 old_write_domain, old_read_domains;
2565 /* Force a pagefault for domain tracking on next user access */
2566 i915_gem_release_mmap(obj);
2568 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2571 /* Wait for any direct GTT access to complete */
2574 old_read_domains = obj->base.read_domains;
2575 old_write_domain = obj->base.write_domain;
2577 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2578 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2580 trace_i915_gem_object_change_domain(obj,
2586 * Unbinds an object from the GTT aperture.
2589 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2591 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2592 struct i915_vma *vma;
2595 if (!i915_gem_obj_ggtt_bound(obj))
2601 BUG_ON(obj->pages == NULL);
2603 ret = i915_gem_object_finish_gpu(obj);
2606 /* Continue on if we fail due to EIO, the GPU is hung so we
2607 * should be safe and we need to cleanup or else we might
2608 * cause memory corruption through use-after-free.
2611 i915_gem_object_finish_gtt(obj);
2613 /* release the fence reg _after_ flushing */
2614 ret = i915_gem_object_put_fence(obj);
2618 trace_i915_gem_object_unbind(obj);
2620 if (obj->has_global_gtt_mapping)
2621 i915_gem_gtt_unbind_object(obj);
2622 if (obj->has_aliasing_ppgtt_mapping) {
2623 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2624 obj->has_aliasing_ppgtt_mapping = 0;
2626 i915_gem_gtt_finish_object(obj);
2627 i915_gem_object_unpin_pages(obj);
2629 list_del(&obj->mm_list);
2630 /* Avoid an unnecessary call to unbind on rebind. */
2631 obj->map_and_fenceable = true;
2633 vma = __i915_gem_obj_to_vma(obj);
2634 list_del(&vma->vma_link);
2635 drm_mm_remove_node(&vma->node);
2636 i915_gem_vma_destroy(vma);
2638 /* Since the unbound list is global, only move to that list if
2639 * no more VMAs exist.
2640 * NB: Until we have real VMAs there will only ever be one */
2641 WARN_ON(!list_empty(&obj->vma_list));
2642 if (list_empty(&obj->vma_list))
2643 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2648 int i915_gpu_idle(struct drm_device *dev)
2650 drm_i915_private_t *dev_priv = dev->dev_private;
2651 struct intel_ring_buffer *ring;
2654 /* Flush everything onto the inactive list. */
2655 for_each_ring(ring, dev_priv, i) {
2656 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2660 ret = intel_ring_idle(ring);
2668 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2669 struct drm_i915_gem_object *obj)
2671 drm_i915_private_t *dev_priv = dev->dev_private;
2673 int fence_pitch_shift;
2676 if (INTEL_INFO(dev)->gen >= 6) {
2677 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2678 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2680 fence_reg = FENCE_REG_965_0;
2681 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2685 u32 size = i915_gem_obj_ggtt_size(obj);
2687 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2689 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2690 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2691 if (obj->tiling_mode == I915_TILING_Y)
2692 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2693 val |= I965_FENCE_REG_VALID;
2697 fence_reg += reg * 8;
2698 I915_WRITE64(fence_reg, val);
2699 POSTING_READ(fence_reg);
2702 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2703 struct drm_i915_gem_object *obj)
2705 drm_i915_private_t *dev_priv = dev->dev_private;
2709 u32 size = i915_gem_obj_ggtt_size(obj);
2713 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2714 (size & -size) != size ||
2715 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2716 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2717 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2719 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2724 /* Note: pitch better be a power of two tile widths */
2725 pitch_val = obj->stride / tile_width;
2726 pitch_val = ffs(pitch_val) - 1;
2728 val = i915_gem_obj_ggtt_offset(obj);
2729 if (obj->tiling_mode == I915_TILING_Y)
2730 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2731 val |= I915_FENCE_SIZE_BITS(size);
2732 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2733 val |= I830_FENCE_REG_VALID;
2738 reg = FENCE_REG_830_0 + reg * 4;
2740 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2742 I915_WRITE(reg, val);
2746 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2747 struct drm_i915_gem_object *obj)
2749 drm_i915_private_t *dev_priv = dev->dev_private;
2753 u32 size = i915_gem_obj_ggtt_size(obj);
2756 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2757 (size & -size) != size ||
2758 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2759 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2760 i915_gem_obj_ggtt_offset(obj), size);
2762 pitch_val = obj->stride / 128;
2763 pitch_val = ffs(pitch_val) - 1;
2765 val = i915_gem_obj_ggtt_offset(obj);
2766 if (obj->tiling_mode == I915_TILING_Y)
2767 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2768 val |= I830_FENCE_SIZE_BITS(size);
2769 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2770 val |= I830_FENCE_REG_VALID;
2774 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2775 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2778 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2780 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2783 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2784 struct drm_i915_gem_object *obj)
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2788 /* Ensure that all CPU reads are completed before installing a fence
2789 * and all writes before removing the fence.
2791 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2794 switch (INTEL_INFO(dev)->gen) {
2798 case 4: i965_write_fence_reg(dev, reg, obj); break;
2799 case 3: i915_write_fence_reg(dev, reg, obj); break;
2800 case 2: i830_write_fence_reg(dev, reg, obj); break;
2804 /* And similarly be paranoid that no direct access to this region
2805 * is reordered to before the fence is installed.
2807 if (i915_gem_object_needs_mb(obj))
2811 static inline int fence_number(struct drm_i915_private *dev_priv,
2812 struct drm_i915_fence_reg *fence)
2814 return fence - dev_priv->fence_regs;
2817 struct write_fence {
2818 struct drm_device *dev;
2819 struct drm_i915_gem_object *obj;
2823 static void i915_gem_write_fence__ipi(void *data)
2825 struct write_fence *args = data;
2827 /* Required for SNB+ with LLC */
2830 /* Required for VLV */
2831 i915_gem_write_fence(args->dev, args->fence, args->obj);
2834 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2835 struct drm_i915_fence_reg *fence,
2838 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2839 struct write_fence args = {
2840 .dev = obj->base.dev,
2841 .fence = fence_number(dev_priv, fence),
2842 .obj = enable ? obj : NULL,
2845 /* In order to fully serialize access to the fenced region and
2846 * the update to the fence register we need to take extreme
2847 * measures on SNB+. In theory, the write to the fence register
2848 * flushes all memory transactions before, and coupled with the
2849 * mb() placed around the register write we serialise all memory
2850 * operations with respect to the changes in the tiler. Yet, on
2851 * SNB+ we need to take a step further and emit an explicit wbinvd()
2852 * on each processor in order to manually flush all memory
2853 * transactions before updating the fence register.
2855 * However, Valleyview complicates matter. There the wbinvd is
2856 * insufficient and unlike SNB/IVB requires the serialising
2857 * register write. (Note that that register write by itself is
2858 * conversely not sufficient for SNB+.) To compromise, we do both.
2860 if (INTEL_INFO(args.dev)->gen >= 6)
2861 on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
2863 i915_gem_write_fence(args.dev, args.fence, args.obj);
2866 obj->fence_reg = args.fence;
2868 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2870 obj->fence_reg = I915_FENCE_REG_NONE;
2872 list_del_init(&fence->lru_list);
2877 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2879 if (obj->last_fenced_seqno) {
2880 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2884 obj->last_fenced_seqno = 0;
2887 obj->fenced_gpu_access = false;
2892 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2894 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2895 struct drm_i915_fence_reg *fence;
2898 ret = i915_gem_object_wait_fence(obj);
2902 if (obj->fence_reg == I915_FENCE_REG_NONE)
2905 fence = &dev_priv->fence_regs[obj->fence_reg];
2907 i915_gem_object_fence_lost(obj);
2908 i915_gem_object_update_fence(obj, fence, false);
2913 static struct drm_i915_fence_reg *
2914 i915_find_fence_reg(struct drm_device *dev)
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 struct drm_i915_fence_reg *reg, *avail;
2920 /* First try to find a free reg */
2922 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2923 reg = &dev_priv->fence_regs[i];
2927 if (!reg->pin_count)
2934 /* None available, try to steal one or wait for a user to finish */
2935 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2946 * i915_gem_object_get_fence - set up fencing for an object
2947 * @obj: object to map through a fence reg
2949 * When mapping objects through the GTT, userspace wants to be able to write
2950 * to them without having to worry about swizzling if the object is tiled.
2951 * This function walks the fence regs looking for a free one for @obj,
2952 * stealing one if it can't find any.
2954 * It then sets up the reg based on the object's properties: address, pitch
2955 * and tiling format.
2957 * For an untiled surface, this removes any existing fence.
2960 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2962 struct drm_device *dev = obj->base.dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 bool enable = obj->tiling_mode != I915_TILING_NONE;
2965 struct drm_i915_fence_reg *reg;
2968 /* Have we updated the tiling parameters upon the object and so
2969 * will need to serialise the write to the associated fence register?
2971 if (obj->fence_dirty) {
2972 ret = i915_gem_object_wait_fence(obj);
2977 /* Just update our place in the LRU if our fence is getting reused. */
2978 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2979 reg = &dev_priv->fence_regs[obj->fence_reg];
2980 if (!obj->fence_dirty) {
2981 list_move_tail(®->lru_list,
2982 &dev_priv->mm.fence_list);
2985 } else if (enable) {
2986 reg = i915_find_fence_reg(dev);
2991 struct drm_i915_gem_object *old = reg->obj;
2993 ret = i915_gem_object_wait_fence(old);
2997 i915_gem_object_fence_lost(old);
3002 i915_gem_object_update_fence(obj, reg, enable);
3003 obj->fence_dirty = false;
3008 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3009 struct drm_mm_node *gtt_space,
3010 unsigned long cache_level)
3012 struct drm_mm_node *other;
3014 /* On non-LLC machines we have to be careful when putting differing
3015 * types of snoopable memory together to avoid the prefetcher
3016 * crossing memory domains and dying.
3021 if (!drm_mm_node_allocated(gtt_space))
3024 if (list_empty(>t_space->node_list))
3027 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3028 if (other->allocated && !other->hole_follows && other->color != cache_level)
3031 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3032 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3038 static void i915_gem_verify_gtt(struct drm_device *dev)
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct drm_i915_gem_object *obj;
3045 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3046 if (obj->gtt_space == NULL) {
3047 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3052 if (obj->cache_level != obj->gtt_space->color) {
3053 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3054 i915_gem_obj_ggtt_offset(obj),
3055 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3057 obj->gtt_space->color);
3062 if (!i915_gem_valid_gtt_space(dev,
3064 obj->cache_level)) {
3065 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3066 i915_gem_obj_ggtt_offset(obj),
3067 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3079 * Finds free space in the GTT aperture and binds the object there.
3082 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3084 bool map_and_fenceable,
3087 struct drm_device *dev = obj->base.dev;
3088 drm_i915_private_t *dev_priv = dev->dev_private;
3089 struct i915_address_space *vm = &dev_priv->gtt.base;
3090 u32 size, fence_size, fence_alignment, unfenced_alignment;
3091 bool mappable, fenceable;
3092 size_t gtt_max = map_and_fenceable ?
3093 dev_priv->gtt.mappable_end : dev_priv->gtt.base.total;
3094 struct i915_vma *vma;
3097 if (WARN_ON(!list_empty(&obj->vma_list)))
3100 fence_size = i915_gem_get_gtt_size(dev,
3103 fence_alignment = i915_gem_get_gtt_alignment(dev,
3105 obj->tiling_mode, true);
3106 unfenced_alignment =
3107 i915_gem_get_gtt_alignment(dev,
3109 obj->tiling_mode, false);
3112 alignment = map_and_fenceable ? fence_alignment :
3114 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3115 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3119 size = map_and_fenceable ? fence_size : obj->base.size;
3121 /* If the object is bigger than the entire aperture, reject it early
3122 * before evicting everything in a vain attempt to find space.
3124 if (obj->base.size > gtt_max) {
3125 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3127 map_and_fenceable ? "mappable" : "total",
3132 ret = i915_gem_object_get_pages(obj);
3136 i915_gem_object_pin_pages(obj);
3138 vma = i915_gem_vma_create(obj, &dev_priv->gtt.base);
3145 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
3148 obj->cache_level, 0, gtt_max);
3150 ret = i915_gem_evict_something(dev, size, alignment,
3159 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3160 obj->cache_level))) {
3162 goto err_remove_node;
3165 ret = i915_gem_gtt_prepare_object(obj);
3167 goto err_remove_node;
3169 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3170 list_add_tail(&obj->mm_list, &vm->inactive_list);
3171 list_add(&vma->vma_link, &obj->vma_list);
3174 i915_gem_obj_ggtt_size(obj) == fence_size &&
3175 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3177 mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <=
3178 dev_priv->gtt.mappable_end;
3180 obj->map_and_fenceable = mappable && fenceable;
3182 trace_i915_gem_object_bind(obj, map_and_fenceable);
3183 i915_gem_verify_gtt(dev);
3187 drm_mm_remove_node(&vma->node);
3189 i915_gem_vma_destroy(vma);
3191 i915_gem_object_unpin_pages(obj);
3196 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3198 /* If we don't have a page list set up, then we're not pinned
3199 * to GPU, and we can ignore the cache flush because it'll happen
3200 * again at bind time.
3202 if (obj->pages == NULL)
3206 * Stolen memory is always coherent with the GPU as it is explicitly
3207 * marked as wc by the system, or the system is cache-coherent.
3212 /* If the GPU is snooping the contents of the CPU cache,
3213 * we do not need to manually clear the CPU cache lines. However,
3214 * the caches are only snooped when the render cache is
3215 * flushed/invalidated. As we always have to emit invalidations
3216 * and flushes when moving into and out of the RENDER domain, correct
3217 * snooping behaviour occurs naturally as the result of our domain
3220 if (obj->cache_level != I915_CACHE_NONE)
3223 trace_i915_gem_object_clflush(obj);
3225 drm_clflush_sg(obj->pages);
3228 /** Flushes the GTT write domain for the object if it's dirty. */
3230 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3232 uint32_t old_write_domain;
3234 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3237 /* No actual flushing is required for the GTT write domain. Writes
3238 * to it immediately go to main memory as far as we know, so there's
3239 * no chipset flush. It also doesn't land in render cache.
3241 * However, we do have to enforce the order so that all writes through
3242 * the GTT land before any writes to the device, such as updates to
3247 old_write_domain = obj->base.write_domain;
3248 obj->base.write_domain = 0;
3250 trace_i915_gem_object_change_domain(obj,
3251 obj->base.read_domains,
3255 /** Flushes the CPU write domain for the object if it's dirty. */
3257 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3259 uint32_t old_write_domain;
3261 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3264 i915_gem_clflush_object(obj);
3265 i915_gem_chipset_flush(obj->base.dev);
3266 old_write_domain = obj->base.write_domain;
3267 obj->base.write_domain = 0;
3269 trace_i915_gem_object_change_domain(obj,
3270 obj->base.read_domains,
3275 * Moves a single object to the GTT read, and possibly write domain.
3277 * This function returns when the move is complete, including waiting on
3281 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3283 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3284 uint32_t old_write_domain, old_read_domains;
3287 /* Not valid to be called on unbound objects. */
3288 if (!i915_gem_obj_ggtt_bound(obj))
3291 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3294 ret = i915_gem_object_wait_rendering(obj, !write);
3298 i915_gem_object_flush_cpu_write_domain(obj);
3300 /* Serialise direct access to this object with the barriers for
3301 * coherent writes from the GPU, by effectively invalidating the
3302 * GTT domain upon first access.
3304 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3307 old_write_domain = obj->base.write_domain;
3308 old_read_domains = obj->base.read_domains;
3310 /* It should now be out of any other write domains, and we can update
3311 * the domain values for our changes.
3313 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3314 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3316 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3317 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3321 trace_i915_gem_object_change_domain(obj,
3325 /* And bump the LRU for this access */
3326 if (i915_gem_object_is_inactive(obj))
3327 list_move_tail(&obj->mm_list,
3328 &dev_priv->gtt.base.inactive_list);
3333 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3334 enum i915_cache_level cache_level)
3336 struct drm_device *dev = obj->base.dev;
3337 drm_i915_private_t *dev_priv = dev->dev_private;
3338 struct i915_vma *vma = __i915_gem_obj_to_vma(obj);
3341 if (obj->cache_level == cache_level)
3344 if (obj->pin_count) {
3345 DRM_DEBUG("can not change the cache level of pinned objects\n");
3349 if (vma && !i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3350 ret = i915_gem_object_unbind(obj);
3355 if (i915_gem_obj_ggtt_bound(obj)) {
3356 ret = i915_gem_object_finish_gpu(obj);
3360 i915_gem_object_finish_gtt(obj);
3362 /* Before SandyBridge, you could not use tiling or fence
3363 * registers with snooped memory, so relinquish any fences
3364 * currently pointing to our region in the aperture.
3366 if (INTEL_INFO(dev)->gen < 6) {
3367 ret = i915_gem_object_put_fence(obj);
3372 if (obj->has_global_gtt_mapping)
3373 i915_gem_gtt_bind_object(obj, cache_level);
3374 if (obj->has_aliasing_ppgtt_mapping)
3375 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3378 i915_gem_obj_ggtt_set_color(obj, cache_level);
3381 if (cache_level == I915_CACHE_NONE) {
3382 u32 old_read_domains, old_write_domain;
3384 /* If we're coming from LLC cached, then we haven't
3385 * actually been tracking whether the data is in the
3386 * CPU cache or not, since we only allow one bit set
3387 * in obj->write_domain and have been skipping the clflushes.
3388 * Just set it to the CPU cache for now.
3390 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3391 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3393 old_read_domains = obj->base.read_domains;
3394 old_write_domain = obj->base.write_domain;
3396 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3397 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3399 trace_i915_gem_object_change_domain(obj,
3404 obj->cache_level = cache_level;
3405 i915_gem_verify_gtt(dev);
3409 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3410 struct drm_file *file)
3412 struct drm_i915_gem_caching *args = data;
3413 struct drm_i915_gem_object *obj;
3416 ret = i915_mutex_lock_interruptible(dev);
3420 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3421 if (&obj->base == NULL) {
3426 args->caching = obj->cache_level != I915_CACHE_NONE;
3428 drm_gem_object_unreference(&obj->base);
3430 mutex_unlock(&dev->struct_mutex);
3434 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3435 struct drm_file *file)
3437 struct drm_i915_gem_caching *args = data;
3438 struct drm_i915_gem_object *obj;
3439 enum i915_cache_level level;
3442 switch (args->caching) {
3443 case I915_CACHING_NONE:
3444 level = I915_CACHE_NONE;
3446 case I915_CACHING_CACHED:
3447 level = I915_CACHE_LLC;
3453 ret = i915_mutex_lock_interruptible(dev);
3457 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3458 if (&obj->base == NULL) {
3463 ret = i915_gem_object_set_cache_level(obj, level);
3465 drm_gem_object_unreference(&obj->base);
3467 mutex_unlock(&dev->struct_mutex);
3472 * Prepare buffer for display plane (scanout, cursors, etc).
3473 * Can be called from an uninterruptible phase (modesetting) and allows
3474 * any flushes to be pipelined (for pageflips).
3477 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3479 struct intel_ring_buffer *pipelined)
3481 u32 old_read_domains, old_write_domain;
3484 if (pipelined != obj->ring) {
3485 ret = i915_gem_object_sync(obj, pipelined);
3490 /* The display engine is not coherent with the LLC cache on gen6. As
3491 * a result, we make sure that the pinning that is about to occur is
3492 * done with uncached PTEs. This is lowest common denominator for all
3495 * However for gen6+, we could do better by using the GFDT bit instead
3496 * of uncaching, which would allow us to flush all the LLC-cached data
3497 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3499 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3503 /* As the user may map the buffer once pinned in the display plane
3504 * (e.g. libkms for the bootup splash), we have to ensure that we
3505 * always use map_and_fenceable for all scanout buffers.
3507 ret = i915_gem_object_pin(obj, alignment, true, false);
3511 i915_gem_object_flush_cpu_write_domain(obj);
3513 old_write_domain = obj->base.write_domain;
3514 old_read_domains = obj->base.read_domains;
3516 /* It should now be out of any other write domains, and we can update
3517 * the domain values for our changes.
3519 obj->base.write_domain = 0;
3520 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3522 trace_i915_gem_object_change_domain(obj,
3530 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3534 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3537 ret = i915_gem_object_wait_rendering(obj, false);
3541 /* Ensure that we invalidate the GPU's caches and TLBs. */
3542 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3547 * Moves a single object to the CPU read, and possibly write domain.
3549 * This function returns when the move is complete, including waiting on
3553 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3555 uint32_t old_write_domain, old_read_domains;
3558 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3561 ret = i915_gem_object_wait_rendering(obj, !write);
3565 i915_gem_object_flush_gtt_write_domain(obj);
3567 old_write_domain = obj->base.write_domain;
3568 old_read_domains = obj->base.read_domains;
3570 /* Flush the CPU cache if it's still invalid. */
3571 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3572 i915_gem_clflush_object(obj);
3574 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3577 /* It should now be out of any other write domains, and we can update
3578 * the domain values for our changes.
3580 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3582 /* If we're writing through the CPU, then the GPU read domains will
3583 * need to be invalidated at next use.
3586 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3587 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3590 trace_i915_gem_object_change_domain(obj,
3597 /* Throttle our rendering by waiting until the ring has completed our requests
3598 * emitted over 20 msec ago.
3600 * Note that if we were to use the current jiffies each time around the loop,
3601 * we wouldn't escape the function with any frames outstanding if the time to
3602 * render a frame was over 20ms.
3604 * This should get us reasonable parallelism between CPU and GPU but also
3605 * relatively low latency when blocking on a particular request to finish.
3608 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct drm_i915_file_private *file_priv = file->driver_priv;
3612 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3613 struct drm_i915_gem_request *request;
3614 struct intel_ring_buffer *ring = NULL;
3615 unsigned reset_counter;
3619 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3623 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3627 spin_lock(&file_priv->mm.lock);
3628 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3629 if (time_after_eq(request->emitted_jiffies, recent_enough))
3632 ring = request->ring;
3633 seqno = request->seqno;
3635 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3636 spin_unlock(&file_priv->mm.lock);
3641 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3643 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3649 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3651 bool map_and_fenceable,
3656 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3659 if (i915_gem_obj_ggtt_bound(obj)) {
3660 if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) ||
3661 (map_and_fenceable && !obj->map_and_fenceable)) {
3662 WARN(obj->pin_count,
3663 "bo is already pinned with incorrect alignment:"
3664 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3665 " obj->map_and_fenceable=%d\n",
3666 i915_gem_obj_ggtt_offset(obj), alignment,
3668 obj->map_and_fenceable);
3669 ret = i915_gem_object_unbind(obj);
3675 if (!i915_gem_obj_ggtt_bound(obj)) {
3676 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3678 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3684 if (!dev_priv->mm.aliasing_ppgtt)
3685 i915_gem_gtt_bind_object(obj, obj->cache_level);
3688 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3689 i915_gem_gtt_bind_object(obj, obj->cache_level);
3692 obj->pin_mappable |= map_and_fenceable;
3698 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3700 BUG_ON(obj->pin_count == 0);
3701 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3703 if (--obj->pin_count == 0)
3704 obj->pin_mappable = false;
3708 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3709 struct drm_file *file)
3711 struct drm_i915_gem_pin *args = data;
3712 struct drm_i915_gem_object *obj;
3715 ret = i915_mutex_lock_interruptible(dev);
3719 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3720 if (&obj->base == NULL) {
3725 if (obj->madv != I915_MADV_WILLNEED) {
3726 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3731 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3732 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3738 if (obj->user_pin_count == 0) {
3739 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3744 obj->user_pin_count++;
3745 obj->pin_filp = file;
3747 /* XXX - flush the CPU caches for pinned objects
3748 * as the X server doesn't manage domains yet
3750 i915_gem_object_flush_cpu_write_domain(obj);
3751 args->offset = i915_gem_obj_ggtt_offset(obj);
3753 drm_gem_object_unreference(&obj->base);
3755 mutex_unlock(&dev->struct_mutex);
3760 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3761 struct drm_file *file)
3763 struct drm_i915_gem_pin *args = data;
3764 struct drm_i915_gem_object *obj;
3767 ret = i915_mutex_lock_interruptible(dev);
3771 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3772 if (&obj->base == NULL) {
3777 if (obj->pin_filp != file) {
3778 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3783 obj->user_pin_count--;
3784 if (obj->user_pin_count == 0) {
3785 obj->pin_filp = NULL;
3786 i915_gem_object_unpin(obj);
3790 drm_gem_object_unreference(&obj->base);
3792 mutex_unlock(&dev->struct_mutex);
3797 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3798 struct drm_file *file)
3800 struct drm_i915_gem_busy *args = data;
3801 struct drm_i915_gem_object *obj;
3804 ret = i915_mutex_lock_interruptible(dev);
3808 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3809 if (&obj->base == NULL) {
3814 /* Count all active objects as busy, even if they are currently not used
3815 * by the gpu. Users of this interface expect objects to eventually
3816 * become non-busy without any further actions, therefore emit any
3817 * necessary flushes here.
3819 ret = i915_gem_object_flush_active(obj);
3821 args->busy = obj->active;
3823 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3824 args->busy |= intel_ring_flag(obj->ring) << 16;
3827 drm_gem_object_unreference(&obj->base);
3829 mutex_unlock(&dev->struct_mutex);
3834 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3835 struct drm_file *file_priv)
3837 return i915_gem_ring_throttle(dev, file_priv);
3841 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3842 struct drm_file *file_priv)
3844 struct drm_i915_gem_madvise *args = data;
3845 struct drm_i915_gem_object *obj;
3848 switch (args->madv) {
3849 case I915_MADV_DONTNEED:
3850 case I915_MADV_WILLNEED:
3856 ret = i915_mutex_lock_interruptible(dev);
3860 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3861 if (&obj->base == NULL) {
3866 if (obj->pin_count) {
3871 if (obj->madv != __I915_MADV_PURGED)
3872 obj->madv = args->madv;
3874 /* if the object is no longer attached, discard its backing storage */
3875 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3876 i915_gem_object_truncate(obj);
3878 args->retained = obj->madv != __I915_MADV_PURGED;
3881 drm_gem_object_unreference(&obj->base);
3883 mutex_unlock(&dev->struct_mutex);
3887 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3888 const struct drm_i915_gem_object_ops *ops)
3890 INIT_LIST_HEAD(&obj->mm_list);
3891 INIT_LIST_HEAD(&obj->global_list);
3892 INIT_LIST_HEAD(&obj->ring_list);
3893 INIT_LIST_HEAD(&obj->exec_list);
3894 INIT_LIST_HEAD(&obj->vma_list);
3898 obj->fence_reg = I915_FENCE_REG_NONE;
3899 obj->madv = I915_MADV_WILLNEED;
3900 /* Avoid an unnecessary call to unbind on the first bind. */
3901 obj->map_and_fenceable = true;
3903 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3906 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3907 .get_pages = i915_gem_object_get_pages_gtt,
3908 .put_pages = i915_gem_object_put_pages_gtt,
3911 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3914 struct drm_i915_gem_object *obj;
3915 struct address_space *mapping;
3918 obj = i915_gem_object_alloc(dev);
3922 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3923 i915_gem_object_free(obj);
3927 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3928 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3929 /* 965gm cannot relocate objects above 4GiB. */
3930 mask &= ~__GFP_HIGHMEM;
3931 mask |= __GFP_DMA32;
3934 mapping = file_inode(obj->base.filp)->i_mapping;
3935 mapping_set_gfp_mask(mapping, mask);
3937 i915_gem_object_init(obj, &i915_gem_object_ops);
3939 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3940 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3943 /* On some devices, we can have the GPU use the LLC (the CPU
3944 * cache) for about a 10% performance improvement
3945 * compared to uncached. Graphics requests other than
3946 * display scanout are coherent with the CPU in
3947 * accessing this cache. This means in this mode we
3948 * don't need to clflush on the CPU side, and on the
3949 * GPU side we only need to flush internal caches to
3950 * get data visible to the CPU.
3952 * However, we maintain the display planes as UC, and so
3953 * need to rebind when first used as such.
3955 obj->cache_level = I915_CACHE_LLC;
3957 obj->cache_level = I915_CACHE_NONE;
3962 int i915_gem_init_object(struct drm_gem_object *obj)
3969 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3971 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3972 struct drm_device *dev = obj->base.dev;
3973 drm_i915_private_t *dev_priv = dev->dev_private;
3975 trace_i915_gem_object_destroy(obj);
3978 i915_gem_detach_phys_object(dev, obj);
3981 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3982 bool was_interruptible;
3984 was_interruptible = dev_priv->mm.interruptible;
3985 dev_priv->mm.interruptible = false;
3987 WARN_ON(i915_gem_object_unbind(obj));
3989 dev_priv->mm.interruptible = was_interruptible;
3992 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3993 * before progressing. */
3995 i915_gem_object_unpin_pages(obj);
3997 if (WARN_ON(obj->pages_pin_count))
3998 obj->pages_pin_count = 0;
3999 i915_gem_object_put_pages(obj);
4000 i915_gem_object_free_mmap_offset(obj);
4001 i915_gem_object_release_stolen(obj);
4005 if (obj->base.import_attach)
4006 drm_prime_gem_destroy(&obj->base, NULL);
4008 drm_gem_object_release(&obj->base);
4009 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4012 i915_gem_object_free(obj);
4015 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4016 struct i915_address_space *vm)
4018 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4020 return ERR_PTR(-ENOMEM);
4022 INIT_LIST_HEAD(&vma->vma_link);
4029 void i915_gem_vma_destroy(struct i915_vma *vma)
4031 WARN_ON(vma->node.allocated);
4036 i915_gem_idle(struct drm_device *dev)
4038 drm_i915_private_t *dev_priv = dev->dev_private;
4041 if (dev_priv->ums.mm_suspended) {
4042 mutex_unlock(&dev->struct_mutex);
4046 ret = i915_gpu_idle(dev);
4048 mutex_unlock(&dev->struct_mutex);
4051 i915_gem_retire_requests(dev);
4053 /* Under UMS, be paranoid and evict. */
4054 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4055 i915_gem_evict_everything(dev);
4057 i915_gem_reset_fences(dev);
4059 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4061 i915_kernel_lost_context(dev);
4062 i915_gem_cleanup_ringbuffer(dev);
4064 /* Cancel the retire work handler, which should be idle now. */
4065 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4070 void i915_gem_l3_remap(struct drm_device *dev)
4072 drm_i915_private_t *dev_priv = dev->dev_private;
4076 if (!HAS_L3_GPU_CACHE(dev))
4079 if (!dev_priv->l3_parity.remap_info)
4082 misccpctl = I915_READ(GEN7_MISCCPCTL);
4083 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4084 POSTING_READ(GEN7_MISCCPCTL);
4086 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4087 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4088 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4089 DRM_DEBUG("0x%x was already programmed to %x\n",
4090 GEN7_L3LOG_BASE + i, remap);
4091 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4092 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4093 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4096 /* Make sure all the writes land before disabling dop clock gating */
4097 POSTING_READ(GEN7_L3LOG_BASE);
4099 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4102 void i915_gem_init_swizzling(struct drm_device *dev)
4104 drm_i915_private_t *dev_priv = dev->dev_private;
4106 if (INTEL_INFO(dev)->gen < 5 ||
4107 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4110 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4111 DISP_TILE_SURFACE_SWIZZLING);
4116 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4118 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4119 else if (IS_GEN7(dev))
4120 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4126 intel_enable_blt(struct drm_device *dev)
4131 /* The blitter was dysfunctional on early prototypes */
4132 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4133 DRM_INFO("BLT not supported on this pre-production hardware;"
4134 " graphics performance will be degraded.\n");
4141 static int i915_gem_init_rings(struct drm_device *dev)
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4146 ret = intel_init_render_ring_buffer(dev);
4151 ret = intel_init_bsd_ring_buffer(dev);
4153 goto cleanup_render_ring;
4156 if (intel_enable_blt(dev)) {
4157 ret = intel_init_blt_ring_buffer(dev);
4159 goto cleanup_bsd_ring;
4162 if (HAS_VEBOX(dev)) {
4163 ret = intel_init_vebox_ring_buffer(dev);
4165 goto cleanup_blt_ring;
4169 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4171 goto cleanup_vebox_ring;
4176 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4178 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4180 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4181 cleanup_render_ring:
4182 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4188 i915_gem_init_hw(struct drm_device *dev)
4190 drm_i915_private_t *dev_priv = dev->dev_private;
4193 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4196 if (dev_priv->ellc_size)
4197 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4199 if (HAS_PCH_NOP(dev)) {
4200 u32 temp = I915_READ(GEN7_MSG_CTL);
4201 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4202 I915_WRITE(GEN7_MSG_CTL, temp);
4205 i915_gem_l3_remap(dev);
4207 i915_gem_init_swizzling(dev);
4209 ret = i915_gem_init_rings(dev);
4214 * XXX: There was some w/a described somewhere suggesting loading
4215 * contexts before PPGTT.
4217 i915_gem_context_init(dev);
4218 if (dev_priv->mm.aliasing_ppgtt) {
4219 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4221 i915_gem_cleanup_aliasing_ppgtt(dev);
4222 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4229 int i915_gem_init(struct drm_device *dev)
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4234 mutex_lock(&dev->struct_mutex);
4236 if (IS_VALLEYVIEW(dev)) {
4237 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4238 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4239 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4240 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4243 i915_gem_init_global_gtt(dev);
4245 ret = i915_gem_init_hw(dev);
4246 mutex_unlock(&dev->struct_mutex);
4248 i915_gem_cleanup_aliasing_ppgtt(dev);
4252 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4253 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4254 dev_priv->dri1.allow_batchbuffer = 1;
4259 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4261 drm_i915_private_t *dev_priv = dev->dev_private;
4262 struct intel_ring_buffer *ring;
4265 for_each_ring(ring, dev_priv, i)
4266 intel_cleanup_ring_buffer(ring);
4270 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4271 struct drm_file *file_priv)
4273 struct drm_i915_private *dev_priv = dev->dev_private;
4276 if (drm_core_check_feature(dev, DRIVER_MODESET))
4279 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4280 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4281 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4284 mutex_lock(&dev->struct_mutex);
4285 dev_priv->ums.mm_suspended = 0;
4287 ret = i915_gem_init_hw(dev);
4289 mutex_unlock(&dev->struct_mutex);
4293 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4294 mutex_unlock(&dev->struct_mutex);
4296 ret = drm_irq_install(dev);
4298 goto cleanup_ringbuffer;
4303 mutex_lock(&dev->struct_mutex);
4304 i915_gem_cleanup_ringbuffer(dev);
4305 dev_priv->ums.mm_suspended = 1;
4306 mutex_unlock(&dev->struct_mutex);
4312 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4313 struct drm_file *file_priv)
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4318 if (drm_core_check_feature(dev, DRIVER_MODESET))
4321 drm_irq_uninstall(dev);
4323 mutex_lock(&dev->struct_mutex);
4324 ret = i915_gem_idle(dev);
4326 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4327 * We need to replace this with a semaphore, or something.
4328 * And not confound ums.mm_suspended!
4331 dev_priv->ums.mm_suspended = 1;
4332 mutex_unlock(&dev->struct_mutex);
4338 i915_gem_lastclose(struct drm_device *dev)
4342 if (drm_core_check_feature(dev, DRIVER_MODESET))
4345 mutex_lock(&dev->struct_mutex);
4346 ret = i915_gem_idle(dev);
4348 DRM_ERROR("failed to idle hardware: %d\n", ret);
4349 mutex_unlock(&dev->struct_mutex);
4353 init_ring_lists(struct intel_ring_buffer *ring)
4355 INIT_LIST_HEAD(&ring->active_list);
4356 INIT_LIST_HEAD(&ring->request_list);
4360 i915_gem_load(struct drm_device *dev)
4362 drm_i915_private_t *dev_priv = dev->dev_private;
4366 kmem_cache_create("i915_gem_object",
4367 sizeof(struct drm_i915_gem_object), 0,
4371 INIT_LIST_HEAD(&dev_priv->gtt.base.active_list);
4372 INIT_LIST_HEAD(&dev_priv->gtt.base.inactive_list);
4373 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4374 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4375 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4376 for (i = 0; i < I915_NUM_RINGS; i++)
4377 init_ring_lists(&dev_priv->ring[i]);
4378 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4379 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4380 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4381 i915_gem_retire_work_handler);
4382 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4384 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4386 I915_WRITE(MI_ARB_STATE,
4387 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4390 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4392 /* Old X drivers will take 0-2 for front, back, depth buffers */
4393 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4394 dev_priv->fence_reg_start = 3;
4396 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4397 dev_priv->num_fence_regs = 32;
4398 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4399 dev_priv->num_fence_regs = 16;
4401 dev_priv->num_fence_regs = 8;
4403 /* Initialize fence registers to zero */
4404 i915_gem_reset_fences(dev);
4406 i915_gem_detect_bit_6_swizzle(dev);
4407 init_waitqueue_head(&dev_priv->pending_flip_queue);
4409 dev_priv->mm.interruptible = true;
4411 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4412 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4413 register_shrinker(&dev_priv->mm.inactive_shrinker);
4417 * Create a physically contiguous memory object for this object
4418 * e.g. for cursor + overlay regs
4420 static int i915_gem_init_phys_object(struct drm_device *dev,
4421 int id, int size, int align)
4423 drm_i915_private_t *dev_priv = dev->dev_private;
4424 struct drm_i915_gem_phys_object *phys_obj;
4427 if (dev_priv->mm.phys_objs[id - 1] || !size)
4430 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4436 phys_obj->handle = drm_pci_alloc(dev, size, align);
4437 if (!phys_obj->handle) {
4442 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4445 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4453 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4455 drm_i915_private_t *dev_priv = dev->dev_private;
4456 struct drm_i915_gem_phys_object *phys_obj;
4458 if (!dev_priv->mm.phys_objs[id - 1])
4461 phys_obj = dev_priv->mm.phys_objs[id - 1];
4462 if (phys_obj->cur_obj) {
4463 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4467 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4469 drm_pci_free(dev, phys_obj->handle);
4471 dev_priv->mm.phys_objs[id - 1] = NULL;
4474 void i915_gem_free_all_phys_object(struct drm_device *dev)
4478 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4479 i915_gem_free_phys_object(dev, i);
4482 void i915_gem_detach_phys_object(struct drm_device *dev,
4483 struct drm_i915_gem_object *obj)
4485 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4492 vaddr = obj->phys_obj->handle->vaddr;
4494 page_count = obj->base.size / PAGE_SIZE;
4495 for (i = 0; i < page_count; i++) {
4496 struct page *page = shmem_read_mapping_page(mapping, i);
4497 if (!IS_ERR(page)) {
4498 char *dst = kmap_atomic(page);
4499 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4502 drm_clflush_pages(&page, 1);
4504 set_page_dirty(page);
4505 mark_page_accessed(page);
4506 page_cache_release(page);
4509 i915_gem_chipset_flush(dev);
4511 obj->phys_obj->cur_obj = NULL;
4512 obj->phys_obj = NULL;
4516 i915_gem_attach_phys_object(struct drm_device *dev,
4517 struct drm_i915_gem_object *obj,
4521 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4522 drm_i915_private_t *dev_priv = dev->dev_private;
4527 if (id > I915_MAX_PHYS_OBJECT)
4530 if (obj->phys_obj) {
4531 if (obj->phys_obj->id == id)
4533 i915_gem_detach_phys_object(dev, obj);
4536 /* create a new object */
4537 if (!dev_priv->mm.phys_objs[id - 1]) {
4538 ret = i915_gem_init_phys_object(dev, id,
4539 obj->base.size, align);
4541 DRM_ERROR("failed to init phys object %d size: %zu\n",
4542 id, obj->base.size);
4547 /* bind to the object */
4548 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4549 obj->phys_obj->cur_obj = obj;
4551 page_count = obj->base.size / PAGE_SIZE;
4553 for (i = 0; i < page_count; i++) {
4557 page = shmem_read_mapping_page(mapping, i);
4559 return PTR_ERR(page);
4561 src = kmap_atomic(page);
4562 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4563 memcpy(dst, src, PAGE_SIZE);
4566 mark_page_accessed(page);
4567 page_cache_release(page);
4574 i915_gem_phys_pwrite(struct drm_device *dev,
4575 struct drm_i915_gem_object *obj,
4576 struct drm_i915_gem_pwrite *args,
4577 struct drm_file *file_priv)
4579 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4580 char __user *user_data = to_user_ptr(args->data_ptr);
4582 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4583 unsigned long unwritten;
4585 /* The physical object once assigned is fixed for the lifetime
4586 * of the obj, so we can safely drop the lock and continue
4589 mutex_unlock(&dev->struct_mutex);
4590 unwritten = copy_from_user(vaddr, user_data, args->size);
4591 mutex_lock(&dev->struct_mutex);
4596 i915_gem_chipset_flush(dev);
4600 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4602 struct drm_i915_file_private *file_priv = file->driver_priv;
4604 /* Clean up our request list when the client is going away, so that
4605 * later retire_requests won't dereference our soon-to-be-gone
4608 spin_lock(&file_priv->mm.lock);
4609 while (!list_empty(&file_priv->mm.request_list)) {
4610 struct drm_i915_gem_request *request;
4612 request = list_first_entry(&file_priv->mm.request_list,
4613 struct drm_i915_gem_request,
4615 list_del(&request->client_list);
4616 request->file_priv = NULL;
4618 spin_unlock(&file_priv->mm.lock);
4621 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4623 if (!mutex_is_locked(mutex))
4626 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4627 return mutex->owner == task;
4629 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4635 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4637 struct drm_i915_private *dev_priv =
4638 container_of(shrinker,
4639 struct drm_i915_private,
4640 mm.inactive_shrinker);
4641 struct drm_device *dev = dev_priv->dev;
4642 struct i915_address_space *vm = &dev_priv->gtt.base;
4643 struct drm_i915_gem_object *obj;
4644 int nr_to_scan = sc->nr_to_scan;
4648 if (!mutex_trylock(&dev->struct_mutex)) {
4649 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4652 if (dev_priv->mm.shrinker_no_lock_stealing)
4659 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4661 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4664 i915_gem_shrink_all(dev_priv);
4668 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4669 if (obj->pages_pin_count == 0)
4670 cnt += obj->base.size >> PAGE_SHIFT;
4671 list_for_each_entry(obj, &vm->inactive_list, global_list)
4672 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4673 cnt += obj->base.size >> PAGE_SHIFT;
4676 mutex_unlock(&dev->struct_mutex);