2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 struct change_domains {
37 uint32_t invalidate_domains;
38 uint32_t flush_domains;
44 * Set the next domain for the specified object. This
45 * may not actually perform the necessary flushing/invaliding though,
46 * as that may want to be batched with other set_domain operations
48 * This is (we hope) the only really tricky part of gem. The goal
49 * is fairly simple -- track which caches hold bits of the object
50 * and make sure they remain coherent. A few concrete examples may
51 * help to explain how it works. For shorthand, we use the notation
52 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
53 * a pair of read and write domain masks.
55 * Case 1: the batch buffer
61 * 5. Unmapped from GTT
64 * Let's take these a step at a time
67 * Pages allocated from the kernel may still have
68 * cache contents, so we set them to (CPU, CPU) always.
69 * 2. Written by CPU (using pwrite)
70 * The pwrite function calls set_domain (CPU, CPU) and
71 * this function does nothing (as nothing changes)
73 * This function asserts that the object is not
74 * currently in any GPU-based read or write domains
76 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
77 * As write_domain is zero, this function adds in the
78 * current read domains (CPU+COMMAND, 0).
79 * flush_domains is set to CPU.
80 * invalidate_domains is set to COMMAND
81 * clflush is run to get data out of the CPU caches
82 * then i915_dev_set_domain calls i915_gem_flush to
83 * emit an MI_FLUSH and drm_agp_chipset_flush
84 * 5. Unmapped from GTT
85 * i915_gem_object_unbind calls set_domain (CPU, CPU)
86 * flush_domains and invalidate_domains end up both zero
87 * so no flushing/invalidating happens
91 * Case 2: The shared render buffer
95 * 3. Read/written by GPU
96 * 4. set_domain to (CPU,CPU)
97 * 5. Read/written by CPU
98 * 6. Read/written by GPU
101 * Same as last example, (CPU, CPU)
103 * Nothing changes (assertions find that it is not in the GPU)
104 * 3. Read/written by GPU
105 * execbuffer calls set_domain (RENDER, RENDER)
106 * flush_domains gets CPU
107 * invalidate_domains gets GPU
109 * MI_FLUSH and drm_agp_chipset_flush
110 * 4. set_domain (CPU, CPU)
111 * flush_domains gets GPU
112 * invalidate_domains gets CPU
113 * wait_rendering (obj) to make sure all drawing is complete.
114 * This will include an MI_FLUSH to get the data from GPU
116 * clflush (obj) to invalidate the CPU cache
117 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
118 * 5. Read/written by CPU
119 * cache lines are loaded and dirtied
120 * 6. Read written by GPU
121 * Same as last GPU access
123 * Case 3: The constant buffer
128 * 4. Updated (written) by CPU again
137 * flush_domains = CPU
138 * invalidate_domains = RENDER
141 * drm_agp_chipset_flush
142 * 4. Updated (written) by CPU again
144 * flush_domains = 0 (no previous write domain)
145 * invalidate_domains = 0 (no new read domains)
148 * flush_domains = CPU
149 * invalidate_domains = RENDER
152 * drm_agp_chipset_flush
155 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
156 struct intel_ring_buffer *ring,
157 struct change_domains *cd)
159 uint32_t invalidate_domains = 0, flush_domains = 0;
162 * If the object isn't moving to a new write domain,
163 * let the object stay in multiple read domains
165 if (obj->base.pending_write_domain == 0)
166 obj->base.pending_read_domains |= obj->base.read_domains;
169 * Flush the current write domain if
170 * the new read domains don't match. Invalidate
171 * any read domains which differ from the old
174 if (obj->base.write_domain &&
175 (((obj->base.write_domain != obj->base.pending_read_domains ||
176 obj->ring != ring)) ||
177 (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
178 flush_domains |= obj->base.write_domain;
179 invalidate_domains |=
180 obj->base.pending_read_domains & ~obj->base.write_domain;
183 * Invalidate any read caches which may have
184 * stale data. That is, any new read domains.
186 invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
188 i915_gem_clflush_object(obj);
190 /* blow away mappings if mapped through GTT */
191 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
192 i915_gem_release_mmap(obj);
194 if (obj->base.pending_write_domain)
195 cd->flips |= atomic_read(&obj->pending_flip);
197 /* The actual obj->write_domain will be updated with
198 * pending_write_domain after we emit the accumulated flush for all
199 * of our domain changes in execbuffers (which clears objects'
200 * write_domains). So if we have a current write domain that we
201 * aren't changing, set pending_write_domain to that.
203 if (flush_domains == 0 && obj->base.pending_write_domain == 0)
204 obj->base.pending_write_domain = obj->base.write_domain;
206 cd->invalidate_domains |= invalidate_domains;
207 cd->flush_domains |= flush_domains;
208 if (flush_domains & I915_GEM_GPU_DOMAINS)
209 cd->flush_rings |= obj->ring->id;
210 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
211 cd->flush_rings |= ring->id;
216 struct hlist_head buckets[0];
219 static struct eb_objects *
222 struct eb_objects *eb;
223 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
226 eb = kzalloc(count*sizeof(struct hlist_head) +
227 sizeof(struct eb_objects),
237 eb_reset(struct eb_objects *eb)
239 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
243 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
245 hlist_add_head(&obj->exec_node,
246 &eb->buckets[obj->exec_handle & eb->and]);
249 static struct drm_i915_gem_object *
250 eb_get_object(struct eb_objects *eb, unsigned long handle)
252 struct hlist_head *head;
253 struct hlist_node *node;
254 struct drm_i915_gem_object *obj;
256 head = &eb->buckets[handle & eb->and];
257 hlist_for_each(node, head) {
258 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
259 if (obj->exec_handle == handle)
267 eb_destroy(struct eb_objects *eb)
273 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
274 struct eb_objects *eb,
275 struct drm_i915_gem_relocation_entry *reloc)
277 struct drm_device *dev = obj->base.dev;
278 struct drm_gem_object *target_obj;
279 uint32_t target_offset;
282 /* we've already hold a reference to all valid objects */
283 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
284 if (unlikely(target_obj == NULL))
287 target_offset = to_intel_bo(target_obj)->gtt_offset;
289 /* The target buffer should have appeared before us in the
290 * exec_object list, so it should have a GTT space bound by now.
292 if (unlikely(target_offset == 0)) {
293 DRM_ERROR("No GTT space found for object %d\n",
294 reloc->target_handle);
298 /* Validate that the target is in a valid r/w GPU domain */
299 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
300 DRM_ERROR("reloc with multiple write domains: "
301 "obj %p target %d offset %d "
302 "read %08x write %08x",
303 obj, reloc->target_handle,
306 reloc->write_domain);
309 if (unlikely((reloc->write_domain | reloc->read_domains) & I915_GEM_DOMAIN_CPU)) {
310 DRM_ERROR("reloc with read/write CPU domains: "
311 "obj %p target %d offset %d "
312 "read %08x write %08x",
313 obj, reloc->target_handle,
316 reloc->write_domain);
319 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
320 reloc->write_domain != target_obj->pending_write_domain)) {
321 DRM_ERROR("Write domain conflict: "
322 "obj %p target %d offset %d "
323 "new %08x old %08x\n",
324 obj, reloc->target_handle,
327 target_obj->pending_write_domain);
331 target_obj->pending_read_domains |= reloc->read_domains;
332 target_obj->pending_write_domain |= reloc->write_domain;
334 /* If the relocation already has the right value in it, no
335 * more work needs to be done.
337 if (target_offset == reloc->presumed_offset)
340 /* Check that the relocation address is valid... */
341 if (unlikely(reloc->offset > obj->base.size - 4)) {
342 DRM_ERROR("Relocation beyond object bounds: "
343 "obj %p target %d offset %d size %d.\n",
344 obj, reloc->target_handle,
346 (int) obj->base.size);
349 if (unlikely(reloc->offset & 3)) {
350 DRM_ERROR("Relocation not 4-byte aligned: "
351 "obj %p target %d offset %d.\n",
352 obj, reloc->target_handle,
353 (int) reloc->offset);
357 reloc->delta += target_offset;
358 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
359 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
362 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
363 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
364 kunmap_atomic(vaddr);
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 uint32_t __iomem *reloc_entry;
368 void __iomem *reloc_page;
370 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
374 /* Map the page containing the relocation we're going to perform. */
375 reloc->offset += obj->gtt_offset;
376 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
377 reloc->offset & PAGE_MASK);
378 reloc_entry = (uint32_t __iomem *)
379 (reloc_page + (reloc->offset & ~PAGE_MASK));
380 iowrite32(reloc->delta, reloc_entry);
381 io_mapping_unmap_atomic(reloc_page);
384 /* and update the user's relocation entry */
385 reloc->presumed_offset = target_offset;
391 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
392 struct eb_objects *eb)
394 struct drm_i915_gem_relocation_entry __user *user_relocs;
395 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
398 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
399 for (i = 0; i < entry->relocation_count; i++) {
400 struct drm_i915_gem_relocation_entry reloc;
402 if (__copy_from_user_inatomic(&reloc,
407 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
411 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
412 &reloc.presumed_offset,
413 sizeof(reloc.presumed_offset)))
421 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
422 struct eb_objects *eb,
423 struct drm_i915_gem_relocation_entry *relocs)
425 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
428 for (i = 0; i < entry->relocation_count; i++) {
429 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
438 i915_gem_execbuffer_relocate(struct drm_device *dev,
439 struct eb_objects *eb,
440 struct list_head *objects)
442 struct drm_i915_gem_object *obj;
445 list_for_each_entry(obj, objects, exec_list) {
446 ret = i915_gem_execbuffer_relocate_object(obj, eb);
455 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
456 struct drm_file *file,
457 struct list_head *objects)
459 struct drm_i915_gem_object *obj;
461 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
462 struct list_head ordered_objects;
464 INIT_LIST_HEAD(&ordered_objects);
465 while (!list_empty(objects)) {
466 struct drm_i915_gem_exec_object2 *entry;
467 bool need_fence, need_mappable;
469 obj = list_first_entry(objects,
470 struct drm_i915_gem_object,
472 entry = obj->exec_entry;
475 has_fenced_gpu_access &&
476 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
477 obj->tiling_mode != I915_TILING_NONE;
479 entry->relocation_count ? true : need_fence;
482 list_move(&obj->exec_list, &ordered_objects);
484 list_move_tail(&obj->exec_list, &ordered_objects);
486 obj->base.pending_read_domains = 0;
487 obj->base.pending_write_domain = 0;
489 list_splice(&ordered_objects, objects);
491 /* Attempt to pin all of the buffers into the GTT.
492 * This is done in 3 phases:
494 * 1a. Unbind all objects that do not match the GTT constraints for
495 * the execbuffer (fenceable, mappable, alignment etc).
496 * 1b. Increment pin count for already bound objects.
497 * 2. Bind new objects.
498 * 3. Decrement pin count.
500 * This avoid unnecessary unbinding of later objects in order to makr
501 * room for the earlier objects *unless* we need to defragment.
507 /* Unbind any ill-fitting objects or pin. */
508 list_for_each_entry(obj, objects, exec_list) {
509 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
510 bool need_fence, need_mappable;
515 has_fenced_gpu_access &&
516 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
517 obj->tiling_mode != I915_TILING_NONE;
519 entry->relocation_count ? true : need_fence;
521 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
522 (need_mappable && !obj->map_and_fenceable))
523 ret = i915_gem_object_unbind(obj);
525 ret = i915_gem_object_pin(obj,
534 /* Bind fresh objects */
535 list_for_each_entry(obj, objects, exec_list) {
536 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
540 has_fenced_gpu_access &&
541 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
542 obj->tiling_mode != I915_TILING_NONE;
544 if (!obj->gtt_space) {
546 entry->relocation_count ? true : need_fence;
548 ret = i915_gem_object_pin(obj,
555 if (has_fenced_gpu_access) {
557 ret = i915_gem_object_get_fence(obj, ring);
560 } else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
561 obj->tiling_mode == I915_TILING_NONE) {
563 ret = i915_gem_object_put_fence(obj);
567 obj->pending_fenced_gpu_access = need_fence;
570 entry->offset = obj->gtt_offset;
573 /* Decrement pin count for bound objects */
574 list_for_each_entry(obj, objects, exec_list) {
576 i915_gem_object_unpin(obj);
579 if (ret != -ENOSPC || retry > 1)
582 /* First attempt, just clear anything that is purgeable.
583 * Second attempt, clear the entire GTT.
585 ret = i915_gem_evict_everything(ring->dev, retry == 0);
593 obj = list_entry(obj->exec_list.prev,
594 struct drm_i915_gem_object,
596 while (objects != &obj->exec_list) {
598 i915_gem_object_unpin(obj);
600 obj = list_entry(obj->exec_list.prev,
601 struct drm_i915_gem_object,
609 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
610 struct drm_file *file,
611 struct intel_ring_buffer *ring,
612 struct list_head *objects,
613 struct eb_objects *eb,
614 struct drm_i915_gem_exec_object2 *exec,
617 struct drm_i915_gem_relocation_entry *reloc;
618 struct drm_i915_gem_object *obj;
622 /* We may process another execbuffer during the unlock... */
623 while (!list_empty(objects)) {
624 obj = list_first_entry(objects,
625 struct drm_i915_gem_object,
627 list_del_init(&obj->exec_list);
628 drm_gem_object_unreference(&obj->base);
631 mutex_unlock(&dev->struct_mutex);
634 for (i = 0; i < count; i++)
635 total += exec[i].relocation_count;
637 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
638 reloc = drm_malloc_ab(total, sizeof(*reloc));
639 if (reloc == NULL || reloc_offset == NULL) {
640 drm_free_large(reloc);
641 drm_free_large(reloc_offset);
642 mutex_lock(&dev->struct_mutex);
647 for (i = 0; i < count; i++) {
648 struct drm_i915_gem_relocation_entry __user *user_relocs;
650 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
652 if (copy_from_user(reloc+total, user_relocs,
653 exec[i].relocation_count * sizeof(*reloc))) {
655 mutex_lock(&dev->struct_mutex);
659 reloc_offset[i] = total;
660 total += exec[i].relocation_count;
663 ret = i915_mutex_lock_interruptible(dev);
665 mutex_lock(&dev->struct_mutex);
669 /* reacquire the objects */
671 for (i = 0; i < count; i++) {
672 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
674 if (&obj->base == NULL) {
675 DRM_ERROR("Invalid object handle %d at index %d\n",
681 list_add_tail(&obj->exec_list, objects);
682 obj->exec_handle = exec[i].handle;
683 obj->exec_entry = &exec[i];
684 eb_add_object(eb, obj);
687 ret = i915_gem_execbuffer_reserve(ring, file, objects);
691 list_for_each_entry(obj, objects, exec_list) {
692 int offset = obj->exec_entry - exec;
693 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
694 reloc + reloc_offset[offset]);
699 /* Leave the user relocations as are, this is the painfully slow path,
700 * and we want to avoid the complication of dropping the lock whilst
701 * having buffers reserved in the aperture and so causing spurious
702 * ENOSPC for random operations.
706 drm_free_large(reloc);
707 drm_free_large(reloc_offset);
712 i915_gem_execbuffer_flush(struct drm_device *dev,
713 uint32_t invalidate_domains,
714 uint32_t flush_domains,
715 uint32_t flush_rings)
717 drm_i915_private_t *dev_priv = dev->dev_private;
720 if (flush_domains & I915_GEM_DOMAIN_CPU)
721 intel_gtt_chipset_flush();
723 if (flush_domains & I915_GEM_DOMAIN_GTT)
726 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
727 for (i = 0; i < I915_NUM_RINGS; i++)
728 if (flush_rings & (1 << i)) {
729 ret = i915_gem_flush_ring(&dev_priv->ring[i],
741 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
742 struct intel_ring_buffer *to)
744 struct intel_ring_buffer *from = obj->ring;
748 if (from == NULL || to == from)
751 /* XXX gpu semaphores are implicated in various hard hangs on SNB */
752 if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
753 return i915_gem_object_wait_rendering(obj);
755 idx = intel_ring_sync_index(from, to);
757 seqno = obj->last_rendering_seqno;
758 if (seqno <= from->sync_seqno[idx])
761 if (seqno == from->outstanding_lazy_request) {
762 struct drm_i915_gem_request *request;
764 request = kzalloc(sizeof(*request), GFP_KERNEL);
768 ret = i915_add_request(from, NULL, request);
774 seqno = request->seqno;
777 from->sync_seqno[idx] = seqno;
778 return intel_ring_sync(to, from, seqno - 1);
782 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
784 u32 plane, flip_mask;
787 /* Check for any pending flips. As we only maintain a flip queue depth
788 * of 1, we can simply insert a WAIT for the next display flip prior
789 * to executing the batch and avoid stalling the CPU.
792 for (plane = 0; flips >> plane; plane++) {
793 if (((flips >> plane) & 1) == 0)
797 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
799 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
801 ret = intel_ring_begin(ring, 2);
805 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
806 intel_ring_emit(ring, MI_NOOP);
807 intel_ring_advance(ring);
815 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
816 struct list_head *objects)
818 struct drm_i915_gem_object *obj;
819 struct change_domains cd;
822 memset(&cd, 0, sizeof(cd));
823 list_for_each_entry(obj, objects, exec_list)
824 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
826 if (cd.invalidate_domains | cd.flush_domains) {
827 ret = i915_gem_execbuffer_flush(ring->dev,
828 cd.invalidate_domains,
836 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
841 list_for_each_entry(obj, objects, exec_list) {
842 ret = i915_gem_execbuffer_sync_rings(obj, ring);
851 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
853 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
857 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
862 for (i = 0; i < count; i++) {
863 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
864 int length; /* limited by fault_in_pages_readable() */
866 /* First check for malicious input causing overflow */
867 if (exec[i].relocation_count >
868 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
871 length = exec[i].relocation_count *
872 sizeof(struct drm_i915_gem_relocation_entry);
873 if (!access_ok(VERIFY_READ, ptr, length))
876 /* we may also need to update the presumed offsets */
877 if (!access_ok(VERIFY_WRITE, ptr, length))
880 if (fault_in_pages_readable(ptr, length))
888 i915_gem_execbuffer_move_to_active(struct list_head *objects,
889 struct intel_ring_buffer *ring,
892 struct drm_i915_gem_object *obj;
894 list_for_each_entry(obj, objects, exec_list) {
895 u32 old_read = obj->base.read_domains;
896 u32 old_write = obj->base.write_domain;
899 obj->base.read_domains = obj->base.pending_read_domains;
900 obj->base.write_domain = obj->base.pending_write_domain;
901 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
903 i915_gem_object_move_to_active(obj, ring, seqno);
904 if (obj->base.write_domain) {
906 obj->pending_gpu_write = true;
907 list_move_tail(&obj->gpu_write_list,
908 &ring->gpu_write_list);
909 intel_mark_busy(ring->dev, obj);
912 trace_i915_gem_object_change_domain(obj, old_read, old_write);
917 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
918 struct drm_file *file,
919 struct intel_ring_buffer *ring)
921 struct drm_i915_gem_request *request;
925 * Ensure that the commands in the batch buffer are
926 * finished before the interrupt fires.
928 * The sampler always gets flushed on i965 (sigh).
930 invalidate = I915_GEM_DOMAIN_COMMAND;
931 if (INTEL_INFO(dev)->gen >= 4)
932 invalidate |= I915_GEM_DOMAIN_SAMPLER;
933 if (ring->flush(ring, invalidate, 0)) {
934 i915_gem_next_request_seqno(ring);
938 /* Add a breadcrumb for the completion of the batch buffer */
939 request = kzalloc(sizeof(*request), GFP_KERNEL);
940 if (request == NULL || i915_add_request(ring, file, request)) {
941 i915_gem_next_request_seqno(ring);
947 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
948 struct drm_file *file,
949 struct drm_i915_gem_execbuffer2 *args,
950 struct drm_i915_gem_exec_object2 *exec)
952 drm_i915_private_t *dev_priv = dev->dev_private;
953 struct list_head objects;
954 struct eb_objects *eb;
955 struct drm_i915_gem_object *batch_obj;
956 struct drm_clip_rect *cliprects = NULL;
957 struct intel_ring_buffer *ring;
958 u32 exec_start, exec_len;
962 if (!i915_gem_check_execbuffer(args)) {
963 DRM_ERROR("execbuf with invalid offset/length\n");
967 ret = validate_exec_list(exec, args->buffer_count);
971 switch (args->flags & I915_EXEC_RING_MASK) {
972 case I915_EXEC_DEFAULT:
973 case I915_EXEC_RENDER:
974 ring = &dev_priv->ring[RCS];
978 DRM_ERROR("execbuf with invalid ring (BSD)\n");
981 ring = &dev_priv->ring[VCS];
985 DRM_ERROR("execbuf with invalid ring (BLT)\n");
988 ring = &dev_priv->ring[BCS];
991 DRM_ERROR("execbuf with unknown ring: %d\n",
992 (int)(args->flags & I915_EXEC_RING_MASK));
996 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
998 case I915_EXEC_CONSTANTS_REL_GENERAL:
999 case I915_EXEC_CONSTANTS_ABSOLUTE:
1000 case I915_EXEC_CONSTANTS_REL_SURFACE:
1001 if (ring == &dev_priv->ring[RCS] &&
1002 mode != dev_priv->relative_constants_mode) {
1003 if (INTEL_INFO(dev)->gen < 4)
1006 if (INTEL_INFO(dev)->gen > 5 &&
1007 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1010 ret = intel_ring_begin(ring, 4);
1014 intel_ring_emit(ring, MI_NOOP);
1015 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1016 intel_ring_emit(ring, INSTPM);
1017 intel_ring_emit(ring,
1018 I915_EXEC_CONSTANTS_MASK << 16 | mode);
1019 intel_ring_advance(ring);
1021 dev_priv->relative_constants_mode = mode;
1025 DRM_ERROR("execbuf with unknown constants: %d\n", mode);
1029 if (args->buffer_count < 1) {
1030 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1034 if (args->num_cliprects != 0) {
1035 if (ring != &dev_priv->ring[RCS]) {
1036 DRM_ERROR("clip rectangles are only valid with the render ring\n");
1040 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1042 if (cliprects == NULL) {
1047 if (copy_from_user(cliprects,
1048 (struct drm_clip_rect __user *)(uintptr_t)
1049 args->cliprects_ptr,
1050 sizeof(*cliprects)*args->num_cliprects)) {
1056 ret = i915_mutex_lock_interruptible(dev);
1060 if (dev_priv->mm.suspended) {
1061 mutex_unlock(&dev->struct_mutex);
1066 eb = eb_create(args->buffer_count);
1068 mutex_unlock(&dev->struct_mutex);
1073 /* Look up object handles */
1074 INIT_LIST_HEAD(&objects);
1075 for (i = 0; i < args->buffer_count; i++) {
1076 struct drm_i915_gem_object *obj;
1078 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1080 if (&obj->base == NULL) {
1081 DRM_ERROR("Invalid object handle %d at index %d\n",
1083 /* prevent error path from reading uninitialized data */
1088 if (!list_empty(&obj->exec_list)) {
1089 DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1090 obj, exec[i].handle, i);
1095 list_add_tail(&obj->exec_list, &objects);
1096 obj->exec_handle = exec[i].handle;
1097 obj->exec_entry = &exec[i];
1098 eb_add_object(eb, obj);
1101 /* take note of the batch buffer before we might reorder the lists */
1102 batch_obj = list_entry(objects.prev,
1103 struct drm_i915_gem_object,
1106 /* Move the objects en-masse into the GTT, evicting if necessary. */
1107 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1111 /* The objects are in their final locations, apply the relocations. */
1112 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1114 if (ret == -EFAULT) {
1115 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1118 args->buffer_count);
1119 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1125 /* Set the pending read domains for the batch buffer to COMMAND */
1126 if (batch_obj->base.pending_write_domain) {
1127 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1131 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1133 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1137 seqno = i915_gem_next_request_seqno(ring);
1138 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1139 if (seqno < ring->sync_seqno[i]) {
1140 /* The GPU can not handle its semaphore value wrapping,
1141 * so every billion or so execbuffers, we need to stall
1142 * the GPU in order to reset the counters.
1144 ret = i915_gpu_idle(dev);
1148 BUG_ON(ring->sync_seqno[i]);
1152 trace_i915_gem_ring_dispatch(ring, seqno);
1154 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1155 exec_len = args->batch_len;
1157 for (i = 0; i < args->num_cliprects; i++) {
1158 ret = i915_emit_box(dev, &cliprects[i],
1159 args->DR1, args->DR4);
1163 ret = ring->dispatch_execbuffer(ring,
1164 exec_start, exec_len);
1169 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1174 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1175 i915_gem_execbuffer_retire_commands(dev, file, ring);
1179 while (!list_empty(&objects)) {
1180 struct drm_i915_gem_object *obj;
1182 obj = list_first_entry(&objects,
1183 struct drm_i915_gem_object,
1185 list_del_init(&obj->exec_list);
1186 drm_gem_object_unreference(&obj->base);
1189 mutex_unlock(&dev->struct_mutex);
1197 * Legacy execbuffer just creates an exec2 list from the original exec object
1198 * list array and passes it to the real function.
1201 i915_gem_execbuffer(struct drm_device *dev, void *data,
1202 struct drm_file *file)
1204 struct drm_i915_gem_execbuffer *args = data;
1205 struct drm_i915_gem_execbuffer2 exec2;
1206 struct drm_i915_gem_exec_object *exec_list = NULL;
1207 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1210 if (args->buffer_count < 1) {
1211 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1215 /* Copy in the exec list from userland */
1216 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1217 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1218 if (exec_list == NULL || exec2_list == NULL) {
1219 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1220 args->buffer_count);
1221 drm_free_large(exec_list);
1222 drm_free_large(exec2_list);
1225 ret = copy_from_user(exec_list,
1226 (struct drm_i915_relocation_entry __user *)
1227 (uintptr_t) args->buffers_ptr,
1228 sizeof(*exec_list) * args->buffer_count);
1230 DRM_ERROR("copy %d exec entries failed %d\n",
1231 args->buffer_count, ret);
1232 drm_free_large(exec_list);
1233 drm_free_large(exec2_list);
1237 for (i = 0; i < args->buffer_count; i++) {
1238 exec2_list[i].handle = exec_list[i].handle;
1239 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1240 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1241 exec2_list[i].alignment = exec_list[i].alignment;
1242 exec2_list[i].offset = exec_list[i].offset;
1243 if (INTEL_INFO(dev)->gen < 4)
1244 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1246 exec2_list[i].flags = 0;
1249 exec2.buffers_ptr = args->buffers_ptr;
1250 exec2.buffer_count = args->buffer_count;
1251 exec2.batch_start_offset = args->batch_start_offset;
1252 exec2.batch_len = args->batch_len;
1253 exec2.DR1 = args->DR1;
1254 exec2.DR4 = args->DR4;
1255 exec2.num_cliprects = args->num_cliprects;
1256 exec2.cliprects_ptr = args->cliprects_ptr;
1257 exec2.flags = I915_EXEC_RENDER;
1259 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1261 /* Copy the new buffer offsets back to the user's exec list. */
1262 for (i = 0; i < args->buffer_count; i++)
1263 exec_list[i].offset = exec2_list[i].offset;
1264 /* ... and back out to userspace */
1265 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1266 (uintptr_t) args->buffers_ptr,
1268 sizeof(*exec_list) * args->buffer_count);
1271 DRM_ERROR("failed to copy %d exec entries "
1272 "back to user (%d)\n",
1273 args->buffer_count, ret);
1277 drm_free_large(exec_list);
1278 drm_free_large(exec2_list);
1283 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1284 struct drm_file *file)
1286 struct drm_i915_gem_execbuffer2 *args = data;
1287 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1290 if (args->buffer_count < 1) {
1291 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1295 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1296 GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1297 if (exec2_list == NULL)
1298 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1299 args->buffer_count);
1300 if (exec2_list == NULL) {
1301 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1302 args->buffer_count);
1305 ret = copy_from_user(exec2_list,
1306 (struct drm_i915_relocation_entry __user *)
1307 (uintptr_t) args->buffers_ptr,
1308 sizeof(*exec2_list) * args->buffer_count);
1310 DRM_ERROR("copy %d exec entries failed %d\n",
1311 args->buffer_count, ret);
1312 drm_free_large(exec2_list);
1316 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1318 /* Copy the new buffer offsets back to the user's exec list. */
1319 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1320 (uintptr_t) args->buffers_ptr,
1322 sizeof(*exec2_list) * args->buffer_count);
1325 DRM_ERROR("failed to copy %d exec entries "
1326 "back to user (%d)\n",
1327 args->buffer_count, ret);
1331 drm_free_large(exec2_list);