drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/dma_remapping.h>
  35 #include <linux/uaccess.h>
  36
  37 #define  __EXEC_OBJECT_HAS_PIN          (1<<31)
  38 #define  __EXEC_OBJECT_HAS_FENCE        (1<<30)
  39 #define  __EXEC_OBJECT_NEEDS_MAP        (1<<29)
  40 #define  __EXEC_OBJECT_NEEDS_BIAS       (1<<28)
  41 #define  __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
  42
  43 #define BATCH_OFFSET_BIAS (256*1024)
  44
  45 struct i915_execbuffer_params {
  46         struct drm_device               *dev;
  47         struct drm_file                 *file;
  48         u32                              dispatch_flags;
  49         u32                              args_batch_start_offset;
  50         u32                              batch_obj_vm_offset;
  51         struct intel_engine_cs          *engine;
  52         struct drm_i915_gem_object      *batch_obj;
  53         struct i915_gem_context         *ctx;
  54         struct drm_i915_gem_request     *request;
  55 };
  56
  57 struct eb_vmas {
  58         struct list_head vmas;
  59         int and;
  60         union {
  61                 struct i915_vma *lut[0];
  62                 struct hlist_head buckets[0];
  63         };
  64 };
  65
  66 static struct eb_vmas *
  67 eb_create(struct drm_i915_gem_execbuffer2 *args)
  68 {
  69         struct eb_vmas *eb = NULL;
  70
  71         if (args->flags & I915_EXEC_HANDLE_LUT) {
  72                 unsigned size = args->buffer_count;
  73                 size *= sizeof(struct i915_vma *);
  74                 size += sizeof(struct eb_vmas);
  75                 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  76         }
  77
  78         if (eb == NULL) {
  79                 unsigned size = args->buffer_count;
  80                 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  81                 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  82                 while (count > 2*size)
  83                         count >>= 1;
  84                 eb = kzalloc(count*sizeof(struct hlist_head) +
  85                              sizeof(struct eb_vmas),
  86                              GFP_TEMPORARY);
  87                 if (eb == NULL)
  88                         return eb;
  89
  90                 eb->and = count - 1;
  91         } else
  92                 eb->and = -args->buffer_count;
  93
  94         INIT_LIST_HEAD(&eb->vmas);
  95         return eb;
  96 }
  97
  98 static void
  99 eb_reset(struct eb_vmas *eb)
 100 {
 101         if (eb->and >= 0)
 102                 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 103 }
 104
 105 static int
 106 eb_lookup_vmas(struct eb_vmas *eb,
 107                struct drm_i915_gem_exec_object2 *exec,
 108                const struct drm_i915_gem_execbuffer2 *args,
 109                struct i915_address_space *vm,
 110                struct drm_file *file)
 111 {
 112         struct drm_i915_gem_object *obj;
 113         struct list_head objects;
 114         int i, ret;
 115
 116         INIT_LIST_HEAD(&objects);
 117         spin_lock(&file->table_lock);
 118         /* Grab a reference to the object and release the lock so we can lookup
 119          * or create the VMA without using GFP_ATOMIC */
 120         for (i = 0; i < args->buffer_count; i++) {
 121                 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
 122                 if (obj == NULL) {
 123                         spin_unlock(&file->table_lock);
 124                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 125                                    exec[i].handle, i);
 126                         ret = -ENOENT;
 127                         goto err;
 128                 }
 129
 130                 if (!list_empty(&obj->obj_exec_link)) {
 131                         spin_unlock(&file->table_lock);
 132                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
 133                                    obj, exec[i].handle, i);
 134                         ret = -EINVAL;
 135                         goto err;
 136                 }
 137
 138                 i915_gem_object_get(obj);
 139                 list_add_tail(&obj->obj_exec_link, &objects);
 140         }
 141         spin_unlock(&file->table_lock);
 142
 143         i = 0;
 144         while (!list_empty(&objects)) {
 145                 struct i915_vma *vma;
 146
 147                 obj = list_first_entry(&objects,
 148                                        struct drm_i915_gem_object,
 149                                        obj_exec_link);
 150
 151                 /*
 152                  * NOTE: We can leak any vmas created here when something fails
 153                  * later on. But that's no issue since vma_unbind can deal with
 154                  * vmas which are not actually bound. And since only
 155                  * lookup_or_create exists as an interface to get at the vma
 156                  * from the (obj, vm) we don't run the risk of creating
 157                  * duplicated vmas for the same vm.
 158                  */
 159                 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
 160                 if (IS_ERR(vma)) {
 161                         DRM_DEBUG("Failed to lookup VMA\n");
 162                         ret = PTR_ERR(vma);
 163                         goto err;
 164                 }
 165
 166                 /* Transfer ownership from the objects list to the vmas list. */
 167                 list_add_tail(&vma->exec_list, &eb->vmas);
 168                 list_del_init(&obj->obj_exec_link);
 169
 170                 vma->exec_entry = &exec[i];
 171                 if (eb->and < 0) {
 172                         eb->lut[i] = vma;
 173                 } else {
 174                         uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
 175                         vma->exec_handle = handle;
 176                         hlist_add_head(&vma->exec_node,
 177                                        &eb->buckets[handle & eb->and]);
 178                 }
 179                 ++i;
 180         }
 181
 182         return 0;
 183
 184
 185 err:
 186         while (!list_empty(&objects)) {
 187                 obj = list_first_entry(&objects,
 188                                        struct drm_i915_gem_object,
 189                                        obj_exec_link);
 190                 list_del_init(&obj->obj_exec_link);
 191                 i915_gem_object_put(obj);
 192         }
 193         /*
 194          * Objects already transfered to the vmas list will be unreferenced by
 195          * eb_destroy.
 196          */
 197
 198         return ret;
 199 }
 200
 201 static inline struct i915_vma *
 202 eb_get_batch_vma(struct eb_vmas *eb)
 203 {
 204         /* The batch is always the LAST item in the VMA list */
 205         struct i915_vma *vma = list_last_entry(&eb->vmas, typeof(*vma), exec_list);
 206
 207         return vma;
 208 }
 209
 210 static struct drm_i915_gem_object *
 211 eb_get_batch(struct eb_vmas *eb)
 212 {
 213         struct i915_vma *vma = eb_get_batch_vma(eb);
 214
 215         /*
 216          * SNA is doing fancy tricks with compressing batch buffers, which leads
 217          * to negative relocation deltas. Usually that works out ok since the
 218          * relocate address is still positive, except when the batch is placed
 219          * very low in the GTT. Ensure this doesn't happen.
 220          *
 221          * Note that actual hangs have only been observed on gen7, but for
 222          * paranoia do it everywhere.
 223          */
 224         if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
 225                 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 226
 227         return vma->obj;
 228 }
 229
 230 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
 231 {
 232         if (eb->and < 0) {
 233                 if (handle >= -eb->and)
 234                         return NULL;
 235                 return eb->lut[handle];
 236         } else {
 237                 struct hlist_head *head;
 238                 struct i915_vma *vma;
 239
 240                 head = &eb->buckets[handle & eb->and];
 241                 hlist_for_each_entry(vma, head, exec_node) {
 242                         if (vma->exec_handle == handle)
 243                                 return vma;
 244                 }
 245                 return NULL;
 246         }
 247 }
 248
 249 static void
 250 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
 251 {
 252         struct drm_i915_gem_exec_object2 *entry;
 253         struct drm_i915_gem_object *obj = vma->obj;
 254
 255         if (!drm_mm_node_allocated(&vma->node))
 256                 return;
 257
 258         entry = vma->exec_entry;
 259
 260         if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
 261                 i915_gem_object_unpin_fence(obj);
 262
 263         if (entry->flags & __EXEC_OBJECT_HAS_PIN)
 264                 vma->pin_count--;
 265
 266         entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
 267 }
 268
 269 static void eb_destroy(struct eb_vmas *eb)
 270 {
 271         while (!list_empty(&eb->vmas)) {
 272                 struct i915_vma *vma;
 273
 274                 vma = list_first_entry(&eb->vmas,
 275                                        struct i915_vma,
 276                                        exec_list);
 277                 list_del_init(&vma->exec_list);
 278                 i915_gem_execbuffer_unreserve_vma(vma);
 279                 i915_gem_object_put(vma->obj);
 280         }
 281         kfree(eb);
 282 }
 283
 284 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 285 {
 286         return (HAS_LLC(obj->base.dev) ||
 287                 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 288                 obj->cache_level != I915_CACHE_NONE);
 289 }
 290
 291 /* Used to convert any address to canonical form.
 292  * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
 293  * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
 294  * addresses to be in a canonical form:
 295  * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
 296  * canonical form [63:48] == [47]."
 297  */
 298 #define GEN8_HIGH_ADDRESS_BIT 47
 299 static inline uint64_t gen8_canonical_addr(uint64_t address)
 300 {
 301         return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
 302 }
 303
 304 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
 305 {
 306         return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
 307 }
 308
 309 static inline uint64_t
 310 relocation_target(struct drm_i915_gem_relocation_entry *reloc,
 311                   uint64_t target_offset)
 312 {
 313         return gen8_canonical_addr((int)reloc->delta + target_offset);
 314 }
 315
 316 static int
 317 relocate_entry_cpu(struct drm_i915_gem_object *obj,
 318                    struct drm_i915_gem_relocation_entry *reloc,
 319                    uint64_t target_offset)
 320 {
 321         struct drm_device *dev = obj->base.dev;
 322         uint32_t page_offset = offset_in_page(reloc->offset);
 323         uint64_t delta = relocation_target(reloc, target_offset);
 324         char *vaddr;
 325         int ret;
 326
 327         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 328         if (ret)
 329                 return ret;
 330
 331         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 332                                 reloc->offset >> PAGE_SHIFT));
 333         *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
 334
 335         if (INTEL_INFO(dev)->gen >= 8) {
 336                 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 337
 338                 if (page_offset == 0) {
 339                         kunmap_atomic(vaddr);
 340                         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 341                             (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
 342                 }
 343
 344                 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
 345         }
 346
 347         kunmap_atomic(vaddr);
 348
 349         return 0;
 350 }
 351
 352 static int
 353 relocate_entry_gtt(struct drm_i915_gem_object *obj,
 354                    struct drm_i915_gem_relocation_entry *reloc,
 355                    uint64_t target_offset)
 356 {
 357         struct drm_device *dev = obj->base.dev;
 358         struct drm_i915_private *dev_priv = to_i915(dev);
 359         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 360         uint64_t delta = relocation_target(reloc, target_offset);
 361         uint64_t offset;
 362         void __iomem *reloc_page;
 363         int ret;
 364
 365         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 366         if (ret)
 367                 return ret;
 368
 369         ret = i915_gem_object_put_fence(obj);
 370         if (ret)
 371                 return ret;
 372
 373         /* Map the page containing the relocation we're going to perform.  */
 374         offset = i915_gem_obj_ggtt_offset(obj);
 375         offset += reloc->offset;
 376         reloc_page = io_mapping_map_atomic_wc(ggtt->mappable,
 377                                               offset & PAGE_MASK);
 378         iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
 379
 380         if (INTEL_INFO(dev)->gen >= 8) {
 381                 offset += sizeof(uint32_t);
 382
 383                 if (offset_in_page(offset) == 0) {
 384                         io_mapping_unmap_atomic(reloc_page);
 385                         reloc_page =
 386                                 io_mapping_map_atomic_wc(ggtt->mappable,
 387                                                          offset);
 388                 }
 389
 390                 iowrite32(upper_32_bits(delta),
 391                           reloc_page + offset_in_page(offset));
 392         }
 393
 394         io_mapping_unmap_atomic(reloc_page);
 395
 396         return 0;
 397 }
 398
 399 static void
 400 clflush_write32(void *addr, uint32_t value)
 401 {
 402         /* This is not a fast path, so KISS. */
 403         drm_clflush_virt_range(addr, sizeof(uint32_t));
 404         *(uint32_t *)addr = value;
 405         drm_clflush_virt_range(addr, sizeof(uint32_t));
 406 }
 407
 408 static int
 409 relocate_entry_clflush(struct drm_i915_gem_object *obj,
 410                        struct drm_i915_gem_relocation_entry *reloc,
 411                        uint64_t target_offset)
 412 {
 413         struct drm_device *dev = obj->base.dev;
 414         uint32_t page_offset = offset_in_page(reloc->offset);
 415         uint64_t delta = relocation_target(reloc, target_offset);
 416         char *vaddr;
 417         int ret;
 418
 419         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 420         if (ret)
 421                 return ret;
 422
 423         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 424                                 reloc->offset >> PAGE_SHIFT));
 425         clflush_write32(vaddr + page_offset, lower_32_bits(delta));
 426
 427         if (INTEL_INFO(dev)->gen >= 8) {
 428                 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 429
 430                 if (page_offset == 0) {
 431                         kunmap_atomic(vaddr);
 432                         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 433                             (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
 434                 }
 435
 436                 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
 437         }
 438
 439         kunmap_atomic(vaddr);
 440
 441         return 0;
 442 }
 443
 444 static bool object_is_idle(struct drm_i915_gem_object *obj)
 445 {
 446         unsigned long active = obj->active;
 447         int idx;
 448
 449         for_each_active(active, idx) {
 450                 if (!i915_gem_active_is_idle(&obj->last_read[idx],
 451                                              &obj->base.dev->struct_mutex))
 452                         return false;
 453         }
 454
 455         return true;
 456 }
 457
 458 static int
 459 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 460                                    struct eb_vmas *eb,
 461                                    struct drm_i915_gem_relocation_entry *reloc)
 462 {
 463         struct drm_device *dev = obj->base.dev;
 464         struct drm_gem_object *target_obj;
 465         struct drm_i915_gem_object *target_i915_obj;
 466         struct i915_vma *target_vma;
 467         uint64_t target_offset;
 468         int ret;
 469
 470         /* we've already hold a reference to all valid objects */
 471         target_vma = eb_get_vma(eb, reloc->target_handle);
 472         if (unlikely(target_vma == NULL))
 473                 return -ENOENT;
 474         target_i915_obj = target_vma->obj;
 475         target_obj = &target_vma->obj->base;
 476
 477         target_offset = gen8_canonical_addr(target_vma->node.start);
 478
 479         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 480          * pipe_control writes because the gpu doesn't properly redirect them
 481          * through the ppgtt for non_secure batchbuffers. */
 482         if (unlikely(IS_GEN6(dev) &&
 483             reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
 484                 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
 485                                     PIN_GLOBAL);
 486                 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
 487                         return ret;
 488         }
 489
 490         /* Validate that the target is in a valid r/w GPU domain */
 491         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 492                 DRM_DEBUG("reloc with multiple write domains: "
 493                           "obj %p target %d offset %d "
 494                           "read %08x write %08x",
 495                           obj, reloc->target_handle,
 496                           (int) reloc->offset,
 497                           reloc->read_domains,
 498                           reloc->write_domain);
 499                 return -EINVAL;
 500         }
 501         if (unlikely((reloc->write_domain | reloc->read_domains)
 502                      & ~I915_GEM_GPU_DOMAINS)) {
 503                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 504                           "obj %p target %d offset %d "
 505                           "read %08x write %08x",
 506                           obj, reloc->target_handle,
 507                           (int) reloc->offset,
 508                           reloc->read_domains,
 509                           reloc->write_domain);
 510                 return -EINVAL;
 511         }
 512
 513         target_obj->pending_read_domains |= reloc->read_domains;
 514         target_obj->pending_write_domain |= reloc->write_domain;
 515
 516         /* If the relocation already has the right value in it, no
 517          * more work needs to be done.
 518          */
 519         if (target_offset == reloc->presumed_offset)
 520                 return 0;
 521
 522         /* Check that the relocation address is valid... */
 523         if (unlikely(reloc->offset >
 524                 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
 525                 DRM_DEBUG("Relocation beyond object bounds: "
 526                           "obj %p target %d offset %d size %d.\n",
 527                           obj, reloc->target_handle,
 528                           (int) reloc->offset,
 529                           (int) obj->base.size);
 530                 return -EINVAL;
 531         }
 532         if (unlikely(reloc->offset & 3)) {
 533                 DRM_DEBUG("Relocation not 4-byte aligned: "
 534                           "obj %p target %d offset %d.\n",
 535                           obj, reloc->target_handle,
 536                           (int) reloc->offset);
 537                 return -EINVAL;
 538         }
 539
 540         /* We can't wait for rendering with pagefaults disabled */
 541         if (pagefault_disabled() && !object_is_idle(obj))
 542                 return -EFAULT;
 543
 544         if (use_cpu_reloc(obj))
 545                 ret = relocate_entry_cpu(obj, reloc, target_offset);
 546         else if (obj->map_and_fenceable)
 547                 ret = relocate_entry_gtt(obj, reloc, target_offset);
 548         else if (static_cpu_has(X86_FEATURE_CLFLUSH))
 549                 ret = relocate_entry_clflush(obj, reloc, target_offset);
 550         else {
 551                 WARN_ONCE(1, "Impossible case in relocation handling\n");
 552                 ret = -ENODEV;
 553         }
 554
 555         if (ret)
 556                 return ret;
 557
 558         /* and update the user's relocation entry */
 559         reloc->presumed_offset = target_offset;
 560
 561         return 0;
 562 }
 563
 564 static int
 565 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
 566                                  struct eb_vmas *eb)
 567 {
 568 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
 569         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
 570         struct drm_i915_gem_relocation_entry __user *user_relocs;
 571         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 572         int remain, ret;
 573
 574         user_relocs = u64_to_user_ptr(entry->relocs_ptr);
 575
 576         remain = entry->relocation_count;
 577         while (remain) {
 578                 struct drm_i915_gem_relocation_entry *r = stack_reloc;
 579                 int count = remain;
 580                 if (count > ARRAY_SIZE(stack_reloc))
 581                         count = ARRAY_SIZE(stack_reloc);
 582                 remain -= count;
 583
 584                 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
 585                         return -EFAULT;
 586
 587                 do {
 588                         u64 offset = r->presumed_offset;
 589
 590                         ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
 591                         if (ret)
 592                                 return ret;
 593
 594                         if (r->presumed_offset != offset &&
 595                             __put_user(r->presumed_offset, &user_relocs->presumed_offset)) {
 596                                 return -EFAULT;
 597                         }
 598
 599                         user_relocs++;
 600                         r++;
 601                 } while (--count);
 602         }
 603
 604         return 0;
 605 #undef N_RELOC
 606 }
 607
 608 static int
 609 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
 610                                       struct eb_vmas *eb,
 611                                       struct drm_i915_gem_relocation_entry *relocs)
 612 {
 613         const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 614         int i, ret;
 615
 616         for (i = 0; i < entry->relocation_count; i++) {
 617                 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
 618                 if (ret)
 619                         return ret;
 620         }
 621
 622         return 0;
 623 }
 624
 625 static int
 626 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
 627 {
 628         struct i915_vma *vma;
 629         int ret = 0;
 630
 631         /* This is the fast path and we cannot handle a pagefault whilst
 632          * holding the struct mutex lest the user pass in the relocations
 633          * contained within a mmaped bo. For in such a case we, the page
 634          * fault handler would call i915_gem_fault() and we would try to
 635          * acquire the struct mutex again. Obviously this is bad and so
 636          * lockdep complains vehemently.
 637          */
 638         pagefault_disable();
 639         list_for_each_entry(vma, &eb->vmas, exec_list) {
 640                 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
 641                 if (ret)
 642                         break;
 643         }
 644         pagefault_enable();
 645
 646         return ret;
 647 }
 648
 649 static bool only_mappable_for_reloc(unsigned int flags)
 650 {
 651         return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
 652                 __EXEC_OBJECT_NEEDS_MAP;
 653 }
 654
 655 static int
 656 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 657                                 struct intel_engine_cs *engine,
 658                                 bool *need_reloc)
 659 {
 660         struct drm_i915_gem_object *obj = vma->obj;
 661         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 662         uint64_t flags;
 663         int ret;
 664
 665         flags = PIN_USER;
 666         if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
 667                 flags |= PIN_GLOBAL;
 668
 669         if (!drm_mm_node_allocated(&vma->node)) {
 670                 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
 671                  * limit address to the first 4GBs for unflagged objects.
 672                  */
 673                 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
 674                         flags |= PIN_ZONE_4G;
 675                 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
 676                         flags |= PIN_GLOBAL | PIN_MAPPABLE;
 677                 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
 678                         flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
 679                 if (entry->flags & EXEC_OBJECT_PINNED)
 680                         flags |= entry->offset | PIN_OFFSET_FIXED;
 681                 if ((flags & PIN_MAPPABLE) == 0)
 682                         flags |= PIN_HIGH;
 683         }
 684
 685         ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
 686         if ((ret == -ENOSPC  || ret == -E2BIG) &&
 687             only_mappable_for_reloc(entry->flags))
 688                 ret = i915_gem_object_pin(obj, vma->vm,
 689                                           entry->alignment,
 690                                           flags & ~PIN_MAPPABLE);
 691         if (ret)
 692                 return ret;
 693
 694         entry->flags |= __EXEC_OBJECT_HAS_PIN;
 695
 696         if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 697                 ret = i915_gem_object_get_fence(obj);
 698                 if (ret)
 699                         return ret;
 700
 701                 if (i915_gem_object_pin_fence(obj))
 702                         entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 703         }
 704
 705         if (entry->offset != vma->node.start) {
 706                 entry->offset = vma->node.start;
 707                 *need_reloc = true;
 708         }
 709
 710         if (entry->flags & EXEC_OBJECT_WRITE) {
 711                 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
 712                 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
 713         }
 714
 715         return 0;
 716 }
 717
 718 static bool
 719 need_reloc_mappable(struct i915_vma *vma)
 720 {
 721         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 722
 723         if (entry->relocation_count == 0)
 724                 return false;
 725
 726         if (!vma->is_ggtt)
 727                 return false;
 728
 729         /* See also use_cpu_reloc() */
 730         if (HAS_LLC(vma->obj->base.dev))
 731                 return false;
 732
 733         if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
 734                 return false;
 735
 736         return true;
 737 }
 738
 739 static bool
 740 eb_vma_misplaced(struct i915_vma *vma)
 741 {
 742         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 743         struct drm_i915_gem_object *obj = vma->obj;
 744
 745         WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt);
 746
 747         if (entry->alignment &&
 748             vma->node.start & (entry->alignment - 1))
 749                 return true;
 750
 751         if (entry->flags & EXEC_OBJECT_PINNED &&
 752             vma->node.start != entry->offset)
 753                 return true;
 754
 755         if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
 756             vma->node.start < BATCH_OFFSET_BIAS)
 757                 return true;
 758
 759         /* avoid costly ping-pong once a batch bo ended up non-mappable */
 760         if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
 761                 return !only_mappable_for_reloc(entry->flags);
 762
 763         if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
 764             (vma->node.start + vma->node.size - 1) >> 32)
 765                 return true;
 766
 767         return false;
 768 }
 769
 770 static int
 771 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
 772                             struct list_head *vmas,
 773                             struct i915_gem_context *ctx,
 774                             bool *need_relocs)
 775 {
 776         struct drm_i915_gem_object *obj;
 777         struct i915_vma *vma;
 778         struct i915_address_space *vm;
 779         struct list_head ordered_vmas;
 780         struct list_head pinned_vmas;
 781         bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
 782         int retry;
 783
 784         i915_gem_retire_requests_ring(engine);
 785
 786         vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
 787
 788         INIT_LIST_HEAD(&ordered_vmas);
 789         INIT_LIST_HEAD(&pinned_vmas);
 790         while (!list_empty(vmas)) {
 791                 struct drm_i915_gem_exec_object2 *entry;
 792                 bool need_fence, need_mappable;
 793
 794                 vma = list_first_entry(vmas, struct i915_vma, exec_list);
 795                 obj = vma->obj;
 796                 entry = vma->exec_entry;
 797
 798                 if (ctx->flags & CONTEXT_NO_ZEROMAP)
 799                         entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 800
 801                 if (!has_fenced_gpu_access)
 802                         entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 803                 need_fence =
 804                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 805                         obj->tiling_mode != I915_TILING_NONE;
 806                 need_mappable = need_fence || need_reloc_mappable(vma);
 807
 808                 if (entry->flags & EXEC_OBJECT_PINNED)
 809                         list_move_tail(&vma->exec_list, &pinned_vmas);
 810                 else if (need_mappable) {
 811                         entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
 812                         list_move(&vma->exec_list, &ordered_vmas);
 813                 } else
 814                         list_move_tail(&vma->exec_list, &ordered_vmas);
 815
 816                 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
 817                 obj->base.pending_write_domain = 0;
 818         }
 819         list_splice(&ordered_vmas, vmas);
 820         list_splice(&pinned_vmas, vmas);
 821
 822         /* Attempt to pin all of the buffers into the GTT.
 823          * This is done in 3 phases:
 824          *
 825          * 1a. Unbind all objects that do not match the GTT constraints for
 826          *     the execbuffer (fenceable, mappable, alignment etc).
 827          * 1b. Increment pin count for already bound objects.
 828          * 2.  Bind new objects.
 829          * 3.  Decrement pin count.
 830          *
 831          * This avoid unnecessary unbinding of later objects in order to make
 832          * room for the earlier objects *unless* we need to defragment.
 833          */
 834         retry = 0;
 835         do {
 836                 int ret = 0;
 837
 838                 /* Unbind any ill-fitting objects or pin. */
 839                 list_for_each_entry(vma, vmas, exec_list) {
 840                         if (!drm_mm_node_allocated(&vma->node))
 841                                 continue;
 842
 843                         if (eb_vma_misplaced(vma))
 844                                 ret = i915_vma_unbind(vma);
 845                         else
 846                                 ret = i915_gem_execbuffer_reserve_vma(vma,
 847                                                                       engine,
 848                                                                       need_relocs);
 849                         if (ret)
 850                                 goto err;
 851                 }
 852
 853                 /* Bind fresh objects */
 854                 list_for_each_entry(vma, vmas, exec_list) {
 855                         if (drm_mm_node_allocated(&vma->node))
 856                                 continue;
 857
 858                         ret = i915_gem_execbuffer_reserve_vma(vma, engine,
 859                                                               need_relocs);
 860                         if (ret)
 861                                 goto err;
 862                 }
 863
 864 err:
 865                 if (ret != -ENOSPC || retry++)
 866                         return ret;
 867
 868                 /* Decrement pin count for bound objects */
 869                 list_for_each_entry(vma, vmas, exec_list)
 870                         i915_gem_execbuffer_unreserve_vma(vma);
 871
 872                 ret = i915_gem_evict_vm(vm, true);
 873                 if (ret)
 874                         return ret;
 875         } while (1);
 876 }
 877
 878 static int
 879 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 880                                   struct drm_i915_gem_execbuffer2 *args,
 881                                   struct drm_file *file,
 882                                   struct intel_engine_cs *engine,
 883                                   struct eb_vmas *eb,
 884                                   struct drm_i915_gem_exec_object2 *exec,
 885                                   struct i915_gem_context *ctx)
 886 {
 887         struct drm_i915_gem_relocation_entry *reloc;
 888         struct i915_address_space *vm;
 889         struct i915_vma *vma;
 890         bool need_relocs;
 891         int *reloc_offset;
 892         int i, total, ret;
 893         unsigned count = args->buffer_count;
 894
 895         vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
 896
 897         /* We may process another execbuffer during the unlock... */
 898         while (!list_empty(&eb->vmas)) {
 899                 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
 900                 list_del_init(&vma->exec_list);
 901                 i915_gem_execbuffer_unreserve_vma(vma);
 902                 i915_gem_object_put(vma->obj);
 903         }
 904
 905         mutex_unlock(&dev->struct_mutex);
 906
 907         total = 0;
 908         for (i = 0; i < count; i++)
 909                 total += exec[i].relocation_count;
 910
 911         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
 912         reloc = drm_malloc_ab(total, sizeof(*reloc));
 913         if (reloc == NULL || reloc_offset == NULL) {
 914                 drm_free_large(reloc);
 915                 drm_free_large(reloc_offset);
 916                 mutex_lock(&dev->struct_mutex);
 917                 return -ENOMEM;
 918         }
 919
 920         total = 0;
 921         for (i = 0; i < count; i++) {
 922                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 923                 u64 invalid_offset = (u64)-1;
 924                 int j;
 925
 926                 user_relocs = u64_to_user_ptr(exec[i].relocs_ptr);
 927
 928                 if (copy_from_user(reloc+total, user_relocs,
 929                                    exec[i].relocation_count * sizeof(*reloc))) {
 930                         ret = -EFAULT;
 931                         mutex_lock(&dev->struct_mutex);
 932                         goto err;
 933                 }
 934
 935                 /* As we do not update the known relocation offsets after
 936                  * relocating (due to the complexities in lock handling),
 937                  * we need to mark them as invalid now so that we force the
 938                  * relocation processing next time. Just in case the target
 939                  * object is evicted and then rebound into its old
 940                  * presumed_offset before the next execbuffer - if that
 941                  * happened we would make the mistake of assuming that the
 942                  * relocations were valid.
 943                  */
 944                 for (j = 0; j < exec[i].relocation_count; j++) {
 945                         if (__copy_to_user(&user_relocs[j].presumed_offset,
 946                                            &invalid_offset,
 947                                            sizeof(invalid_offset))) {
 948                                 ret = -EFAULT;
 949                                 mutex_lock(&dev->struct_mutex);
 950                                 goto err;
 951                         }
 952                 }
 953
 954                 reloc_offset[i] = total;
 955                 total += exec[i].relocation_count;
 956         }
 957
 958         ret = i915_mutex_lock_interruptible(dev);
 959         if (ret) {
 960                 mutex_lock(&dev->struct_mutex);
 961                 goto err;
 962         }
 963
 964         /* reacquire the objects */
 965         eb_reset(eb);
 966         ret = eb_lookup_vmas(eb, exec, args, vm, file);
 967         if (ret)
 968                 goto err;
 969
 970         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
 971         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
 972                                           &need_relocs);
 973         if (ret)
 974                 goto err;
 975
 976         list_for_each_entry(vma, &eb->vmas, exec_list) {
 977                 int offset = vma->exec_entry - exec;
 978                 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
 979                                                             reloc + reloc_offset[offset]);
 980                 if (ret)
 981                         goto err;
 982         }
 983
 984         /* Leave the user relocations as are, this is the painfully slow path,
 985          * and we want to avoid the complication of dropping the lock whilst
 986          * having buffers reserved in the aperture and so causing spurious
 987          * ENOSPC for random operations.
 988          */
 989
 990 err:
 991         drm_free_large(reloc);
 992         drm_free_large(reloc_offset);
 993         return ret;
 994 }
 995
 996 static int
 997 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
 998                                 struct list_head *vmas)
 999 {
1000         const unsigned other_rings = ~intel_engine_flag(req->engine);
1001         struct i915_vma *vma;
1002         uint32_t flush_domains = 0;
1003         bool flush_chipset = false;
1004         int ret;
1005
1006         list_for_each_entry(vma, vmas, exec_list) {
1007                 struct drm_i915_gem_object *obj = vma->obj;
1008
1009                 if (obj->active & other_rings) {
1010                         ret = i915_gem_object_sync(obj, req);
1011                         if (ret)
1012                                 return ret;
1013                 }
1014
1015                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
1016                         flush_chipset |= i915_gem_clflush_object(obj, false);
1017
1018                 flush_domains |= obj->base.write_domain;
1019         }
1020
1021         if (flush_chipset)
1022                 i915_gem_chipset_flush(req->engine->i915);
1023
1024         if (flush_domains & I915_GEM_DOMAIN_GTT)
1025                 wmb();
1026
1027         /* Unconditionally invalidate GPU caches and TLBs. */
1028         return req->engine->emit_flush(req, EMIT_INVALIDATE);
1029 }
1030
1031 static bool
1032 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1033 {
1034         if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
1035                 return false;
1036
1037         /* Kernel clipping was a DRI1 misfeature */
1038         if (exec->num_cliprects || exec->cliprects_ptr)
1039                 return false;
1040
1041         if (exec->DR4 == 0xffffffff) {
1042                 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1043                 exec->DR4 = 0;
1044         }
1045         if (exec->DR1 || exec->DR4)
1046                 return false;
1047
1048         if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1049                 return false;
1050
1051         return true;
1052 }
1053
1054 static int
1055 validate_exec_list(struct drm_device *dev,
1056                    struct drm_i915_gem_exec_object2 *exec,
1057                    int count)
1058 {
1059         unsigned relocs_total = 0;
1060         unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1061         unsigned invalid_flags;
1062         int i;
1063
1064         /* INTERNAL flags must not overlap with external ones */
1065         BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1066
1067         invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1068         if (USES_FULL_PPGTT(dev))
1069                 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1070
1071         for (i = 0; i < count; i++) {
1072                 char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr);
1073                 int length; /* limited by fault_in_pages_readable() */
1074
1075                 if (exec[i].flags & invalid_flags)
1076                         return -EINVAL;
1077
1078                 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1079                  * any non-page-aligned or non-canonical addresses.
1080                  */
1081                 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1082                         if (exec[i].offset !=
1083                             gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1084                                 return -EINVAL;
1085
1086                         /* From drm_mm perspective address space is continuous,
1087                          * so from this point we're always using non-canonical
1088                          * form internally.
1089                          */
1090                         exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1091                 }
1092
1093                 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1094                         return -EINVAL;
1095
1096                 /* First check for malicious input causing overflow in
1097                  * the worst case where we need to allocate the entire
1098                  * relocation tree as a single array.
1099                  */
1100                 if (exec[i].relocation_count > relocs_max - relocs_total)
1101                         return -EINVAL;
1102                 relocs_total += exec[i].relocation_count;
1103
1104                 length = exec[i].relocation_count *
1105                         sizeof(struct drm_i915_gem_relocation_entry);
1106                 /*
1107                  * We must check that the entire relocation array is safe
1108                  * to read, but since we may need to update the presumed
1109                  * offsets during execution, check for full write access.
1110                  */
1111                 if (!access_ok(VERIFY_WRITE, ptr, length))
1112                         return -EFAULT;
1113
1114                 if (likely(!i915.prefault_disable)) {
1115                         if (fault_in_multipages_readable(ptr, length))
1116                                 return -EFAULT;
1117                 }
1118         }
1119
1120         return 0;
1121 }
1122
1123 static struct i915_gem_context *
1124 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1125                           struct intel_engine_cs *engine, const u32 ctx_id)
1126 {
1127         struct i915_gem_context *ctx = NULL;
1128         struct i915_ctx_hang_stats *hs;
1129
1130         if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1131                 return ERR_PTR(-EINVAL);
1132
1133         ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1134         if (IS_ERR(ctx))
1135                 return ctx;
1136
1137         hs = &ctx->hang_stats;
1138         if (hs->banned) {
1139                 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1140                 return ERR_PTR(-EIO);
1141         }
1142
1143         return ctx;
1144 }
1145
1146 static void
1147 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1148                                    struct drm_i915_gem_request *req)
1149 {
1150         struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1151         struct i915_vma *vma;
1152
1153         list_for_each_entry(vma, vmas, exec_list) {
1154                 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1155                 struct drm_i915_gem_object *obj = vma->obj;
1156                 u32 old_read = obj->base.read_domains;
1157                 u32 old_write = obj->base.write_domain;
1158
1159                 obj->dirty = 1; /* be paranoid  */
1160                 obj->base.write_domain = obj->base.pending_write_domain;
1161                 if (obj->base.write_domain == 0)
1162                         obj->base.pending_read_domains |= obj->base.read_domains;
1163                 obj->base.read_domains = obj->base.pending_read_domains;
1164
1165                 i915_vma_move_to_active(vma, req);
1166                 if (obj->base.write_domain) {
1167                         i915_gem_active_set(&obj->last_write, req);
1168
1169                         intel_fb_obj_invalidate(obj, ORIGIN_CS);
1170
1171                         /* update for the implicit flush after a batch */
1172                         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1173                 }
1174                 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1175                         i915_gem_active_set(&obj->last_fence, req);
1176                         if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1177                                 struct drm_i915_private *dev_priv = engine->i915;
1178                                 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1179                                                &dev_priv->mm.fence_list);
1180                         }
1181                 }
1182
1183                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1184         }
1185 }
1186
1187 static void
1188 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
1189 {
1190         /* Add a breadcrumb for the completion of the batch buffer */
1191         __i915_add_request(params->request, params->batch_obj, true);
1192 }
1193
1194 static int
1195 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1196 {
1197         struct intel_ring *ring = req->ring;
1198         int ret, i;
1199
1200         if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1201                 DRM_DEBUG("sol reset is gen7/rcs only\n");
1202                 return -EINVAL;
1203         }
1204
1205         ret = intel_ring_begin(req, 4 * 3);
1206         if (ret)
1207                 return ret;
1208
1209         for (i = 0; i < 4; i++) {
1210                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1211                 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1212                 intel_ring_emit(ring, 0);
1213         }
1214
1215         intel_ring_advance(ring);
1216
1217         return 0;
1218 }
1219
1220 static struct drm_i915_gem_object*
1221 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1222                           struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1223                           struct eb_vmas *eb,
1224                           struct drm_i915_gem_object *batch_obj,
1225                           u32 batch_start_offset,
1226                           u32 batch_len,
1227                           bool is_master)
1228 {
1229         struct drm_i915_gem_object *shadow_batch_obj;
1230         struct i915_vma *vma;
1231         int ret;
1232
1233         shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1234                                                    PAGE_ALIGN(batch_len));
1235         if (IS_ERR(shadow_batch_obj))
1236                 return shadow_batch_obj;
1237
1238         ret = intel_engine_cmd_parser(engine,
1239                                       batch_obj,
1240                                       shadow_batch_obj,
1241                                       batch_start_offset,
1242                                       batch_len,
1243                                       is_master);
1244         if (ret)
1245                 goto err;
1246
1247         ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1248         if (ret)
1249                 goto err;
1250
1251         i915_gem_object_unpin_pages(shadow_batch_obj);
1252
1253         memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1254
1255         vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1256         vma->exec_entry = shadow_exec_entry;
1257         vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1258         i915_gem_object_get(shadow_batch_obj);
1259         list_add_tail(&vma->exec_list, &eb->vmas);
1260
1261         shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1262
1263         return shadow_batch_obj;
1264
1265 err:
1266         i915_gem_object_unpin_pages(shadow_batch_obj);
1267         if (ret == -EACCES) /* unhandled chained batch */
1268                 return batch_obj;
1269         else
1270                 return ERR_PTR(ret);
1271 }
1272
1273 static int
1274 execbuf_submit(struct i915_execbuffer_params *params,
1275                struct drm_i915_gem_execbuffer2 *args,
1276                struct list_head *vmas)
1277 {
1278         struct drm_i915_private *dev_priv = params->request->i915;
1279         u64 exec_start, exec_len;
1280         int instp_mode;
1281         u32 instp_mask;
1282         int ret;
1283
1284         ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1285         if (ret)
1286                 return ret;
1287
1288         ret = i915_switch_context(params->request);
1289         if (ret)
1290                 return ret;
1291
1292         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1293         instp_mask = I915_EXEC_CONSTANTS_MASK;
1294         switch (instp_mode) {
1295         case I915_EXEC_CONSTANTS_REL_GENERAL:
1296         case I915_EXEC_CONSTANTS_ABSOLUTE:
1297         case I915_EXEC_CONSTANTS_REL_SURFACE:
1298                 if (instp_mode != 0 && params->engine->id != RCS) {
1299                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1300                         return -EINVAL;
1301                 }
1302
1303                 if (instp_mode != dev_priv->relative_constants_mode) {
1304                         if (INTEL_INFO(dev_priv)->gen < 4) {
1305                                 DRM_DEBUG("no rel constants on pre-gen4\n");
1306                                 return -EINVAL;
1307                         }
1308
1309                         if (INTEL_INFO(dev_priv)->gen > 5 &&
1310                             instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1311                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1312                                 return -EINVAL;
1313                         }
1314
1315                         /* The HW changed the meaning on this bit on gen6 */
1316                         if (INTEL_INFO(dev_priv)->gen >= 6)
1317                                 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1318                 }
1319                 break;
1320         default:
1321                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1322                 return -EINVAL;
1323         }
1324
1325         if (params->engine->id == RCS &&
1326             instp_mode != dev_priv->relative_constants_mode) {
1327                 struct intel_ring *ring = params->request->ring;
1328
1329                 ret = intel_ring_begin(params->request, 4);
1330                 if (ret)
1331                         return ret;
1332
1333                 intel_ring_emit(ring, MI_NOOP);
1334                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1335                 intel_ring_emit_reg(ring, INSTPM);
1336                 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1337                 intel_ring_advance(ring);
1338
1339                 dev_priv->relative_constants_mode = instp_mode;
1340         }
1341
1342         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1343                 ret = i915_reset_gen7_sol_offsets(params->request);
1344                 if (ret)
1345                         return ret;
1346         }
1347
1348         exec_len   = args->batch_len;
1349         exec_start = params->batch_obj_vm_offset +
1350                      params->args_batch_start_offset;
1351
1352         if (exec_len == 0)
1353                 exec_len = params->batch_obj->base.size;
1354
1355         ret = params->engine->emit_bb_start(params->request,
1356                                             exec_start, exec_len,
1357                                             params->dispatch_flags);
1358         if (ret)
1359                 return ret;
1360
1361         trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1362
1363         i915_gem_execbuffer_move_to_active(vmas, params->request);
1364
1365         return 0;
1366 }
1367
1368 /**
1369  * Find one BSD ring to dispatch the corresponding BSD command.
1370  * The engine index is returned.
1371  */
1372 static unsigned int
1373 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1374                          struct drm_file *file)
1375 {
1376         struct drm_i915_file_private *file_priv = file->driver_priv;
1377
1378         /* Check whether the file_priv has already selected one ring. */
1379         if ((int)file_priv->bsd_engine < 0) {
1380                 /* If not, use the ping-pong mechanism to select one. */
1381                 mutex_lock(&dev_priv->drm.struct_mutex);
1382                 file_priv->bsd_engine = dev_priv->mm.bsd_engine_dispatch_index;
1383                 dev_priv->mm.bsd_engine_dispatch_index ^= 1;
1384                 mutex_unlock(&dev_priv->drm.struct_mutex);
1385         }
1386
1387         return file_priv->bsd_engine;
1388 }
1389
1390 #define I915_USER_RINGS (4)
1391
1392 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1393         [I915_EXEC_DEFAULT]     = RCS,
1394         [I915_EXEC_RENDER]      = RCS,
1395         [I915_EXEC_BLT]         = BCS,
1396         [I915_EXEC_BSD]         = VCS,
1397         [I915_EXEC_VEBOX]       = VECS
1398 };
1399
1400 static struct intel_engine_cs *
1401 eb_select_engine(struct drm_i915_private *dev_priv,
1402                  struct drm_file *file,
1403                  struct drm_i915_gem_execbuffer2 *args)
1404 {
1405         unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1406         struct intel_engine_cs *engine;
1407
1408         if (user_ring_id > I915_USER_RINGS) {
1409                 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1410                 return NULL;
1411         }
1412
1413         if ((user_ring_id != I915_EXEC_BSD) &&
1414             ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1415                 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1416                           "bsd dispatch flags: %d\n", (int)(args->flags));
1417                 return NULL;
1418         }
1419
1420         if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1421                 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1422
1423                 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1424                         bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1425                 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1426                            bsd_idx <= I915_EXEC_BSD_RING2) {
1427                         bsd_idx >>= I915_EXEC_BSD_SHIFT;
1428                         bsd_idx--;
1429                 } else {
1430                         DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1431                                   bsd_idx);
1432                         return NULL;
1433                 }
1434
1435                 engine = &dev_priv->engine[_VCS(bsd_idx)];
1436         } else {
1437                 engine = &dev_priv->engine[user_ring_map[user_ring_id]];
1438         }
1439
1440         if (!intel_engine_initialized(engine)) {
1441                 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1442                 return NULL;
1443         }
1444
1445         return engine;
1446 }
1447
1448 static int
1449 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1450                        struct drm_file *file,
1451                        struct drm_i915_gem_execbuffer2 *args,
1452                        struct drm_i915_gem_exec_object2 *exec)
1453 {
1454         struct drm_i915_private *dev_priv = to_i915(dev);
1455         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1456         struct eb_vmas *eb;
1457         struct drm_i915_gem_object *batch_obj;
1458         struct drm_i915_gem_exec_object2 shadow_exec_entry;
1459         struct intel_engine_cs *engine;
1460         struct i915_gem_context *ctx;
1461         struct i915_address_space *vm;
1462         struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1463         struct i915_execbuffer_params *params = &params_master;
1464         const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1465         u32 dispatch_flags;
1466         int ret;
1467         bool need_relocs;
1468
1469         if (!i915_gem_check_execbuffer(args))
1470                 return -EINVAL;
1471
1472         ret = validate_exec_list(dev, exec, args->buffer_count);
1473         if (ret)
1474                 return ret;
1475
1476         dispatch_flags = 0;
1477         if (args->flags & I915_EXEC_SECURE) {
1478                 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1479                     return -EPERM;
1480
1481                 dispatch_flags |= I915_DISPATCH_SECURE;
1482         }
1483         if (args->flags & I915_EXEC_IS_PINNED)
1484                 dispatch_flags |= I915_DISPATCH_PINNED;
1485
1486         engine = eb_select_engine(dev_priv, file, args);
1487         if (!engine)
1488                 return -EINVAL;
1489
1490         if (args->buffer_count < 1) {
1491                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1492                 return -EINVAL;
1493         }
1494
1495         if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1496                 if (!HAS_RESOURCE_STREAMER(dev)) {
1497                         DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1498                         return -EINVAL;
1499                 }
1500                 if (engine->id != RCS) {
1501                         DRM_DEBUG("RS is not available on %s\n",
1502                                  engine->name);
1503                         return -EINVAL;
1504                 }
1505
1506                 dispatch_flags |= I915_DISPATCH_RS;
1507         }
1508
1509         /* Take a local wakeref for preparing to dispatch the execbuf as
1510          * we expect to access the hardware fairly frequently in the
1511          * process. Upon first dispatch, we acquire another prolonged
1512          * wakeref that we hold until the GPU has been idle for at least
1513          * 100ms.
1514          */
1515         intel_runtime_pm_get(dev_priv);
1516
1517         ret = i915_mutex_lock_interruptible(dev);
1518         if (ret)
1519                 goto pre_mutex_err;
1520
1521         ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1522         if (IS_ERR(ctx)) {
1523                 mutex_unlock(&dev->struct_mutex);
1524                 ret = PTR_ERR(ctx);
1525                 goto pre_mutex_err;
1526         }
1527
1528         i915_gem_context_get(ctx);
1529
1530         if (ctx->ppgtt)
1531                 vm = &ctx->ppgtt->base;
1532         else
1533                 vm = &ggtt->base;
1534
1535         memset(&params_master, 0x00, sizeof(params_master));
1536
1537         eb = eb_create(args);
1538         if (eb == NULL) {
1539                 i915_gem_context_put(ctx);
1540                 mutex_unlock(&dev->struct_mutex);
1541                 ret = -ENOMEM;
1542                 goto pre_mutex_err;
1543         }
1544
1545         /* Look up object handles */
1546         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1547         if (ret)
1548                 goto err;
1549
1550         /* take note of the batch buffer before we might reorder the lists */
1551         batch_obj = eb_get_batch(eb);
1552
1553         /* Move the objects en-masse into the GTT, evicting if necessary. */
1554         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1555         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1556                                           &need_relocs);
1557         if (ret)
1558                 goto err;
1559
1560         /* The objects are in their final locations, apply the relocations. */
1561         if (need_relocs)
1562                 ret = i915_gem_execbuffer_relocate(eb);
1563         if (ret) {
1564                 if (ret == -EFAULT) {
1565                         ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1566                                                                 engine,
1567                                                                 eb, exec, ctx);
1568                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1569                 }
1570                 if (ret)
1571                         goto err;
1572         }
1573
1574         /* Set the pending read domains for the batch buffer to COMMAND */
1575         if (batch_obj->base.pending_write_domain) {
1576                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1577                 ret = -EINVAL;
1578                 goto err;
1579         }
1580
1581         params->args_batch_start_offset = args->batch_start_offset;
1582         if (intel_engine_needs_cmd_parser(engine) && args->batch_len) {
1583                 struct drm_i915_gem_object *parsed_batch_obj;
1584
1585                 parsed_batch_obj = i915_gem_execbuffer_parse(engine,
1586                                                              &shadow_exec_entry,
1587                                                              eb,
1588                                                              batch_obj,
1589                                                              args->batch_start_offset,
1590                                                              args->batch_len,
1591                                                              drm_is_current_master(file));
1592                 if (IS_ERR(parsed_batch_obj)) {
1593                         ret = PTR_ERR(parsed_batch_obj);
1594                         goto err;
1595                 }
1596
1597                 /*
1598                  * parsed_batch_obj == batch_obj means batch not fully parsed:
1599                  * Accept, but don't promote to secure.
1600                  */
1601
1602                 if (parsed_batch_obj != batch_obj) {
1603                         /*
1604                          * Batch parsed and accepted:
1605                          *
1606                          * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1607                          * bit from MI_BATCH_BUFFER_START commands issued in
1608                          * the dispatch_execbuffer implementations. We
1609                          * specifically don't want that set on batches the
1610                          * command parser has accepted.
1611                          */
1612                         dispatch_flags |= I915_DISPATCH_SECURE;
1613                         params->args_batch_start_offset = 0;
1614                         batch_obj = parsed_batch_obj;
1615                 }
1616         }
1617
1618         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1619
1620         /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1621          * batch" bit. Hence we need to pin secure batches into the global gtt.
1622          * hsw should have this fixed, but bdw mucks it up again. */
1623         if (dispatch_flags & I915_DISPATCH_SECURE) {
1624                 /*
1625                  * So on first glance it looks freaky that we pin the batch here
1626                  * outside of the reservation loop. But:
1627                  * - The batch is already pinned into the relevant ppgtt, so we
1628                  *   already have the backing storage fully allocated.
1629                  * - No other BO uses the global gtt (well contexts, but meh),
1630                  *   so we don't really have issues with multiple objects not
1631                  *   fitting due to fragmentation.
1632                  * So this is actually safe.
1633                  */
1634                 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1635                 if (ret)
1636                         goto err;
1637
1638                 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
1639         } else
1640                 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
1641
1642         /* Allocate a request for this batch buffer nice and early. */
1643         params->request = i915_gem_request_alloc(engine, ctx);
1644         if (IS_ERR(params->request)) {
1645                 ret = PTR_ERR(params->request);
1646                 goto err_batch_unpin;
1647         }
1648
1649         ret = i915_gem_request_add_to_client(params->request, file);
1650         if (ret)
1651                 goto err_request;
1652
1653         /*
1654          * Save assorted stuff away to pass through to *_submission().
1655          * NB: This data should be 'persistent' and not local as it will
1656          * kept around beyond the duration of the IOCTL once the GPU
1657          * scheduler arrives.
1658          */
1659         params->dev                     = dev;
1660         params->file                    = file;
1661         params->engine                    = engine;
1662         params->dispatch_flags          = dispatch_flags;
1663         params->batch_obj               = batch_obj;
1664         params->ctx                     = ctx;
1665
1666         ret = execbuf_submit(params, args, &eb->vmas);
1667 err_request:
1668         i915_gem_execbuffer_retire_commands(params);
1669
1670 err_batch_unpin:
1671         /*
1672          * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1673          * batch vma for correctness. For less ugly and less fragility this
1674          * needs to be adjusted to also track the ggtt batch vma properly as
1675          * active.
1676          */
1677         if (dispatch_flags & I915_DISPATCH_SECURE)
1678                 i915_gem_object_ggtt_unpin(batch_obj);
1679
1680 err:
1681         /* the request owns the ref now */
1682         i915_gem_context_put(ctx);
1683         eb_destroy(eb);
1684
1685         mutex_unlock(&dev->struct_mutex);
1686
1687 pre_mutex_err:
1688         /* intel_gpu_busy should also get a ref, so it will free when the device
1689          * is really idle. */
1690         intel_runtime_pm_put(dev_priv);
1691         return ret;
1692 }
1693
1694 /*
1695  * Legacy execbuffer just creates an exec2 list from the original exec object
1696  * list array and passes it to the real function.
1697  */
1698 int
1699 i915_gem_execbuffer(struct drm_device *dev, void *data,
1700                     struct drm_file *file)
1701 {
1702         struct drm_i915_gem_execbuffer *args = data;
1703         struct drm_i915_gem_execbuffer2 exec2;
1704         struct drm_i915_gem_exec_object *exec_list = NULL;
1705         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1706         int ret, i;
1707
1708         if (args->buffer_count < 1) {
1709                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1710                 return -EINVAL;
1711         }
1712
1713         /* Copy in the exec list from userland */
1714         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1715         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1716         if (exec_list == NULL || exec2_list == NULL) {
1717                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1718                           args->buffer_count);
1719                 drm_free_large(exec_list);
1720                 drm_free_large(exec2_list);
1721                 return -ENOMEM;
1722         }
1723         ret = copy_from_user(exec_list,
1724                              u64_to_user_ptr(args->buffers_ptr),
1725                              sizeof(*exec_list) * args->buffer_count);
1726         if (ret != 0) {
1727                 DRM_DEBUG("copy %d exec entries failed %d\n",
1728                           args->buffer_count, ret);
1729                 drm_free_large(exec_list);
1730                 drm_free_large(exec2_list);
1731                 return -EFAULT;
1732         }
1733
1734         for (i = 0; i < args->buffer_count; i++) {
1735                 exec2_list[i].handle = exec_list[i].handle;
1736                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1737                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1738                 exec2_list[i].alignment = exec_list[i].alignment;
1739                 exec2_list[i].offset = exec_list[i].offset;
1740                 if (INTEL_INFO(dev)->gen < 4)
1741                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1742                 else
1743                         exec2_list[i].flags = 0;
1744         }
1745
1746         exec2.buffers_ptr = args->buffers_ptr;
1747         exec2.buffer_count = args->buffer_count;
1748         exec2.batch_start_offset = args->batch_start_offset;
1749         exec2.batch_len = args->batch_len;
1750         exec2.DR1 = args->DR1;
1751         exec2.DR4 = args->DR4;
1752         exec2.num_cliprects = args->num_cliprects;
1753         exec2.cliprects_ptr = args->cliprects_ptr;
1754         exec2.flags = I915_EXEC_RENDER;
1755         i915_execbuffer2_set_context_id(exec2, 0);
1756
1757         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1758         if (!ret) {
1759                 struct drm_i915_gem_exec_object __user *user_exec_list =
1760                         u64_to_user_ptr(args->buffers_ptr);
1761
1762                 /* Copy the new buffer offsets back to the user's exec list. */
1763                 for (i = 0; i < args->buffer_count; i++) {
1764                         exec2_list[i].offset =
1765                                 gen8_canonical_addr(exec2_list[i].offset);
1766                         ret = __copy_to_user(&user_exec_list[i].offset,
1767                                              &exec2_list[i].offset,
1768                                              sizeof(user_exec_list[i].offset));
1769                         if (ret) {
1770                                 ret = -EFAULT;
1771                                 DRM_DEBUG("failed to copy %d exec entries "
1772                                           "back to user (%d)\n",
1773                                           args->buffer_count, ret);
1774                                 break;
1775                         }
1776                 }
1777         }
1778
1779         drm_free_large(exec_list);
1780         drm_free_large(exec2_list);
1781         return ret;
1782 }
1783
1784 int
1785 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1786                      struct drm_file *file)
1787 {
1788         struct drm_i915_gem_execbuffer2 *args = data;
1789         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1790         int ret;
1791
1792         if (args->buffer_count < 1 ||
1793             args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1794                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1795                 return -EINVAL;
1796         }
1797
1798         if (args->rsvd2 != 0) {
1799                 DRM_DEBUG("dirty rvsd2 field\n");
1800                 return -EINVAL;
1801         }
1802
1803         exec2_list = drm_malloc_gfp(args->buffer_count,
1804                                     sizeof(*exec2_list),
1805                                     GFP_TEMPORARY);
1806         if (exec2_list == NULL) {
1807                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1808                           args->buffer_count);
1809                 return -ENOMEM;
1810         }
1811         ret = copy_from_user(exec2_list,
1812                              u64_to_user_ptr(args->buffers_ptr),
1813                              sizeof(*exec2_list) * args->buffer_count);
1814         if (ret != 0) {
1815                 DRM_DEBUG("copy %d exec entries failed %d\n",
1816                           args->buffer_count, ret);
1817                 drm_free_large(exec2_list);
1818                 return -EFAULT;
1819         }
1820
1821         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1822         if (!ret) {
1823                 /* Copy the new buffer offsets back to the user's exec list. */
1824                 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1825                                    u64_to_user_ptr(args->buffers_ptr);
1826                 int i;
1827
1828                 for (i = 0; i < args->buffer_count; i++) {
1829                         exec2_list[i].offset =
1830                                 gen8_canonical_addr(exec2_list[i].offset);
1831                         ret = __copy_to_user(&user_exec_list[i].offset,
1832                                              &exec2_list[i].offset,
1833                                              sizeof(user_exec_list[i].offset));
1834                         if (ret) {
1835                                 ret = -EFAULT;
1836                                 DRM_DEBUG("failed to copy %d exec entries "
1837                                           "back to user\n",
1838                                           args->buffer_count);
1839                                 break;
1840                         }
1841                 }
1842         }
1843
1844         drm_free_large(exec2_list);
1845         return ret;
1846 }