drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <linux/dma_remapping.h>
  30 #include <linux/reservation.h>
  31 #include <linux/uaccess.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35
  36 #include "i915_drv.h"
  37 #include "i915_gem_dmabuf.h"
  38 #include "i915_trace.h"
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41
  42 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
  43
  44 #define  __EXEC_OBJECT_HAS_PIN          (1<<31)
  45 #define  __EXEC_OBJECT_HAS_FENCE        (1<<30)
  46 #define  __EXEC_OBJECT_NEEDS_MAP        (1<<29)
  47 #define  __EXEC_OBJECT_NEEDS_BIAS       (1<<28)
  48 #define  __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
  49
  50 #define BATCH_OFFSET_BIAS (256*1024)
  51
  52 struct i915_execbuffer_params {
  53         struct drm_device               *dev;
  54         struct drm_file                 *file;
  55         struct i915_vma                 *batch;
  56         u32                             dispatch_flags;
  57         u32                             args_batch_start_offset;
  58         struct intel_engine_cs          *engine;
  59         struct i915_gem_context         *ctx;
  60         struct drm_i915_gem_request     *request;
  61 };
  62
  63 struct eb_vmas {
  64         struct drm_i915_private *i915;
  65         struct list_head vmas;
  66         int and;
  67         union {
  68                 struct i915_vma *lut[0];
  69                 struct hlist_head buckets[0];
  70         };
  71 };
  72
  73 static struct eb_vmas *
  74 eb_create(struct drm_i915_private *i915,
  75           struct drm_i915_gem_execbuffer2 *args)
  76 {
  77         struct eb_vmas *eb = NULL;
  78
  79         if (args->flags & I915_EXEC_HANDLE_LUT) {
  80                 unsigned size = args->buffer_count;
  81                 size *= sizeof(struct i915_vma *);
  82                 size += sizeof(struct eb_vmas);
  83                 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  84         }
  85
  86         if (eb == NULL) {
  87                 unsigned size = args->buffer_count;
  88                 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  89                 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  90                 while (count > 2*size)
  91                         count >>= 1;
  92                 eb = kzalloc(count*sizeof(struct hlist_head) +
  93                              sizeof(struct eb_vmas),
  94                              GFP_TEMPORARY);
  95                 if (eb == NULL)
  96                         return eb;
  97
  98                 eb->and = count - 1;
  99         } else
 100                 eb->and = -args->buffer_count;
 101
 102         eb->i915 = i915;
 103         INIT_LIST_HEAD(&eb->vmas);
 104         return eb;
 105 }
 106
 107 static void
 108 eb_reset(struct eb_vmas *eb)
 109 {
 110         if (eb->and >= 0)
 111                 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 112 }
 113
 114 static struct i915_vma *
 115 eb_get_batch(struct eb_vmas *eb)
 116 {
 117         struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
 118
 119         /*
 120          * SNA is doing fancy tricks with compressing batch buffers, which leads
 121          * to negative relocation deltas. Usually that works out ok since the
 122          * relocate address is still positive, except when the batch is placed
 123          * very low in the GTT. Ensure this doesn't happen.
 124          *
 125          * Note that actual hangs have only been observed on gen7, but for
 126          * paranoia do it everywhere.
 127          */
 128         if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
 129                 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 130
 131         return vma;
 132 }
 133
 134 static int
 135 eb_lookup_vmas(struct eb_vmas *eb,
 136                struct drm_i915_gem_exec_object2 *exec,
 137                const struct drm_i915_gem_execbuffer2 *args,
 138                struct i915_address_space *vm,
 139                struct drm_file *file)
 140 {
 141         struct drm_i915_gem_object *obj;
 142         struct list_head objects;
 143         int i, ret;
 144
 145         INIT_LIST_HEAD(&objects);
 146         spin_lock(&file->table_lock);
 147         /* Grab a reference to the object and release the lock so we can lookup
 148          * or create the VMA without using GFP_ATOMIC */
 149         for (i = 0; i < args->buffer_count; i++) {
 150                 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
 151                 if (obj == NULL) {
 152                         spin_unlock(&file->table_lock);
 153                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 154                                    exec[i].handle, i);
 155                         ret = -ENOENT;
 156                         goto err;
 157                 }
 158
 159                 if (!list_empty(&obj->obj_exec_link)) {
 160                         spin_unlock(&file->table_lock);
 161                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
 162                                    obj, exec[i].handle, i);
 163                         ret = -EINVAL;
 164                         goto err;
 165                 }
 166
 167                 i915_gem_object_get(obj);
 168                 list_add_tail(&obj->obj_exec_link, &objects);
 169         }
 170         spin_unlock(&file->table_lock);
 171
 172         i = 0;
 173         while (!list_empty(&objects)) {
 174                 struct i915_vma *vma;
 175
 176                 obj = list_first_entry(&objects,
 177                                        struct drm_i915_gem_object,
 178                                        obj_exec_link);
 179
 180                 /*
 181                  * NOTE: We can leak any vmas created here when something fails
 182                  * later on. But that's no issue since vma_unbind can deal with
 183                  * vmas which are not actually bound. And since only
 184                  * lookup_or_create exists as an interface to get at the vma
 185                  * from the (obj, vm) we don't run the risk of creating
 186                  * duplicated vmas for the same vm.
 187                  */
 188                 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, NULL);
 189                 if (unlikely(IS_ERR(vma))) {
 190                         DRM_DEBUG("Failed to lookup VMA\n");
 191                         ret = PTR_ERR(vma);
 192                         goto err;
 193                 }
 194
 195                 /* Transfer ownership from the objects list to the vmas list. */
 196                 list_add_tail(&vma->exec_list, &eb->vmas);
 197                 list_del_init(&obj->obj_exec_link);
 198
 199                 vma->exec_entry = &exec[i];
 200                 if (eb->and < 0) {
 201                         eb->lut[i] = vma;
 202                 } else {
 203                         uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
 204                         vma->exec_handle = handle;
 205                         hlist_add_head(&vma->exec_node,
 206                                        &eb->buckets[handle & eb->and]);
 207                 }
 208                 ++i;
 209         }
 210
 211         return 0;
 212
 213
 214 err:
 215         while (!list_empty(&objects)) {
 216                 obj = list_first_entry(&objects,
 217                                        struct drm_i915_gem_object,
 218                                        obj_exec_link);
 219                 list_del_init(&obj->obj_exec_link);
 220                 i915_gem_object_put(obj);
 221         }
 222         /*
 223          * Objects already transfered to the vmas list will be unreferenced by
 224          * eb_destroy.
 225          */
 226
 227         return ret;
 228 }
 229
 230 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
 231 {
 232         if (eb->and < 0) {
 233                 if (handle >= -eb->and)
 234                         return NULL;
 235                 return eb->lut[handle];
 236         } else {
 237                 struct hlist_head *head;
 238                 struct i915_vma *vma;
 239
 240                 head = &eb->buckets[handle & eb->and];
 241                 hlist_for_each_entry(vma, head, exec_node) {
 242                         if (vma->exec_handle == handle)
 243                                 return vma;
 244                 }
 245                 return NULL;
 246         }
 247 }
 248
 249 static void
 250 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
 251 {
 252         struct drm_i915_gem_exec_object2 *entry;
 253         struct drm_i915_gem_object *obj = vma->obj;
 254
 255         if (!drm_mm_node_allocated(&vma->node))
 256                 return;
 257
 258         entry = vma->exec_entry;
 259
 260         if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
 261                 i915_gem_object_unpin_fence(obj);
 262
 263         if (entry->flags & __EXEC_OBJECT_HAS_PIN)
 264                 __i915_vma_unpin(vma);
 265
 266         entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
 267 }
 268
 269 static void eb_destroy(struct eb_vmas *eb)
 270 {
 271         while (!list_empty(&eb->vmas)) {
 272                 struct i915_vma *vma;
 273
 274                 vma = list_first_entry(&eb->vmas,
 275                                        struct i915_vma,
 276                                        exec_list);
 277                 list_del_init(&vma->exec_list);
 278                 i915_gem_execbuffer_unreserve_vma(vma);
 279                 i915_vma_put(vma);
 280         }
 281         kfree(eb);
 282 }
 283
 284 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 285 {
 286         if (!i915_gem_object_has_struct_page(obj))
 287                 return false;
 288
 289         if (DBG_USE_CPU_RELOC)
 290                 return DBG_USE_CPU_RELOC > 0;
 291
 292         return (HAS_LLC(obj->base.dev) ||
 293                 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 294                 obj->cache_level != I915_CACHE_NONE);
 295 }
 296
 297 /* Used to convert any address to canonical form.
 298  * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
 299  * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
 300  * addresses to be in a canonical form:
 301  * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
 302  * canonical form [63:48] == [47]."
 303  */
 304 #define GEN8_HIGH_ADDRESS_BIT 47
 305 static inline uint64_t gen8_canonical_addr(uint64_t address)
 306 {
 307         return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
 308 }
 309
 310 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
 311 {
 312         return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
 313 }
 314
 315 static inline uint64_t
 316 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
 317                   uint64_t target_offset)
 318 {
 319         return gen8_canonical_addr((int)reloc->delta + target_offset);
 320 }
 321
 322 struct reloc_cache {
 323         struct drm_i915_private *i915;
 324         struct drm_mm_node node;
 325         unsigned long vaddr;
 326         unsigned int page;
 327         bool use_64bit_reloc;
 328 };
 329
 330 static void reloc_cache_init(struct reloc_cache *cache,
 331                              struct drm_i915_private *i915)
 332 {
 333         cache->page = -1;
 334         cache->vaddr = 0;
 335         cache->i915 = i915;
 336         cache->use_64bit_reloc = INTEL_GEN(cache->i915) >= 8;
 337         cache->node.allocated = false;
 338 }
 339
 340 static inline void *unmask_page(unsigned long p)
 341 {
 342         return (void *)(uintptr_t)(p & PAGE_MASK);
 343 }
 344
 345 static inline unsigned int unmask_flags(unsigned long p)
 346 {
 347         return p & ~PAGE_MASK;
 348 }
 349
 350 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
 351
 352 static void reloc_cache_fini(struct reloc_cache *cache)
 353 {
 354         void *vaddr;
 355
 356         if (!cache->vaddr)
 357                 return;
 358
 359         vaddr = unmask_page(cache->vaddr);
 360         if (cache->vaddr & KMAP) {
 361                 if (cache->vaddr & CLFLUSH_AFTER)
 362                         mb();
 363
 364                 kunmap_atomic(vaddr);
 365                 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
 366         } else {
 367                 wmb();
 368                 io_mapping_unmap_atomic((void __iomem *)vaddr);
 369                 if (cache->node.allocated) {
 370                         struct i915_ggtt *ggtt = &cache->i915->ggtt;
 371
 372                         ggtt->base.clear_range(&ggtt->base,
 373                                                cache->node.start,
 374                                                cache->node.size,
 375                                                true);
 376                         drm_mm_remove_node(&cache->node);
 377                 } else {
 378                         i915_vma_unpin((struct i915_vma *)cache->node.mm);
 379                 }
 380         }
 381 }
 382
 383 static void *reloc_kmap(struct drm_i915_gem_object *obj,
 384                         struct reloc_cache *cache,
 385                         int page)
 386 {
 387         void *vaddr;
 388
 389         if (cache->vaddr) {
 390                 kunmap_atomic(unmask_page(cache->vaddr));
 391         } else {
 392                 unsigned int flushes;
 393                 int ret;
 394
 395                 ret = i915_gem_obj_prepare_shmem_write(obj, &flushes);
 396                 if (ret)
 397                         return ERR_PTR(ret);
 398
 399                 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
 400                 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
 401
 402                 cache->vaddr = flushes | KMAP;
 403                 cache->node.mm = (void *)obj;
 404                 if (flushes)
 405                         mb();
 406         }
 407
 408         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
 409         cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
 410         cache->page = page;
 411
 412         return vaddr;
 413 }
 414
 415 static void *reloc_iomap(struct drm_i915_gem_object *obj,
 416                          struct reloc_cache *cache,
 417                          int page)
 418 {
 419         struct i915_ggtt *ggtt = &cache->i915->ggtt;
 420         unsigned long offset;
 421         void *vaddr;
 422
 423         if (cache->node.allocated) {
 424                 wmb();
 425                 ggtt->base.insert_page(&ggtt->base,
 426                                        i915_gem_object_get_dma_address(obj, page),
 427                                        cache->node.start, I915_CACHE_NONE, 0);
 428                 cache->page = page;
 429                 return unmask_page(cache->vaddr);
 430         }
 431
 432         if (cache->vaddr) {
 433                 io_mapping_unmap_atomic(unmask_page(cache->vaddr));
 434         } else {
 435                 struct i915_vma *vma;
 436                 int ret;
 437
 438                 if (use_cpu_reloc(obj))
 439                         return NULL;
 440
 441                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
 442                 if (ret)
 443                         return ERR_PTR(ret);
 444
 445                 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
 446                                                PIN_MAPPABLE | PIN_NONBLOCK);
 447                 if (IS_ERR(vma)) {
 448                         memset(&cache->node, 0, sizeof(cache->node));
 449                         ret = drm_mm_insert_node_in_range_generic
 450                                 (&ggtt->base.mm, &cache->node,
 451                                  4096, 0, 0,
 452                                  0, ggtt->mappable_end,
 453                                  DRM_MM_SEARCH_DEFAULT,
 454                                  DRM_MM_CREATE_DEFAULT);
 455                         if (ret)
 456                                 return ERR_PTR(ret);
 457                 } else {
 458                         ret = i915_gem_object_put_fence(obj);
 459                         if (ret) {
 460                                 i915_vma_unpin(vma);
 461                                 return ERR_PTR(ret);
 462                         }
 463
 464                         cache->node.start = vma->node.start;
 465                         cache->node.mm = (void *)vma;
 466                 }
 467         }
 468
 469         offset = cache->node.start;
 470         if (cache->node.allocated) {
 471                 ggtt->base.insert_page(&ggtt->base,
 472                                        i915_gem_object_get_dma_address(obj, page),
 473                                        offset, I915_CACHE_NONE, 0);
 474         } else {
 475                 offset += page << PAGE_SHIFT;
 476         }
 477
 478         vaddr = io_mapping_map_atomic_wc(cache->i915->ggtt.mappable, offset);
 479         cache->page = page;
 480         cache->vaddr = (unsigned long)vaddr;
 481
 482         return vaddr;
 483 }
 484
 485 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
 486                          struct reloc_cache *cache,
 487                          int page)
 488 {
 489         void *vaddr;
 490
 491         if (cache->page == page) {
 492                 vaddr = unmask_page(cache->vaddr);
 493         } else {
 494                 vaddr = NULL;
 495                 if ((cache->vaddr & KMAP) == 0)
 496                         vaddr = reloc_iomap(obj, cache, page);
 497                 if (!vaddr)
 498                         vaddr = reloc_kmap(obj, cache, page);
 499         }
 500
 501         return vaddr;
 502 }
 503
 504 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 505 {
 506         if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
 507                 if (flushes & CLFLUSH_BEFORE) {
 508                         clflushopt(addr);
 509                         mb();
 510                 }
 511
 512                 *addr = value;
 513
 514                 /* Writes to the same cacheline are serialised by the CPU
 515                  * (including clflush). On the write path, we only require
 516                  * that it hits memory in an orderly fashion and place
 517                  * mb barriers at the start and end of the relocation phase
 518                  * to ensure ordering of clflush wrt to the system.
 519                  */
 520                 if (flushes & CLFLUSH_AFTER)
 521                         clflushopt(addr);
 522         } else
 523                 *addr = value;
 524 }
 525
 526 static int
 527 relocate_entry(struct drm_i915_gem_object *obj,
 528                const struct drm_i915_gem_relocation_entry *reloc,
 529                struct reloc_cache *cache,
 530                u64 target_offset)
 531 {
 532         u64 offset = reloc->offset;
 533         bool wide = cache->use_64bit_reloc;
 534         void *vaddr;
 535
 536         target_offset = relocation_target(reloc, target_offset);
 537 repeat:
 538         vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT);
 539         if (IS_ERR(vaddr))
 540                 return PTR_ERR(vaddr);
 541
 542         clflush_write32(vaddr + offset_in_page(offset),
 543                         lower_32_bits(target_offset),
 544                         cache->vaddr);
 545
 546         if (wide) {
 547                 offset += sizeof(u32);
 548                 target_offset >>= 32;
 549                 wide = false;
 550                 goto repeat;
 551         }
 552
 553         return 0;
 554 }
 555
 556 static bool object_is_idle(struct drm_i915_gem_object *obj)
 557 {
 558         unsigned long active = i915_gem_object_get_active(obj);
 559         int idx;
 560
 561         for_each_active(active, idx) {
 562                 if (!i915_gem_active_is_idle(&obj->last_read[idx],
 563                                              &obj->base.dev->struct_mutex))
 564                         return false;
 565         }
 566
 567         return true;
 568 }
 569
 570 static int
 571 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 572                                    struct eb_vmas *eb,
 573                                    struct drm_i915_gem_relocation_entry *reloc,
 574                                    struct reloc_cache *cache)
 575 {
 576         struct drm_device *dev = obj->base.dev;
 577         struct drm_gem_object *target_obj;
 578         struct drm_i915_gem_object *target_i915_obj;
 579         struct i915_vma *target_vma;
 580         uint64_t target_offset;
 581         int ret;
 582
 583         /* we've already hold a reference to all valid objects */
 584         target_vma = eb_get_vma(eb, reloc->target_handle);
 585         if (unlikely(target_vma == NULL))
 586                 return -ENOENT;
 587         target_i915_obj = target_vma->obj;
 588         target_obj = &target_vma->obj->base;
 589
 590         target_offset = gen8_canonical_addr(target_vma->node.start);
 591
 592         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 593          * pipe_control writes because the gpu doesn't properly redirect them
 594          * through the ppgtt for non_secure batchbuffers. */
 595         if (unlikely(IS_GEN6(dev) &&
 596             reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
 597                 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
 598                                     PIN_GLOBAL);
 599                 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
 600                         return ret;
 601         }
 602
 603         /* Validate that the target is in a valid r/w GPU domain */
 604         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 605                 DRM_DEBUG("reloc with multiple write domains: "
 606                           "obj %p target %d offset %d "
 607                           "read %08x write %08x",
 608                           obj, reloc->target_handle,
 609                           (int) reloc->offset,
 610                           reloc->read_domains,
 611                           reloc->write_domain);
 612                 return -EINVAL;
 613         }
 614         if (unlikely((reloc->write_domain | reloc->read_domains)
 615                      & ~I915_GEM_GPU_DOMAINS)) {
 616                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 617                           "obj %p target %d offset %d "
 618                           "read %08x write %08x",
 619                           obj, reloc->target_handle,
 620                           (int) reloc->offset,
 621                           reloc->read_domains,
 622                           reloc->write_domain);
 623                 return -EINVAL;
 624         }
 625
 626         target_obj->pending_read_domains |= reloc->read_domains;
 627         target_obj->pending_write_domain |= reloc->write_domain;
 628
 629         /* If the relocation already has the right value in it, no
 630          * more work needs to be done.
 631          */
 632         if (target_offset == reloc->presumed_offset)
 633                 return 0;
 634
 635         /* Check that the relocation address is valid... */
 636         if (unlikely(reloc->offset >
 637                      obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) {
 638                 DRM_DEBUG("Relocation beyond object bounds: "
 639                           "obj %p target %d offset %d size %d.\n",
 640                           obj, reloc->target_handle,
 641                           (int) reloc->offset,
 642                           (int) obj->base.size);
 643                 return -EINVAL;
 644         }
 645         if (unlikely(reloc->offset & 3)) {
 646                 DRM_DEBUG("Relocation not 4-byte aligned: "
 647                           "obj %p target %d offset %d.\n",
 648                           obj, reloc->target_handle,
 649                           (int) reloc->offset);
 650                 return -EINVAL;
 651         }
 652
 653         /* We can't wait for rendering with pagefaults disabled */
 654         if (pagefault_disabled() && !object_is_idle(obj))
 655                 return -EFAULT;
 656
 657         ret = relocate_entry(obj, reloc, cache, target_offset);
 658         if (ret)
 659                 return ret;
 660
 661         /* and update the user's relocation entry */
 662         reloc->presumed_offset = target_offset;
 663         return 0;
 664 }
 665
 666 static int
 667 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
 668                                  struct eb_vmas *eb)
 669 {
 670 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
 671         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
 672         struct drm_i915_gem_relocation_entry __user *user_relocs;
 673         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 674         struct reloc_cache cache;
 675         int remain, ret = 0;
 676
 677         user_relocs = u64_to_user_ptr(entry->relocs_ptr);
 678         reloc_cache_init(&cache, eb->i915);
 679
 680         remain = entry->relocation_count;
 681         while (remain) {
 682                 struct drm_i915_gem_relocation_entry *r = stack_reloc;
 683                 int count = remain;
 684                 if (count > ARRAY_SIZE(stack_reloc))
 685                         count = ARRAY_SIZE(stack_reloc);
 686                 remain -= count;
 687
 688                 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) {
 689                         ret = -EFAULT;
 690                         goto out;
 691                 }
 692
 693                 do {
 694                         u64 offset = r->presumed_offset;
 695
 696                         ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, &cache);
 697                         if (ret)
 698                                 goto out;
 699
 700                         if (r->presumed_offset != offset &&
 701                             __put_user(r->presumed_offset,
 702                                        &user_relocs->presumed_offset)) {
 703                                 ret = -EFAULT;
 704                                 goto out;
 705                         }
 706
 707                         user_relocs++;
 708                         r++;
 709                 } while (--count);
 710         }
 711
 712 out:
 713         reloc_cache_fini(&cache);
 714         return ret;
 715 #undef N_RELOC
 716 }
 717
 718 static int
 719 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
 720                                       struct eb_vmas *eb,
 721                                       struct drm_i915_gem_relocation_entry *relocs)
 722 {
 723         const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 724         struct reloc_cache cache;
 725         int i, ret = 0;
 726
 727         reloc_cache_init(&cache, eb->i915);
 728         for (i = 0; i < entry->relocation_count; i++) {
 729                 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], &cache);
 730                 if (ret)
 731                         break;
 732         }
 733         reloc_cache_fini(&cache);
 734
 735         return ret;
 736 }
 737
 738 static int
 739 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
 740 {
 741         struct i915_vma *vma;
 742         int ret = 0;
 743
 744         /* This is the fast path and we cannot handle a pagefault whilst
 745          * holding the struct mutex lest the user pass in the relocations
 746          * contained within a mmaped bo. For in such a case we, the page
 747          * fault handler would call i915_gem_fault() and we would try to
 748          * acquire the struct mutex again. Obviously this is bad and so
 749          * lockdep complains vehemently.
 750          */
 751         pagefault_disable();
 752         list_for_each_entry(vma, &eb->vmas, exec_list) {
 753                 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
 754                 if (ret)
 755                         break;
 756         }
 757         pagefault_enable();
 758
 759         return ret;
 760 }
 761
 762 static bool only_mappable_for_reloc(unsigned int flags)
 763 {
 764         return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
 765                 __EXEC_OBJECT_NEEDS_MAP;
 766 }
 767
 768 static int
 769 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 770                                 struct intel_engine_cs *engine,
 771                                 bool *need_reloc)
 772 {
 773         struct drm_i915_gem_object *obj = vma->obj;
 774         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 775         uint64_t flags;
 776         int ret;
 777
 778         flags = PIN_USER;
 779         if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
 780                 flags |= PIN_GLOBAL;
 781
 782         if (!drm_mm_node_allocated(&vma->node)) {
 783                 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
 784                  * limit address to the first 4GBs for unflagged objects.
 785                  */
 786                 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
 787                         flags |= PIN_ZONE_4G;
 788                 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
 789                         flags |= PIN_GLOBAL | PIN_MAPPABLE;
 790                 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
 791                         flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
 792                 if (entry->flags & EXEC_OBJECT_PINNED)
 793                         flags |= entry->offset | PIN_OFFSET_FIXED;
 794                 if ((flags & PIN_MAPPABLE) == 0)
 795                         flags |= PIN_HIGH;
 796         }
 797
 798         ret = i915_vma_pin(vma,
 799                            entry->pad_to_size,
 800                            entry->alignment,
 801                            flags);
 802         if ((ret == -ENOSPC || ret == -E2BIG) &&
 803             only_mappable_for_reloc(entry->flags))
 804                 ret = i915_vma_pin(vma,
 805                                    entry->pad_to_size,
 806                                    entry->alignment,
 807                                    flags & ~PIN_MAPPABLE);
 808         if (ret)
 809                 return ret;
 810
 811         entry->flags |= __EXEC_OBJECT_HAS_PIN;
 812
 813         if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 814                 ret = i915_gem_object_get_fence(obj);
 815                 if (ret)
 816                         return ret;
 817
 818                 if (i915_gem_object_pin_fence(obj))
 819                         entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 820         }
 821
 822         if (entry->offset != vma->node.start) {
 823                 entry->offset = vma->node.start;
 824                 *need_reloc = true;
 825         }
 826
 827         if (entry->flags & EXEC_OBJECT_WRITE) {
 828                 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
 829                 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static bool
 836 need_reloc_mappable(struct i915_vma *vma)
 837 {
 838         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 839
 840         if (entry->relocation_count == 0)
 841                 return false;
 842
 843         if (!i915_vma_is_ggtt(vma))
 844                 return false;
 845
 846         /* See also use_cpu_reloc() */
 847         if (HAS_LLC(vma->obj->base.dev))
 848                 return false;
 849
 850         if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
 851                 return false;
 852
 853         return true;
 854 }
 855
 856 static bool
 857 eb_vma_misplaced(struct i915_vma *vma)
 858 {
 859         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 860         struct drm_i915_gem_object *obj = vma->obj;
 861
 862         WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
 863                 !i915_vma_is_ggtt(vma));
 864
 865         if (entry->alignment &&
 866             vma->node.start & (entry->alignment - 1))
 867                 return true;
 868
 869         if (vma->node.size < entry->pad_to_size)
 870                 return true;
 871
 872         if (entry->flags & EXEC_OBJECT_PINNED &&
 873             vma->node.start != entry->offset)
 874                 return true;
 875
 876         if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
 877             vma->node.start < BATCH_OFFSET_BIAS)
 878                 return true;
 879
 880         /* avoid costly ping-pong once a batch bo ended up non-mappable */
 881         if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
 882                 return !only_mappable_for_reloc(entry->flags);
 883
 884         if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
 885             (vma->node.start + vma->node.size - 1) >> 32)
 886                 return true;
 887
 888         return false;
 889 }
 890
 891 static int
 892 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
 893                             struct list_head *vmas,
 894                             struct i915_gem_context *ctx,
 895                             bool *need_relocs)
 896 {
 897         struct drm_i915_gem_object *obj;
 898         struct i915_vma *vma;
 899         struct i915_address_space *vm;
 900         struct list_head ordered_vmas;
 901         struct list_head pinned_vmas;
 902         bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
 903         int retry;
 904
 905         vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
 906
 907         INIT_LIST_HEAD(&ordered_vmas);
 908         INIT_LIST_HEAD(&pinned_vmas);
 909         while (!list_empty(vmas)) {
 910                 struct drm_i915_gem_exec_object2 *entry;
 911                 bool need_fence, need_mappable;
 912
 913                 vma = list_first_entry(vmas, struct i915_vma, exec_list);
 914                 obj = vma->obj;
 915                 entry = vma->exec_entry;
 916
 917                 if (ctx->flags & CONTEXT_NO_ZEROMAP)
 918                         entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 919
 920                 if (!has_fenced_gpu_access)
 921                         entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 922                 need_fence =
 923                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 924                         i915_gem_object_is_tiled(obj);
 925                 need_mappable = need_fence || need_reloc_mappable(vma);
 926
 927                 if (entry->flags & EXEC_OBJECT_PINNED)
 928                         list_move_tail(&vma->exec_list, &pinned_vmas);
 929                 else if (need_mappable) {
 930                         entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
 931                         list_move(&vma->exec_list, &ordered_vmas);
 932                 } else
 933                         list_move_tail(&vma->exec_list, &ordered_vmas);
 934
 935                 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
 936                 obj->base.pending_write_domain = 0;
 937         }
 938         list_splice(&ordered_vmas, vmas);
 939         list_splice(&pinned_vmas, vmas);
 940
 941         /* Attempt to pin all of the buffers into the GTT.
 942          * This is done in 3 phases:
 943          *
 944          * 1a. Unbind all objects that do not match the GTT constraints for
 945          *     the execbuffer (fenceable, mappable, alignment etc).
 946          * 1b. Increment pin count for already bound objects.
 947          * 2.  Bind new objects.
 948          * 3.  Decrement pin count.
 949          *
 950          * This avoid unnecessary unbinding of later objects in order to make
 951          * room for the earlier objects *unless* we need to defragment.
 952          */
 953         retry = 0;
 954         do {
 955                 int ret = 0;
 956
 957                 /* Unbind any ill-fitting objects or pin. */
 958                 list_for_each_entry(vma, vmas, exec_list) {
 959                         if (!drm_mm_node_allocated(&vma->node))
 960                                 continue;
 961
 962                         if (eb_vma_misplaced(vma))
 963                                 ret = i915_vma_unbind(vma);
 964                         else
 965                                 ret = i915_gem_execbuffer_reserve_vma(vma,
 966                                                                       engine,
 967                                                                       need_relocs);
 968                         if (ret)
 969                                 goto err;
 970                 }
 971
 972                 /* Bind fresh objects */
 973                 list_for_each_entry(vma, vmas, exec_list) {
 974                         if (drm_mm_node_allocated(&vma->node))
 975                                 continue;
 976
 977                         ret = i915_gem_execbuffer_reserve_vma(vma, engine,
 978                                                               need_relocs);
 979                         if (ret)
 980                                 goto err;
 981                 }
 982
 983 err:
 984                 if (ret != -ENOSPC || retry++)
 985                         return ret;
 986
 987                 /* Decrement pin count for bound objects */
 988                 list_for_each_entry(vma, vmas, exec_list)
 989                         i915_gem_execbuffer_unreserve_vma(vma);
 990
 991                 ret = i915_gem_evict_vm(vm, true);
 992                 if (ret)
 993                         return ret;
 994         } while (1);
 995 }
 996
 997 static int
 998 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 999                                   struct drm_i915_gem_execbuffer2 *args,
1000                                   struct drm_file *file,
1001                                   struct intel_engine_cs *engine,
1002                                   struct eb_vmas *eb,
1003                                   struct drm_i915_gem_exec_object2 *exec,
1004                                   struct i915_gem_context *ctx)
1005 {
1006         struct drm_i915_gem_relocation_entry *reloc;
1007         struct i915_address_space *vm;
1008         struct i915_vma *vma;
1009         bool need_relocs;
1010         int *reloc_offset;
1011         int i, total, ret;
1012         unsigned count = args->buffer_count;
1013
1014         vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
1015
1016         /* We may process another execbuffer during the unlock... */
1017         while (!list_empty(&eb->vmas)) {
1018                 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
1019                 list_del_init(&vma->exec_list);
1020                 i915_gem_execbuffer_unreserve_vma(vma);
1021                 i915_vma_put(vma);
1022         }
1023
1024         mutex_unlock(&dev->struct_mutex);
1025
1026         total = 0;
1027         for (i = 0; i < count; i++)
1028                 total += exec[i].relocation_count;
1029
1030         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
1031         reloc = drm_malloc_ab(total, sizeof(*reloc));
1032         if (reloc == NULL || reloc_offset == NULL) {
1033                 drm_free_large(reloc);
1034                 drm_free_large(reloc_offset);
1035                 mutex_lock(&dev->struct_mutex);
1036                 return -ENOMEM;
1037         }
1038
1039         total = 0;
1040         for (i = 0; i < count; i++) {
1041                 struct drm_i915_gem_relocation_entry __user *user_relocs;
1042                 u64 invalid_offset = (u64)-1;
1043                 int j;
1044
1045                 user_relocs = u64_to_user_ptr(exec[i].relocs_ptr);
1046
1047                 if (copy_from_user(reloc+total, user_relocs,
1048                                    exec[i].relocation_count * sizeof(*reloc))) {
1049                         ret = -EFAULT;
1050                         mutex_lock(&dev->struct_mutex);
1051                         goto err;
1052                 }
1053
1054                 /* As we do not update the known relocation offsets after
1055                  * relocating (due to the complexities in lock handling),
1056                  * we need to mark them as invalid now so that we force the
1057                  * relocation processing next time. Just in case the target
1058                  * object is evicted and then rebound into its old
1059                  * presumed_offset before the next execbuffer - if that
1060                  * happened we would make the mistake of assuming that the
1061                  * relocations were valid.
1062                  */
1063                 for (j = 0; j < exec[i].relocation_count; j++) {
1064                         if (__copy_to_user(&user_relocs[j].presumed_offset,
1065                                            &invalid_offset,
1066                                            sizeof(invalid_offset))) {
1067                                 ret = -EFAULT;
1068                                 mutex_lock(&dev->struct_mutex);
1069                                 goto err;
1070                         }
1071                 }
1072
1073                 reloc_offset[i] = total;
1074                 total += exec[i].relocation_count;
1075         }
1076
1077         ret = i915_mutex_lock_interruptible(dev);
1078         if (ret) {
1079                 mutex_lock(&dev->struct_mutex);
1080                 goto err;
1081         }
1082
1083         /* reacquire the objects */
1084         eb_reset(eb);
1085         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1086         if (ret)
1087                 goto err;
1088
1089         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1090         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1091                                           &need_relocs);
1092         if (ret)
1093                 goto err;
1094
1095         list_for_each_entry(vma, &eb->vmas, exec_list) {
1096                 int offset = vma->exec_entry - exec;
1097                 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
1098                                                             reloc + reloc_offset[offset]);
1099                 if (ret)
1100                         goto err;
1101         }
1102
1103         /* Leave the user relocations as are, this is the painfully slow path,
1104          * and we want to avoid the complication of dropping the lock whilst
1105          * having buffers reserved in the aperture and so causing spurious
1106          * ENOSPC for random operations.
1107          */
1108
1109 err:
1110         drm_free_large(reloc);
1111         drm_free_large(reloc_offset);
1112         return ret;
1113 }
1114
1115 static unsigned int eb_other_engines(struct drm_i915_gem_request *req)
1116 {
1117         unsigned int mask;
1118
1119         mask = ~intel_engine_flag(req->engine) & I915_BO_ACTIVE_MASK;
1120         mask <<= I915_BO_ACTIVE_SHIFT;
1121
1122         return mask;
1123 }
1124
1125 static int
1126 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
1127                                 struct list_head *vmas)
1128 {
1129         const unsigned int other_rings = eb_other_engines(req);
1130         struct i915_vma *vma;
1131         int ret;
1132
1133         list_for_each_entry(vma, vmas, exec_list) {
1134                 struct drm_i915_gem_object *obj = vma->obj;
1135
1136                 if (obj->flags & other_rings) {
1137                         ret = i915_gem_object_sync(obj, req);
1138                         if (ret)
1139                                 return ret;
1140                 }
1141
1142                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
1143                         i915_gem_clflush_object(obj, false);
1144         }
1145
1146         /* Unconditionally flush any chipset caches (for streaming writes). */
1147         i915_gem_chipset_flush(req->engine->i915);
1148
1149         /* Unconditionally invalidate GPU caches and TLBs. */
1150         return req->engine->emit_flush(req, EMIT_INVALIDATE);
1151 }
1152
1153 static bool
1154 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1155 {
1156         if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
1157                 return false;
1158
1159         /* Kernel clipping was a DRI1 misfeature */
1160         if (exec->num_cliprects || exec->cliprects_ptr)
1161                 return false;
1162
1163         if (exec->DR4 == 0xffffffff) {
1164                 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1165                 exec->DR4 = 0;
1166         }
1167         if (exec->DR1 || exec->DR4)
1168                 return false;
1169
1170         if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1171                 return false;
1172
1173         return true;
1174 }
1175
1176 static int
1177 validate_exec_list(struct drm_device *dev,
1178                    struct drm_i915_gem_exec_object2 *exec,
1179                    int count)
1180 {
1181         unsigned relocs_total = 0;
1182         unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1183         unsigned invalid_flags;
1184         int i;
1185
1186         /* INTERNAL flags must not overlap with external ones */
1187         BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1188
1189         invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1190         if (USES_FULL_PPGTT(dev))
1191                 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1192
1193         for (i = 0; i < count; i++) {
1194                 char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr);
1195                 int length; /* limited by fault_in_pages_readable() */
1196
1197                 if (exec[i].flags & invalid_flags)
1198                         return -EINVAL;
1199
1200                 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1201                  * any non-page-aligned or non-canonical addresses.
1202                  */
1203                 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1204                         if (exec[i].offset !=
1205                             gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1206                                 return -EINVAL;
1207
1208                         /* From drm_mm perspective address space is continuous,
1209                          * so from this point we're always using non-canonical
1210                          * form internally.
1211                          */
1212                         exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1213                 }
1214
1215                 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1216                         return -EINVAL;
1217
1218                 /* pad_to_size was once a reserved field, so sanitize it */
1219                 if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) {
1220                         if (offset_in_page(exec[i].pad_to_size))
1221                                 return -EINVAL;
1222                 } else {
1223                         exec[i].pad_to_size = 0;
1224                 }
1225
1226                 /* First check for malicious input causing overflow in
1227                  * the worst case where we need to allocate the entire
1228                  * relocation tree as a single array.
1229                  */
1230                 if (exec[i].relocation_count > relocs_max - relocs_total)
1231                         return -EINVAL;
1232                 relocs_total += exec[i].relocation_count;
1233
1234                 length = exec[i].relocation_count *
1235                         sizeof(struct drm_i915_gem_relocation_entry);
1236                 /*
1237                  * We must check that the entire relocation array is safe
1238                  * to read, but since we may need to update the presumed
1239                  * offsets during execution, check for full write access.
1240                  */
1241                 if (!access_ok(VERIFY_WRITE, ptr, length))
1242                         return -EFAULT;
1243
1244                 if (likely(!i915.prefault_disable)) {
1245                         if (fault_in_multipages_readable(ptr, length))
1246                                 return -EFAULT;
1247                 }
1248         }
1249
1250         return 0;
1251 }
1252
1253 static struct i915_gem_context *
1254 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1255                           struct intel_engine_cs *engine, const u32 ctx_id)
1256 {
1257         struct i915_gem_context *ctx = NULL;
1258         struct i915_ctx_hang_stats *hs;
1259
1260         if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1261                 return ERR_PTR(-EINVAL);
1262
1263         ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1264         if (IS_ERR(ctx))
1265                 return ctx;
1266
1267         hs = &ctx->hang_stats;
1268         if (hs->banned) {
1269                 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1270                 return ERR_PTR(-EIO);
1271         }
1272
1273         return ctx;
1274 }
1275
1276 void i915_vma_move_to_active(struct i915_vma *vma,
1277                              struct drm_i915_gem_request *req,
1278                              unsigned int flags)
1279 {
1280         struct drm_i915_gem_object *obj = vma->obj;
1281         const unsigned int idx = req->engine->id;
1282
1283         GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1284
1285         obj->dirty = 1; /* be paranoid  */
1286
1287         /* Add a reference if we're newly entering the active list.
1288          * The order in which we add operations to the retirement queue is
1289          * vital here: mark_active adds to the start of the callback list,
1290          * such that subsequent callbacks are called first. Therefore we
1291          * add the active reference first and queue for it to be dropped
1292          * *last*.
1293          */
1294         if (!i915_gem_object_is_active(obj))
1295                 i915_gem_object_get(obj);
1296         i915_gem_object_set_active(obj, idx);
1297         i915_gem_active_set(&obj->last_read[idx], req);
1298
1299         if (flags & EXEC_OBJECT_WRITE) {
1300                 i915_gem_active_set(&obj->last_write, req);
1301
1302                 intel_fb_obj_invalidate(obj, ORIGIN_CS);
1303
1304                 /* update for the implicit flush after a batch */
1305                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1306         }
1307
1308         if (flags & EXEC_OBJECT_NEEDS_FENCE) {
1309                 i915_gem_active_set(&obj->last_fence, req);
1310                 if (flags & __EXEC_OBJECT_HAS_FENCE) {
1311                         struct drm_i915_private *dev_priv = req->i915;
1312
1313                         list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1314                                        &dev_priv->mm.fence_list);
1315                 }
1316         }
1317
1318         i915_vma_set_active(vma, idx);
1319         i915_gem_active_set(&vma->last_read[idx], req);
1320         list_move_tail(&vma->vm_link, &vma->vm->active_list);
1321 }
1322
1323 static void eb_export_fence(struct drm_i915_gem_object *obj,
1324                             struct drm_i915_gem_request *req,
1325                             unsigned int flags)
1326 {
1327         struct reservation_object *resv;
1328
1329         resv = i915_gem_object_get_dmabuf_resv(obj);
1330         if (!resv)
1331                 return;
1332
1333         /* Ignore errors from failing to allocate the new fence, we can't
1334          * handle an error right now. Worst case should be missed
1335          * synchronisation leading to rendering corruption.
1336          */
1337         ww_mutex_lock(&resv->lock, NULL);
1338         if (flags & EXEC_OBJECT_WRITE)
1339                 reservation_object_add_excl_fence(resv, &req->fence);
1340         else if (reservation_object_reserve_shared(resv) == 0)
1341                 reservation_object_add_shared_fence(resv, &req->fence);
1342         ww_mutex_unlock(&resv->lock);
1343 }
1344
1345 static void
1346 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1347                                    struct drm_i915_gem_request *req)
1348 {
1349         struct i915_vma *vma;
1350
1351         list_for_each_entry(vma, vmas, exec_list) {
1352                 struct drm_i915_gem_object *obj = vma->obj;
1353                 u32 old_read = obj->base.read_domains;
1354                 u32 old_write = obj->base.write_domain;
1355
1356                 obj->base.write_domain = obj->base.pending_write_domain;
1357                 if (obj->base.write_domain)
1358                         vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
1359                 else
1360                         obj->base.pending_read_domains |= obj->base.read_domains;
1361                 obj->base.read_domains = obj->base.pending_read_domains;
1362
1363                 i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
1364                 eb_export_fence(obj, req, vma->exec_entry->flags);
1365                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1366         }
1367 }
1368
1369 static int
1370 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1371 {
1372         struct intel_ring *ring = req->ring;
1373         int ret, i;
1374
1375         if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1376                 DRM_DEBUG("sol reset is gen7/rcs only\n");
1377                 return -EINVAL;
1378         }
1379
1380         ret = intel_ring_begin(req, 4 * 3);
1381         if (ret)
1382                 return ret;
1383
1384         for (i = 0; i < 4; i++) {
1385                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1386                 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1387                 intel_ring_emit(ring, 0);
1388         }
1389
1390         intel_ring_advance(ring);
1391
1392         return 0;
1393 }
1394
1395 static struct i915_vma *
1396 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1397                           struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1398                           struct drm_i915_gem_object *batch_obj,
1399                           struct eb_vmas *eb,
1400                           u32 batch_start_offset,
1401                           u32 batch_len,
1402                           bool is_master)
1403 {
1404         struct drm_i915_gem_object *shadow_batch_obj;
1405         struct i915_vma *vma;
1406         int ret;
1407
1408         shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1409                                                    PAGE_ALIGN(batch_len));
1410         if (IS_ERR(shadow_batch_obj))
1411                 return ERR_CAST(shadow_batch_obj);
1412
1413         ret = intel_engine_cmd_parser(engine,
1414                                       batch_obj,
1415                                       shadow_batch_obj,
1416                                       batch_start_offset,
1417                                       batch_len,
1418                                       is_master);
1419         if (ret) {
1420                 if (ret == -EACCES) /* unhandled chained batch */
1421                         vma = NULL;
1422                 else
1423                         vma = ERR_PTR(ret);
1424                 goto out;
1425         }
1426
1427         vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1428         if (IS_ERR(vma))
1429                 goto out;
1430
1431         memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1432
1433         vma->exec_entry = shadow_exec_entry;
1434         vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1435         i915_gem_object_get(shadow_batch_obj);
1436         list_add_tail(&vma->exec_list, &eb->vmas);
1437
1438 out:
1439         i915_gem_object_unpin_pages(shadow_batch_obj);
1440         return vma;
1441 }
1442
1443 static int
1444 execbuf_submit(struct i915_execbuffer_params *params,
1445                struct drm_i915_gem_execbuffer2 *args,
1446                struct list_head *vmas)
1447 {
1448         struct drm_i915_private *dev_priv = params->request->i915;
1449         u64 exec_start, exec_len;
1450         int instp_mode;
1451         u32 instp_mask;
1452         int ret;
1453
1454         ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1455         if (ret)
1456                 return ret;
1457
1458         ret = i915_switch_context(params->request);
1459         if (ret)
1460                 return ret;
1461
1462         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1463         instp_mask = I915_EXEC_CONSTANTS_MASK;
1464         switch (instp_mode) {
1465         case I915_EXEC_CONSTANTS_REL_GENERAL:
1466         case I915_EXEC_CONSTANTS_ABSOLUTE:
1467         case I915_EXEC_CONSTANTS_REL_SURFACE:
1468                 if (instp_mode != 0 && params->engine->id != RCS) {
1469                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1470                         return -EINVAL;
1471                 }
1472
1473                 if (instp_mode != dev_priv->relative_constants_mode) {
1474                         if (INTEL_INFO(dev_priv)->gen < 4) {
1475                                 DRM_DEBUG("no rel constants on pre-gen4\n");
1476                                 return -EINVAL;
1477                         }
1478
1479                         if (INTEL_INFO(dev_priv)->gen > 5 &&
1480                             instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1481                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1482                                 return -EINVAL;
1483                         }
1484
1485                         /* The HW changed the meaning on this bit on gen6 */
1486                         if (INTEL_INFO(dev_priv)->gen >= 6)
1487                                 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1488                 }
1489                 break;
1490         default:
1491                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1492                 return -EINVAL;
1493         }
1494
1495         if (params->engine->id == RCS &&
1496             instp_mode != dev_priv->relative_constants_mode) {
1497                 struct intel_ring *ring = params->request->ring;
1498
1499                 ret = intel_ring_begin(params->request, 4);
1500                 if (ret)
1501                         return ret;
1502
1503                 intel_ring_emit(ring, MI_NOOP);
1504                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1505                 intel_ring_emit_reg(ring, INSTPM);
1506                 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1507                 intel_ring_advance(ring);
1508
1509                 dev_priv->relative_constants_mode = instp_mode;
1510         }
1511
1512         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1513                 ret = i915_reset_gen7_sol_offsets(params->request);
1514                 if (ret)
1515                         return ret;
1516         }
1517
1518         exec_len   = args->batch_len;
1519         exec_start = params->batch->node.start +
1520                      params->args_batch_start_offset;
1521
1522         if (exec_len == 0)
1523                 exec_len = params->batch->size;
1524
1525         ret = params->engine->emit_bb_start(params->request,
1526                                             exec_start, exec_len,
1527                                             params->dispatch_flags);
1528         if (ret)
1529                 return ret;
1530
1531         trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1532
1533         i915_gem_execbuffer_move_to_active(vmas, params->request);
1534
1535         return 0;
1536 }
1537
1538 /**
1539  * Find one BSD ring to dispatch the corresponding BSD command.
1540  * The engine index is returned.
1541  */
1542 static unsigned int
1543 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1544                          struct drm_file *file)
1545 {
1546         struct drm_i915_file_private *file_priv = file->driver_priv;
1547
1548         /* Check whether the file_priv has already selected one ring. */
1549         if ((int)file_priv->bsd_engine < 0) {
1550                 /* If not, use the ping-pong mechanism to select one. */
1551                 mutex_lock(&dev_priv->drm.struct_mutex);
1552                 file_priv->bsd_engine = dev_priv->mm.bsd_engine_dispatch_index;
1553                 dev_priv->mm.bsd_engine_dispatch_index ^= 1;
1554                 mutex_unlock(&dev_priv->drm.struct_mutex);
1555         }
1556
1557         return file_priv->bsd_engine;
1558 }
1559
1560 #define I915_USER_RINGS (4)
1561
1562 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1563         [I915_EXEC_DEFAULT]     = RCS,
1564         [I915_EXEC_RENDER]      = RCS,
1565         [I915_EXEC_BLT]         = BCS,
1566         [I915_EXEC_BSD]         = VCS,
1567         [I915_EXEC_VEBOX]       = VECS
1568 };
1569
1570 static struct intel_engine_cs *
1571 eb_select_engine(struct drm_i915_private *dev_priv,
1572                  struct drm_file *file,
1573                  struct drm_i915_gem_execbuffer2 *args)
1574 {
1575         unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1576         struct intel_engine_cs *engine;
1577
1578         if (user_ring_id > I915_USER_RINGS) {
1579                 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1580                 return NULL;
1581         }
1582
1583         if ((user_ring_id != I915_EXEC_BSD) &&
1584             ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1585                 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1586                           "bsd dispatch flags: %d\n", (int)(args->flags));
1587                 return NULL;
1588         }
1589
1590         if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1591                 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1592
1593                 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1594                         bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1595                 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1596                            bsd_idx <= I915_EXEC_BSD_RING2) {
1597                         bsd_idx >>= I915_EXEC_BSD_SHIFT;
1598                         bsd_idx--;
1599                 } else {
1600                         DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1601                                   bsd_idx);
1602                         return NULL;
1603                 }
1604
1605                 engine = &dev_priv->engine[_VCS(bsd_idx)];
1606         } else {
1607                 engine = &dev_priv->engine[user_ring_map[user_ring_id]];
1608         }
1609
1610         if (!intel_engine_initialized(engine)) {
1611                 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1612                 return NULL;
1613         }
1614
1615         return engine;
1616 }
1617
1618 static int
1619 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1620                        struct drm_file *file,
1621                        struct drm_i915_gem_execbuffer2 *args,
1622                        struct drm_i915_gem_exec_object2 *exec)
1623 {
1624         struct drm_i915_private *dev_priv = to_i915(dev);
1625         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1626         struct eb_vmas *eb;
1627         struct drm_i915_gem_exec_object2 shadow_exec_entry;
1628         struct intel_engine_cs *engine;
1629         struct i915_gem_context *ctx;
1630         struct i915_address_space *vm;
1631         struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1632         struct i915_execbuffer_params *params = &params_master;
1633         const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1634         u32 dispatch_flags;
1635         int ret;
1636         bool need_relocs;
1637
1638         if (!i915_gem_check_execbuffer(args))
1639                 return -EINVAL;
1640
1641         ret = validate_exec_list(dev, exec, args->buffer_count);
1642         if (ret)
1643                 return ret;
1644
1645         dispatch_flags = 0;
1646         if (args->flags & I915_EXEC_SECURE) {
1647                 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1648                     return -EPERM;
1649
1650                 dispatch_flags |= I915_DISPATCH_SECURE;
1651         }
1652         if (args->flags & I915_EXEC_IS_PINNED)
1653                 dispatch_flags |= I915_DISPATCH_PINNED;
1654
1655         engine = eb_select_engine(dev_priv, file, args);
1656         if (!engine)
1657                 return -EINVAL;
1658
1659         if (args->buffer_count < 1) {
1660                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1661                 return -EINVAL;
1662         }
1663
1664         if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1665                 if (!HAS_RESOURCE_STREAMER(dev)) {
1666                         DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1667                         return -EINVAL;
1668                 }
1669                 if (engine->id != RCS) {
1670                         DRM_DEBUG("RS is not available on %s\n",
1671                                  engine->name);
1672                         return -EINVAL;
1673                 }
1674
1675                 dispatch_flags |= I915_DISPATCH_RS;
1676         }
1677
1678         /* Take a local wakeref for preparing to dispatch the execbuf as
1679          * we expect to access the hardware fairly frequently in the
1680          * process. Upon first dispatch, we acquire another prolonged
1681          * wakeref that we hold until the GPU has been idle for at least
1682          * 100ms.
1683          */
1684         intel_runtime_pm_get(dev_priv);
1685
1686         ret = i915_mutex_lock_interruptible(dev);
1687         if (ret)
1688                 goto pre_mutex_err;
1689
1690         ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1691         if (IS_ERR(ctx)) {
1692                 mutex_unlock(&dev->struct_mutex);
1693                 ret = PTR_ERR(ctx);
1694                 goto pre_mutex_err;
1695         }
1696
1697         i915_gem_context_get(ctx);
1698
1699         if (ctx->ppgtt)
1700                 vm = &ctx->ppgtt->base;
1701         else
1702                 vm = &ggtt->base;
1703
1704         memset(&params_master, 0x00, sizeof(params_master));
1705
1706         eb = eb_create(dev_priv, args);
1707         if (eb == NULL) {
1708                 i915_gem_context_put(ctx);
1709                 mutex_unlock(&dev->struct_mutex);
1710                 ret = -ENOMEM;
1711                 goto pre_mutex_err;
1712         }
1713
1714         /* Look up object handles */
1715         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1716         if (ret)
1717                 goto err;
1718
1719         /* take note of the batch buffer before we might reorder the lists */
1720         params->batch = eb_get_batch(eb);
1721
1722         /* Move the objects en-masse into the GTT, evicting if necessary. */
1723         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1724         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1725                                           &need_relocs);
1726         if (ret)
1727                 goto err;
1728
1729         /* The objects are in their final locations, apply the relocations. */
1730         if (need_relocs)
1731                 ret = i915_gem_execbuffer_relocate(eb);
1732         if (ret) {
1733                 if (ret == -EFAULT) {
1734                         ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1735                                                                 engine,
1736                                                                 eb, exec, ctx);
1737                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1738                 }
1739                 if (ret)
1740                         goto err;
1741         }
1742
1743         /* Set the pending read domains for the batch buffer to COMMAND */
1744         if (params->batch->obj->base.pending_write_domain) {
1745                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1746                 ret = -EINVAL;
1747                 goto err;
1748         }
1749
1750         params->args_batch_start_offset = args->batch_start_offset;
1751         if (intel_engine_needs_cmd_parser(engine) && args->batch_len) {
1752                 struct i915_vma *vma;
1753
1754                 vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry,
1755                                                 params->batch->obj,
1756                                                 eb,
1757                                                 args->batch_start_offset,
1758                                                 args->batch_len,
1759                                                 drm_is_current_master(file));
1760                 if (IS_ERR(vma)) {
1761                         ret = PTR_ERR(vma);
1762                         goto err;
1763                 }
1764
1765                 if (vma) {
1766                         /*
1767                          * Batch parsed and accepted:
1768                          *
1769                          * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1770                          * bit from MI_BATCH_BUFFER_START commands issued in
1771                          * the dispatch_execbuffer implementations. We
1772                          * specifically don't want that set on batches the
1773                          * command parser has accepted.
1774                          */
1775                         dispatch_flags |= I915_DISPATCH_SECURE;
1776                         params->args_batch_start_offset = 0;
1777                         params->batch = vma;
1778                 }
1779         }
1780
1781         params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1782
1783         /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1784          * batch" bit. Hence we need to pin secure batches into the global gtt.
1785          * hsw should have this fixed, but bdw mucks it up again. */
1786         if (dispatch_flags & I915_DISPATCH_SECURE) {
1787                 struct drm_i915_gem_object *obj = params->batch->obj;
1788                 struct i915_vma *vma;
1789
1790                 /*
1791                  * So on first glance it looks freaky that we pin the batch here
1792                  * outside of the reservation loop. But:
1793                  * - The batch is already pinned into the relevant ppgtt, so we
1794                  *   already have the backing storage fully allocated.
1795                  * - No other BO uses the global gtt (well contexts, but meh),
1796                  *   so we don't really have issues with multiple objects not
1797                  *   fitting due to fragmentation.
1798                  * So this is actually safe.
1799                  */
1800                 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
1801                 if (IS_ERR(vma)) {
1802                         ret = PTR_ERR(vma);
1803                         goto err;
1804                 }
1805
1806                 params->batch = vma;
1807         }
1808
1809         /* Allocate a request for this batch buffer nice and early. */
1810         params->request = i915_gem_request_alloc(engine, ctx);
1811         if (IS_ERR(params->request)) {
1812                 ret = PTR_ERR(params->request);
1813                 goto err_batch_unpin;
1814         }
1815
1816         /* Whilst this request exists, batch_obj will be on the
1817          * active_list, and so will hold the active reference. Only when this
1818          * request is retired will the the batch_obj be moved onto the
1819          * inactive_list and lose its active reference. Hence we do not need
1820          * to explicitly hold another reference here.
1821          */
1822         params->request->batch = params->batch;
1823
1824         ret = i915_gem_request_add_to_client(params->request, file);
1825         if (ret)
1826                 goto err_request;
1827
1828         /*
1829          * Save assorted stuff away to pass through to *_submission().
1830          * NB: This data should be 'persistent' and not local as it will
1831          * kept around beyond the duration of the IOCTL once the GPU
1832          * scheduler arrives.
1833          */
1834         params->dev                     = dev;
1835         params->file                    = file;
1836         params->engine                    = engine;
1837         params->dispatch_flags          = dispatch_flags;
1838         params->ctx                     = ctx;
1839
1840         ret = execbuf_submit(params, args, &eb->vmas);
1841 err_request:
1842         __i915_add_request(params->request, ret == 0);
1843
1844 err_batch_unpin:
1845         /*
1846          * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1847          * batch vma for correctness. For less ugly and less fragility this
1848          * needs to be adjusted to also track the ggtt batch vma properly as
1849          * active.
1850          */
1851         if (dispatch_flags & I915_DISPATCH_SECURE)
1852                 i915_vma_unpin(params->batch);
1853 err:
1854         /* the request owns the ref now */
1855         i915_gem_context_put(ctx);
1856         eb_destroy(eb);
1857
1858         mutex_unlock(&dev->struct_mutex);
1859
1860 pre_mutex_err:
1861         /* intel_gpu_busy should also get a ref, so it will free when the device
1862          * is really idle. */
1863         intel_runtime_pm_put(dev_priv);
1864         return ret;
1865 }
1866
1867 /*
1868  * Legacy execbuffer just creates an exec2 list from the original exec object
1869  * list array and passes it to the real function.
1870  */
1871 int
1872 i915_gem_execbuffer(struct drm_device *dev, void *data,
1873                     struct drm_file *file)
1874 {
1875         struct drm_i915_gem_execbuffer *args = data;
1876         struct drm_i915_gem_execbuffer2 exec2;
1877         struct drm_i915_gem_exec_object *exec_list = NULL;
1878         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1879         int ret, i;
1880
1881         if (args->buffer_count < 1) {
1882                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1883                 return -EINVAL;
1884         }
1885
1886         /* Copy in the exec list from userland */
1887         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1888         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1889         if (exec_list == NULL || exec2_list == NULL) {
1890                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1891                           args->buffer_count);
1892                 drm_free_large(exec_list);
1893                 drm_free_large(exec2_list);
1894                 return -ENOMEM;
1895         }
1896         ret = copy_from_user(exec_list,
1897                              u64_to_user_ptr(args->buffers_ptr),
1898                              sizeof(*exec_list) * args->buffer_count);
1899         if (ret != 0) {
1900                 DRM_DEBUG("copy %d exec entries failed %d\n",
1901                           args->buffer_count, ret);
1902                 drm_free_large(exec_list);
1903                 drm_free_large(exec2_list);
1904                 return -EFAULT;
1905         }
1906
1907         for (i = 0; i < args->buffer_count; i++) {
1908                 exec2_list[i].handle = exec_list[i].handle;
1909                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1910                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1911                 exec2_list[i].alignment = exec_list[i].alignment;
1912                 exec2_list[i].offset = exec_list[i].offset;
1913                 if (INTEL_INFO(dev)->gen < 4)
1914                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1915                 else
1916                         exec2_list[i].flags = 0;
1917         }
1918
1919         exec2.buffers_ptr = args->buffers_ptr;
1920         exec2.buffer_count = args->buffer_count;
1921         exec2.batch_start_offset = args->batch_start_offset;
1922         exec2.batch_len = args->batch_len;
1923         exec2.DR1 = args->DR1;
1924         exec2.DR4 = args->DR4;
1925         exec2.num_cliprects = args->num_cliprects;
1926         exec2.cliprects_ptr = args->cliprects_ptr;
1927         exec2.flags = I915_EXEC_RENDER;
1928         i915_execbuffer2_set_context_id(exec2, 0);
1929
1930         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1931         if (!ret) {
1932                 struct drm_i915_gem_exec_object __user *user_exec_list =
1933                         u64_to_user_ptr(args->buffers_ptr);
1934
1935                 /* Copy the new buffer offsets back to the user's exec list. */
1936                 for (i = 0; i < args->buffer_count; i++) {
1937                         exec2_list[i].offset =
1938                                 gen8_canonical_addr(exec2_list[i].offset);
1939                         ret = __copy_to_user(&user_exec_list[i].offset,
1940                                              &exec2_list[i].offset,
1941                                              sizeof(user_exec_list[i].offset));
1942                         if (ret) {
1943                                 ret = -EFAULT;
1944                                 DRM_DEBUG("failed to copy %d exec entries "
1945                                           "back to user (%d)\n",
1946                                           args->buffer_count, ret);
1947                                 break;
1948                         }
1949                 }
1950         }
1951
1952         drm_free_large(exec_list);
1953         drm_free_large(exec2_list);
1954         return ret;
1955 }
1956
1957 int
1958 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1959                      struct drm_file *file)
1960 {
1961         struct drm_i915_gem_execbuffer2 *args = data;
1962         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1963         int ret;
1964
1965         if (args->buffer_count < 1 ||
1966             args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1967                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1968                 return -EINVAL;
1969         }
1970
1971         if (args->rsvd2 != 0) {
1972                 DRM_DEBUG("dirty rvsd2 field\n");
1973                 return -EINVAL;
1974         }
1975
1976         exec2_list = drm_malloc_gfp(args->buffer_count,
1977                                     sizeof(*exec2_list),
1978                                     GFP_TEMPORARY);
1979         if (exec2_list == NULL) {
1980                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1981                           args->buffer_count);
1982                 return -ENOMEM;
1983         }
1984         ret = copy_from_user(exec2_list,
1985                              u64_to_user_ptr(args->buffers_ptr),
1986                              sizeof(*exec2_list) * args->buffer_count);
1987         if (ret != 0) {
1988                 DRM_DEBUG("copy %d exec entries failed %d\n",
1989                           args->buffer_count, ret);
1990                 drm_free_large(exec2_list);
1991                 return -EFAULT;
1992         }
1993
1994         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1995         if (!ret) {
1996                 /* Copy the new buffer offsets back to the user's exec list. */
1997                 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1998                                    u64_to_user_ptr(args->buffers_ptr);
1999                 int i;
2000
2001                 for (i = 0; i < args->buffer_count; i++) {
2002                         exec2_list[i].offset =
2003                                 gen8_canonical_addr(exec2_list[i].offset);
2004                         ret = __copy_to_user(&user_exec_list[i].offset,
2005                                              &exec2_list[i].offset,
2006                                              sizeof(user_exec_list[i].offset));
2007                         if (ret) {
2008                                 ret = -EFAULT;
2009                                 DRM_DEBUG("failed to copy %d exec entries "
2010                                           "back to user\n",
2011                                           args->buffer_count);
2012                                 break;
2013                         }
2014                 }
2015         }
2016
2017         drm_free_large(exec2_list);
2018         return ret;
2019 }