drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 #define GEN6_PPGTT_PD_ENTRIES 512
  32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  33 typedef uint64_t gen8_gtt_pte_t;
  34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  35
  36 /* PPGTT stuff */
  37 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  38 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  39
  40 #define GEN6_PDE_VALID                  (1 << 0)
  41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  42 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  43
  44 #define GEN6_PTE_VALID                  (1 << 0)
  45 #define GEN6_PTE_UNCACHED               (1 << 1)
  46 #define HSW_PTE_UNCACHED                (0)
  47 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  48 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  49 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  50 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  51
  52 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  53  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  54  */
  55 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  56                                          (((bits) & 0x8) << (11 - 3)))
  57 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  58 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  59 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  60 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  61
  62 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  63 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
  64 #define GEN8_LEGACY_PDPS                4
  65
  66 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  67 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  68 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  69 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  70
  71 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  72                                              enum i915_cache_level level,
  73                                              bool valid)
  74 {
  75         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  76         pte |= addr;
  77         if (level != I915_CACHE_NONE)
  78                 pte |= PPAT_CACHED_INDEX;
  79         else
  80                 pte |= PPAT_UNCACHED_INDEX;
  81         return pte;
  82 }
  83
  84 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
  85                                              dma_addr_t addr,
  86                                              enum i915_cache_level level)
  87 {
  88         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
  89         pde |= addr;
  90         if (level != I915_CACHE_NONE)
  91                 pde |= PPAT_CACHED_PDE_INDEX;
  92         else
  93                 pde |= PPAT_UNCACHED_INDEX;
  94         return pde;
  95 }
  96
  97 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
  98                                      enum i915_cache_level level,
  99                                      bool valid)
 100 {
 101         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 102         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 103
 104         switch (level) {
 105         case I915_CACHE_L3_LLC:
 106         case I915_CACHE_LLC:
 107                 pte |= GEN6_PTE_CACHE_LLC;
 108                 break;
 109         case I915_CACHE_NONE:
 110                 pte |= GEN6_PTE_UNCACHED;
 111                 break;
 112         default:
 113                 WARN_ON(1);
 114         }
 115
 116         return pte;
 117 }
 118
 119 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 120                                      enum i915_cache_level level,
 121                                      bool valid)
 122 {
 123         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 124         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 125
 126         switch (level) {
 127         case I915_CACHE_L3_LLC:
 128                 pte |= GEN7_PTE_CACHE_L3_LLC;
 129                 break;
 130         case I915_CACHE_LLC:
 131                 pte |= GEN6_PTE_CACHE_LLC;
 132                 break;
 133         case I915_CACHE_NONE:
 134                 pte |= GEN6_PTE_UNCACHED;
 135                 break;
 136         default:
 137                 WARN_ON(1);
 138         }
 139
 140         return pte;
 141 }
 142
 143 #define BYT_PTE_WRITEABLE               (1 << 1)
 144 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 145
 146 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 147                                      enum i915_cache_level level,
 148                                      bool valid)
 149 {
 150         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 151         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 152
 153         /* Mark the page as writeable.  Other platforms don't have a
 154          * setting for read-only/writable, so this matches that behavior.
 155          */
 156         pte |= BYT_PTE_WRITEABLE;
 157
 158         if (level != I915_CACHE_NONE)
 159                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 160
 161         return pte;
 162 }
 163
 164 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 165                                      enum i915_cache_level level,
 166                                      bool valid)
 167 {
 168         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 169         pte |= HSW_PTE_ADDR_ENCODE(addr);
 170
 171         if (level != I915_CACHE_NONE)
 172                 pte |= HSW_WB_LLC_AGE3;
 173
 174         return pte;
 175 }
 176
 177 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 178                                       enum i915_cache_level level,
 179                                       bool valid)
 180 {
 181         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 182         pte |= HSW_PTE_ADDR_ENCODE(addr);
 183
 184         switch (level) {
 185         case I915_CACHE_NONE:
 186                 break;
 187         case I915_CACHE_WT:
 188                 pte |= HSW_WT_ELLC_LLC_AGE0;
 189                 break;
 190         default:
 191                 pte |= HSW_WB_ELLC_LLC_AGE0;
 192                 break;
 193         }
 194
 195         return pte;
 196 }
 197
 198 /* Broadwell Page Directory Pointer Descriptors */
 199 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
 200                            uint64_t val)
 201 {
 202         int ret;
 203
 204         BUG_ON(entry >= 4);
 205
 206         ret = intel_ring_begin(ring, 6);
 207         if (ret)
 208                 return ret;
 209
 210         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 211         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 212         intel_ring_emit(ring, (u32)(val >> 32));
 213         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 214         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 215         intel_ring_emit(ring, (u32)(val));
 216         intel_ring_advance(ring);
 217
 218         return 0;
 219 }
 220
 221 static int gen8_ppgtt_enable(struct drm_device *dev)
 222 {
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct intel_ring_buffer *ring;
 225         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 226         int i, j, ret;
 227
 228         /* bit of a hack to find the actual last used pd */
 229         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 230
 231         for_each_ring(ring, dev_priv, j) {
 232                 I915_WRITE(RING_MODE_GEN7(ring),
 233                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 234         }
 235
 236         for (i = used_pd - 1; i >= 0; i--) {
 237                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 238                 for_each_ring(ring, dev_priv, j) {
 239                         ret = gen8_write_pdp(ring, i, addr);
 240                         if (ret)
 241                                 goto err_out;
 242                 }
 243         }
 244         return 0;
 245
 246 err_out:
 247         for_each_ring(ring, dev_priv, j)
 248                 I915_WRITE(RING_MODE_GEN7(ring),
 249                            _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
 250         return ret;
 251 }
 252
 253 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 254                                    unsigned first_entry,
 255                                    unsigned num_entries,
 256                                    bool use_scratch)
 257 {
 258         struct i915_hw_ppgtt *ppgtt =
 259                 container_of(vm, struct i915_hw_ppgtt, base);
 260         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 261         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 262         unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
 263         unsigned last_pte, i;
 264
 265         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 266                                       I915_CACHE_LLC, use_scratch);
 267
 268         while (num_entries) {
 269                 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
 270
 271                 last_pte = first_pte + num_entries;
 272                 if (last_pte > GEN8_PTES_PER_PAGE)
 273                         last_pte = GEN8_PTES_PER_PAGE;
 274
 275                 pt_vaddr = kmap_atomic(page_table);
 276
 277                 for (i = first_pte; i < last_pte; i++)
 278                         pt_vaddr[i] = scratch_pte;
 279
 280                 kunmap_atomic(pt_vaddr);
 281
 282                 num_entries -= last_pte - first_pte;
 283                 first_pte = 0;
 284                 act_pt++;
 285         }
 286 }
 287
 288 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 289                                       struct sg_table *pages,
 290                                       unsigned first_entry,
 291                                       enum i915_cache_level cache_level)
 292 {
 293         struct i915_hw_ppgtt *ppgtt =
 294                 container_of(vm, struct i915_hw_ppgtt, base);
 295         gen8_gtt_pte_t *pt_vaddr;
 296         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 297         unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
 298         struct sg_page_iter sg_iter;
 299
 300         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 301         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 302                 dma_addr_t page_addr;
 303
 304                 page_addr = sg_dma_address(sg_iter.sg) +
 305                                 (sg_iter.sg_pgoffset << PAGE_SHIFT);
 306                 pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
 307                                                     true);
 308                 if (++act_pte == GEN8_PTES_PER_PAGE) {
 309                         kunmap_atomic(pt_vaddr);
 310                         act_pt++;
 311                         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 312                         act_pte = 0;
 313
 314                 }
 315         }
 316         kunmap_atomic(pt_vaddr);
 317 }
 318
 319 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 320 {
 321         struct i915_hw_ppgtt *ppgtt =
 322                 container_of(vm, struct i915_hw_ppgtt, base);
 323         int i, j;
 324
 325         drm_mm_takedown(&vm->mm);
 326
 327         for (i = 0; i < ppgtt->num_pd_pages ; i++) {
 328                 if (ppgtt->pd_dma_addr[i]) {
 329                         pci_unmap_page(ppgtt->base.dev->pdev,
 330                                        ppgtt->pd_dma_addr[i],
 331                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 332
 333                         for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 334                                 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 335                                 if (addr)
 336                                         pci_unmap_page(ppgtt->base.dev->pdev,
 337                                                        addr,
 338                                                        PAGE_SIZE,
 339                                                        PCI_DMA_BIDIRECTIONAL);
 340
 341                         }
 342                 }
 343                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 344         }
 345
 346         __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
 347         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 348 }
 349
 350 /**
 351  * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
 352  * net effect resembling a 2-level page table in normal x86 terms. Each PDP
 353  * represents 1GB of memory
 354  * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
 355  *
 356  * TODO: Do something with the size parameter
 357  **/
 358 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 359 {
 360         struct page *pt_pages;
 361         int i, j, ret = -ENOMEM;
 362         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 363         const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 364
 365         if (size % (1<<30))
 366                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 367
 368         /* FIXME: split allocation into smaller pieces. For now we only ever do
 369          * this once, but with full PPGTT, the multiple contiguous allocations
 370          * will be bad.
 371          */
 372         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 373         if (!ppgtt->pd_pages)
 374                 return -ENOMEM;
 375
 376         pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
 377         if (!pt_pages) {
 378                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 379                 return -ENOMEM;
 380         }
 381
 382         ppgtt->gen8_pt_pages = pt_pages;
 383         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 384         ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 385         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 386         ppgtt->enable = gen8_ppgtt_enable;
 387         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 388         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 389         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 390         ppgtt->base.start = 0;
 391         ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 392
 393         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 394
 395         /*
 396          * - Create a mapping for the page directories.
 397          * - For each page directory:
 398          *      allocate space for page table mappings.
 399          *      map each page table
 400          */
 401         for (i = 0; i < max_pdp; i++) {
 402                 dma_addr_t temp;
 403                 temp = pci_map_page(ppgtt->base.dev->pdev,
 404                                     &ppgtt->pd_pages[i], 0,
 405                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 406                 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 407                         goto err_out;
 408
 409                 ppgtt->pd_dma_addr[i] = temp;
 410
 411                 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
 412                 if (!ppgtt->gen8_pt_dma_addr[i])
 413                         goto err_out;
 414
 415                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 416                         struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
 417                         temp = pci_map_page(ppgtt->base.dev->pdev,
 418                                             p, 0, PAGE_SIZE,
 419                                             PCI_DMA_BIDIRECTIONAL);
 420
 421                         if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 422                                 goto err_out;
 423
 424                         ppgtt->gen8_pt_dma_addr[i][j] = temp;
 425                 }
 426         }
 427
 428         /* For now, the PPGTT helper functions all require that the PDEs are
 429          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 430          * will never need to touch the PDEs again */
 431         for (i = 0; i < max_pdp; i++) {
 432                 gen8_ppgtt_pde_t *pd_vaddr;
 433                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 434                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 435                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 436                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 437                                                       I915_CACHE_LLC);
 438                 }
 439                 kunmap_atomic(pd_vaddr);
 440         }
 441
 442         ppgtt->base.clear_range(&ppgtt->base, 0,
 443                                 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
 444                                 true);
 445
 446         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 447                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 448         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 449                          ppgtt->num_pt_pages,
 450                          (ppgtt->num_pt_pages - num_pt_pages) +
 451                          size % (1<<30));
 452         return 0;
 453
 454 err_out:
 455         ppgtt->base.cleanup(&ppgtt->base);
 456         return ret;
 457 }
 458
 459 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 460 {
 461         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 462         gen6_gtt_pte_t __iomem *pd_addr;
 463         uint32_t pd_entry;
 464         int i;
 465
 466         WARN_ON(ppgtt->pd_offset & 0x3f);
 467         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 468                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 469         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 470                 dma_addr_t pt_addr;
 471
 472                 pt_addr = ppgtt->pt_dma_addr[i];
 473                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 474                 pd_entry |= GEN6_PDE_VALID;
 475
 476                 writel(pd_entry, pd_addr + i);
 477         }
 478         readl(pd_addr);
 479 }
 480
 481 static int gen6_ppgtt_enable(struct drm_device *dev)
 482 {
 483         drm_i915_private_t *dev_priv = dev->dev_private;
 484         uint32_t pd_offset;
 485         struct intel_ring_buffer *ring;
 486         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 487         int i;
 488
 489         BUG_ON(ppgtt->pd_offset & 0x3f);
 490
 491         gen6_write_pdes(ppgtt);
 492
 493         pd_offset = ppgtt->pd_offset;
 494         pd_offset /= 64; /* in cachelines, */
 495         pd_offset <<= 16;
 496
 497         if (INTEL_INFO(dev)->gen == 6) {
 498                 uint32_t ecochk, gab_ctl, ecobits;
 499
 500                 ecobits = I915_READ(GAC_ECO_BITS);
 501                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 502                                          ECOBITS_PPGTT_CACHE64B);
 503
 504                 gab_ctl = I915_READ(GAB_CTL);
 505                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 506
 507                 ecochk = I915_READ(GAM_ECOCHK);
 508                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 509                                        ECOCHK_PPGTT_CACHE64B);
 510                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 511         } else if (INTEL_INFO(dev)->gen >= 7) {
 512                 uint32_t ecochk, ecobits;
 513
 514                 ecobits = I915_READ(GAC_ECO_BITS);
 515                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 516
 517                 ecochk = I915_READ(GAM_ECOCHK);
 518                 if (IS_HASWELL(dev)) {
 519                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 520                 } else {
 521                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 522                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 523                 }
 524                 I915_WRITE(GAM_ECOCHK, ecochk);
 525                 /* GFX_MODE is per-ring on gen7+ */
 526         }
 527
 528         for_each_ring(ring, dev_priv, i) {
 529                 if (INTEL_INFO(dev)->gen >= 7)
 530                         I915_WRITE(RING_MODE_GEN7(ring),
 531                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 532
 533                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 534                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 535         }
 536         return 0;
 537 }
 538
 539 /* PPGTT support for Sandybdrige/Gen6 and later */
 540 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 541                                    unsigned first_entry,
 542                                    unsigned num_entries,
 543                                    bool use_scratch)
 544 {
 545         struct i915_hw_ppgtt *ppgtt =
 546                 container_of(vm, struct i915_hw_ppgtt, base);
 547         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 548         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 549         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 550         unsigned last_pte, i;
 551
 552         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 553
 554         while (num_entries) {
 555                 last_pte = first_pte + num_entries;
 556                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 557                         last_pte = I915_PPGTT_PT_ENTRIES;
 558
 559                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 560
 561                 for (i = first_pte; i < last_pte; i++)
 562                         pt_vaddr[i] = scratch_pte;
 563
 564                 kunmap_atomic(pt_vaddr);
 565
 566                 num_entries -= last_pte - first_pte;
 567                 first_pte = 0;
 568                 act_pt++;
 569         }
 570 }
 571
 572 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 573                                       struct sg_table *pages,
 574                                       unsigned first_entry,
 575                                       enum i915_cache_level cache_level)
 576 {
 577         struct i915_hw_ppgtt *ppgtt =
 578                 container_of(vm, struct i915_hw_ppgtt, base);
 579         gen6_gtt_pte_t *pt_vaddr;
 580         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 581         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 582         struct sg_page_iter sg_iter;
 583
 584         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 585         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 586                 dma_addr_t page_addr;
 587
 588                 page_addr = sg_page_iter_dma_address(&sg_iter);
 589                 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
 590                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 591                         kunmap_atomic(pt_vaddr);
 592                         act_pt++;
 593                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 594                         act_pte = 0;
 595
 596                 }
 597         }
 598         kunmap_atomic(pt_vaddr);
 599 }
 600
 601 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 602 {
 603         struct i915_hw_ppgtt *ppgtt =
 604                 container_of(vm, struct i915_hw_ppgtt, base);
 605         int i;
 606
 607         drm_mm_takedown(&ppgtt->base.mm);
 608
 609         if (ppgtt->pt_dma_addr) {
 610                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 611                         pci_unmap_page(ppgtt->base.dev->pdev,
 612                                        ppgtt->pt_dma_addr[i],
 613                                        4096, PCI_DMA_BIDIRECTIONAL);
 614         }
 615
 616         kfree(ppgtt->pt_dma_addr);
 617         for (i = 0; i < ppgtt->num_pd_entries; i++)
 618                 __free_page(ppgtt->pt_pages[i]);
 619         kfree(ppgtt->pt_pages);
 620         kfree(ppgtt);
 621 }
 622
 623 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 624 {
 625         struct drm_device *dev = ppgtt->base.dev;
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         unsigned first_pd_entry_in_global_pt;
 628         int i;
 629         int ret = -ENOMEM;
 630
 631         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 632          * entries. For aliasing ppgtt support we just steal them at the end for
 633          * now. */
 634         first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 635
 636         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 637         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 638         ppgtt->enable = gen6_ppgtt_enable;
 639         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 640         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 641         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 642         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 643         ppgtt->base.start = 0;
 644         ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
 645         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
 646                                   GFP_KERNEL);
 647         if (!ppgtt->pt_pages)
 648                 return -ENOMEM;
 649
 650         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 651                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 652                 if (!ppgtt->pt_pages[i])
 653                         goto err_pt_alloc;
 654         }
 655
 656         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
 657                                      GFP_KERNEL);
 658         if (!ppgtt->pt_dma_addr)
 659                 goto err_pt_alloc;
 660
 661         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 662                 dma_addr_t pt_addr;
 663
 664                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 665                                        PCI_DMA_BIDIRECTIONAL);
 666
 667                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 668                         ret = -EIO;
 669                         goto err_pd_pin;
 670
 671                 }
 672                 ppgtt->pt_dma_addr[i] = pt_addr;
 673         }
 674
 675         ppgtt->base.clear_range(&ppgtt->base, 0,
 676                                 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
 677
 678         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 679
 680         return 0;
 681
 682 err_pd_pin:
 683         if (ppgtt->pt_dma_addr) {
 684                 for (i--; i >= 0; i--)
 685                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 686                                        4096, PCI_DMA_BIDIRECTIONAL);
 687         }
 688 err_pt_alloc:
 689         kfree(ppgtt->pt_dma_addr);
 690         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 691                 if (ppgtt->pt_pages[i])
 692                         __free_page(ppgtt->pt_pages[i]);
 693         }
 694         kfree(ppgtt->pt_pages);
 695
 696         return ret;
 697 }
 698
 699 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 700 {
 701         struct drm_i915_private *dev_priv = dev->dev_private;
 702         struct i915_hw_ppgtt *ppgtt;
 703         int ret;
 704
 705         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 706         if (!ppgtt)
 707                 return -ENOMEM;
 708
 709         ppgtt->base.dev = dev;
 710
 711         if (INTEL_INFO(dev)->gen < 8)
 712                 ret = gen6_ppgtt_init(ppgtt);
 713         else if (IS_GEN8(dev))
 714                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 715         else
 716                 BUG();
 717
 718         if (ret)
 719                 kfree(ppgtt);
 720         else {
 721                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 722                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
 723                             ppgtt->base.total);
 724         }
 725
 726         return ret;
 727 }
 728
 729 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 730 {
 731         struct drm_i915_private *dev_priv = dev->dev_private;
 732         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 733
 734         if (!ppgtt)
 735                 return;
 736
 737         ppgtt->base.cleanup(&ppgtt->base);
 738         dev_priv->mm.aliasing_ppgtt = NULL;
 739 }
 740
 741 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 742                             struct drm_i915_gem_object *obj,
 743                             enum i915_cache_level cache_level)
 744 {
 745         ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
 746                                    i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 747                                    cache_level);
 748 }
 749
 750 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 751                               struct drm_i915_gem_object *obj)
 752 {
 753         ppgtt->base.clear_range(&ppgtt->base,
 754                                 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 755                                 obj->base.size >> PAGE_SHIFT,
 756                                 true);
 757 }
 758
 759 extern int intel_iommu_gfx_mapped;
 760 /* Certain Gen5 chipsets require require idling the GPU before
 761  * unmapping anything from the GTT when VT-d is enabled.
 762  */
 763 static inline bool needs_idle_maps(struct drm_device *dev)
 764 {
 765 #ifdef CONFIG_INTEL_IOMMU
 766         /* Query intel_iommu to see if we need the workaround. Presumably that
 767          * was loaded first.
 768          */
 769         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 770                 return true;
 771 #endif
 772         return false;
 773 }
 774
 775 static bool do_idling(struct drm_i915_private *dev_priv)
 776 {
 777         bool ret = dev_priv->mm.interruptible;
 778
 779         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 780                 dev_priv->mm.interruptible = false;
 781                 if (i915_gpu_idle(dev_priv->dev)) {
 782                         DRM_ERROR("Couldn't idle GPU\n");
 783                         /* Wait a bit, in hopes it avoids the hang */
 784                         udelay(10);
 785                 }
 786         }
 787
 788         return ret;
 789 }
 790
 791 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 792 {
 793         if (unlikely(dev_priv->gtt.do_idle_maps))
 794                 dev_priv->mm.interruptible = interruptible;
 795 }
 796
 797 void i915_check_and_clear_faults(struct drm_device *dev)
 798 {
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         struct intel_ring_buffer *ring;
 801         int i;
 802
 803         if (INTEL_INFO(dev)->gen < 6)
 804                 return;
 805
 806         for_each_ring(ring, dev_priv, i) {
 807                 u32 fault_reg;
 808                 fault_reg = I915_READ(RING_FAULT_REG(ring));
 809                 if (fault_reg & RING_FAULT_VALID) {
 810                         DRM_DEBUG_DRIVER("Unexpected fault\n"
 811                                          "\tAddr: 0x%08lx\\n"
 812                                          "\tAddress space: %s\n"
 813                                          "\tSource ID: %d\n"
 814                                          "\tType: %d\n",
 815                                          fault_reg & PAGE_MASK,
 816                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
 817                                          RING_FAULT_SRCID(fault_reg),
 818                                          RING_FAULT_FAULT_TYPE(fault_reg));
 819                         I915_WRITE(RING_FAULT_REG(ring),
 820                                    fault_reg & ~RING_FAULT_VALID);
 821                 }
 822         }
 823         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
 824 }
 825
 826 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
 827 {
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829
 830         /* Don't bother messing with faults pre GEN6 as we have little
 831          * documentation supporting that it's a good idea.
 832          */
 833         if (INTEL_INFO(dev)->gen < 6)
 834                 return;
 835
 836         i915_check_and_clear_faults(dev);
 837
 838         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 839                                        dev_priv->gtt.base.start / PAGE_SIZE,
 840                                        dev_priv->gtt.base.total / PAGE_SIZE,
 841                                        false);
 842 }
 843
 844 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         struct drm_i915_gem_object *obj;
 848
 849         i915_check_and_clear_faults(dev);
 850
 851         /* First fill our portion of the GTT with scratch pages */
 852         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 853                                        dev_priv->gtt.base.start / PAGE_SIZE,
 854                                        dev_priv->gtt.base.total / PAGE_SIZE,
 855                                        true);
 856
 857         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 858                 i915_gem_clflush_object(obj, obj->pin_display);
 859                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 860         }
 861
 862         i915_gem_chipset_flush(dev);
 863 }
 864
 865 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 866 {
 867         if (obj->has_dma_mapping)
 868                 return 0;
 869
 870         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 871                         obj->pages->sgl, obj->pages->nents,
 872                         PCI_DMA_BIDIRECTIONAL))
 873                 return -ENOSPC;
 874
 875         return 0;
 876 }
 877
 878 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
 879 {
 880 #ifdef writeq
 881         writeq(pte, addr);
 882 #else
 883         iowrite32((u32)pte, addr);
 884         iowrite32(pte >> 32, addr + 4);
 885 #endif
 886 }
 887
 888 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 889                                      struct sg_table *st,
 890                                      unsigned int first_entry,
 891                                      enum i915_cache_level level)
 892 {
 893         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 894         gen8_gtt_pte_t __iomem *gtt_entries =
 895                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 896         int i = 0;
 897         struct sg_page_iter sg_iter;
 898         dma_addr_t addr;
 899
 900         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 901                 addr = sg_dma_address(sg_iter.sg) +
 902                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
 903                 gen8_set_pte(&gtt_entries[i],
 904                              gen8_pte_encode(addr, level, true));
 905                 i++;
 906         }
 907
 908         /*
 909          * XXX: This serves as a posting read to make sure that the PTE has
 910          * actually been updated. There is some concern that even though
 911          * registers and PTEs are within the same BAR that they are potentially
 912          * of NUMA access patterns. Therefore, even with the way we assume
 913          * hardware should work, we must keep this posting read for paranoia.
 914          */
 915         if (i != 0)
 916                 WARN_ON(readq(&gtt_entries[i-1])
 917                         != gen8_pte_encode(addr, level, true));
 918
 919 #if 0 /* TODO: Still needed on GEN8? */
 920         /* This next bit makes the above posting read even more important. We
 921          * want to flush the TLBs only after we're certain all the PTE updates
 922          * have finished.
 923          */
 924         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 925         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 926 #endif
 927 }
 928
 929 /*
 930  * Binds an object into the global gtt with the specified cache level. The object
 931  * will be accessible to the GPU via commands whose operands reference offsets
 932  * within the global GTT as well as accessible by the GPU through the GMADR
 933  * mapped BAR (dev_priv->mm.gtt->gtt).
 934  */
 935 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 936                                      struct sg_table *st,
 937                                      unsigned int first_entry,
 938                                      enum i915_cache_level level)
 939 {
 940         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 941         gen6_gtt_pte_t __iomem *gtt_entries =
 942                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 943         int i = 0;
 944         struct sg_page_iter sg_iter;
 945         dma_addr_t addr;
 946
 947         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 948                 addr = sg_page_iter_dma_address(&sg_iter);
 949                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
 950                 i++;
 951         }
 952
 953         /* XXX: This serves as a posting read to make sure that the PTE has
 954          * actually been updated. There is some concern that even though
 955          * registers and PTEs are within the same BAR that they are potentially
 956          * of NUMA access patterns. Therefore, even with the way we assume
 957          * hardware should work, we must keep this posting read for paranoia.
 958          */
 959         if (i != 0)
 960                 WARN_ON(readl(&gtt_entries[i-1]) !=
 961                         vm->pte_encode(addr, level, true));
 962
 963         /* This next bit makes the above posting read even more important. We
 964          * want to flush the TLBs only after we're certain all the PTE updates
 965          * have finished.
 966          */
 967         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 968         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 969 }
 970
 971 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 972                                   unsigned int first_entry,
 973                                   unsigned int num_entries,
 974                                   bool use_scratch)
 975 {
 976         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 977         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
 978                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 979         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 980         int i;
 981
 982         if (WARN(num_entries > max_entries,
 983                  "First entry = %d; Num entries = %d (max=%d)\n",
 984                  first_entry, num_entries, max_entries))
 985                 num_entries = max_entries;
 986
 987         scratch_pte = gen8_pte_encode(vm->scratch.addr,
 988                                       I915_CACHE_LLC,
 989                                       use_scratch);
 990         for (i = 0; i < num_entries; i++)
 991                 gen8_set_pte(&gtt_base[i], scratch_pte);
 992         readl(gtt_base);
 993 }
 994
 995 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 996                                   unsigned int first_entry,
 997                                   unsigned int num_entries,
 998                                   bool use_scratch)
 999 {
1000         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1001         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1002                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1003         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1004         int i;
1005
1006         if (WARN(num_entries > max_entries,
1007                  "First entry = %d; Num entries = %d (max=%d)\n",
1008                  first_entry, num_entries, max_entries))
1009                 num_entries = max_entries;
1010
1011         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1012
1013         for (i = 0; i < num_entries; i++)
1014                 iowrite32(scratch_pte, &gtt_base[i]);
1015         readl(gtt_base);
1016 }
1017
1018 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1019                                      struct sg_table *st,
1020                                      unsigned int pg_start,
1021                                      enum i915_cache_level cache_level)
1022 {
1023         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1024                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1025
1026         intel_gtt_insert_sg_entries(st, pg_start, flags);
1027
1028 }
1029
1030 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1031                                   unsigned int first_entry,
1032                                   unsigned int num_entries,
1033                                   bool unused)
1034 {
1035         intel_gtt_clear_range(first_entry, num_entries);
1036 }
1037
1038
1039 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1040                               enum i915_cache_level cache_level)
1041 {
1042         struct drm_device *dev = obj->base.dev;
1043         struct drm_i915_private *dev_priv = dev->dev_private;
1044         const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
1045
1046         dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
1047                                           entry,
1048                                           cache_level);
1049
1050         obj->has_global_gtt_mapping = 1;
1051 }
1052
1053 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
1054 {
1055         struct drm_device *dev = obj->base.dev;
1056         struct drm_i915_private *dev_priv = dev->dev_private;
1057         const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
1058
1059         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1060                                        entry,
1061                                        obj->base.size >> PAGE_SHIFT,
1062                                        true);
1063
1064         obj->has_global_gtt_mapping = 0;
1065 }
1066
1067 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1068 {
1069         struct drm_device *dev = obj->base.dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         bool interruptible;
1072
1073         interruptible = do_idling(dev_priv);
1074
1075         if (!obj->has_dma_mapping)
1076                 dma_unmap_sg(&dev->pdev->dev,
1077                              obj->pages->sgl, obj->pages->nents,
1078                              PCI_DMA_BIDIRECTIONAL);
1079
1080         undo_idling(dev_priv, interruptible);
1081 }
1082
1083 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1084                                   unsigned long color,
1085                                   unsigned long *start,
1086                                   unsigned long *end)
1087 {
1088         if (node->color != color)
1089                 *start += 4096;
1090
1091         if (!list_empty(&node->node_list)) {
1092                 node = list_entry(node->node_list.next,
1093                                   struct drm_mm_node,
1094                                   node_list);
1095                 if (node->allocated && node->color != color)
1096                         *end -= 4096;
1097         }
1098 }
1099
1100 void i915_gem_setup_global_gtt(struct drm_device *dev,
1101                                unsigned long start,
1102                                unsigned long mappable_end,
1103                                unsigned long end)
1104 {
1105         /* Let GEM Manage all of the aperture.
1106          *
1107          * However, leave one page at the end still bound to the scratch page.
1108          * There are a number of places where the hardware apparently prefetches
1109          * past the end of the object, and we've seen multiple hangs with the
1110          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1111          * aperture.  One page should be enough to keep any prefetching inside
1112          * of the aperture.
1113          */
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1116         struct drm_mm_node *entry;
1117         struct drm_i915_gem_object *obj;
1118         unsigned long hole_start, hole_end;
1119
1120         BUG_ON(mappable_end > end);
1121
1122         /* Subtract the guard page ... */
1123         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1124         if (!HAS_LLC(dev))
1125                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1126
1127         /* Mark any preallocated objects as occupied */
1128         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1129                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1130                 int ret;
1131                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1132                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1133
1134                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1135                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1136                 if (ret)
1137                         DRM_DEBUG_KMS("Reservation failed\n");
1138                 obj->has_global_gtt_mapping = 1;
1139         }
1140
1141         dev_priv->gtt.base.start = start;
1142         dev_priv->gtt.base.total = end - start;
1143
1144         /* Clear any non-preallocated blocks */
1145         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1146                 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1147                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1148                               hole_start, hole_end);
1149                 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1150         }
1151
1152         /* And finally clear the reserved guard page */
1153         ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1154 }
1155
1156 static bool
1157 intel_enable_ppgtt(struct drm_device *dev)
1158 {
1159         if (i915_enable_ppgtt >= 0)
1160                 return i915_enable_ppgtt;
1161
1162 #ifdef CONFIG_INTEL_IOMMU
1163         /* Disable ppgtt on SNB if VT-d is on. */
1164         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1165                 return false;
1166 #endif
1167
1168         return true;
1169 }
1170
1171 void i915_gem_init_global_gtt(struct drm_device *dev)
1172 {
1173         struct drm_i915_private *dev_priv = dev->dev_private;
1174         unsigned long gtt_size, mappable_size;
1175
1176         gtt_size = dev_priv->gtt.base.total;
1177         mappable_size = dev_priv->gtt.mappable_end;
1178
1179         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1180                 int ret;
1181
1182                 if (INTEL_INFO(dev)->gen <= 7) {
1183                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1184                          * aperture accordingly when using aliasing ppgtt. */
1185                         gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
1186                 }
1187
1188                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1189
1190                 ret = i915_gem_init_aliasing_ppgtt(dev);
1191                 if (!ret)
1192                         return;
1193
1194                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
1195                 drm_mm_takedown(&dev_priv->gtt.base.mm);
1196                 if (INTEL_INFO(dev)->gen < 8)
1197                         gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE;
1198         }
1199         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1200 }
1201
1202 static int setup_scratch_page(struct drm_device *dev)
1203 {
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         struct page *page;
1206         dma_addr_t dma_addr;
1207
1208         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1209         if (page == NULL)
1210                 return -ENOMEM;
1211         get_page(page);
1212         set_pages_uc(page, 1);
1213
1214 #ifdef CONFIG_INTEL_IOMMU
1215         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1216                                 PCI_DMA_BIDIRECTIONAL);
1217         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1218                 return -EINVAL;
1219 #else
1220         dma_addr = page_to_phys(page);
1221 #endif
1222         dev_priv->gtt.base.scratch.page = page;
1223         dev_priv->gtt.base.scratch.addr = dma_addr;
1224
1225         return 0;
1226 }
1227
1228 static void teardown_scratch_page(struct drm_device *dev)
1229 {
1230         struct drm_i915_private *dev_priv = dev->dev_private;
1231         struct page *page = dev_priv->gtt.base.scratch.page;
1232
1233         set_pages_wb(page, 1);
1234         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1235                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1236         put_page(page);
1237         __free_page(page);
1238 }
1239
1240 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1241 {
1242         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1243         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1244         return snb_gmch_ctl << 20;
1245 }
1246
1247 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1248 {
1249         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1250         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1251         if (bdw_gmch_ctl)
1252                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1253         if (bdw_gmch_ctl > 4) {
1254                 WARN_ON(!i915_preliminary_hw_support);
1255                 return 4<<20;
1256         }
1257
1258         return bdw_gmch_ctl << 20;
1259 }
1260
1261 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1262 {
1263         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1264         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1265         return snb_gmch_ctl << 25; /* 32 MB units */
1266 }
1267
1268 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1269 {
1270         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1271         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1272         return bdw_gmch_ctl << 25; /* 32 MB units */
1273 }
1274
1275 static int ggtt_probe_common(struct drm_device *dev,
1276                              size_t gtt_size)
1277 {
1278         struct drm_i915_private *dev_priv = dev->dev_private;
1279         phys_addr_t gtt_bus_addr;
1280         int ret;
1281
1282         /* For Modern GENs the PTEs and register space are split in the BAR */
1283         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1284                 (pci_resource_len(dev->pdev, 0) / 2);
1285
1286         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1287         if (!dev_priv->gtt.gsm) {
1288                 DRM_ERROR("Failed to map the gtt page table\n");
1289                 return -ENOMEM;
1290         }
1291
1292         ret = setup_scratch_page(dev);
1293         if (ret) {
1294                 DRM_ERROR("Scratch setup failed\n");
1295                 /* iounmap will also get called at remove, but meh */
1296                 iounmap(dev_priv->gtt.gsm);
1297         }
1298
1299         return ret;
1300 }
1301
1302 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1303  * bits. When using advanced contexts each context stores its own PAT, but
1304  * writing this data shouldn't be harmful even in those cases. */
1305 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1306 {
1307 #define GEN8_PPAT_UC            (0<<0)
1308 #define GEN8_PPAT_WC            (1<<0)
1309 #define GEN8_PPAT_WT            (2<<0)
1310 #define GEN8_PPAT_WB            (3<<0)
1311 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1312 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1313 #define GEN8_PPAT_LLC           (1<<2)
1314 #define GEN8_PPAT_LLCELLC       (2<<2)
1315 #define GEN8_PPAT_LLCeLLC       (3<<2)
1316 #define GEN8_PPAT_AGE(x)        (x<<4)
1317 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1318         uint64_t pat;
1319
1320         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1321               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1322               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1323               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1324               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1325               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1326               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1327               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1328
1329         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1330          * write would work. */
1331         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1332         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1333 }
1334
1335 static int gen8_gmch_probe(struct drm_device *dev,
1336                            size_t *gtt_total,
1337                            size_t *stolen,
1338                            phys_addr_t *mappable_base,
1339                            unsigned long *mappable_end)
1340 {
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         unsigned int gtt_size;
1343         u16 snb_gmch_ctl;
1344         int ret;
1345
1346         /* TODO: We're not aware of mappable constraints on gen8 yet */
1347         *mappable_base = pci_resource_start(dev->pdev, 2);
1348         *mappable_end = pci_resource_len(dev->pdev, 2);
1349
1350         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1351                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1352
1353         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1354
1355         *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1356
1357         gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1358         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1359
1360         gen8_setup_private_ppat(dev_priv);
1361
1362         ret = ggtt_probe_common(dev, gtt_size);
1363
1364         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1365         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1366
1367         return ret;
1368 }
1369
1370 static int gen6_gmch_probe(struct drm_device *dev,
1371                            size_t *gtt_total,
1372                            size_t *stolen,
1373                            phys_addr_t *mappable_base,
1374                            unsigned long *mappable_end)
1375 {
1376         struct drm_i915_private *dev_priv = dev->dev_private;
1377         unsigned int gtt_size;
1378         u16 snb_gmch_ctl;
1379         int ret;
1380
1381         *mappable_base = pci_resource_start(dev->pdev, 2);
1382         *mappable_end = pci_resource_len(dev->pdev, 2);
1383
1384         /* 64/512MB is the current min/max we actually know of, but this is just
1385          * a coarse sanity check.
1386          */
1387         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1388                 DRM_ERROR("Unknown GMADR size (%lx)\n",
1389                           dev_priv->gtt.mappable_end);
1390                 return -ENXIO;
1391         }
1392
1393         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1394                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1395         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1396
1397         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1398
1399         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1400         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1401
1402         ret = ggtt_probe_common(dev, gtt_size);
1403
1404         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1405         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1406
1407         return ret;
1408 }
1409
1410 static void gen6_gmch_remove(struct i915_address_space *vm)
1411 {
1412
1413         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1414
1415         drm_mm_takedown(&vm->mm);
1416         iounmap(gtt->gsm);
1417         teardown_scratch_page(vm->dev);
1418 }
1419
1420 static int i915_gmch_probe(struct drm_device *dev,
1421                            size_t *gtt_total,
1422                            size_t *stolen,
1423                            phys_addr_t *mappable_base,
1424                            unsigned long *mappable_end)
1425 {
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         int ret;
1428
1429         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1430         if (!ret) {
1431                 DRM_ERROR("failed to set up gmch\n");
1432                 return -EIO;
1433         }
1434
1435         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1436
1437         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1438         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1439         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
1440
1441         return 0;
1442 }
1443
1444 static void i915_gmch_remove(struct i915_address_space *vm)
1445 {
1446         intel_gmch_remove();
1447 }
1448
1449 int i915_gem_gtt_init(struct drm_device *dev)
1450 {
1451         struct drm_i915_private *dev_priv = dev->dev_private;
1452         struct i915_gtt *gtt = &dev_priv->gtt;
1453         int ret;
1454
1455         if (INTEL_INFO(dev)->gen <= 5) {
1456                 gtt->gtt_probe = i915_gmch_probe;
1457                 gtt->base.cleanup = i915_gmch_remove;
1458         } else if (INTEL_INFO(dev)->gen < 8) {
1459                 gtt->gtt_probe = gen6_gmch_probe;
1460                 gtt->base.cleanup = gen6_gmch_remove;
1461                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1462                         gtt->base.pte_encode = iris_pte_encode;
1463                 else if (IS_HASWELL(dev))
1464                         gtt->base.pte_encode = hsw_pte_encode;
1465                 else if (IS_VALLEYVIEW(dev))
1466                         gtt->base.pte_encode = byt_pte_encode;
1467                 else if (INTEL_INFO(dev)->gen >= 7)
1468                         gtt->base.pte_encode = ivb_pte_encode;
1469                 else
1470                         gtt->base.pte_encode = snb_pte_encode;
1471         } else {
1472                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1473                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1474         }
1475
1476         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1477                              &gtt->mappable_base, &gtt->mappable_end);
1478         if (ret)
1479                 return ret;
1480
1481         gtt->base.dev = dev;
1482
1483         /* GMADR is the PCI mmio aperture into the global GTT. */
1484         DRM_INFO("Memory usable by graphics device = %zdM\n",
1485                  gtt->base.total >> 20);
1486         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1487         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1488
1489         return 0;
1490 }