2 * Copyright (c) 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
30 #include <generated/utsrelease.h>
33 static const char *yesno(int v)
35 return v ? "yes" : "no";
38 static const char *ring_str(int ring)
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 case VCS2: return "bsd2";
50 static const char *pin_flag(int pinned)
60 static const char *tiling_flag(int tiling)
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
70 static const char *dirty_flag(int dirty)
72 return dirty ? " dirty" : "";
75 static const char *purgeable_flag(int purgeable)
77 return purgeable ? " purgeable" : "";
80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
88 if (e->bytes == e->size - 1 || e->err)
94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
97 if (e->pos + len <= e->start) {
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
111 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
137 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
142 if (!__i915_error_ok(e))
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
150 len = vsnprintf(NULL, 0, f, tmp);
153 if (!__i915_error_seek(e, len))
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
161 __i915_error_advance(e, len);
164 static void i915_error_puts(struct drm_i915_error_state_buf *e,
169 if (!__i915_error_ok(e))
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
184 __i915_error_advance(e, len);
187 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188 #define err_puts(e, s) i915_error_puts(e, s)
190 static void print_error_buffers(struct drm_i915_error_state_buf *m,
192 struct drm_i915_error_buffer *err,
195 err_printf(m, " %s [%d]:\n", name, count);
198 err_printf(m, " %08x %8u %02x %02x %x %x",
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
208 err_puts(m, err->userptr ? " userptr" : "");
209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
214 err_printf(m, " (name: %d)", err->name);
215 if (err->fence_reg != I915_FENCE_REG_NONE)
216 err_printf(m, " (fence: %d)", err->fence_reg);
223 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
230 case HANGCHECK_ACTIVE:
232 case HANGCHECK_ACTIVE_LOOP:
233 return "active (loop)";
243 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
244 struct drm_device *dev,
245 struct drm_i915_error_ring *ring)
250 err_printf(m, " HEAD: 0x%08x\n", ring->head);
251 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
252 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
253 err_printf(m, " HWS: 0x%08x\n", ring->hws);
254 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
255 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
256 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
257 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
258 if (INTEL_INFO(dev)->gen >= 4) {
259 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
260 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
261 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
263 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
264 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
265 lower_32_bits(ring->faddr));
266 if (INTEL_INFO(dev)->gen >= 6) {
267 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
268 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
269 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
270 ring->semaphore_mboxes[0],
271 ring->semaphore_seqno[0]);
272 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
273 ring->semaphore_mboxes[1],
274 ring->semaphore_seqno[1]);
275 if (HAS_VEBOX(dev)) {
276 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
277 ring->semaphore_mboxes[2],
278 ring->semaphore_seqno[2]);
281 if (USES_PPGTT(dev)) {
282 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
284 if (INTEL_INFO(dev)->gen >= 8) {
286 for (i = 0; i < 4; i++)
287 err_printf(m, " PDP%d: 0x%016llx\n",
288 i, ring->vm_info.pdp[i]);
290 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
291 ring->vm_info.pp_dir_base);
294 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
295 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
296 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
297 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
298 err_printf(m, " hangcheck: %s [%d]\n",
299 hangcheck_action_to_str(ring->hangcheck_action),
300 ring->hangcheck_score);
303 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
308 i915_error_vprintf(e, f, args);
312 static void print_error_obj(struct drm_i915_error_state_buf *m,
313 struct drm_i915_error_object *obj)
315 int page, offset, elt;
317 for (page = offset = 0; page < obj->page_count; page++) {
318 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
319 err_printf(m, "%08x : %08x\n", offset,
320 obj->pages[page][elt]);
326 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
327 const struct i915_error_state_file_priv *error_priv)
329 struct drm_device *dev = error_priv->dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 struct drm_i915_error_state *error = error_priv->error;
332 struct drm_i915_error_object *obj;
333 int i, j, offset, elt;
334 int max_hangcheck_score;
337 err_printf(m, "no error state collected\n");
341 err_printf(m, "%s\n", error->error_msg);
342 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
343 error->time.tv_usec);
344 err_printf(m, "Kernel: " UTS_RELEASE "\n");
345 max_hangcheck_score = 0;
346 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
347 if (error->ring[i].hangcheck_score > max_hangcheck_score)
348 max_hangcheck_score = error->ring[i].hangcheck_score;
350 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
351 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
352 error->ring[i].pid != -1) {
353 err_printf(m, "Active process (on ring %s): %s [%d]\n",
359 err_printf(m, "Reset count: %u\n", error->reset_count);
360 err_printf(m, "Suspend count: %u\n", error->suspend_count);
361 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
362 err_printf(m, "EIR: 0x%08x\n", error->eir);
363 err_printf(m, "IER: 0x%08x\n", error->ier);
364 if (INTEL_INFO(dev)->gen >= 8) {
365 for (i = 0; i < 4; i++)
366 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
368 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
369 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
370 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
371 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
372 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
373 err_printf(m, "CCID: 0x%08x\n", error->ccid);
374 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
376 for (i = 0; i < dev_priv->num_fence_regs; i++)
377 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
379 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
380 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
381 error->extra_instdone[i]);
383 if (INTEL_INFO(dev)->gen >= 6) {
384 err_printf(m, "ERROR: 0x%08x\n", error->error);
385 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
388 if (INTEL_INFO(dev)->gen == 7)
389 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
391 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
392 err_printf(m, "%s command stream:\n", ring_str(i));
393 i915_ring_error_state(m, dev, &error->ring[i]);
396 for (i = 0; i < error->vm_count; i++) {
397 err_printf(m, "vm[%d]\n", i);
399 print_error_buffers(m, "Active",
401 error->active_bo_count[i]);
403 print_error_buffers(m, "Pinned",
405 error->pinned_bo_count[i]);
408 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
409 obj = error->ring[i].batchbuffer;
411 err_puts(m, dev_priv->ring[i].name);
412 if (error->ring[i].pid != -1)
413 err_printf(m, " (submitted by %s [%d])",
416 err_printf(m, " --- gtt_offset = 0x%08x\n",
418 print_error_obj(m, obj);
421 obj = error->ring[i].wa_batchbuffer;
423 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
424 dev_priv->ring[i].name, obj->gtt_offset);
425 print_error_obj(m, obj);
428 if (error->ring[i].num_requests) {
429 err_printf(m, "%s --- %d requests\n",
430 dev_priv->ring[i].name,
431 error->ring[i].num_requests);
432 for (j = 0; j < error->ring[i].num_requests; j++) {
433 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
434 error->ring[i].requests[j].seqno,
435 error->ring[i].requests[j].jiffies,
436 error->ring[i].requests[j].tail);
440 if ((obj = error->ring[i].ringbuffer)) {
441 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
442 dev_priv->ring[i].name,
444 print_error_obj(m, obj);
447 if ((obj = error->ring[i].hws_page)) {
448 err_printf(m, "%s --- HW Status = 0x%08x\n",
449 dev_priv->ring[i].name,
452 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
453 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
456 obj->pages[0][elt+1],
457 obj->pages[0][elt+2],
458 obj->pages[0][elt+3]);
463 if ((obj = error->ring[i].ctx)) {
464 err_printf(m, "%s --- HW Context = 0x%08x\n",
465 dev_priv->ring[i].name,
467 print_error_obj(m, obj);
471 if ((obj = error->semaphore_obj)) {
472 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
473 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
474 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
477 obj->pages[0][elt+1],
478 obj->pages[0][elt+2],
479 obj->pages[0][elt+3]);
484 intel_overlay_print_error_state(m, error->overlay);
487 intel_display_print_error_state(m, dev, error->display);
490 if (m->bytes == 0 && m->err)
496 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
497 struct drm_i915_private *i915,
498 size_t count, loff_t pos)
500 memset(ebuf, 0, sizeof(*ebuf));
503 /* We need to have enough room to store any i915_error_state printf
504 * so that we can move it to start position.
506 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
507 ebuf->buf = kmalloc(ebuf->size,
508 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
510 if (ebuf->buf == NULL) {
511 ebuf->size = PAGE_SIZE;
512 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
515 if (ebuf->buf == NULL) {
517 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
520 if (ebuf->buf == NULL)
528 static void i915_error_object_free(struct drm_i915_error_object *obj)
535 for (page = 0; page < obj->page_count; page++)
536 kfree(obj->pages[page]);
541 static void i915_error_state_free(struct kref *error_ref)
543 struct drm_i915_error_state *error = container_of(error_ref,
544 typeof(*error), ref);
547 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
548 i915_error_object_free(error->ring[i].batchbuffer);
549 i915_error_object_free(error->ring[i].ringbuffer);
550 i915_error_object_free(error->ring[i].hws_page);
551 i915_error_object_free(error->ring[i].ctx);
552 kfree(error->ring[i].requests);
555 i915_error_object_free(error->semaphore_obj);
556 kfree(error->active_bo);
557 kfree(error->overlay);
558 kfree(error->display);
562 static struct drm_i915_error_object *
563 i915_error_object_create(struct drm_i915_private *dev_priv,
564 struct drm_i915_gem_object *src,
565 struct i915_address_space *vm)
567 struct drm_i915_error_object *dst;
573 if (src == NULL || src->pages == NULL)
576 num_pages = src->base.size >> PAGE_SHIFT;
578 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
582 if (i915_gem_obj_bound(src, vm))
583 dst->gtt_offset = i915_gem_obj_offset(src, vm);
585 dst->gtt_offset = -1;
587 reloc_offset = dst->gtt_offset;
588 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
590 src->has_global_gtt_mapping &&
591 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
593 /* Cannot access stolen address directly, try to use the aperture */
597 if (!src->has_global_gtt_mapping)
600 reloc_offset = i915_gem_obj_ggtt_offset(src);
601 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
605 /* Cannot access snooped pages through the aperture */
606 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
609 dst->page_count = num_pages;
610 while (num_pages--) {
614 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
618 local_irq_save(flags);
622 /* Simply ignore tiling or any overlapping fence.
623 * It's part of the error state, and this hopefully
624 * captures what the GPU read.
627 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
629 memcpy_fromio(d, s, PAGE_SIZE);
630 io_mapping_unmap_atomic(s);
635 page = i915_gem_object_get_page(src, i);
637 drm_clflush_pages(&page, 1);
639 s = kmap_atomic(page);
640 memcpy(d, s, PAGE_SIZE);
643 drm_clflush_pages(&page, 1);
645 local_irq_restore(flags);
648 reloc_offset += PAGE_SIZE;
655 kfree(dst->pages[i]);
659 #define i915_error_ggtt_object_create(dev_priv, src) \
660 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
662 static void capture_bo(struct drm_i915_error_buffer *err,
663 struct i915_vma *vma)
665 struct drm_i915_gem_object *obj = vma->obj;
667 err->size = obj->base.size;
668 err->name = obj->base.name;
669 err->rseqno = obj->last_read_seqno;
670 err->wseqno = obj->last_write_seqno;
671 err->gtt_offset = vma->node.start;
672 err->read_domains = obj->base.read_domains;
673 err->write_domain = obj->base.write_domain;
674 err->fence_reg = obj->fence_reg;
676 if (i915_gem_obj_is_pinned(obj))
678 if (obj->user_pin_count > 0)
680 err->tiling = obj->tiling_mode;
681 err->dirty = obj->dirty;
682 err->purgeable = obj->madv != I915_MADV_WILLNEED;
683 err->userptr = obj->userptr.mm != NULL;
684 err->ring = obj->ring ? obj->ring->id : -1;
685 err->cache_level = obj->cache_level;
688 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
689 int count, struct list_head *head)
691 struct i915_vma *vma;
694 list_for_each_entry(vma, head, mm_list) {
695 capture_bo(err++, vma);
703 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
704 int count, struct list_head *head,
705 struct i915_address_space *vm)
707 struct drm_i915_gem_object *obj;
708 struct drm_i915_error_buffer * const first = err;
709 struct drm_i915_error_buffer * const last = err + count;
711 list_for_each_entry(obj, head, global_list) {
712 struct i915_vma *vma;
717 list_for_each_entry(vma, &obj->vma_list, vma_link)
718 if (vma->vm == vm && vma->pin_count > 0) {
719 capture_bo(err++, vma);
727 /* Generate a semi-unique error code. The code is not meant to have meaning, The
728 * code's only purpose is to try to prevent false duplicated bug reports by
729 * grossly estimating a GPU error state.
731 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
732 * the hang if we could strip the GTT offset information from it.
734 * It's only a small step better than a random number in its current form.
736 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
737 struct drm_i915_error_state *error,
740 uint32_t error_code = 0;
743 /* IPEHR would be an ideal way to detect errors, as it's the gross
744 * measure of "the command that hung." However, has some very common
745 * synchronization commands which almost always appear in the case
746 * strictly a client bug. Use instdone to differentiate those some.
748 for (i = 0; i < I915_NUM_RINGS; i++) {
749 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
753 return error->ring[i].ipehr ^ error->ring[i].instdone;
760 static void i915_gem_record_fences(struct drm_device *dev,
761 struct drm_i915_error_state *error)
763 struct drm_i915_private *dev_priv = dev->dev_private;
767 switch (INTEL_INFO(dev)->gen) {
771 for (i = 0; i < dev_priv->num_fence_regs; i++)
772 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
776 for (i = 0; i < 16; i++)
777 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
780 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
781 for (i = 0; i < 8; i++)
782 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
784 for (i = 0; i < 8; i++)
785 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
794 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
795 struct drm_i915_error_state *error,
796 struct intel_engine_cs *ring,
797 struct drm_i915_error_ring *ering)
799 struct intel_engine_cs *to;
802 if (!i915_semaphore_is_enabled(dev_priv->dev))
805 if (!error->semaphore_obj)
806 error->semaphore_obj =
807 i915_error_object_create(dev_priv,
808 dev_priv->semaphore_obj,
809 &dev_priv->gtt.base);
811 for_each_ring(to, dev_priv, i) {
819 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
821 tmp = error->semaphore_obj->pages[0];
822 idx = intel_ring_sync_index(ring, to);
824 ering->semaphore_mboxes[idx] = tmp[signal_offset];
825 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
829 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
830 struct intel_engine_cs *ring,
831 struct drm_i915_error_ring *ering)
833 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
834 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
835 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
836 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
838 if (HAS_VEBOX(dev_priv->dev)) {
839 ering->semaphore_mboxes[2] =
840 I915_READ(RING_SYNC_2(ring->mmio_base));
841 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
845 static void i915_record_ring_state(struct drm_device *dev,
846 struct drm_i915_error_state *error,
847 struct intel_engine_cs *ring,
848 struct drm_i915_error_ring *ering)
850 struct drm_i915_private *dev_priv = dev->dev_private;
852 if (INTEL_INFO(dev)->gen >= 6) {
853 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
854 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
855 if (INTEL_INFO(dev)->gen >= 8)
856 gen8_record_semaphore_state(dev_priv, error, ring, ering);
858 gen6_record_semaphore_state(dev_priv, ring, ering);
861 if (INTEL_INFO(dev)->gen >= 4) {
862 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
863 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
864 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
865 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
866 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
867 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
868 if (INTEL_INFO(dev)->gen >= 8) {
869 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
870 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
872 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
874 ering->faddr = I915_READ(DMA_FADD_I8XX);
875 ering->ipeir = I915_READ(IPEIR);
876 ering->ipehr = I915_READ(IPEHR);
877 ering->instdone = I915_READ(INSTDONE);
880 ering->waiting = waitqueue_active(&ring->irq_queue);
881 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
882 ering->seqno = ring->get_seqno(ring, false);
883 ering->acthd = intel_ring_get_active_head(ring);
884 ering->head = I915_READ_HEAD(ring);
885 ering->tail = I915_READ_TAIL(ring);
886 ering->ctl = I915_READ_CTL(ring);
888 if (I915_NEED_GFX_HWS(dev)) {
895 mmio = RENDER_HWS_PGA_GEN7;
898 mmio = BLT_HWS_PGA_GEN7;
901 mmio = BSD_HWS_PGA_GEN7;
904 mmio = VEBOX_HWS_PGA_GEN7;
907 } else if (IS_GEN6(ring->dev)) {
908 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
910 /* XXX: gen8 returns to sanity */
911 mmio = RING_HWS_PGA(ring->mmio_base);
914 ering->hws = I915_READ(mmio);
917 ering->hangcheck_score = ring->hangcheck.score;
918 ering->hangcheck_action = ring->hangcheck.action;
920 if (USES_PPGTT(dev)) {
923 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
925 switch (INTEL_INFO(dev)->gen) {
927 for (i = 0; i < 4; i++) {
928 ering->vm_info.pdp[i] =
929 I915_READ(GEN8_RING_PDP_UDW(ring, i));
930 ering->vm_info.pdp[i] <<= 32;
931 ering->vm_info.pdp[i] |=
932 I915_READ(GEN8_RING_PDP_LDW(ring, i));
936 ering->vm_info.pp_dir_base =
937 I915_READ(RING_PP_DIR_BASE(ring));
940 ering->vm_info.pp_dir_base =
941 I915_READ(RING_PP_DIR_BASE_READ(ring));
948 static void i915_gem_record_active_context(struct intel_engine_cs *ring,
949 struct drm_i915_error_state *error,
950 struct drm_i915_error_ring *ering)
952 struct drm_i915_private *dev_priv = ring->dev->dev_private;
953 struct drm_i915_gem_object *obj;
955 /* Currently render ring is the only HW context user */
956 if (ring->id != RCS || !error->ccid)
959 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
960 if (!i915_gem_obj_ggtt_bound(obj))
963 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
964 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
970 static void i915_gem_record_rings(struct drm_device *dev,
971 struct drm_i915_error_state *error)
973 struct drm_i915_private *dev_priv = dev->dev_private;
974 struct drm_i915_gem_request *request;
977 for (i = 0; i < I915_NUM_RINGS; i++) {
978 struct intel_engine_cs *ring = &dev_priv->ring[i];
979 struct intel_ringbuffer *rbuf;
981 error->ring[i].pid = -1;
983 if (ring->dev == NULL)
986 error->ring[i].valid = true;
988 i915_record_ring_state(dev, error, ring, &error->ring[i]);
990 request = i915_gem_find_active_request(ring);
992 struct i915_address_space *vm;
994 vm = request->ctx && request->ctx->ppgtt ?
995 &request->ctx->ppgtt->base :
998 /* We need to copy these to an anonymous buffer
999 * as the simplest method to avoid being overwritten
1002 error->ring[i].batchbuffer =
1003 i915_error_object_create(dev_priv,
1007 if (HAS_BROKEN_CS_TLB(dev_priv->dev))
1008 error->ring[i].wa_batchbuffer =
1009 i915_error_ggtt_object_create(dev_priv,
1012 if (request->file_priv) {
1013 struct task_struct *task;
1016 task = pid_task(request->file_priv->file->pid,
1019 strcpy(error->ring[i].comm, task->comm);
1020 error->ring[i].pid = task->pid;
1026 if (i915.enable_execlists) {
1027 /* TODO: This is only a small fix to keep basic error
1028 * capture working, but we need to add more information
1029 * for it to be useful (e.g. dump the context being
1033 rbuf = request->ctx->engine[ring->id].ringbuf;
1035 rbuf = ring->default_context->engine[ring->id].ringbuf;
1037 rbuf = ring->buffer;
1039 error->ring[i].cpu_ring_head = rbuf->head;
1040 error->ring[i].cpu_ring_tail = rbuf->tail;
1042 error->ring[i].ringbuffer =
1043 i915_error_ggtt_object_create(dev_priv, rbuf->obj);
1045 error->ring[i].hws_page =
1046 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
1048 i915_gem_record_active_context(ring, error, &error->ring[i]);
1051 list_for_each_entry(request, &ring->request_list, list)
1054 error->ring[i].num_requests = count;
1055 error->ring[i].requests =
1056 kcalloc(count, sizeof(*error->ring[i].requests),
1058 if (error->ring[i].requests == NULL) {
1059 error->ring[i].num_requests = 0;
1064 list_for_each_entry(request, &ring->request_list, list) {
1065 struct drm_i915_error_request *erq;
1067 erq = &error->ring[i].requests[count++];
1068 erq->seqno = request->seqno;
1069 erq->jiffies = request->emitted_jiffies;
1070 erq->tail = request->tail;
1075 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1078 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1079 struct drm_i915_error_state *error,
1080 struct i915_address_space *vm,
1083 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1084 struct drm_i915_gem_object *obj;
1085 struct i915_vma *vma;
1089 list_for_each_entry(vma, &vm->active_list, mm_list)
1091 error->active_bo_count[ndx] = i;
1093 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1094 list_for_each_entry(vma, &obj->vma_list, vma_link)
1095 if (vma->vm == vm && vma->pin_count > 0) {
1100 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1103 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1105 pinned_bo = active_bo + error->active_bo_count[ndx];
1109 error->active_bo_count[ndx] =
1110 capture_active_bo(active_bo,
1111 error->active_bo_count[ndx],
1115 error->pinned_bo_count[ndx] =
1116 capture_pinned_bo(pinned_bo,
1117 error->pinned_bo_count[ndx],
1118 &dev_priv->mm.bound_list, vm);
1119 error->active_bo[ndx] = active_bo;
1120 error->pinned_bo[ndx] = pinned_bo;
1123 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1124 struct drm_i915_error_state *error)
1126 struct i915_address_space *vm;
1129 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1132 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1133 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1134 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1136 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1139 if (error->active_bo == NULL ||
1140 error->pinned_bo == NULL ||
1141 error->active_bo_count == NULL ||
1142 error->pinned_bo_count == NULL) {
1143 kfree(error->active_bo);
1144 kfree(error->active_bo_count);
1145 kfree(error->pinned_bo);
1146 kfree(error->pinned_bo_count);
1148 error->active_bo = NULL;
1149 error->active_bo_count = NULL;
1150 error->pinned_bo = NULL;
1151 error->pinned_bo_count = NULL;
1153 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1154 i915_gem_capture_vm(dev_priv, error, vm, i++);
1156 error->vm_count = cnt;
1160 /* Capture all registers which don't fit into another category. */
1161 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1162 struct drm_i915_error_state *error)
1164 struct drm_device *dev = dev_priv->dev;
1167 /* General organization
1168 * 1. Registers specific to a single generation
1169 * 2. Registers which belong to multiple generations
1170 * 3. Feature specific registers.
1171 * 4. Everything else
1172 * Please try to follow the order.
1175 /* 1: Registers specific to a single generation */
1176 if (IS_VALLEYVIEW(dev)) {
1177 error->gtier[0] = I915_READ(GTIER);
1178 error->ier = I915_READ(VLV_IER);
1179 error->forcewake = I915_READ(FORCEWAKE_VLV);
1183 error->err_int = I915_READ(GEN7_ERR_INT);
1186 error->forcewake = I915_READ(FORCEWAKE);
1187 error->gab_ctl = I915_READ(GAB_CTL);
1188 error->gfx_mode = I915_READ(GFX_MODE);
1191 /* 2: Registers which belong to multiple generations */
1192 if (INTEL_INFO(dev)->gen >= 7)
1193 error->forcewake = I915_READ(FORCEWAKE_MT);
1195 if (INTEL_INFO(dev)->gen >= 6) {
1196 error->derrmr = I915_READ(DERRMR);
1197 error->error = I915_READ(ERROR_GEN6);
1198 error->done_reg = I915_READ(DONE_REG);
1201 /* 3: Feature specific registers */
1202 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1203 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1204 error->gac_eco = I915_READ(GAC_ECO_BITS);
1207 /* 4: Everything else */
1208 if (HAS_HW_CONTEXTS(dev))
1209 error->ccid = I915_READ(CCID);
1211 if (INTEL_INFO(dev)->gen >= 8) {
1212 error->ier = I915_READ(GEN8_DE_MISC_IER);
1213 for (i = 0; i < 4; i++)
1214 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1215 } else if (HAS_PCH_SPLIT(dev)) {
1216 error->ier = I915_READ(DEIER);
1217 error->gtier[0] = I915_READ(GTIER);
1218 } else if (IS_GEN2(dev)) {
1219 error->ier = I915_READ16(IER);
1220 } else if (!IS_VALLEYVIEW(dev)) {
1221 error->ier = I915_READ(IER);
1223 error->eir = I915_READ(EIR);
1224 error->pgtbl_er = I915_READ(PGTBL_ER);
1226 i915_get_extra_instdone(dev, error->extra_instdone);
1229 static void i915_error_capture_msg(struct drm_device *dev,
1230 struct drm_i915_error_state *error,
1232 const char *error_msg)
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1236 int ring_id = -1, len;
1238 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1240 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1241 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1243 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1244 len += scnprintf(error->error_msg + len,
1245 sizeof(error->error_msg) - len,
1247 error->ring[ring_id].comm,
1248 error->ring[ring_id].pid);
1250 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1251 ", reason: %s, action: %s",
1253 wedged ? "reset" : "continue");
1256 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1257 struct drm_i915_error_state *error)
1259 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1260 error->suspend_count = dev_priv->suspend_count;
1264 * i915_capture_error_state - capture an error record for later analysis
1267 * Should be called when an error is detected (either a hang or an error
1268 * interrupt) to capture error state from the time of the error. Fills
1269 * out a structure which becomes available in debugfs for user level tools
1272 void i915_capture_error_state(struct drm_device *dev, bool wedged,
1273 const char *error_msg)
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 struct drm_i915_error_state *error;
1278 unsigned long flags;
1280 /* Account for pipe specific data like PIPE*STAT */
1281 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1283 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1287 kref_init(&error->ref);
1289 i915_capture_gen_state(dev_priv, error);
1290 i915_capture_reg_state(dev_priv, error);
1291 i915_gem_capture_buffers(dev_priv, error);
1292 i915_gem_record_fences(dev, error);
1293 i915_gem_record_rings(dev, error);
1295 do_gettimeofday(&error->time);
1297 error->overlay = intel_overlay_capture_error_state(dev);
1298 error->display = intel_display_capture_error_state(dev);
1300 i915_error_capture_msg(dev, error, wedged, error_msg);
1301 DRM_INFO("%s\n", error->error_msg);
1303 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1304 if (dev_priv->gpu_error.first_error == NULL) {
1305 dev_priv->gpu_error.first_error = error;
1308 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1311 i915_error_state_free(&error->ref);
1316 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1317 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1318 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1319 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1320 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1325 void i915_error_state_get(struct drm_device *dev,
1326 struct i915_error_state_file_priv *error_priv)
1328 struct drm_i915_private *dev_priv = dev->dev_private;
1329 unsigned long flags;
1331 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1332 error_priv->error = dev_priv->gpu_error.first_error;
1333 if (error_priv->error)
1334 kref_get(&error_priv->error->ref);
1335 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1339 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1341 if (error_priv->error)
1342 kref_put(&error_priv->error->ref, i915_error_state_free);
1345 void i915_destroy_error_state(struct drm_device *dev)
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 struct drm_i915_error_state *error;
1349 unsigned long flags;
1351 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1352 error = dev_priv->gpu_error.first_error;
1353 dev_priv->gpu_error.first_error = NULL;
1354 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1357 kref_put(&error->ref, i915_error_state_free);
1360 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1363 case I915_CACHE_NONE: return " uncached";
1364 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1365 case I915_CACHE_L3_LLC: return " L3+LLC";
1366 case I915_CACHE_WT: return " WT";
1371 /* NB: please notice the memset */
1372 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1377 switch (INTEL_INFO(dev)->gen) {
1380 instdone[0] = I915_READ(INSTDONE);
1385 instdone[0] = I915_READ(INSTDONE_I965);
1386 instdone[1] = I915_READ(INSTDONE1);
1389 WARN_ONCE(1, "Unsupported platform\n");
1392 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1393 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1394 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1395 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);