drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 297 {
 298         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 299         int ret = IRQ_NONE;
 300         u32 de_iir, gt_iir, de_ier, pch_iir;
 301         u32 hotplug_mask;
 302         struct drm_i915_master_private *master_priv;
 303         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 304         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 305
 306         if (IS_GEN6(dev))
 307                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 308
 309         /* disable master interrupt before clearing iir  */
 310         de_ier = I915_READ(DEIER);
 311         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 312         (void)I915_READ(DEIER);
 313
 314         de_iir = I915_READ(DEIIR);
 315         gt_iir = I915_READ(GTIIR);
 316         pch_iir = I915_READ(SDEIIR);
 317
 318         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 319                 goto done;
 320
 321         if (HAS_PCH_CPT(dev))
 322                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 323         else
 324                 hotplug_mask = SDE_HOTPLUG_MASK;
 325
 326         ret = IRQ_HANDLED;
 327
 328         if (dev->primary->master) {
 329                 master_priv = dev->primary->master->driver_priv;
 330                 if (master_priv->sarea_priv)
 331                         master_priv->sarea_priv->last_dispatch =
 332                                 READ_BREADCRUMB(dev_priv);
 333         }
 334
 335         if (gt_iir & GT_PIPE_NOTIFY) {
 336                 u32 seqno = render_ring->get_seqno(dev, render_ring);
 337                 render_ring->irq_gem_seqno = seqno;
 338                 trace_i915_gem_request_complete(dev, seqno);
 339                 wake_up_all(&dev_priv->render_ring.irq_queue);
 340                 dev_priv->hangcheck_count = 0;
 341                 mod_timer(&dev_priv->hangcheck_timer,
 342                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 343         }
 344         if (gt_iir & bsd_usr_interrupt)
 345                 wake_up_all(&dev_priv->bsd_ring.irq_queue);
 346
 347         if (de_iir & DE_GSE)
 348                 intel_opregion_gse_intr(dev);
 349
 350         if (de_iir & DE_PLANEA_FLIP_DONE) {
 351                 intel_prepare_page_flip(dev, 0);
 352                 intel_finish_page_flip_plane(dev, 0);
 353         }
 354
 355         if (de_iir & DE_PLANEB_FLIP_DONE) {
 356                 intel_prepare_page_flip(dev, 1);
 357                 intel_finish_page_flip_plane(dev, 1);
 358         }
 359
 360         if (de_iir & DE_PIPEA_VBLANK)
 361                 drm_handle_vblank(dev, 0);
 362
 363         if (de_iir & DE_PIPEB_VBLANK)
 364                 drm_handle_vblank(dev, 1);
 365
 366         /* check event from PCH */
 367         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 368                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 369
 370         if (de_iir & DE_PCU_EVENT) {
 371                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 372                 i915_handle_rps_change(dev);
 373         }
 374
 375         /* should clear PCH hotplug event before clear CPU irq */
 376         I915_WRITE(SDEIIR, pch_iir);
 377         I915_WRITE(GTIIR, gt_iir);
 378         I915_WRITE(DEIIR, de_iir);
 379
 380 done:
 381         I915_WRITE(DEIER, de_ier);
 382         (void)I915_READ(DEIER);
 383
 384         return ret;
 385 }
 386
 387 /**
 388  * i915_error_work_func - do process context error handling work
 389  * @work: work struct
 390  *
 391  * Fire an error uevent so userspace can see that a hang or error
 392  * was detected.
 393  */
 394 static void i915_error_work_func(struct work_struct *work)
 395 {
 396         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 397                                                     error_work);
 398         struct drm_device *dev = dev_priv->dev;
 399         char *error_event[] = { "ERROR=1", NULL };
 400         char *reset_event[] = { "RESET=1", NULL };
 401         char *reset_done_event[] = { "ERROR=0", NULL };
 402
 403         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 404
 405         if (atomic_read(&dev_priv->mm.wedged)) {
 406                 DRM_DEBUG_DRIVER("resetting chip\n");
 407                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 408                 if (!i915_reset(dev, GRDOM_RENDER)) {
 409                         atomic_set(&dev_priv->mm.wedged, 0);
 410                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 411                 }
 412                 complete_all(&dev_priv->error_completion);
 413         }
 414 }
 415
 416 #ifdef CONFIG_DEBUG_FS
 417 static struct drm_i915_error_object *
 418 i915_error_object_create(struct drm_device *dev,
 419                          struct drm_gem_object *src)
 420 {
 421         drm_i915_private_t *dev_priv = dev->dev_private;
 422         struct drm_i915_error_object *dst;
 423         struct drm_i915_gem_object *src_priv;
 424         int page, page_count;
 425         u32 reloc_offset;
 426
 427         if (src == NULL)
 428                 return NULL;
 429
 430         src_priv = to_intel_bo(src);
 431         if (src_priv->pages == NULL)
 432                 return NULL;
 433
 434         page_count = src->size / PAGE_SIZE;
 435
 436         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 437         if (dst == NULL)
 438                 return NULL;
 439
 440         reloc_offset = src_priv->gtt_offset;
 441         for (page = 0; page < page_count; page++) {
 442                 unsigned long flags;
 443                 void __iomem *s;
 444                 void *d;
 445
 446                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 447                 if (d == NULL)
 448                         goto unwind;
 449
 450                 local_irq_save(flags);
 451                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 452                                              reloc_offset,
 453                                              KM_IRQ0);
 454                 memcpy_fromio(d, s, PAGE_SIZE);
 455                 io_mapping_unmap_atomic(s, KM_IRQ0);
 456                 local_irq_restore(flags);
 457
 458                 dst->pages[page] = d;
 459
 460                 reloc_offset += PAGE_SIZE;
 461         }
 462         dst->page_count = page_count;
 463         dst->gtt_offset = src_priv->gtt_offset;
 464
 465         return dst;
 466
 467 unwind:
 468         while (page--)
 469                 kfree(dst->pages[page]);
 470         kfree(dst);
 471         return NULL;
 472 }
 473
 474 static void
 475 i915_error_object_free(struct drm_i915_error_object *obj)
 476 {
 477         int page;
 478
 479         if (obj == NULL)
 480                 return;
 481
 482         for (page = 0; page < obj->page_count; page++)
 483                 kfree(obj->pages[page]);
 484
 485         kfree(obj);
 486 }
 487
 488 static void
 489 i915_error_state_free(struct drm_device *dev,
 490                       struct drm_i915_error_state *error)
 491 {
 492         i915_error_object_free(error->batchbuffer[0]);
 493         i915_error_object_free(error->batchbuffer[1]);
 494         i915_error_object_free(error->ringbuffer);
 495         kfree(error->active_bo);
 496         kfree(error->overlay);
 497         kfree(error);
 498 }
 499
 500 static u32
 501 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 502 {
 503         u32 cmd;
 504
 505         if (IS_I830(dev) || IS_845G(dev))
 506                 cmd = MI_BATCH_BUFFER;
 507         else if (INTEL_INFO(dev)->gen >= 4)
 508                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 509                        MI_BATCH_NON_SECURE_I965);
 510         else
 511                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 512
 513         return ring[0] == cmd ? ring[1] : 0;
 514 }
 515
 516 static u32
 517 i915_ringbuffer_last_batch(struct drm_device *dev)
 518 {
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         u32 head, bbaddr;
 521         u32 *ring;
 522
 523         /* Locate the current position in the ringbuffer and walk back
 524          * to find the most recently dispatched batch buffer.
 525          */
 526         bbaddr = 0;
 527         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 528         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 529
 530         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 531                 bbaddr = i915_get_bbaddr(dev, ring);
 532                 if (bbaddr)
 533                         break;
 534         }
 535
 536         if (bbaddr == 0) {
 537                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 538                                 + dev_priv->render_ring.size);
 539                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 540                         bbaddr = i915_get_bbaddr(dev, ring);
 541                         if (bbaddr)
 542                                 break;
 543                 }
 544         }
 545
 546         return bbaddr;
 547 }
 548
 549 /**
 550  * i915_capture_error_state - capture an error record for later analysis
 551  * @dev: drm device
 552  *
 553  * Should be called when an error is detected (either a hang or an error
 554  * interrupt) to capture error state from the time of the error.  Fills
 555  * out a structure which becomes available in debugfs for user level tools
 556  * to pick up.
 557  */
 558 static void i915_capture_error_state(struct drm_device *dev)
 559 {
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct drm_i915_gem_object *obj_priv;
 562         struct drm_i915_error_state *error;
 563         struct drm_gem_object *batchbuffer[2];
 564         unsigned long flags;
 565         u32 bbaddr;
 566         int count;
 567
 568         spin_lock_irqsave(&dev_priv->error_lock, flags);
 569         error = dev_priv->first_error;
 570         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 571         if (error)
 572                 return;
 573
 574         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 575         if (!error) {
 576                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 577                 return;
 578         }
 579
 580         DRM_DEBUG_DRIVER("generating error event\n");
 581
 582         error->seqno =
 583                 dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring);
 584         error->eir = I915_READ(EIR);
 585         error->pgtbl_er = I915_READ(PGTBL_ER);
 586         error->pipeastat = I915_READ(PIPEASTAT);
 587         error->pipebstat = I915_READ(PIPEBSTAT);
 588         error->instpm = I915_READ(INSTPM);
 589         if (INTEL_INFO(dev)->gen < 4) {
 590                 error->ipeir = I915_READ(IPEIR);
 591                 error->ipehr = I915_READ(IPEHR);
 592                 error->instdone = I915_READ(INSTDONE);
 593                 error->acthd = I915_READ(ACTHD);
 594                 error->bbaddr = 0;
 595         } else {
 596                 error->ipeir = I915_READ(IPEIR_I965);
 597                 error->ipehr = I915_READ(IPEHR_I965);
 598                 error->instdone = I915_READ(INSTDONE_I965);
 599                 error->instps = I915_READ(INSTPS);
 600                 error->instdone1 = I915_READ(INSTDONE1);
 601                 error->acthd = I915_READ(ACTHD_I965);
 602                 error->bbaddr = I915_READ64(BB_ADDR);
 603         }
 604
 605         bbaddr = i915_ringbuffer_last_batch(dev);
 606
 607         /* Grab the current batchbuffer, most likely to have crashed. */
 608         batchbuffer[0] = NULL;
 609         batchbuffer[1] = NULL;
 610         count = 0;
 611         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 612                 struct drm_gem_object *obj = &obj_priv->base;
 613
 614                 if (batchbuffer[0] == NULL &&
 615                     bbaddr >= obj_priv->gtt_offset &&
 616                     bbaddr < obj_priv->gtt_offset + obj->size)
 617                         batchbuffer[0] = obj;
 618
 619                 if (batchbuffer[1] == NULL &&
 620                     error->acthd >= obj_priv->gtt_offset &&
 621                     error->acthd < obj_priv->gtt_offset + obj->size)
 622                         batchbuffer[1] = obj;
 623
 624                 count++;
 625         }
 626         /* Scan the other lists for completeness for those bizarre errors. */
 627         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 628                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) {
 629                         struct drm_gem_object *obj = &obj_priv->base;
 630
 631                         if (batchbuffer[0] == NULL &&
 632                             bbaddr >= obj_priv->gtt_offset &&
 633                             bbaddr < obj_priv->gtt_offset + obj->size)
 634                                 batchbuffer[0] = obj;
 635
 636                         if (batchbuffer[1] == NULL &&
 637                             error->acthd >= obj_priv->gtt_offset &&
 638                             error->acthd < obj_priv->gtt_offset + obj->size)
 639                                 batchbuffer[1] = obj;
 640
 641                         if (batchbuffer[0] && batchbuffer[1])
 642                                 break;
 643                 }
 644         }
 645         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 646                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) {
 647                         struct drm_gem_object *obj = &obj_priv->base;
 648
 649                         if (batchbuffer[0] == NULL &&
 650                             bbaddr >= obj_priv->gtt_offset &&
 651                             bbaddr < obj_priv->gtt_offset + obj->size)
 652                                 batchbuffer[0] = obj;
 653
 654                         if (batchbuffer[1] == NULL &&
 655                             error->acthd >= obj_priv->gtt_offset &&
 656                             error->acthd < obj_priv->gtt_offset + obj->size)
 657                                 batchbuffer[1] = obj;
 658
 659                         if (batchbuffer[0] && batchbuffer[1])
 660                                 break;
 661                 }
 662         }
 663
 664         /* We need to copy these to an anonymous buffer as the simplest
 665          * method to avoid being overwritten by userspace.
 666          */
 667         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 668         if (batchbuffer[1] != batchbuffer[0])
 669                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 670         else
 671                 error->batchbuffer[1] = NULL;
 672
 673         /* Record the ringbuffer */
 674         error->ringbuffer = i915_error_object_create(dev,
 675                         dev_priv->render_ring.gem_object);
 676
 677         /* Record buffers on the active list. */
 678         error->active_bo = NULL;
 679         error->active_bo_count = 0;
 680
 681         if (count)
 682                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 683                                            GFP_ATOMIC);
 684
 685         if (error->active_bo) {
 686                 int i = 0;
 687                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 688                         struct drm_gem_object *obj = &obj_priv->base;
 689
 690                         error->active_bo[i].size = obj->size;
 691                         error->active_bo[i].name = obj->name;
 692                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 693                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 694                         error->active_bo[i].read_domains = obj->read_domains;
 695                         error->active_bo[i].write_domain = obj->write_domain;
 696                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 697                         error->active_bo[i].pinned = 0;
 698                         if (obj_priv->pin_count > 0)
 699                                 error->active_bo[i].pinned = 1;
 700                         if (obj_priv->user_pin_count > 0)
 701                                 error->active_bo[i].pinned = -1;
 702                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 703                         error->active_bo[i].dirty = obj_priv->dirty;
 704                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 705
 706                         if (++i == count)
 707                                 break;
 708                 }
 709                 error->active_bo_count = i;
 710         }
 711
 712         do_gettimeofday(&error->time);
 713
 714         error->overlay = intel_overlay_capture_error_state(dev);
 715
 716         spin_lock_irqsave(&dev_priv->error_lock, flags);
 717         if (dev_priv->first_error == NULL) {
 718                 dev_priv->first_error = error;
 719                 error = NULL;
 720         }
 721         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 722
 723         if (error)
 724                 i915_error_state_free(dev, error);
 725 }
 726
 727 void i915_destroy_error_state(struct drm_device *dev)
 728 {
 729         struct drm_i915_private *dev_priv = dev->dev_private;
 730         struct drm_i915_error_state *error;
 731
 732         spin_lock(&dev_priv->error_lock);
 733         error = dev_priv->first_error;
 734         dev_priv->first_error = NULL;
 735         spin_unlock(&dev_priv->error_lock);
 736
 737         if (error)
 738                 i915_error_state_free(dev, error);
 739 }
 740 #else
 741 #define i915_capture_error_state(x)
 742 #endif
 743
 744 static void i915_report_and_clear_eir(struct drm_device *dev)
 745 {
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         u32 eir = I915_READ(EIR);
 748
 749         if (!eir)
 750                 return;
 751
 752         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 753                eir);
 754
 755         if (IS_G4X(dev)) {
 756                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 757                         u32 ipeir = I915_READ(IPEIR_I965);
 758
 759                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 760                                I915_READ(IPEIR_I965));
 761                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 762                                I915_READ(IPEHR_I965));
 763                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 764                                I915_READ(INSTDONE_I965));
 765                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 766                                I915_READ(INSTPS));
 767                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 768                                I915_READ(INSTDONE1));
 769                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 770                                I915_READ(ACTHD_I965));
 771                         I915_WRITE(IPEIR_I965, ipeir);
 772                         (void)I915_READ(IPEIR_I965);
 773                 }
 774                 if (eir & GM45_ERROR_PAGE_TABLE) {
 775                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 776                         printk(KERN_ERR "page table error\n");
 777                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 778                                pgtbl_err);
 779                         I915_WRITE(PGTBL_ER, pgtbl_err);
 780                         (void)I915_READ(PGTBL_ER);
 781                 }
 782         }
 783
 784         if (!IS_GEN2(dev)) {
 785                 if (eir & I915_ERROR_PAGE_TABLE) {
 786                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 787                         printk(KERN_ERR "page table error\n");
 788                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 789                                pgtbl_err);
 790                         I915_WRITE(PGTBL_ER, pgtbl_err);
 791                         (void)I915_READ(PGTBL_ER);
 792                 }
 793         }
 794
 795         if (eir & I915_ERROR_MEMORY_REFRESH) {
 796                 u32 pipea_stats = I915_READ(PIPEASTAT);
 797                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 798
 799                 printk(KERN_ERR "memory refresh error\n");
 800                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 801                        pipea_stats);
 802                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 803                        pipeb_stats);
 804                 /* pipestat has already been acked */
 805         }
 806         if (eir & I915_ERROR_INSTRUCTION) {
 807                 printk(KERN_ERR "instruction error\n");
 808                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 809                        I915_READ(INSTPM));
 810                 if (INTEL_INFO(dev)->gen < 4) {
 811                         u32 ipeir = I915_READ(IPEIR);
 812
 813                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 814                                I915_READ(IPEIR));
 815                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 816                                I915_READ(IPEHR));
 817                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 818                                I915_READ(INSTDONE));
 819                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 820                                I915_READ(ACTHD));
 821                         I915_WRITE(IPEIR, ipeir);
 822                         (void)I915_READ(IPEIR);
 823                 } else {
 824                         u32 ipeir = I915_READ(IPEIR_I965);
 825
 826                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 827                                I915_READ(IPEIR_I965));
 828                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 829                                I915_READ(IPEHR_I965));
 830                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 831                                I915_READ(INSTDONE_I965));
 832                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 833                                I915_READ(INSTPS));
 834                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 835                                I915_READ(INSTDONE1));
 836                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 837                                I915_READ(ACTHD_I965));
 838                         I915_WRITE(IPEIR_I965, ipeir);
 839                         (void)I915_READ(IPEIR_I965);
 840                 }
 841         }
 842
 843         I915_WRITE(EIR, eir);
 844         (void)I915_READ(EIR);
 845         eir = I915_READ(EIR);
 846         if (eir) {
 847                 /*
 848                  * some errors might have become stuck,
 849                  * mask them.
 850                  */
 851                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 852                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 853                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 854         }
 855 }
 856
 857 /**
 858  * i915_handle_error - handle an error interrupt
 859  * @dev: drm device
 860  *
 861  * Do some basic checking of regsiter state at error interrupt time and
 862  * dump it to the syslog.  Also call i915_capture_error_state() to make
 863  * sure we get a record and make it available in debugfs.  Fire a uevent
 864  * so userspace knows something bad happened (should trigger collection
 865  * of a ring dump etc.).
 866  */
 867 static void i915_handle_error(struct drm_device *dev, bool wedged)
 868 {
 869         struct drm_i915_private *dev_priv = dev->dev_private;
 870
 871         i915_capture_error_state(dev);
 872         i915_report_and_clear_eir(dev);
 873
 874         if (wedged) {
 875                 INIT_COMPLETION(dev_priv->error_completion);
 876                 atomic_set(&dev_priv->mm.wedged, 1);
 877
 878                 /*
 879                  * Wakeup waiting processes so they don't hang
 880                  */
 881                 wake_up_all(&dev_priv->render_ring.irq_queue);
 882                 if (HAS_BSD(dev))
 883                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 884         }
 885
 886         queue_work(dev_priv->wq, &dev_priv->error_work);
 887 }
 888
 889 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 890 {
 891         drm_i915_private_t *dev_priv = dev->dev_private;
 892         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 894         struct drm_i915_gem_object *obj_priv;
 895         struct intel_unpin_work *work;
 896         unsigned long flags;
 897         bool stall_detected;
 898
 899         /* Ignore early vblank irqs */
 900         if (intel_crtc == NULL)
 901                 return;
 902
 903         spin_lock_irqsave(&dev->event_lock, flags);
 904         work = intel_crtc->unpin_work;
 905
 906         if (work == NULL || work->pending || !work->enable_stall_check) {
 907                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 908                 spin_unlock_irqrestore(&dev->event_lock, flags);
 909                 return;
 910         }
 911
 912         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 913         obj_priv = to_intel_bo(work->pending_flip_obj);
 914         if (INTEL_INFO(dev)->gen >= 4) {
 915                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 916                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 917         } else {
 918                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 919                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 920                                                         crtc->y * crtc->fb->pitch +
 921                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 922         }
 923
 924         spin_unlock_irqrestore(&dev->event_lock, flags);
 925
 926         if (stall_detected) {
 927                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 928                 intel_prepare_page_flip(dev, intel_crtc->plane);
 929         }
 930 }
 931
 932 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 933 {
 934         struct drm_device *dev = (struct drm_device *) arg;
 935         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 936         struct drm_i915_master_private *master_priv;
 937         u32 iir, new_iir;
 938         u32 pipea_stats, pipeb_stats;
 939         u32 vblank_status;
 940         int vblank = 0;
 941         unsigned long irqflags;
 942         int irq_received;
 943         int ret = IRQ_NONE;
 944         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 945
 946         atomic_inc(&dev_priv->irq_received);
 947
 948         if (HAS_PCH_SPLIT(dev))
 949                 return ironlake_irq_handler(dev);
 950
 951         iir = I915_READ(IIR);
 952
 953         if (INTEL_INFO(dev)->gen >= 4)
 954                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 955         else
 956                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 957
 958         for (;;) {
 959                 irq_received = iir != 0;
 960
 961                 /* Can't rely on pipestat interrupt bit in iir as it might
 962                  * have been cleared after the pipestat interrupt was received.
 963                  * It doesn't set the bit in iir again, but it still produces
 964                  * interrupts (for non-MSI).
 965                  */
 966                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 967                 pipea_stats = I915_READ(PIPEASTAT);
 968                 pipeb_stats = I915_READ(PIPEBSTAT);
 969
 970                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 971                         i915_handle_error(dev, false);
 972
 973                 /*
 974                  * Clear the PIPE(A|B)STAT regs before the IIR
 975                  */
 976                 if (pipea_stats & 0x8000ffff) {
 977                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 978                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 979                         I915_WRITE(PIPEASTAT, pipea_stats);
 980                         irq_received = 1;
 981                 }
 982
 983                 if (pipeb_stats & 0x8000ffff) {
 984                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 985                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 986                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 987                         irq_received = 1;
 988                 }
 989                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 990
 991                 if (!irq_received)
 992                         break;
 993
 994                 ret = IRQ_HANDLED;
 995
 996                 /* Consume port.  Then clear IIR or we'll miss events */
 997                 if ((I915_HAS_HOTPLUG(dev)) &&
 998                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 999                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1000
1001                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1002                                   hotplug_status);
1003                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1004                                 queue_work(dev_priv->wq,
1005                                            &dev_priv->hotplug_work);
1006
1007                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1008                         I915_READ(PORT_HOTPLUG_STAT);
1009                 }
1010
1011                 I915_WRITE(IIR, iir);
1012                 new_iir = I915_READ(IIR); /* Flush posted writes */
1013
1014                 if (dev->primary->master) {
1015                         master_priv = dev->primary->master->driver_priv;
1016                         if (master_priv->sarea_priv)
1017                                 master_priv->sarea_priv->last_dispatch =
1018                                         READ_BREADCRUMB(dev_priv);
1019                 }
1020
1021                 if (iir & I915_USER_INTERRUPT) {
1022                         u32 seqno = render_ring->get_seqno(dev, render_ring);
1023                         render_ring->irq_gem_seqno = seqno;
1024                         trace_i915_gem_request_complete(dev, seqno);
1025                         wake_up_all(&dev_priv->render_ring.irq_queue);
1026                         dev_priv->hangcheck_count = 0;
1027                         mod_timer(&dev_priv->hangcheck_timer,
1028                                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1029                 }
1030
1031                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1032                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1033
1034                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1035                         intel_prepare_page_flip(dev, 0);
1036                         if (dev_priv->flip_pending_is_done)
1037                                 intel_finish_page_flip_plane(dev, 0);
1038                 }
1039
1040                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1041                         intel_prepare_page_flip(dev, 1);
1042                         if (dev_priv->flip_pending_is_done)
1043                                 intel_finish_page_flip_plane(dev, 1);
1044                 }
1045
1046                 if (pipea_stats & vblank_status) {
1047                         vblank++;
1048                         drm_handle_vblank(dev, 0);
1049                         if (!dev_priv->flip_pending_is_done) {
1050                                 i915_pageflip_stall_check(dev, 0);
1051                                 intel_finish_page_flip(dev, 0);
1052                         }
1053                 }
1054
1055                 if (pipeb_stats & vblank_status) {
1056                         vblank++;
1057                         drm_handle_vblank(dev, 1);
1058                         if (!dev_priv->flip_pending_is_done) {
1059                                 i915_pageflip_stall_check(dev, 1);
1060                                 intel_finish_page_flip(dev, 1);
1061                         }
1062                 }
1063
1064                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1065                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1066                     (iir & I915_ASLE_INTERRUPT))
1067                         intel_opregion_asle_intr(dev);
1068
1069                 /* With MSI, interrupts are only generated when iir
1070                  * transitions from zero to nonzero.  If another bit got
1071                  * set while we were handling the existing iir bits, then
1072                  * we would never get another interrupt.
1073                  *
1074                  * This is fine on non-MSI as well, as if we hit this path
1075                  * we avoid exiting the interrupt handler only to generate
1076                  * another one.
1077                  *
1078                  * Note that for MSI this could cause a stray interrupt report
1079                  * if an interrupt landed in the time between writing IIR and
1080                  * the posting read.  This should be rare enough to never
1081                  * trigger the 99% of 100,000 interrupts test for disabling
1082                  * stray interrupts.
1083                  */
1084                 iir = new_iir;
1085         }
1086
1087         return ret;
1088 }
1089
1090 static int i915_emit_irq(struct drm_device * dev)
1091 {
1092         drm_i915_private_t *dev_priv = dev->dev_private;
1093         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1094
1095         i915_kernel_lost_context(dev);
1096
1097         DRM_DEBUG_DRIVER("\n");
1098
1099         dev_priv->counter++;
1100         if (dev_priv->counter > 0x7FFFFFFFUL)
1101                 dev_priv->counter = 1;
1102         if (master_priv->sarea_priv)
1103                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1104
1105         BEGIN_LP_RING(4);
1106         OUT_RING(MI_STORE_DWORD_INDEX);
1107         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1108         OUT_RING(dev_priv->counter);
1109         OUT_RING(MI_USER_INTERRUPT);
1110         ADVANCE_LP_RING();
1111
1112         return dev_priv->counter;
1113 }
1114
1115 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1116 {
1117         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1118         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1119
1120         if (dev_priv->trace_irq_seqno == 0)
1121                 render_ring->user_irq_get(dev, render_ring);
1122
1123         dev_priv->trace_irq_seqno = seqno;
1124 }
1125
1126 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1127 {
1128         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1129         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1130         int ret = 0;
1131         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1132
1133         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1134                   READ_BREADCRUMB(dev_priv));
1135
1136         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1137                 if (master_priv->sarea_priv)
1138                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1139                 return 0;
1140         }
1141
1142         if (master_priv->sarea_priv)
1143                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1144
1145         render_ring->user_irq_get(dev, render_ring);
1146         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1147                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1148         render_ring->user_irq_put(dev, render_ring);
1149
1150         if (ret == -EBUSY) {
1151                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1152                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1153         }
1154
1155         return ret;
1156 }
1157
1158 /* Needs the lock as it touches the ring.
1159  */
1160 int i915_irq_emit(struct drm_device *dev, void *data,
1161                          struct drm_file *file_priv)
1162 {
1163         drm_i915_private_t *dev_priv = dev->dev_private;
1164         drm_i915_irq_emit_t *emit = data;
1165         int result;
1166
1167         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1168                 DRM_ERROR("called with no initialization\n");
1169                 return -EINVAL;
1170         }
1171
1172         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1173
1174         mutex_lock(&dev->struct_mutex);
1175         result = i915_emit_irq(dev);
1176         mutex_unlock(&dev->struct_mutex);
1177
1178         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1179                 DRM_ERROR("copy_to_user\n");
1180                 return -EFAULT;
1181         }
1182
1183         return 0;
1184 }
1185
1186 /* Doesn't need the hardware lock.
1187  */
1188 int i915_irq_wait(struct drm_device *dev, void *data,
1189                          struct drm_file *file_priv)
1190 {
1191         drm_i915_private_t *dev_priv = dev->dev_private;
1192         drm_i915_irq_wait_t *irqwait = data;
1193
1194         if (!dev_priv) {
1195                 DRM_ERROR("called with no initialization\n");
1196                 return -EINVAL;
1197         }
1198
1199         return i915_wait_irq(dev, irqwait->irq_seq);
1200 }
1201
1202 /* Called from drm generic code, passed 'crtc' which
1203  * we use as a pipe index
1204  */
1205 int i915_enable_vblank(struct drm_device *dev, int pipe)
1206 {
1207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1208         unsigned long irqflags;
1209
1210         if (!i915_pipe_enabled(dev, pipe))
1211                 return -EINVAL;
1212
1213         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1214         if (HAS_PCH_SPLIT(dev))
1215                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1216                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1217         else if (INTEL_INFO(dev)->gen >= 4)
1218                 i915_enable_pipestat(dev_priv, pipe,
1219                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1220         else
1221                 i915_enable_pipestat(dev_priv, pipe,
1222                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1223         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1224         return 0;
1225 }
1226
1227 /* Called from drm generic code, passed 'crtc' which
1228  * we use as a pipe index
1229  */
1230 void i915_disable_vblank(struct drm_device *dev, int pipe)
1231 {
1232         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1233         unsigned long irqflags;
1234
1235         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1236         if (HAS_PCH_SPLIT(dev))
1237                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1238                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1239         else
1240                 i915_disable_pipestat(dev_priv, pipe,
1241                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1242                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1243         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1244 }
1245
1246 void i915_enable_interrupt (struct drm_device *dev)
1247 {
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249
1250         if (!HAS_PCH_SPLIT(dev))
1251                 intel_opregion_enable_asle(dev);
1252         dev_priv->irq_enabled = 1;
1253 }
1254
1255
1256 /* Set the vblank monitor pipe
1257  */
1258 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1259                          struct drm_file *file_priv)
1260 {
1261         drm_i915_private_t *dev_priv = dev->dev_private;
1262
1263         if (!dev_priv) {
1264                 DRM_ERROR("called with no initialization\n");
1265                 return -EINVAL;
1266         }
1267
1268         return 0;
1269 }
1270
1271 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1272                          struct drm_file *file_priv)
1273 {
1274         drm_i915_private_t *dev_priv = dev->dev_private;
1275         drm_i915_vblank_pipe_t *pipe = data;
1276
1277         if (!dev_priv) {
1278                 DRM_ERROR("called with no initialization\n");
1279                 return -EINVAL;
1280         }
1281
1282         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1283
1284         return 0;
1285 }
1286
1287 /**
1288  * Schedule buffer swap at given vertical blank.
1289  */
1290 int i915_vblank_swap(struct drm_device *dev, void *data,
1291                      struct drm_file *file_priv)
1292 {
1293         /* The delayed swap mechanism was fundamentally racy, and has been
1294          * removed.  The model was that the client requested a delayed flip/swap
1295          * from the kernel, then waited for vblank before continuing to perform
1296          * rendering.  The problem was that the kernel might wake the client
1297          * up before it dispatched the vblank swap (since the lock has to be
1298          * held while touching the ringbuffer), in which case the client would
1299          * clear and start the next frame before the swap occurred, and
1300          * flicker would occur in addition to likely missing the vblank.
1301          *
1302          * In the absence of this ioctl, userland falls back to a correct path
1303          * of waiting for a vblank, then dispatching the swap on its own.
1304          * Context switching to userland and back is plenty fast enough for
1305          * meeting the requirements of vblank swapping.
1306          */
1307         return -EINVAL;
1308 }
1309
1310 static struct drm_i915_gem_request *
1311 i915_get_tail_request(struct drm_device *dev)
1312 {
1313         drm_i915_private_t *dev_priv = dev->dev_private;
1314         return list_entry(dev_priv->render_ring.request_list.prev,
1315                         struct drm_i915_gem_request, list);
1316 }
1317
1318 /**
1319  * This is called when the chip hasn't reported back with completed
1320  * batchbuffers in a long time. The first time this is called we simply record
1321  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1322  * again, we assume the chip is wedged and try to fix it.
1323  */
1324 void i915_hangcheck_elapsed(unsigned long data)
1325 {
1326         struct drm_device *dev = (struct drm_device *)data;
1327         drm_i915_private_t *dev_priv = dev->dev_private;
1328         uint32_t acthd, instdone, instdone1;
1329
1330         if (INTEL_INFO(dev)->gen < 4) {
1331                 acthd = I915_READ(ACTHD);
1332                 instdone = I915_READ(INSTDONE);
1333                 instdone1 = 0;
1334         } else {
1335                 acthd = I915_READ(ACTHD_I965);
1336                 instdone = I915_READ(INSTDONE_I965);
1337                 instdone1 = I915_READ(INSTDONE1);
1338         }
1339
1340         /* If all work is done then ACTHD clearly hasn't advanced. */
1341         if (list_empty(&dev_priv->render_ring.request_list) ||
1342                 i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring),
1343                                   i915_get_tail_request(dev)->seqno)) {
1344                 bool missed_wakeup = false;
1345
1346                 dev_priv->hangcheck_count = 0;
1347
1348                 /* Issue a wake-up to catch stuck h/w. */
1349                 if (dev_priv->render_ring.waiting_gem_seqno &&
1350                     waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1351                         wake_up_all(&dev_priv->render_ring.irq_queue);
1352                         missed_wakeup = true;
1353                 }
1354
1355                 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1356                     waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1357                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1358                         missed_wakeup = true;
1359                 }
1360
1361                 if (missed_wakeup)
1362                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1363                 return;
1364         }
1365
1366         if (dev_priv->last_acthd == acthd &&
1367             dev_priv->last_instdone == instdone &&
1368             dev_priv->last_instdone1 == instdone1) {
1369                 if (dev_priv->hangcheck_count++ > 1) {
1370                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1371
1372                         if (!IS_GEN2(dev)) {
1373                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1374                                  * If so we can simply poke the RB_WAIT bit
1375                                  * and break the hang. This should work on
1376                                  * all but the second generation chipsets.
1377                                  */
1378                                 u32 tmp = I915_READ(PRB0_CTL);
1379                                 if (tmp & RING_WAIT) {
1380                                         I915_WRITE(PRB0_CTL, tmp);
1381                                         POSTING_READ(PRB0_CTL);
1382                                         goto out;
1383                                 }
1384                         }
1385
1386                         i915_handle_error(dev, true);
1387                         return;
1388                 }
1389         } else {
1390                 dev_priv->hangcheck_count = 0;
1391
1392                 dev_priv->last_acthd = acthd;
1393                 dev_priv->last_instdone = instdone;
1394                 dev_priv->last_instdone1 = instdone1;
1395         }
1396
1397 out:
1398         /* Reset timer case chip hangs without another request being added */
1399         mod_timer(&dev_priv->hangcheck_timer,
1400                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1401 }
1402
1403 /* drm_dma.h hooks
1404 */
1405 static void ironlake_irq_preinstall(struct drm_device *dev)
1406 {
1407         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1408
1409         I915_WRITE(HWSTAM, 0xeffe);
1410
1411         /* XXX hotplug from PCH */
1412
1413         I915_WRITE(DEIMR, 0xffffffff);
1414         I915_WRITE(DEIER, 0x0);
1415         (void) I915_READ(DEIER);
1416
1417         /* and GT */
1418         I915_WRITE(GTIMR, 0xffffffff);
1419         I915_WRITE(GTIER, 0x0);
1420         (void) I915_READ(GTIER);
1421
1422         /* south display irq */
1423         I915_WRITE(SDEIMR, 0xffffffff);
1424         I915_WRITE(SDEIER, 0x0);
1425         (void) I915_READ(SDEIER);
1426 }
1427
1428 static int ironlake_irq_postinstall(struct drm_device *dev)
1429 {
1430         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1431         /* enable kind of interrupts always enabled */
1432         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1433                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1434         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1435         u32 hotplug_mask;
1436
1437         dev_priv->irq_mask_reg = ~display_mask;
1438         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1439
1440         /* should always can generate irq */
1441         I915_WRITE(DEIIR, I915_READ(DEIIR));
1442         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1443         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1444         (void) I915_READ(DEIER);
1445
1446         if (IS_GEN6(dev))
1447                 render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT;
1448
1449         dev_priv->gt_irq_mask_reg = ~render_mask;
1450         dev_priv->gt_irq_enable_reg = render_mask;
1451
1452         I915_WRITE(GTIIR, I915_READ(GTIIR));
1453         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1454         if (IS_GEN6(dev)) {
1455                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1456                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1457         }
1458
1459         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1460         (void) I915_READ(GTIER);
1461
1462         if (HAS_PCH_CPT(dev)) {
1463                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1464                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1465         } else {
1466                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1467                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1468         }
1469
1470         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1471         dev_priv->pch_irq_enable_reg = hotplug_mask;
1472
1473         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1474         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1475         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1476         (void) I915_READ(SDEIER);
1477
1478         if (IS_IRONLAKE_M(dev)) {
1479                 /* Clear & enable PCU event interrupts */
1480                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1481                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1482                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1483         }
1484
1485         return 0;
1486 }
1487
1488 void i915_driver_irq_preinstall(struct drm_device * dev)
1489 {
1490         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1491
1492         atomic_set(&dev_priv->irq_received, 0);
1493
1494         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1495         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1496
1497         if (HAS_PCH_SPLIT(dev)) {
1498                 ironlake_irq_preinstall(dev);
1499                 return;
1500         }
1501
1502         if (I915_HAS_HOTPLUG(dev)) {
1503                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1504                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1505         }
1506
1507         I915_WRITE(HWSTAM, 0xeffe);
1508         I915_WRITE(PIPEASTAT, 0);
1509         I915_WRITE(PIPEBSTAT, 0);
1510         I915_WRITE(IMR, 0xffffffff);
1511         I915_WRITE(IER, 0x0);
1512         (void) I915_READ(IER);
1513 }
1514
1515 /*
1516  * Must be called after intel_modeset_init or hotplug interrupts won't be
1517  * enabled correctly.
1518  */
1519 int i915_driver_irq_postinstall(struct drm_device *dev)
1520 {
1521         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1522         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1523         u32 error_mask;
1524
1525         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1526
1527         if (HAS_BSD(dev))
1528                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1529
1530         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1531
1532         if (HAS_PCH_SPLIT(dev))
1533                 return ironlake_irq_postinstall(dev);
1534
1535         /* Unmask the interrupts that we always want on. */
1536         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1537
1538         dev_priv->pipestat[0] = 0;
1539         dev_priv->pipestat[1] = 0;
1540
1541         if (I915_HAS_HOTPLUG(dev)) {
1542                 /* Enable in IER... */
1543                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1544                 /* and unmask in IMR */
1545                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1546         }
1547
1548         /*
1549          * Enable some error detection, note the instruction error mask
1550          * bit is reserved, so we leave it masked.
1551          */
1552         if (IS_G4X(dev)) {
1553                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1554                                GM45_ERROR_MEM_PRIV |
1555                                GM45_ERROR_CP_PRIV |
1556                                I915_ERROR_MEMORY_REFRESH);
1557         } else {
1558                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1559                                I915_ERROR_MEMORY_REFRESH);
1560         }
1561         I915_WRITE(EMR, error_mask);
1562
1563         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1564         I915_WRITE(IER, enable_mask);
1565         (void) I915_READ(IER);
1566
1567         if (I915_HAS_HOTPLUG(dev)) {
1568                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1569
1570                 /* Note HDMI and DP share bits */
1571                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1572                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1573                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1574                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1575                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1576                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1577                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1578                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1579                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1580                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1581                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1582                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1583
1584                         /* Programming the CRT detection parameters tends
1585                            to generate a spurious hotplug event about three
1586                            seconds later.  So just do it once.
1587                         */
1588                         if (IS_G4X(dev))
1589                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1590                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1591                 }
1592
1593                 /* Ignore TV since it's buggy */
1594
1595                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1596         }
1597
1598         intel_opregion_enable_asle(dev);
1599
1600         return 0;
1601 }
1602
1603 static void ironlake_irq_uninstall(struct drm_device *dev)
1604 {
1605         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1606         I915_WRITE(HWSTAM, 0xffffffff);
1607
1608         I915_WRITE(DEIMR, 0xffffffff);
1609         I915_WRITE(DEIER, 0x0);
1610         I915_WRITE(DEIIR, I915_READ(DEIIR));
1611
1612         I915_WRITE(GTIMR, 0xffffffff);
1613         I915_WRITE(GTIER, 0x0);
1614         I915_WRITE(GTIIR, I915_READ(GTIIR));
1615 }
1616
1617 void i915_driver_irq_uninstall(struct drm_device * dev)
1618 {
1619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1620
1621         if (!dev_priv)
1622                 return;
1623
1624         dev_priv->vblank_pipe = 0;
1625
1626         if (HAS_PCH_SPLIT(dev)) {
1627                 ironlake_irq_uninstall(dev);
1628                 return;
1629         }
1630
1631         if (I915_HAS_HOTPLUG(dev)) {
1632                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1633                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1634         }
1635
1636         I915_WRITE(HWSTAM, 0xffffffff);
1637         I915_WRITE(PIPEASTAT, 0);
1638         I915_WRITE(PIPEBSTAT, 0);
1639         I915_WRITE(IMR, 0xffffffff);
1640         I915_WRITE(IER, 0x0);
1641
1642         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1643         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1644         I915_WRITE(IIR, I915_READ(IIR));
1645 }