drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x80009010, 0x000000C0, 0x1 },
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x80007011, 0x000000C0, 0x1 },
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x80005012, 0x000000C0, 0x1 },
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x80007011, 0x000000CD, 0x1 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x80005012, 0x000000C0, 0x1 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x3 },
 162         { 0x80009010, 0x000000C0, 0x3 },
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x3 },
 165         { 0x80007011, 0x000000C0, 0x3 },
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x3 },
 168 };
 169
 170 /*
 171  * Skylake H and S
 172  * eDP 1.4 low vswing translation parameters
 173  */
 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 175         { 0x00000018, 0x000000A8, 0x0 },
 176         { 0x00004013, 0x000000A9, 0x0 },
 177         { 0x00007011, 0x000000A2, 0x0 },
 178         { 0x00009010, 0x0000009C, 0x0 },
 179         { 0x00000018, 0x000000A9, 0x0 },
 180         { 0x00006013, 0x000000A2, 0x0 },
 181         { 0x00007011, 0x000000A6, 0x0 },
 182         { 0x00000018, 0x000000AB, 0x0 },
 183         { 0x00007013, 0x0000009F, 0x0 },
 184         { 0x00000018, 0x000000DF, 0x0 },
 185 };
 186
 187 /*
 188  * Skylake U
 189  * eDP 1.4 low vswing translation parameters
 190  */
 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 192         { 0x00000018, 0x000000A8, 0x0 },
 193         { 0x00004013, 0x000000A9, 0x0 },
 194         { 0x00007011, 0x000000A2, 0x0 },
 195         { 0x00009010, 0x0000009C, 0x0 },
 196         { 0x00000018, 0x000000A9, 0x0 },
 197         { 0x00006013, 0x000000A2, 0x0 },
 198         { 0x00007011, 0x000000A6, 0x0 },
 199         { 0x00002016, 0x000000AB, 0x0 },
 200         { 0x00005013, 0x0000009F, 0x0 },
 201         { 0x00000018, 0x000000DF, 0x0 },
 202 };
 203
 204 /*
 205  * Skylake Y
 206  * eDP 1.4 low vswing translation parameters
 207  */
 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 209         { 0x00000018, 0x000000A8, 0x0 },
 210         { 0x00004013, 0x000000AB, 0x0 },
 211         { 0x00007011, 0x000000A4, 0x0 },
 212         { 0x00009010, 0x000000DF, 0x0 },
 213         { 0x00000018, 0x000000AA, 0x0 },
 214         { 0x00006013, 0x000000A4, 0x0 },
 215         { 0x00007011, 0x0000009D, 0x0 },
 216         { 0x00000018, 0x000000A0, 0x0 },
 217         { 0x00006012, 0x000000DF, 0x0 },
 218         { 0x00000018, 0x0000008A, 0x0 },
 219 };
 220
 221 /* Skylake U, H and S */
 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 223         { 0x00000018, 0x000000AC, 0x0 },
 224         { 0x00005012, 0x0000009D, 0x0 },
 225         { 0x00007011, 0x00000088, 0x0 },
 226         { 0x00000018, 0x000000A1, 0x0 },
 227         { 0x00000018, 0x00000098, 0x0 },
 228         { 0x00004013, 0x00000088, 0x0 },
 229         { 0x80006012, 0x000000CD, 0x1 },
 230         { 0x00000018, 0x000000DF, 0x0 },
 231         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 232         { 0x80003015, 0x000000C0, 0x1 },
 233         { 0x80000018, 0x000000C0, 0x1 },
 234 };
 235
 236 /* Skylake Y */
 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 238         { 0x00000018, 0x000000A1, 0x0 },
 239         { 0x00005012, 0x000000DF, 0x0 },
 240         { 0x80007011, 0x000000CB, 0x3 },
 241         { 0x00000018, 0x000000A4, 0x0 },
 242         { 0x00000018, 0x0000009D, 0x0 },
 243         { 0x00004013, 0x00000080, 0x0 },
 244         { 0x80006013, 0x000000C0, 0x3 },
 245         { 0x00000018, 0x0000008A, 0x0 },
 246         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 247         { 0x80003015, 0x000000C0, 0x3 },
 248         { 0x80000018, 0x000000C0, 0x3 },
 249 };
 250
 251 struct bxt_ddi_buf_trans {
 252         u32 margin;     /* swing value */
 253         u32 scale;      /* scale value */
 254         u32 enable;     /* scale enable */
 255         u32 deemphasis;
 256         bool default_index; /* true if the entry represents default value */
 257 };
 258
 259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 260                                         /* Idx  NT mV diff      db  */
 261         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 262         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 263         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 264         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 265         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 266         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 267         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 268         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 269         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 270         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 271 };
 272
 273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 274                                         /* Idx  NT mV diff      db  */
 275         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 276         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 277         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 278         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 279         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 280         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 281         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 282         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 283         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 284         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 285 };
 286
 287 /* BSpec has 2 recommended values - entries 0 and 8.
 288  * Using the entry with higher vswing.
 289  */
 290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 291                                         /* Idx  NT mV diff      db  */
 292         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 293         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 294         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 295         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 296         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 297         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 298         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 299         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 300         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 301         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 302 };
 303
 304 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 305 {
 306         switch (encoder->type) {
 307         case INTEL_OUTPUT_DP_MST:
 308                 return enc_to_mst(&encoder->base)->primary->port;
 309         case INTEL_OUTPUT_DP:
 310         case INTEL_OUTPUT_EDP:
 311         case INTEL_OUTPUT_HDMI:
 312         case INTEL_OUTPUT_UNKNOWN:
 313                 return enc_to_dig_port(&encoder->base)->port;
 314         case INTEL_OUTPUT_ANALOG:
 315                 return PORT_E;
 316         default:
 317                 MISSING_CASE(encoder->type);
 318                 return PORT_A;
 319         }
 320 }
 321
 322 static const struct ddi_buf_trans *
 323 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 324 {
 325         if (dev_priv->vbt.edp.low_vswing) {
 326                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 327                 return bdw_ddi_translations_edp;
 328         } else {
 329                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 330                 return bdw_ddi_translations_dp;
 331         }
 332 }
 333
 334 static const struct ddi_buf_trans *
 335 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 336 {
 337         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 338                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 339                 return skl_y_ddi_translations_dp;
 340         } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 341                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 342                 return skl_u_ddi_translations_dp;
 343         } else {
 344                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 345                 return skl_ddi_translations_dp;
 346         }
 347 }
 348
 349 static const struct ddi_buf_trans *
 350 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 351 {
 352         if (dev_priv->vbt.edp.low_vswing) {
 353                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 354                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 355                         return skl_y_ddi_translations_edp;
 356                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 357                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 358                         return skl_u_ddi_translations_edp;
 359                 } else {
 360                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 361                         return skl_ddi_translations_edp;
 362                 }
 363         }
 364
 365         return skl_get_buf_trans_dp(dev_priv, n_entries);
 366 }
 367
 368 static const struct ddi_buf_trans *
 369 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 370 {
 371         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 372                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 373                 return skl_y_ddi_translations_hdmi;
 374         } else {
 375                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 376                 return skl_ddi_translations_hdmi;
 377         }
 378 }
 379
 380 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 381 {
 382         int n_hdmi_entries;
 383         int hdmi_level;
 384         int hdmi_default_entry;
 385
 386         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 387
 388         if (IS_BROXTON(dev_priv))
 389                 return hdmi_level;
 390
 391         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 392                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 393                 hdmi_default_entry = 8;
 394         } else if (IS_BROADWELL(dev_priv)) {
 395                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 396                 hdmi_default_entry = 7;
 397         } else if (IS_HASWELL(dev_priv)) {
 398                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 399                 hdmi_default_entry = 6;
 400         } else {
 401                 WARN(1, "ddi translation table missing\n");
 402                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 403                 hdmi_default_entry = 7;
 404         }
 405
 406         /* Choose a good default if VBT is badly populated */
 407         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 408             hdmi_level >= n_hdmi_entries)
 409                 hdmi_level = hdmi_default_entry;
 410
 411         return hdmi_level;
 412 }
 413
 414 /*
 415  * Starting with Haswell, DDI port buffers must be programmed with correct
 416  * values in advance. This function programs the correct values for
 417  * DP/eDP/FDI use cases.
 418  */
 419 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 420 {
 421         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 422         u32 iboost_bit = 0;
 423         int i, n_dp_entries, n_edp_entries, size;
 424         enum port port = intel_ddi_get_encoder_port(encoder);
 425         const struct ddi_buf_trans *ddi_translations_fdi;
 426         const struct ddi_buf_trans *ddi_translations_dp;
 427         const struct ddi_buf_trans *ddi_translations_edp;
 428         const struct ddi_buf_trans *ddi_translations;
 429
 430         if (IS_BROXTON(dev_priv))
 431                 return;
 432
 433         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 434                 ddi_translations_fdi = NULL;
 435                 ddi_translations_dp =
 436                                 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
 437                 ddi_translations_edp =
 438                                 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
 439
 440                 /* If we're boosting the current, set bit 31 of trans1 */
 441                 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 442                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 443
 444                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 445                             port != PORT_A && port != PORT_E &&
 446                             n_edp_entries > 9))
 447                         n_edp_entries = 9;
 448         } else if (IS_BROADWELL(dev_priv)) {
 449                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 450                 ddi_translations_dp = bdw_ddi_translations_dp;
 451                 ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
 452                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 453         } else if (IS_HASWELL(dev_priv)) {
 454                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 455                 ddi_translations_dp = hsw_ddi_translations_dp;
 456                 ddi_translations_edp = hsw_ddi_translations_dp;
 457                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 458         } else {
 459                 WARN(1, "ddi translation table missing\n");
 460                 ddi_translations_edp = bdw_ddi_translations_dp;
 461                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 462                 ddi_translations_dp = bdw_ddi_translations_dp;
 463                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 464                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 465         }
 466
 467         switch (encoder->type) {
 468         case INTEL_OUTPUT_EDP:
 469                 ddi_translations = ddi_translations_edp;
 470                 size = n_edp_entries;
 471                 break;
 472         case INTEL_OUTPUT_DP:
 473                 ddi_translations = ddi_translations_dp;
 474                 size = n_dp_entries;
 475                 break;
 476         case INTEL_OUTPUT_ANALOG:
 477                 ddi_translations = ddi_translations_fdi;
 478                 size = n_dp_entries;
 479                 break;
 480         default:
 481                 BUG();
 482         }
 483
 484         for (i = 0; i < size; i++) {
 485                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 486                            ddi_translations[i].trans1 | iboost_bit);
 487                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 488                            ddi_translations[i].trans2);
 489         }
 490 }
 491
 492 /*
 493  * Starting with Haswell, DDI port buffers must be programmed with correct
 494  * values in advance. This function programs the correct values for
 495  * HDMI/DVI use cases.
 496  */
 497 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 498 {
 499         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 500         u32 iboost_bit = 0;
 501         int n_hdmi_entries, hdmi_level;
 502         enum port port = intel_ddi_get_encoder_port(encoder);
 503         const struct ddi_buf_trans *ddi_translations_hdmi;
 504
 505         if (IS_BROXTON(dev_priv))
 506                 return;
 507
 508         hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 509
 510         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 511                 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 512
 513                 /* If we're boosting the current, set bit 31 of trans1 */
 514                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 515                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 516         } else if (IS_BROADWELL(dev_priv)) {
 517                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 518                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 519         } else if (IS_HASWELL(dev_priv)) {
 520                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 521                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 522         } else {
 523                 WARN(1, "ddi translation table missing\n");
 524                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 525                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 526         }
 527
 528         /* Entry 9 is for HDMI: */
 529         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 530                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 531         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 532                    ddi_translations_hdmi[hdmi_level].trans2);
 533 }
 534
 535 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 536                                     enum port port)
 537 {
 538         i915_reg_t reg = DDI_BUF_CTL(port);
 539         int i;
 540
 541         for (i = 0; i < 16; i++) {
 542                 udelay(1);
 543                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 544                         return;
 545         }
 546         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 547 }
 548
 549 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
 550 {
 551         switch (pll->id) {
 552         case DPLL_ID_WRPLL1:
 553                 return PORT_CLK_SEL_WRPLL1;
 554         case DPLL_ID_WRPLL2:
 555                 return PORT_CLK_SEL_WRPLL2;
 556         case DPLL_ID_SPLL:
 557                 return PORT_CLK_SEL_SPLL;
 558         case DPLL_ID_LCPLL_810:
 559                 return PORT_CLK_SEL_LCPLL_810;
 560         case DPLL_ID_LCPLL_1350:
 561                 return PORT_CLK_SEL_LCPLL_1350;
 562         case DPLL_ID_LCPLL_2700:
 563                 return PORT_CLK_SEL_LCPLL_2700;
 564         default:
 565                 MISSING_CASE(pll->id);
 566                 return PORT_CLK_SEL_NONE;
 567         }
 568 }
 569
 570 /* Starting with Haswell, different DDI ports can work in FDI mode for
 571  * connection to the PCH-located connectors. For this, it is necessary to train
 572  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 573  *
 574  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 575  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 576  * DDI A (which is used for eDP)
 577  */
 578
 579 void hsw_fdi_link_train(struct drm_crtc *crtc)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct drm_i915_private *dev_priv = to_i915(dev);
 583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 584         struct intel_encoder *encoder;
 585         u32 temp, i, rx_ctl_val, ddi_pll_sel;
 586
 587         for_each_encoder_on_crtc(dev, crtc, encoder) {
 588                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 589                 intel_prepare_dp_ddi_buffers(encoder);
 590         }
 591
 592         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 593          * mode set "sequence for CRT port" document:
 594          * - TP1 to TP2 time with the default value
 595          * - FDI delay to 90h
 596          *
 597          * WaFDIAutoLinkSetTimingOverrride:hsw
 598          */
 599         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 600                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 601                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 602
 603         /* Enable the PCH Receiver FDI PLL */
 604         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 605                      FDI_RX_PLL_ENABLE |
 606                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 607         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 608         POSTING_READ(FDI_RX_CTL(PIPE_A));
 609         udelay(220);
 610
 611         /* Switch from Rawclk to PCDclk */
 612         rx_ctl_val |= FDI_PCDCLK;
 613         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 614
 615         /* Configure Port Clock Select */
 616         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
 617         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
 618         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 619
 620         /* Start the training iterating through available voltages and emphasis,
 621          * testing each value twice. */
 622         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 623                 /* Configure DP_TP_CTL with auto-training */
 624                 I915_WRITE(DP_TP_CTL(PORT_E),
 625                                         DP_TP_CTL_FDI_AUTOTRAIN |
 626                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 627                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 628                                         DP_TP_CTL_ENABLE);
 629
 630                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 631                  * DDI E does not support port reversal, the functionality is
 632                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 633                  * port reversal bit */
 634                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 635                            DDI_BUF_CTL_ENABLE |
 636                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 637                            DDI_BUF_TRANS_SELECT(i / 2));
 638                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 639
 640                 udelay(600);
 641
 642                 /* Program PCH FDI Receiver TU */
 643                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 644
 645                 /* Enable PCH FDI Receiver with auto-training */
 646                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 647                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 648                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 649
 650                 /* Wait for FDI receiver lane calibration */
 651                 udelay(30);
 652
 653                 /* Unset FDI_RX_MISC pwrdn lanes */
 654                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 655                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 656                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 657                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 658
 659                 /* Wait for FDI auto training time */
 660                 udelay(5);
 661
 662                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 663                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 664                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 665                         break;
 666                 }
 667
 668                 /*
 669                  * Leave things enabled even if we failed to train FDI.
 670                  * Results in less fireworks from the state checker.
 671                  */
 672                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 673                         DRM_ERROR("FDI link training failed!\n");
 674                         break;
 675                 }
 676
 677                 rx_ctl_val &= ~FDI_RX_ENABLE;
 678                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 679                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 680
 681                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 682                 temp &= ~DDI_BUF_CTL_ENABLE;
 683                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 684                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 685
 686                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 687                 temp = I915_READ(DP_TP_CTL(PORT_E));
 688                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 689                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 690                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 691                 POSTING_READ(DP_TP_CTL(PORT_E));
 692
 693                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 694
 695                 /* Reset FDI_RX_MISC pwrdn lanes */
 696                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 697                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 698                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 699                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 700                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 701         }
 702
 703         /* Enable normal pixel sending for FDI */
 704         I915_WRITE(DP_TP_CTL(PORT_E),
 705                    DP_TP_CTL_FDI_AUTOTRAIN |
 706                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 707                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 708                    DP_TP_CTL_ENABLE);
 709 }
 710
 711 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 712 {
 713         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 714         struct intel_digital_port *intel_dig_port =
 715                 enc_to_dig_port(&encoder->base);
 716
 717         intel_dp->DP = intel_dig_port->saved_port_bits |
 718                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 719         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 720 }
 721
 722 static struct intel_encoder *
 723 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 724 {
 725         struct drm_device *dev = crtc->dev;
 726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 727         struct intel_encoder *intel_encoder, *ret = NULL;
 728         int num_encoders = 0;
 729
 730         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 731                 ret = intel_encoder;
 732                 num_encoders++;
 733         }
 734
 735         if (num_encoders != 1)
 736                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 737                      pipe_name(intel_crtc->pipe));
 738
 739         BUG_ON(ret == NULL);
 740         return ret;
 741 }
 742
 743 struct intel_encoder *
 744 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 745 {
 746         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 747         struct intel_encoder *ret = NULL;
 748         struct drm_atomic_state *state;
 749         struct drm_connector *connector;
 750         struct drm_connector_state *connector_state;
 751         int num_encoders = 0;
 752         int i;
 753
 754         state = crtc_state->base.state;
 755
 756         for_each_connector_in_state(state, connector, connector_state, i) {
 757                 if (connector_state->crtc != crtc_state->base.crtc)
 758                         continue;
 759
 760                 ret = to_intel_encoder(connector_state->best_encoder);
 761                 num_encoders++;
 762         }
 763
 764         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 765              pipe_name(crtc->pipe));
 766
 767         BUG_ON(ret == NULL);
 768         return ret;
 769 }
 770
 771 #define LC_FREQ 2700
 772
 773 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 774                                    i915_reg_t reg)
 775 {
 776         int refclk = LC_FREQ;
 777         int n, p, r;
 778         u32 wrpll;
 779
 780         wrpll = I915_READ(reg);
 781         switch (wrpll & WRPLL_PLL_REF_MASK) {
 782         case WRPLL_PLL_SSC:
 783         case WRPLL_PLL_NON_SSC:
 784                 /*
 785                  * We could calculate spread here, but our checking
 786                  * code only cares about 5% accuracy, and spread is a max of
 787                  * 0.5% downspread.
 788                  */
 789                 refclk = 135;
 790                 break;
 791         case WRPLL_PLL_LCPLL:
 792                 refclk = LC_FREQ;
 793                 break;
 794         default:
 795                 WARN(1, "bad wrpll refclk\n");
 796                 return 0;
 797         }
 798
 799         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 800         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 801         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 802
 803         /* Convert to KHz, p & r have a fixed point portion */
 804         return (refclk * n * 100) / (p * r);
 805 }
 806
 807 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 808                                uint32_t dpll)
 809 {
 810         i915_reg_t cfgcr1_reg, cfgcr2_reg;
 811         uint32_t cfgcr1_val, cfgcr2_val;
 812         uint32_t p0, p1, p2, dco_freq;
 813
 814         cfgcr1_reg = DPLL_CFGCR1(dpll);
 815         cfgcr2_reg = DPLL_CFGCR2(dpll);
 816
 817         cfgcr1_val = I915_READ(cfgcr1_reg);
 818         cfgcr2_val = I915_READ(cfgcr2_reg);
 819
 820         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 821         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 822
 823         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 824                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 825         else
 826                 p1 = 1;
 827
 828
 829         switch (p0) {
 830         case DPLL_CFGCR2_PDIV_1:
 831                 p0 = 1;
 832                 break;
 833         case DPLL_CFGCR2_PDIV_2:
 834                 p0 = 2;
 835                 break;
 836         case DPLL_CFGCR2_PDIV_3:
 837                 p0 = 3;
 838                 break;
 839         case DPLL_CFGCR2_PDIV_7:
 840                 p0 = 7;
 841                 break;
 842         }
 843
 844         switch (p2) {
 845         case DPLL_CFGCR2_KDIV_5:
 846                 p2 = 5;
 847                 break;
 848         case DPLL_CFGCR2_KDIV_2:
 849                 p2 = 2;
 850                 break;
 851         case DPLL_CFGCR2_KDIV_3:
 852                 p2 = 3;
 853                 break;
 854         case DPLL_CFGCR2_KDIV_1:
 855                 p2 = 1;
 856                 break;
 857         }
 858
 859         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 860
 861         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 862                 1000) / 0x8000;
 863
 864         return dco_freq / (p0 * p1 * p2 * 5);
 865 }
 866
 867 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 868 {
 869         int dotclock;
 870
 871         if (pipe_config->has_pch_encoder)
 872                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 873                                                     &pipe_config->fdi_m_n);
 874         else if (intel_crtc_has_dp_encoder(pipe_config))
 875                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 876                                                     &pipe_config->dp_m_n);
 877         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
 878                 dotclock = pipe_config->port_clock * 2 / 3;
 879         else
 880                 dotclock = pipe_config->port_clock;
 881
 882         if (pipe_config->pixel_multiplier)
 883                 dotclock /= pipe_config->pixel_multiplier;
 884
 885         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 886 }
 887
 888 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 889                                 struct intel_crtc_state *pipe_config)
 890 {
 891         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 892         int link_clock = 0;
 893         uint32_t dpll_ctl1, dpll;
 894
 895         dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
 896
 897         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 898
 899         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 900                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 901         } else {
 902                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
 903                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
 904
 905                 switch (link_clock) {
 906                 case DPLL_CTRL1_LINK_RATE_810:
 907                         link_clock = 81000;
 908                         break;
 909                 case DPLL_CTRL1_LINK_RATE_1080:
 910                         link_clock = 108000;
 911                         break;
 912                 case DPLL_CTRL1_LINK_RATE_1350:
 913                         link_clock = 135000;
 914                         break;
 915                 case DPLL_CTRL1_LINK_RATE_1620:
 916                         link_clock = 162000;
 917                         break;
 918                 case DPLL_CTRL1_LINK_RATE_2160:
 919                         link_clock = 216000;
 920                         break;
 921                 case DPLL_CTRL1_LINK_RATE_2700:
 922                         link_clock = 270000;
 923                         break;
 924                 default:
 925                         WARN(1, "Unsupported link rate\n");
 926                         break;
 927                 }
 928                 link_clock *= 2;
 929         }
 930
 931         pipe_config->port_clock = link_clock;
 932
 933         ddi_dotclock_get(pipe_config);
 934 }
 935
 936 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 937                               struct intel_crtc_state *pipe_config)
 938 {
 939         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 940         int link_clock = 0;
 941         u32 val, pll;
 942
 943         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
 944         switch (val & PORT_CLK_SEL_MASK) {
 945         case PORT_CLK_SEL_LCPLL_810:
 946                 link_clock = 81000;
 947                 break;
 948         case PORT_CLK_SEL_LCPLL_1350:
 949                 link_clock = 135000;
 950                 break;
 951         case PORT_CLK_SEL_LCPLL_2700:
 952                 link_clock = 270000;
 953                 break;
 954         case PORT_CLK_SEL_WRPLL1:
 955                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
 956                 break;
 957         case PORT_CLK_SEL_WRPLL2:
 958                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
 959                 break;
 960         case PORT_CLK_SEL_SPLL:
 961                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 962                 if (pll == SPLL_PLL_FREQ_810MHz)
 963                         link_clock = 81000;
 964                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 965                         link_clock = 135000;
 966                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 967                         link_clock = 270000;
 968                 else {
 969                         WARN(1, "bad spll freq\n");
 970                         return;
 971                 }
 972                 break;
 973         default:
 974                 WARN(1, "bad port clock sel\n");
 975                 return;
 976         }
 977
 978         pipe_config->port_clock = link_clock * 2;
 979
 980         ddi_dotclock_get(pipe_config);
 981 }
 982
 983 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
 984                                 enum intel_dpll_id dpll)
 985 {
 986         struct intel_shared_dpll *pll;
 987         struct intel_dpll_hw_state *state;
 988         struct dpll clock;
 989
 990         /* For DDI ports we always use a shared PLL. */
 991         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
 992                 return 0;
 993
 994         pll = &dev_priv->shared_dplls[dpll];
 995         state = &pll->config.hw_state;
 996
 997         clock.m1 = 2;
 998         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
 999         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1000                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1001         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1002         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1003         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1004
1005         return chv_calc_dpll_params(100000, &clock);
1006 }
1007
1008 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1009                                 struct intel_crtc_state *pipe_config)
1010 {
1011         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1012         enum port port = intel_ddi_get_encoder_port(encoder);
1013         uint32_t dpll = port;
1014
1015         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1016
1017         ddi_dotclock_get(pipe_config);
1018 }
1019
1020 void intel_ddi_clock_get(struct intel_encoder *encoder,
1021                          struct intel_crtc_state *pipe_config)
1022 {
1023         struct drm_device *dev = encoder->base.dev;
1024
1025         if (INTEL_INFO(dev)->gen <= 8)
1026                 hsw_ddi_clock_get(encoder, pipe_config);
1027         else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1028                 skl_ddi_clock_get(encoder, pipe_config);
1029         else if (IS_BROXTON(dev))
1030                 bxt_ddi_clock_get(encoder, pipe_config);
1031 }
1032
1033 static bool
1034 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1035                    struct intel_crtc_state *crtc_state,
1036                    struct intel_encoder *intel_encoder)
1037 {
1038         struct intel_shared_dpll *pll;
1039
1040         pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1041                                     intel_encoder);
1042         if (!pll)
1043                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1044                                  pipe_name(intel_crtc->pipe));
1045
1046         return pll;
1047 }
1048
1049 static bool
1050 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1051                    struct intel_crtc_state *crtc_state,
1052                    struct intel_encoder *intel_encoder)
1053 {
1054         struct intel_shared_dpll *pll;
1055
1056         pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1057         if (pll == NULL) {
1058                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1059                                  pipe_name(intel_crtc->pipe));
1060                 return false;
1061         }
1062
1063         return true;
1064 }
1065
1066 static bool
1067 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1068                    struct intel_crtc_state *crtc_state,
1069                    struct intel_encoder *intel_encoder)
1070 {
1071         return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1072 }
1073
1074 /*
1075  * Tries to find a *shared* PLL for the CRTC and store it in
1076  * intel_crtc->ddi_pll_sel.
1077  *
1078  * For private DPLLs, compute_config() should do the selection for us. This
1079  * function should be folded into compute_config() eventually.
1080  */
1081 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1082                           struct intel_crtc_state *crtc_state)
1083 {
1084         struct drm_device *dev = intel_crtc->base.dev;
1085         struct intel_encoder *intel_encoder =
1086                 intel_ddi_get_crtc_new_encoder(crtc_state);
1087
1088         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1089                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1090                                           intel_encoder);
1091         else if (IS_BROXTON(dev))
1092                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1093                                           intel_encoder);
1094         else
1095                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1096                                           intel_encoder);
1097 }
1098
1099 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1100 {
1101         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1103         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1104         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1105         int type = intel_encoder->type;
1106         uint32_t temp;
1107
1108         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1109                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1110
1111                 temp = TRANS_MSA_SYNC_CLK;
1112                 switch (intel_crtc->config->pipe_bpp) {
1113                 case 18:
1114                         temp |= TRANS_MSA_6_BPC;
1115                         break;
1116                 case 24:
1117                         temp |= TRANS_MSA_8_BPC;
1118                         break;
1119                 case 30:
1120                         temp |= TRANS_MSA_10_BPC;
1121                         break;
1122                 case 36:
1123                         temp |= TRANS_MSA_12_BPC;
1124                         break;
1125                 default:
1126                         BUG();
1127                 }
1128                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1129         }
1130 }
1131
1132 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1133 {
1134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1135         struct drm_device *dev = crtc->dev;
1136         struct drm_i915_private *dev_priv = to_i915(dev);
1137         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1138         uint32_t temp;
1139         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1140         if (state == true)
1141                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1142         else
1143                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1144         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1145 }
1146
1147 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1148 {
1149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1150         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1151         struct drm_device *dev = crtc->dev;
1152         struct drm_i915_private *dev_priv = to_i915(dev);
1153         enum pipe pipe = intel_crtc->pipe;
1154         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1155         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1156         int type = intel_encoder->type;
1157         uint32_t temp;
1158
1159         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1160         temp = TRANS_DDI_FUNC_ENABLE;
1161         temp |= TRANS_DDI_SELECT_PORT(port);
1162
1163         switch (intel_crtc->config->pipe_bpp) {
1164         case 18:
1165                 temp |= TRANS_DDI_BPC_6;
1166                 break;
1167         case 24:
1168                 temp |= TRANS_DDI_BPC_8;
1169                 break;
1170         case 30:
1171                 temp |= TRANS_DDI_BPC_10;
1172                 break;
1173         case 36:
1174                 temp |= TRANS_DDI_BPC_12;
1175                 break;
1176         default:
1177                 BUG();
1178         }
1179
1180         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1181                 temp |= TRANS_DDI_PVSYNC;
1182         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1183                 temp |= TRANS_DDI_PHSYNC;
1184
1185         if (cpu_transcoder == TRANSCODER_EDP) {
1186                 switch (pipe) {
1187                 case PIPE_A:
1188                         /* On Haswell, can only use the always-on power well for
1189                          * eDP when not using the panel fitter, and when not
1190                          * using motion blur mitigation (which we don't
1191                          * support). */
1192                         if (IS_HASWELL(dev) &&
1193                             (intel_crtc->config->pch_pfit.enabled ||
1194                              intel_crtc->config->pch_pfit.force_thru))
1195                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1196                         else
1197                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1198                         break;
1199                 case PIPE_B:
1200                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1201                         break;
1202                 case PIPE_C:
1203                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1204                         break;
1205                 default:
1206                         BUG();
1207                         break;
1208                 }
1209         }
1210
1211         if (type == INTEL_OUTPUT_HDMI) {
1212                 if (intel_crtc->config->has_hdmi_sink)
1213                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1214                 else
1215                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1216         } else if (type == INTEL_OUTPUT_ANALOG) {
1217                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1218                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1219         } else if (type == INTEL_OUTPUT_DP ||
1220                    type == INTEL_OUTPUT_EDP) {
1221                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1222                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1223         } else if (type == INTEL_OUTPUT_DP_MST) {
1224                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1225                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1226         } else {
1227                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1228                      intel_encoder->type, pipe_name(pipe));
1229         }
1230
1231         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1232 }
1233
1234 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1235                                        enum transcoder cpu_transcoder)
1236 {
1237         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1238         uint32_t val = I915_READ(reg);
1239
1240         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1241         val |= TRANS_DDI_PORT_NONE;
1242         I915_WRITE(reg, val);
1243 }
1244
1245 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1246 {
1247         struct drm_device *dev = intel_connector->base.dev;
1248         struct drm_i915_private *dev_priv = to_i915(dev);
1249         struct intel_encoder *intel_encoder = intel_connector->encoder;
1250         int type = intel_connector->base.connector_type;
1251         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1252         enum pipe pipe = 0;
1253         enum transcoder cpu_transcoder;
1254         enum intel_display_power_domain power_domain;
1255         uint32_t tmp;
1256         bool ret;
1257
1258         power_domain = intel_display_port_power_domain(intel_encoder);
1259         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1260                 return false;
1261
1262         if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1263                 ret = false;
1264                 goto out;
1265         }
1266
1267         if (port == PORT_A)
1268                 cpu_transcoder = TRANSCODER_EDP;
1269         else
1270                 cpu_transcoder = (enum transcoder) pipe;
1271
1272         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1273
1274         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1275         case TRANS_DDI_MODE_SELECT_HDMI:
1276         case TRANS_DDI_MODE_SELECT_DVI:
1277                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1278                 break;
1279
1280         case TRANS_DDI_MODE_SELECT_DP_SST:
1281                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1282                       type == DRM_MODE_CONNECTOR_DisplayPort;
1283                 break;
1284
1285         case TRANS_DDI_MODE_SELECT_DP_MST:
1286                 /* if the transcoder is in MST state then
1287                  * connector isn't connected */
1288                 ret = false;
1289                 break;
1290
1291         case TRANS_DDI_MODE_SELECT_FDI:
1292                 ret = type == DRM_MODE_CONNECTOR_VGA;
1293                 break;
1294
1295         default:
1296                 ret = false;
1297                 break;
1298         }
1299
1300 out:
1301         intel_display_power_put(dev_priv, power_domain);
1302
1303         return ret;
1304 }
1305
1306 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1307                             enum pipe *pipe)
1308 {
1309         struct drm_device *dev = encoder->base.dev;
1310         struct drm_i915_private *dev_priv = to_i915(dev);
1311         enum port port = intel_ddi_get_encoder_port(encoder);
1312         enum intel_display_power_domain power_domain;
1313         u32 tmp;
1314         int i;
1315         bool ret;
1316
1317         power_domain = intel_display_port_power_domain(encoder);
1318         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1319                 return false;
1320
1321         ret = false;
1322
1323         tmp = I915_READ(DDI_BUF_CTL(port));
1324
1325         if (!(tmp & DDI_BUF_CTL_ENABLE))
1326                 goto out;
1327
1328         if (port == PORT_A) {
1329                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1330
1331                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1332                 case TRANS_DDI_EDP_INPUT_A_ON:
1333                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1334                         *pipe = PIPE_A;
1335                         break;
1336                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1337                         *pipe = PIPE_B;
1338                         break;
1339                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1340                         *pipe = PIPE_C;
1341                         break;
1342                 }
1343
1344                 ret = true;
1345
1346                 goto out;
1347         }
1348
1349         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1350                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1351
1352                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1353                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1354                             TRANS_DDI_MODE_SELECT_DP_MST)
1355                                 goto out;
1356
1357                         *pipe = i;
1358                         ret = true;
1359
1360                         goto out;
1361                 }
1362         }
1363
1364         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1365
1366 out:
1367         if (ret && IS_BROXTON(dev_priv)) {
1368                 tmp = I915_READ(BXT_PHY_CTL(port));
1369                 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1370                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1371                         DRM_ERROR("Port %c enabled but PHY powered down? "
1372                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1373         }
1374
1375         intel_display_power_put(dev_priv, power_domain);
1376
1377         return ret;
1378 }
1379
1380 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1381 {
1382         struct drm_crtc *crtc = &intel_crtc->base;
1383         struct drm_device *dev = crtc->dev;
1384         struct drm_i915_private *dev_priv = to_i915(dev);
1385         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1386         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1387         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1388
1389         if (cpu_transcoder != TRANSCODER_EDP)
1390                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1391                            TRANS_CLK_SEL_PORT(port));
1392 }
1393
1394 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1395 {
1396         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1397         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1398
1399         if (cpu_transcoder != TRANSCODER_EDP)
1400                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1401                            TRANS_CLK_SEL_DISABLED);
1402 }
1403
1404 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1405                                 enum port port, uint8_t iboost)
1406 {
1407         u32 tmp;
1408
1409         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1410         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1411         if (iboost)
1412                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1413         else
1414                 tmp |= BALANCE_LEG_DISABLE(port);
1415         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1416 }
1417
1418 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1419 {
1420         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1421         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1422         enum port port = intel_dig_port->port;
1423         int type = encoder->type;
1424         const struct ddi_buf_trans *ddi_translations;
1425         uint8_t iboost;
1426         uint8_t dp_iboost, hdmi_iboost;
1427         int n_entries;
1428
1429         /* VBT may override standard boost values */
1430         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1431         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1432
1433         if (type == INTEL_OUTPUT_DP) {
1434                 if (dp_iboost) {
1435                         iboost = dp_iboost;
1436                 } else {
1437                         ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
1438                         iboost = ddi_translations[level].i_boost;
1439                 }
1440         } else if (type == INTEL_OUTPUT_EDP) {
1441                 if (dp_iboost) {
1442                         iboost = dp_iboost;
1443                 } else {
1444                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1445
1446                         if (WARN_ON(port != PORT_A &&
1447                                     port != PORT_E && n_entries > 9))
1448                                 n_entries = 9;
1449
1450                         iboost = ddi_translations[level].i_boost;
1451                 }
1452         } else if (type == INTEL_OUTPUT_HDMI) {
1453                 if (hdmi_iboost) {
1454                         iboost = hdmi_iboost;
1455                 } else {
1456                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1457                         iboost = ddi_translations[level].i_boost;
1458                 }
1459         } else {
1460                 return;
1461         }
1462
1463         /* Make sure that the requested I_boost is valid */
1464         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1465                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1466                 return;
1467         }
1468
1469         _skl_ddi_set_iboost(dev_priv, port, iboost);
1470
1471         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1472                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1473 }
1474
1475 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1476                                     u32 level, enum port port, int type)
1477 {
1478         const struct bxt_ddi_buf_trans *ddi_translations;
1479         u32 n_entries, i;
1480         uint32_t val;
1481
1482         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1483                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1484                 ddi_translations = bxt_ddi_translations_edp;
1485         } else if (type == INTEL_OUTPUT_DP
1486                         || type == INTEL_OUTPUT_EDP) {
1487                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1488                 ddi_translations = bxt_ddi_translations_dp;
1489         } else if (type == INTEL_OUTPUT_HDMI) {
1490                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1491                 ddi_translations = bxt_ddi_translations_hdmi;
1492         } else {
1493                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1494                                 type);
1495                 return;
1496         }
1497
1498         /* Check if default value has to be used */
1499         if (level >= n_entries ||
1500             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1501                 for (i = 0; i < n_entries; i++) {
1502                         if (ddi_translations[i].default_index) {
1503                                 level = i;
1504                                 break;
1505                         }
1506                 }
1507         }
1508
1509         /*
1510          * While we write to the group register to program all lanes at once we
1511          * can read only lane registers and we pick lanes 0/1 for that.
1512          */
1513         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1514         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1515         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1516
1517         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1518         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1519         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1520                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1521         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1522
1523         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1524         val &= ~SCALE_DCOMP_METHOD;
1525         if (ddi_translations[level].enable)
1526                 val |= SCALE_DCOMP_METHOD;
1527
1528         if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1529                 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1530
1531         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1532
1533         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1534         val &= ~DE_EMPHASIS;
1535         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1536         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1537
1538         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1539         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1540         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1541 }
1542
1543 static uint32_t translate_signal_level(int signal_levels)
1544 {
1545         uint32_t level;
1546
1547         switch (signal_levels) {
1548         default:
1549                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1550                               signal_levels);
1551         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1552                 level = 0;
1553                 break;
1554         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1555                 level = 1;
1556                 break;
1557         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1558                 level = 2;
1559                 break;
1560         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1561                 level = 3;
1562                 break;
1563
1564         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1565                 level = 4;
1566                 break;
1567         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1568                 level = 5;
1569                 break;
1570         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1571                 level = 6;
1572                 break;
1573
1574         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1575                 level = 7;
1576                 break;
1577         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1578                 level = 8;
1579                 break;
1580
1581         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1582                 level = 9;
1583                 break;
1584         }
1585
1586         return level;
1587 }
1588
1589 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1590 {
1591         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1592         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1593         struct intel_encoder *encoder = &dport->base;
1594         uint8_t train_set = intel_dp->train_set[0];
1595         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1596                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1597         enum port port = dport->port;
1598         uint32_t level;
1599
1600         level = translate_signal_level(signal_levels);
1601
1602         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1603                 skl_ddi_set_iboost(encoder, level);
1604         else if (IS_BROXTON(dev_priv))
1605                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1606
1607         return DDI_BUF_TRANS_SELECT(level);
1608 }
1609
1610 void intel_ddi_clk_select(struct intel_encoder *encoder,
1611                           struct intel_shared_dpll *pll)
1612 {
1613         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1614         enum port port = intel_ddi_get_encoder_port(encoder);
1615
1616         if (WARN_ON(!pll))
1617                 return;
1618
1619         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1620                 uint32_t val;
1621
1622                 /* DDI -> PLL mapping  */
1623                 val = I915_READ(DPLL_CTRL2);
1624
1625                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1626                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1627                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
1628                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1629
1630                 I915_WRITE(DPLL_CTRL2, val);
1631
1632         } else if (INTEL_INFO(dev_priv)->gen < 9) {
1633                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1634         }
1635 }
1636
1637 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
1638                                     int link_rate, uint32_t lane_count,
1639                                     struct intel_shared_dpll *pll,
1640                                     bool link_mst)
1641 {
1642         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1643         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1644         enum port port = intel_ddi_get_encoder_port(encoder);
1645
1646         intel_dp_set_link_params(intel_dp, link_rate, lane_count,
1647                                  link_mst);
1648         if (encoder->type == INTEL_OUTPUT_EDP)
1649                 intel_edp_panel_on(intel_dp);
1650
1651         intel_ddi_clk_select(encoder, pll);
1652         intel_prepare_dp_ddi_buffers(encoder);
1653         intel_ddi_init_dp_buf_reg(encoder);
1654         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1655         intel_dp_start_link_train(intel_dp);
1656         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
1657                 intel_dp_stop_link_train(intel_dp);
1658 }
1659
1660 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
1661                                       bool has_hdmi_sink,
1662                                       struct drm_display_mode *adjusted_mode,
1663                                       struct intel_shared_dpll *pll)
1664 {
1665         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1666         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1667         struct drm_encoder *drm_encoder = &encoder->base;
1668         enum port port = intel_ddi_get_encoder_port(encoder);
1669         int level = intel_ddi_hdmi_level(dev_priv, port);
1670
1671         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1672         intel_ddi_clk_select(encoder, pll);
1673         intel_prepare_hdmi_ddi_buffers(encoder);
1674         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1675                 skl_ddi_set_iboost(encoder, level);
1676         else if (IS_BROXTON(dev_priv))
1677                 bxt_ddi_vswing_sequence(dev_priv, level, port,
1678                                         INTEL_OUTPUT_HDMI);
1679
1680         intel_hdmi->set_infoframes(drm_encoder,
1681                                    has_hdmi_sink,
1682                                    adjusted_mode);
1683 }
1684
1685 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
1686                                  struct intel_crtc_state *pipe_config,
1687                                  struct drm_connector_state *conn_state)
1688 {
1689         struct drm_encoder *encoder = &intel_encoder->base;
1690         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1691         int type = intel_encoder->type;
1692
1693         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1694                 intel_ddi_pre_enable_dp(intel_encoder,
1695                                         crtc->config->port_clock,
1696                                         crtc->config->lane_count,
1697                                         crtc->config->shared_dpll,
1698                                         intel_crtc_has_type(crtc->config,
1699                                                             INTEL_OUTPUT_DP_MST));
1700         }
1701         if (type == INTEL_OUTPUT_HDMI) {
1702                 intel_ddi_pre_enable_hdmi(intel_encoder,
1703                                           crtc->config->has_hdmi_sink,
1704                                           &crtc->config->base.adjusted_mode,
1705                                           crtc->config->shared_dpll);
1706         }
1707 }
1708
1709 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
1710                                    struct intel_crtc_state *old_crtc_state,
1711                                    struct drm_connector_state *old_conn_state)
1712 {
1713         struct drm_encoder *encoder = &intel_encoder->base;
1714         struct drm_device *dev = encoder->dev;
1715         struct drm_i915_private *dev_priv = to_i915(dev);
1716         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1717         int type = intel_encoder->type;
1718         uint32_t val;
1719         bool wait = false;
1720
1721         /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
1722
1723         val = I915_READ(DDI_BUF_CTL(port));
1724         if (val & DDI_BUF_CTL_ENABLE) {
1725                 val &= ~DDI_BUF_CTL_ENABLE;
1726                 I915_WRITE(DDI_BUF_CTL(port), val);
1727                 wait = true;
1728         }
1729
1730         val = I915_READ(DP_TP_CTL(port));
1731         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1732         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1733         I915_WRITE(DP_TP_CTL(port), val);
1734
1735         if (wait)
1736                 intel_wait_ddi_buf_idle(dev_priv, port);
1737
1738         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1739                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1740                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1741                 intel_edp_panel_vdd_on(intel_dp);
1742                 intel_edp_panel_off(intel_dp);
1743         }
1744
1745         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1746                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1747                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1748         else if (INTEL_INFO(dev)->gen < 9)
1749                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1750
1751         if (type == INTEL_OUTPUT_HDMI) {
1752                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1753
1754                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1755         }
1756 }
1757
1758 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1759                                 struct intel_crtc_state *old_crtc_state,
1760                                 struct drm_connector_state *old_conn_state)
1761 {
1762         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1763         uint32_t val;
1764
1765         /*
1766          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
1767          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
1768          * step 13 is the correct place for it. Step 18 is where it was
1769          * originally before the BUN.
1770          */
1771         val = I915_READ(FDI_RX_CTL(PIPE_A));
1772         val &= ~FDI_RX_ENABLE;
1773         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1774
1775         intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state);
1776
1777         val = I915_READ(FDI_RX_MISC(PIPE_A));
1778         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1779         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1780         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1781
1782         val = I915_READ(FDI_RX_CTL(PIPE_A));
1783         val &= ~FDI_PCDCLK;
1784         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1785
1786         val = I915_READ(FDI_RX_CTL(PIPE_A));
1787         val &= ~FDI_RX_PLL_ENABLE;
1788         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1789 }
1790
1791 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
1792                              struct intel_crtc_state *pipe_config,
1793                              struct drm_connector_state *conn_state)
1794 {
1795         struct drm_encoder *encoder = &intel_encoder->base;
1796         struct drm_crtc *crtc = encoder->crtc;
1797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1798         struct drm_device *dev = encoder->dev;
1799         struct drm_i915_private *dev_priv = to_i915(dev);
1800         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1801         int type = intel_encoder->type;
1802
1803         if (type == INTEL_OUTPUT_HDMI) {
1804                 struct intel_digital_port *intel_dig_port =
1805                         enc_to_dig_port(encoder);
1806
1807                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1808                  * are ignored so nothing special needs to be done besides
1809                  * enabling the port.
1810                  */
1811                 I915_WRITE(DDI_BUF_CTL(port),
1812                            intel_dig_port->saved_port_bits |
1813                            DDI_BUF_CTL_ENABLE);
1814         } else if (type == INTEL_OUTPUT_EDP) {
1815                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1816
1817                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1818                         intel_dp_stop_link_train(intel_dp);
1819
1820                 intel_edp_backlight_on(intel_dp);
1821                 intel_psr_enable(intel_dp);
1822                 intel_edp_drrs_enable(intel_dp, pipe_config);
1823         }
1824
1825         if (intel_crtc->config->has_audio) {
1826                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1827                 intel_audio_codec_enable(intel_encoder);
1828         }
1829 }
1830
1831 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
1832                               struct intel_crtc_state *old_crtc_state,
1833                               struct drm_connector_state *old_conn_state)
1834 {
1835         struct drm_encoder *encoder = &intel_encoder->base;
1836         struct drm_crtc *crtc = encoder->crtc;
1837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1838         int type = intel_encoder->type;
1839         struct drm_device *dev = encoder->dev;
1840         struct drm_i915_private *dev_priv = to_i915(dev);
1841
1842         if (intel_crtc->config->has_audio) {
1843                 intel_audio_codec_disable(intel_encoder);
1844                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1845         }
1846
1847         if (type == INTEL_OUTPUT_EDP) {
1848                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1849
1850                 intel_edp_drrs_disable(intel_dp, old_crtc_state);
1851                 intel_psr_disable(intel_dp);
1852                 intel_edp_backlight_off(intel_dp);
1853         }
1854 }
1855
1856 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1857                             enum dpio_phy phy)
1858 {
1859         enum port port;
1860
1861         if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1862                 return false;
1863
1864         if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1865              (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1866                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1867                                  phy);
1868
1869                 return false;
1870         }
1871
1872         if (phy == DPIO_PHY1 &&
1873             !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1874                 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1875
1876                 return false;
1877         }
1878
1879         if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1880                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1881                                  phy);
1882
1883                 return false;
1884         }
1885
1886         for_each_port_masked(port,
1887                              phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1888                                                 BIT(PORT_A)) {
1889                 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1890
1891                 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1892                         DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1893                                          "for port %c powered down "
1894                                          "(PHY_CTL %08x)\n",
1895                                          phy, port_name(port), tmp);
1896
1897                         return false;
1898                 }
1899         }
1900
1901         return true;
1902 }
1903
1904 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1905 {
1906         u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1907
1908         return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1909 }
1910
1911 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1912                                   enum dpio_phy phy)
1913 {
1914         if (intel_wait_for_register(dev_priv,
1915                                     BXT_PORT_REF_DW3(phy),
1916                                     GRC_DONE, GRC_DONE,
1917                                     10))
1918                 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1919 }
1920
1921 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1922 {
1923         u32 val;
1924
1925         if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
1926                 /* Still read out the GRC value for state verification */
1927                 if (phy == DPIO_PHY0)
1928                         dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
1929
1930                 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
1931                         DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1932                                          "won't reprogram it\n", phy);
1933
1934                         return;
1935                 }
1936
1937                 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1938                                  "force reprogramming it\n", phy);
1939         }
1940
1941         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1942         val |= GT_DISPLAY_POWER_ON(phy);
1943         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1944
1945         /*
1946          * The PHY registers start out inaccessible and respond to reads with
1947          * all 1s.  Eventually they become accessible as they power up, then
1948          * the reserved bit will give the default 0.  Poll on the reserved bit
1949          * becoming 0 to find when the PHY is accessible.
1950          * HW team confirmed that the time to reach phypowergood status is
1951          * anywhere between 50 us and 100us.
1952          */
1953         if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1954                 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
1955                 DRM_ERROR("timeout during PHY%d power on\n", phy);
1956         }
1957
1958         /* Program PLL Rcomp code offset */
1959         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1960         val &= ~IREF0RC_OFFSET_MASK;
1961         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1962         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1963
1964         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1965         val &= ~IREF1RC_OFFSET_MASK;
1966         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1967         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1968
1969         /* Program power gating */
1970         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1971         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1972                 SUS_CLK_CONFIG;
1973         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1974
1975         if (phy == DPIO_PHY0) {
1976                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1977                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1978                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1979         }
1980
1981         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1982         val &= ~OCL2_LDOFUSE_PWR_DIS;
1983         /*
1984          * On PHY1 disable power on the second channel, since no port is
1985          * connected there. On PHY0 both channels have a port, so leave it
1986          * enabled.
1987          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1988          * power down the second channel on PHY0 as well.
1989          *
1990          * FIXME: Clarify programming of the following, the register is
1991          * read-only with bit 6 fixed at 0 at least in stepping A.
1992          */
1993         if (phy == DPIO_PHY1)
1994                 val |= OCL2_LDOFUSE_PWR_DIS;
1995         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1996
1997         if (phy == DPIO_PHY0) {
1998                 uint32_t grc_code;
1999                 /*
2000                  * PHY0 isn't connected to an RCOMP resistor so copy over
2001                  * the corresponding calibrated value from PHY1, and disable
2002                  * the automatic calibration on PHY0.
2003                  */
2004                 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
2005                 grc_code = val << GRC_CODE_FAST_SHIFT |
2006                            val << GRC_CODE_SLOW_SHIFT |
2007                            val;
2008                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2009
2010                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2011                 val |= GRC_DIS | GRC_RDY_OVRD;
2012                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2013         }
2014
2015         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2016         val |= COMMON_RESET_DIS;
2017         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2018
2019         if (phy == DPIO_PHY1)
2020                 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
2021 }
2022
2023 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
2024 {
2025         uint32_t val;
2026
2027         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2028         val &= ~COMMON_RESET_DIS;
2029         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2030
2031         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2032         val &= ~GT_DISPLAY_POWER_ON(phy);
2033         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2034 }
2035
2036 static bool __printf(6, 7)
2037 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2038                        i915_reg_t reg, u32 mask, u32 expected,
2039                        const char *reg_fmt, ...)
2040 {
2041         struct va_format vaf;
2042         va_list args;
2043         u32 val;
2044
2045         val = I915_READ(reg);
2046         if ((val & mask) == expected)
2047                 return true;
2048
2049         va_start(args, reg_fmt);
2050         vaf.fmt = reg_fmt;
2051         vaf.va = &args;
2052
2053         DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
2054                          "current %08x, expected %08x (mask %08x)\n",
2055                          phy, &vaf, reg.reg, val, (val & ~mask) | expected,
2056                          mask);
2057
2058         va_end(args);
2059
2060         return false;
2061 }
2062
2063 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
2064                               enum dpio_phy phy)
2065 {
2066         uint32_t mask;
2067         bool ok;
2068
2069 #define _CHK(reg, mask, exp, fmt, ...)                                  \
2070         __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,      \
2071                                ## __VA_ARGS__)
2072
2073         if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
2074                 return false;
2075
2076         ok = true;
2077
2078         /* PLL Rcomp code offset */
2079         ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
2080                     IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
2081                     "BXT_PORT_CL1CM_DW9(%d)", phy);
2082         ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
2083                     IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2084                     "BXT_PORT_CL1CM_DW10(%d)", phy);
2085
2086         /* Power gating */
2087         mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2088         ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2089                     "BXT_PORT_CL1CM_DW28(%d)", phy);
2090
2091         if (phy == DPIO_PHY0)
2092                 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2093                            DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2094                            "BXT_PORT_CL2CM_DW6_BC");
2095
2096         /*
2097          * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2098          * at least on stepping A this bit is read-only and fixed at 0.
2099          */
2100
2101         if (phy == DPIO_PHY0) {
2102                 u32 grc_code = dev_priv->bxt_phy_grc;
2103
2104                 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2105                            grc_code << GRC_CODE_SLOW_SHIFT |
2106                            grc_code;
2107                 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2108                        GRC_CODE_NOM_MASK;
2109                 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2110                             "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2111
2112                 mask = GRC_DIS | GRC_RDY_OVRD;
2113                 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2114                             "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2115         }
2116
2117         return ok;
2118 #undef _CHK
2119 }
2120
2121 static uint8_t
2122 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2123                                      struct intel_crtc_state *pipe_config)
2124 {
2125         switch (pipe_config->lane_count) {
2126         case 1:
2127                 return 0;
2128         case 2:
2129                 return BIT(2) | BIT(0);
2130         case 4:
2131                 return BIT(3) | BIT(2) | BIT(0);
2132         default:
2133                 MISSING_CASE(pipe_config->lane_count);
2134
2135                 return 0;
2136         }
2137 }
2138
2139 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2140                                    struct intel_crtc_state *pipe_config,
2141                                    struct drm_connector_state *conn_state)
2142 {
2143         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2144         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2145         enum port port = dport->port;
2146         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2147         int lane;
2148
2149         for (lane = 0; lane < 4; lane++) {
2150                 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2151
2152                 /*
2153                  * Note that on CHV this flag is called UPAR, but has
2154                  * the same function.
2155                  */
2156                 val &= ~LATENCY_OPTIM;
2157                 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2158                         val |= LATENCY_OPTIM;
2159
2160                 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2161         }
2162 }
2163
2164 static uint8_t
2165 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2166 {
2167         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2168         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2169         enum port port = dport->port;
2170         int lane;
2171         uint8_t mask;
2172
2173         mask = 0;
2174         for (lane = 0; lane < 4; lane++) {
2175                 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2176
2177                 if (val & LATENCY_OPTIM)
2178                         mask |= BIT(lane);
2179         }
2180
2181         return mask;
2182 }
2183
2184 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2185 {
2186         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2187         struct drm_i915_private *dev_priv =
2188                 to_i915(intel_dig_port->base.base.dev);
2189         enum port port = intel_dig_port->port;
2190         uint32_t val;
2191         bool wait = false;
2192
2193         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2194                 val = I915_READ(DDI_BUF_CTL(port));
2195                 if (val & DDI_BUF_CTL_ENABLE) {
2196                         val &= ~DDI_BUF_CTL_ENABLE;
2197                         I915_WRITE(DDI_BUF_CTL(port), val);
2198                         wait = true;
2199                 }
2200
2201                 val = I915_READ(DP_TP_CTL(port));
2202                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2203                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2204                 I915_WRITE(DP_TP_CTL(port), val);
2205                 POSTING_READ(DP_TP_CTL(port));
2206
2207                 if (wait)
2208                         intel_wait_ddi_buf_idle(dev_priv, port);
2209         }
2210
2211         val = DP_TP_CTL_ENABLE |
2212               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2213         if (intel_dp->link_mst)
2214                 val |= DP_TP_CTL_MODE_MST;
2215         else {
2216                 val |= DP_TP_CTL_MODE_SST;
2217                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2218                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2219         }
2220         I915_WRITE(DP_TP_CTL(port), val);
2221         POSTING_READ(DP_TP_CTL(port));
2222
2223         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2224         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2225         POSTING_READ(DDI_BUF_CTL(port));
2226
2227         udelay(600);
2228 }
2229
2230 void intel_ddi_get_config(struct intel_encoder *encoder,
2231                           struct intel_crtc_state *pipe_config)
2232 {
2233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2234         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2235         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2236         struct intel_hdmi *intel_hdmi;
2237         u32 temp, flags = 0;
2238
2239         /* XXX: DSI transcoder paranoia */
2240         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2241                 return;
2242
2243         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2244         if (temp & TRANS_DDI_PHSYNC)
2245                 flags |= DRM_MODE_FLAG_PHSYNC;
2246         else
2247                 flags |= DRM_MODE_FLAG_NHSYNC;
2248         if (temp & TRANS_DDI_PVSYNC)
2249                 flags |= DRM_MODE_FLAG_PVSYNC;
2250         else
2251                 flags |= DRM_MODE_FLAG_NVSYNC;
2252
2253         pipe_config->base.adjusted_mode.flags |= flags;
2254
2255         switch (temp & TRANS_DDI_BPC_MASK) {
2256         case TRANS_DDI_BPC_6:
2257                 pipe_config->pipe_bpp = 18;
2258                 break;
2259         case TRANS_DDI_BPC_8:
2260                 pipe_config->pipe_bpp = 24;
2261                 break;
2262         case TRANS_DDI_BPC_10:
2263                 pipe_config->pipe_bpp = 30;
2264                 break;
2265         case TRANS_DDI_BPC_12:
2266                 pipe_config->pipe_bpp = 36;
2267                 break;
2268         default:
2269                 break;
2270         }
2271
2272         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2273         case TRANS_DDI_MODE_SELECT_HDMI:
2274                 pipe_config->has_hdmi_sink = true;
2275                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2276
2277                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2278                         pipe_config->has_infoframe = true;
2279                 /* fall through */
2280         case TRANS_DDI_MODE_SELECT_DVI:
2281                 pipe_config->lane_count = 4;
2282                 break;
2283         case TRANS_DDI_MODE_SELECT_FDI:
2284                 break;
2285         case TRANS_DDI_MODE_SELECT_DP_SST:
2286         case TRANS_DDI_MODE_SELECT_DP_MST:
2287                 pipe_config->lane_count =
2288                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2289                 intel_dp_get_m_n(intel_crtc, pipe_config);
2290                 break;
2291         default:
2292                 break;
2293         }
2294
2295         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2296                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2297                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2298                         pipe_config->has_audio = true;
2299         }
2300
2301         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2302             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2303                 /*
2304                  * This is a big fat ugly hack.
2305                  *
2306                  * Some machines in UEFI boot mode provide us a VBT that has 18
2307                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2308                  * unknown we fail to light up. Yet the same BIOS boots up with
2309                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2310                  * max, not what it tells us to use.
2311                  *
2312                  * Note: This will still be broken if the eDP panel is not lit
2313                  * up by the BIOS, and thus we can't get the mode at module
2314                  * load.
2315                  */
2316                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2317                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2318                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2319         }
2320
2321         intel_ddi_clock_get(encoder, pipe_config);
2322
2323         if (IS_BROXTON(dev_priv))
2324                 pipe_config->lane_lat_optim_mask =
2325                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2326 }
2327
2328 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2329                                      struct intel_crtc_state *pipe_config,
2330                                      struct drm_connector_state *conn_state)
2331 {
2332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2333         int type = encoder->type;
2334         int port = intel_ddi_get_encoder_port(encoder);
2335         int ret;
2336
2337         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2338
2339         if (port == PORT_A)
2340                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2341
2342         if (type == INTEL_OUTPUT_HDMI)
2343                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2344         else
2345                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2346
2347         if (IS_BROXTON(dev_priv) && ret)
2348                 pipe_config->lane_lat_optim_mask =
2349                         bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2350                                                              pipe_config);
2351
2352         return ret;
2353
2354 }
2355
2356 static const struct drm_encoder_funcs intel_ddi_funcs = {
2357         .reset = intel_dp_encoder_reset,
2358         .destroy = intel_dp_encoder_destroy,
2359 };
2360
2361 static struct intel_connector *
2362 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2363 {
2364         struct intel_connector *connector;
2365         enum port port = intel_dig_port->port;
2366
2367         connector = intel_connector_alloc();
2368         if (!connector)
2369                 return NULL;
2370
2371         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2372         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2373                 kfree(connector);
2374                 return NULL;
2375         }
2376
2377         return connector;
2378 }
2379
2380 static struct intel_connector *
2381 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2382 {
2383         struct intel_connector *connector;
2384         enum port port = intel_dig_port->port;
2385
2386         connector = intel_connector_alloc();
2387         if (!connector)
2388                 return NULL;
2389
2390         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2391         intel_hdmi_init_connector(intel_dig_port, connector);
2392
2393         return connector;
2394 }
2395
2396 struct intel_shared_dpll *
2397 intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
2398 {
2399         struct intel_connector *connector = intel_dp->attached_connector;
2400         struct intel_encoder *encoder = connector->encoder;
2401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2402         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2403         struct intel_shared_dpll *pll = NULL;
2404         struct intel_shared_dpll_config tmp_pll_config;
2405         enum intel_dpll_id dpll_id;
2406
2407         if (IS_BROXTON(dev_priv)) {
2408                 dpll_id =  (enum intel_dpll_id)dig_port->port;
2409                 /*
2410                  * Select the required PLL. This works for platforms where
2411                  * there is no shared DPLL.
2412                  */
2413                 pll = &dev_priv->shared_dplls[dpll_id];
2414                 if (WARN_ON(pll->active_mask)) {
2415
2416                         DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
2417                                   pll->active_mask);
2418                         return NULL;
2419                 }
2420                 tmp_pll_config = pll->config;
2421                 if (!bxt_ddi_dp_set_dpll_hw_state(clock,
2422                                                   &pll->config.hw_state)) {
2423                         DRM_ERROR("Could not setup DPLL\n");
2424                         pll->config = tmp_pll_config;
2425                         return NULL;
2426                 }
2427         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2428                 pll = skl_find_link_pll(dev_priv, clock);
2429         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2430                 pll = hsw_ddi_dp_get_dpll(encoder, clock);
2431         }
2432         return pll;
2433 }
2434
2435 void intel_ddi_init(struct drm_device *dev, enum port port)
2436 {
2437         struct drm_i915_private *dev_priv = to_i915(dev);
2438         struct intel_digital_port *intel_dig_port;
2439         struct intel_encoder *intel_encoder;
2440         struct drm_encoder *encoder;
2441         bool init_hdmi, init_dp;
2442         int max_lanes;
2443
2444         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2445                 switch (port) {
2446                 case PORT_A:
2447                         max_lanes = 4;
2448                         break;
2449                 case PORT_E:
2450                         max_lanes = 0;
2451                         break;
2452                 default:
2453                         max_lanes = 4;
2454                         break;
2455                 }
2456         } else {
2457                 switch (port) {
2458                 case PORT_A:
2459                         max_lanes = 2;
2460                         break;
2461                 case PORT_E:
2462                         max_lanes = 2;
2463                         break;
2464                 default:
2465                         max_lanes = 4;
2466                         break;
2467                 }
2468         }
2469
2470         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2471                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2472         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2473         if (!init_dp && !init_hdmi) {
2474                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2475                               port_name(port));
2476                 return;
2477         }
2478
2479         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2480         if (!intel_dig_port)
2481                 return;
2482
2483         intel_encoder = &intel_dig_port->base;
2484         encoder = &intel_encoder->base;
2485
2486         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2487                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2488
2489         intel_encoder->compute_config = intel_ddi_compute_config;
2490         intel_encoder->enable = intel_enable_ddi;
2491         if (IS_BROXTON(dev_priv))
2492                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2493         intel_encoder->pre_enable = intel_ddi_pre_enable;
2494         intel_encoder->disable = intel_disable_ddi;
2495         intel_encoder->post_disable = intel_ddi_post_disable;
2496         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2497         intel_encoder->get_config = intel_ddi_get_config;
2498         intel_encoder->suspend = intel_dp_encoder_suspend;
2499
2500         intel_dig_port->port = port;
2501         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2502                                           (DDI_BUF_PORT_REVERSAL |
2503                                            DDI_A_4_LANES);
2504
2505         /*
2506          * Bspec says that DDI_A_4_LANES is the only supported configuration
2507          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2508          * wasn't lit up at boot.  Force this bit on in our internal
2509          * configuration so that we use the proper lane count for our
2510          * calculations.
2511          */
2512         if (IS_BROXTON(dev) && port == PORT_A) {
2513                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2514                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2515                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2516                         max_lanes = 4;
2517                 }
2518         }
2519
2520         intel_dig_port->max_lanes = max_lanes;
2521
2522         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2523         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2524         intel_encoder->cloneable = 0;
2525
2526         if (init_dp) {
2527                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2528                         goto err;
2529
2530                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2531                 /*
2532                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2533                  * interrupts to check the external panel connection.
2534                  */
2535                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
2536                         dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2537                 else
2538                         dev_priv->hotplug.irq_port[port] = intel_dig_port;
2539         }
2540
2541         /* In theory we don't need the encoder->type check, but leave it just in
2542          * case we have some really bad VBTs... */
2543         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2544                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2545                         goto err;
2546         }
2547
2548         return;
2549
2550 err:
2551         drm_encoder_cleanup(encoder);
2552         kfree(intel_dig_port);
2553 }