2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
65 typedef struct intel_limit intel_limit_t;
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
72 intel_pch_rawclk(struct drm_device *dev)
74 struct drm_i915_private *dev_priv = dev->dev_private;
76 WARN_ON(!HAS_PCH_SPLIT(dev));
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
312 static const intel_limit_t intel_limits_vlv = {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk, intel_clock_t *clock)
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 if (WARN_ON(clock->n == 0 || clock->p == 0))
334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 struct drm_device *dev = crtc->dev;
357 const intel_limit_t *limit;
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360 if (intel_is_dual_link_lvds(dev)) {
361 if (refclk == 100000)
362 limit = &intel_limits_ironlake_dual_lvds_100m;
364 limit = &intel_limits_ironlake_dual_lvds;
366 if (refclk == 100000)
367 limit = &intel_limits_ironlake_single_lvds_100m;
369 limit = &intel_limits_ironlake_single_lvds;
372 limit = &intel_limits_ironlake_dac;
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
379 struct drm_device *dev = crtc->dev;
380 const intel_limit_t *limit;
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383 if (intel_is_dual_link_lvds(dev))
384 limit = &intel_limits_g4x_dual_channel_lvds;
386 limit = &intel_limits_g4x_single_channel_lvds;
387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389 limit = &intel_limits_g4x_hdmi;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391 limit = &intel_limits_g4x_sdvo;
392 } else /* The option is for other outputs */
393 limit = &intel_limits_i9xx_sdvo;
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
403 if (HAS_PCH_SPLIT(dev))
404 limit = intel_ironlake_limit(crtc, refclk);
405 else if (IS_G4X(dev)) {
406 limit = intel_g4x_limit(crtc);
407 } else if (IS_PINEVIEW(dev)) {
408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409 limit = &intel_limits_pineview_lvds;
411 limit = &intel_limits_pineview_sdvo;
412 } else if (IS_VALLEYVIEW(dev)) {
413 limit = &intel_limits_vlv;
414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
418 limit = &intel_limits_i9xx_sdvo;
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421 limit = &intel_limits_i8xx_lvds;
422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423 limit = &intel_limits_i8xx_dvo;
425 limit = &intel_limits_i8xx_dac;
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
435 if (WARN_ON(clock->n == 0 || clock->p == 0))
437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
448 clock->m = i9xx_dpll_compute_m(clock);
449 clock->p = clock->p1 * clock->p2;
450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492 INTELPllInvalid("dot out of range\n");
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
502 struct drm_device *dev = crtc->dev;
506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
512 if (intel_is_dual_link_lvds(dev))
513 clock.p2 = limit->p2.p2_fast;
515 clock.p2 = limit->p2.p2_slow;
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
520 clock.p2 = limit->p2.p2_fast;
523 memset(best_clock, 0, sizeof(*best_clock));
525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
529 if (clock.m2 >= clock.m1)
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
542 clock.p != match_clock->p)
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
555 return (err != target);
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
563 struct drm_device *dev = crtc->dev;
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
576 clock.p2 = limit->p2.p2_slow;
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
581 clock.p2 = limit->p2.p2_fast;
584 memset(best_clock, 0, sizeof(*best_clock));
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
596 pineview_clock(refclk, &clock);
597 if (!intel_PLL_is_valid(dev, limit,
601 clock.p != match_clock->p)
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
614 return (err != target);
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
622 struct drm_device *dev = crtc->dev;
626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631 if (intel_is_dual_link_lvds(dev))
632 clock.p2 = limit->p2.p2_fast;
634 clock.p2 = limit->p2.p2_slow;
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
639 clock.p2 = limit->p2.p2_fast;
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
655 i9xx_clock(refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
660 this_err = abs(clock.dot - target);
661 if (this_err < err_most) {
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
679 struct drm_device *dev = crtc->dev;
681 unsigned int bestppm = 1000000;
682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
686 target *= 5; /* fast clock */
688 memset(best_clock, 0, sizeof(*best_clock));
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695 clock.p = clock.p1 * clock.p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698 unsigned int ppm, diff;
700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
703 vlv_clock(refclk, &clock);
705 if (!intel_PLL_is_valid(dev, limit,
709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
712 if (ppm < 100 && clock.p > best_clock->p) {
718 if (bestppm >= 10 && ppm < bestppm - 10) {
731 bool intel_crtc_active(struct drm_crtc *crtc)
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
744 return intel_crtc->active && crtc->fb &&
745 intel_crtc->config.adjusted_mode.crtc_clock;
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
754 return intel_crtc->config.cpu_transcoder;
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
762 frame = I915_READ(frame_reg);
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
769 * intel_wait_for_vblank - wait for vblank on a given pipe
771 * @pipe: pipe to wait for
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 int pipestat_reg = PIPESTAT(pipe);
781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
806 DRM_DEBUG_KMS("vblank wait timed out\n");
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
817 line_mask = DSL_LINEMASK_GEN2;
819 line_mask = DSL_LINEMASK_GEN3;
821 line1 = I915_READ(reg) & line_mask;
823 line2 = I915_READ(reg) & line_mask;
825 return line1 == line2;
829 * intel_wait_for_pipe_off - wait for pipe to turn off
831 * @pipe: pipe to wait for
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
838 * wait for the pipe register state bit to turn off
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
851 if (INTEL_INFO(dev)->gen >= 4) {
852 int reg = PIPECONF(cpu_transcoder);
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
857 WARN(1, "pipe_off wait timed out\n");
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
877 if (HAS_PCH_IBX(dev_priv->dev)) {
880 bit = SDE_PORTB_HOTPLUG;
883 bit = SDE_PORTC_HOTPLUG;
886 bit = SDE_PORTD_HOTPLUG;
894 bit = SDE_PORTB_HOTPLUG_CPT;
897 bit = SDE_PORTC_HOTPLUG_CPT;
900 bit = SDE_PORTD_HOTPLUG_CPT;
907 return I915_READ(SDEISR) & bit;
910 static const char *state_string(bool enabled)
912 return enabled ? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954 if (crtc->config.shared_dpll < 0)
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
966 struct intel_dpll_hw_state hw_state;
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1063 int pp_reg, lvds_reg;
1065 enum pipe panel_pipe = PIPE_A;
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1072 pp_reg = PP_CONTROL;
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1092 struct drm_device *dev = dev_priv->dev;
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1157 struct drm_device *dev = dev_priv->dev;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1187 struct drm_device *dev = dev_priv->dev;
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1248 if ((val & DP_PORT_EN) == 0)
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1266 if ((val & SDVO_ENABLE) == 0)
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1282 if ((val & LVDS_PORT_EN) == 0)
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1363 static void intel_init_dpio(struct drm_device *dev)
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1367 if (!IS_VALLEYVIEW(dev))
1370 /* Enable the CRI clock source so we can get at the display */
1371 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1372 DPLL_INTEGRATED_CRI_CLK_VLV);
1374 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1376 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1377 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1378 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1379 * b. The other bits such as sfr settings / modesel may all be set
1382 * This should only be done on init and resume from S3 with both
1383 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1385 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1388 static void vlv_enable_pll(struct intel_crtc *crtc)
1390 struct drm_device *dev = crtc->base.dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 int reg = DPLL(crtc->pipe);
1393 u32 dpll = crtc->config.dpll_hw_state.dpll;
1395 assert_pipe_disabled(dev_priv, crtc->pipe);
1397 /* No really, not for ILK+ */
1398 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1400 /* PLL is protected by panel, make sure we can write it */
1401 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1402 assert_panel_unlocked(dev_priv, crtc->pipe);
1404 I915_WRITE(reg, dpll);
1408 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1409 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1411 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1412 POSTING_READ(DPLL_MD(crtc->pipe));
1414 /* We do this three times for luck */
1415 I915_WRITE(reg, dpll);
1417 udelay(150); /* wait for warmup */
1418 I915_WRITE(reg, dpll);
1420 udelay(150); /* wait for warmup */
1421 I915_WRITE(reg, dpll);
1423 udelay(150); /* wait for warmup */
1426 static void i9xx_enable_pll(struct intel_crtc *crtc)
1428 struct drm_device *dev = crtc->base.dev;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 int reg = DPLL(crtc->pipe);
1431 u32 dpll = crtc->config.dpll_hw_state.dpll;
1433 assert_pipe_disabled(dev_priv, crtc->pipe);
1435 /* No really, not for ILK+ */
1436 BUG_ON(dev_priv->info->gen >= 5);
1438 /* PLL is protected by panel, make sure we can write it */
1439 if (IS_MOBILE(dev) && !IS_I830(dev))
1440 assert_panel_unlocked(dev_priv, crtc->pipe);
1442 I915_WRITE(reg, dpll);
1444 /* Wait for the clocks to stabilize. */
1448 if (INTEL_INFO(dev)->gen >= 4) {
1449 I915_WRITE(DPLL_MD(crtc->pipe),
1450 crtc->config.dpll_hw_state.dpll_md);
1452 /* The pixel multiplier can only be updated once the
1453 * DPLL is enabled and the clocks are stable.
1455 * So write it again.
1457 I915_WRITE(reg, dpll);
1460 /* We do this three times for luck */
1461 I915_WRITE(reg, dpll);
1463 udelay(150); /* wait for warmup */
1464 I915_WRITE(reg, dpll);
1466 udelay(150); /* wait for warmup */
1467 I915_WRITE(reg, dpll);
1469 udelay(150); /* wait for warmup */
1473 * i9xx_disable_pll - disable a PLL
1474 * @dev_priv: i915 private structure
1475 * @pipe: pipe PLL to disable
1477 * Disable the PLL for @pipe, making sure the pipe is off first.
1479 * Note! This is for pre-ILK only.
1481 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1483 /* Don't disable pipe A or pipe A PLLs if needed */
1484 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1490 I915_WRITE(DPLL(pipe), 0);
1491 POSTING_READ(DPLL(pipe));
1494 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1498 /* Make sure the pipe isn't still relying on us */
1499 assert_pipe_disabled(dev_priv, pipe);
1501 /* Leave integrated clock source enabled */
1503 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1504 I915_WRITE(DPLL(pipe), val);
1505 POSTING_READ(DPLL(pipe));
1508 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1509 struct intel_digital_port *dport)
1513 switch (dport->port) {
1515 port_mask = DPLL_PORTB_READY_MASK;
1518 port_mask = DPLL_PORTC_READY_MASK;
1524 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1525 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1526 port_name(dport->port), I915_READ(DPLL(0)));
1530 * ironlake_enable_shared_dpll - enable PCH PLL
1531 * @dev_priv: i915 private structure
1532 * @pipe: pipe PLL to enable
1534 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1535 * drives the transcoder clock.
1537 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1539 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1540 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1542 /* PCH PLLs only available on ILK, SNB and IVB */
1543 BUG_ON(dev_priv->info->gen < 5);
1544 if (WARN_ON(pll == NULL))
1547 if (WARN_ON(pll->refcount == 0))
1550 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1551 pll->name, pll->active, pll->on,
1552 crtc->base.base.id);
1554 if (pll->active++) {
1556 assert_shared_dpll_enabled(dev_priv, pll);
1561 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1562 pll->enable(dev_priv, pll);
1566 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1568 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1569 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1571 /* PCH only available on ILK+ */
1572 BUG_ON(dev_priv->info->gen < 5);
1573 if (WARN_ON(pll == NULL))
1576 if (WARN_ON(pll->refcount == 0))
1579 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1580 pll->name, pll->active, pll->on,
1581 crtc->base.base.id);
1583 if (WARN_ON(pll->active == 0)) {
1584 assert_shared_dpll_disabled(dev_priv, pll);
1588 assert_shared_dpll_enabled(dev_priv, pll);
1593 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1594 pll->disable(dev_priv, pll);
1598 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1601 struct drm_device *dev = dev_priv->dev;
1602 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1604 uint32_t reg, val, pipeconf_val;
1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv->info->gen < 5);
1609 /* Make sure PCH DPLL is enabled */
1610 assert_shared_dpll_enabled(dev_priv,
1611 intel_crtc_to_shared_dpll(intel_crtc));
1613 /* FDI must be feeding us bits for PCH ports */
1614 assert_fdi_tx_enabled(dev_priv, pipe);
1615 assert_fdi_rx_enabled(dev_priv, pipe);
1617 if (HAS_PCH_CPT(dev)) {
1618 /* Workaround: Set the timing override bit before enabling the
1619 * pch transcoder. */
1620 reg = TRANS_CHICKEN2(pipe);
1621 val = I915_READ(reg);
1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623 I915_WRITE(reg, val);
1626 reg = PCH_TRANSCONF(pipe);
1627 val = I915_READ(reg);
1628 pipeconf_val = I915_READ(PIPECONF(pipe));
1630 if (HAS_PCH_IBX(dev_priv->dev)) {
1632 * make the BPC in transcoder be consistent with
1633 * that in pipeconf reg.
1635 val &= ~PIPECONF_BPC_MASK;
1636 val |= pipeconf_val & PIPECONF_BPC_MASK;
1639 val &= ~TRANS_INTERLACE_MASK;
1640 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1641 if (HAS_PCH_IBX(dev_priv->dev) &&
1642 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1643 val |= TRANS_LEGACY_INTERLACED_ILK;
1645 val |= TRANS_INTERLACED;
1647 val |= TRANS_PROGRESSIVE;
1649 I915_WRITE(reg, val | TRANS_ENABLE);
1650 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1651 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1654 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1655 enum transcoder cpu_transcoder)
1657 u32 val, pipeconf_val;
1659 /* PCH only available on ILK+ */
1660 BUG_ON(dev_priv->info->gen < 5);
1662 /* FDI must be feeding us bits for PCH ports */
1663 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1664 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1666 /* Workaround: set timing override bit. */
1667 val = I915_READ(_TRANSA_CHICKEN2);
1668 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1669 I915_WRITE(_TRANSA_CHICKEN2, val);
1672 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1674 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1675 PIPECONF_INTERLACED_ILK)
1676 val |= TRANS_INTERLACED;
1678 val |= TRANS_PROGRESSIVE;
1680 I915_WRITE(LPT_TRANSCONF, val);
1681 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1682 DRM_ERROR("Failed to enable PCH transcoder\n");
1685 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1688 struct drm_device *dev = dev_priv->dev;
1691 /* FDI relies on the transcoder */
1692 assert_fdi_tx_disabled(dev_priv, pipe);
1693 assert_fdi_rx_disabled(dev_priv, pipe);
1695 /* Ports must be off as well */
1696 assert_pch_ports_disabled(dev_priv, pipe);
1698 reg = PCH_TRANSCONF(pipe);
1699 val = I915_READ(reg);
1700 val &= ~TRANS_ENABLE;
1701 I915_WRITE(reg, val);
1702 /* wait for PCH transcoder off, transcoder state */
1703 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1704 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1706 if (!HAS_PCH_IBX(dev)) {
1707 /* Workaround: Clear the timing override chicken bit again. */
1708 reg = TRANS_CHICKEN2(pipe);
1709 val = I915_READ(reg);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(reg, val);
1715 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1719 val = I915_READ(LPT_TRANSCONF);
1720 val &= ~TRANS_ENABLE;
1721 I915_WRITE(LPT_TRANSCONF, val);
1722 /* wait for PCH transcoder off, transcoder state */
1723 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1724 DRM_ERROR("Failed to disable PCH transcoder\n");
1726 /* Workaround: clear timing override bit. */
1727 val = I915_READ(_TRANSA_CHICKEN2);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(_TRANSA_CHICKEN2, val);
1733 * intel_enable_pipe - enable a pipe, asserting requirements
1734 * @dev_priv: i915 private structure
1735 * @pipe: pipe to enable
1736 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1738 * Enable @pipe, making sure that various hardware specific requirements
1739 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1741 * @pipe should be %PIPE_A or %PIPE_B.
1743 * Will wait until the pipe is actually running (i.e. first vblank) before
1746 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1747 bool pch_port, bool dsi)
1749 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1751 enum pipe pch_transcoder;
1755 assert_planes_disabled(dev_priv, pipe);
1756 assert_cursor_disabled(dev_priv, pipe);
1757 assert_sprites_disabled(dev_priv, pipe);
1759 if (HAS_PCH_LPT(dev_priv->dev))
1760 pch_transcoder = TRANSCODER_A;
1762 pch_transcoder = pipe;
1765 * A pipe without a PLL won't actually be able to drive bits from
1766 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1769 if (!HAS_PCH_SPLIT(dev_priv->dev))
1771 assert_dsi_pll_enabled(dev_priv);
1773 assert_pll_enabled(dev_priv, pipe);
1776 /* if driving the PCH, we need FDI enabled */
1777 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1778 assert_fdi_tx_pll_enabled(dev_priv,
1779 (enum pipe) cpu_transcoder);
1781 /* FIXME: assert CPU port conditions for SNB+ */
1784 reg = PIPECONF(cpu_transcoder);
1785 val = I915_READ(reg);
1786 if (val & PIPECONF_ENABLE)
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1794 * intel_disable_pipe - disable a pipe, asserting requirements
1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1801 * @pipe should be %PIPE_A or %PIPE_B.
1803 * Will wait until the pipe has shut down before returning.
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1817 assert_planes_disabled(dev_priv, pipe);
1818 assert_cursor_disabled(dev_priv, pipe);
1819 assert_sprites_disabled(dev_priv, pipe);
1821 /* Don't disable pipe A or pipe A PLLs if needed */
1822 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1825 reg = PIPECONF(cpu_transcoder);
1826 val = I915_READ(reg);
1827 if ((val & PIPECONF_ENABLE) == 0)
1830 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1831 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1835 * Plane regs are double buffered, going from enabled->disabled needs a
1836 * trigger in order to latch. The display address reg provides this.
1838 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1841 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1843 I915_WRITE(reg, I915_READ(reg));
1848 * intel_enable_primary_plane - enable the primary plane on a given pipe
1849 * @dev_priv: i915 private structure
1850 * @plane: plane to enable
1851 * @pipe: pipe being fed
1853 * Enable @plane on @pipe, making sure that @pipe is running first.
1855 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1856 enum plane plane, enum pipe pipe)
1858 struct intel_crtc *intel_crtc =
1859 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1863 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1864 assert_pipe_enabled(dev_priv, pipe);
1866 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1868 intel_crtc->primary_enabled = true;
1870 reg = DSPCNTR(plane);
1871 val = I915_READ(reg);
1872 if (val & DISPLAY_PLANE_ENABLE)
1875 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1876 intel_flush_primary_plane(dev_priv, plane);
1877 intel_wait_for_vblank(dev_priv->dev, pipe);
1881 * intel_disable_primary_plane - disable the primary plane
1882 * @dev_priv: i915 private structure
1883 * @plane: plane to disable
1884 * @pipe: pipe consuming the data
1886 * Disable @plane; should be an independent operation.
1888 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1889 enum plane plane, enum pipe pipe)
1891 struct intel_crtc *intel_crtc =
1892 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1896 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1898 intel_crtc->primary_enabled = false;
1900 reg = DSPCNTR(plane);
1901 val = I915_READ(reg);
1902 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1905 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1906 intel_flush_primary_plane(dev_priv, plane);
1907 intel_wait_for_vblank(dev_priv->dev, pipe);
1910 static bool need_vtd_wa(struct drm_device *dev)
1912 #ifdef CONFIG_INTEL_IOMMU
1913 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1920 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1921 struct drm_i915_gem_object *obj,
1922 struct intel_ring_buffer *pipelined)
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1928 switch (obj->tiling_mode) {
1929 case I915_TILING_NONE:
1930 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1931 alignment = 128 * 1024;
1932 else if (INTEL_INFO(dev)->gen >= 4)
1933 alignment = 4 * 1024;
1935 alignment = 64 * 1024;
1938 /* pin() will align the object as required by fence */
1942 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1948 /* Note that the w/a also requires 64 PTE of padding following the
1949 * bo. We currently fill all unused PTE with the shadow page and so
1950 * we should always have valid PTE following the scanout preventing
1953 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1954 alignment = 256 * 1024;
1956 dev_priv->mm.interruptible = false;
1957 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1959 goto err_interruptible;
1961 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1962 * fence, whereas 965+ only requires a fence if using
1963 * framebuffer compression. For simplicity, we always install
1964 * a fence as the cost is not that onerous.
1966 ret = i915_gem_object_get_fence(obj);
1970 i915_gem_object_pin_fence(obj);
1972 dev_priv->mm.interruptible = true;
1976 i915_gem_object_unpin_from_display_plane(obj);
1978 dev_priv->mm.interruptible = true;
1982 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1984 i915_gem_object_unpin_fence(obj);
1985 i915_gem_object_unpin_from_display_plane(obj);
1988 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1989 * is assumed to be a power-of-two. */
1990 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1991 unsigned int tiling_mode,
1995 if (tiling_mode != I915_TILING_NONE) {
1996 unsigned int tile_rows, tiles;
2001 tiles = *x / (512/cpp);
2004 return tile_rows * pitch * 8 + tiles * 4096;
2006 unsigned int offset;
2008 offset = *y * pitch + *x * cpp;
2010 *x = (offset & 4095) / cpp;
2011 return offset & -4096;
2015 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2018 struct drm_device *dev = crtc->dev;
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021 struct intel_framebuffer *intel_fb;
2022 struct drm_i915_gem_object *obj;
2023 int plane = intel_crtc->plane;
2024 unsigned long linear_offset;
2033 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2037 intel_fb = to_intel_framebuffer(fb);
2038 obj = intel_fb->obj;
2040 reg = DSPCNTR(plane);
2041 dspcntr = I915_READ(reg);
2042 /* Mask out pixel format bits in case we change it */
2043 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2044 switch (fb->pixel_format) {
2046 dspcntr |= DISPPLANE_8BPP;
2048 case DRM_FORMAT_XRGB1555:
2049 case DRM_FORMAT_ARGB1555:
2050 dspcntr |= DISPPLANE_BGRX555;
2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
2075 if (INTEL_INFO(dev)->gen >= 4) {
2076 if (obj->tiling_mode != I915_TILING_NONE)
2077 dspcntr |= DISPPLANE_TILED;
2079 dspcntr &= ~DISPPLANE_TILED;
2083 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2085 I915_WRITE(reg, dspcntr);
2087 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2089 if (INTEL_INFO(dev)->gen >= 4) {
2090 intel_crtc->dspaddr_offset =
2091 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2092 fb->bits_per_pixel / 8,
2094 linear_offset -= intel_crtc->dspaddr_offset;
2096 intel_crtc->dspaddr_offset = linear_offset;
2099 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2100 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103 if (INTEL_INFO(dev)->gen >= 4) {
2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
2124 unsigned long linear_offset;
2134 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145 switch (fb->pixel_format) {
2147 dspcntr |= DISPPLANE_8BPP;
2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
2172 if (obj->tiling_mode != I915_TILING_NONE)
2173 dspcntr |= DISPPLANE_TILED;
2175 dspcntr &= ~DISPPLANE_TILED;
2177 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2178 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2180 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2182 I915_WRITE(reg, dspcntr);
2184 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2185 intel_crtc->dspaddr_offset =
2186 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2187 fb->bits_per_pixel / 8,
2189 linear_offset -= intel_crtc->dspaddr_offset;
2191 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2192 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2194 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2195 I915_MODIFY_DISPBASE(DSPSURF(plane),
2196 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2197 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2198 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2200 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2201 I915_WRITE(DSPLINOFF(plane), linear_offset);
2208 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2210 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2211 int x, int y, enum mode_set_atomic state)
2213 struct drm_device *dev = crtc->dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2216 if (dev_priv->display.disable_fbc)
2217 dev_priv->display.disable_fbc(dev);
2218 intel_increase_pllclock(crtc);
2220 return dev_priv->display.update_plane(crtc, fb, x, y);
2223 void intel_display_handle_reset(struct drm_device *dev)
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct drm_crtc *crtc;
2229 * Flips in the rings have been nuked by the reset,
2230 * so complete all pending flips so that user space
2231 * will get its events and not get stuck.
2233 * Also update the base address of all primary
2234 * planes to the the last fb to make sure we're
2235 * showing the correct fb after a reset.
2237 * Need to make two loops over the crtcs so that we
2238 * don't try to grab a crtc mutex before the
2239 * pending_flip_queue really got woken up.
2242 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244 enum plane plane = intel_crtc->plane;
2246 intel_prepare_page_flip(dev, plane);
2247 intel_finish_page_flip_plane(dev, plane);
2250 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253 mutex_lock(&crtc->mutex);
2255 * FIXME: Once we have proper support for primary planes (and
2256 * disabling them without disabling the entire crtc) allow again
2259 if (intel_crtc->active && crtc->fb)
2260 dev_priv->display.update_plane(crtc, crtc->fb,
2262 mutex_unlock(&crtc->mutex);
2267 intel_finish_fb(struct drm_framebuffer *old_fb)
2269 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2270 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2271 bool was_interruptible = dev_priv->mm.interruptible;
2274 /* Big Hammer, we also need to ensure that any pending
2275 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2276 * current scanout is retired before unpinning the old
2279 * This should only fail upon a hung GPU, in which case we
2280 * can safely continue.
2282 dev_priv->mm.interruptible = false;
2283 ret = i915_gem_object_finish_gpu(obj);
2284 dev_priv->mm.interruptible = was_interruptible;
2289 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2291 struct drm_device *dev = crtc->dev;
2292 struct drm_i915_master_private *master_priv;
2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2295 if (!dev->primary->master)
2298 master_priv = dev->primary->master->driver_priv;
2299 if (!master_priv->sarea_priv)
2302 switch (intel_crtc->pipe) {
2304 master_priv->sarea_priv->pipeA_x = x;
2305 master_priv->sarea_priv->pipeA_y = y;
2308 master_priv->sarea_priv->pipeB_x = x;
2309 master_priv->sarea_priv->pipeB_y = y;
2317 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2318 struct drm_framebuffer *fb)
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 struct drm_framebuffer *old_fb;
2328 DRM_ERROR("No FB bound\n");
2332 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2333 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2334 plane_name(intel_crtc->plane),
2335 INTEL_INFO(dev)->num_pipes);
2339 mutex_lock(&dev->struct_mutex);
2340 ret = intel_pin_and_fence_fb_obj(dev,
2341 to_intel_framebuffer(fb)->obj,
2344 mutex_unlock(&dev->struct_mutex);
2345 DRM_ERROR("pin & fence failed\n");
2350 * Update pipe size and adjust fitter if needed: the reason for this is
2351 * that in compute_mode_changes we check the native mode (not the pfit
2352 * mode) to see if we can flip rather than do a full mode set. In the
2353 * fastboot case, we'll flip, but if we don't update the pipesrc and
2354 * pfit state, we'll end up with a big fb scanned out into the wrong
2357 * To fix this properly, we need to hoist the checks up into
2358 * compute_mode_changes (or above), check the actual pfit state and
2359 * whether the platform allows pfit disable with pipe active, and only
2360 * then update the pipesrc and pfit state, even on the flip path.
2362 if (i915_fastboot) {
2363 const struct drm_display_mode *adjusted_mode =
2364 &intel_crtc->config.adjusted_mode;
2366 I915_WRITE(PIPESRC(intel_crtc->pipe),
2367 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2368 (adjusted_mode->crtc_vdisplay - 1));
2369 if (!intel_crtc->config.pch_pfit.enabled &&
2370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2372 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2373 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2374 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2378 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2380 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2381 mutex_unlock(&dev->struct_mutex);
2382 DRM_ERROR("failed to update base address\n");
2392 if (intel_crtc->active && old_fb != fb)
2393 intel_wait_for_vblank(dev, intel_crtc->pipe);
2394 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2397 intel_update_fbc(dev);
2398 intel_edp_psr_update(dev);
2399 mutex_unlock(&dev->struct_mutex);
2401 intel_crtc_update_sarea_pos(crtc, x, y);
2406 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
2414 /* enable normal train */
2415 reg = FDI_TX_CTL(pipe);
2416 temp = I915_READ(reg);
2417 if (IS_IVYBRIDGE(dev)) {
2418 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2419 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2424 I915_WRITE(reg, temp);
2426 reg = FDI_RX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 if (HAS_PCH_CPT(dev)) {
2429 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2430 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_NONE;
2435 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2437 /* wait one idle pattern time */
2441 /* IVB wants error correction enabled */
2442 if (IS_IVYBRIDGE(dev))
2443 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2444 FDI_FE_ERRC_ENABLE);
2447 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2449 return crtc->base.enabled && crtc->active &&
2450 crtc->config.has_pch_encoder;
2453 static void ivb_modeset_global_resources(struct drm_device *dev)
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *pipe_B_crtc =
2457 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2458 struct intel_crtc *pipe_C_crtc =
2459 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2463 * When everything is off disable fdi C so that we could enable fdi B
2464 * with all lanes. Note that we don't care about enabled pipes without
2465 * an enabled pch encoder.
2467 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2468 !pipe_has_enabled_pch(pipe_C_crtc)) {
2469 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2470 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2472 temp = I915_READ(SOUTH_CHICKEN1);
2473 temp &= ~FDI_BC_BIFURCATION_SELECT;
2474 DRM_DEBUG_KMS("disabling fdi C rx\n");
2475 I915_WRITE(SOUTH_CHICKEN1, temp);
2479 /* The FDI link training functions for ILK/Ibexpeak. */
2480 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2482 struct drm_device *dev = crtc->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2485 int pipe = intel_crtc->pipe;
2486 int plane = intel_crtc->plane;
2487 u32 reg, temp, tries;
2489 /* FDI needs bits from pipe & plane first */
2490 assert_pipe_enabled(dev_priv, pipe);
2491 assert_plane_enabled(dev_priv, plane);
2493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2495 reg = FDI_RX_IMR(pipe);
2496 temp = I915_READ(reg);
2497 temp &= ~FDI_RX_SYMBOL_LOCK;
2498 temp &= ~FDI_RX_BIT_LOCK;
2499 I915_WRITE(reg, temp);
2503 /* enable CPU FDI TX and PCH FDI RX */
2504 reg = FDI_TX_CTL(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2507 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2512 reg = FDI_RX_CTL(pipe);
2513 temp = I915_READ(reg);
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_1;
2516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2521 /* Ironlake workaround, enable clock pointer after FDI enable*/
2522 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2523 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2524 FDI_RX_PHASE_SYNC_POINTER_EN);
2526 reg = FDI_RX_IIR(pipe);
2527 for (tries = 0; tries < 5; tries++) {
2528 temp = I915_READ(reg);
2529 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2531 if ((temp & FDI_RX_BIT_LOCK)) {
2532 DRM_DEBUG_KMS("FDI train 1 done.\n");
2533 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2538 DRM_ERROR("FDI train 1 fail!\n");
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
2545 I915_WRITE(reg, temp);
2547 reg = FDI_RX_CTL(pipe);
2548 temp = I915_READ(reg);
2549 temp &= ~FDI_LINK_TRAIN_NONE;
2550 temp |= FDI_LINK_TRAIN_PATTERN_2;
2551 I915_WRITE(reg, temp);
2556 reg = FDI_RX_IIR(pipe);
2557 for (tries = 0; tries < 5; tries++) {
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2561 if (temp & FDI_RX_SYMBOL_LOCK) {
2562 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2563 DRM_DEBUG_KMS("FDI train 2 done.\n");
2568 DRM_ERROR("FDI train 2 fail!\n");
2570 DRM_DEBUG_KMS("FDI train done\n");
2574 static const int snb_b_fdi_train_param[] = {
2575 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2576 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2577 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2578 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2581 /* The FDI link training functions for SNB/Cougarpoint. */
2582 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2584 struct drm_device *dev = crtc->dev;
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2587 int pipe = intel_crtc->pipe;
2588 u32 reg, temp, i, retry;
2590 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2592 reg = FDI_RX_IMR(pipe);
2593 temp = I915_READ(reg);
2594 temp &= ~FDI_RX_SYMBOL_LOCK;
2595 temp &= ~FDI_RX_BIT_LOCK;
2596 I915_WRITE(reg, temp);
2601 /* enable CPU FDI TX and PCH FDI RX */
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2605 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2606 temp &= ~FDI_LINK_TRAIN_NONE;
2607 temp |= FDI_LINK_TRAIN_PATTERN_1;
2608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2611 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2613 I915_WRITE(FDI_RX_MISC(pipe),
2614 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2616 reg = FDI_RX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 if (HAS_PCH_CPT(dev)) {
2619 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2620 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2622 temp &= ~FDI_LINK_TRAIN_NONE;
2623 temp |= FDI_LINK_TRAIN_PATTERN_1;
2625 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2630 for (i = 0; i < 4; i++) {
2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2634 temp |= snb_b_fdi_train_param[i];
2635 I915_WRITE(reg, temp);
2640 for (retry = 0; retry < 5; retry++) {
2641 reg = FDI_RX_IIR(pipe);
2642 temp = I915_READ(reg);
2643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644 if (temp & FDI_RX_BIT_LOCK) {
2645 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2646 DRM_DEBUG_KMS("FDI train 1 done.\n");
2655 DRM_ERROR("FDI train 1 fail!\n");
2658 reg = FDI_TX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_NONE;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2;
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2665 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2667 I915_WRITE(reg, temp);
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 if (HAS_PCH_CPT(dev)) {
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2675 temp &= ~FDI_LINK_TRAIN_NONE;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2;
2678 I915_WRITE(reg, temp);
2683 for (i = 0; i < 4; i++) {
2684 reg = FDI_TX_CTL(pipe);
2685 temp = I915_READ(reg);
2686 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2687 temp |= snb_b_fdi_train_param[i];
2688 I915_WRITE(reg, temp);
2693 for (retry = 0; retry < 5; retry++) {
2694 reg = FDI_RX_IIR(pipe);
2695 temp = I915_READ(reg);
2696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2697 if (temp & FDI_RX_SYMBOL_LOCK) {
2698 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2699 DRM_DEBUG_KMS("FDI train 2 done.\n");
2708 DRM_ERROR("FDI train 2 fail!\n");
2710 DRM_DEBUG_KMS("FDI train done.\n");
2713 /* Manual link training for Ivy Bridge A0 parts */
2714 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2716 struct drm_device *dev = crtc->dev;
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2719 int pipe = intel_crtc->pipe;
2720 u32 reg, temp, i, j;
2722 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2724 reg = FDI_RX_IMR(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_RX_SYMBOL_LOCK;
2727 temp &= ~FDI_RX_BIT_LOCK;
2728 I915_WRITE(reg, temp);
2733 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2734 I915_READ(FDI_RX_IIR(pipe)));
2736 /* Try each vswing and preemphasis setting twice before moving on */
2737 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2738 /* disable first in case we need to retry */
2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2742 temp &= ~FDI_TX_ENABLE;
2743 I915_WRITE(reg, temp);
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_AUTO;
2748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749 temp &= ~FDI_RX_ENABLE;
2750 I915_WRITE(reg, temp);
2752 /* enable CPU FDI TX and PCH FDI RX */
2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2757 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2758 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2759 temp |= snb_b_fdi_train_param[j/2];
2760 temp |= FDI_COMPOSITE_SYNC;
2761 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2763 I915_WRITE(FDI_RX_MISC(pipe),
2764 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2766 reg = FDI_RX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2769 temp |= FDI_COMPOSITE_SYNC;
2770 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2773 udelay(1); /* should be 0.5us */
2775 for (i = 0; i < 4; i++) {
2776 reg = FDI_RX_IIR(pipe);
2777 temp = I915_READ(reg);
2778 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2780 if (temp & FDI_RX_BIT_LOCK ||
2781 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2782 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2783 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2787 udelay(1); /* should be 0.5us */
2790 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2798 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2799 I915_WRITE(reg, temp);
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2804 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2805 I915_WRITE(reg, temp);
2808 udelay(2); /* should be 1.5us */
2810 for (i = 0; i < 4; i++) {
2811 reg = FDI_RX_IIR(pipe);
2812 temp = I915_READ(reg);
2813 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2815 if (temp & FDI_RX_SYMBOL_LOCK ||
2816 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2817 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2818 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2822 udelay(2); /* should be 1.5us */
2825 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2829 DRM_DEBUG_KMS("FDI train done.\n");
2832 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2834 struct drm_device *dev = intel_crtc->base.dev;
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2836 int pipe = intel_crtc->pipe;
2840 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2841 reg = FDI_RX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2844 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2845 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2846 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2851 /* Switch from Rawclk to PCDclk */
2852 temp = I915_READ(reg);
2853 I915_WRITE(reg, temp | FDI_PCDCLK);
2858 /* Enable CPU FDI TX PLL, always on for Ironlake */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2862 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2869 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2871 struct drm_device *dev = intel_crtc->base.dev;
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 int pipe = intel_crtc->pipe;
2876 /* Switch from PCDclk to Rawclk */
2877 reg = FDI_RX_CTL(pipe);
2878 temp = I915_READ(reg);
2879 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2881 /* Disable CPU FDI TX PLL */
2882 reg = FDI_TX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2893 /* Wait for the clocks to turn off. */
2898 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
2906 /* disable CPU FDI tx and PCH FDI rx */
2907 reg = FDI_TX_CTL(pipe);
2908 temp = I915_READ(reg);
2909 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2912 reg = FDI_RX_CTL(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~(0x7 << 16);
2915 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2916 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2921 /* Ironlake workaround, disable clock pointer after downing FDI */
2922 if (HAS_PCH_IBX(dev)) {
2923 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2926 /* still set train pattern 1 */
2927 reg = FDI_TX_CTL(pipe);
2928 temp = I915_READ(reg);
2929 temp &= ~FDI_LINK_TRAIN_NONE;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1;
2931 I915_WRITE(reg, temp);
2933 reg = FDI_RX_CTL(pipe);
2934 temp = I915_READ(reg);
2935 if (HAS_PCH_CPT(dev)) {
2936 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2937 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942 /* BPC in FDI rx is consistent with that in PIPECONF */
2943 temp &= ~(0x07 << 16);
2944 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2945 I915_WRITE(reg, temp);
2951 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2953 struct drm_device *dev = crtc->dev;
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 unsigned long flags;
2959 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2960 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2963 spin_lock_irqsave(&dev->event_lock, flags);
2964 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965 spin_unlock_irqrestore(&dev->event_lock, flags);
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2972 struct drm_device *dev = crtc->dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2975 if (crtc->fb == NULL)
2978 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2980 wait_event(dev_priv->pending_flip_queue,
2981 !intel_crtc_has_pending_flip(crtc));
2983 mutex_lock(&dev->struct_mutex);
2984 intel_finish_fb(crtc->fb);
2985 mutex_unlock(&dev->struct_mutex);
2988 /* Program iCLKIP clock to the desired frequency */
2989 static void lpt_program_iclkip(struct drm_crtc *crtc)
2991 struct drm_device *dev = crtc->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2994 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2997 mutex_lock(&dev_priv->dpio_lock);
2999 /* It is necessary to ungate the pixclk gate prior to programming
3000 * the divisors, and gate it back when it is done.
3002 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3004 /* Disable SSCCTL */
3005 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3006 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3010 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3011 if (clock == 20000) {
3016 /* The iCLK virtual clock root frequency is in MHz,
3017 * but the adjusted_mode->crtc_clock in in KHz. To get the
3018 * divisors, it is necessary to divide one by another, so we
3019 * convert the virtual clock precision to KHz here for higher
3022 u32 iclk_virtual_root_freq = 172800 * 1000;
3023 u32 iclk_pi_range = 64;
3024 u32 desired_divisor, msb_divisor_value, pi_value;
3026 desired_divisor = (iclk_virtual_root_freq / clock);
3027 msb_divisor_value = desired_divisor / iclk_pi_range;
3028 pi_value = desired_divisor % iclk_pi_range;
3031 divsel = msb_divisor_value - 2;
3032 phaseinc = pi_value;
3035 /* This should not happen with any sane values */
3036 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3037 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3038 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3039 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3041 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3048 /* Program SSCDIVINTPHASE6 */
3049 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3050 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3051 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3052 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3053 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3054 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3055 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3056 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3058 /* Program SSCAUXDIV */
3059 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3060 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3061 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3062 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3064 /* Enable modulator and associated divider */
3065 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3066 temp &= ~SBI_SSCCTL_DISABLE;
3067 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3069 /* Wait for initialization time */
3072 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3074 mutex_unlock(&dev_priv->dpio_lock);
3077 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3078 enum pipe pch_transcoder)
3080 struct drm_device *dev = crtc->base.dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3084 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3085 I915_READ(HTOTAL(cpu_transcoder)));
3086 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3087 I915_READ(HBLANK(cpu_transcoder)));
3088 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3089 I915_READ(HSYNC(cpu_transcoder)));
3091 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3092 I915_READ(VTOTAL(cpu_transcoder)));
3093 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3094 I915_READ(VBLANK(cpu_transcoder)));
3095 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3096 I915_READ(VSYNC(cpu_transcoder)));
3097 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3098 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3101 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3103 struct drm_i915_private *dev_priv = dev->dev_private;
3106 temp = I915_READ(SOUTH_CHICKEN1);
3107 if (temp & FDI_BC_BIFURCATION_SELECT)
3110 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3111 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3113 temp |= FDI_BC_BIFURCATION_SELECT;
3114 DRM_DEBUG_KMS("enabling fdi C rx\n");
3115 I915_WRITE(SOUTH_CHICKEN1, temp);
3116 POSTING_READ(SOUTH_CHICKEN1);
3119 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3121 struct drm_device *dev = intel_crtc->base.dev;
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3124 switch (intel_crtc->pipe) {
3128 if (intel_crtc->config.fdi_lanes > 2)
3129 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3131 cpt_enable_fdi_bc_bifurcation(dev);
3135 cpt_enable_fdi_bc_bifurcation(dev);
3144 * Enable PCH resources required for PCH ports:
3146 * - FDI training & RX/TX
3147 * - update transcoder timings
3148 * - DP transcoding bits
3151 static void ironlake_pch_enable(struct drm_crtc *crtc)
3153 struct drm_device *dev = crtc->dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156 int pipe = intel_crtc->pipe;
3159 assert_pch_transcoder_disabled(dev_priv, pipe);
3161 if (IS_IVYBRIDGE(dev))
3162 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3164 /* Write the TU size bits before fdi link training, so that error
3165 * detection works. */
3166 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3167 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3169 /* For PCH output, training FDI link */
3170 dev_priv->display.fdi_link_train(crtc);
3172 /* We need to program the right clock selection before writing the pixel
3173 * mutliplier into the DPLL. */
3174 if (HAS_PCH_CPT(dev)) {
3177 temp = I915_READ(PCH_DPLL_SEL);
3178 temp |= TRANS_DPLL_ENABLE(pipe);
3179 sel = TRANS_DPLLB_SEL(pipe);
3180 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3184 I915_WRITE(PCH_DPLL_SEL, temp);
3187 /* XXX: pch pll's can be enabled any time before we enable the PCH
3188 * transcoder, and we actually should do this to not upset any PCH
3189 * transcoder that already use the clock when we share it.
3191 * Note that enable_shared_dpll tries to do the right thing, but
3192 * get_shared_dpll unconditionally resets the pll - we need that to have
3193 * the right LVDS enable sequence. */
3194 ironlake_enable_shared_dpll(intel_crtc);
3196 /* set transcoder timing, panel must allow it */
3197 assert_panel_unlocked(dev_priv, pipe);
3198 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3200 intel_fdi_normal_train(crtc);
3202 /* For PCH DP, enable TRANS_DP_CTL */
3203 if (HAS_PCH_CPT(dev) &&
3204 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3205 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3206 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3207 reg = TRANS_DP_CTL(pipe);
3208 temp = I915_READ(reg);
3209 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3210 TRANS_DP_SYNC_MASK |
3212 temp |= (TRANS_DP_OUTPUT_ENABLE |
3213 TRANS_DP_ENH_FRAMING);
3214 temp |= bpc << 9; /* same format but at 11:9 */
3216 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3217 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3218 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3219 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3221 switch (intel_trans_dp_port_sel(crtc)) {
3223 temp |= TRANS_DP_PORT_SEL_B;
3226 temp |= TRANS_DP_PORT_SEL_C;
3229 temp |= TRANS_DP_PORT_SEL_D;
3235 I915_WRITE(reg, temp);
3238 ironlake_enable_pch_transcoder(dev_priv, pipe);
3241 static void lpt_pch_enable(struct drm_crtc *crtc)
3243 struct drm_device *dev = crtc->dev;
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3246 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3248 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3250 lpt_program_iclkip(crtc);
3252 /* Set transcoder timing. */
3253 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3255 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3258 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3260 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3265 if (pll->refcount == 0) {
3266 WARN(1, "bad %s refcount\n", pll->name);
3270 if (--pll->refcount == 0) {
3272 WARN_ON(pll->active);
3275 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3278 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3280 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3281 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3282 enum intel_dpll_id i;
3285 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3286 crtc->base.base.id, pll->name);
3287 intel_put_shared_dpll(crtc);
3290 if (HAS_PCH_IBX(dev_priv->dev)) {
3291 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3292 i = (enum intel_dpll_id) crtc->pipe;
3293 pll = &dev_priv->shared_dplls[i];
3295 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3296 crtc->base.base.id, pll->name);
3301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3302 pll = &dev_priv->shared_dplls[i];
3304 /* Only want to check enabled timings first */
3305 if (pll->refcount == 0)
3308 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3309 sizeof(pll->hw_state)) == 0) {
3310 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3312 pll->name, pll->refcount, pll->active);
3318 /* Ok no matching timings, maybe there's a free one? */
3319 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3320 pll = &dev_priv->shared_dplls[i];
3321 if (pll->refcount == 0) {
3322 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3323 crtc->base.base.id, pll->name);
3331 crtc->config.shared_dpll = i;
3332 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3333 pipe_name(crtc->pipe));
3335 if (pll->active == 0) {
3336 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3337 sizeof(pll->hw_state));
3339 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3341 assert_shared_dpll_disabled(dev_priv, pll);
3343 pll->mode_set(dev_priv, pll);
3350 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 int dslreg = PIPEDSL(pipe);
3356 temp = I915_READ(dslreg);
3358 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3359 if (wait_for(I915_READ(dslreg) != temp, 5))
3360 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3364 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3366 struct drm_device *dev = crtc->base.dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 int pipe = crtc->pipe;
3370 if (crtc->config.pch_pfit.enabled) {
3371 /* Force use of hard-coded filter coefficients
3372 * as some pre-programmed values are broken,
3375 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3376 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3377 PF_PIPE_SEL_IVB(pipe));
3379 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3380 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3381 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3385 static void intel_enable_planes(struct drm_crtc *crtc)
3387 struct drm_device *dev = crtc->dev;
3388 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3389 struct intel_plane *intel_plane;
3391 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3392 if (intel_plane->pipe == pipe)
3393 intel_plane_restore(&intel_plane->base);
3396 static void intel_disable_planes(struct drm_crtc *crtc)
3398 struct drm_device *dev = crtc->dev;
3399 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3400 struct intel_plane *intel_plane;
3402 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3403 if (intel_plane->pipe == pipe)
3404 intel_plane_disable(&intel_plane->base);
3407 void hsw_enable_ips(struct intel_crtc *crtc)
3409 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3411 if (!crtc->config.ips_enabled)
3414 /* We can only enable IPS after we enable a plane and wait for a vblank.
3415 * We guarantee that the plane is enabled by calling intel_enable_ips
3416 * only after intel_enable_plane. And intel_enable_plane already waits
3417 * for a vblank, so all we need to do here is to enable the IPS bit. */
3418 assert_plane_enabled(dev_priv, crtc->plane);
3419 if (IS_BROADWELL(crtc->base.dev)) {
3420 mutex_lock(&dev_priv->rps.hw_lock);
3421 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3422 mutex_unlock(&dev_priv->rps.hw_lock);
3423 /* Quoting Art Runyan: "its not safe to expect any particular
3424 * value in IPS_CTL bit 31 after enabling IPS through the
3425 * mailbox." Therefore we need to defer waiting on the state
3427 * TODO: need to fix this for state checker
3430 I915_WRITE(IPS_CTL, IPS_ENABLE);
3431 /* The bit only becomes 1 in the next vblank, so this wait here
3432 * is essentially intel_wait_for_vblank. If we don't have this
3433 * and don't wait for vblanks until the end of crtc_enable, then
3434 * the HW state readout code will complain that the expected
3435 * IPS_CTL value is not the one we read. */
3436 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3437 DRM_ERROR("Timed out waiting for IPS enable\n");
3441 void hsw_disable_ips(struct intel_crtc *crtc)
3443 struct drm_device *dev = crtc->base.dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3446 if (!crtc->config.ips_enabled)
3449 assert_plane_enabled(dev_priv, crtc->plane);
3450 if (IS_BROADWELL(crtc->base.dev)) {
3451 mutex_lock(&dev_priv->rps.hw_lock);
3452 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3453 mutex_unlock(&dev_priv->rps.hw_lock);
3455 I915_WRITE(IPS_CTL, 0);
3456 POSTING_READ(IPS_CTL);
3458 /* We need to wait for a vblank before we can disable the plane. */
3459 intel_wait_for_vblank(dev, crtc->pipe);
3462 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3463 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3465 struct drm_device *dev = crtc->dev;
3466 struct drm_i915_private *dev_priv = dev->dev_private;
3467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3468 enum pipe pipe = intel_crtc->pipe;
3469 int palreg = PALETTE(pipe);
3471 bool reenable_ips = false;
3473 /* The clocks have to be on to load the palette. */
3474 if (!crtc->enabled || !intel_crtc->active)
3477 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3479 assert_dsi_pll_enabled(dev_priv);
3481 assert_pll_enabled(dev_priv, pipe);
3484 /* use legacy palette for Ironlake */
3485 if (HAS_PCH_SPLIT(dev))
3486 palreg = LGC_PALETTE(pipe);
3488 /* Workaround : Do not read or write the pipe palette/gamma data while
3489 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3491 if (intel_crtc->config.ips_enabled &&
3492 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3493 GAMMA_MODE_MODE_SPLIT)) {
3494 hsw_disable_ips(intel_crtc);
3495 reenable_ips = true;
3498 for (i = 0; i < 256; i++) {
3499 I915_WRITE(palreg + 4 * i,
3500 (intel_crtc->lut_r[i] << 16) |
3501 (intel_crtc->lut_g[i] << 8) |
3502 intel_crtc->lut_b[i]);
3506 hsw_enable_ips(intel_crtc);
3509 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3518 WARN_ON(!crtc->enabled);
3520 if (intel_crtc->active)
3523 intel_crtc->active = true;
3525 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3526 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->pre_enable)
3530 encoder->pre_enable(encoder);
3532 if (intel_crtc->config.has_pch_encoder) {
3533 /* Note: FDI PLL enabling _must_ be done before we enable the
3534 * cpu pipes, hence this is separate from all the other fdi/pch
3536 ironlake_fdi_pll_enable(intel_crtc);
3538 assert_fdi_tx_disabled(dev_priv, pipe);
3539 assert_fdi_rx_disabled(dev_priv, pipe);
3542 ironlake_pfit_enable(intel_crtc);
3545 * On ILK+ LUT must be loaded before the pipe is running but with
3548 intel_crtc_load_lut(crtc);
3550 intel_update_watermarks(crtc);
3551 intel_enable_pipe(dev_priv, pipe,
3552 intel_crtc->config.has_pch_encoder, false);
3553 intel_enable_primary_plane(dev_priv, plane, pipe);
3554 intel_enable_planes(crtc);
3555 intel_crtc_update_cursor(crtc, true);
3557 if (intel_crtc->config.has_pch_encoder)
3558 ironlake_pch_enable(crtc);
3560 mutex_lock(&dev->struct_mutex);
3561 intel_update_fbc(dev);
3562 mutex_unlock(&dev->struct_mutex);
3564 for_each_encoder_on_crtc(dev, crtc, encoder)
3565 encoder->enable(encoder);
3567 if (HAS_PCH_CPT(dev))
3568 cpt_verify_modeset(dev, intel_crtc->pipe);
3571 * There seems to be a race in PCH platform hw (at least on some
3572 * outputs) where an enabled pipe still completes any pageflip right
3573 * away (as if the pipe is off) instead of waiting for vblank. As soon
3574 * as the first vblank happend, everything works as expected. Hence just
3575 * wait for one vblank before returning to avoid strange things
3578 intel_wait_for_vblank(dev, intel_crtc->pipe);
3581 /* IPS only exists on ULT machines and is tied to pipe A. */
3582 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3584 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3587 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3589 struct drm_device *dev = crtc->dev;
3590 struct drm_i915_private *dev_priv = dev->dev_private;
3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592 int pipe = intel_crtc->pipe;
3593 int plane = intel_crtc->plane;
3595 intel_enable_primary_plane(dev_priv, plane, pipe);
3596 intel_enable_planes(crtc);
3597 intel_crtc_update_cursor(crtc, true);
3599 hsw_enable_ips(intel_crtc);
3601 mutex_lock(&dev->struct_mutex);
3602 intel_update_fbc(dev);
3603 mutex_unlock(&dev->struct_mutex);
3606 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611 int pipe = intel_crtc->pipe;
3612 int plane = intel_crtc->plane;
3614 intel_crtc_wait_for_pending_flips(crtc);
3615 drm_vblank_off(dev, pipe);
3617 /* FBC must be disabled before disabling the plane on HSW. */
3618 if (dev_priv->fbc.plane == plane)
3619 intel_disable_fbc(dev);
3621 hsw_disable_ips(intel_crtc);
3623 intel_crtc_update_cursor(crtc, false);
3624 intel_disable_planes(crtc);
3625 intel_disable_primary_plane(dev_priv, plane, pipe);
3629 * This implements the workaround described in the "notes" section of the mode
3630 * set sequence documentation. When going from no pipes or single pipe to
3631 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3632 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3634 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3636 struct drm_device *dev = crtc->base.dev;
3637 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3639 /* We want to get the other_active_crtc only if there's only 1 other
3641 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3642 if (!crtc_it->active || crtc_it == crtc)
3645 if (other_active_crtc)
3648 other_active_crtc = crtc_it;
3650 if (!other_active_crtc)
3653 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3654 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3657 static void haswell_crtc_enable(struct drm_crtc *crtc)
3659 struct drm_device *dev = crtc->dev;
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662 struct intel_encoder *encoder;
3663 int pipe = intel_crtc->pipe;
3665 WARN_ON(!crtc->enabled);
3667 if (intel_crtc->active)
3670 intel_crtc->active = true;
3672 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3673 if (intel_crtc->config.has_pch_encoder)
3674 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3676 if (intel_crtc->config.has_pch_encoder)
3677 dev_priv->display.fdi_link_train(crtc);
3679 for_each_encoder_on_crtc(dev, crtc, encoder)
3680 if (encoder->pre_enable)
3681 encoder->pre_enable(encoder);
3683 intel_ddi_enable_pipe_clock(intel_crtc);
3685 ironlake_pfit_enable(intel_crtc);
3688 * On ILK+ LUT must be loaded before the pipe is running but with
3691 intel_crtc_load_lut(crtc);
3693 intel_ddi_set_pipe_settings(crtc);
3694 intel_ddi_enable_transcoder_func(crtc);
3696 intel_update_watermarks(crtc);
3697 intel_enable_pipe(dev_priv, pipe,
3698 intel_crtc->config.has_pch_encoder, false);
3700 if (intel_crtc->config.has_pch_encoder)
3701 lpt_pch_enable(crtc);
3703 for_each_encoder_on_crtc(dev, crtc, encoder) {
3704 encoder->enable(encoder);
3705 intel_opregion_notify_encoder(encoder, true);
3708 /* If we change the relative order between pipe/planes enabling, we need
3709 * to change the workaround. */
3710 haswell_mode_set_planes_workaround(intel_crtc);
3711 haswell_crtc_enable_planes(crtc);
3714 * There seems to be a race in PCH platform hw (at least on some
3715 * outputs) where an enabled pipe still completes any pageflip right
3716 * away (as if the pipe is off) instead of waiting for vblank. As soon
3717 * as the first vblank happend, everything works as expected. Hence just
3718 * wait for one vblank before returning to avoid strange things
3721 intel_wait_for_vblank(dev, intel_crtc->pipe);
3724 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3726 struct drm_device *dev = crtc->base.dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 int pipe = crtc->pipe;
3730 /* To avoid upsetting the power well on haswell only disable the pfit if
3731 * it's in use. The hw state code will make sure we get this right. */
3732 if (crtc->config.pch_pfit.enabled) {
3733 I915_WRITE(PF_CTL(pipe), 0);
3734 I915_WRITE(PF_WIN_POS(pipe), 0);
3735 I915_WRITE(PF_WIN_SZ(pipe), 0);
3739 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3741 struct drm_device *dev = crtc->dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744 struct intel_encoder *encoder;
3745 int pipe = intel_crtc->pipe;
3746 int plane = intel_crtc->plane;
3750 if (!intel_crtc->active)
3753 for_each_encoder_on_crtc(dev, crtc, encoder)
3754 encoder->disable(encoder);
3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
3759 if (dev_priv->fbc.plane == plane)
3760 intel_disable_fbc(dev);
3762 intel_crtc_update_cursor(crtc, false);
3763 intel_disable_planes(crtc);
3764 intel_disable_primary_plane(dev_priv, plane, pipe);
3766 if (intel_crtc->config.has_pch_encoder)
3767 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3769 intel_disable_pipe(dev_priv, pipe);
3771 ironlake_pfit_disable(intel_crtc);
3773 for_each_encoder_on_crtc(dev, crtc, encoder)
3774 if (encoder->post_disable)
3775 encoder->post_disable(encoder);
3777 if (intel_crtc->config.has_pch_encoder) {
3778 ironlake_fdi_disable(crtc);
3780 ironlake_disable_pch_transcoder(dev_priv, pipe);
3781 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3783 if (HAS_PCH_CPT(dev)) {
3784 /* disable TRANS_DP_CTL */
3785 reg = TRANS_DP_CTL(pipe);
3786 temp = I915_READ(reg);
3787 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3788 TRANS_DP_PORT_SEL_MASK);
3789 temp |= TRANS_DP_PORT_SEL_NONE;
3790 I915_WRITE(reg, temp);
3792 /* disable DPLL_SEL */
3793 temp = I915_READ(PCH_DPLL_SEL);
3794 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3795 I915_WRITE(PCH_DPLL_SEL, temp);
3798 /* disable PCH DPLL */
3799 intel_disable_shared_dpll(intel_crtc);
3801 ironlake_fdi_pll_disable(intel_crtc);
3804 intel_crtc->active = false;
3805 intel_update_watermarks(crtc);
3807 mutex_lock(&dev->struct_mutex);
3808 intel_update_fbc(dev);
3809 mutex_unlock(&dev->struct_mutex);
3812 static void haswell_crtc_disable(struct drm_crtc *crtc)
3814 struct drm_device *dev = crtc->dev;
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3817 struct intel_encoder *encoder;
3818 int pipe = intel_crtc->pipe;
3819 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3821 if (!intel_crtc->active)
3824 haswell_crtc_disable_planes(crtc);
3826 for_each_encoder_on_crtc(dev, crtc, encoder) {
3827 intel_opregion_notify_encoder(encoder, false);
3828 encoder->disable(encoder);
3831 if (intel_crtc->config.has_pch_encoder)
3832 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3833 intel_disable_pipe(dev_priv, pipe);
3835 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3837 ironlake_pfit_disable(intel_crtc);
3839 intel_ddi_disable_pipe_clock(intel_crtc);
3841 for_each_encoder_on_crtc(dev, crtc, encoder)
3842 if (encoder->post_disable)
3843 encoder->post_disable(encoder);
3845 if (intel_crtc->config.has_pch_encoder) {
3846 lpt_disable_pch_transcoder(dev_priv);
3847 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3848 intel_ddi_fdi_disable(crtc);
3851 intel_crtc->active = false;
3852 intel_update_watermarks(crtc);
3854 mutex_lock(&dev->struct_mutex);
3855 intel_update_fbc(dev);
3856 mutex_unlock(&dev->struct_mutex);
3859 static void ironlake_crtc_off(struct drm_crtc *crtc)
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 intel_put_shared_dpll(intel_crtc);
3865 static void haswell_crtc_off(struct drm_crtc *crtc)
3867 intel_ddi_put_crtc_pll(crtc);
3870 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3872 if (!enable && intel_crtc->overlay) {
3873 struct drm_device *dev = intel_crtc->base.dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3876 mutex_lock(&dev->struct_mutex);
3877 dev_priv->mm.interruptible = false;
3878 (void) intel_overlay_switch_off(intel_crtc->overlay);
3879 dev_priv->mm.interruptible = true;
3880 mutex_unlock(&dev->struct_mutex);
3883 /* Let userspace switch the overlay on again. In most cases userspace
3884 * has to recompute where to put it anyway.
3889 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3890 * cursor plane briefly if not already running after enabling the display
3892 * This workaround avoids occasional blank screens when self refresh is
3896 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3898 u32 cntl = I915_READ(CURCNTR(pipe));
3900 if ((cntl & CURSOR_MODE) == 0) {
3901 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3903 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3904 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3905 intel_wait_for_vblank(dev_priv->dev, pipe);
3906 I915_WRITE(CURCNTR(pipe), cntl);
3907 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3908 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3912 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3914 struct drm_device *dev = crtc->base.dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916 struct intel_crtc_config *pipe_config = &crtc->config;
3918 if (!crtc->config.gmch_pfit.control)
3922 * The panel fitter should only be adjusted whilst the pipe is disabled,
3923 * according to register description and PRM.
3925 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3926 assert_pipe_disabled(dev_priv, crtc->pipe);
3928 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3929 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3931 /* Border color in case we don't scale up to the full screen. Black by
3932 * default, change to something else for debugging. */
3933 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3936 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3938 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3940 /* Obtain SKU information */
3941 mutex_lock(&dev_priv->dpio_lock);
3942 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3943 CCK_FUSE_HPLL_FREQ_MASK;
3944 mutex_unlock(&dev_priv->dpio_lock);
3946 return vco_freq[hpll_freq];
3949 /* Adjust CDclk dividers to allow high res or save power if possible */
3950 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3952 struct drm_i915_private *dev_priv = dev->dev_private;
3955 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3957 else if (cdclk == 266)
3962 mutex_lock(&dev_priv->rps.hw_lock);
3963 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3964 val &= ~DSPFREQGUAR_MASK;
3965 val |= (cmd << DSPFREQGUAR_SHIFT);
3966 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3967 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3968 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3970 DRM_ERROR("timed out waiting for CDclk change\n");
3972 mutex_unlock(&dev_priv->rps.hw_lock);
3977 vco = valleyview_get_vco(dev_priv);
3978 divider = ((vco << 1) / cdclk) - 1;
3980 mutex_lock(&dev_priv->dpio_lock);
3981 /* adjust cdclk divider */
3982 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3985 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3986 mutex_unlock(&dev_priv->dpio_lock);
3989 mutex_lock(&dev_priv->dpio_lock);
3990 /* adjust self-refresh exit latency value */
3991 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
3995 * For high bandwidth configs, we set a higher latency in the bunit
3996 * so that the core display fetch happens in time to avoid underruns.
3999 val |= 4500 / 250; /* 4.5 usec */
4001 val |= 3000 / 250; /* 3.0 usec */
4002 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4003 mutex_unlock(&dev_priv->dpio_lock);
4005 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4006 intel_i2c_reset(dev);
4009 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4014 vco = valleyview_get_vco(dev_priv);
4016 mutex_lock(&dev_priv->dpio_lock);
4017 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4018 mutex_unlock(&dev_priv->dpio_lock);
4022 cur_cdclk = (vco << 1) / (divider + 1);
4027 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4032 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4035 * Really only a few cases to deal with, as only 4 CDclks are supported:
4040 * So we check to see whether we're above 90% of the lower bin and
4043 if (max_pixclk > 288000) {
4045 } else if (max_pixclk > 240000) {
4049 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4052 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4053 unsigned modeset_pipes,
4054 struct intel_crtc_config *pipe_config)
4056 struct drm_device *dev = dev_priv->dev;
4057 struct intel_crtc *intel_crtc;
4060 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4062 if (modeset_pipes & (1 << intel_crtc->pipe))
4063 max_pixclk = max(max_pixclk,
4064 pipe_config->adjusted_mode.crtc_clock);
4065 else if (intel_crtc->base.enabled)
4066 max_pixclk = max(max_pixclk,
4067 intel_crtc->config.adjusted_mode.crtc_clock);
4073 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4074 unsigned *prepare_pipes,
4075 unsigned modeset_pipes,
4076 struct intel_crtc_config *pipe_config)
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 struct intel_crtc *intel_crtc;
4080 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4082 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4084 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4087 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4089 if (intel_crtc->base.enabled)
4090 *prepare_pipes |= (1 << intel_crtc->pipe);
4093 static void valleyview_modeset_global_resources(struct drm_device *dev)
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4097 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4098 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4100 if (req_cdclk != cur_cdclk)
4101 valleyview_set_cdclk(dev, req_cdclk);
4104 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109 struct intel_encoder *encoder;
4110 int pipe = intel_crtc->pipe;
4111 int plane = intel_crtc->plane;
4114 WARN_ON(!crtc->enabled);
4116 if (intel_crtc->active)
4119 intel_crtc->active = true;
4121 for_each_encoder_on_crtc(dev, crtc, encoder)
4122 if (encoder->pre_pll_enable)
4123 encoder->pre_pll_enable(encoder);
4125 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4128 vlv_enable_pll(intel_crtc);
4130 for_each_encoder_on_crtc(dev, crtc, encoder)
4131 if (encoder->pre_enable)
4132 encoder->pre_enable(encoder);
4134 i9xx_pfit_enable(intel_crtc);
4136 intel_crtc_load_lut(crtc);
4138 intel_update_watermarks(crtc);
4139 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4140 intel_enable_primary_plane(dev_priv, plane, pipe);
4141 intel_enable_planes(crtc);
4142 intel_crtc_update_cursor(crtc, true);
4144 intel_update_fbc(dev);
4146 for_each_encoder_on_crtc(dev, crtc, encoder)
4147 encoder->enable(encoder);
4150 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155 struct intel_encoder *encoder;
4156 int pipe = intel_crtc->pipe;
4157 int plane = intel_crtc->plane;
4159 WARN_ON(!crtc->enabled);
4161 if (intel_crtc->active)
4164 intel_crtc->active = true;
4166 for_each_encoder_on_crtc(dev, crtc, encoder)
4167 if (encoder->pre_enable)
4168 encoder->pre_enable(encoder);
4170 i9xx_enable_pll(intel_crtc);
4172 i9xx_pfit_enable(intel_crtc);
4174 intel_crtc_load_lut(crtc);
4176 intel_update_watermarks(crtc);
4177 intel_enable_pipe(dev_priv, pipe, false, false);
4178 intel_enable_primary_plane(dev_priv, plane, pipe);
4179 intel_enable_planes(crtc);
4180 /* The fixup needs to happen before cursor is enabled */
4182 g4x_fixup_plane(dev_priv, pipe);
4183 intel_crtc_update_cursor(crtc, true);
4185 /* Give the overlay scaler a chance to enable if it's on this pipe */
4186 intel_crtc_dpms_overlay(intel_crtc, true);
4188 intel_update_fbc(dev);
4190 for_each_encoder_on_crtc(dev, crtc, encoder)
4191 encoder->enable(encoder);
4194 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4196 struct drm_device *dev = crtc->base.dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4199 if (!crtc->config.gmch_pfit.control)
4202 assert_pipe_disabled(dev_priv, crtc->pipe);
4204 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4205 I915_READ(PFIT_CONTROL));
4206 I915_WRITE(PFIT_CONTROL, 0);
4209 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4211 struct drm_device *dev = crtc->dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214 struct intel_encoder *encoder;
4215 int pipe = intel_crtc->pipe;
4216 int plane = intel_crtc->plane;
4218 if (!intel_crtc->active)
4221 for_each_encoder_on_crtc(dev, crtc, encoder)
4222 encoder->disable(encoder);
4224 /* Give the overlay scaler a chance to disable if it's on this pipe */
4225 intel_crtc_wait_for_pending_flips(crtc);
4226 drm_vblank_off(dev, pipe);
4228 if (dev_priv->fbc.plane == plane)
4229 intel_disable_fbc(dev);
4231 intel_crtc_dpms_overlay(intel_crtc, false);
4232 intel_crtc_update_cursor(crtc, false);
4233 intel_disable_planes(crtc);
4234 intel_disable_primary_plane(dev_priv, plane, pipe);
4236 intel_disable_pipe(dev_priv, pipe);
4238 i9xx_pfit_disable(intel_crtc);
4240 for_each_encoder_on_crtc(dev, crtc, encoder)
4241 if (encoder->post_disable)
4242 encoder->post_disable(encoder);
4244 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4245 vlv_disable_pll(dev_priv, pipe);
4246 else if (!IS_VALLEYVIEW(dev))
4247 i9xx_disable_pll(dev_priv, pipe);
4249 intel_crtc->active = false;
4250 intel_update_watermarks(crtc);
4252 intel_update_fbc(dev);
4255 static void i9xx_crtc_off(struct drm_crtc *crtc)
4259 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_master_private *master_priv;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 int pipe = intel_crtc->pipe;
4267 if (!dev->primary->master)
4270 master_priv = dev->primary->master->driver_priv;
4271 if (!master_priv->sarea_priv)
4276 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4277 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4280 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4281 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4284 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4290 * Sets the power management mode of the pipe and plane.
4292 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_encoder *intel_encoder;
4297 bool enable = false;
4299 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4300 enable |= intel_encoder->connectors_active;
4303 dev_priv->display.crtc_enable(crtc);
4305 dev_priv->display.crtc_disable(crtc);
4307 intel_crtc_update_sarea(crtc, enable);
4310 static void intel_crtc_disable(struct drm_crtc *crtc)
4312 struct drm_device *dev = crtc->dev;
4313 struct drm_connector *connector;
4314 struct drm_i915_private *dev_priv = dev->dev_private;
4315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 /* crtc should still be enabled when we disable it. */
4318 WARN_ON(!crtc->enabled);
4320 dev_priv->display.crtc_disable(crtc);
4321 intel_crtc->eld_vld = false;
4322 intel_crtc_update_sarea(crtc, false);
4323 dev_priv->display.off(crtc);
4325 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4326 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4327 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4330 mutex_lock(&dev->struct_mutex);
4331 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4332 mutex_unlock(&dev->struct_mutex);
4336 /* Update computed state. */
4337 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4338 if (!connector->encoder || !connector->encoder->crtc)
4341 if (connector->encoder->crtc != crtc)
4344 connector->dpms = DRM_MODE_DPMS_OFF;
4345 to_intel_encoder(connector->encoder)->connectors_active = false;
4349 void intel_encoder_destroy(struct drm_encoder *encoder)
4351 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4353 drm_encoder_cleanup(encoder);
4354 kfree(intel_encoder);
4357 /* Simple dpms helper for encoders with just one connector, no cloning and only
4358 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4359 * state of the entire output pipe. */
4360 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4362 if (mode == DRM_MODE_DPMS_ON) {
4363 encoder->connectors_active = true;
4365 intel_crtc_update_dpms(encoder->base.crtc);
4367 encoder->connectors_active = false;
4369 intel_crtc_update_dpms(encoder->base.crtc);
4373 /* Cross check the actual hw state with our own modeset state tracking (and it's
4374 * internal consistency). */
4375 static void intel_connector_check_state(struct intel_connector *connector)
4377 if (connector->get_hw_state(connector)) {
4378 struct intel_encoder *encoder = connector->encoder;
4379 struct drm_crtc *crtc;
4380 bool encoder_enabled;
4383 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4384 connector->base.base.id,
4385 drm_get_connector_name(&connector->base));
4387 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4388 "wrong connector dpms state\n");
4389 WARN(connector->base.encoder != &encoder->base,
4390 "active connector not linked to encoder\n");
4391 WARN(!encoder->connectors_active,
4392 "encoder->connectors_active not set\n");
4394 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4395 WARN(!encoder_enabled, "encoder not enabled\n");
4396 if (WARN_ON(!encoder->base.crtc))
4399 crtc = encoder->base.crtc;
4401 WARN(!crtc->enabled, "crtc not enabled\n");
4402 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4403 WARN(pipe != to_intel_crtc(crtc)->pipe,
4404 "encoder active on the wrong pipe\n");
4408 /* Even simpler default implementation, if there's really no special case to
4410 void intel_connector_dpms(struct drm_connector *connector, int mode)
4412 /* All the simple cases only support two dpms states. */
4413 if (mode != DRM_MODE_DPMS_ON)
4414 mode = DRM_MODE_DPMS_OFF;
4416 if (mode == connector->dpms)
4419 connector->dpms = mode;
4421 /* Only need to change hw state when actually enabled */
4422 if (connector->encoder)
4423 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4425 intel_modeset_check_state(connector->dev);
4428 /* Simple connector->get_hw_state implementation for encoders that support only
4429 * one connector and no cloning and hence the encoder state determines the state
4430 * of the connector. */
4431 bool intel_connector_get_hw_state(struct intel_connector *connector)
4434 struct intel_encoder *encoder = connector->encoder;
4436 return encoder->get_hw_state(encoder, &pipe);
4439 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4440 struct intel_crtc_config *pipe_config)
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 struct intel_crtc *pipe_B_crtc =
4444 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4446 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4447 pipe_name(pipe), pipe_config->fdi_lanes);
4448 if (pipe_config->fdi_lanes > 4) {
4449 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4450 pipe_name(pipe), pipe_config->fdi_lanes);
4454 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4455 if (pipe_config->fdi_lanes > 2) {
4456 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4457 pipe_config->fdi_lanes);
4464 if (INTEL_INFO(dev)->num_pipes == 2)
4467 /* Ivybridge 3 pipe is really complicated */
4472 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4473 pipe_config->fdi_lanes > 2) {
4474 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4475 pipe_name(pipe), pipe_config->fdi_lanes);
4480 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4481 pipe_B_crtc->config.fdi_lanes <= 2) {
4482 if (pipe_config->fdi_lanes > 2) {
4483 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4484 pipe_name(pipe), pipe_config->fdi_lanes);
4488 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4498 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4499 struct intel_crtc_config *pipe_config)
4501 struct drm_device *dev = intel_crtc->base.dev;
4502 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4503 int lane, link_bw, fdi_dotclock;
4504 bool setup_ok, needs_recompute = false;
4507 /* FDI is a binary signal running at ~2.7GHz, encoding
4508 * each output octet as 10 bits. The actual frequency
4509 * is stored as a divider into a 100MHz clock, and the
4510 * mode pixel clock is stored in units of 1KHz.
4511 * Hence the bw of each lane in terms of the mode signal
4514 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4516 fdi_dotclock = adjusted_mode->crtc_clock;
4518 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4519 pipe_config->pipe_bpp);
4521 pipe_config->fdi_lanes = lane;
4523 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4524 link_bw, &pipe_config->fdi_m_n);
4526 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4527 intel_crtc->pipe, pipe_config);
4528 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4529 pipe_config->pipe_bpp -= 2*3;
4530 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4531 pipe_config->pipe_bpp);
4532 needs_recompute = true;
4533 pipe_config->bw_constrained = true;
4538 if (needs_recompute)
4541 return setup_ok ? 0 : -EINVAL;
4544 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4545 struct intel_crtc_config *pipe_config)
4547 pipe_config->ips_enabled = i915_enable_ips &&
4548 hsw_crtc_supports_ips(crtc) &&
4549 pipe_config->pipe_bpp <= 24;
4552 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4553 struct intel_crtc_config *pipe_config)
4555 struct drm_device *dev = crtc->base.dev;
4556 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4558 /* FIXME should check pixel clock limits on all platforms */
4559 if (INTEL_INFO(dev)->gen < 4) {
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4562 dev_priv->display.get_display_clock_speed(dev);
4565 * Enable pixel doubling when the dot clock
4566 * is > 90% of the (display) core speed.
4568 * GDG double wide on either pipe,
4569 * otherwise pipe A only.
4571 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4572 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4574 pipe_config->double_wide = true;
4577 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4582 * Pipe horizontal size must be even in:
4584 * - LVDS dual channel mode
4585 * - Double wide pipe
4587 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4588 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4589 pipe_config->pipe_src_w &= ~1;
4591 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4592 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4594 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4595 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4598 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4599 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4600 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4601 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4603 pipe_config->pipe_bpp = 8*3;
4607 hsw_compute_ips_config(crtc, pipe_config);
4609 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4610 * clock survives for now. */
4611 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4612 pipe_config->shared_dpll = crtc->config.shared_dpll;
4614 if (pipe_config->has_pch_encoder)
4615 return ironlake_fdi_compute_config(crtc, pipe_config);
4620 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4622 return 400000; /* FIXME */
4625 static int i945_get_display_clock_speed(struct drm_device *dev)
4630 static int i915_get_display_clock_speed(struct drm_device *dev)
4635 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4640 static int pnv_get_display_clock_speed(struct drm_device *dev)
4644 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4646 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4647 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4649 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4651 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4653 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4656 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4657 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4659 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4664 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4668 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4670 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4673 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4674 case GC_DISPLAY_CLOCK_333_MHZ:
4677 case GC_DISPLAY_CLOCK_190_200_MHZ:
4683 static int i865_get_display_clock_speed(struct drm_device *dev)
4688 static int i855_get_display_clock_speed(struct drm_device *dev)
4691 /* Assume that the hardware is in the high speed state. This
4692 * should be the default.
4694 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4695 case GC_CLOCK_133_200:
4696 case GC_CLOCK_100_200:
4698 case GC_CLOCK_166_250:
4700 case GC_CLOCK_100_133:
4704 /* Shouldn't happen */
4708 static int i830_get_display_clock_speed(struct drm_device *dev)
4714 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4716 while (*num > DATA_LINK_M_N_MASK ||
4717 *den > DATA_LINK_M_N_MASK) {
4723 static void compute_m_n(unsigned int m, unsigned int n,
4724 uint32_t *ret_m, uint32_t *ret_n)
4726 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4727 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4728 intel_reduce_m_n_ratio(ret_m, ret_n);
4732 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4733 int pixel_clock, int link_clock,
4734 struct intel_link_m_n *m_n)
4738 compute_m_n(bits_per_pixel * pixel_clock,
4739 link_clock * nlanes * 8,
4740 &m_n->gmch_m, &m_n->gmch_n);
4742 compute_m_n(pixel_clock, link_clock,
4743 &m_n->link_m, &m_n->link_n);
4746 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4748 if (i915_panel_use_ssc >= 0)
4749 return i915_panel_use_ssc != 0;
4750 return dev_priv->vbt.lvds_use_ssc
4751 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4754 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4756 struct drm_device *dev = crtc->dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4760 if (IS_VALLEYVIEW(dev)) {
4762 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4763 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4764 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4765 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4767 } else if (!IS_GEN2(dev)) {
4776 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4778 return (1 << dpll->n) << 16 | dpll->m2;
4781 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4783 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4786 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4787 intel_clock_t *reduced_clock)
4789 struct drm_device *dev = crtc->base.dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 int pipe = crtc->pipe;
4794 if (IS_PINEVIEW(dev)) {
4795 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4797 fp2 = pnv_dpll_compute_fp(reduced_clock);
4799 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4801 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4804 I915_WRITE(FP0(pipe), fp);
4805 crtc->config.dpll_hw_state.fp0 = fp;
4807 crtc->lowfreq_avail = false;
4808 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4809 reduced_clock && i915_powersave) {
4810 I915_WRITE(FP1(pipe), fp2);
4811 crtc->config.dpll_hw_state.fp1 = fp2;
4812 crtc->lowfreq_avail = true;
4814 I915_WRITE(FP1(pipe), fp);
4815 crtc->config.dpll_hw_state.fp1 = fp;
4819 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4825 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4826 * and set it to a reasonable value instead.
4828 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4829 reg_val &= 0xffffff00;
4830 reg_val |= 0x00000030;
4831 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4833 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4834 reg_val &= 0x8cffffff;
4835 reg_val = 0x8c000000;
4836 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4838 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4839 reg_val &= 0xffffff00;
4840 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4842 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4843 reg_val &= 0x00ffffff;
4844 reg_val |= 0xb0000000;
4845 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4848 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4849 struct intel_link_m_n *m_n)
4851 struct drm_device *dev = crtc->base.dev;
4852 struct drm_i915_private *dev_priv = dev->dev_private;
4853 int pipe = crtc->pipe;
4855 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4856 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4857 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4858 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4861 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4862 struct intel_link_m_n *m_n)
4864 struct drm_device *dev = crtc->base.dev;
4865 struct drm_i915_private *dev_priv = dev->dev_private;
4866 int pipe = crtc->pipe;
4867 enum transcoder transcoder = crtc->config.cpu_transcoder;
4869 if (INTEL_INFO(dev)->gen >= 5) {
4870 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4871 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4872 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4873 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4875 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4876 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4877 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4878 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4882 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4884 if (crtc->config.has_pch_encoder)
4885 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4887 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4890 static void vlv_update_pll(struct intel_crtc *crtc)
4892 struct drm_device *dev = crtc->base.dev;
4893 struct drm_i915_private *dev_priv = dev->dev_private;
4894 int pipe = crtc->pipe;
4896 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4897 u32 coreclk, reg_val, dpll_md;
4899 mutex_lock(&dev_priv->dpio_lock);
4901 bestn = crtc->config.dpll.n;
4902 bestm1 = crtc->config.dpll.m1;
4903 bestm2 = crtc->config.dpll.m2;
4904 bestp1 = crtc->config.dpll.p1;
4905 bestp2 = crtc->config.dpll.p2;
4907 /* See eDP HDMI DPIO driver vbios notes doc */
4909 /* PLL B needs special handling */
4911 vlv_pllb_recal_opamp(dev_priv, pipe);
4913 /* Set up Tx target for periodic Rcomp update */
4914 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4916 /* Disable target IRef on PLL */
4917 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4918 reg_val &= 0x00ffffff;
4919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4921 /* Disable fast lock */
4922 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4924 /* Set idtafcrecal before PLL is enabled */
4925 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4926 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4927 mdiv |= ((bestn << DPIO_N_SHIFT));
4928 mdiv |= (1 << DPIO_K_SHIFT);
4931 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4932 * but we don't support that).
4933 * Note: don't use the DAC post divider as it seems unstable.
4935 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4936 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4938 mdiv |= DPIO_ENABLE_CALIBRATION;
4939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4941 /* Set HBR and RBR LPF coefficients */
4942 if (crtc->config.port_clock == 162000 ||
4943 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4944 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4951 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4952 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4953 /* Use SSC source */
4955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4960 } else { /* HDMI or VGA */
4961 /* Use bend source */
4963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4970 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4971 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4972 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4973 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4974 coreclk |= 0x01000000;
4975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4977 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4979 /* Enable DPIO clock input */
4980 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4981 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4982 /* We should never disable this, set it here for state tracking */
4984 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4985 dpll |= DPLL_VCO_ENABLE;
4986 crtc->config.dpll_hw_state.dpll = dpll;
4988 dpll_md = (crtc->config.pixel_multiplier - 1)
4989 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4990 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4992 if (crtc->config.has_dp_encoder)
4993 intel_dp_set_m_n(crtc);
4995 mutex_unlock(&dev_priv->dpio_lock);
4998 static void i9xx_update_pll(struct intel_crtc *crtc,
4999 intel_clock_t *reduced_clock,
5002 struct drm_device *dev = crtc->base.dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5006 struct dpll *clock = &crtc->config.dpll;
5008 i9xx_update_pll_dividers(crtc, reduced_clock);
5010 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5011 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5013 dpll = DPLL_VGA_MODE_DIS;
5015 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5016 dpll |= DPLLB_MODE_LVDS;
5018 dpll |= DPLLB_MODE_DAC_SERIAL;
5020 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5021 dpll |= (crtc->config.pixel_multiplier - 1)
5022 << SDVO_MULTIPLIER_SHIFT_HIRES;
5026 dpll |= DPLL_SDVO_HIGH_SPEED;
5028 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5029 dpll |= DPLL_SDVO_HIGH_SPEED;
5031 /* compute bitmask from p1 value */
5032 if (IS_PINEVIEW(dev))
5033 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5036 if (IS_G4X(dev) && reduced_clock)
5037 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5039 switch (clock->p2) {
5041 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5044 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5047 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5050 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5053 if (INTEL_INFO(dev)->gen >= 4)
5054 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5056 if (crtc->config.sdvo_tv_clock)
5057 dpll |= PLL_REF_INPUT_TVCLKINBC;
5058 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5059 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5060 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5062 dpll |= PLL_REF_INPUT_DREFCLK;
5064 dpll |= DPLL_VCO_ENABLE;
5065 crtc->config.dpll_hw_state.dpll = dpll;
5067 if (INTEL_INFO(dev)->gen >= 4) {
5068 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5069 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5070 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5073 if (crtc->config.has_dp_encoder)
5074 intel_dp_set_m_n(crtc);
5077 static void i8xx_update_pll(struct intel_crtc *crtc,
5078 intel_clock_t *reduced_clock,
5081 struct drm_device *dev = crtc->base.dev;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
5084 struct dpll *clock = &crtc->config.dpll;
5086 i9xx_update_pll_dividers(crtc, reduced_clock);
5088 dpll = DPLL_VGA_MODE_DIS;
5090 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5091 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5094 dpll |= PLL_P1_DIVIDE_BY_TWO;
5096 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5098 dpll |= PLL_P2_DIVIDE_BY_4;
5101 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5102 dpll |= DPLL_DVO_2X_MODE;
5104 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5105 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5106 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5108 dpll |= PLL_REF_INPUT_DREFCLK;
5110 dpll |= DPLL_VCO_ENABLE;
5111 crtc->config.dpll_hw_state.dpll = dpll;
5114 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5116 struct drm_device *dev = intel_crtc->base.dev;
5117 struct drm_i915_private *dev_priv = dev->dev_private;
5118 enum pipe pipe = intel_crtc->pipe;
5119 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5120 struct drm_display_mode *adjusted_mode =
5121 &intel_crtc->config.adjusted_mode;
5122 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5124 /* We need to be careful not to changed the adjusted mode, for otherwise
5125 * the hw state checker will get angry at the mismatch. */
5126 crtc_vtotal = adjusted_mode->crtc_vtotal;
5127 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5129 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5130 /* the chip adds 2 halflines automatically */
5132 crtc_vblank_end -= 1;
5133 vsyncshift = adjusted_mode->crtc_hsync_start
5134 - adjusted_mode->crtc_htotal / 2;
5139 if (INTEL_INFO(dev)->gen > 3)
5140 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5142 I915_WRITE(HTOTAL(cpu_transcoder),
5143 (adjusted_mode->crtc_hdisplay - 1) |
5144 ((adjusted_mode->crtc_htotal - 1) << 16));
5145 I915_WRITE(HBLANK(cpu_transcoder),
5146 (adjusted_mode->crtc_hblank_start - 1) |
5147 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5148 I915_WRITE(HSYNC(cpu_transcoder),
5149 (adjusted_mode->crtc_hsync_start - 1) |
5150 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5152 I915_WRITE(VTOTAL(cpu_transcoder),
5153 (adjusted_mode->crtc_vdisplay - 1) |
5154 ((crtc_vtotal - 1) << 16));
5155 I915_WRITE(VBLANK(cpu_transcoder),
5156 (adjusted_mode->crtc_vblank_start - 1) |
5157 ((crtc_vblank_end - 1) << 16));
5158 I915_WRITE(VSYNC(cpu_transcoder),
5159 (adjusted_mode->crtc_vsync_start - 1) |
5160 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5162 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5163 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5164 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5166 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5167 (pipe == PIPE_B || pipe == PIPE_C))
5168 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5170 /* pipesrc controls the size that is scaled from, which should
5171 * always be the user's requested size.
5173 I915_WRITE(PIPESRC(pipe),
5174 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5175 (intel_crtc->config.pipe_src_h - 1));
5178 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5179 struct intel_crtc_config *pipe_config)
5181 struct drm_device *dev = crtc->base.dev;
5182 struct drm_i915_private *dev_priv = dev->dev_private;
5183 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5186 tmp = I915_READ(HTOTAL(cpu_transcoder));
5187 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5188 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5189 tmp = I915_READ(HBLANK(cpu_transcoder));
5190 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5191 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5192 tmp = I915_READ(HSYNC(cpu_transcoder));
5193 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5194 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5196 tmp = I915_READ(VTOTAL(cpu_transcoder));
5197 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5198 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5199 tmp = I915_READ(VBLANK(cpu_transcoder));
5200 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5201 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5202 tmp = I915_READ(VSYNC(cpu_transcoder));
5203 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5204 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5206 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5207 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5208 pipe_config->adjusted_mode.crtc_vtotal += 1;
5209 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5212 tmp = I915_READ(PIPESRC(crtc->pipe));
5213 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5214 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5216 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5217 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5220 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5221 struct intel_crtc_config *pipe_config)
5223 struct drm_crtc *crtc = &intel_crtc->base;
5225 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5226 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5227 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5228 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5230 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5231 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5232 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5233 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5235 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5237 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5238 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5241 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5243 struct drm_device *dev = intel_crtc->base.dev;
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5249 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5250 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5251 pipeconf |= PIPECONF_ENABLE;
5253 if (intel_crtc->config.double_wide)
5254 pipeconf |= PIPECONF_DOUBLE_WIDE;
5256 /* only g4x and later have fancy bpc/dither controls */
5257 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5258 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5259 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5260 pipeconf |= PIPECONF_DITHER_EN |
5261 PIPECONF_DITHER_TYPE_SP;
5263 switch (intel_crtc->config.pipe_bpp) {
5265 pipeconf |= PIPECONF_6BPC;
5268 pipeconf |= PIPECONF_8BPC;
5271 pipeconf |= PIPECONF_10BPC;
5274 /* Case prevented by intel_choose_pipe_bpp_dither. */
5279 if (HAS_PIPE_CXSR(dev)) {
5280 if (intel_crtc->lowfreq_avail) {
5281 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5282 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5284 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5288 if (!IS_GEN2(dev) &&
5289 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5290 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5292 pipeconf |= PIPECONF_PROGRESSIVE;
5294 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5295 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5297 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5298 POSTING_READ(PIPECONF(intel_crtc->pipe));
5301 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5303 struct drm_framebuffer *fb)
5305 struct drm_device *dev = crtc->dev;
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5308 int pipe = intel_crtc->pipe;
5309 int plane = intel_crtc->plane;
5310 int refclk, num_connectors = 0;
5311 intel_clock_t clock, reduced_clock;
5313 bool ok, has_reduced_clock = false;
5314 bool is_lvds = false, is_dsi = false;
5315 struct intel_encoder *encoder;
5316 const intel_limit_t *limit;
5319 for_each_encoder_on_crtc(dev, crtc, encoder) {
5320 switch (encoder->type) {
5321 case INTEL_OUTPUT_LVDS:
5324 case INTEL_OUTPUT_DSI:
5335 if (!intel_crtc->config.clock_set) {
5336 refclk = i9xx_get_refclk(crtc, num_connectors);
5339 * Returns a set of divisors for the desired target clock with
5340 * the given refclk, or FALSE. The returned values represent
5341 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5344 limit = intel_limit(crtc, refclk);
5345 ok = dev_priv->display.find_dpll(limit, crtc,
5346 intel_crtc->config.port_clock,
5347 refclk, NULL, &clock);
5349 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5353 if (is_lvds && dev_priv->lvds_downclock_avail) {
5355 * Ensure we match the reduced clock's P to the target
5356 * clock. If the clocks don't match, we can't switch
5357 * the display clock by using the FP0/FP1. In such case
5358 * we will disable the LVDS downclock feature.
5361 dev_priv->display.find_dpll(limit, crtc,
5362 dev_priv->lvds_downclock,
5366 /* Compat-code for transition, will disappear. */
5367 intel_crtc->config.dpll.n = clock.n;
5368 intel_crtc->config.dpll.m1 = clock.m1;
5369 intel_crtc->config.dpll.m2 = clock.m2;
5370 intel_crtc->config.dpll.p1 = clock.p1;
5371 intel_crtc->config.dpll.p2 = clock.p2;
5375 i8xx_update_pll(intel_crtc,
5376 has_reduced_clock ? &reduced_clock : NULL,
5378 } else if (IS_VALLEYVIEW(dev)) {
5379 vlv_update_pll(intel_crtc);
5381 i9xx_update_pll(intel_crtc,
5382 has_reduced_clock ? &reduced_clock : NULL,
5387 /* Set up the display plane register */
5388 dspcntr = DISPPLANE_GAMMA_ENABLE;
5390 if (!IS_VALLEYVIEW(dev)) {
5392 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5394 dspcntr |= DISPPLANE_SEL_PIPE_B;
5397 intel_set_pipe_timings(intel_crtc);
5399 /* pipesrc and dspsize control the size that is scaled from,
5400 * which should always be the user's requested size.
5402 I915_WRITE(DSPSIZE(plane),
5403 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5404 (intel_crtc->config.pipe_src_w - 1));
5405 I915_WRITE(DSPPOS(plane), 0);
5407 i9xx_set_pipeconf(intel_crtc);
5409 I915_WRITE(DSPCNTR(plane), dspcntr);
5410 POSTING_READ(DSPCNTR(plane));
5412 ret = intel_pipe_set_base(crtc, x, y, fb);
5417 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5418 struct intel_crtc_config *pipe_config)
5420 struct drm_device *dev = crtc->base.dev;
5421 struct drm_i915_private *dev_priv = dev->dev_private;
5424 tmp = I915_READ(PFIT_CONTROL);
5425 if (!(tmp & PFIT_ENABLE))
5428 /* Check whether the pfit is attached to our pipe. */
5429 if (INTEL_INFO(dev)->gen < 4) {
5430 if (crtc->pipe != PIPE_B)
5433 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5437 pipe_config->gmch_pfit.control = tmp;
5438 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5439 if (INTEL_INFO(dev)->gen < 5)
5440 pipe_config->gmch_pfit.lvds_border_bits =
5441 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5444 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5445 struct intel_crtc_config *pipe_config)
5447 struct drm_device *dev = crtc->base.dev;
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 int pipe = pipe_config->cpu_transcoder;
5450 intel_clock_t clock;
5452 int refclk = 100000;
5454 mutex_lock(&dev_priv->dpio_lock);
5455 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5456 mutex_unlock(&dev_priv->dpio_lock);
5458 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5459 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5460 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5461 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5462 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5464 vlv_clock(refclk, &clock);
5466 /* clock.dot is the fast clock */
5467 pipe_config->port_clock = clock.dot / 5;
5470 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5471 struct intel_crtc_config *pipe_config)
5473 struct drm_device *dev = crtc->base.dev;
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5477 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5478 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5480 tmp = I915_READ(PIPECONF(crtc->pipe));
5481 if (!(tmp & PIPECONF_ENABLE))
5484 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5485 switch (tmp & PIPECONF_BPC_MASK) {
5487 pipe_config->pipe_bpp = 18;
5490 pipe_config->pipe_bpp = 24;
5492 case PIPECONF_10BPC:
5493 pipe_config->pipe_bpp = 30;
5500 if (INTEL_INFO(dev)->gen < 4)
5501 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5503 intel_get_pipe_timings(crtc, pipe_config);
5505 i9xx_get_pfit_config(crtc, pipe_config);
5507 if (INTEL_INFO(dev)->gen >= 4) {
5508 tmp = I915_READ(DPLL_MD(crtc->pipe));
5509 pipe_config->pixel_multiplier =
5510 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5511 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5512 pipe_config->dpll_hw_state.dpll_md = tmp;
5513 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5514 tmp = I915_READ(DPLL(crtc->pipe));
5515 pipe_config->pixel_multiplier =
5516 ((tmp & SDVO_MULTIPLIER_MASK)
5517 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5519 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5520 * port and will be fixed up in the encoder->get_config
5522 pipe_config->pixel_multiplier = 1;
5524 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5525 if (!IS_VALLEYVIEW(dev)) {
5526 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5527 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5529 /* Mask out read-only status bits. */
5530 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5531 DPLL_PORTC_READY_MASK |
5532 DPLL_PORTB_READY_MASK);
5535 if (IS_VALLEYVIEW(dev))
5536 vlv_crtc_clock_get(crtc, pipe_config);
5538 i9xx_crtc_clock_get(crtc, pipe_config);
5543 static void ironlake_init_pch_refclk(struct drm_device *dev)
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 struct drm_mode_config *mode_config = &dev->mode_config;
5547 struct intel_encoder *encoder;
5549 bool has_lvds = false;
5550 bool has_cpu_edp = false;
5551 bool has_panel = false;
5552 bool has_ck505 = false;
5553 bool can_ssc = false;
5555 /* We need to take the global config into account */
5556 list_for_each_entry(encoder, &mode_config->encoder_list,
5558 switch (encoder->type) {
5559 case INTEL_OUTPUT_LVDS:
5563 case INTEL_OUTPUT_EDP:
5565 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5571 if (HAS_PCH_IBX(dev)) {
5572 has_ck505 = dev_priv->vbt.display_clock_mode;
5573 can_ssc = has_ck505;
5579 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5580 has_panel, has_lvds, has_ck505);
5582 /* Ironlake: try to setup display ref clock before DPLL
5583 * enabling. This is only under driver's control after
5584 * PCH B stepping, previous chipset stepping should be
5585 * ignoring this setting.
5587 val = I915_READ(PCH_DREF_CONTROL);
5589 /* As we must carefully and slowly disable/enable each source in turn,
5590 * compute the final state we want first and check if we need to
5591 * make any changes at all.
5594 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5596 final |= DREF_NONSPREAD_CK505_ENABLE;
5598 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5600 final &= ~DREF_SSC_SOURCE_MASK;
5601 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5602 final &= ~DREF_SSC1_ENABLE;
5605 final |= DREF_SSC_SOURCE_ENABLE;
5607 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5608 final |= DREF_SSC1_ENABLE;
5611 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5612 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5614 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5616 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5618 final |= DREF_SSC_SOURCE_DISABLE;
5619 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5625 /* Always enable nonspread source */
5626 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5629 val |= DREF_NONSPREAD_CK505_ENABLE;
5631 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5634 val &= ~DREF_SSC_SOURCE_MASK;
5635 val |= DREF_SSC_SOURCE_ENABLE;
5637 /* SSC must be turned on before enabling the CPU output */
5638 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5639 DRM_DEBUG_KMS("Using SSC on panel\n");
5640 val |= DREF_SSC1_ENABLE;
5642 val &= ~DREF_SSC1_ENABLE;
5644 /* Get SSC going before enabling the outputs */
5645 I915_WRITE(PCH_DREF_CONTROL, val);
5646 POSTING_READ(PCH_DREF_CONTROL);
5649 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5651 /* Enable CPU source on CPU attached eDP */
5653 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5654 DRM_DEBUG_KMS("Using SSC on eDP\n");
5655 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5658 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5660 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5662 I915_WRITE(PCH_DREF_CONTROL, val);
5663 POSTING_READ(PCH_DREF_CONTROL);
5666 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5668 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5670 /* Turn off CPU output */
5671 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5673 I915_WRITE(PCH_DREF_CONTROL, val);
5674 POSTING_READ(PCH_DREF_CONTROL);
5677 /* Turn off the SSC source */
5678 val &= ~DREF_SSC_SOURCE_MASK;
5679 val |= DREF_SSC_SOURCE_DISABLE;
5682 val &= ~DREF_SSC1_ENABLE;
5684 I915_WRITE(PCH_DREF_CONTROL, val);
5685 POSTING_READ(PCH_DREF_CONTROL);
5689 BUG_ON(val != final);
5692 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5696 tmp = I915_READ(SOUTH_CHICKEN2);
5697 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5698 I915_WRITE(SOUTH_CHICKEN2, tmp);
5700 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5701 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5702 DRM_ERROR("FDI mPHY reset assert timeout\n");
5704 tmp = I915_READ(SOUTH_CHICKEN2);
5705 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5706 I915_WRITE(SOUTH_CHICKEN2, tmp);
5708 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5709 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5710 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5713 /* WaMPhyProgramming:hsw */
5714 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5718 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5719 tmp &= ~(0xFF << 24);
5720 tmp |= (0x12 << 24);
5721 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5723 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5725 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5727 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5729 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5731 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5732 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5733 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5735 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5736 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5737 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5739 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5742 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5744 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5747 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5749 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5752 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5754 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5757 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5759 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5760 tmp &= ~(0xFF << 16);
5761 tmp |= (0x1C << 16);
5762 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5764 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5765 tmp &= ~(0xFF << 16);
5766 tmp |= (0x1C << 16);
5767 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5769 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5771 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5773 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5775 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5777 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5778 tmp &= ~(0xF << 28);
5780 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5782 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5783 tmp &= ~(0xF << 28);
5785 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5788 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5789 * Programming" based on the parameters passed:
5790 * - Sequence to enable CLKOUT_DP
5791 * - Sequence to enable CLKOUT_DP without spread
5792 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5794 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5800 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5802 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5803 with_fdi, "LP PCH doesn't have FDI\n"))
5806 mutex_lock(&dev_priv->dpio_lock);
5808 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5809 tmp &= ~SBI_SSCCTL_DISABLE;
5810 tmp |= SBI_SSCCTL_PATHALT;
5811 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5816 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5817 tmp &= ~SBI_SSCCTL_PATHALT;
5818 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5821 lpt_reset_fdi_mphy(dev_priv);
5822 lpt_program_fdi_mphy(dev_priv);
5826 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5827 SBI_GEN0 : SBI_DBUFF0;
5828 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5829 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5830 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5832 mutex_unlock(&dev_priv->dpio_lock);
5835 /* Sequence to disable CLKOUT_DP */
5836 static void lpt_disable_clkout_dp(struct drm_device *dev)
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5841 mutex_lock(&dev_priv->dpio_lock);
5843 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5844 SBI_GEN0 : SBI_DBUFF0;
5845 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5846 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5847 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5849 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5850 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5851 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5852 tmp |= SBI_SSCCTL_PATHALT;
5853 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5856 tmp |= SBI_SSCCTL_DISABLE;
5857 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5860 mutex_unlock(&dev_priv->dpio_lock);
5863 static void lpt_init_pch_refclk(struct drm_device *dev)
5865 struct drm_mode_config *mode_config = &dev->mode_config;
5866 struct intel_encoder *encoder;
5867 bool has_vga = false;
5869 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5870 switch (encoder->type) {
5871 case INTEL_OUTPUT_ANALOG:
5878 lpt_enable_clkout_dp(dev, true, true);
5880 lpt_disable_clkout_dp(dev);
5884 * Initialize reference clocks when the driver loads
5886 void intel_init_pch_refclk(struct drm_device *dev)
5888 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5889 ironlake_init_pch_refclk(dev);
5890 else if (HAS_PCH_LPT(dev))
5891 lpt_init_pch_refclk(dev);
5894 static int ironlake_get_refclk(struct drm_crtc *crtc)
5896 struct drm_device *dev = crtc->dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 struct intel_encoder *encoder;
5899 int num_connectors = 0;
5900 bool is_lvds = false;
5902 for_each_encoder_on_crtc(dev, crtc, encoder) {
5903 switch (encoder->type) {
5904 case INTEL_OUTPUT_LVDS:
5911 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5912 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5913 dev_priv->vbt.lvds_ssc_freq);
5914 return dev_priv->vbt.lvds_ssc_freq * 1000;
5920 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5922 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5924 int pipe = intel_crtc->pipe;
5929 switch (intel_crtc->config.pipe_bpp) {
5931 val |= PIPECONF_6BPC;
5934 val |= PIPECONF_8BPC;
5937 val |= PIPECONF_10BPC;
5940 val |= PIPECONF_12BPC;
5943 /* Case prevented by intel_choose_pipe_bpp_dither. */
5947 if (intel_crtc->config.dither)
5948 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5950 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5951 val |= PIPECONF_INTERLACED_ILK;
5953 val |= PIPECONF_PROGRESSIVE;
5955 if (intel_crtc->config.limited_color_range)
5956 val |= PIPECONF_COLOR_RANGE_SELECT;
5958 I915_WRITE(PIPECONF(pipe), val);
5959 POSTING_READ(PIPECONF(pipe));
5963 * Set up the pipe CSC unit.
5965 * Currently only full range RGB to limited range RGB conversion
5966 * is supported, but eventually this should handle various
5967 * RGB<->YCbCr scenarios as well.
5969 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5971 struct drm_device *dev = crtc->dev;
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5974 int pipe = intel_crtc->pipe;
5975 uint16_t coeff = 0x7800; /* 1.0 */
5978 * TODO: Check what kind of values actually come out of the pipe
5979 * with these coeff/postoff values and adjust to get the best
5980 * accuracy. Perhaps we even need to take the bpc value into
5984 if (intel_crtc->config.limited_color_range)
5985 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5988 * GY/GU and RY/RU should be the other way around according
5989 * to BSpec, but reality doesn't agree. Just set them up in
5990 * a way that results in the correct picture.
5992 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5993 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5995 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5996 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5998 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5999 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6001 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6002 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6003 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6005 if (INTEL_INFO(dev)->gen > 6) {
6006 uint16_t postoff = 0;
6008 if (intel_crtc->config.limited_color_range)
6009 postoff = (16 * (1 << 13) / 255) & 0x1fff;
6011 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6012 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6013 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6015 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6017 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6019 if (intel_crtc->config.limited_color_range)
6020 mode |= CSC_BLACK_SCREEN_OFFSET;
6022 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6026 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6028 struct drm_device *dev = crtc->dev;
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 enum pipe pipe = intel_crtc->pipe;
6032 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6037 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6038 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6040 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6041 val |= PIPECONF_INTERLACED_ILK;
6043 val |= PIPECONF_PROGRESSIVE;
6045 I915_WRITE(PIPECONF(cpu_transcoder), val);
6046 POSTING_READ(PIPECONF(cpu_transcoder));
6048 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6049 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6051 if (IS_BROADWELL(dev)) {
6054 switch (intel_crtc->config.pipe_bpp) {
6056 val |= PIPEMISC_DITHER_6_BPC;
6059 val |= PIPEMISC_DITHER_8_BPC;
6062 val |= PIPEMISC_DITHER_10_BPC;
6065 val |= PIPEMISC_DITHER_12_BPC;
6068 /* Case prevented by pipe_config_set_bpp. */
6072 if (intel_crtc->config.dither)
6073 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6075 I915_WRITE(PIPEMISC(pipe), val);
6079 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6080 intel_clock_t *clock,
6081 bool *has_reduced_clock,
6082 intel_clock_t *reduced_clock)
6084 struct drm_device *dev = crtc->dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086 struct intel_encoder *intel_encoder;
6088 const intel_limit_t *limit;
6089 bool ret, is_lvds = false;
6091 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6092 switch (intel_encoder->type) {
6093 case INTEL_OUTPUT_LVDS:
6099 refclk = ironlake_get_refclk(crtc);
6102 * Returns a set of divisors for the desired target clock with the given
6103 * refclk, or FALSE. The returned values represent the clock equation:
6104 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6106 limit = intel_limit(crtc, refclk);
6107 ret = dev_priv->display.find_dpll(limit, crtc,
6108 to_intel_crtc(crtc)->config.port_clock,
6109 refclk, NULL, clock);
6113 if (is_lvds && dev_priv->lvds_downclock_avail) {
6115 * Ensure we match the reduced clock's P to the target clock.
6116 * If the clocks don't match, we can't switch the display clock
6117 * by using the FP0/FP1. In such case we will disable the LVDS
6118 * downclock feature.
6120 *has_reduced_clock =
6121 dev_priv->display.find_dpll(limit, crtc,
6122 dev_priv->lvds_downclock,
6130 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6133 * Account for spread spectrum to avoid
6134 * oversubscribing the link. Max center spread
6135 * is 2.5%; use 5% for safety's sake.
6137 u32 bps = target_clock * bpp * 21 / 20;
6138 return bps / (link_bw * 8) + 1;
6141 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6143 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6146 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6148 intel_clock_t *reduced_clock, u32 *fp2)
6150 struct drm_crtc *crtc = &intel_crtc->base;
6151 struct drm_device *dev = crtc->dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 struct intel_encoder *intel_encoder;
6155 int factor, num_connectors = 0;
6156 bool is_lvds = false, is_sdvo = false;
6158 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6159 switch (intel_encoder->type) {
6160 case INTEL_OUTPUT_LVDS:
6163 case INTEL_OUTPUT_SDVO:
6164 case INTEL_OUTPUT_HDMI:
6172 /* Enable autotuning of the PLL clock (if permissible) */
6175 if ((intel_panel_use_ssc(dev_priv) &&
6176 dev_priv->vbt.lvds_ssc_freq == 100) ||
6177 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6179 } else if (intel_crtc->config.sdvo_tv_clock)
6182 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6185 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6191 dpll |= DPLLB_MODE_LVDS;
6193 dpll |= DPLLB_MODE_DAC_SERIAL;
6195 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6196 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6199 dpll |= DPLL_SDVO_HIGH_SPEED;
6200 if (intel_crtc->config.has_dp_encoder)
6201 dpll |= DPLL_SDVO_HIGH_SPEED;
6203 /* compute bitmask from p1 value */
6204 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6206 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6208 switch (intel_crtc->config.dpll.p2) {
6210 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6213 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6216 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6219 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6223 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6224 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6226 dpll |= PLL_REF_INPUT_DREFCLK;
6228 return dpll | DPLL_VCO_ENABLE;
6231 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6233 struct drm_framebuffer *fb)
6235 struct drm_device *dev = crtc->dev;
6236 struct drm_i915_private *dev_priv = dev->dev_private;
6237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6238 int pipe = intel_crtc->pipe;
6239 int plane = intel_crtc->plane;
6240 int num_connectors = 0;
6241 intel_clock_t clock, reduced_clock;
6242 u32 dpll = 0, fp = 0, fp2 = 0;
6243 bool ok, has_reduced_clock = false;
6244 bool is_lvds = false;
6245 struct intel_encoder *encoder;
6246 struct intel_shared_dpll *pll;
6249 for_each_encoder_on_crtc(dev, crtc, encoder) {
6250 switch (encoder->type) {
6251 case INTEL_OUTPUT_LVDS:
6259 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6260 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6262 ok = ironlake_compute_clocks(crtc, &clock,
6263 &has_reduced_clock, &reduced_clock);
6264 if (!ok && !intel_crtc->config.clock_set) {
6265 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6268 /* Compat-code for transition, will disappear. */
6269 if (!intel_crtc->config.clock_set) {
6270 intel_crtc->config.dpll.n = clock.n;
6271 intel_crtc->config.dpll.m1 = clock.m1;
6272 intel_crtc->config.dpll.m2 = clock.m2;
6273 intel_crtc->config.dpll.p1 = clock.p1;
6274 intel_crtc->config.dpll.p2 = clock.p2;
6277 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6278 if (intel_crtc->config.has_pch_encoder) {
6279 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6280 if (has_reduced_clock)
6281 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6283 dpll = ironlake_compute_dpll(intel_crtc,
6284 &fp, &reduced_clock,
6285 has_reduced_clock ? &fp2 : NULL);
6287 intel_crtc->config.dpll_hw_state.dpll = dpll;
6288 intel_crtc->config.dpll_hw_state.fp0 = fp;
6289 if (has_reduced_clock)
6290 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6292 intel_crtc->config.dpll_hw_state.fp1 = fp;
6294 pll = intel_get_shared_dpll(intel_crtc);
6296 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6301 intel_put_shared_dpll(intel_crtc);
6303 if (intel_crtc->config.has_dp_encoder)
6304 intel_dp_set_m_n(intel_crtc);
6306 if (is_lvds && has_reduced_clock && i915_powersave)
6307 intel_crtc->lowfreq_avail = true;
6309 intel_crtc->lowfreq_avail = false;
6311 intel_set_pipe_timings(intel_crtc);
6313 if (intel_crtc->config.has_pch_encoder) {
6314 intel_cpu_transcoder_set_m_n(intel_crtc,
6315 &intel_crtc->config.fdi_m_n);
6318 ironlake_set_pipeconf(crtc);
6320 /* Set up the display plane register */
6321 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6322 POSTING_READ(DSPCNTR(plane));
6324 ret = intel_pipe_set_base(crtc, x, y, fb);
6329 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6330 struct intel_link_m_n *m_n)
6332 struct drm_device *dev = crtc->base.dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 enum pipe pipe = crtc->pipe;
6336 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6337 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6338 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6340 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6341 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6342 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6345 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6346 enum transcoder transcoder,
6347 struct intel_link_m_n *m_n)
6349 struct drm_device *dev = crtc->base.dev;
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351 enum pipe pipe = crtc->pipe;
6353 if (INTEL_INFO(dev)->gen >= 5) {
6354 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6355 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6356 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6358 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6359 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6360 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6362 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6363 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6364 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6366 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6367 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6368 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6372 void intel_dp_get_m_n(struct intel_crtc *crtc,
6373 struct intel_crtc_config *pipe_config)
6375 if (crtc->config.has_pch_encoder)
6376 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6378 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6379 &pipe_config->dp_m_n);
6382 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6383 struct intel_crtc_config *pipe_config)
6385 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6386 &pipe_config->fdi_m_n);
6389 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6390 struct intel_crtc_config *pipe_config)
6392 struct drm_device *dev = crtc->base.dev;
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6396 tmp = I915_READ(PF_CTL(crtc->pipe));
6398 if (tmp & PF_ENABLE) {
6399 pipe_config->pch_pfit.enabled = true;
6400 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6401 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6403 /* We currently do not free assignements of panel fitters on
6404 * ivb/hsw (since we don't use the higher upscaling modes which
6405 * differentiates them) so just WARN about this case for now. */
6407 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6408 PF_PIPE_SEL_IVB(crtc->pipe));
6413 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6414 struct intel_crtc_config *pipe_config)
6416 struct drm_device *dev = crtc->base.dev;
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6420 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6421 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6423 tmp = I915_READ(PIPECONF(crtc->pipe));
6424 if (!(tmp & PIPECONF_ENABLE))
6427 switch (tmp & PIPECONF_BPC_MASK) {
6429 pipe_config->pipe_bpp = 18;
6432 pipe_config->pipe_bpp = 24;
6434 case PIPECONF_10BPC:
6435 pipe_config->pipe_bpp = 30;
6437 case PIPECONF_12BPC:
6438 pipe_config->pipe_bpp = 36;
6444 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6445 struct intel_shared_dpll *pll;
6447 pipe_config->has_pch_encoder = true;
6449 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6450 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6451 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6453 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6455 if (HAS_PCH_IBX(dev_priv->dev)) {
6456 pipe_config->shared_dpll =
6457 (enum intel_dpll_id) crtc->pipe;
6459 tmp = I915_READ(PCH_DPLL_SEL);
6460 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6461 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6463 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6466 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6468 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6469 &pipe_config->dpll_hw_state));
6471 tmp = pipe_config->dpll_hw_state.dpll;
6472 pipe_config->pixel_multiplier =
6473 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6474 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6476 ironlake_pch_clock_get(crtc, pipe_config);
6478 pipe_config->pixel_multiplier = 1;
6481 intel_get_pipe_timings(crtc, pipe_config);
6483 ironlake_get_pfit_config(crtc, pipe_config);
6488 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6490 struct drm_device *dev = dev_priv->dev;
6491 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6492 struct intel_crtc *crtc;
6493 unsigned long irqflags;
6496 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6497 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6498 pipe_name(crtc->pipe));
6500 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6501 WARN(plls->spll_refcount, "SPLL enabled\n");
6502 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6503 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6504 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6505 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6506 "CPU PWM1 enabled\n");
6507 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6508 "CPU PWM2 enabled\n");
6509 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6510 "PCH PWM1 enabled\n");
6511 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6512 "Utility pin enabled\n");
6513 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6515 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6516 val = I915_READ(DEIMR);
6517 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6518 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6519 val = I915_READ(SDEIMR);
6520 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6521 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6522 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6526 * This function implements pieces of two sequences from BSpec:
6527 * - Sequence for display software to disable LCPLL
6528 * - Sequence for display software to allow package C8+
6529 * The steps implemented here are just the steps that actually touch the LCPLL
6530 * register. Callers should take care of disabling all the display engine
6531 * functions, doing the mode unset, fixing interrupts, etc.
6533 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6534 bool switch_to_fclk, bool allow_power_down)
6538 assert_can_disable_lcpll(dev_priv);
6540 val = I915_READ(LCPLL_CTL);
6542 if (switch_to_fclk) {
6543 val |= LCPLL_CD_SOURCE_FCLK;
6544 I915_WRITE(LCPLL_CTL, val);
6546 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6547 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6548 DRM_ERROR("Switching to FCLK failed\n");
6550 val = I915_READ(LCPLL_CTL);
6553 val |= LCPLL_PLL_DISABLE;
6554 I915_WRITE(LCPLL_CTL, val);
6555 POSTING_READ(LCPLL_CTL);
6557 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6558 DRM_ERROR("LCPLL still locked\n");
6560 val = I915_READ(D_COMP);
6561 val |= D_COMP_COMP_DISABLE;
6562 mutex_lock(&dev_priv->rps.hw_lock);
6563 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6564 DRM_ERROR("Failed to disable D_COMP\n");
6565 mutex_unlock(&dev_priv->rps.hw_lock);
6566 POSTING_READ(D_COMP);
6569 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6570 DRM_ERROR("D_COMP RCOMP still in progress\n");
6572 if (allow_power_down) {
6573 val = I915_READ(LCPLL_CTL);
6574 val |= LCPLL_POWER_DOWN_ALLOW;
6575 I915_WRITE(LCPLL_CTL, val);
6576 POSTING_READ(LCPLL_CTL);
6581 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6584 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6588 val = I915_READ(LCPLL_CTL);
6590 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6591 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6594 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6595 * we'll hang the machine! */
6596 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6598 if (val & LCPLL_POWER_DOWN_ALLOW) {
6599 val &= ~LCPLL_POWER_DOWN_ALLOW;
6600 I915_WRITE(LCPLL_CTL, val);
6601 POSTING_READ(LCPLL_CTL);
6604 val = I915_READ(D_COMP);
6605 val |= D_COMP_COMP_FORCE;
6606 val &= ~D_COMP_COMP_DISABLE;
6607 mutex_lock(&dev_priv->rps.hw_lock);
6608 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6609 DRM_ERROR("Failed to enable D_COMP\n");
6610 mutex_unlock(&dev_priv->rps.hw_lock);
6611 POSTING_READ(D_COMP);
6613 val = I915_READ(LCPLL_CTL);
6614 val &= ~LCPLL_PLL_DISABLE;
6615 I915_WRITE(LCPLL_CTL, val);
6617 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6618 DRM_ERROR("LCPLL not locked yet\n");
6620 if (val & LCPLL_CD_SOURCE_FCLK) {
6621 val = I915_READ(LCPLL_CTL);
6622 val &= ~LCPLL_CD_SOURCE_FCLK;
6623 I915_WRITE(LCPLL_CTL, val);
6625 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6626 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6627 DRM_ERROR("Switching back to LCPLL failed\n");
6630 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6633 void hsw_enable_pc8_work(struct work_struct *__work)
6635 struct drm_i915_private *dev_priv =
6636 container_of(to_delayed_work(__work), struct drm_i915_private,
6638 struct drm_device *dev = dev_priv->dev;
6641 if (dev_priv->pc8.enabled)
6644 DRM_DEBUG_KMS("Enabling package C8+\n");
6646 dev_priv->pc8.enabled = true;
6648 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6649 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6650 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6651 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6654 lpt_disable_clkout_dp(dev);
6655 hsw_pc8_disable_interrupts(dev);
6656 hsw_disable_lcpll(dev_priv, true, true);
6659 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6661 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6662 WARN(dev_priv->pc8.disable_count < 1,
6663 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6665 dev_priv->pc8.disable_count--;
6666 if (dev_priv->pc8.disable_count != 0)
6669 schedule_delayed_work(&dev_priv->pc8.enable_work,
6670 msecs_to_jiffies(i915_pc8_timeout));
6673 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6675 struct drm_device *dev = dev_priv->dev;
6678 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6679 WARN(dev_priv->pc8.disable_count < 0,
6680 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6682 dev_priv->pc8.disable_count++;
6683 if (dev_priv->pc8.disable_count != 1)
6686 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6687 if (!dev_priv->pc8.enabled)
6690 DRM_DEBUG_KMS("Disabling package C8+\n");
6692 hsw_restore_lcpll(dev_priv);
6693 hsw_pc8_restore_interrupts(dev);
6694 lpt_init_pch_refclk(dev);
6696 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6697 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6698 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6699 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6702 intel_prepare_ddi(dev);
6703 i915_gem_init_swizzling(dev);
6704 mutex_lock(&dev_priv->rps.hw_lock);
6705 gen6_update_ring_freq(dev);
6706 mutex_unlock(&dev_priv->rps.hw_lock);
6707 dev_priv->pc8.enabled = false;
6710 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6712 if (!HAS_PC8(dev_priv->dev))
6715 mutex_lock(&dev_priv->pc8.lock);
6716 __hsw_enable_package_c8(dev_priv);
6717 mutex_unlock(&dev_priv->pc8.lock);
6720 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6722 if (!HAS_PC8(dev_priv->dev))
6725 mutex_lock(&dev_priv->pc8.lock);
6726 __hsw_disable_package_c8(dev_priv);
6727 mutex_unlock(&dev_priv->pc8.lock);
6730 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6732 struct drm_device *dev = dev_priv->dev;
6733 struct intel_crtc *crtc;
6736 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6737 if (crtc->base.enabled)
6740 /* This case is still possible since we have the i915.disable_power_well
6741 * parameter and also the KVMr or something else might be requesting the
6743 val = I915_READ(HSW_PWR_WELL_DRIVER);
6745 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6752 /* Since we're called from modeset_global_resources there's no way to
6753 * symmetrically increase and decrease the refcount, so we use
6754 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6757 static void hsw_update_package_c8(struct drm_device *dev)
6759 struct drm_i915_private *dev_priv = dev->dev_private;
6762 if (!HAS_PC8(dev_priv->dev))
6765 if (!i915_enable_pc8)
6768 mutex_lock(&dev_priv->pc8.lock);
6770 allow = hsw_can_enable_package_c8(dev_priv);
6772 if (allow == dev_priv->pc8.requirements_met)
6775 dev_priv->pc8.requirements_met = allow;
6778 __hsw_enable_package_c8(dev_priv);
6780 __hsw_disable_package_c8(dev_priv);
6783 mutex_unlock(&dev_priv->pc8.lock);
6786 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6788 if (!HAS_PC8(dev_priv->dev))
6791 mutex_lock(&dev_priv->pc8.lock);
6792 if (!dev_priv->pc8.gpu_idle) {
6793 dev_priv->pc8.gpu_idle = true;
6794 __hsw_enable_package_c8(dev_priv);
6796 mutex_unlock(&dev_priv->pc8.lock);
6799 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6801 if (!HAS_PC8(dev_priv->dev))
6804 mutex_lock(&dev_priv->pc8.lock);
6805 if (dev_priv->pc8.gpu_idle) {
6806 dev_priv->pc8.gpu_idle = false;
6807 __hsw_disable_package_c8(dev_priv);
6809 mutex_unlock(&dev_priv->pc8.lock);
6812 #define for_each_power_domain(domain, mask) \
6813 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6814 if ((1 << (domain)) & (mask))
6816 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6817 enum pipe pipe, bool pfit_enabled)
6820 enum transcoder transcoder;
6822 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6824 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6825 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6827 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6832 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6834 struct drm_i915_private *dev_priv = dev->dev_private;
6836 if (dev_priv->power_domains.init_power_on == enable)
6840 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6842 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6844 dev_priv->power_domains.init_power_on = enable;
6847 static void modeset_update_power_wells(struct drm_device *dev)
6849 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6850 struct intel_crtc *crtc;
6853 * First get all needed power domains, then put all unneeded, to avoid
6854 * any unnecessary toggling of the power wells.
6856 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6857 enum intel_display_power_domain domain;
6859 if (!crtc->base.enabled)
6862 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6864 crtc->config.pch_pfit.enabled);
6866 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6867 intel_display_power_get(dev, domain);
6870 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6871 enum intel_display_power_domain domain;
6873 for_each_power_domain(domain, crtc->enabled_power_domains)
6874 intel_display_power_put(dev, domain);
6876 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6879 intel_display_set_init_power(dev, false);
6882 static void haswell_modeset_global_resources(struct drm_device *dev)
6884 modeset_update_power_wells(dev);
6885 hsw_update_package_c8(dev);
6888 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6890 struct drm_framebuffer *fb)
6892 struct drm_device *dev = crtc->dev;
6893 struct drm_i915_private *dev_priv = dev->dev_private;
6894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895 int plane = intel_crtc->plane;
6898 if (!intel_ddi_pll_mode_set(crtc))
6901 if (intel_crtc->config.has_dp_encoder)
6902 intel_dp_set_m_n(intel_crtc);
6904 intel_crtc->lowfreq_avail = false;
6906 intel_set_pipe_timings(intel_crtc);
6908 if (intel_crtc->config.has_pch_encoder) {
6909 intel_cpu_transcoder_set_m_n(intel_crtc,
6910 &intel_crtc->config.fdi_m_n);
6913 haswell_set_pipeconf(crtc);
6915 intel_set_pipe_csc(crtc);
6917 /* Set up the display plane register */
6918 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6919 POSTING_READ(DSPCNTR(plane));
6921 ret = intel_pipe_set_base(crtc, x, y, fb);
6926 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6927 struct intel_crtc_config *pipe_config)
6929 struct drm_device *dev = crtc->base.dev;
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931 enum intel_display_power_domain pfit_domain;
6934 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6935 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6937 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6938 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6939 enum pipe trans_edp_pipe;
6940 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6942 WARN(1, "unknown pipe linked to edp transcoder\n");
6943 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6944 case TRANS_DDI_EDP_INPUT_A_ON:
6945 trans_edp_pipe = PIPE_A;
6947 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6948 trans_edp_pipe = PIPE_B;
6950 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6951 trans_edp_pipe = PIPE_C;
6955 if (trans_edp_pipe == crtc->pipe)
6956 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6959 if (!intel_display_power_enabled(dev,
6960 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6963 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6964 if (!(tmp & PIPECONF_ENABLE))
6968 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6969 * DDI E. So just check whether this pipe is wired to DDI E and whether
6970 * the PCH transcoder is on.
6972 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6973 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6974 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6975 pipe_config->has_pch_encoder = true;
6977 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6978 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6979 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6981 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6984 intel_get_pipe_timings(crtc, pipe_config);
6986 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6987 if (intel_display_power_enabled(dev, pfit_domain))
6988 ironlake_get_pfit_config(crtc, pipe_config);
6990 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6991 (I915_READ(IPS_CTL) & IPS_ENABLE);
6993 pipe_config->pixel_multiplier = 1;
6998 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7000 struct drm_framebuffer *fb)
7002 struct drm_device *dev = crtc->dev;
7003 struct drm_i915_private *dev_priv = dev->dev_private;
7004 struct intel_encoder *encoder;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7007 int pipe = intel_crtc->pipe;
7010 drm_vblank_pre_modeset(dev, pipe);
7012 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7014 drm_vblank_post_modeset(dev, pipe);
7019 for_each_encoder_on_crtc(dev, crtc, encoder) {
7020 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7021 encoder->base.base.id,
7022 drm_get_encoder_name(&encoder->base),
7023 mode->base.id, mode->name);
7024 encoder->mode_set(encoder);
7033 } hdmi_audio_clock[] = {
7034 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7035 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7036 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7037 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7038 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7039 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7040 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7041 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7042 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7043 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7046 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7047 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7051 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7052 if (mode->clock == hdmi_audio_clock[i].clock)
7056 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7057 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7061 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7062 hdmi_audio_clock[i].clock,
7063 hdmi_audio_clock[i].config);
7065 return hdmi_audio_clock[i].config;
7068 static bool intel_eld_uptodate(struct drm_connector *connector,
7069 int reg_eldv, uint32_t bits_eldv,
7070 int reg_elda, uint32_t bits_elda,
7073 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7074 uint8_t *eld = connector->eld;
7077 i = I915_READ(reg_eldv);
7086 i = I915_READ(reg_elda);
7088 I915_WRITE(reg_elda, i);
7090 for (i = 0; i < eld[2]; i++)
7091 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7097 static void g4x_write_eld(struct drm_connector *connector,
7098 struct drm_crtc *crtc,
7099 struct drm_display_mode *mode)
7101 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7102 uint8_t *eld = connector->eld;
7107 i = I915_READ(G4X_AUD_VID_DID);
7109 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7110 eldv = G4X_ELDV_DEVCL_DEVBLC;
7112 eldv = G4X_ELDV_DEVCTG;
7114 if (intel_eld_uptodate(connector,
7115 G4X_AUD_CNTL_ST, eldv,
7116 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7117 G4X_HDMIW_HDMIEDID))
7120 i = I915_READ(G4X_AUD_CNTL_ST);
7121 i &= ~(eldv | G4X_ELD_ADDR);
7122 len = (i >> 9) & 0x1f; /* ELD buffer size */
7123 I915_WRITE(G4X_AUD_CNTL_ST, i);
7128 len = min_t(uint8_t, eld[2], len);
7129 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7130 for (i = 0; i < len; i++)
7131 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7133 i = I915_READ(G4X_AUD_CNTL_ST);
7135 I915_WRITE(G4X_AUD_CNTL_ST, i);
7138 static void haswell_write_eld(struct drm_connector *connector,
7139 struct drm_crtc *crtc,
7140 struct drm_display_mode *mode)
7142 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7143 uint8_t *eld = connector->eld;
7144 struct drm_device *dev = crtc->dev;
7145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7149 int pipe = to_intel_crtc(crtc)->pipe;
7152 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7153 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7154 int aud_config = HSW_AUD_CFG(pipe);
7155 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7158 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7160 /* Audio output enable */
7161 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7162 tmp = I915_READ(aud_cntrl_st2);
7163 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7164 I915_WRITE(aud_cntrl_st2, tmp);
7166 /* Wait for 1 vertical blank */
7167 intel_wait_for_vblank(dev, pipe);
7169 /* Set ELD valid state */
7170 tmp = I915_READ(aud_cntrl_st2);
7171 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7172 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7173 I915_WRITE(aud_cntrl_st2, tmp);
7174 tmp = I915_READ(aud_cntrl_st2);
7175 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7177 /* Enable HDMI mode */
7178 tmp = I915_READ(aud_config);
7179 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7180 /* clear N_programing_enable and N_value_index */
7181 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7182 I915_WRITE(aud_config, tmp);
7184 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7186 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7187 intel_crtc->eld_vld = true;
7189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7190 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7191 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7192 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7194 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7197 if (intel_eld_uptodate(connector,
7198 aud_cntrl_st2, eldv,
7199 aud_cntl_st, IBX_ELD_ADDRESS,
7203 i = I915_READ(aud_cntrl_st2);
7205 I915_WRITE(aud_cntrl_st2, i);
7210 i = I915_READ(aud_cntl_st);
7211 i &= ~IBX_ELD_ADDRESS;
7212 I915_WRITE(aud_cntl_st, i);
7213 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7214 DRM_DEBUG_DRIVER("port num:%d\n", i);
7216 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7217 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7218 for (i = 0; i < len; i++)
7219 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7221 i = I915_READ(aud_cntrl_st2);
7223 I915_WRITE(aud_cntrl_st2, i);
7227 static void ironlake_write_eld(struct drm_connector *connector,
7228 struct drm_crtc *crtc,
7229 struct drm_display_mode *mode)
7231 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7232 uint8_t *eld = connector->eld;
7240 int pipe = to_intel_crtc(crtc)->pipe;
7242 if (HAS_PCH_IBX(connector->dev)) {
7243 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7244 aud_config = IBX_AUD_CFG(pipe);
7245 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7246 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7247 } else if (IS_VALLEYVIEW(connector->dev)) {
7248 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7249 aud_config = VLV_AUD_CFG(pipe);
7250 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7251 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7253 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7254 aud_config = CPT_AUD_CFG(pipe);
7255 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7256 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7259 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7261 if (IS_VALLEYVIEW(connector->dev)) {
7262 struct intel_encoder *intel_encoder;
7263 struct intel_digital_port *intel_dig_port;
7265 intel_encoder = intel_attached_encoder(connector);
7266 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7267 i = intel_dig_port->port;
7269 i = I915_READ(aud_cntl_st);
7270 i = (i >> 29) & DIP_PORT_SEL_MASK;
7271 /* DIP_Port_Select, 0x1 = PortB */
7275 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7276 /* operate blindly on all ports */
7277 eldv = IBX_ELD_VALIDB;
7278 eldv |= IBX_ELD_VALIDB << 4;
7279 eldv |= IBX_ELD_VALIDB << 8;
7281 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7282 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7285 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7286 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7287 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7288 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7290 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7293 if (intel_eld_uptodate(connector,
7294 aud_cntrl_st2, eldv,
7295 aud_cntl_st, IBX_ELD_ADDRESS,
7299 i = I915_READ(aud_cntrl_st2);
7301 I915_WRITE(aud_cntrl_st2, i);
7306 i = I915_READ(aud_cntl_st);
7307 i &= ~IBX_ELD_ADDRESS;
7308 I915_WRITE(aud_cntl_st, i);
7310 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7311 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7312 for (i = 0; i < len; i++)
7313 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7315 i = I915_READ(aud_cntrl_st2);
7317 I915_WRITE(aud_cntrl_st2, i);
7320 void intel_write_eld(struct drm_encoder *encoder,
7321 struct drm_display_mode *mode)
7323 struct drm_crtc *crtc = encoder->crtc;
7324 struct drm_connector *connector;
7325 struct drm_device *dev = encoder->dev;
7326 struct drm_i915_private *dev_priv = dev->dev_private;
7328 connector = drm_select_eld(encoder, mode);
7332 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7334 drm_get_connector_name(connector),
7335 connector->encoder->base.id,
7336 drm_get_encoder_name(connector->encoder));
7338 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7340 if (dev_priv->display.write_eld)
7341 dev_priv->display.write_eld(connector, crtc, mode);
7344 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7346 struct drm_device *dev = crtc->dev;
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7349 bool visible = base != 0;
7352 if (intel_crtc->cursor_visible == visible)
7355 cntl = I915_READ(_CURACNTR);
7357 /* On these chipsets we can only modify the base whilst
7358 * the cursor is disabled.
7360 I915_WRITE(_CURABASE, base);
7362 cntl &= ~(CURSOR_FORMAT_MASK);
7363 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7364 cntl |= CURSOR_ENABLE |
7365 CURSOR_GAMMA_ENABLE |
7368 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7369 I915_WRITE(_CURACNTR, cntl);
7371 intel_crtc->cursor_visible = visible;
7374 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7376 struct drm_device *dev = crtc->dev;
7377 struct drm_i915_private *dev_priv = dev->dev_private;
7378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7379 int pipe = intel_crtc->pipe;
7380 bool visible = base != 0;
7382 if (intel_crtc->cursor_visible != visible) {
7383 uint32_t cntl = I915_READ(CURCNTR(pipe));
7385 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7386 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7387 cntl |= pipe << 28; /* Connect to correct pipe */
7389 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7390 cntl |= CURSOR_MODE_DISABLE;
7392 I915_WRITE(CURCNTR(pipe), cntl);
7394 intel_crtc->cursor_visible = visible;
7396 /* and commit changes on next vblank */
7397 POSTING_READ(CURCNTR(pipe));
7398 I915_WRITE(CURBASE(pipe), base);
7399 POSTING_READ(CURBASE(pipe));
7402 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7404 struct drm_device *dev = crtc->dev;
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407 int pipe = intel_crtc->pipe;
7408 bool visible = base != 0;
7410 if (intel_crtc->cursor_visible != visible) {
7411 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7413 cntl &= ~CURSOR_MODE;
7414 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7416 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7417 cntl |= CURSOR_MODE_DISABLE;
7419 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7420 cntl |= CURSOR_PIPE_CSC_ENABLE;
7421 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7423 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7425 intel_crtc->cursor_visible = visible;
7427 /* and commit changes on next vblank */
7428 POSTING_READ(CURCNTR_IVB(pipe));
7429 I915_WRITE(CURBASE_IVB(pipe), base);
7430 POSTING_READ(CURBASE_IVB(pipe));
7433 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7434 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7437 struct drm_device *dev = crtc->dev;
7438 struct drm_i915_private *dev_priv = dev->dev_private;
7439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7440 int pipe = intel_crtc->pipe;
7441 int x = intel_crtc->cursor_x;
7442 int y = intel_crtc->cursor_y;
7443 u32 base = 0, pos = 0;
7447 base = intel_crtc->cursor_addr;
7449 if (x >= intel_crtc->config.pipe_src_w)
7452 if (y >= intel_crtc->config.pipe_src_h)
7456 if (x + intel_crtc->cursor_width <= 0)
7459 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7462 pos |= x << CURSOR_X_SHIFT;
7465 if (y + intel_crtc->cursor_height <= 0)
7468 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7471 pos |= y << CURSOR_Y_SHIFT;
7473 visible = base != 0;
7474 if (!visible && !intel_crtc->cursor_visible)
7477 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7478 I915_WRITE(CURPOS_IVB(pipe), pos);
7479 ivb_update_cursor(crtc, base);
7481 I915_WRITE(CURPOS(pipe), pos);
7482 if (IS_845G(dev) || IS_I865G(dev))
7483 i845_update_cursor(crtc, base);
7485 i9xx_update_cursor(crtc, base);
7489 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7490 struct drm_file *file,
7492 uint32_t width, uint32_t height)
7494 struct drm_device *dev = crtc->dev;
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7497 struct drm_i915_gem_object *obj;
7501 /* if we want to turn off the cursor ignore width and height */
7503 DRM_DEBUG_KMS("cursor off\n");
7506 mutex_lock(&dev->struct_mutex);
7510 /* Currently we only support 64x64 cursors */
7511 if (width != 64 || height != 64) {
7512 DRM_ERROR("we currently only support 64x64 cursors\n");
7516 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7517 if (&obj->base == NULL)
7520 if (obj->base.size < width * height * 4) {
7521 DRM_ERROR("buffer is to small\n");
7526 /* we only need to pin inside GTT if cursor is non-phy */
7527 mutex_lock(&dev->struct_mutex);
7528 if (!dev_priv->info->cursor_needs_physical) {
7531 if (obj->tiling_mode) {
7532 DRM_ERROR("cursor cannot be tiled\n");
7537 /* Note that the w/a also requires 2 PTE of padding following
7538 * the bo. We currently fill all unused PTE with the shadow
7539 * page and so we should always have valid PTE following the
7540 * cursor preventing the VT-d warning.
7543 if (need_vtd_wa(dev))
7544 alignment = 64*1024;
7546 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7548 DRM_ERROR("failed to move cursor bo into the GTT\n");
7552 ret = i915_gem_object_put_fence(obj);
7554 DRM_ERROR("failed to release fence for cursor");
7558 addr = i915_gem_obj_ggtt_offset(obj);
7560 int align = IS_I830(dev) ? 16 * 1024 : 256;
7561 ret = i915_gem_attach_phys_object(dev, obj,
7562 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7565 DRM_ERROR("failed to attach phys object\n");
7568 addr = obj->phys_obj->handle->busaddr;
7572 I915_WRITE(CURSIZE, (height << 12) | width);
7575 if (intel_crtc->cursor_bo) {
7576 if (dev_priv->info->cursor_needs_physical) {
7577 if (intel_crtc->cursor_bo != obj)
7578 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7580 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7581 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7584 mutex_unlock(&dev->struct_mutex);
7586 intel_crtc->cursor_addr = addr;
7587 intel_crtc->cursor_bo = obj;
7588 intel_crtc->cursor_width = width;
7589 intel_crtc->cursor_height = height;
7591 if (intel_crtc->active)
7592 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7596 i915_gem_object_unpin_from_display_plane(obj);
7598 mutex_unlock(&dev->struct_mutex);
7600 drm_gem_object_unreference_unlocked(&obj->base);
7604 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7608 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7609 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7611 if (intel_crtc->active)
7612 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7617 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7618 u16 *blue, uint32_t start, uint32_t size)
7620 int end = (start + size > 256) ? 256 : start + size, i;
7621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7623 for (i = start; i < end; i++) {
7624 intel_crtc->lut_r[i] = red[i] >> 8;
7625 intel_crtc->lut_g[i] = green[i] >> 8;
7626 intel_crtc->lut_b[i] = blue[i] >> 8;
7629 intel_crtc_load_lut(crtc);
7632 /* VESA 640x480x72Hz mode to set on the pipe */
7633 static struct drm_display_mode load_detect_mode = {
7634 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7635 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7638 static struct drm_framebuffer *
7639 intel_framebuffer_create(struct drm_device *dev,
7640 struct drm_mode_fb_cmd2 *mode_cmd,
7641 struct drm_i915_gem_object *obj)
7643 struct intel_framebuffer *intel_fb;
7646 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7648 drm_gem_object_unreference_unlocked(&obj->base);
7649 return ERR_PTR(-ENOMEM);
7652 ret = i915_mutex_lock_interruptible(dev);
7656 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7657 mutex_unlock(&dev->struct_mutex);
7661 return &intel_fb->base;
7663 drm_gem_object_unreference_unlocked(&obj->base);
7666 return ERR_PTR(ret);
7670 intel_framebuffer_pitch_for_width(int width, int bpp)
7672 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7673 return ALIGN(pitch, 64);
7677 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7679 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7680 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7683 static struct drm_framebuffer *
7684 intel_framebuffer_create_for_mode(struct drm_device *dev,
7685 struct drm_display_mode *mode,
7688 struct drm_i915_gem_object *obj;
7689 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7691 obj = i915_gem_alloc_object(dev,
7692 intel_framebuffer_size_for_mode(mode, bpp));
7694 return ERR_PTR(-ENOMEM);
7696 mode_cmd.width = mode->hdisplay;
7697 mode_cmd.height = mode->vdisplay;
7698 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7700 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7702 return intel_framebuffer_create(dev, &mode_cmd, obj);
7705 static struct drm_framebuffer *
7706 mode_fits_in_fbdev(struct drm_device *dev,
7707 struct drm_display_mode *mode)
7709 #ifdef CONFIG_DRM_I915_FBDEV
7710 struct drm_i915_private *dev_priv = dev->dev_private;
7711 struct drm_i915_gem_object *obj;
7712 struct drm_framebuffer *fb;
7714 if (dev_priv->fbdev == NULL)
7717 obj = dev_priv->fbdev->ifb.obj;
7721 fb = &dev_priv->fbdev->ifb.base;
7722 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7723 fb->bits_per_pixel))
7726 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7735 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7736 struct drm_display_mode *mode,
7737 struct intel_load_detect_pipe *old)
7739 struct intel_crtc *intel_crtc;
7740 struct intel_encoder *intel_encoder =
7741 intel_attached_encoder(connector);
7742 struct drm_crtc *possible_crtc;
7743 struct drm_encoder *encoder = &intel_encoder->base;
7744 struct drm_crtc *crtc = NULL;
7745 struct drm_device *dev = encoder->dev;
7746 struct drm_framebuffer *fb;
7749 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7750 connector->base.id, drm_get_connector_name(connector),
7751 encoder->base.id, drm_get_encoder_name(encoder));
7754 * Algorithm gets a little messy:
7756 * - if the connector already has an assigned crtc, use it (but make
7757 * sure it's on first)
7759 * - try to find the first unused crtc that can drive this connector,
7760 * and use that if we find one
7763 /* See if we already have a CRTC for this connector */
7764 if (encoder->crtc) {
7765 crtc = encoder->crtc;
7767 mutex_lock(&crtc->mutex);
7769 old->dpms_mode = connector->dpms;
7770 old->load_detect_temp = false;
7772 /* Make sure the crtc and connector are running */
7773 if (connector->dpms != DRM_MODE_DPMS_ON)
7774 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7779 /* Find an unused one (if possible) */
7780 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7782 if (!(encoder->possible_crtcs & (1 << i)))
7784 if (!possible_crtc->enabled) {
7785 crtc = possible_crtc;
7791 * If we didn't find an unused CRTC, don't use any.
7794 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7798 mutex_lock(&crtc->mutex);
7799 intel_encoder->new_crtc = to_intel_crtc(crtc);
7800 to_intel_connector(connector)->new_encoder = intel_encoder;
7802 intel_crtc = to_intel_crtc(crtc);
7803 old->dpms_mode = connector->dpms;
7804 old->load_detect_temp = true;
7805 old->release_fb = NULL;
7808 mode = &load_detect_mode;
7810 /* We need a framebuffer large enough to accommodate all accesses
7811 * that the plane may generate whilst we perform load detection.
7812 * We can not rely on the fbcon either being present (we get called
7813 * during its initialisation to detect all boot displays, or it may
7814 * not even exist) or that it is large enough to satisfy the
7817 fb = mode_fits_in_fbdev(dev, mode);
7819 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7820 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7821 old->release_fb = fb;
7823 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7825 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7826 mutex_unlock(&crtc->mutex);
7830 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7831 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7832 if (old->release_fb)
7833 old->release_fb->funcs->destroy(old->release_fb);
7834 mutex_unlock(&crtc->mutex);
7838 /* let the connector get through one full cycle before testing */
7839 intel_wait_for_vblank(dev, intel_crtc->pipe);
7843 void intel_release_load_detect_pipe(struct drm_connector *connector,
7844 struct intel_load_detect_pipe *old)
7846 struct intel_encoder *intel_encoder =
7847 intel_attached_encoder(connector);
7848 struct drm_encoder *encoder = &intel_encoder->base;
7849 struct drm_crtc *crtc = encoder->crtc;
7851 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7852 connector->base.id, drm_get_connector_name(connector),
7853 encoder->base.id, drm_get_encoder_name(encoder));
7855 if (old->load_detect_temp) {
7856 to_intel_connector(connector)->new_encoder = NULL;
7857 intel_encoder->new_crtc = NULL;
7858 intel_set_mode(crtc, NULL, 0, 0, NULL);
7860 if (old->release_fb) {
7861 drm_framebuffer_unregister_private(old->release_fb);
7862 drm_framebuffer_unreference(old->release_fb);
7865 mutex_unlock(&crtc->mutex);
7869 /* Switch crtc and encoder back off if necessary */
7870 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7871 connector->funcs->dpms(connector, old->dpms_mode);
7873 mutex_unlock(&crtc->mutex);
7876 static int i9xx_pll_refclk(struct drm_device *dev,
7877 const struct intel_crtc_config *pipe_config)
7879 struct drm_i915_private *dev_priv = dev->dev_private;
7880 u32 dpll = pipe_config->dpll_hw_state.dpll;
7882 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7883 return dev_priv->vbt.lvds_ssc_freq * 1000;
7884 else if (HAS_PCH_SPLIT(dev))
7886 else if (!IS_GEN2(dev))
7892 /* Returns the clock of the currently programmed mode of the given pipe. */
7893 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7894 struct intel_crtc_config *pipe_config)
7896 struct drm_device *dev = crtc->base.dev;
7897 struct drm_i915_private *dev_priv = dev->dev_private;
7898 int pipe = pipe_config->cpu_transcoder;
7899 u32 dpll = pipe_config->dpll_hw_state.dpll;
7901 intel_clock_t clock;
7902 int refclk = i9xx_pll_refclk(dev, pipe_config);
7904 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7905 fp = pipe_config->dpll_hw_state.fp0;
7907 fp = pipe_config->dpll_hw_state.fp1;
7909 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7910 if (IS_PINEVIEW(dev)) {
7911 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7912 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7914 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7915 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7918 if (!IS_GEN2(dev)) {
7919 if (IS_PINEVIEW(dev))
7920 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7921 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7923 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7924 DPLL_FPA01_P1_POST_DIV_SHIFT);
7926 switch (dpll & DPLL_MODE_MASK) {
7927 case DPLLB_MODE_DAC_SERIAL:
7928 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7931 case DPLLB_MODE_LVDS:
7932 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7936 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7937 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7941 if (IS_PINEVIEW(dev))
7942 pineview_clock(refclk, &clock);
7944 i9xx_clock(refclk, &clock);
7946 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7949 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7950 DPLL_FPA01_P1_POST_DIV_SHIFT);
7953 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7956 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7957 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7959 if (dpll & PLL_P2_DIVIDE_BY_4)
7965 i9xx_clock(refclk, &clock);
7969 * This value includes pixel_multiplier. We will use
7970 * port_clock to compute adjusted_mode.crtc_clock in the
7971 * encoder's get_config() function.
7973 pipe_config->port_clock = clock.dot;
7976 int intel_dotclock_calculate(int link_freq,
7977 const struct intel_link_m_n *m_n)
7980 * The calculation for the data clock is:
7981 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7982 * But we want to avoid losing precison if possible, so:
7983 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7985 * and the link clock is simpler:
7986 * link_clock = (m * link_clock) / n
7992 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7995 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7996 struct intel_crtc_config *pipe_config)
7998 struct drm_device *dev = crtc->base.dev;
8000 /* read out port_clock from the DPLL */
8001 i9xx_crtc_clock_get(crtc, pipe_config);
8004 * This value does not include pixel_multiplier.
8005 * We will check that port_clock and adjusted_mode.crtc_clock
8006 * agree once we know their relationship in the encoder's
8007 * get_config() function.
8009 pipe_config->adjusted_mode.crtc_clock =
8010 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8011 &pipe_config->fdi_m_n);
8014 /** Returns the currently programmed mode of the given pipe. */
8015 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8016 struct drm_crtc *crtc)
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8020 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8021 struct drm_display_mode *mode;
8022 struct intel_crtc_config pipe_config;
8023 int htot = I915_READ(HTOTAL(cpu_transcoder));
8024 int hsync = I915_READ(HSYNC(cpu_transcoder));
8025 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8026 int vsync = I915_READ(VSYNC(cpu_transcoder));
8027 enum pipe pipe = intel_crtc->pipe;
8029 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8034 * Construct a pipe_config sufficient for getting the clock info
8035 * back out of crtc_clock_get.
8037 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8038 * to use a real value here instead.
8040 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8041 pipe_config.pixel_multiplier = 1;
8042 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8043 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8044 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8045 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8047 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8048 mode->hdisplay = (htot & 0xffff) + 1;
8049 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8050 mode->hsync_start = (hsync & 0xffff) + 1;
8051 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8052 mode->vdisplay = (vtot & 0xffff) + 1;
8053 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8054 mode->vsync_start = (vsync & 0xffff) + 1;
8055 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8057 drm_mode_set_name(mode);
8062 static void intel_increase_pllclock(struct drm_crtc *crtc)
8064 struct drm_device *dev = crtc->dev;
8065 drm_i915_private_t *dev_priv = dev->dev_private;
8066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8067 int pipe = intel_crtc->pipe;
8068 int dpll_reg = DPLL(pipe);
8071 if (HAS_PCH_SPLIT(dev))
8074 if (!dev_priv->lvds_downclock_avail)
8077 dpll = I915_READ(dpll_reg);
8078 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8079 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8081 assert_panel_unlocked(dev_priv, pipe);
8083 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8084 I915_WRITE(dpll_reg, dpll);
8085 intel_wait_for_vblank(dev, pipe);
8087 dpll = I915_READ(dpll_reg);
8088 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8089 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8093 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8095 struct drm_device *dev = crtc->dev;
8096 drm_i915_private_t *dev_priv = dev->dev_private;
8097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8099 if (HAS_PCH_SPLIT(dev))
8102 if (!dev_priv->lvds_downclock_avail)
8106 * Since this is called by a timer, we should never get here in
8109 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8110 int pipe = intel_crtc->pipe;
8111 int dpll_reg = DPLL(pipe);
8114 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8116 assert_panel_unlocked(dev_priv, pipe);
8118 dpll = I915_READ(dpll_reg);
8119 dpll |= DISPLAY_RATE_SELECT_FPA1;
8120 I915_WRITE(dpll_reg, dpll);
8121 intel_wait_for_vblank(dev, pipe);
8122 dpll = I915_READ(dpll_reg);
8123 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8124 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8129 void intel_mark_busy(struct drm_device *dev)
8131 struct drm_i915_private *dev_priv = dev->dev_private;
8133 hsw_package_c8_gpu_busy(dev_priv);
8134 i915_update_gfx_val(dev_priv);
8137 void intel_mark_idle(struct drm_device *dev)
8139 struct drm_i915_private *dev_priv = dev->dev_private;
8140 struct drm_crtc *crtc;
8142 hsw_package_c8_gpu_idle(dev_priv);
8144 if (!i915_powersave)
8147 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8151 intel_decrease_pllclock(crtc);
8154 if (dev_priv->info->gen >= 6)
8155 gen6_rps_idle(dev->dev_private);
8158 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8159 struct intel_ring_buffer *ring)
8161 struct drm_device *dev = obj->base.dev;
8162 struct drm_crtc *crtc;
8164 if (!i915_powersave)
8167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8171 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8174 intel_increase_pllclock(crtc);
8175 if (ring && intel_fbc_enabled(dev))
8176 ring->fbc_dirty = true;
8180 static void intel_crtc_destroy(struct drm_crtc *crtc)
8182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8183 struct drm_device *dev = crtc->dev;
8184 struct intel_unpin_work *work;
8185 unsigned long flags;
8187 spin_lock_irqsave(&dev->event_lock, flags);
8188 work = intel_crtc->unpin_work;
8189 intel_crtc->unpin_work = NULL;
8190 spin_unlock_irqrestore(&dev->event_lock, flags);
8193 cancel_work_sync(&work->work);
8197 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8199 drm_crtc_cleanup(crtc);
8204 static void intel_unpin_work_fn(struct work_struct *__work)
8206 struct intel_unpin_work *work =
8207 container_of(__work, struct intel_unpin_work, work);
8208 struct drm_device *dev = work->crtc->dev;
8210 mutex_lock(&dev->struct_mutex);
8211 intel_unpin_fb_obj(work->old_fb_obj);
8212 drm_gem_object_unreference(&work->pending_flip_obj->base);
8213 drm_gem_object_unreference(&work->old_fb_obj->base);
8215 intel_update_fbc(dev);
8216 mutex_unlock(&dev->struct_mutex);
8218 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8219 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8224 static void do_intel_finish_page_flip(struct drm_device *dev,
8225 struct drm_crtc *crtc)
8227 drm_i915_private_t *dev_priv = dev->dev_private;
8228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8229 struct intel_unpin_work *work;
8230 unsigned long flags;
8232 /* Ignore early vblank irqs */
8233 if (intel_crtc == NULL)
8236 spin_lock_irqsave(&dev->event_lock, flags);
8237 work = intel_crtc->unpin_work;
8239 /* Ensure we don't miss a work->pending update ... */
8242 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8243 spin_unlock_irqrestore(&dev->event_lock, flags);
8247 /* and that the unpin work is consistent wrt ->pending. */
8250 intel_crtc->unpin_work = NULL;
8253 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8255 drm_vblank_put(dev, intel_crtc->pipe);
8257 spin_unlock_irqrestore(&dev->event_lock, flags);
8259 wake_up_all(&dev_priv->pending_flip_queue);
8261 queue_work(dev_priv->wq, &work->work);
8263 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8266 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8268 drm_i915_private_t *dev_priv = dev->dev_private;
8269 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8271 do_intel_finish_page_flip(dev, crtc);
8274 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8276 drm_i915_private_t *dev_priv = dev->dev_private;
8277 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8279 do_intel_finish_page_flip(dev, crtc);
8282 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8284 drm_i915_private_t *dev_priv = dev->dev_private;
8285 struct intel_crtc *intel_crtc =
8286 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8287 unsigned long flags;
8289 /* NB: An MMIO update of the plane base pointer will also
8290 * generate a page-flip completion irq, i.e. every modeset
8291 * is also accompanied by a spurious intel_prepare_page_flip().
8293 spin_lock_irqsave(&dev->event_lock, flags);
8294 if (intel_crtc->unpin_work)
8295 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8296 spin_unlock_irqrestore(&dev->event_lock, flags);
8299 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8301 /* Ensure that the work item is consistent when activating it ... */
8303 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8304 /* and that it is marked active as soon as the irq could fire. */
8308 static int intel_gen2_queue_flip(struct drm_device *dev,
8309 struct drm_crtc *crtc,
8310 struct drm_framebuffer *fb,
8311 struct drm_i915_gem_object *obj,
8314 struct drm_i915_private *dev_priv = dev->dev_private;
8315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8317 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8320 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8324 ret = intel_ring_begin(ring, 6);
8328 /* Can't queue multiple flips, so wait for the previous
8329 * one to finish before executing the next.
8331 if (intel_crtc->plane)
8332 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8334 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8335 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8336 intel_ring_emit(ring, MI_NOOP);
8337 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8338 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8339 intel_ring_emit(ring, fb->pitches[0]);
8340 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8341 intel_ring_emit(ring, 0); /* aux display base address, unused */
8343 intel_mark_page_flip_active(intel_crtc);
8344 __intel_ring_advance(ring);
8348 intel_unpin_fb_obj(obj);
8353 static int intel_gen3_queue_flip(struct drm_device *dev,
8354 struct drm_crtc *crtc,
8355 struct drm_framebuffer *fb,
8356 struct drm_i915_gem_object *obj,
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8362 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8365 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8369 ret = intel_ring_begin(ring, 6);
8373 if (intel_crtc->plane)
8374 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8376 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8377 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8378 intel_ring_emit(ring, MI_NOOP);
8379 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8380 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8381 intel_ring_emit(ring, fb->pitches[0]);
8382 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8383 intel_ring_emit(ring, MI_NOOP);
8385 intel_mark_page_flip_active(intel_crtc);
8386 __intel_ring_advance(ring);
8390 intel_unpin_fb_obj(obj);
8395 static int intel_gen4_queue_flip(struct drm_device *dev,
8396 struct drm_crtc *crtc,
8397 struct drm_framebuffer *fb,
8398 struct drm_i915_gem_object *obj,
8401 struct drm_i915_private *dev_priv = dev->dev_private;
8402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8403 uint32_t pf, pipesrc;
8404 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8407 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8411 ret = intel_ring_begin(ring, 4);
8415 /* i965+ uses the linear or tiled offsets from the
8416 * Display Registers (which do not change across a page-flip)
8417 * so we need only reprogram the base address.
8419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8421 intel_ring_emit(ring, fb->pitches[0]);
8422 intel_ring_emit(ring,
8423 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8426 /* XXX Enabling the panel-fitter across page-flip is so far
8427 * untested on non-native modes, so ignore it for now.
8428 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8431 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8432 intel_ring_emit(ring, pf | pipesrc);
8434 intel_mark_page_flip_active(intel_crtc);
8435 __intel_ring_advance(ring);
8439 intel_unpin_fb_obj(obj);
8444 static int intel_gen6_queue_flip(struct drm_device *dev,
8445 struct drm_crtc *crtc,
8446 struct drm_framebuffer *fb,
8447 struct drm_i915_gem_object *obj,
8450 struct drm_i915_private *dev_priv = dev->dev_private;
8451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8452 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8453 uint32_t pf, pipesrc;
8456 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8460 ret = intel_ring_begin(ring, 4);
8464 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8465 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8466 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8467 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8469 /* Contrary to the suggestions in the documentation,
8470 * "Enable Panel Fitter" does not seem to be required when page
8471 * flipping with a non-native mode, and worse causes a normal
8473 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8476 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8477 intel_ring_emit(ring, pf | pipesrc);
8479 intel_mark_page_flip_active(intel_crtc);
8480 __intel_ring_advance(ring);
8484 intel_unpin_fb_obj(obj);
8489 static int intel_gen7_queue_flip(struct drm_device *dev,
8490 struct drm_crtc *crtc,
8491 struct drm_framebuffer *fb,
8492 struct drm_i915_gem_object *obj,
8495 struct drm_i915_private *dev_priv = dev->dev_private;
8496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8497 struct intel_ring_buffer *ring;
8498 uint32_t plane_bit = 0;
8502 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8503 ring = &dev_priv->ring[BCS];
8505 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8509 switch(intel_crtc->plane) {
8511 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8514 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8517 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8520 WARN_ONCE(1, "unknown plane in flip command\n");
8526 if (ring->id == RCS)
8529 ret = intel_ring_begin(ring, len);
8533 /* Unmask the flip-done completion message. Note that the bspec says that
8534 * we should do this for both the BCS and RCS, and that we must not unmask
8535 * more than one flip event at any time (or ensure that one flip message
8536 * can be sent by waiting for flip-done prior to queueing new flips).
8537 * Experimentation says that BCS works despite DERRMR masking all
8538 * flip-done completion events and that unmasking all planes at once
8539 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8540 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8542 if (ring->id == RCS) {
8543 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8544 intel_ring_emit(ring, DERRMR);
8545 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8546 DERRMR_PIPEB_PRI_FLIP_DONE |
8547 DERRMR_PIPEC_PRI_FLIP_DONE));
8548 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8549 intel_ring_emit(ring, DERRMR);
8550 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8553 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8554 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8555 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8556 intel_ring_emit(ring, (MI_NOOP));
8558 intel_mark_page_flip_active(intel_crtc);
8559 __intel_ring_advance(ring);
8563 intel_unpin_fb_obj(obj);
8568 static int intel_default_queue_flip(struct drm_device *dev,
8569 struct drm_crtc *crtc,
8570 struct drm_framebuffer *fb,
8571 struct drm_i915_gem_object *obj,
8577 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8578 struct drm_framebuffer *fb,
8579 struct drm_pending_vblank_event *event,
8580 uint32_t page_flip_flags)
8582 struct drm_device *dev = crtc->dev;
8583 struct drm_i915_private *dev_priv = dev->dev_private;
8584 struct drm_framebuffer *old_fb = crtc->fb;
8585 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8587 struct intel_unpin_work *work;
8588 unsigned long flags;
8591 /* Can't change pixel format via MI display flips. */
8592 if (fb->pixel_format != crtc->fb->pixel_format)
8596 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8597 * Note that pitch changes could also affect these register.
8599 if (INTEL_INFO(dev)->gen > 3 &&
8600 (fb->offsets[0] != crtc->fb->offsets[0] ||
8601 fb->pitches[0] != crtc->fb->pitches[0]))
8604 work = kzalloc(sizeof(*work), GFP_KERNEL);
8608 work->event = event;
8610 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8611 INIT_WORK(&work->work, intel_unpin_work_fn);
8613 ret = drm_vblank_get(dev, intel_crtc->pipe);
8617 /* We borrow the event spin lock for protecting unpin_work */
8618 spin_lock_irqsave(&dev->event_lock, flags);
8619 if (intel_crtc->unpin_work) {
8620 spin_unlock_irqrestore(&dev->event_lock, flags);
8622 drm_vblank_put(dev, intel_crtc->pipe);
8624 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8627 intel_crtc->unpin_work = work;
8628 spin_unlock_irqrestore(&dev->event_lock, flags);
8630 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8631 flush_workqueue(dev_priv->wq);
8633 ret = i915_mutex_lock_interruptible(dev);
8637 /* Reference the objects for the scheduled work. */
8638 drm_gem_object_reference(&work->old_fb_obj->base);
8639 drm_gem_object_reference(&obj->base);
8643 work->pending_flip_obj = obj;
8645 work->enable_stall_check = true;
8647 atomic_inc(&intel_crtc->unpin_work_count);
8648 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8650 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8652 goto cleanup_pending;
8654 intel_disable_fbc(dev);
8655 intel_mark_fb_busy(obj, NULL);
8656 mutex_unlock(&dev->struct_mutex);
8658 trace_i915_flip_request(intel_crtc->plane, obj);
8663 atomic_dec(&intel_crtc->unpin_work_count);
8665 drm_gem_object_unreference(&work->old_fb_obj->base);
8666 drm_gem_object_unreference(&obj->base);
8667 mutex_unlock(&dev->struct_mutex);
8670 spin_lock_irqsave(&dev->event_lock, flags);
8671 intel_crtc->unpin_work = NULL;
8672 spin_unlock_irqrestore(&dev->event_lock, flags);
8674 drm_vblank_put(dev, intel_crtc->pipe);
8681 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8682 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8683 .load_lut = intel_crtc_load_lut,
8686 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8687 struct drm_crtc *crtc)
8689 struct drm_device *dev;
8690 struct drm_crtc *tmp;
8693 WARN(!crtc, "checking null crtc?\n");
8697 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8703 if (encoder->possible_crtcs & crtc_mask)
8709 * intel_modeset_update_staged_output_state
8711 * Updates the staged output configuration state, e.g. after we've read out the
8714 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8716 struct intel_encoder *encoder;
8717 struct intel_connector *connector;
8719 list_for_each_entry(connector, &dev->mode_config.connector_list,
8721 connector->new_encoder =
8722 to_intel_encoder(connector->base.encoder);
8725 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8728 to_intel_crtc(encoder->base.crtc);
8733 * intel_modeset_commit_output_state
8735 * This function copies the stage display pipe configuration to the real one.
8737 static void intel_modeset_commit_output_state(struct drm_device *dev)
8739 struct intel_encoder *encoder;
8740 struct intel_connector *connector;
8742 list_for_each_entry(connector, &dev->mode_config.connector_list,
8744 connector->base.encoder = &connector->new_encoder->base;
8747 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8749 encoder->base.crtc = &encoder->new_crtc->base;
8754 connected_sink_compute_bpp(struct intel_connector * connector,
8755 struct intel_crtc_config *pipe_config)
8757 int bpp = pipe_config->pipe_bpp;
8759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8760 connector->base.base.id,
8761 drm_get_connector_name(&connector->base));
8763 /* Don't use an invalid EDID bpc value */
8764 if (connector->base.display_info.bpc &&
8765 connector->base.display_info.bpc * 3 < bpp) {
8766 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8767 bpp, connector->base.display_info.bpc*3);
8768 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8771 /* Clamp bpp to 8 on screens without EDID 1.4 */
8772 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8773 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8775 pipe_config->pipe_bpp = 24;
8780 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8781 struct drm_framebuffer *fb,
8782 struct intel_crtc_config *pipe_config)
8784 struct drm_device *dev = crtc->base.dev;
8785 struct intel_connector *connector;
8788 switch (fb->pixel_format) {
8790 bpp = 8*3; /* since we go through a colormap */
8792 case DRM_FORMAT_XRGB1555:
8793 case DRM_FORMAT_ARGB1555:
8794 /* checked in intel_framebuffer_init already */
8795 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8797 case DRM_FORMAT_RGB565:
8798 bpp = 6*3; /* min is 18bpp */
8800 case DRM_FORMAT_XBGR8888:
8801 case DRM_FORMAT_ABGR8888:
8802 /* checked in intel_framebuffer_init already */
8803 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8805 case DRM_FORMAT_XRGB8888:
8806 case DRM_FORMAT_ARGB8888:
8809 case DRM_FORMAT_XRGB2101010:
8810 case DRM_FORMAT_ARGB2101010:
8811 case DRM_FORMAT_XBGR2101010:
8812 case DRM_FORMAT_ABGR2101010:
8813 /* checked in intel_framebuffer_init already */
8814 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8818 /* TODO: gen4+ supports 16 bpc floating point, too. */
8820 DRM_DEBUG_KMS("unsupported depth\n");
8824 pipe_config->pipe_bpp = bpp;
8826 /* Clamp display bpp to EDID value */
8827 list_for_each_entry(connector, &dev->mode_config.connector_list,
8829 if (!connector->new_encoder ||
8830 connector->new_encoder->new_crtc != crtc)
8833 connected_sink_compute_bpp(connector, pipe_config);
8839 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8841 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8842 "type: 0x%x flags: 0x%x\n",
8844 mode->crtc_hdisplay, mode->crtc_hsync_start,
8845 mode->crtc_hsync_end, mode->crtc_htotal,
8846 mode->crtc_vdisplay, mode->crtc_vsync_start,
8847 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8850 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8851 struct intel_crtc_config *pipe_config,
8852 const char *context)
8854 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8855 context, pipe_name(crtc->pipe));
8857 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8858 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8859 pipe_config->pipe_bpp, pipe_config->dither);
8860 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8861 pipe_config->has_pch_encoder,
8862 pipe_config->fdi_lanes,
8863 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8864 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8865 pipe_config->fdi_m_n.tu);
8866 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8867 pipe_config->has_dp_encoder,
8868 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8869 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8870 pipe_config->dp_m_n.tu);
8871 DRM_DEBUG_KMS("requested mode:\n");
8872 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8873 DRM_DEBUG_KMS("adjusted mode:\n");
8874 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8875 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8876 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8877 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8878 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8879 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8880 pipe_config->gmch_pfit.control,
8881 pipe_config->gmch_pfit.pgm_ratios,
8882 pipe_config->gmch_pfit.lvds_border_bits);
8883 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8884 pipe_config->pch_pfit.pos,
8885 pipe_config->pch_pfit.size,
8886 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8887 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8888 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8891 static bool check_encoder_cloning(struct drm_crtc *crtc)
8893 int num_encoders = 0;
8894 bool uncloneable_encoders = false;
8895 struct intel_encoder *encoder;
8897 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8899 if (&encoder->new_crtc->base != crtc)
8903 if (!encoder->cloneable)
8904 uncloneable_encoders = true;
8907 return !(num_encoders > 1 && uncloneable_encoders);
8910 static struct intel_crtc_config *
8911 intel_modeset_pipe_config(struct drm_crtc *crtc,
8912 struct drm_framebuffer *fb,
8913 struct drm_display_mode *mode)
8915 struct drm_device *dev = crtc->dev;
8916 struct intel_encoder *encoder;
8917 struct intel_crtc_config *pipe_config;
8918 int plane_bpp, ret = -EINVAL;
8921 if (!check_encoder_cloning(crtc)) {
8922 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8923 return ERR_PTR(-EINVAL);
8926 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8928 return ERR_PTR(-ENOMEM);
8930 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8931 drm_mode_copy(&pipe_config->requested_mode, mode);
8933 pipe_config->cpu_transcoder =
8934 (enum transcoder) to_intel_crtc(crtc)->pipe;
8935 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8938 * Sanitize sync polarity flags based on requested ones. If neither
8939 * positive or negative polarity is requested, treat this as meaning
8940 * negative polarity.
8942 if (!(pipe_config->adjusted_mode.flags &
8943 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8944 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8946 if (!(pipe_config->adjusted_mode.flags &
8947 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8948 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8950 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8951 * plane pixel format and any sink constraints into account. Returns the
8952 * source plane bpp so that dithering can be selected on mismatches
8953 * after encoders and crtc also have had their say. */
8954 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8960 * Determine the real pipe dimensions. Note that stereo modes can
8961 * increase the actual pipe size due to the frame doubling and
8962 * insertion of additional space for blanks between the frame. This
8963 * is stored in the crtc timings. We use the requested mode to do this
8964 * computation to clearly distinguish it from the adjusted mode, which
8965 * can be changed by the connectors in the below retry loop.
8967 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8968 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8969 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8972 /* Ensure the port clock defaults are reset when retrying. */
8973 pipe_config->port_clock = 0;
8974 pipe_config->pixel_multiplier = 1;
8976 /* Fill in default crtc timings, allow encoders to overwrite them. */
8977 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8979 /* Pass our mode to the connectors and the CRTC to give them a chance to
8980 * adjust it according to limitations or connector properties, and also
8981 * a chance to reject the mode entirely.
8983 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8986 if (&encoder->new_crtc->base != crtc)
8989 if (!(encoder->compute_config(encoder, pipe_config))) {
8990 DRM_DEBUG_KMS("Encoder config failure\n");
8995 /* Set default port clock if not overwritten by the encoder. Needs to be
8996 * done afterwards in case the encoder adjusts the mode. */
8997 if (!pipe_config->port_clock)
8998 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8999 * pipe_config->pixel_multiplier;
9001 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9003 DRM_DEBUG_KMS("CRTC fixup failed\n");
9008 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9013 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9018 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9019 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9020 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9025 return ERR_PTR(ret);
9028 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9029 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9031 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9032 unsigned *prepare_pipes, unsigned *disable_pipes)
9034 struct intel_crtc *intel_crtc;
9035 struct drm_device *dev = crtc->dev;
9036 struct intel_encoder *encoder;
9037 struct intel_connector *connector;
9038 struct drm_crtc *tmp_crtc;
9040 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9042 /* Check which crtcs have changed outputs connected to them, these need
9043 * to be part of the prepare_pipes mask. We don't (yet) support global
9044 * modeset across multiple crtcs, so modeset_pipes will only have one
9045 * bit set at most. */
9046 list_for_each_entry(connector, &dev->mode_config.connector_list,
9048 if (connector->base.encoder == &connector->new_encoder->base)
9051 if (connector->base.encoder) {
9052 tmp_crtc = connector->base.encoder->crtc;
9054 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9057 if (connector->new_encoder)
9059 1 << connector->new_encoder->new_crtc->pipe;
9062 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9064 if (encoder->base.crtc == &encoder->new_crtc->base)
9067 if (encoder->base.crtc) {
9068 tmp_crtc = encoder->base.crtc;
9070 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9073 if (encoder->new_crtc)
9074 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9077 /* Check for any pipes that will be fully disabled ... */
9078 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9082 /* Don't try to disable disabled crtcs. */
9083 if (!intel_crtc->base.enabled)
9086 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9088 if (encoder->new_crtc == intel_crtc)
9093 *disable_pipes |= 1 << intel_crtc->pipe;
9097 /* set_mode is also used to update properties on life display pipes. */
9098 intel_crtc = to_intel_crtc(crtc);
9100 *prepare_pipes |= 1 << intel_crtc->pipe;
9103 * For simplicity do a full modeset on any pipe where the output routing
9104 * changed. We could be more clever, but that would require us to be
9105 * more careful with calling the relevant encoder->mode_set functions.
9108 *modeset_pipes = *prepare_pipes;
9110 /* ... and mask these out. */
9111 *modeset_pipes &= ~(*disable_pipes);
9112 *prepare_pipes &= ~(*disable_pipes);
9115 * HACK: We don't (yet) fully support global modesets. intel_set_config
9116 * obies this rule, but the modeset restore mode of
9117 * intel_modeset_setup_hw_state does not.
9119 *modeset_pipes &= 1 << intel_crtc->pipe;
9120 *prepare_pipes &= 1 << intel_crtc->pipe;
9122 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9123 *modeset_pipes, *prepare_pipes, *disable_pipes);
9126 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9128 struct drm_encoder *encoder;
9129 struct drm_device *dev = crtc->dev;
9131 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9132 if (encoder->crtc == crtc)
9139 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9141 struct intel_encoder *intel_encoder;
9142 struct intel_crtc *intel_crtc;
9143 struct drm_connector *connector;
9145 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9147 if (!intel_encoder->base.crtc)
9150 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9152 if (prepare_pipes & (1 << intel_crtc->pipe))
9153 intel_encoder->connectors_active = false;
9156 intel_modeset_commit_output_state(dev);
9158 /* Update computed state. */
9159 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9161 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9164 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9165 if (!connector->encoder || !connector->encoder->crtc)
9168 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9170 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9171 struct drm_property *dpms_property =
9172 dev->mode_config.dpms_property;
9174 connector->dpms = DRM_MODE_DPMS_ON;
9175 drm_object_property_set_value(&connector->base,
9179 intel_encoder = to_intel_encoder(connector->encoder);
9180 intel_encoder->connectors_active = true;
9186 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9190 if (clock1 == clock2)
9193 if (!clock1 || !clock2)
9196 diff = abs(clock1 - clock2);
9198 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9204 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9205 list_for_each_entry((intel_crtc), \
9206 &(dev)->mode_config.crtc_list, \
9208 if (mask & (1 <<(intel_crtc)->pipe))
9211 intel_pipe_config_compare(struct drm_device *dev,
9212 struct intel_crtc_config *current_config,
9213 struct intel_crtc_config *pipe_config)
9215 #define PIPE_CONF_CHECK_X(name) \
9216 if (current_config->name != pipe_config->name) { \
9217 DRM_ERROR("mismatch in " #name " " \
9218 "(expected 0x%08x, found 0x%08x)\n", \
9219 current_config->name, \
9220 pipe_config->name); \
9224 #define PIPE_CONF_CHECK_I(name) \
9225 if (current_config->name != pipe_config->name) { \
9226 DRM_ERROR("mismatch in " #name " " \
9227 "(expected %i, found %i)\n", \
9228 current_config->name, \
9229 pipe_config->name); \
9233 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9234 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9235 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9236 "(expected %i, found %i)\n", \
9237 current_config->name & (mask), \
9238 pipe_config->name & (mask)); \
9242 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9243 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9244 DRM_ERROR("mismatch in " #name " " \
9245 "(expected %i, found %i)\n", \
9246 current_config->name, \
9247 pipe_config->name); \
9251 #define PIPE_CONF_QUIRK(quirk) \
9252 ((current_config->quirks | pipe_config->quirks) & (quirk))
9254 PIPE_CONF_CHECK_I(cpu_transcoder);
9256 PIPE_CONF_CHECK_I(has_pch_encoder);
9257 PIPE_CONF_CHECK_I(fdi_lanes);
9258 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9259 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9260 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9261 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9262 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9264 PIPE_CONF_CHECK_I(has_dp_encoder);
9265 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9266 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9267 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9268 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9269 PIPE_CONF_CHECK_I(dp_m_n.tu);
9271 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9272 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9273 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9274 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9275 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9276 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9278 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9279 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9280 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9281 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9282 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9283 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9285 PIPE_CONF_CHECK_I(pixel_multiplier);
9287 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9288 DRM_MODE_FLAG_INTERLACE);
9290 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9291 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9292 DRM_MODE_FLAG_PHSYNC);
9293 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9294 DRM_MODE_FLAG_NHSYNC);
9295 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9296 DRM_MODE_FLAG_PVSYNC);
9297 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9298 DRM_MODE_FLAG_NVSYNC);
9301 PIPE_CONF_CHECK_I(pipe_src_w);
9302 PIPE_CONF_CHECK_I(pipe_src_h);
9304 PIPE_CONF_CHECK_I(gmch_pfit.control);
9305 /* pfit ratios are autocomputed by the hw on gen4+ */
9306 if (INTEL_INFO(dev)->gen < 4)
9307 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9308 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9309 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9310 if (current_config->pch_pfit.enabled) {
9311 PIPE_CONF_CHECK_I(pch_pfit.pos);
9312 PIPE_CONF_CHECK_I(pch_pfit.size);
9315 PIPE_CONF_CHECK_I(ips_enabled);
9317 PIPE_CONF_CHECK_I(double_wide);
9319 PIPE_CONF_CHECK_I(shared_dpll);
9320 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9321 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9322 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9323 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9325 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9326 PIPE_CONF_CHECK_I(pipe_bpp);
9328 if (!IS_HASWELL(dev)) {
9329 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9330 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9333 #undef PIPE_CONF_CHECK_X
9334 #undef PIPE_CONF_CHECK_I
9335 #undef PIPE_CONF_CHECK_FLAGS
9336 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9337 #undef PIPE_CONF_QUIRK
9343 check_connector_state(struct drm_device *dev)
9345 struct intel_connector *connector;
9347 list_for_each_entry(connector, &dev->mode_config.connector_list,
9349 /* This also checks the encoder/connector hw state with the
9350 * ->get_hw_state callbacks. */
9351 intel_connector_check_state(connector);
9353 WARN(&connector->new_encoder->base != connector->base.encoder,
9354 "connector's staged encoder doesn't match current encoder\n");
9359 check_encoder_state(struct drm_device *dev)
9361 struct intel_encoder *encoder;
9362 struct intel_connector *connector;
9364 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9366 bool enabled = false;
9367 bool active = false;
9368 enum pipe pipe, tracked_pipe;
9370 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9371 encoder->base.base.id,
9372 drm_get_encoder_name(&encoder->base));
9374 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9375 "encoder's stage crtc doesn't match current crtc\n");
9376 WARN(encoder->connectors_active && !encoder->base.crtc,
9377 "encoder's active_connectors set, but no crtc\n");
9379 list_for_each_entry(connector, &dev->mode_config.connector_list,
9381 if (connector->base.encoder != &encoder->base)
9384 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9387 WARN(!!encoder->base.crtc != enabled,
9388 "encoder's enabled state mismatch "
9389 "(expected %i, found %i)\n",
9390 !!encoder->base.crtc, enabled);
9391 WARN(active && !encoder->base.crtc,
9392 "active encoder with no crtc\n");
9394 WARN(encoder->connectors_active != active,
9395 "encoder's computed active state doesn't match tracked active state "
9396 "(expected %i, found %i)\n", active, encoder->connectors_active);
9398 active = encoder->get_hw_state(encoder, &pipe);
9399 WARN(active != encoder->connectors_active,
9400 "encoder's hw state doesn't match sw tracking "
9401 "(expected %i, found %i)\n",
9402 encoder->connectors_active, active);
9404 if (!encoder->base.crtc)
9407 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9408 WARN(active && pipe != tracked_pipe,
9409 "active encoder's pipe doesn't match"
9410 "(expected %i, found %i)\n",
9411 tracked_pipe, pipe);
9417 check_crtc_state(struct drm_device *dev)
9419 drm_i915_private_t *dev_priv = dev->dev_private;
9420 struct intel_crtc *crtc;
9421 struct intel_encoder *encoder;
9422 struct intel_crtc_config pipe_config;
9424 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9426 bool enabled = false;
9427 bool active = false;
9429 memset(&pipe_config, 0, sizeof(pipe_config));
9431 DRM_DEBUG_KMS("[CRTC:%d]\n",
9432 crtc->base.base.id);
9434 WARN(crtc->active && !crtc->base.enabled,
9435 "active crtc, but not enabled in sw tracking\n");
9437 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9439 if (encoder->base.crtc != &crtc->base)
9442 if (encoder->connectors_active)
9446 WARN(active != crtc->active,
9447 "crtc's computed active state doesn't match tracked active state "
9448 "(expected %i, found %i)\n", active, crtc->active);
9449 WARN(enabled != crtc->base.enabled,
9450 "crtc's computed enabled state doesn't match tracked enabled state "
9451 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9453 active = dev_priv->display.get_pipe_config(crtc,
9456 /* hw state is inconsistent with the pipe A quirk */
9457 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9458 active = crtc->active;
9460 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9463 if (encoder->base.crtc != &crtc->base)
9465 if (encoder->get_hw_state(encoder, &pipe))
9466 encoder->get_config(encoder, &pipe_config);
9469 WARN(crtc->active != active,
9470 "crtc active state doesn't match with hw state "
9471 "(expected %i, found %i)\n", crtc->active, active);
9474 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9475 WARN(1, "pipe state doesn't match!\n");
9476 intel_dump_pipe_config(crtc, &pipe_config,
9478 intel_dump_pipe_config(crtc, &crtc->config,
9485 check_shared_dpll_state(struct drm_device *dev)
9487 drm_i915_private_t *dev_priv = dev->dev_private;
9488 struct intel_crtc *crtc;
9489 struct intel_dpll_hw_state dpll_hw_state;
9492 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9493 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9494 int enabled_crtcs = 0, active_crtcs = 0;
9497 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9499 DRM_DEBUG_KMS("%s\n", pll->name);
9501 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9503 WARN(pll->active > pll->refcount,
9504 "more active pll users than references: %i vs %i\n",
9505 pll->active, pll->refcount);
9506 WARN(pll->active && !pll->on,
9507 "pll in active use but not on in sw tracking\n");
9508 WARN(pll->on && !pll->active,
9509 "pll in on but not on in use in sw tracking\n");
9510 WARN(pll->on != active,
9511 "pll on state mismatch (expected %i, found %i)\n",
9514 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9516 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9518 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9521 WARN(pll->active != active_crtcs,
9522 "pll active crtcs mismatch (expected %i, found %i)\n",
9523 pll->active, active_crtcs);
9524 WARN(pll->refcount != enabled_crtcs,
9525 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9526 pll->refcount, enabled_crtcs);
9528 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9529 sizeof(dpll_hw_state)),
9530 "pll hw state mismatch\n");
9535 intel_modeset_check_state(struct drm_device *dev)
9537 check_connector_state(dev);
9538 check_encoder_state(dev);
9539 check_crtc_state(dev);
9540 check_shared_dpll_state(dev);
9543 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9547 * FDI already provided one idea for the dotclock.
9548 * Yell if the encoder disagrees.
9550 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9551 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9552 pipe_config->adjusted_mode.crtc_clock, dotclock);
9555 static int __intel_set_mode(struct drm_crtc *crtc,
9556 struct drm_display_mode *mode,
9557 int x, int y, struct drm_framebuffer *fb)
9559 struct drm_device *dev = crtc->dev;
9560 drm_i915_private_t *dev_priv = dev->dev_private;
9561 struct drm_display_mode *saved_mode, *saved_hwmode;
9562 struct intel_crtc_config *pipe_config = NULL;
9563 struct intel_crtc *intel_crtc;
9564 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9567 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9570 saved_hwmode = saved_mode + 1;
9572 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9573 &prepare_pipes, &disable_pipes);
9575 *saved_hwmode = crtc->hwmode;
9576 *saved_mode = crtc->mode;
9578 /* Hack: Because we don't (yet) support global modeset on multiple
9579 * crtcs, we don't keep track of the new mode for more than one crtc.
9580 * Hence simply check whether any bit is set in modeset_pipes in all the
9581 * pieces of code that are not yet converted to deal with mutliple crtcs
9582 * changing their mode at the same time. */
9583 if (modeset_pipes) {
9584 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9585 if (IS_ERR(pipe_config)) {
9586 ret = PTR_ERR(pipe_config);
9591 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9596 * See if the config requires any additional preparation, e.g.
9597 * to adjust global state with pipes off. We need to do this
9598 * here so we can get the modeset_pipe updated config for the new
9599 * mode set on this crtc. For other crtcs we need to use the
9600 * adjusted_mode bits in the crtc directly.
9602 if (IS_VALLEYVIEW(dev)) {
9603 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9604 modeset_pipes, pipe_config);
9606 /* may have added more to prepare_pipes than we should */
9607 prepare_pipes &= ~disable_pipes;
9610 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9611 intel_crtc_disable(&intel_crtc->base);
9613 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9614 if (intel_crtc->base.enabled)
9615 dev_priv->display.crtc_disable(&intel_crtc->base);
9618 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9619 * to set it here already despite that we pass it down the callchain.
9621 if (modeset_pipes) {
9623 /* mode_set/enable/disable functions rely on a correct pipe
9625 to_intel_crtc(crtc)->config = *pipe_config;
9628 /* Only after disabling all output pipelines that will be changed can we
9629 * update the the output configuration. */
9630 intel_modeset_update_state(dev, prepare_pipes);
9632 if (dev_priv->display.modeset_global_resources)
9633 dev_priv->display.modeset_global_resources(dev);
9635 /* Set up the DPLL and any encoders state that needs to adjust or depend
9638 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9639 ret = intel_crtc_mode_set(&intel_crtc->base,
9645 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9646 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9647 dev_priv->display.crtc_enable(&intel_crtc->base);
9649 if (modeset_pipes) {
9650 /* Store real post-adjustment hardware mode. */
9651 crtc->hwmode = pipe_config->adjusted_mode;
9653 /* Calculate and store various constants which
9654 * are later needed by vblank and swap-completion
9655 * timestamping. They are derived from true hwmode.
9657 drm_calc_timestamping_constants(crtc);
9660 /* FIXME: add subpixel order */
9662 if (ret && crtc->enabled) {
9663 crtc->hwmode = *saved_hwmode;
9664 crtc->mode = *saved_mode;
9673 static int intel_set_mode(struct drm_crtc *crtc,
9674 struct drm_display_mode *mode,
9675 int x, int y, struct drm_framebuffer *fb)
9679 ret = __intel_set_mode(crtc, mode, x, y, fb);
9682 intel_modeset_check_state(crtc->dev);
9687 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9689 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9692 #undef for_each_intel_crtc_masked
9694 static void intel_set_config_free(struct intel_set_config *config)
9699 kfree(config->save_connector_encoders);
9700 kfree(config->save_encoder_crtcs);
9704 static int intel_set_config_save_state(struct drm_device *dev,
9705 struct intel_set_config *config)
9707 struct drm_encoder *encoder;
9708 struct drm_connector *connector;
9711 config->save_encoder_crtcs =
9712 kcalloc(dev->mode_config.num_encoder,
9713 sizeof(struct drm_crtc *), GFP_KERNEL);
9714 if (!config->save_encoder_crtcs)
9717 config->save_connector_encoders =
9718 kcalloc(dev->mode_config.num_connector,
9719 sizeof(struct drm_encoder *), GFP_KERNEL);
9720 if (!config->save_connector_encoders)
9723 /* Copy data. Note that driver private data is not affected.
9724 * Should anything bad happen only the expected state is
9725 * restored, not the drivers personal bookkeeping.
9728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9729 config->save_encoder_crtcs[count++] = encoder->crtc;
9733 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9734 config->save_connector_encoders[count++] = connector->encoder;
9740 static void intel_set_config_restore_state(struct drm_device *dev,
9741 struct intel_set_config *config)
9743 struct intel_encoder *encoder;
9744 struct intel_connector *connector;
9748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9750 to_intel_crtc(config->save_encoder_crtcs[count++]);
9754 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9755 connector->new_encoder =
9756 to_intel_encoder(config->save_connector_encoders[count++]);
9761 is_crtc_connector_off(struct drm_mode_set *set)
9765 if (set->num_connectors == 0)
9768 if (WARN_ON(set->connectors == NULL))
9771 for (i = 0; i < set->num_connectors; i++)
9772 if (set->connectors[i]->encoder &&
9773 set->connectors[i]->encoder->crtc == set->crtc &&
9774 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9781 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9782 struct intel_set_config *config)
9785 /* We should be able to check here if the fb has the same properties
9786 * and then just flip_or_move it */
9787 if (is_crtc_connector_off(set)) {
9788 config->mode_changed = true;
9789 } else if (set->crtc->fb != set->fb) {
9790 /* If we have no fb then treat it as a full mode set */
9791 if (set->crtc->fb == NULL) {
9792 struct intel_crtc *intel_crtc =
9793 to_intel_crtc(set->crtc);
9795 if (intel_crtc->active && i915_fastboot) {
9796 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9797 config->fb_changed = true;
9799 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9800 config->mode_changed = true;
9802 } else if (set->fb == NULL) {
9803 config->mode_changed = true;
9804 } else if (set->fb->pixel_format !=
9805 set->crtc->fb->pixel_format) {
9806 config->mode_changed = true;
9808 config->fb_changed = true;
9812 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9813 config->fb_changed = true;
9815 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9816 DRM_DEBUG_KMS("modes are different, full mode set\n");
9817 drm_mode_debug_printmodeline(&set->crtc->mode);
9818 drm_mode_debug_printmodeline(set->mode);
9819 config->mode_changed = true;
9822 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9823 set->crtc->base.id, config->mode_changed, config->fb_changed);
9827 intel_modeset_stage_output_state(struct drm_device *dev,
9828 struct drm_mode_set *set,
9829 struct intel_set_config *config)
9831 struct drm_crtc *new_crtc;
9832 struct intel_connector *connector;
9833 struct intel_encoder *encoder;
9836 /* The upper layers ensure that we either disable a crtc or have a list
9837 * of connectors. For paranoia, double-check this. */
9838 WARN_ON(!set->fb && (set->num_connectors != 0));
9839 WARN_ON(set->fb && (set->num_connectors == 0));
9841 list_for_each_entry(connector, &dev->mode_config.connector_list,
9843 /* Otherwise traverse passed in connector list and get encoders
9845 for (ro = 0; ro < set->num_connectors; ro++) {
9846 if (set->connectors[ro] == &connector->base) {
9847 connector->new_encoder = connector->encoder;
9852 /* If we disable the crtc, disable all its connectors. Also, if
9853 * the connector is on the changing crtc but not on the new
9854 * connector list, disable it. */
9855 if ((!set->fb || ro == set->num_connectors) &&
9856 connector->base.encoder &&
9857 connector->base.encoder->crtc == set->crtc) {
9858 connector->new_encoder = NULL;
9860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9861 connector->base.base.id,
9862 drm_get_connector_name(&connector->base));
9866 if (&connector->new_encoder->base != connector->base.encoder) {
9867 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9868 config->mode_changed = true;
9871 /* connector->new_encoder is now updated for all connectors. */
9873 /* Update crtc of enabled connectors. */
9874 list_for_each_entry(connector, &dev->mode_config.connector_list,
9876 if (!connector->new_encoder)
9879 new_crtc = connector->new_encoder->base.crtc;
9881 for (ro = 0; ro < set->num_connectors; ro++) {
9882 if (set->connectors[ro] == &connector->base)
9883 new_crtc = set->crtc;
9886 /* Make sure the new CRTC will work with the encoder */
9887 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9891 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9894 connector->base.base.id,
9895 drm_get_connector_name(&connector->base),
9899 /* Check for any encoders that needs to be disabled. */
9900 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9902 list_for_each_entry(connector,
9903 &dev->mode_config.connector_list,
9905 if (connector->new_encoder == encoder) {
9906 WARN_ON(!connector->new_encoder->new_crtc);
9911 encoder->new_crtc = NULL;
9913 /* Only now check for crtc changes so we don't miss encoders
9914 * that will be disabled. */
9915 if (&encoder->new_crtc->base != encoder->base.crtc) {
9916 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9917 config->mode_changed = true;
9920 /* Now we've also updated encoder->new_crtc for all encoders. */
9925 static int intel_crtc_set_config(struct drm_mode_set *set)
9927 struct drm_device *dev;
9928 struct drm_mode_set save_set;
9929 struct intel_set_config *config;
9934 BUG_ON(!set->crtc->helper_private);
9936 /* Enforce sane interface api - has been abused by the fb helper. */
9937 BUG_ON(!set->mode && set->fb);
9938 BUG_ON(set->fb && set->num_connectors == 0);
9941 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9942 set->crtc->base.id, set->fb->base.id,
9943 (int)set->num_connectors, set->x, set->y);
9945 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9948 dev = set->crtc->dev;
9951 config = kzalloc(sizeof(*config), GFP_KERNEL);
9955 ret = intel_set_config_save_state(dev, config);
9959 save_set.crtc = set->crtc;
9960 save_set.mode = &set->crtc->mode;
9961 save_set.x = set->crtc->x;
9962 save_set.y = set->crtc->y;
9963 save_set.fb = set->crtc->fb;
9965 /* Compute whether we need a full modeset, only an fb base update or no
9966 * change at all. In the future we might also check whether only the
9967 * mode changed, e.g. for LVDS where we only change the panel fitter in
9969 intel_set_config_compute_mode_changes(set, config);
9971 ret = intel_modeset_stage_output_state(dev, set, config);
9975 if (config->mode_changed) {
9976 ret = intel_set_mode(set->crtc, set->mode,
9977 set->x, set->y, set->fb);
9978 } else if (config->fb_changed) {
9979 intel_crtc_wait_for_pending_flips(set->crtc);
9981 ret = intel_pipe_set_base(set->crtc,
9982 set->x, set->y, set->fb);
9986 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9987 set->crtc->base.id, ret);
9989 intel_set_config_restore_state(dev, config);
9991 /* Try to restore the config */
9992 if (config->mode_changed &&
9993 intel_set_mode(save_set.crtc, save_set.mode,
9994 save_set.x, save_set.y, save_set.fb))
9995 DRM_ERROR("failed to restore config after modeset failure\n");
9999 intel_set_config_free(config);
10003 static const struct drm_crtc_funcs intel_crtc_funcs = {
10004 .cursor_set = intel_crtc_cursor_set,
10005 .cursor_move = intel_crtc_cursor_move,
10006 .gamma_set = intel_crtc_gamma_set,
10007 .set_config = intel_crtc_set_config,
10008 .destroy = intel_crtc_destroy,
10009 .page_flip = intel_crtc_page_flip,
10012 static void intel_cpu_pll_init(struct drm_device *dev)
10015 intel_ddi_pll_init(dev);
10018 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10019 struct intel_shared_dpll *pll,
10020 struct intel_dpll_hw_state *hw_state)
10024 val = I915_READ(PCH_DPLL(pll->id));
10025 hw_state->dpll = val;
10026 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10027 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10029 return val & DPLL_VCO_ENABLE;
10032 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10033 struct intel_shared_dpll *pll)
10035 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10036 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10039 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10040 struct intel_shared_dpll *pll)
10042 /* PCH refclock must be enabled first */
10043 assert_pch_refclk_enabled(dev_priv);
10045 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10047 /* Wait for the clocks to stabilize. */
10048 POSTING_READ(PCH_DPLL(pll->id));
10051 /* The pixel multiplier can only be updated once the
10052 * DPLL is enabled and the clocks are stable.
10054 * So write it again.
10056 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10057 POSTING_READ(PCH_DPLL(pll->id));
10061 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10062 struct intel_shared_dpll *pll)
10064 struct drm_device *dev = dev_priv->dev;
10065 struct intel_crtc *crtc;
10067 /* Make sure no transcoder isn't still depending on us. */
10068 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10069 if (intel_crtc_to_shared_dpll(crtc) == pll)
10070 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10073 I915_WRITE(PCH_DPLL(pll->id), 0);
10074 POSTING_READ(PCH_DPLL(pll->id));
10078 static char *ibx_pch_dpll_names[] = {
10083 static void ibx_pch_dpll_init(struct drm_device *dev)
10085 struct drm_i915_private *dev_priv = dev->dev_private;
10088 dev_priv->num_shared_dpll = 2;
10090 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10091 dev_priv->shared_dplls[i].id = i;
10092 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10093 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10094 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10095 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10096 dev_priv->shared_dplls[i].get_hw_state =
10097 ibx_pch_dpll_get_hw_state;
10101 static void intel_shared_dpll_init(struct drm_device *dev)
10103 struct drm_i915_private *dev_priv = dev->dev_private;
10105 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10106 ibx_pch_dpll_init(dev);
10108 dev_priv->num_shared_dpll = 0;
10110 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10111 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10112 dev_priv->num_shared_dpll);
10115 static void intel_crtc_init(struct drm_device *dev, int pipe)
10117 drm_i915_private_t *dev_priv = dev->dev_private;
10118 struct intel_crtc *intel_crtc;
10121 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10122 if (intel_crtc == NULL)
10125 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10127 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10128 for (i = 0; i < 256; i++) {
10129 intel_crtc->lut_r[i] = i;
10130 intel_crtc->lut_g[i] = i;
10131 intel_crtc->lut_b[i] = i;
10135 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10136 * is hooked to plane B. Hence we want plane A feeding pipe B.
10138 intel_crtc->pipe = pipe;
10139 intel_crtc->plane = pipe;
10140 if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10141 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10142 intel_crtc->plane = !pipe;
10145 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10146 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10147 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10148 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10150 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10153 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10155 struct drm_encoder *encoder = connector->base.encoder;
10157 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10160 return INVALID_PIPE;
10162 return to_intel_crtc(encoder->crtc)->pipe;
10165 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10166 struct drm_file *file)
10168 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10169 struct drm_mode_object *drmmode_obj;
10170 struct intel_crtc *crtc;
10172 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10175 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10176 DRM_MODE_OBJECT_CRTC);
10178 if (!drmmode_obj) {
10179 DRM_ERROR("no such CRTC id\n");
10183 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10184 pipe_from_crtc_id->pipe = crtc->pipe;
10189 static int intel_encoder_clones(struct intel_encoder *encoder)
10191 struct drm_device *dev = encoder->base.dev;
10192 struct intel_encoder *source_encoder;
10193 int index_mask = 0;
10196 list_for_each_entry(source_encoder,
10197 &dev->mode_config.encoder_list, base.head) {
10199 if (encoder == source_encoder)
10200 index_mask |= (1 << entry);
10202 /* Intel hw has only one MUX where enocoders could be cloned. */
10203 if (encoder->cloneable && source_encoder->cloneable)
10204 index_mask |= (1 << entry);
10212 static bool has_edp_a(struct drm_device *dev)
10214 struct drm_i915_private *dev_priv = dev->dev_private;
10216 if (!IS_MOBILE(dev))
10219 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10222 if (IS_GEN5(dev) &&
10223 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10229 static void intel_setup_outputs(struct drm_device *dev)
10231 struct drm_i915_private *dev_priv = dev->dev_private;
10232 struct intel_encoder *encoder;
10233 bool dpd_is_edp = false;
10235 intel_lvds_init(dev);
10238 intel_crt_init(dev);
10240 if (HAS_DDI(dev)) {
10243 /* Haswell uses DDI functions to detect digital outputs */
10244 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10245 /* DDI A only supports eDP */
10247 intel_ddi_init(dev, PORT_A);
10249 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10251 found = I915_READ(SFUSE_STRAP);
10253 if (found & SFUSE_STRAP_DDIB_DETECTED)
10254 intel_ddi_init(dev, PORT_B);
10255 if (found & SFUSE_STRAP_DDIC_DETECTED)
10256 intel_ddi_init(dev, PORT_C);
10257 if (found & SFUSE_STRAP_DDID_DETECTED)
10258 intel_ddi_init(dev, PORT_D);
10259 } else if (HAS_PCH_SPLIT(dev)) {
10261 dpd_is_edp = intel_dpd_is_edp(dev);
10263 if (has_edp_a(dev))
10264 intel_dp_init(dev, DP_A, PORT_A);
10266 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10267 /* PCH SDVOB multiplex with HDMIB */
10268 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10270 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10271 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10272 intel_dp_init(dev, PCH_DP_B, PORT_B);
10275 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10276 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10278 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10279 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10281 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10282 intel_dp_init(dev, PCH_DP_C, PORT_C);
10284 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10285 intel_dp_init(dev, PCH_DP_D, PORT_D);
10286 } else if (IS_VALLEYVIEW(dev)) {
10287 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10288 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10290 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10291 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10294 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10295 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10297 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10298 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10302 intel_dsi_init(dev);
10303 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10304 bool found = false;
10306 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10307 DRM_DEBUG_KMS("probing SDVOB\n");
10308 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10309 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10310 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10311 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10314 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10315 intel_dp_init(dev, DP_B, PORT_B);
10318 /* Before G4X SDVOC doesn't have its own detect register */
10320 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10321 DRM_DEBUG_KMS("probing SDVOC\n");
10322 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10325 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10327 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10328 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10329 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10331 if (SUPPORTS_INTEGRATED_DP(dev))
10332 intel_dp_init(dev, DP_C, PORT_C);
10335 if (SUPPORTS_INTEGRATED_DP(dev) &&
10336 (I915_READ(DP_D) & DP_DETECTED))
10337 intel_dp_init(dev, DP_D, PORT_D);
10338 } else if (IS_GEN2(dev))
10339 intel_dvo_init(dev);
10341 if (SUPPORTS_TV(dev))
10342 intel_tv_init(dev);
10344 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10345 encoder->base.possible_crtcs = encoder->crtc_mask;
10346 encoder->base.possible_clones =
10347 intel_encoder_clones(encoder);
10350 intel_init_pch_refclk(dev);
10352 drm_helper_move_panel_connectors_to_head(dev);
10355 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10357 drm_framebuffer_cleanup(&fb->base);
10358 WARN_ON(!fb->obj->framebuffer_references--);
10359 drm_gem_object_unreference_unlocked(&fb->obj->base);
10362 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10364 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10366 intel_framebuffer_fini(intel_fb);
10370 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10371 struct drm_file *file,
10372 unsigned int *handle)
10374 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10375 struct drm_i915_gem_object *obj = intel_fb->obj;
10377 return drm_gem_handle_create(file, &obj->base, handle);
10380 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10381 .destroy = intel_user_framebuffer_destroy,
10382 .create_handle = intel_user_framebuffer_create_handle,
10385 int intel_framebuffer_init(struct drm_device *dev,
10386 struct intel_framebuffer *intel_fb,
10387 struct drm_mode_fb_cmd2 *mode_cmd,
10388 struct drm_i915_gem_object *obj)
10390 int aligned_height, tile_height;
10394 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10396 if (obj->tiling_mode == I915_TILING_Y) {
10397 DRM_DEBUG("hardware does not support tiling Y\n");
10401 if (mode_cmd->pitches[0] & 63) {
10402 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10403 mode_cmd->pitches[0]);
10407 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10408 pitch_limit = 32*1024;
10409 } else if (INTEL_INFO(dev)->gen >= 4) {
10410 if (obj->tiling_mode)
10411 pitch_limit = 16*1024;
10413 pitch_limit = 32*1024;
10414 } else if (INTEL_INFO(dev)->gen >= 3) {
10415 if (obj->tiling_mode)
10416 pitch_limit = 8*1024;
10418 pitch_limit = 16*1024;
10420 /* XXX DSPC is limited to 4k tiled */
10421 pitch_limit = 8*1024;
10423 if (mode_cmd->pitches[0] > pitch_limit) {
10424 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10425 obj->tiling_mode ? "tiled" : "linear",
10426 mode_cmd->pitches[0], pitch_limit);
10430 if (obj->tiling_mode != I915_TILING_NONE &&
10431 mode_cmd->pitches[0] != obj->stride) {
10432 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10433 mode_cmd->pitches[0], obj->stride);
10437 /* Reject formats not supported by any plane early. */
10438 switch (mode_cmd->pixel_format) {
10439 case DRM_FORMAT_C8:
10440 case DRM_FORMAT_RGB565:
10441 case DRM_FORMAT_XRGB8888:
10442 case DRM_FORMAT_ARGB8888:
10444 case DRM_FORMAT_XRGB1555:
10445 case DRM_FORMAT_ARGB1555:
10446 if (INTEL_INFO(dev)->gen > 3) {
10447 DRM_DEBUG("unsupported pixel format: %s\n",
10448 drm_get_format_name(mode_cmd->pixel_format));
10452 case DRM_FORMAT_XBGR8888:
10453 case DRM_FORMAT_ABGR8888:
10454 case DRM_FORMAT_XRGB2101010:
10455 case DRM_FORMAT_ARGB2101010:
10456 case DRM_FORMAT_XBGR2101010:
10457 case DRM_FORMAT_ABGR2101010:
10458 if (INTEL_INFO(dev)->gen < 4) {
10459 DRM_DEBUG("unsupported pixel format: %s\n",
10460 drm_get_format_name(mode_cmd->pixel_format));
10464 case DRM_FORMAT_YUYV:
10465 case DRM_FORMAT_UYVY:
10466 case DRM_FORMAT_YVYU:
10467 case DRM_FORMAT_VYUY:
10468 if (INTEL_INFO(dev)->gen < 5) {
10469 DRM_DEBUG("unsupported pixel format: %s\n",
10470 drm_get_format_name(mode_cmd->pixel_format));
10475 DRM_DEBUG("unsupported pixel format: %s\n",
10476 drm_get_format_name(mode_cmd->pixel_format));
10480 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10481 if (mode_cmd->offsets[0] != 0)
10484 tile_height = IS_GEN2(dev) ? 16 : 8;
10485 aligned_height = ALIGN(mode_cmd->height,
10486 obj->tiling_mode ? tile_height : 1);
10487 /* FIXME drm helper for size checks (especially planar formats)? */
10488 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10491 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10492 intel_fb->obj = obj;
10493 intel_fb->obj->framebuffer_references++;
10495 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10497 DRM_ERROR("framebuffer init failed %d\n", ret);
10504 static struct drm_framebuffer *
10505 intel_user_framebuffer_create(struct drm_device *dev,
10506 struct drm_file *filp,
10507 struct drm_mode_fb_cmd2 *mode_cmd)
10509 struct drm_i915_gem_object *obj;
10511 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10512 mode_cmd->handles[0]));
10513 if (&obj->base == NULL)
10514 return ERR_PTR(-ENOENT);
10516 return intel_framebuffer_create(dev, mode_cmd, obj);
10519 #ifndef CONFIG_DRM_I915_FBDEV
10520 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10525 static const struct drm_mode_config_funcs intel_mode_funcs = {
10526 .fb_create = intel_user_framebuffer_create,
10527 .output_poll_changed = intel_fbdev_output_poll_changed,
10530 /* Set up chip specific display functions */
10531 static void intel_init_display(struct drm_device *dev)
10533 struct drm_i915_private *dev_priv = dev->dev_private;
10535 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10536 dev_priv->display.find_dpll = g4x_find_best_dpll;
10537 else if (IS_VALLEYVIEW(dev))
10538 dev_priv->display.find_dpll = vlv_find_best_dpll;
10539 else if (IS_PINEVIEW(dev))
10540 dev_priv->display.find_dpll = pnv_find_best_dpll;
10542 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10544 if (HAS_DDI(dev)) {
10545 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10546 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10547 dev_priv->display.crtc_enable = haswell_crtc_enable;
10548 dev_priv->display.crtc_disable = haswell_crtc_disable;
10549 dev_priv->display.off = haswell_crtc_off;
10550 dev_priv->display.update_plane = ironlake_update_plane;
10551 } else if (HAS_PCH_SPLIT(dev)) {
10552 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10553 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10554 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10555 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10556 dev_priv->display.off = ironlake_crtc_off;
10557 dev_priv->display.update_plane = ironlake_update_plane;
10558 } else if (IS_VALLEYVIEW(dev)) {
10559 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10560 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10561 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10562 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10563 dev_priv->display.off = i9xx_crtc_off;
10564 dev_priv->display.update_plane = i9xx_update_plane;
10566 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10567 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10568 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10569 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10570 dev_priv->display.off = i9xx_crtc_off;
10571 dev_priv->display.update_plane = i9xx_update_plane;
10574 /* Returns the core display clock speed */
10575 if (IS_VALLEYVIEW(dev))
10576 dev_priv->display.get_display_clock_speed =
10577 valleyview_get_display_clock_speed;
10578 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10579 dev_priv->display.get_display_clock_speed =
10580 i945_get_display_clock_speed;
10581 else if (IS_I915G(dev))
10582 dev_priv->display.get_display_clock_speed =
10583 i915_get_display_clock_speed;
10584 else if (IS_I945GM(dev) || IS_845G(dev))
10585 dev_priv->display.get_display_clock_speed =
10586 i9xx_misc_get_display_clock_speed;
10587 else if (IS_PINEVIEW(dev))
10588 dev_priv->display.get_display_clock_speed =
10589 pnv_get_display_clock_speed;
10590 else if (IS_I915GM(dev))
10591 dev_priv->display.get_display_clock_speed =
10592 i915gm_get_display_clock_speed;
10593 else if (IS_I865G(dev))
10594 dev_priv->display.get_display_clock_speed =
10595 i865_get_display_clock_speed;
10596 else if (IS_I85X(dev))
10597 dev_priv->display.get_display_clock_speed =
10598 i855_get_display_clock_speed;
10599 else /* 852, 830 */
10600 dev_priv->display.get_display_clock_speed =
10601 i830_get_display_clock_speed;
10603 if (HAS_PCH_SPLIT(dev)) {
10604 if (IS_GEN5(dev)) {
10605 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10606 dev_priv->display.write_eld = ironlake_write_eld;
10607 } else if (IS_GEN6(dev)) {
10608 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10609 dev_priv->display.write_eld = ironlake_write_eld;
10610 } else if (IS_IVYBRIDGE(dev)) {
10611 /* FIXME: detect B0+ stepping and use auto training */
10612 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10613 dev_priv->display.write_eld = ironlake_write_eld;
10614 dev_priv->display.modeset_global_resources =
10615 ivb_modeset_global_resources;
10616 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10617 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10618 dev_priv->display.write_eld = haswell_write_eld;
10619 dev_priv->display.modeset_global_resources =
10620 haswell_modeset_global_resources;
10622 } else if (IS_G4X(dev)) {
10623 dev_priv->display.write_eld = g4x_write_eld;
10624 } else if (IS_VALLEYVIEW(dev)) {
10625 dev_priv->display.modeset_global_resources =
10626 valleyview_modeset_global_resources;
10627 dev_priv->display.write_eld = ironlake_write_eld;
10630 /* Default just returns -ENODEV to indicate unsupported */
10631 dev_priv->display.queue_flip = intel_default_queue_flip;
10633 switch (INTEL_INFO(dev)->gen) {
10635 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10639 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10644 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10648 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10651 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10652 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10656 intel_panel_init_backlight_funcs(dev);
10660 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10661 * resume, or other times. This quirk makes sure that's the case for
10662 * affected systems.
10664 static void quirk_pipea_force(struct drm_device *dev)
10666 struct drm_i915_private *dev_priv = dev->dev_private;
10668 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10669 DRM_INFO("applying pipe a force quirk\n");
10673 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10675 static void quirk_ssc_force_disable(struct drm_device *dev)
10677 struct drm_i915_private *dev_priv = dev->dev_private;
10678 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10679 DRM_INFO("applying lvds SSC disable quirk\n");
10683 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10686 static void quirk_invert_brightness(struct drm_device *dev)
10688 struct drm_i915_private *dev_priv = dev->dev_private;
10689 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10690 DRM_INFO("applying inverted panel brightness quirk\n");
10693 struct intel_quirk {
10695 int subsystem_vendor;
10696 int subsystem_device;
10697 void (*hook)(struct drm_device *dev);
10700 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10701 struct intel_dmi_quirk {
10702 void (*hook)(struct drm_device *dev);
10703 const struct dmi_system_id (*dmi_id_list)[];
10706 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10708 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10712 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10714 .dmi_id_list = &(const struct dmi_system_id[]) {
10716 .callback = intel_dmi_reverse_brightness,
10717 .ident = "NCR Corporation",
10718 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10719 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10722 { } /* terminating entry */
10724 .hook = quirk_invert_brightness,
10728 static struct intel_quirk intel_quirks[] = {
10729 /* HP Mini needs pipe A force quirk (LP: #322104) */
10730 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10732 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10733 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10735 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10736 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10738 /* 830 needs to leave pipe A & dpll A up */
10739 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10741 /* Lenovo U160 cannot use SSC on LVDS */
10742 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10744 /* Sony Vaio Y cannot use SSC on LVDS */
10745 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10748 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10749 * seem to use inverted backlight PWM.
10751 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10754 static void intel_init_quirks(struct drm_device *dev)
10756 struct pci_dev *d = dev->pdev;
10759 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10760 struct intel_quirk *q = &intel_quirks[i];
10762 if (d->device == q->device &&
10763 (d->subsystem_vendor == q->subsystem_vendor ||
10764 q->subsystem_vendor == PCI_ANY_ID) &&
10765 (d->subsystem_device == q->subsystem_device ||
10766 q->subsystem_device == PCI_ANY_ID))
10769 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10770 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10771 intel_dmi_quirks[i].hook(dev);
10775 /* Disable the VGA plane that we never use */
10776 static void i915_disable_vga(struct drm_device *dev)
10778 struct drm_i915_private *dev_priv = dev->dev_private;
10780 u32 vga_reg = i915_vgacntrl_reg(dev);
10782 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10783 outb(SR01, VGA_SR_INDEX);
10784 sr1 = inb(VGA_SR_DATA);
10785 outb(sr1 | 1<<5, VGA_SR_DATA);
10786 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10789 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10790 POSTING_READ(vga_reg);
10793 void intel_modeset_init_hw(struct drm_device *dev)
10795 intel_prepare_ddi(dev);
10797 intel_init_clock_gating(dev);
10799 intel_init_dpio(dev);
10801 mutex_lock(&dev->struct_mutex);
10802 intel_enable_gt_powersave(dev);
10803 mutex_unlock(&dev->struct_mutex);
10806 void intel_modeset_suspend_hw(struct drm_device *dev)
10808 intel_suspend_hw(dev);
10811 void intel_modeset_init(struct drm_device *dev)
10813 struct drm_i915_private *dev_priv = dev->dev_private;
10816 drm_mode_config_init(dev);
10818 dev->mode_config.min_width = 0;
10819 dev->mode_config.min_height = 0;
10821 dev->mode_config.preferred_depth = 24;
10822 dev->mode_config.prefer_shadow = 1;
10824 dev->mode_config.funcs = &intel_mode_funcs;
10826 intel_init_quirks(dev);
10828 intel_init_pm(dev);
10830 if (INTEL_INFO(dev)->num_pipes == 0)
10833 intel_init_display(dev);
10835 if (IS_GEN2(dev)) {
10836 dev->mode_config.max_width = 2048;
10837 dev->mode_config.max_height = 2048;
10838 } else if (IS_GEN3(dev)) {
10839 dev->mode_config.max_width = 4096;
10840 dev->mode_config.max_height = 4096;
10842 dev->mode_config.max_width = 8192;
10843 dev->mode_config.max_height = 8192;
10845 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10847 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10848 INTEL_INFO(dev)->num_pipes,
10849 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10852 intel_crtc_init(dev, i);
10853 for (j = 0; j < dev_priv->num_plane; j++) {
10854 ret = intel_plane_init(dev, i, j);
10856 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10857 pipe_name(i), sprite_name(i, j), ret);
10861 intel_cpu_pll_init(dev);
10862 intel_shared_dpll_init(dev);
10864 /* Just disable it once at startup */
10865 i915_disable_vga(dev);
10866 intel_setup_outputs(dev);
10868 /* Just in case the BIOS is doing something questionable. */
10869 intel_disable_fbc(dev);
10873 intel_connector_break_all_links(struct intel_connector *connector)
10875 connector->base.dpms = DRM_MODE_DPMS_OFF;
10876 connector->base.encoder = NULL;
10877 connector->encoder->connectors_active = false;
10878 connector->encoder->base.crtc = NULL;
10881 static void intel_enable_pipe_a(struct drm_device *dev)
10883 struct intel_connector *connector;
10884 struct drm_connector *crt = NULL;
10885 struct intel_load_detect_pipe load_detect_temp;
10887 /* We can't just switch on the pipe A, we need to set things up with a
10888 * proper mode and output configuration. As a gross hack, enable pipe A
10889 * by enabling the load detect pipe once. */
10890 list_for_each_entry(connector,
10891 &dev->mode_config.connector_list,
10893 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10894 crt = &connector->base;
10902 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10903 intel_release_load_detect_pipe(crt, &load_detect_temp);
10909 intel_check_plane_mapping(struct intel_crtc *crtc)
10911 struct drm_device *dev = crtc->base.dev;
10912 struct drm_i915_private *dev_priv = dev->dev_private;
10915 if (INTEL_INFO(dev)->num_pipes == 1)
10918 reg = DSPCNTR(!crtc->plane);
10919 val = I915_READ(reg);
10921 if ((val & DISPLAY_PLANE_ENABLE) &&
10922 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10928 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10930 struct drm_device *dev = crtc->base.dev;
10931 struct drm_i915_private *dev_priv = dev->dev_private;
10934 /* Clear any frame start delays used for debugging left by the BIOS */
10935 reg = PIPECONF(crtc->config.cpu_transcoder);
10936 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10938 /* We need to sanitize the plane -> pipe mapping first because this will
10939 * disable the crtc (and hence change the state) if it is wrong. Note
10940 * that gen4+ has a fixed plane -> pipe mapping. */
10941 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10942 struct intel_connector *connector;
10945 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10946 crtc->base.base.id);
10948 /* Pipe has the wrong plane attached and the plane is active.
10949 * Temporarily change the plane mapping and disable everything
10951 plane = crtc->plane;
10952 crtc->plane = !plane;
10953 dev_priv->display.crtc_disable(&crtc->base);
10954 crtc->plane = plane;
10956 /* ... and break all links. */
10957 list_for_each_entry(connector, &dev->mode_config.connector_list,
10959 if (connector->encoder->base.crtc != &crtc->base)
10962 intel_connector_break_all_links(connector);
10965 WARN_ON(crtc->active);
10966 crtc->base.enabled = false;
10969 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10970 crtc->pipe == PIPE_A && !crtc->active) {
10971 /* BIOS forgot to enable pipe A, this mostly happens after
10972 * resume. Force-enable the pipe to fix this, the update_dpms
10973 * call below we restore the pipe to the right state, but leave
10974 * the required bits on. */
10975 intel_enable_pipe_a(dev);
10978 /* Adjust the state of the output pipe according to whether we
10979 * have active connectors/encoders. */
10980 intel_crtc_update_dpms(&crtc->base);
10982 if (crtc->active != crtc->base.enabled) {
10983 struct intel_encoder *encoder;
10985 /* This can happen either due to bugs in the get_hw_state
10986 * functions or because the pipe is force-enabled due to the
10988 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10989 crtc->base.base.id,
10990 crtc->base.enabled ? "enabled" : "disabled",
10991 crtc->active ? "enabled" : "disabled");
10993 crtc->base.enabled = crtc->active;
10995 /* Because we only establish the connector -> encoder ->
10996 * crtc links if something is active, this means the
10997 * crtc is now deactivated. Break the links. connector
10998 * -> encoder links are only establish when things are
10999 * actually up, hence no need to break them. */
11000 WARN_ON(crtc->active);
11002 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11003 WARN_ON(encoder->connectors_active);
11004 encoder->base.crtc = NULL;
11009 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11011 struct intel_connector *connector;
11012 struct drm_device *dev = encoder->base.dev;
11014 /* We need to check both for a crtc link (meaning that the
11015 * encoder is active and trying to read from a pipe) and the
11016 * pipe itself being active. */
11017 bool has_active_crtc = encoder->base.crtc &&
11018 to_intel_crtc(encoder->base.crtc)->active;
11020 if (encoder->connectors_active && !has_active_crtc) {
11021 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11022 encoder->base.base.id,
11023 drm_get_encoder_name(&encoder->base));
11025 /* Connector is active, but has no active pipe. This is
11026 * fallout from our resume register restoring. Disable
11027 * the encoder manually again. */
11028 if (encoder->base.crtc) {
11029 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11030 encoder->base.base.id,
11031 drm_get_encoder_name(&encoder->base));
11032 encoder->disable(encoder);
11035 /* Inconsistent output/port/pipe state happens presumably due to
11036 * a bug in one of the get_hw_state functions. Or someplace else
11037 * in our code, like the register restore mess on resume. Clamp
11038 * things to off as a safer default. */
11039 list_for_each_entry(connector,
11040 &dev->mode_config.connector_list,
11042 if (connector->encoder != encoder)
11045 intel_connector_break_all_links(connector);
11048 /* Enabled encoders without active connectors will be fixed in
11049 * the crtc fixup. */
11052 void i915_redisable_vga(struct drm_device *dev)
11054 struct drm_i915_private *dev_priv = dev->dev_private;
11055 u32 vga_reg = i915_vgacntrl_reg(dev);
11057 /* This function can be called both from intel_modeset_setup_hw_state or
11058 * at a very early point in our resume sequence, where the power well
11059 * structures are not yet restored. Since this function is at a very
11060 * paranoid "someone might have enabled VGA while we were not looking"
11061 * level, just check if the power well is enabled instead of trying to
11062 * follow the "don't touch the power well if we don't need it" policy
11063 * the rest of the driver uses. */
11064 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11065 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11068 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11069 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11070 i915_disable_vga(dev);
11074 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11076 struct drm_i915_private *dev_priv = dev->dev_private;
11078 struct intel_crtc *crtc;
11079 struct intel_encoder *encoder;
11080 struct intel_connector *connector;
11083 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11085 memset(&crtc->config, 0, sizeof(crtc->config));
11087 crtc->active = dev_priv->display.get_pipe_config(crtc,
11090 crtc->base.enabled = crtc->active;
11091 crtc->primary_enabled = crtc->active;
11093 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11094 crtc->base.base.id,
11095 crtc->active ? "enabled" : "disabled");
11098 /* FIXME: Smash this into the new shared dpll infrastructure. */
11100 intel_ddi_setup_hw_pll_state(dev);
11102 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11103 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11105 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11107 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11109 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11112 pll->refcount = pll->active;
11114 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11115 pll->name, pll->refcount, pll->on);
11118 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11122 if (encoder->get_hw_state(encoder, &pipe)) {
11123 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11124 encoder->base.crtc = &crtc->base;
11125 encoder->get_config(encoder, &crtc->config);
11127 encoder->base.crtc = NULL;
11130 encoder->connectors_active = false;
11131 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11132 encoder->base.base.id,
11133 drm_get_encoder_name(&encoder->base),
11134 encoder->base.crtc ? "enabled" : "disabled",
11138 list_for_each_entry(connector, &dev->mode_config.connector_list,
11140 if (connector->get_hw_state(connector)) {
11141 connector->base.dpms = DRM_MODE_DPMS_ON;
11142 connector->encoder->connectors_active = true;
11143 connector->base.encoder = &connector->encoder->base;
11145 connector->base.dpms = DRM_MODE_DPMS_OFF;
11146 connector->base.encoder = NULL;
11148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11149 connector->base.base.id,
11150 drm_get_connector_name(&connector->base),
11151 connector->base.encoder ? "enabled" : "disabled");
11155 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11156 * and i915 state tracking structures. */
11157 void intel_modeset_setup_hw_state(struct drm_device *dev,
11158 bool force_restore)
11160 struct drm_i915_private *dev_priv = dev->dev_private;
11162 struct intel_crtc *crtc;
11163 struct intel_encoder *encoder;
11166 intel_modeset_readout_hw_state(dev);
11169 * Now that we have the config, copy it to each CRTC struct
11170 * Note that this could go away if we move to using crtc_config
11171 * checking everywhere.
11173 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11175 if (crtc->active && i915_fastboot) {
11176 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11178 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11179 crtc->base.base.id);
11180 drm_mode_debug_printmodeline(&crtc->base.mode);
11184 /* HW state is read out, now we need to sanitize this mess. */
11185 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11187 intel_sanitize_encoder(encoder);
11190 for_each_pipe(pipe) {
11191 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11192 intel_sanitize_crtc(crtc);
11193 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11196 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11197 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11199 if (!pll->on || pll->active)
11202 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11204 pll->disable(dev_priv, pll);
11208 if (IS_HASWELL(dev))
11209 ilk_wm_get_hw_state(dev);
11211 if (force_restore) {
11212 i915_redisable_vga(dev);
11215 * We need to use raw interfaces for restoring state to avoid
11216 * checking (bogus) intermediate states.
11218 for_each_pipe(pipe) {
11219 struct drm_crtc *crtc =
11220 dev_priv->pipe_to_crtc_mapping[pipe];
11222 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11226 intel_modeset_update_staged_output_state(dev);
11229 intel_modeset_check_state(dev);
11231 drm_mode_config_reset(dev);
11234 void intel_modeset_gem_init(struct drm_device *dev)
11236 intel_modeset_init_hw(dev);
11238 intel_setup_overlay(dev);
11240 intel_modeset_setup_hw_state(dev, false);
11243 void intel_modeset_cleanup(struct drm_device *dev)
11245 struct drm_i915_private *dev_priv = dev->dev_private;
11246 struct drm_crtc *crtc;
11247 struct drm_connector *connector;
11250 * Interrupts and polling as the first thing to avoid creating havoc.
11251 * Too much stuff here (turning of rps, connectors, ...) would
11252 * experience fancy races otherwise.
11254 drm_irq_uninstall(dev);
11255 cancel_work_sync(&dev_priv->hotplug_work);
11257 * Due to the hpd irq storm handling the hotplug work can re-arm the
11258 * poll handlers. Hence disable polling after hpd handling is shut down.
11260 drm_kms_helper_poll_fini(dev);
11262 mutex_lock(&dev->struct_mutex);
11264 intel_unregister_dsm_handler();
11266 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11267 /* Skip inactive CRTCs */
11271 intel_increase_pllclock(crtc);
11274 intel_disable_fbc(dev);
11276 intel_disable_gt_powersave(dev);
11278 ironlake_teardown_rc6(dev);
11280 mutex_unlock(&dev->struct_mutex);
11282 /* flush any delayed tasks or pending work */
11283 flush_scheduled_work();
11285 /* destroy the backlight and sysfs files before encoders/connectors */
11286 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11287 intel_panel_destroy_backlight(connector);
11288 drm_sysfs_connector_remove(connector);
11291 drm_mode_config_cleanup(dev);
11293 intel_cleanup_overlay(dev);
11297 * Return which encoder is currently attached for connector.
11299 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11301 return &intel_attached_encoder(connector)->base;
11304 void intel_connector_attach_encoder(struct intel_connector *connector,
11305 struct intel_encoder *encoder)
11307 connector->encoder = encoder;
11308 drm_mode_connector_attach_encoder(&connector->base,
11313 * set vga decode state - true == enable VGA decode
11315 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11317 struct drm_i915_private *dev_priv = dev->dev_private;
11320 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11322 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11324 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11325 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11329 struct intel_display_error_state {
11331 u32 power_well_driver;
11333 int num_transcoders;
11335 struct intel_cursor_error_state {
11340 } cursor[I915_MAX_PIPES];
11342 struct intel_pipe_error_state {
11343 bool power_domain_on;
11345 } pipe[I915_MAX_PIPES];
11347 struct intel_plane_error_state {
11355 } plane[I915_MAX_PIPES];
11357 struct intel_transcoder_error_state {
11358 bool power_domain_on;
11359 enum transcoder cpu_transcoder;
11372 struct intel_display_error_state *
11373 intel_display_capture_error_state(struct drm_device *dev)
11375 drm_i915_private_t *dev_priv = dev->dev_private;
11376 struct intel_display_error_state *error;
11377 int transcoders[] = {
11385 if (INTEL_INFO(dev)->num_pipes == 0)
11388 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11392 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11393 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11396 error->pipe[i].power_domain_on =
11397 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11398 if (!error->pipe[i].power_domain_on)
11401 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11402 error->cursor[i].control = I915_READ(CURCNTR(i));
11403 error->cursor[i].position = I915_READ(CURPOS(i));
11404 error->cursor[i].base = I915_READ(CURBASE(i));
11406 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11407 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11408 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11411 error->plane[i].control = I915_READ(DSPCNTR(i));
11412 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11413 if (INTEL_INFO(dev)->gen <= 3) {
11414 error->plane[i].size = I915_READ(DSPSIZE(i));
11415 error->plane[i].pos = I915_READ(DSPPOS(i));
11417 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11418 error->plane[i].addr = I915_READ(DSPADDR(i));
11419 if (INTEL_INFO(dev)->gen >= 4) {
11420 error->plane[i].surface = I915_READ(DSPSURF(i));
11421 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11424 error->pipe[i].source = I915_READ(PIPESRC(i));
11427 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11428 if (HAS_DDI(dev_priv->dev))
11429 error->num_transcoders++; /* Account for eDP. */
11431 for (i = 0; i < error->num_transcoders; i++) {
11432 enum transcoder cpu_transcoder = transcoders[i];
11434 error->transcoder[i].power_domain_on =
11435 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11436 if (!error->transcoder[i].power_domain_on)
11439 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11441 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11442 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11443 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11444 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11445 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11446 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11447 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11453 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11456 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11457 struct drm_device *dev,
11458 struct intel_display_error_state *error)
11465 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11466 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11467 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11468 error->power_well_driver);
11470 err_printf(m, "Pipe [%d]:\n", i);
11471 err_printf(m, " Power: %s\n",
11472 error->pipe[i].power_domain_on ? "on" : "off");
11473 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11475 err_printf(m, "Plane [%d]:\n", i);
11476 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11477 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11478 if (INTEL_INFO(dev)->gen <= 3) {
11479 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11480 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11482 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11483 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11484 if (INTEL_INFO(dev)->gen >= 4) {
11485 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11486 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11489 err_printf(m, "Cursor [%d]:\n", i);
11490 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11491 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11492 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11495 for (i = 0; i < error->num_transcoders; i++) {
11496 err_printf(m, "CPU transcoder: %c\n",
11497 transcoder_name(error->transcoder[i].cpu_transcoder));
11498 err_printf(m, " Power: %s\n",
11499 error->transcoder[i].power_domain_on ? "on" : "off");
11500 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11501 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11502 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11503 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11504 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11505 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11506 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);