drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 DRM_DEBUG_KMS("vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1099                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1100         else if (IS_845G(dev) || IS_I865G(dev))
1101                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1102         else
1103                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN((val & DISPLAY_PLANE_ENABLE),
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN((val & SP_ENABLE),
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN((val & SPRITE_ENABLE),
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN((val & DVS_ENABLE),
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455         I915_WRITE(reg, dpll);
1456
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807
1808         /*
1809          * There's no guarantee the pipe will really start running now. It
1810          * depends on the Gen, the output type and the relative order between
1811          * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812          * necessary.
1813          * TODO: audit the previous gens.
1814          */
1815         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816                 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818
1819 /**
1820  * intel_disable_pipe - disable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to disable
1823  *
1824  * Disable @pipe, making sure that various hardware specific requirements
1825  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826  *
1827  * @pipe should be %PIPE_A or %PIPE_B.
1828  *
1829  * Will wait until the pipe has shut down before returning.
1830  */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832                                enum pipe pipe)
1833 {
1834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835                                                                       pipe);
1836         int reg;
1837         u32 val;
1838
1839         /*
1840          * Make sure planes won't keep trying to pump pixels to us,
1841          * or we might hang the display.
1842          */
1843         assert_planes_disabled(dev_priv, pipe);
1844         assert_cursor_disabled(dev_priv, pipe);
1845         assert_sprites_disabled(dev_priv, pipe);
1846
1847         /* Don't disable pipe A or pipe A PLLs if needed */
1848         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849                 return;
1850
1851         reg = PIPECONF(cpu_transcoder);
1852         val = I915_READ(reg);
1853         if ((val & PIPECONF_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861  * Plane regs are double buffered, going from enabled->disabled needs a
1862  * trigger in order to latch.  The display address reg provides this.
1863  */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865                                enum plane plane)
1866 {
1867         struct drm_device *dev = dev_priv->dev;
1868         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870         I915_WRITE(reg, I915_READ(reg));
1871         POSTING_READ(reg);
1872 }
1873
1874 /**
1875  * intel_enable_primary_plane - enable the primary plane on a given pipe
1876  * @dev_priv: i915 private structure
1877  * @plane: plane to enable
1878  * @pipe: pipe being fed
1879  *
1880  * Enable @plane on @pipe, making sure that @pipe is running first.
1881  */
1882 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1883                                        enum plane plane, enum pipe pipe)
1884 {
1885         struct intel_crtc *intel_crtc =
1886                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887         int reg;
1888         u32 val;
1889
1890         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891         assert_pipe_enabled(dev_priv, pipe);
1892
1893         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894
1895         intel_crtc->primary_enabled = true;
1896
1897         reg = DSPCNTR(plane);
1898         val = I915_READ(reg);
1899         if (val & DISPLAY_PLANE_ENABLE)
1900                 return;
1901
1902         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903         intel_flush_primary_plane(dev_priv, plane);
1904         intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908  * intel_disable_primary_plane - disable the primary plane
1909  * @dev_priv: i915 private structure
1910  * @plane: plane to disable
1911  * @pipe: pipe consuming the data
1912  *
1913  * Disable @plane; should be an independent operation.
1914  */
1915 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1916                                         enum plane plane, enum pipe pipe)
1917 {
1918         struct intel_crtc *intel_crtc =
1919                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920         int reg;
1921         u32 val;
1922
1923         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924
1925         intel_crtc->primary_enabled = false;
1926
1927         reg = DSPCNTR(plane);
1928         val = I915_READ(reg);
1929         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930                 return;
1931
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_primary_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941                 return true;
1942 #endif
1943         return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948         int tile_height;
1949
1950         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951         return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956                            struct drm_i915_gem_object *obj,
1957                            struct intel_ring_buffer *pipelined)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         u32 alignment;
1961         int ret;
1962
1963         switch (obj->tiling_mode) {
1964         case I915_TILING_NONE:
1965                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966                         alignment = 128 * 1024;
1967                 else if (INTEL_INFO(dev)->gen >= 4)
1968                         alignment = 4 * 1024;
1969                 else
1970                         alignment = 64 * 1024;
1971                 break;
1972         case I915_TILING_X:
1973                 /* pin() will align the object as required by fence */
1974                 alignment = 0;
1975                 break;
1976         case I915_TILING_Y:
1977                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978                 return -EINVAL;
1979         default:
1980                 BUG();
1981         }
1982
1983         /* Note that the w/a also requires 64 PTE of padding following the
1984          * bo. We currently fill all unused PTE with the shadow page and so
1985          * we should always have valid PTE following the scanout preventing
1986          * the VT-d warning.
1987          */
1988         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989                 alignment = 256 * 1024;
1990
1991         dev_priv->mm.interruptible = false;
1992         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993         if (ret)
1994                 goto err_interruptible;
1995
1996         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997          * fence, whereas 965+ only requires a fence if using
1998          * framebuffer compression.  For simplicity, we always install
1999          * a fence as the cost is not that onerous.
2000          */
2001         ret = i915_gem_object_get_fence(obj);
2002         if (ret)
2003                 goto err_unpin;
2004
2005         i915_gem_object_pin_fence(obj);
2006
2007         dev_priv->mm.interruptible = true;
2008         return 0;
2009
2010 err_unpin:
2011         i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013         dev_priv->mm.interruptible = true;
2014         return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019         i915_gem_object_unpin_fence(obj);
2020         i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024  * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026                                              unsigned int tiling_mode,
2027                                              unsigned int cpp,
2028                                              unsigned int pitch)
2029 {
2030         if (tiling_mode != I915_TILING_NONE) {
2031                 unsigned int tile_rows, tiles;
2032
2033                 tile_rows = *y / 8;
2034                 *y %= 8;
2035
2036                 tiles = *x / (512/cpp);
2037                 *x %= 512/cpp;
2038
2039                 return tile_rows * pitch * 8 + tiles * 4096;
2040         } else {
2041                 unsigned int offset;
2042
2043                 offset = *y * pitch + *x * cpp;
2044                 *y = 0;
2045                 *x = (offset & 4095) / cpp;
2046                 return offset & -4096;
2047         }
2048 }
2049
2050 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2051                              int x, int y)
2052 {
2053         struct drm_device *dev = crtc->dev;
2054         struct drm_i915_private *dev_priv = dev->dev_private;
2055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056         struct intel_framebuffer *intel_fb;
2057         struct drm_i915_gem_object *obj;
2058         int plane = intel_crtc->plane;
2059         unsigned long linear_offset;
2060         u32 dspcntr;
2061         u32 reg;
2062
2063         switch (plane) {
2064         case 0:
2065         case 1:
2066                 break;
2067         default:
2068                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2069                 return -EINVAL;
2070         }
2071
2072         intel_fb = to_intel_framebuffer(fb);
2073         obj = intel_fb->obj;
2074
2075         reg = DSPCNTR(plane);
2076         dspcntr = I915_READ(reg);
2077         /* Mask out pixel format bits in case we change it */
2078         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2079         switch (fb->pixel_format) {
2080         case DRM_FORMAT_C8:
2081                 dspcntr |= DISPPLANE_8BPP;
2082                 break;
2083         case DRM_FORMAT_XRGB1555:
2084         case DRM_FORMAT_ARGB1555:
2085                 dspcntr |= DISPPLANE_BGRX555;
2086                 break;
2087         case DRM_FORMAT_RGB565:
2088                 dspcntr |= DISPPLANE_BGRX565;
2089                 break;
2090         case DRM_FORMAT_XRGB8888:
2091         case DRM_FORMAT_ARGB8888:
2092                 dspcntr |= DISPPLANE_BGRX888;
2093                 break;
2094         case DRM_FORMAT_XBGR8888:
2095         case DRM_FORMAT_ABGR8888:
2096                 dspcntr |= DISPPLANE_RGBX888;
2097                 break;
2098         case DRM_FORMAT_XRGB2101010:
2099         case DRM_FORMAT_ARGB2101010:
2100                 dspcntr |= DISPPLANE_BGRX101010;
2101                 break;
2102         case DRM_FORMAT_XBGR2101010:
2103         case DRM_FORMAT_ABGR2101010:
2104                 dspcntr |= DISPPLANE_RGBX101010;
2105                 break;
2106         default:
2107                 BUG();
2108         }
2109
2110         if (INTEL_INFO(dev)->gen >= 4) {
2111                 if (obj->tiling_mode != I915_TILING_NONE)
2112                         dspcntr |= DISPPLANE_TILED;
2113                 else
2114                         dspcntr &= ~DISPPLANE_TILED;
2115         }
2116
2117         if (IS_G4X(dev))
2118                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2119
2120         I915_WRITE(reg, dspcntr);
2121
2122         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2123
2124         if (INTEL_INFO(dev)->gen >= 4) {
2125                 intel_crtc->dspaddr_offset =
2126                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2127                                                        fb->bits_per_pixel / 8,
2128                                                        fb->pitches[0]);
2129                 linear_offset -= intel_crtc->dspaddr_offset;
2130         } else {
2131                 intel_crtc->dspaddr_offset = linear_offset;
2132         }
2133
2134         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2135                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2136                       fb->pitches[0]);
2137         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2138         if (INTEL_INFO(dev)->gen >= 4) {
2139                 I915_WRITE(DSPSURF(plane),
2140                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2141                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2143         } else
2144                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2145         POSTING_READ(reg);
2146
2147         return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151                                  struct drm_framebuffer *fb, int x, int y)
2152 {
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156         struct intel_framebuffer *intel_fb;
2157         struct drm_i915_gem_object *obj;
2158         int plane = intel_crtc->plane;
2159         unsigned long linear_offset;
2160         u32 dspcntr;
2161         u32 reg;
2162
2163         switch (plane) {
2164         case 0:
2165         case 1:
2166         case 2:
2167                 break;
2168         default:
2169                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2170                 return -EINVAL;
2171         }
2172
2173         intel_fb = to_intel_framebuffer(fb);
2174         obj = intel_fb->obj;
2175
2176         reg = DSPCNTR(plane);
2177         dspcntr = I915_READ(reg);
2178         /* Mask out pixel format bits in case we change it */
2179         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180         switch (fb->pixel_format) {
2181         case DRM_FORMAT_C8:
2182                 dspcntr |= DISPPLANE_8BPP;
2183                 break;
2184         case DRM_FORMAT_RGB565:
2185                 dspcntr |= DISPPLANE_BGRX565;
2186                 break;
2187         case DRM_FORMAT_XRGB8888:
2188         case DRM_FORMAT_ARGB8888:
2189                 dspcntr |= DISPPLANE_BGRX888;
2190                 break;
2191         case DRM_FORMAT_XBGR8888:
2192         case DRM_FORMAT_ABGR8888:
2193                 dspcntr |= DISPPLANE_RGBX888;
2194                 break;
2195         case DRM_FORMAT_XRGB2101010:
2196         case DRM_FORMAT_ARGB2101010:
2197                 dspcntr |= DISPPLANE_BGRX101010;
2198                 break;
2199         case DRM_FORMAT_XBGR2101010:
2200         case DRM_FORMAT_ABGR2101010:
2201                 dspcntr |= DISPPLANE_RGBX101010;
2202                 break;
2203         default:
2204                 BUG();
2205         }
2206
2207         if (obj->tiling_mode != I915_TILING_NONE)
2208                 dspcntr |= DISPPLANE_TILED;
2209         else
2210                 dspcntr &= ~DISPPLANE_TILED;
2211
2212         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2213                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2214         else
2215                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2216
2217         I915_WRITE(reg, dspcntr);
2218
2219         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2220         intel_crtc->dspaddr_offset =
2221                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2222                                                fb->bits_per_pixel / 8,
2223                                                fb->pitches[0]);
2224         linear_offset -= intel_crtc->dspaddr_offset;
2225
2226         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2227                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2228                       fb->pitches[0]);
2229         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2230         I915_WRITE(DSPSURF(plane),
2231                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2232         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2233                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2234         } else {
2235                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2236                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2237         }
2238         POSTING_READ(reg);
2239
2240         return 0;
2241 }
2242
2243 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2244 static int
2245 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2246                            int x, int y, enum mode_set_atomic state)
2247 {
2248         struct drm_device *dev = crtc->dev;
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250
2251         if (dev_priv->display.disable_fbc)
2252                 dev_priv->display.disable_fbc(dev);
2253         intel_increase_pllclock(crtc);
2254
2255         return dev_priv->display.update_plane(crtc, fb, x, y);
2256 }
2257
2258 void intel_display_handle_reset(struct drm_device *dev)
2259 {
2260         struct drm_i915_private *dev_priv = dev->dev_private;
2261         struct drm_crtc *crtc;
2262
2263         /*
2264          * Flips in the rings have been nuked by the reset,
2265          * so complete all pending flips so that user space
2266          * will get its events and not get stuck.
2267          *
2268          * Also update the base address of all primary
2269          * planes to the the last fb to make sure we're
2270          * showing the correct fb after a reset.
2271          *
2272          * Need to make two loops over the crtcs so that we
2273          * don't try to grab a crtc mutex before the
2274          * pending_flip_queue really got woken up.
2275          */
2276
2277         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2278                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279                 enum plane plane = intel_crtc->plane;
2280
2281                 intel_prepare_page_flip(dev, plane);
2282                 intel_finish_page_flip_plane(dev, plane);
2283         }
2284
2285         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2286                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287
2288                 mutex_lock(&crtc->mutex);
2289                 /*
2290                  * FIXME: Once we have proper support for primary planes (and
2291                  * disabling them without disabling the entire crtc) allow again
2292                  * a NULL crtc->fb.
2293                  */
2294                 if (intel_crtc->active && crtc->fb)
2295                         dev_priv->display.update_plane(crtc, crtc->fb,
2296                                                        crtc->x, crtc->y);
2297                 mutex_unlock(&crtc->mutex);
2298         }
2299 }
2300
2301 static int
2302 intel_finish_fb(struct drm_framebuffer *old_fb)
2303 {
2304         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2305         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2306         bool was_interruptible = dev_priv->mm.interruptible;
2307         int ret;
2308
2309         /* Big Hammer, we also need to ensure that any pending
2310          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2311          * current scanout is retired before unpinning the old
2312          * framebuffer.
2313          *
2314          * This should only fail upon a hung GPU, in which case we
2315          * can safely continue.
2316          */
2317         dev_priv->mm.interruptible = false;
2318         ret = i915_gem_object_finish_gpu(obj);
2319         dev_priv->mm.interruptible = was_interruptible;
2320
2321         return ret;
2322 }
2323
2324 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2325 {
2326         struct drm_device *dev = crtc->dev;
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329         unsigned long flags;
2330         bool pending;
2331
2332         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2333             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2334                 return false;
2335
2336         spin_lock_irqsave(&dev->event_lock, flags);
2337         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2338         spin_unlock_irqrestore(&dev->event_lock, flags);
2339
2340         return pending;
2341 }
2342
2343 static int
2344 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2345                     struct drm_framebuffer *fb)
2346 {
2347         struct drm_device *dev = crtc->dev;
2348         struct drm_i915_private *dev_priv = dev->dev_private;
2349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350         struct drm_framebuffer *old_fb;
2351         int ret;
2352
2353         if (intel_crtc_has_pending_flip(crtc)) {
2354                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2355                 return -EBUSY;
2356         }
2357
2358         /* no fb bound */
2359         if (!fb) {
2360                 DRM_ERROR("No FB bound\n");
2361                 return 0;
2362         }
2363
2364         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2365                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2366                           plane_name(intel_crtc->plane),
2367                           INTEL_INFO(dev)->num_pipes);
2368                 return -EINVAL;
2369         }
2370
2371         mutex_lock(&dev->struct_mutex);
2372         ret = intel_pin_and_fence_fb_obj(dev,
2373                                          to_intel_framebuffer(fb)->obj,
2374                                          NULL);
2375         if (ret != 0) {
2376                 mutex_unlock(&dev->struct_mutex);
2377                 DRM_ERROR("pin & fence failed\n");
2378                 return ret;
2379         }
2380
2381         /*
2382          * Update pipe size and adjust fitter if needed: the reason for this is
2383          * that in compute_mode_changes we check the native mode (not the pfit
2384          * mode) to see if we can flip rather than do a full mode set. In the
2385          * fastboot case, we'll flip, but if we don't update the pipesrc and
2386          * pfit state, we'll end up with a big fb scanned out into the wrong
2387          * sized surface.
2388          *
2389          * To fix this properly, we need to hoist the checks up into
2390          * compute_mode_changes (or above), check the actual pfit state and
2391          * whether the platform allows pfit disable with pipe active, and only
2392          * then update the pipesrc and pfit state, even on the flip path.
2393          */
2394         if (i915.fastboot) {
2395                 const struct drm_display_mode *adjusted_mode =
2396                         &intel_crtc->config.adjusted_mode;
2397
2398                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2399                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2400                            (adjusted_mode->crtc_vdisplay - 1));
2401                 if (!intel_crtc->config.pch_pfit.enabled &&
2402                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2403                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2404                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2405                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2406                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2407                 }
2408                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2409                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2410         }
2411
2412         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2413         if (ret) {
2414                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2415                 mutex_unlock(&dev->struct_mutex);
2416                 DRM_ERROR("failed to update base address\n");
2417                 return ret;
2418         }
2419
2420         old_fb = crtc->fb;
2421         crtc->fb = fb;
2422         crtc->x = x;
2423         crtc->y = y;
2424
2425         if (old_fb) {
2426                 if (intel_crtc->active && old_fb != fb)
2427                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2428                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2429         }
2430
2431         intel_update_fbc(dev);
2432         intel_edp_psr_update(dev);
2433         mutex_unlock(&dev->struct_mutex);
2434
2435         return 0;
2436 }
2437
2438 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2439 {
2440         struct drm_device *dev = crtc->dev;
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2443         int pipe = intel_crtc->pipe;
2444         u32 reg, temp;
2445
2446         /* enable normal train */
2447         reg = FDI_TX_CTL(pipe);
2448         temp = I915_READ(reg);
2449         if (IS_IVYBRIDGE(dev)) {
2450                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2451                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2452         } else {
2453                 temp &= ~FDI_LINK_TRAIN_NONE;
2454                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2455         }
2456         I915_WRITE(reg, temp);
2457
2458         reg = FDI_RX_CTL(pipe);
2459         temp = I915_READ(reg);
2460         if (HAS_PCH_CPT(dev)) {
2461                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2462                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2463         } else {
2464                 temp &= ~FDI_LINK_TRAIN_NONE;
2465                 temp |= FDI_LINK_TRAIN_NONE;
2466         }
2467         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2468
2469         /* wait one idle pattern time */
2470         POSTING_READ(reg);
2471         udelay(1000);
2472
2473         /* IVB wants error correction enabled */
2474         if (IS_IVYBRIDGE(dev))
2475                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2476                            FDI_FE_ERRC_ENABLE);
2477 }
2478
2479 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2480 {
2481         return crtc->base.enabled && crtc->active &&
2482                 crtc->config.has_pch_encoder;
2483 }
2484
2485 static void ivb_modeset_global_resources(struct drm_device *dev)
2486 {
2487         struct drm_i915_private *dev_priv = dev->dev_private;
2488         struct intel_crtc *pipe_B_crtc =
2489                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2490         struct intel_crtc *pipe_C_crtc =
2491                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2492         uint32_t temp;
2493
2494         /*
2495          * When everything is off disable fdi C so that we could enable fdi B
2496          * with all lanes. Note that we don't care about enabled pipes without
2497          * an enabled pch encoder.
2498          */
2499         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2500             !pipe_has_enabled_pch(pipe_C_crtc)) {
2501                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2502                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2503
2504                 temp = I915_READ(SOUTH_CHICKEN1);
2505                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2506                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2507                 I915_WRITE(SOUTH_CHICKEN1, temp);
2508         }
2509 }
2510
2511 /* The FDI link training functions for ILK/Ibexpeak. */
2512 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517         int pipe = intel_crtc->pipe;
2518         int plane = intel_crtc->plane;
2519         u32 reg, temp, tries;
2520
2521         /* FDI needs bits from pipe & plane first */
2522         assert_pipe_enabled(dev_priv, pipe);
2523         assert_plane_enabled(dev_priv, plane);
2524
2525         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2526            for train result */
2527         reg = FDI_RX_IMR(pipe);
2528         temp = I915_READ(reg);
2529         temp &= ~FDI_RX_SYMBOL_LOCK;
2530         temp &= ~FDI_RX_BIT_LOCK;
2531         I915_WRITE(reg, temp);
2532         I915_READ(reg);
2533         udelay(150);
2534
2535         /* enable CPU FDI TX and PCH FDI RX */
2536         reg = FDI_TX_CTL(pipe);
2537         temp = I915_READ(reg);
2538         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2539         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2540         temp &= ~FDI_LINK_TRAIN_NONE;
2541         temp |= FDI_LINK_TRAIN_PATTERN_1;
2542         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2543
2544         reg = FDI_RX_CTL(pipe);
2545         temp = I915_READ(reg);
2546         temp &= ~FDI_LINK_TRAIN_NONE;
2547         temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2549
2550         POSTING_READ(reg);
2551         udelay(150);
2552
2553         /* Ironlake workaround, enable clock pointer after FDI enable*/
2554         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2555         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2556                    FDI_RX_PHASE_SYNC_POINTER_EN);
2557
2558         reg = FDI_RX_IIR(pipe);
2559         for (tries = 0; tries < 5; tries++) {
2560                 temp = I915_READ(reg);
2561                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562
2563                 if ((temp & FDI_RX_BIT_LOCK)) {
2564                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2565                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2566                         break;
2567                 }
2568         }
2569         if (tries == 5)
2570                 DRM_ERROR("FDI train 1 fail!\n");
2571
2572         /* Train 2 */
2573         reg = FDI_TX_CTL(pipe);
2574         temp = I915_READ(reg);
2575         temp &= ~FDI_LINK_TRAIN_NONE;
2576         temp |= FDI_LINK_TRAIN_PATTERN_2;
2577         I915_WRITE(reg, temp);
2578
2579         reg = FDI_RX_CTL(pipe);
2580         temp = I915_READ(reg);
2581         temp &= ~FDI_LINK_TRAIN_NONE;
2582         temp |= FDI_LINK_TRAIN_PATTERN_2;
2583         I915_WRITE(reg, temp);
2584
2585         POSTING_READ(reg);
2586         udelay(150);
2587
2588         reg = FDI_RX_IIR(pipe);
2589         for (tries = 0; tries < 5; tries++) {
2590                 temp = I915_READ(reg);
2591                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2592
2593                 if (temp & FDI_RX_SYMBOL_LOCK) {
2594                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2595                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2596                         break;
2597                 }
2598         }
2599         if (tries == 5)
2600                 DRM_ERROR("FDI train 2 fail!\n");
2601
2602         DRM_DEBUG_KMS("FDI train done\n");
2603
2604 }
2605
2606 static const int snb_b_fdi_train_param[] = {
2607         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2608         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2609         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2610         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2611 };
2612
2613 /* The FDI link training functions for SNB/Cougarpoint. */
2614 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2615 {
2616         struct drm_device *dev = crtc->dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619         int pipe = intel_crtc->pipe;
2620         u32 reg, temp, i, retry;
2621
2622         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2623            for train result */
2624         reg = FDI_RX_IMR(pipe);
2625         temp = I915_READ(reg);
2626         temp &= ~FDI_RX_SYMBOL_LOCK;
2627         temp &= ~FDI_RX_BIT_LOCK;
2628         I915_WRITE(reg, temp);
2629
2630         POSTING_READ(reg);
2631         udelay(150);
2632
2633         /* enable CPU FDI TX and PCH FDI RX */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2637         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2638         temp &= ~FDI_LINK_TRAIN_NONE;
2639         temp |= FDI_LINK_TRAIN_PATTERN_1;
2640         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641         /* SNB-B */
2642         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2644
2645         I915_WRITE(FDI_RX_MISC(pipe),
2646                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2647
2648         reg = FDI_RX_CTL(pipe);
2649         temp = I915_READ(reg);
2650         if (HAS_PCH_CPT(dev)) {
2651                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2653         } else {
2654                 temp &= ~FDI_LINK_TRAIN_NONE;
2655                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2656         }
2657         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         for (i = 0; i < 4; i++) {
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666                 temp |= snb_b_fdi_train_param[i];
2667                 I915_WRITE(reg, temp);
2668
2669                 POSTING_READ(reg);
2670                 udelay(500);
2671
2672                 for (retry = 0; retry < 5; retry++) {
2673                         reg = FDI_RX_IIR(pipe);
2674                         temp = I915_READ(reg);
2675                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676                         if (temp & FDI_RX_BIT_LOCK) {
2677                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2678                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2679                                 break;
2680                         }
2681                         udelay(50);
2682                 }
2683                 if (retry < 5)
2684                         break;
2685         }
2686         if (i == 4)
2687                 DRM_ERROR("FDI train 1 fail!\n");
2688
2689         /* Train 2 */
2690         reg = FDI_TX_CTL(pipe);
2691         temp = I915_READ(reg);
2692         temp &= ~FDI_LINK_TRAIN_NONE;
2693         temp |= FDI_LINK_TRAIN_PATTERN_2;
2694         if (IS_GEN6(dev)) {
2695                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696                 /* SNB-B */
2697                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2698         }
2699         I915_WRITE(reg, temp);
2700
2701         reg = FDI_RX_CTL(pipe);
2702         temp = I915_READ(reg);
2703         if (HAS_PCH_CPT(dev)) {
2704                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2705                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2706         } else {
2707                 temp &= ~FDI_LINK_TRAIN_NONE;
2708                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2709         }
2710         I915_WRITE(reg, temp);
2711
2712         POSTING_READ(reg);
2713         udelay(150);
2714
2715         for (i = 0; i < 4; i++) {
2716                 reg = FDI_TX_CTL(pipe);
2717                 temp = I915_READ(reg);
2718                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719                 temp |= snb_b_fdi_train_param[i];
2720                 I915_WRITE(reg, temp);
2721
2722                 POSTING_READ(reg);
2723                 udelay(500);
2724
2725                 for (retry = 0; retry < 5; retry++) {
2726                         reg = FDI_RX_IIR(pipe);
2727                         temp = I915_READ(reg);
2728                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2729                         if (temp & FDI_RX_SYMBOL_LOCK) {
2730                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2731                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2732                                 break;
2733                         }
2734                         udelay(50);
2735                 }
2736                 if (retry < 5)
2737                         break;
2738         }
2739         if (i == 4)
2740                 DRM_ERROR("FDI train 2 fail!\n");
2741
2742         DRM_DEBUG_KMS("FDI train done.\n");
2743 }
2744
2745 /* Manual link training for Ivy Bridge A0 parts */
2746 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2747 {
2748         struct drm_device *dev = crtc->dev;
2749         struct drm_i915_private *dev_priv = dev->dev_private;
2750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751         int pipe = intel_crtc->pipe;
2752         u32 reg, temp, i, j;
2753
2754         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2755            for train result */
2756         reg = FDI_RX_IMR(pipe);
2757         temp = I915_READ(reg);
2758         temp &= ~FDI_RX_SYMBOL_LOCK;
2759         temp &= ~FDI_RX_BIT_LOCK;
2760         I915_WRITE(reg, temp);
2761
2762         POSTING_READ(reg);
2763         udelay(150);
2764
2765         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2766                       I915_READ(FDI_RX_IIR(pipe)));
2767
2768         /* Try each vswing and preemphasis setting twice before moving on */
2769         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2770                 /* disable first in case we need to retry */
2771                 reg = FDI_TX_CTL(pipe);
2772                 temp = I915_READ(reg);
2773                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2774                 temp &= ~FDI_TX_ENABLE;
2775                 I915_WRITE(reg, temp);
2776
2777                 reg = FDI_RX_CTL(pipe);
2778                 temp = I915_READ(reg);
2779                 temp &= ~FDI_LINK_TRAIN_AUTO;
2780                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781                 temp &= ~FDI_RX_ENABLE;
2782                 I915_WRITE(reg, temp);
2783
2784                 /* enable CPU FDI TX and PCH FDI RX */
2785                 reg = FDI_TX_CTL(pipe);
2786                 temp = I915_READ(reg);
2787                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2788                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2789                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2790                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2791                 temp |= snb_b_fdi_train_param[j/2];
2792                 temp |= FDI_COMPOSITE_SYNC;
2793                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2794
2795                 I915_WRITE(FDI_RX_MISC(pipe),
2796                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2797
2798                 reg = FDI_RX_CTL(pipe);
2799                 temp = I915_READ(reg);
2800                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2801                 temp |= FDI_COMPOSITE_SYNC;
2802                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2803
2804                 POSTING_READ(reg);
2805                 udelay(1); /* should be 0.5us */
2806
2807                 for (i = 0; i < 4; i++) {
2808                         reg = FDI_RX_IIR(pipe);
2809                         temp = I915_READ(reg);
2810                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811
2812                         if (temp & FDI_RX_BIT_LOCK ||
2813                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2814                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2815                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2816                                               i);
2817                                 break;
2818                         }
2819                         udelay(1); /* should be 0.5us */
2820                 }
2821                 if (i == 4) {
2822                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2823                         continue;
2824                 }
2825
2826                 /* Train 2 */
2827                 reg = FDI_TX_CTL(pipe);
2828                 temp = I915_READ(reg);
2829                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2830                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2831                 I915_WRITE(reg, temp);
2832
2833                 reg = FDI_RX_CTL(pipe);
2834                 temp = I915_READ(reg);
2835                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2836                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2837                 I915_WRITE(reg, temp);
2838
2839                 POSTING_READ(reg);
2840                 udelay(2); /* should be 1.5us */
2841
2842                 for (i = 0; i < 4; i++) {
2843                         reg = FDI_RX_IIR(pipe);
2844                         temp = I915_READ(reg);
2845                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2846
2847                         if (temp & FDI_RX_SYMBOL_LOCK ||
2848                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2849                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2850                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2851                                               i);
2852                                 goto train_done;
2853                         }
2854                         udelay(2); /* should be 1.5us */
2855                 }
2856                 if (i == 4)
2857                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2858         }
2859
2860 train_done:
2861         DRM_DEBUG_KMS("FDI train done.\n");
2862 }
2863
2864 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2865 {
2866         struct drm_device *dev = intel_crtc->base.dev;
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         int pipe = intel_crtc->pipe;
2869         u32 reg, temp;
2870
2871
2872         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2873         reg = FDI_RX_CTL(pipe);
2874         temp = I915_READ(reg);
2875         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2876         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2877         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2878         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2879
2880         POSTING_READ(reg);
2881         udelay(200);
2882
2883         /* Switch from Rawclk to PCDclk */
2884         temp = I915_READ(reg);
2885         I915_WRITE(reg, temp | FDI_PCDCLK);
2886
2887         POSTING_READ(reg);
2888         udelay(200);
2889
2890         /* Enable CPU FDI TX PLL, always on for Ironlake */
2891         reg = FDI_TX_CTL(pipe);
2892         temp = I915_READ(reg);
2893         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2894                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2895
2896                 POSTING_READ(reg);
2897                 udelay(100);
2898         }
2899 }
2900
2901 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2902 {
2903         struct drm_device *dev = intel_crtc->base.dev;
2904         struct drm_i915_private *dev_priv = dev->dev_private;
2905         int pipe = intel_crtc->pipe;
2906         u32 reg, temp;
2907
2908         /* Switch from PCDclk to Rawclk */
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2912
2913         /* Disable CPU FDI TX PLL */
2914         reg = FDI_TX_CTL(pipe);
2915         temp = I915_READ(reg);
2916         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2917
2918         POSTING_READ(reg);
2919         udelay(100);
2920
2921         reg = FDI_RX_CTL(pipe);
2922         temp = I915_READ(reg);
2923         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2924
2925         /* Wait for the clocks to turn off. */
2926         POSTING_READ(reg);
2927         udelay(100);
2928 }
2929
2930 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935         int pipe = intel_crtc->pipe;
2936         u32 reg, temp;
2937
2938         /* disable CPU FDI tx and PCH FDI rx */
2939         reg = FDI_TX_CTL(pipe);
2940         temp = I915_READ(reg);
2941         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2942         POSTING_READ(reg);
2943
2944         reg = FDI_RX_CTL(pipe);
2945         temp = I915_READ(reg);
2946         temp &= ~(0x7 << 16);
2947         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2948         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2949
2950         POSTING_READ(reg);
2951         udelay(100);
2952
2953         /* Ironlake workaround, disable clock pointer after downing FDI */
2954         if (HAS_PCH_IBX(dev)) {
2955                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2956         }
2957
2958         /* still set train pattern 1 */
2959         reg = FDI_TX_CTL(pipe);
2960         temp = I915_READ(reg);
2961         temp &= ~FDI_LINK_TRAIN_NONE;
2962         temp |= FDI_LINK_TRAIN_PATTERN_1;
2963         I915_WRITE(reg, temp);
2964
2965         reg = FDI_RX_CTL(pipe);
2966         temp = I915_READ(reg);
2967         if (HAS_PCH_CPT(dev)) {
2968                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2969                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2970         } else {
2971                 temp &= ~FDI_LINK_TRAIN_NONE;
2972                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2973         }
2974         /* BPC in FDI rx is consistent with that in PIPECONF */
2975         temp &= ~(0x07 << 16);
2976         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2977         I915_WRITE(reg, temp);
2978
2979         POSTING_READ(reg);
2980         udelay(100);
2981 }
2982
2983 bool intel_has_pending_fb_unpin(struct drm_device *dev)
2984 {
2985         struct intel_crtc *crtc;
2986
2987         /* Note that we don't need to be called with mode_config.lock here
2988          * as our list of CRTC objects is static for the lifetime of the
2989          * device and so cannot disappear as we iterate. Similarly, we can
2990          * happily treat the predicates as racy, atomic checks as userspace
2991          * cannot claim and pin a new fb without at least acquring the
2992          * struct_mutex and so serialising with us.
2993          */
2994         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2995                 if (atomic_read(&crtc->unpin_work_count) == 0)
2996                         continue;
2997
2998                 if (crtc->unpin_work)
2999                         intel_wait_for_vblank(dev, crtc->pipe);
3000
3001                 return true;
3002         }
3003
3004         return false;
3005 }
3006
3007 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012         if (crtc->fb == NULL)
3013                 return;
3014
3015         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3016
3017         wait_event(dev_priv->pending_flip_queue,
3018                    !intel_crtc_has_pending_flip(crtc));
3019
3020         mutex_lock(&dev->struct_mutex);
3021         intel_finish_fb(crtc->fb);
3022         mutex_unlock(&dev->struct_mutex);
3023 }
3024
3025 /* Program iCLKIP clock to the desired frequency */
3026 static void lpt_program_iclkip(struct drm_crtc *crtc)
3027 {
3028         struct drm_device *dev = crtc->dev;
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3031         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3032         u32 temp;
3033
3034         mutex_lock(&dev_priv->dpio_lock);
3035
3036         /* It is necessary to ungate the pixclk gate prior to programming
3037          * the divisors, and gate it back when it is done.
3038          */
3039         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3040
3041         /* Disable SSCCTL */
3042         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3043                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3044                                 SBI_SSCCTL_DISABLE,
3045                         SBI_ICLK);
3046
3047         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3048         if (clock == 20000) {
3049                 auxdiv = 1;
3050                 divsel = 0x41;
3051                 phaseinc = 0x20;
3052         } else {
3053                 /* The iCLK virtual clock root frequency is in MHz,
3054                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3055                  * divisors, it is necessary to divide one by another, so we
3056                  * convert the virtual clock precision to KHz here for higher
3057                  * precision.
3058                  */
3059                 u32 iclk_virtual_root_freq = 172800 * 1000;
3060                 u32 iclk_pi_range = 64;
3061                 u32 desired_divisor, msb_divisor_value, pi_value;
3062
3063                 desired_divisor = (iclk_virtual_root_freq / clock);
3064                 msb_divisor_value = desired_divisor / iclk_pi_range;
3065                 pi_value = desired_divisor % iclk_pi_range;
3066
3067                 auxdiv = 0;
3068                 divsel = msb_divisor_value - 2;
3069                 phaseinc = pi_value;
3070         }
3071
3072         /* This should not happen with any sane values */
3073         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3074                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3075         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3076                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3077
3078         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3079                         clock,
3080                         auxdiv,
3081                         divsel,
3082                         phasedir,
3083                         phaseinc);
3084
3085         /* Program SSCDIVINTPHASE6 */
3086         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3087         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3088         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3089         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3090         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3091         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3092         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3093         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3094
3095         /* Program SSCAUXDIV */
3096         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3097         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3098         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3099         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3100
3101         /* Enable modulator and associated divider */
3102         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3103         temp &= ~SBI_SSCCTL_DISABLE;
3104         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3105
3106         /* Wait for initialization time */
3107         udelay(24);
3108
3109         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3110
3111         mutex_unlock(&dev_priv->dpio_lock);
3112 }
3113
3114 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3115                                                 enum pipe pch_transcoder)
3116 {
3117         struct drm_device *dev = crtc->base.dev;
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3120
3121         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3122                    I915_READ(HTOTAL(cpu_transcoder)));
3123         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3124                    I915_READ(HBLANK(cpu_transcoder)));
3125         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3126                    I915_READ(HSYNC(cpu_transcoder)));
3127
3128         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3129                    I915_READ(VTOTAL(cpu_transcoder)));
3130         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3131                    I915_READ(VBLANK(cpu_transcoder)));
3132         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3133                    I915_READ(VSYNC(cpu_transcoder)));
3134         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3135                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3136 }
3137
3138 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3139 {
3140         struct drm_i915_private *dev_priv = dev->dev_private;
3141         uint32_t temp;
3142
3143         temp = I915_READ(SOUTH_CHICKEN1);
3144         if (temp & FDI_BC_BIFURCATION_SELECT)
3145                 return;
3146
3147         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3148         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3149
3150         temp |= FDI_BC_BIFURCATION_SELECT;
3151         DRM_DEBUG_KMS("enabling fdi C rx\n");
3152         I915_WRITE(SOUTH_CHICKEN1, temp);
3153         POSTING_READ(SOUTH_CHICKEN1);
3154 }
3155
3156 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3157 {
3158         struct drm_device *dev = intel_crtc->base.dev;
3159         struct drm_i915_private *dev_priv = dev->dev_private;
3160
3161         switch (intel_crtc->pipe) {
3162         case PIPE_A:
3163                 break;
3164         case PIPE_B:
3165                 if (intel_crtc->config.fdi_lanes > 2)
3166                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3167                 else
3168                         cpt_enable_fdi_bc_bifurcation(dev);
3169
3170                 break;
3171         case PIPE_C:
3172                 cpt_enable_fdi_bc_bifurcation(dev);
3173
3174                 break;
3175         default:
3176                 BUG();
3177         }
3178 }
3179
3180 /*
3181  * Enable PCH resources required for PCH ports:
3182  *   - PCH PLLs
3183  *   - FDI training & RX/TX
3184  *   - update transcoder timings
3185  *   - DP transcoding bits
3186  *   - transcoder
3187  */
3188 static void ironlake_pch_enable(struct drm_crtc *crtc)
3189 {
3190         struct drm_device *dev = crtc->dev;
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193         int pipe = intel_crtc->pipe;
3194         u32 reg, temp;
3195
3196         assert_pch_transcoder_disabled(dev_priv, pipe);
3197
3198         if (IS_IVYBRIDGE(dev))
3199                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3200
3201         /* Write the TU size bits before fdi link training, so that error
3202          * detection works. */
3203         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3204                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3205
3206         /* For PCH output, training FDI link */
3207         dev_priv->display.fdi_link_train(crtc);
3208
3209         /* We need to program the right clock selection before writing the pixel
3210          * mutliplier into the DPLL. */
3211         if (HAS_PCH_CPT(dev)) {
3212                 u32 sel;
3213
3214                 temp = I915_READ(PCH_DPLL_SEL);
3215                 temp |= TRANS_DPLL_ENABLE(pipe);
3216                 sel = TRANS_DPLLB_SEL(pipe);
3217                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3218                         temp |= sel;
3219                 else
3220                         temp &= ~sel;
3221                 I915_WRITE(PCH_DPLL_SEL, temp);
3222         }
3223
3224         /* XXX: pch pll's can be enabled any time before we enable the PCH
3225          * transcoder, and we actually should do this to not upset any PCH
3226          * transcoder that already use the clock when we share it.
3227          *
3228          * Note that enable_shared_dpll tries to do the right thing, but
3229          * get_shared_dpll unconditionally resets the pll - we need that to have
3230          * the right LVDS enable sequence. */
3231         ironlake_enable_shared_dpll(intel_crtc);
3232
3233         /* set transcoder timing, panel must allow it */
3234         assert_panel_unlocked(dev_priv, pipe);
3235         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3236
3237         intel_fdi_normal_train(crtc);
3238
3239         /* For PCH DP, enable TRANS_DP_CTL */
3240         if (HAS_PCH_CPT(dev) &&
3241             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3242              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3243                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3244                 reg = TRANS_DP_CTL(pipe);
3245                 temp = I915_READ(reg);
3246                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3247                           TRANS_DP_SYNC_MASK |
3248                           TRANS_DP_BPC_MASK);
3249                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3250                          TRANS_DP_ENH_FRAMING);
3251                 temp |= bpc << 9; /* same format but at 11:9 */
3252
3253                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3254                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3255                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3256                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3257
3258                 switch (intel_trans_dp_port_sel(crtc)) {
3259                 case PCH_DP_B:
3260                         temp |= TRANS_DP_PORT_SEL_B;
3261                         break;
3262                 case PCH_DP_C:
3263                         temp |= TRANS_DP_PORT_SEL_C;
3264                         break;
3265                 case PCH_DP_D:
3266                         temp |= TRANS_DP_PORT_SEL_D;
3267                         break;
3268                 default:
3269                         BUG();
3270                 }
3271
3272                 I915_WRITE(reg, temp);
3273         }
3274
3275         ironlake_enable_pch_transcoder(dev_priv, pipe);
3276 }
3277
3278 static void lpt_pch_enable(struct drm_crtc *crtc)
3279 {
3280         struct drm_device *dev = crtc->dev;
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3283         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3284
3285         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3286
3287         lpt_program_iclkip(crtc);
3288
3289         /* Set transcoder timing. */
3290         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3291
3292         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3293 }
3294
3295 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3296 {
3297         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3298
3299         if (pll == NULL)
3300                 return;
3301
3302         if (pll->refcount == 0) {
3303                 WARN(1, "bad %s refcount\n", pll->name);
3304                 return;
3305         }
3306
3307         if (--pll->refcount == 0) {
3308                 WARN_ON(pll->on);
3309                 WARN_ON(pll->active);
3310         }
3311
3312         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3313 }
3314
3315 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3316 {
3317         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3318         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3319         enum intel_dpll_id i;
3320
3321         if (pll) {
3322                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3323                               crtc->base.base.id, pll->name);
3324                 intel_put_shared_dpll(crtc);
3325         }
3326
3327         if (HAS_PCH_IBX(dev_priv->dev)) {
3328                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3329                 i = (enum intel_dpll_id) crtc->pipe;
3330                 pll = &dev_priv->shared_dplls[i];
3331
3332                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3333                               crtc->base.base.id, pll->name);
3334
3335                 goto found;
3336         }
3337
3338         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3339                 pll = &dev_priv->shared_dplls[i];
3340
3341                 /* Only want to check enabled timings first */
3342                 if (pll->refcount == 0)
3343                         continue;
3344
3345                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3346                            sizeof(pll->hw_state)) == 0) {
3347                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3348                                       crtc->base.base.id,
3349                                       pll->name, pll->refcount, pll->active);
3350
3351                         goto found;
3352                 }
3353         }
3354
3355         /* Ok no matching timings, maybe there's a free one? */
3356         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3357                 pll = &dev_priv->shared_dplls[i];
3358                 if (pll->refcount == 0) {
3359                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3360                                       crtc->base.base.id, pll->name);
3361                         goto found;
3362                 }
3363         }
3364
3365         return NULL;
3366
3367 found:
3368         crtc->config.shared_dpll = i;
3369         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3370                          pipe_name(crtc->pipe));
3371
3372         if (pll->active == 0) {
3373                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3374                        sizeof(pll->hw_state));
3375
3376                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3377                 WARN_ON(pll->on);
3378                 assert_shared_dpll_disabled(dev_priv, pll);
3379
3380                 pll->mode_set(dev_priv, pll);
3381         }
3382         pll->refcount++;
3383
3384         return pll;
3385 }
3386
3387 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3388 {
3389         struct drm_i915_private *dev_priv = dev->dev_private;
3390         int dslreg = PIPEDSL(pipe);
3391         u32 temp;
3392
3393         temp = I915_READ(dslreg);
3394         udelay(500);
3395         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3396                 if (wait_for(I915_READ(dslreg) != temp, 5))
3397                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3398         }
3399 }
3400
3401 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3402 {
3403         struct drm_device *dev = crtc->base.dev;
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         int pipe = crtc->pipe;
3406
3407         if (crtc->config.pch_pfit.enabled) {
3408                 /* Force use of hard-coded filter coefficients
3409                  * as some pre-programmed values are broken,
3410                  * e.g. x201.
3411                  */
3412                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3413                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3414                                                  PF_PIPE_SEL_IVB(pipe));
3415                 else
3416                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3417                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3418                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3419         }
3420 }
3421
3422 static void intel_enable_planes(struct drm_crtc *crtc)
3423 {
3424         struct drm_device *dev = crtc->dev;
3425         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3426         struct intel_plane *intel_plane;
3427
3428         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3429                 if (intel_plane->pipe == pipe)
3430                         intel_plane_restore(&intel_plane->base);
3431 }
3432
3433 static void intel_disable_planes(struct drm_crtc *crtc)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3437         struct intel_plane *intel_plane;
3438
3439         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3440                 if (intel_plane->pipe == pipe)
3441                         intel_plane_disable(&intel_plane->base);
3442 }
3443
3444 void hsw_enable_ips(struct intel_crtc *crtc)
3445 {
3446         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3447
3448         if (!crtc->config.ips_enabled)
3449                 return;
3450
3451         /* We can only enable IPS after we enable a plane and wait for a vblank.
3452          * We guarantee that the plane is enabled by calling intel_enable_ips
3453          * only after intel_enable_plane. And intel_enable_plane already waits
3454          * for a vblank, so all we need to do here is to enable the IPS bit. */
3455         assert_plane_enabled(dev_priv, crtc->plane);
3456         if (IS_BROADWELL(crtc->base.dev)) {
3457                 mutex_lock(&dev_priv->rps.hw_lock);
3458                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3459                 mutex_unlock(&dev_priv->rps.hw_lock);
3460                 /* Quoting Art Runyan: "its not safe to expect any particular
3461                  * value in IPS_CTL bit 31 after enabling IPS through the
3462                  * mailbox." Moreover, the mailbox may return a bogus state,
3463                  * so we need to just enable it and continue on.
3464                  */
3465         } else {
3466                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3467                 /* The bit only becomes 1 in the next vblank, so this wait here
3468                  * is essentially intel_wait_for_vblank. If we don't have this
3469                  * and don't wait for vblanks until the end of crtc_enable, then
3470                  * the HW state readout code will complain that the expected
3471                  * IPS_CTL value is not the one we read. */
3472                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3473                         DRM_ERROR("Timed out waiting for IPS enable\n");
3474         }
3475 }
3476
3477 void hsw_disable_ips(struct intel_crtc *crtc)
3478 {
3479         struct drm_device *dev = crtc->base.dev;
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481
3482         if (!crtc->config.ips_enabled)
3483                 return;
3484
3485         assert_plane_enabled(dev_priv, crtc->plane);
3486         if (IS_BROADWELL(crtc->base.dev)) {
3487                 mutex_lock(&dev_priv->rps.hw_lock);
3488                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3489                 mutex_unlock(&dev_priv->rps.hw_lock);
3490         } else {
3491                 I915_WRITE(IPS_CTL, 0);
3492                 POSTING_READ(IPS_CTL);
3493         }
3494
3495         /* We need to wait for a vblank before we can disable the plane. */
3496         intel_wait_for_vblank(dev, crtc->pipe);
3497 }
3498
3499 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3500 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3501 {
3502         struct drm_device *dev = crtc->dev;
3503         struct drm_i915_private *dev_priv = dev->dev_private;
3504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505         enum pipe pipe = intel_crtc->pipe;
3506         int palreg = PALETTE(pipe);
3507         int i;
3508         bool reenable_ips = false;
3509
3510         /* The clocks have to be on to load the palette. */
3511         if (!crtc->enabled || !intel_crtc->active)
3512                 return;
3513
3514         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3515                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3516                         assert_dsi_pll_enabled(dev_priv);
3517                 else
3518                         assert_pll_enabled(dev_priv, pipe);
3519         }
3520
3521         /* use legacy palette for Ironlake */
3522         if (HAS_PCH_SPLIT(dev))
3523                 palreg = LGC_PALETTE(pipe);
3524
3525         /* Workaround : Do not read or write the pipe palette/gamma data while
3526          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3527          */
3528         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3529             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3530              GAMMA_MODE_MODE_SPLIT)) {
3531                 hsw_disable_ips(intel_crtc);
3532                 reenable_ips = true;
3533         }
3534
3535         for (i = 0; i < 256; i++) {
3536                 I915_WRITE(palreg + 4 * i,
3537                            (intel_crtc->lut_r[i] << 16) |
3538                            (intel_crtc->lut_g[i] << 8) |
3539                            intel_crtc->lut_b[i]);
3540         }
3541
3542         if (reenable_ips)
3543                 hsw_enable_ips(intel_crtc);
3544 }
3545
3546 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3547 {
3548         struct drm_device *dev = crtc->dev;
3549         struct drm_i915_private *dev_priv = dev->dev_private;
3550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3551         struct intel_encoder *encoder;
3552         int pipe = intel_crtc->pipe;
3553         int plane = intel_crtc->plane;
3554
3555         WARN_ON(!crtc->enabled);
3556
3557         if (intel_crtc->active)
3558                 return;
3559
3560         intel_crtc->active = true;
3561
3562         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3563         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3564
3565         for_each_encoder_on_crtc(dev, crtc, encoder)
3566                 if (encoder->pre_enable)
3567                         encoder->pre_enable(encoder);
3568
3569         if (intel_crtc->config.has_pch_encoder) {
3570                 /* Note: FDI PLL enabling _must_ be done before we enable the
3571                  * cpu pipes, hence this is separate from all the other fdi/pch
3572                  * enabling. */
3573                 ironlake_fdi_pll_enable(intel_crtc);
3574         } else {
3575                 assert_fdi_tx_disabled(dev_priv, pipe);
3576                 assert_fdi_rx_disabled(dev_priv, pipe);
3577         }
3578
3579         ironlake_pfit_enable(intel_crtc);
3580
3581         /*
3582          * On ILK+ LUT must be loaded before the pipe is running but with
3583          * clocks enabled
3584          */
3585         intel_crtc_load_lut(crtc);
3586
3587         intel_update_watermarks(crtc);
3588         intel_enable_pipe(intel_crtc);
3589         intel_enable_primary_plane(dev_priv, plane, pipe);
3590         intel_enable_planes(crtc);
3591         intel_crtc_update_cursor(crtc, true);
3592
3593         if (intel_crtc->config.has_pch_encoder)
3594                 ironlake_pch_enable(crtc);
3595
3596         mutex_lock(&dev->struct_mutex);
3597         intel_update_fbc(dev);
3598         mutex_unlock(&dev->struct_mutex);
3599
3600         for_each_encoder_on_crtc(dev, crtc, encoder)
3601                 encoder->enable(encoder);
3602
3603         if (HAS_PCH_CPT(dev))
3604                 cpt_verify_modeset(dev, intel_crtc->pipe);
3605
3606         /*
3607          * There seems to be a race in PCH platform hw (at least on some
3608          * outputs) where an enabled pipe still completes any pageflip right
3609          * away (as if the pipe is off) instead of waiting for vblank. As soon
3610          * as the first vblank happend, everything works as expected. Hence just
3611          * wait for one vblank before returning to avoid strange things
3612          * happening.
3613          */
3614         intel_wait_for_vblank(dev, intel_crtc->pipe);
3615 }
3616
3617 /* IPS only exists on ULT machines and is tied to pipe A. */
3618 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3619 {
3620         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3621 }
3622
3623 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3624 {
3625         struct drm_device *dev = crtc->dev;
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628         int pipe = intel_crtc->pipe;
3629         int plane = intel_crtc->plane;
3630
3631         intel_enable_primary_plane(dev_priv, plane, pipe);
3632         intel_enable_planes(crtc);
3633         intel_crtc_update_cursor(crtc, true);
3634
3635         hsw_enable_ips(intel_crtc);
3636
3637         mutex_lock(&dev->struct_mutex);
3638         intel_update_fbc(dev);
3639         mutex_unlock(&dev->struct_mutex);
3640 }
3641
3642 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3643 {
3644         struct drm_device *dev = crtc->dev;
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647         int pipe = intel_crtc->pipe;
3648         int plane = intel_crtc->plane;
3649
3650         intel_crtc_wait_for_pending_flips(crtc);
3651         drm_vblank_off(dev, pipe);
3652
3653         /* FBC must be disabled before disabling the plane on HSW. */
3654         if (dev_priv->fbc.plane == plane)
3655                 intel_disable_fbc(dev);
3656
3657         hsw_disable_ips(intel_crtc);
3658
3659         intel_crtc_update_cursor(crtc, false);
3660         intel_disable_planes(crtc);
3661         intel_disable_primary_plane(dev_priv, plane, pipe);
3662 }
3663
3664 /*
3665  * This implements the workaround described in the "notes" section of the mode
3666  * set sequence documentation. When going from no pipes or single pipe to
3667  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3668  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3669  */
3670 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3671 {
3672         struct drm_device *dev = crtc->base.dev;
3673         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3674
3675         /* We want to get the other_active_crtc only if there's only 1 other
3676          * active crtc. */
3677         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3678                 if (!crtc_it->active || crtc_it == crtc)
3679                         continue;
3680
3681                 if (other_active_crtc)
3682                         return;
3683
3684                 other_active_crtc = crtc_it;
3685         }
3686         if (!other_active_crtc)
3687                 return;
3688
3689         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3690         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3691 }
3692
3693 static void haswell_crtc_enable(struct drm_crtc *crtc)
3694 {
3695         struct drm_device *dev = crtc->dev;
3696         struct drm_i915_private *dev_priv = dev->dev_private;
3697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698         struct intel_encoder *encoder;
3699         int pipe = intel_crtc->pipe;
3700
3701         WARN_ON(!crtc->enabled);
3702
3703         if (intel_crtc->active)
3704                 return;
3705
3706         intel_crtc->active = true;
3707
3708         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3709         if (intel_crtc->config.has_pch_encoder)
3710                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3711
3712         if (intel_crtc->config.has_pch_encoder)
3713                 dev_priv->display.fdi_link_train(crtc);
3714
3715         for_each_encoder_on_crtc(dev, crtc, encoder)
3716                 if (encoder->pre_enable)
3717                         encoder->pre_enable(encoder);
3718
3719         intel_ddi_enable_pipe_clock(intel_crtc);
3720
3721         ironlake_pfit_enable(intel_crtc);
3722
3723         /*
3724          * On ILK+ LUT must be loaded before the pipe is running but with
3725          * clocks enabled
3726          */
3727         intel_crtc_load_lut(crtc);
3728
3729         intel_ddi_set_pipe_settings(crtc);
3730         intel_ddi_enable_transcoder_func(crtc);
3731
3732         intel_update_watermarks(crtc);
3733         intel_enable_pipe(intel_crtc);
3734
3735         if (intel_crtc->config.has_pch_encoder)
3736                 lpt_pch_enable(crtc);
3737
3738         for_each_encoder_on_crtc(dev, crtc, encoder) {
3739                 encoder->enable(encoder);
3740                 intel_opregion_notify_encoder(encoder, true);
3741         }
3742
3743         /* If we change the relative order between pipe/planes enabling, we need
3744          * to change the workaround. */
3745         haswell_mode_set_planes_workaround(intel_crtc);
3746         haswell_crtc_enable_planes(crtc);
3747 }
3748
3749 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3750 {
3751         struct drm_device *dev = crtc->base.dev;
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         int pipe = crtc->pipe;
3754
3755         /* To avoid upsetting the power well on haswell only disable the pfit if
3756          * it's in use. The hw state code will make sure we get this right. */
3757         if (crtc->config.pch_pfit.enabled) {
3758                 I915_WRITE(PF_CTL(pipe), 0);
3759                 I915_WRITE(PF_WIN_POS(pipe), 0);
3760                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3761         }
3762 }
3763
3764 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3765 {
3766         struct drm_device *dev = crtc->dev;
3767         struct drm_i915_private *dev_priv = dev->dev_private;
3768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3769         struct intel_encoder *encoder;
3770         int pipe = intel_crtc->pipe;
3771         int plane = intel_crtc->plane;
3772         u32 reg, temp;
3773
3774
3775         if (!intel_crtc->active)
3776                 return;
3777
3778         for_each_encoder_on_crtc(dev, crtc, encoder)
3779                 encoder->disable(encoder);
3780
3781         intel_crtc_wait_for_pending_flips(crtc);
3782         drm_vblank_off(dev, pipe);
3783
3784         if (dev_priv->fbc.plane == plane)
3785                 intel_disable_fbc(dev);
3786
3787         intel_crtc_update_cursor(crtc, false);
3788         intel_disable_planes(crtc);
3789         intel_disable_primary_plane(dev_priv, plane, pipe);
3790
3791         if (intel_crtc->config.has_pch_encoder)
3792                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3793
3794         intel_disable_pipe(dev_priv, pipe);
3795
3796         ironlake_pfit_disable(intel_crtc);
3797
3798         for_each_encoder_on_crtc(dev, crtc, encoder)
3799                 if (encoder->post_disable)
3800                         encoder->post_disable(encoder);
3801
3802         if (intel_crtc->config.has_pch_encoder) {
3803                 ironlake_fdi_disable(crtc);
3804
3805                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3806                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3807
3808                 if (HAS_PCH_CPT(dev)) {
3809                         /* disable TRANS_DP_CTL */
3810                         reg = TRANS_DP_CTL(pipe);
3811                         temp = I915_READ(reg);
3812                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3813                                   TRANS_DP_PORT_SEL_MASK);
3814                         temp |= TRANS_DP_PORT_SEL_NONE;
3815                         I915_WRITE(reg, temp);
3816
3817                         /* disable DPLL_SEL */
3818                         temp = I915_READ(PCH_DPLL_SEL);
3819                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3820                         I915_WRITE(PCH_DPLL_SEL, temp);
3821                 }
3822
3823                 /* disable PCH DPLL */
3824                 intel_disable_shared_dpll(intel_crtc);
3825
3826                 ironlake_fdi_pll_disable(intel_crtc);
3827         }
3828
3829         intel_crtc->active = false;
3830         intel_update_watermarks(crtc);
3831
3832         mutex_lock(&dev->struct_mutex);
3833         intel_update_fbc(dev);
3834         mutex_unlock(&dev->struct_mutex);
3835 }
3836
3837 static void haswell_crtc_disable(struct drm_crtc *crtc)
3838 {
3839         struct drm_device *dev = crtc->dev;
3840         struct drm_i915_private *dev_priv = dev->dev_private;
3841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3842         struct intel_encoder *encoder;
3843         int pipe = intel_crtc->pipe;
3844         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3845
3846         if (!intel_crtc->active)
3847                 return;
3848
3849         haswell_crtc_disable_planes(crtc);
3850
3851         for_each_encoder_on_crtc(dev, crtc, encoder) {
3852                 intel_opregion_notify_encoder(encoder, false);
3853                 encoder->disable(encoder);
3854         }
3855
3856         if (intel_crtc->config.has_pch_encoder)
3857                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3858         intel_disable_pipe(dev_priv, pipe);
3859
3860         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3861
3862         ironlake_pfit_disable(intel_crtc);
3863
3864         intel_ddi_disable_pipe_clock(intel_crtc);
3865
3866         for_each_encoder_on_crtc(dev, crtc, encoder)
3867                 if (encoder->post_disable)
3868                         encoder->post_disable(encoder);
3869
3870         if (intel_crtc->config.has_pch_encoder) {
3871                 lpt_disable_pch_transcoder(dev_priv);
3872                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3873                 intel_ddi_fdi_disable(crtc);
3874         }
3875
3876         intel_crtc->active = false;
3877         intel_update_watermarks(crtc);
3878
3879         mutex_lock(&dev->struct_mutex);
3880         intel_update_fbc(dev);
3881         mutex_unlock(&dev->struct_mutex);
3882 }
3883
3884 static void ironlake_crtc_off(struct drm_crtc *crtc)
3885 {
3886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3887         intel_put_shared_dpll(intel_crtc);
3888 }
3889
3890 static void haswell_crtc_off(struct drm_crtc *crtc)
3891 {
3892         intel_ddi_put_crtc_pll(crtc);
3893 }
3894
3895 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3896 {
3897         if (!enable && intel_crtc->overlay) {
3898                 struct drm_device *dev = intel_crtc->base.dev;
3899                 struct drm_i915_private *dev_priv = dev->dev_private;
3900
3901                 mutex_lock(&dev->struct_mutex);
3902                 dev_priv->mm.interruptible = false;
3903                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3904                 dev_priv->mm.interruptible = true;
3905                 mutex_unlock(&dev->struct_mutex);
3906         }
3907
3908         /* Let userspace switch the overlay on again. In most cases userspace
3909          * has to recompute where to put it anyway.
3910          */
3911 }
3912
3913 /**
3914  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3915  * cursor plane briefly if not already running after enabling the display
3916  * plane.
3917  * This workaround avoids occasional blank screens when self refresh is
3918  * enabled.
3919  */
3920 static void
3921 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3922 {
3923         u32 cntl = I915_READ(CURCNTR(pipe));
3924
3925         if ((cntl & CURSOR_MODE) == 0) {
3926                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3927
3928                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3929                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3930                 intel_wait_for_vblank(dev_priv->dev, pipe);
3931                 I915_WRITE(CURCNTR(pipe), cntl);
3932                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3933                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3934         }
3935 }
3936
3937 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3938 {
3939         struct drm_device *dev = crtc->base.dev;
3940         struct drm_i915_private *dev_priv = dev->dev_private;
3941         struct intel_crtc_config *pipe_config = &crtc->config;
3942
3943         if (!crtc->config.gmch_pfit.control)
3944                 return;
3945
3946         /*
3947          * The panel fitter should only be adjusted whilst the pipe is disabled,
3948          * according to register description and PRM.
3949          */
3950         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3951         assert_pipe_disabled(dev_priv, crtc->pipe);
3952
3953         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3954         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3955
3956         /* Border color in case we don't scale up to the full screen. Black by
3957          * default, change to something else for debugging. */
3958         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3959 }
3960
3961 #define for_each_power_domain(domain, mask)                             \
3962         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
3963                 if ((1 << (domain)) & (mask))
3964
3965 enum intel_display_power_domain
3966 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
3967 {
3968         struct drm_device *dev = intel_encoder->base.dev;
3969         struct intel_digital_port *intel_dig_port;
3970
3971         switch (intel_encoder->type) {
3972         case INTEL_OUTPUT_UNKNOWN:
3973                 /* Only DDI platforms should ever use this output type */
3974                 WARN_ON_ONCE(!HAS_DDI(dev));
3975         case INTEL_OUTPUT_DISPLAYPORT:
3976         case INTEL_OUTPUT_HDMI:
3977         case INTEL_OUTPUT_EDP:
3978                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3979                 switch (intel_dig_port->port) {
3980                 case PORT_A:
3981                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
3982                 case PORT_B:
3983                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
3984                 case PORT_C:
3985                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
3986                 case PORT_D:
3987                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
3988                 default:
3989                         WARN_ON_ONCE(1);
3990                         return POWER_DOMAIN_PORT_OTHER;
3991                 }
3992         case INTEL_OUTPUT_ANALOG:
3993                 return POWER_DOMAIN_PORT_CRT;
3994         case INTEL_OUTPUT_DSI:
3995                 return POWER_DOMAIN_PORT_DSI;
3996         default:
3997                 return POWER_DOMAIN_PORT_OTHER;
3998         }
3999 }
4000
4001 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4002 {
4003         struct drm_device *dev = crtc->dev;
4004         struct intel_encoder *intel_encoder;
4005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4006         enum pipe pipe = intel_crtc->pipe;
4007         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4008         unsigned long mask;
4009         enum transcoder transcoder;
4010
4011         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4012
4013         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4014         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4015         if (pfit_enabled)
4016                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4017
4018         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4019                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4020
4021         return mask;
4022 }
4023
4024 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4025                                   bool enable)
4026 {
4027         if (dev_priv->power_domains.init_power_on == enable)
4028                 return;
4029
4030         if (enable)
4031                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4032         else
4033                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4034
4035         dev_priv->power_domains.init_power_on = enable;
4036 }
4037
4038 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4039 {
4040         struct drm_i915_private *dev_priv = dev->dev_private;
4041         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4042         struct intel_crtc *crtc;
4043
4044         /*
4045          * First get all needed power domains, then put all unneeded, to avoid
4046          * any unnecessary toggling of the power wells.
4047          */
4048         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4049                 enum intel_display_power_domain domain;
4050
4051                 if (!crtc->base.enabled)
4052                         continue;
4053
4054                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4055
4056                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4057                         intel_display_power_get(dev_priv, domain);
4058         }
4059
4060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4061                 enum intel_display_power_domain domain;
4062
4063                 for_each_power_domain(domain, crtc->enabled_power_domains)
4064                         intel_display_power_put(dev_priv, domain);
4065
4066                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4067         }
4068
4069         intel_display_set_init_power(dev_priv, false);
4070 }
4071
4072 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4073 {
4074         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4075
4076         /* Obtain SKU information */
4077         mutex_lock(&dev_priv->dpio_lock);
4078         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4079                 CCK_FUSE_HPLL_FREQ_MASK;
4080         mutex_unlock(&dev_priv->dpio_lock);
4081
4082         return vco_freq[hpll_freq];
4083 }
4084
4085 /* Adjust CDclk dividers to allow high res or save power if possible */
4086 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4087 {
4088         struct drm_i915_private *dev_priv = dev->dev_private;
4089         u32 val, cmd;
4090
4091         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4092                 cmd = 2;
4093         else if (cdclk == 266)
4094                 cmd = 1;
4095         else
4096                 cmd = 0;
4097
4098         mutex_lock(&dev_priv->rps.hw_lock);
4099         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4100         val &= ~DSPFREQGUAR_MASK;
4101         val |= (cmd << DSPFREQGUAR_SHIFT);
4102         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4103         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4104                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4105                      50)) {
4106                 DRM_ERROR("timed out waiting for CDclk change\n");
4107         }
4108         mutex_unlock(&dev_priv->rps.hw_lock);
4109
4110         if (cdclk == 400) {
4111                 u32 divider, vco;
4112
4113                 vco = valleyview_get_vco(dev_priv);
4114                 divider = ((vco << 1) / cdclk) - 1;
4115
4116                 mutex_lock(&dev_priv->dpio_lock);
4117                 /* adjust cdclk divider */
4118                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4119                 val &= ~0xf;
4120                 val |= divider;
4121                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4122                 mutex_unlock(&dev_priv->dpio_lock);
4123         }
4124
4125         mutex_lock(&dev_priv->dpio_lock);
4126         /* adjust self-refresh exit latency value */
4127         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4128         val &= ~0x7f;
4129
4130         /*
4131          * For high bandwidth configs, we set a higher latency in the bunit
4132          * so that the core display fetch happens in time to avoid underruns.
4133          */
4134         if (cdclk == 400)
4135                 val |= 4500 / 250; /* 4.5 usec */
4136         else
4137                 val |= 3000 / 250; /* 3.0 usec */
4138         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4139         mutex_unlock(&dev_priv->dpio_lock);
4140
4141         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4142         intel_i2c_reset(dev);
4143 }
4144
4145 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4146 {
4147         int cur_cdclk, vco;
4148         int divider;
4149
4150         vco = valleyview_get_vco(dev_priv);
4151
4152         mutex_lock(&dev_priv->dpio_lock);
4153         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4154         mutex_unlock(&dev_priv->dpio_lock);
4155
4156         divider &= 0xf;
4157
4158         cur_cdclk = (vco << 1) / (divider + 1);
4159
4160         return cur_cdclk;
4161 }
4162
4163 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4164                                  int max_pixclk)
4165 {
4166         int cur_cdclk;
4167
4168         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4169
4170         /*
4171          * Really only a few cases to deal with, as only 4 CDclks are supported:
4172          *   200MHz
4173          *   267MHz
4174          *   320MHz
4175          *   400MHz
4176          * So we check to see whether we're above 90% of the lower bin and
4177          * adjust if needed.
4178          */
4179         if (max_pixclk > 288000) {
4180                 return 400;
4181         } else if (max_pixclk > 240000) {
4182                 return 320;
4183         } else
4184                 return 266;
4185         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4186 }
4187
4188 /* compute the max pixel clock for new configuration */
4189 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4190 {
4191         struct drm_device *dev = dev_priv->dev;
4192         struct intel_crtc *intel_crtc;
4193         int max_pixclk = 0;
4194
4195         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4196                             base.head) {
4197                 if (intel_crtc->new_enabled)
4198                         max_pixclk = max(max_pixclk,
4199                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4200         }
4201
4202         return max_pixclk;
4203 }
4204
4205 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4206                                             unsigned *prepare_pipes)
4207 {
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209         struct intel_crtc *intel_crtc;
4210         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4211         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4212
4213         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4214                 return;
4215
4216         /* disable/enable all currently active pipes while we change cdclk */
4217         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4218                             base.head)
4219                 if (intel_crtc->base.enabled)
4220                         *prepare_pipes |= (1 << intel_crtc->pipe);
4221 }
4222
4223 static void valleyview_modeset_global_resources(struct drm_device *dev)
4224 {
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4227         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4228         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4229
4230         if (req_cdclk != cur_cdclk)
4231                 valleyview_set_cdclk(dev, req_cdclk);
4232 }
4233
4234 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4239         struct intel_encoder *encoder;
4240         int pipe = intel_crtc->pipe;
4241         int plane = intel_crtc->plane;
4242         bool is_dsi;
4243
4244         WARN_ON(!crtc->enabled);
4245
4246         if (intel_crtc->active)
4247                 return;
4248
4249         intel_crtc->active = true;
4250
4251         for_each_encoder_on_crtc(dev, crtc, encoder)
4252                 if (encoder->pre_pll_enable)
4253                         encoder->pre_pll_enable(encoder);
4254
4255         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4256
4257         if (!is_dsi)
4258                 vlv_enable_pll(intel_crtc);
4259
4260         for_each_encoder_on_crtc(dev, crtc, encoder)
4261                 if (encoder->pre_enable)
4262                         encoder->pre_enable(encoder);
4263
4264         i9xx_pfit_enable(intel_crtc);
4265
4266         intel_crtc_load_lut(crtc);
4267
4268         intel_update_watermarks(crtc);
4269         intel_enable_pipe(intel_crtc);
4270         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4271         intel_enable_primary_plane(dev_priv, plane, pipe);
4272         intel_enable_planes(crtc);
4273         intel_crtc_update_cursor(crtc, true);
4274
4275         intel_update_fbc(dev);
4276
4277         for_each_encoder_on_crtc(dev, crtc, encoder)
4278                 encoder->enable(encoder);
4279 }
4280
4281 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4282 {
4283         struct drm_device *dev = crtc->dev;
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286         struct intel_encoder *encoder;
4287         int pipe = intel_crtc->pipe;
4288         int plane = intel_crtc->plane;
4289
4290         WARN_ON(!crtc->enabled);
4291
4292         if (intel_crtc->active)
4293                 return;
4294
4295         intel_crtc->active = true;
4296
4297         for_each_encoder_on_crtc(dev, crtc, encoder)
4298                 if (encoder->pre_enable)
4299                         encoder->pre_enable(encoder);
4300
4301         i9xx_enable_pll(intel_crtc);
4302
4303         i9xx_pfit_enable(intel_crtc);
4304
4305         intel_crtc_load_lut(crtc);
4306
4307         intel_update_watermarks(crtc);
4308         intel_enable_pipe(intel_crtc);
4309         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4310         intel_enable_primary_plane(dev_priv, plane, pipe);
4311         intel_enable_planes(crtc);
4312         /* The fixup needs to happen before cursor is enabled */
4313         if (IS_G4X(dev))
4314                 g4x_fixup_plane(dev_priv, pipe);
4315         intel_crtc_update_cursor(crtc, true);
4316
4317         /* Give the overlay scaler a chance to enable if it's on this pipe */
4318         intel_crtc_dpms_overlay(intel_crtc, true);
4319
4320         intel_update_fbc(dev);
4321
4322         for_each_encoder_on_crtc(dev, crtc, encoder)
4323                 encoder->enable(encoder);
4324 }
4325
4326 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4327 {
4328         struct drm_device *dev = crtc->base.dev;
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330
4331         if (!crtc->config.gmch_pfit.control)
4332                 return;
4333
4334         assert_pipe_disabled(dev_priv, crtc->pipe);
4335
4336         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4337                          I915_READ(PFIT_CONTROL));
4338         I915_WRITE(PFIT_CONTROL, 0);
4339 }
4340
4341 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4342 {
4343         struct drm_device *dev = crtc->dev;
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346         struct intel_encoder *encoder;
4347         int pipe = intel_crtc->pipe;
4348         int plane = intel_crtc->plane;
4349
4350         if (!intel_crtc->active)
4351                 return;
4352
4353         for_each_encoder_on_crtc(dev, crtc, encoder)
4354                 encoder->disable(encoder);
4355
4356         /* Give the overlay scaler a chance to disable if it's on this pipe */
4357         intel_crtc_wait_for_pending_flips(crtc);
4358         drm_vblank_off(dev, pipe);
4359
4360         if (dev_priv->fbc.plane == plane)
4361                 intel_disable_fbc(dev);
4362
4363         intel_crtc_dpms_overlay(intel_crtc, false);
4364         intel_crtc_update_cursor(crtc, false);
4365         intel_disable_planes(crtc);
4366         intel_disable_primary_plane(dev_priv, plane, pipe);
4367
4368         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4369         intel_disable_pipe(dev_priv, pipe);
4370
4371         i9xx_pfit_disable(intel_crtc);
4372
4373         for_each_encoder_on_crtc(dev, crtc, encoder)
4374                 if (encoder->post_disable)
4375                         encoder->post_disable(encoder);
4376
4377         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4378                 vlv_disable_pll(dev_priv, pipe);
4379         else if (!IS_VALLEYVIEW(dev))
4380                 i9xx_disable_pll(dev_priv, pipe);
4381
4382         intel_crtc->active = false;
4383         intel_update_watermarks(crtc);
4384
4385         intel_update_fbc(dev);
4386 }
4387
4388 static void i9xx_crtc_off(struct drm_crtc *crtc)
4389 {
4390 }
4391
4392 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4393                                     bool enabled)
4394 {
4395         struct drm_device *dev = crtc->dev;
4396         struct drm_i915_master_private *master_priv;
4397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398         int pipe = intel_crtc->pipe;
4399
4400         if (!dev->primary->master)
4401                 return;
4402
4403         master_priv = dev->primary->master->driver_priv;
4404         if (!master_priv->sarea_priv)
4405                 return;
4406
4407         switch (pipe) {
4408         case 0:
4409                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4410                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4411                 break;
4412         case 1:
4413                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4414                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4415                 break;
4416         default:
4417                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4418                 break;
4419         }
4420 }
4421
4422 /**
4423  * Sets the power management mode of the pipe and plane.
4424  */
4425 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4426 {
4427         struct drm_device *dev = crtc->dev;
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429         struct intel_encoder *intel_encoder;
4430         bool enable = false;
4431
4432         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4433                 enable |= intel_encoder->connectors_active;
4434
4435         if (enable)
4436                 dev_priv->display.crtc_enable(crtc);
4437         else
4438                 dev_priv->display.crtc_disable(crtc);
4439
4440         intel_crtc_update_sarea(crtc, enable);
4441 }
4442
4443 static void intel_crtc_disable(struct drm_crtc *crtc)
4444 {
4445         struct drm_device *dev = crtc->dev;
4446         struct drm_connector *connector;
4447         struct drm_i915_private *dev_priv = dev->dev_private;
4448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4449
4450         /* crtc should still be enabled when we disable it. */
4451         WARN_ON(!crtc->enabled);
4452
4453         dev_priv->display.crtc_disable(crtc);
4454         intel_crtc->eld_vld = false;
4455         intel_crtc_update_sarea(crtc, false);
4456         dev_priv->display.off(crtc);
4457
4458         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4459         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4460         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4461
4462         if (crtc->fb) {
4463                 mutex_lock(&dev->struct_mutex);
4464                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4465                 mutex_unlock(&dev->struct_mutex);
4466                 crtc->fb = NULL;
4467         }
4468
4469         /* Update computed state. */
4470         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4471                 if (!connector->encoder || !connector->encoder->crtc)
4472                         continue;
4473
4474                 if (connector->encoder->crtc != crtc)
4475                         continue;
4476
4477                 connector->dpms = DRM_MODE_DPMS_OFF;
4478                 to_intel_encoder(connector->encoder)->connectors_active = false;
4479         }
4480 }
4481
4482 void intel_encoder_destroy(struct drm_encoder *encoder)
4483 {
4484         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4485
4486         drm_encoder_cleanup(encoder);
4487         kfree(intel_encoder);
4488 }
4489
4490 /* Simple dpms helper for encoders with just one connector, no cloning and only
4491  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4492  * state of the entire output pipe. */
4493 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4494 {
4495         if (mode == DRM_MODE_DPMS_ON) {
4496                 encoder->connectors_active = true;
4497
4498                 intel_crtc_update_dpms(encoder->base.crtc);
4499         } else {
4500                 encoder->connectors_active = false;
4501
4502                 intel_crtc_update_dpms(encoder->base.crtc);
4503         }
4504 }
4505
4506 /* Cross check the actual hw state with our own modeset state tracking (and it's
4507  * internal consistency). */
4508 static void intel_connector_check_state(struct intel_connector *connector)
4509 {
4510         if (connector->get_hw_state(connector)) {
4511                 struct intel_encoder *encoder = connector->encoder;
4512                 struct drm_crtc *crtc;
4513                 bool encoder_enabled;
4514                 enum pipe pipe;
4515
4516                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4517                               connector->base.base.id,
4518                               drm_get_connector_name(&connector->base));
4519
4520                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4521                      "wrong connector dpms state\n");
4522                 WARN(connector->base.encoder != &encoder->base,
4523                      "active connector not linked to encoder\n");
4524                 WARN(!encoder->connectors_active,
4525                      "encoder->connectors_active not set\n");
4526
4527                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4528                 WARN(!encoder_enabled, "encoder not enabled\n");
4529                 if (WARN_ON(!encoder->base.crtc))
4530                         return;
4531
4532                 crtc = encoder->base.crtc;
4533
4534                 WARN(!crtc->enabled, "crtc not enabled\n");
4535                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4536                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4537                      "encoder active on the wrong pipe\n");
4538         }
4539 }
4540
4541 /* Even simpler default implementation, if there's really no special case to
4542  * consider. */
4543 void intel_connector_dpms(struct drm_connector *connector, int mode)
4544 {
4545         /* All the simple cases only support two dpms states. */
4546         if (mode != DRM_MODE_DPMS_ON)
4547                 mode = DRM_MODE_DPMS_OFF;
4548
4549         if (mode == connector->dpms)
4550                 return;
4551
4552         connector->dpms = mode;
4553
4554         /* Only need to change hw state when actually enabled */
4555         if (connector->encoder)
4556                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4557
4558         intel_modeset_check_state(connector->dev);
4559 }
4560
4561 /* Simple connector->get_hw_state implementation for encoders that support only
4562  * one connector and no cloning and hence the encoder state determines the state
4563  * of the connector. */
4564 bool intel_connector_get_hw_state(struct intel_connector *connector)
4565 {
4566         enum pipe pipe = 0;
4567         struct intel_encoder *encoder = connector->encoder;
4568
4569         return encoder->get_hw_state(encoder, &pipe);
4570 }
4571
4572 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4573                                      struct intel_crtc_config *pipe_config)
4574 {
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576         struct intel_crtc *pipe_B_crtc =
4577                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4578
4579         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4580                       pipe_name(pipe), pipe_config->fdi_lanes);
4581         if (pipe_config->fdi_lanes > 4) {
4582                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4583                               pipe_name(pipe), pipe_config->fdi_lanes);
4584                 return false;
4585         }
4586
4587         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4588                 if (pipe_config->fdi_lanes > 2) {
4589                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4590                                       pipe_config->fdi_lanes);
4591                         return false;
4592                 } else {
4593                         return true;
4594                 }
4595         }
4596
4597         if (INTEL_INFO(dev)->num_pipes == 2)
4598                 return true;
4599
4600         /* Ivybridge 3 pipe is really complicated */
4601         switch (pipe) {
4602         case PIPE_A:
4603                 return true;
4604         case PIPE_B:
4605                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4606                     pipe_config->fdi_lanes > 2) {
4607                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4608                                       pipe_name(pipe), pipe_config->fdi_lanes);
4609                         return false;
4610                 }
4611                 return true;
4612         case PIPE_C:
4613                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4614                     pipe_B_crtc->config.fdi_lanes <= 2) {
4615                         if (pipe_config->fdi_lanes > 2) {
4616                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4617                                               pipe_name(pipe), pipe_config->fdi_lanes);
4618                                 return false;
4619                         }
4620                 } else {
4621                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4622                         return false;
4623                 }
4624                 return true;
4625         default:
4626                 BUG();
4627         }
4628 }
4629
4630 #define RETRY 1
4631 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4632                                        struct intel_crtc_config *pipe_config)
4633 {
4634         struct drm_device *dev = intel_crtc->base.dev;
4635         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4636         int lane, link_bw, fdi_dotclock;
4637         bool setup_ok, needs_recompute = false;
4638
4639 retry:
4640         /* FDI is a binary signal running at ~2.7GHz, encoding
4641          * each output octet as 10 bits. The actual frequency
4642          * is stored as a divider into a 100MHz clock, and the
4643          * mode pixel clock is stored in units of 1KHz.
4644          * Hence the bw of each lane in terms of the mode signal
4645          * is:
4646          */
4647         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4648
4649         fdi_dotclock = adjusted_mode->crtc_clock;
4650
4651         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4652                                            pipe_config->pipe_bpp);
4653
4654         pipe_config->fdi_lanes = lane;
4655
4656         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4657                                link_bw, &pipe_config->fdi_m_n);
4658
4659         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4660                                             intel_crtc->pipe, pipe_config);
4661         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4662                 pipe_config->pipe_bpp -= 2*3;
4663                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4664                               pipe_config->pipe_bpp);
4665                 needs_recompute = true;
4666                 pipe_config->bw_constrained = true;
4667
4668                 goto retry;
4669         }
4670
4671         if (needs_recompute)
4672                 return RETRY;
4673
4674         return setup_ok ? 0 : -EINVAL;
4675 }
4676
4677 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4678                                    struct intel_crtc_config *pipe_config)
4679 {
4680         pipe_config->ips_enabled = i915.enable_ips &&
4681                                    hsw_crtc_supports_ips(crtc) &&
4682                                    pipe_config->pipe_bpp <= 24;
4683 }
4684
4685 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4686                                      struct intel_crtc_config *pipe_config)
4687 {
4688         struct drm_device *dev = crtc->base.dev;
4689         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4690
4691         /* FIXME should check pixel clock limits on all platforms */
4692         if (INTEL_INFO(dev)->gen < 4) {
4693                 struct drm_i915_private *dev_priv = dev->dev_private;
4694                 int clock_limit =
4695                         dev_priv->display.get_display_clock_speed(dev);
4696
4697                 /*
4698                  * Enable pixel doubling when the dot clock
4699                  * is > 90% of the (display) core speed.
4700                  *
4701                  * GDG double wide on either pipe,
4702                  * otherwise pipe A only.
4703                  */
4704                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4705                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4706                         clock_limit *= 2;
4707                         pipe_config->double_wide = true;
4708                 }
4709
4710                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4711                         return -EINVAL;
4712         }
4713
4714         /*
4715          * Pipe horizontal size must be even in:
4716          * - DVO ganged mode
4717          * - LVDS dual channel mode
4718          * - Double wide pipe
4719          */
4720         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4721              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4722                 pipe_config->pipe_src_w &= ~1;
4723
4724         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4725          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4726          */
4727         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4728                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4729                 return -EINVAL;
4730
4731         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4732                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4733         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4734                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4735                  * for lvds. */
4736                 pipe_config->pipe_bpp = 8*3;
4737         }
4738
4739         if (HAS_IPS(dev))
4740                 hsw_compute_ips_config(crtc, pipe_config);
4741
4742         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4743          * clock survives for now. */
4744         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4745                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4746
4747         if (pipe_config->has_pch_encoder)
4748                 return ironlake_fdi_compute_config(crtc, pipe_config);
4749
4750         return 0;
4751 }
4752
4753 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4754 {
4755         return 400000; /* FIXME */
4756 }
4757
4758 static int i945_get_display_clock_speed(struct drm_device *dev)
4759 {
4760         return 400000;
4761 }
4762
4763 static int i915_get_display_clock_speed(struct drm_device *dev)
4764 {
4765         return 333000;
4766 }
4767
4768 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4769 {
4770         return 200000;
4771 }
4772
4773 static int pnv_get_display_clock_speed(struct drm_device *dev)
4774 {
4775         u16 gcfgc = 0;
4776
4777         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4778
4779         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4780         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4781                 return 267000;
4782         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4783                 return 333000;
4784         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4785                 return 444000;
4786         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4787                 return 200000;
4788         default:
4789                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4790         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4791                 return 133000;
4792         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4793                 return 167000;
4794         }
4795 }
4796
4797 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4798 {
4799         u16 gcfgc = 0;
4800
4801         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4802
4803         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4804                 return 133000;
4805         else {
4806                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4807                 case GC_DISPLAY_CLOCK_333_MHZ:
4808                         return 333000;
4809                 default:
4810                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4811                         return 190000;
4812                 }
4813         }
4814 }
4815
4816 static int i865_get_display_clock_speed(struct drm_device *dev)
4817 {
4818         return 266000;
4819 }
4820
4821 static int i855_get_display_clock_speed(struct drm_device *dev)
4822 {
4823         u16 hpllcc = 0;
4824         /* Assume that the hardware is in the high speed state.  This
4825          * should be the default.
4826          */
4827         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4828         case GC_CLOCK_133_200:
4829         case GC_CLOCK_100_200:
4830                 return 200000;
4831         case GC_CLOCK_166_250:
4832                 return 250000;
4833         case GC_CLOCK_100_133:
4834                 return 133000;
4835         }
4836
4837         /* Shouldn't happen */
4838         return 0;
4839 }
4840
4841 static int i830_get_display_clock_speed(struct drm_device *dev)
4842 {
4843         return 133000;
4844 }
4845
4846 static void
4847 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4848 {
4849         while (*num > DATA_LINK_M_N_MASK ||
4850                *den > DATA_LINK_M_N_MASK) {
4851                 *num >>= 1;
4852                 *den >>= 1;
4853         }
4854 }
4855
4856 static void compute_m_n(unsigned int m, unsigned int n,
4857                         uint32_t *ret_m, uint32_t *ret_n)
4858 {
4859         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4860         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4861         intel_reduce_m_n_ratio(ret_m, ret_n);
4862 }
4863
4864 void
4865 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4866                        int pixel_clock, int link_clock,
4867                        struct intel_link_m_n *m_n)
4868 {
4869         m_n->tu = 64;
4870
4871         compute_m_n(bits_per_pixel * pixel_clock,
4872                     link_clock * nlanes * 8,
4873                     &m_n->gmch_m, &m_n->gmch_n);
4874
4875         compute_m_n(pixel_clock, link_clock,
4876                     &m_n->link_m, &m_n->link_n);
4877 }
4878
4879 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4880 {
4881         if (i915.panel_use_ssc >= 0)
4882                 return i915.panel_use_ssc != 0;
4883         return dev_priv->vbt.lvds_use_ssc
4884                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4885 }
4886
4887 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4888 {
4889         struct drm_device *dev = crtc->dev;
4890         struct drm_i915_private *dev_priv = dev->dev_private;
4891         int refclk;
4892
4893         if (IS_VALLEYVIEW(dev)) {
4894                 refclk = 100000;
4895         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4896             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4897                 refclk = dev_priv->vbt.lvds_ssc_freq;
4898                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4899         } else if (!IS_GEN2(dev)) {
4900                 refclk = 96000;
4901         } else {
4902                 refclk = 48000;
4903         }
4904
4905         return refclk;
4906 }
4907
4908 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4909 {
4910         return (1 << dpll->n) << 16 | dpll->m2;
4911 }
4912
4913 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4914 {
4915         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4916 }
4917
4918 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4919                                      intel_clock_t *reduced_clock)
4920 {
4921         struct drm_device *dev = crtc->base.dev;
4922         struct drm_i915_private *dev_priv = dev->dev_private;
4923         int pipe = crtc->pipe;
4924         u32 fp, fp2 = 0;
4925
4926         if (IS_PINEVIEW(dev)) {
4927                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4928                 if (reduced_clock)
4929                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4930         } else {
4931                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4932                 if (reduced_clock)
4933                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4934         }
4935
4936         I915_WRITE(FP0(pipe), fp);
4937         crtc->config.dpll_hw_state.fp0 = fp;
4938
4939         crtc->lowfreq_avail = false;
4940         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4941             reduced_clock && i915.powersave) {
4942                 I915_WRITE(FP1(pipe), fp2);
4943                 crtc->config.dpll_hw_state.fp1 = fp2;
4944                 crtc->lowfreq_avail = true;
4945         } else {
4946                 I915_WRITE(FP1(pipe), fp);
4947                 crtc->config.dpll_hw_state.fp1 = fp;
4948         }
4949 }
4950
4951 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4952                 pipe)
4953 {
4954         u32 reg_val;
4955
4956         /*
4957          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4958          * and set it to a reasonable value instead.
4959          */
4960         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4961         reg_val &= 0xffffff00;
4962         reg_val |= 0x00000030;
4963         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4964
4965         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4966         reg_val &= 0x8cffffff;
4967         reg_val = 0x8c000000;
4968         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4969
4970         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4971         reg_val &= 0xffffff00;
4972         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4973
4974         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4975         reg_val &= 0x00ffffff;
4976         reg_val |= 0xb0000000;
4977         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4978 }
4979
4980 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4981                                          struct intel_link_m_n *m_n)
4982 {
4983         struct drm_device *dev = crtc->base.dev;
4984         struct drm_i915_private *dev_priv = dev->dev_private;
4985         int pipe = crtc->pipe;
4986
4987         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4988         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4989         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4990         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4991 }
4992
4993 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4994                                          struct intel_link_m_n *m_n)
4995 {
4996         struct drm_device *dev = crtc->base.dev;
4997         struct drm_i915_private *dev_priv = dev->dev_private;
4998         int pipe = crtc->pipe;
4999         enum transcoder transcoder = crtc->config.cpu_transcoder;
5000
5001         if (INTEL_INFO(dev)->gen >= 5) {
5002                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5003                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5004                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5005                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5006         } else {
5007                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5008                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5009                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5010                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5011         }
5012 }
5013
5014 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5015 {
5016         if (crtc->config.has_pch_encoder)
5017                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5018         else
5019                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5020 }
5021
5022 static void vlv_update_pll(struct intel_crtc *crtc)
5023 {
5024         struct drm_device *dev = crtc->base.dev;
5025         struct drm_i915_private *dev_priv = dev->dev_private;
5026         int pipe = crtc->pipe;
5027         u32 dpll, mdiv;
5028         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5029         u32 coreclk, reg_val, dpll_md;
5030
5031         mutex_lock(&dev_priv->dpio_lock);
5032
5033         bestn = crtc->config.dpll.n;
5034         bestm1 = crtc->config.dpll.m1;
5035         bestm2 = crtc->config.dpll.m2;
5036         bestp1 = crtc->config.dpll.p1;
5037         bestp2 = crtc->config.dpll.p2;
5038
5039         /* See eDP HDMI DPIO driver vbios notes doc */
5040
5041         /* PLL B needs special handling */
5042         if (pipe)
5043                 vlv_pllb_recal_opamp(dev_priv, pipe);
5044
5045         /* Set up Tx target for periodic Rcomp update */
5046         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5047
5048         /* Disable target IRef on PLL */
5049         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5050         reg_val &= 0x00ffffff;
5051         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5052
5053         /* Disable fast lock */
5054         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5055
5056         /* Set idtafcrecal before PLL is enabled */
5057         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5058         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5059         mdiv |= ((bestn << DPIO_N_SHIFT));
5060         mdiv |= (1 << DPIO_K_SHIFT);
5061
5062         /*
5063          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5064          * but we don't support that).
5065          * Note: don't use the DAC post divider as it seems unstable.
5066          */
5067         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5068         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5069
5070         mdiv |= DPIO_ENABLE_CALIBRATION;
5071         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5072
5073         /* Set HBR and RBR LPF coefficients */
5074         if (crtc->config.port_clock == 162000 ||
5075             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5076             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5077                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5078                                  0x009f0003);
5079         else
5080                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5081                                  0x00d0000f);
5082
5083         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5084             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5085                 /* Use SSC source */
5086                 if (!pipe)
5087                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5088                                          0x0df40000);
5089                 else
5090                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5091                                          0x0df70000);
5092         } else { /* HDMI or VGA */
5093                 /* Use bend source */
5094                 if (!pipe)
5095                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5096                                          0x0df70000);
5097                 else
5098                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5099                                          0x0df40000);
5100         }
5101
5102         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5103         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5104         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5105             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5106                 coreclk |= 0x01000000;
5107         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5108
5109         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5110
5111         /*
5112          * Enable DPIO clock input. We should never disable the reference
5113          * clock for pipe B, since VGA hotplug / manual detection depends
5114          * on it.
5115          */
5116         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5117                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5118         /* We should never disable this, set it here for state tracking */
5119         if (pipe == PIPE_B)
5120                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5121         dpll |= DPLL_VCO_ENABLE;
5122         crtc->config.dpll_hw_state.dpll = dpll;
5123
5124         dpll_md = (crtc->config.pixel_multiplier - 1)
5125                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5126         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5127
5128         if (crtc->config.has_dp_encoder)
5129                 intel_dp_set_m_n(crtc);
5130
5131         mutex_unlock(&dev_priv->dpio_lock);
5132 }
5133
5134 static void i9xx_update_pll(struct intel_crtc *crtc,
5135                             intel_clock_t *reduced_clock,
5136                             int num_connectors)
5137 {
5138         struct drm_device *dev = crtc->base.dev;
5139         struct drm_i915_private *dev_priv = dev->dev_private;
5140         u32 dpll;
5141         bool is_sdvo;
5142         struct dpll *clock = &crtc->config.dpll;
5143
5144         i9xx_update_pll_dividers(crtc, reduced_clock);
5145
5146         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5147                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5148
5149         dpll = DPLL_VGA_MODE_DIS;
5150
5151         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5152                 dpll |= DPLLB_MODE_LVDS;
5153         else
5154                 dpll |= DPLLB_MODE_DAC_SERIAL;
5155
5156         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5157                 dpll |= (crtc->config.pixel_multiplier - 1)
5158                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5159         }
5160
5161         if (is_sdvo)
5162                 dpll |= DPLL_SDVO_HIGH_SPEED;
5163
5164         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5165                 dpll |= DPLL_SDVO_HIGH_SPEED;
5166
5167         /* compute bitmask from p1 value */
5168         if (IS_PINEVIEW(dev))
5169                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5170         else {
5171                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5172                 if (IS_G4X(dev) && reduced_clock)
5173                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5174         }
5175         switch (clock->p2) {
5176         case 5:
5177                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5178                 break;
5179         case 7:
5180                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5181                 break;
5182         case 10:
5183                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5184                 break;
5185         case 14:
5186                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5187                 break;
5188         }
5189         if (INTEL_INFO(dev)->gen >= 4)
5190                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5191
5192         if (crtc->config.sdvo_tv_clock)
5193                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5194         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5195                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5196                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5197         else
5198                 dpll |= PLL_REF_INPUT_DREFCLK;
5199
5200         dpll |= DPLL_VCO_ENABLE;
5201         crtc->config.dpll_hw_state.dpll = dpll;
5202
5203         if (INTEL_INFO(dev)->gen >= 4) {
5204                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5205                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5206                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5207         }
5208
5209         if (crtc->config.has_dp_encoder)
5210                 intel_dp_set_m_n(crtc);
5211 }
5212
5213 static void i8xx_update_pll(struct intel_crtc *crtc,
5214                             intel_clock_t *reduced_clock,
5215                             int num_connectors)
5216 {
5217         struct drm_device *dev = crtc->base.dev;
5218         struct drm_i915_private *dev_priv = dev->dev_private;
5219         u32 dpll;
5220         struct dpll *clock = &crtc->config.dpll;
5221
5222         i9xx_update_pll_dividers(crtc, reduced_clock);
5223
5224         dpll = DPLL_VGA_MODE_DIS;
5225
5226         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5227                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5228         } else {
5229                 if (clock->p1 == 2)
5230                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5231                 else
5232                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5233                 if (clock->p2 == 4)
5234                         dpll |= PLL_P2_DIVIDE_BY_4;
5235         }
5236
5237         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5238                 dpll |= DPLL_DVO_2X_MODE;
5239
5240         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5241                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5242                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5243         else
5244                 dpll |= PLL_REF_INPUT_DREFCLK;
5245
5246         dpll |= DPLL_VCO_ENABLE;
5247         crtc->config.dpll_hw_state.dpll = dpll;
5248 }
5249
5250 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5251 {
5252         struct drm_device *dev = intel_crtc->base.dev;
5253         struct drm_i915_private *dev_priv = dev->dev_private;
5254         enum pipe pipe = intel_crtc->pipe;
5255         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5256         struct drm_display_mode *adjusted_mode =
5257                 &intel_crtc->config.adjusted_mode;
5258         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5259
5260         /* We need to be careful not to changed the adjusted mode, for otherwise
5261          * the hw state checker will get angry at the mismatch. */
5262         crtc_vtotal = adjusted_mode->crtc_vtotal;
5263         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5264
5265         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5266                 /* the chip adds 2 halflines automatically */
5267                 crtc_vtotal -= 1;
5268                 crtc_vblank_end -= 1;
5269                 vsyncshift = adjusted_mode->crtc_hsync_start
5270                              - adjusted_mode->crtc_htotal / 2;
5271         } else {
5272                 vsyncshift = 0;
5273         }
5274
5275         if (INTEL_INFO(dev)->gen > 3)
5276                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5277
5278         I915_WRITE(HTOTAL(cpu_transcoder),
5279                    (adjusted_mode->crtc_hdisplay - 1) |
5280                    ((adjusted_mode->crtc_htotal - 1) << 16));
5281         I915_WRITE(HBLANK(cpu_transcoder),
5282                    (adjusted_mode->crtc_hblank_start - 1) |
5283                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5284         I915_WRITE(HSYNC(cpu_transcoder),
5285                    (adjusted_mode->crtc_hsync_start - 1) |
5286                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5287
5288         I915_WRITE(VTOTAL(cpu_transcoder),
5289                    (adjusted_mode->crtc_vdisplay - 1) |
5290                    ((crtc_vtotal - 1) << 16));
5291         I915_WRITE(VBLANK(cpu_transcoder),
5292                    (adjusted_mode->crtc_vblank_start - 1) |
5293                    ((crtc_vblank_end - 1) << 16));
5294         I915_WRITE(VSYNC(cpu_transcoder),
5295                    (adjusted_mode->crtc_vsync_start - 1) |
5296                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5297
5298         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5299          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5300          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5301          * bits. */
5302         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5303             (pipe == PIPE_B || pipe == PIPE_C))
5304                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5305
5306         /* pipesrc controls the size that is scaled from, which should
5307          * always be the user's requested size.
5308          */
5309         I915_WRITE(PIPESRC(pipe),
5310                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5311                    (intel_crtc->config.pipe_src_h - 1));
5312 }
5313
5314 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5315                                    struct intel_crtc_config *pipe_config)
5316 {
5317         struct drm_device *dev = crtc->base.dev;
5318         struct drm_i915_private *dev_priv = dev->dev_private;
5319         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5320         uint32_t tmp;
5321
5322         tmp = I915_READ(HTOTAL(cpu_transcoder));
5323         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5324         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5325         tmp = I915_READ(HBLANK(cpu_transcoder));
5326         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5327         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5328         tmp = I915_READ(HSYNC(cpu_transcoder));
5329         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5330         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5331
5332         tmp = I915_READ(VTOTAL(cpu_transcoder));
5333         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5334         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5335         tmp = I915_READ(VBLANK(cpu_transcoder));
5336         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5337         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5338         tmp = I915_READ(VSYNC(cpu_transcoder));
5339         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5340         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5341
5342         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5343                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5344                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5345                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5346         }
5347
5348         tmp = I915_READ(PIPESRC(crtc->pipe));
5349         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5350         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5351
5352         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5353         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5354 }
5355
5356 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5357                                  struct intel_crtc_config *pipe_config)
5358 {
5359         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5360         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5361         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5362         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5363
5364         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5365         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5366         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5367         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5368
5369         mode->flags = pipe_config->adjusted_mode.flags;
5370
5371         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5372         mode->flags |= pipe_config->adjusted_mode.flags;
5373 }
5374
5375 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5376 {
5377         struct drm_device *dev = intel_crtc->base.dev;
5378         struct drm_i915_private *dev_priv = dev->dev_private;
5379         uint32_t pipeconf;
5380
5381         pipeconf = 0;
5382
5383         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5384             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5385                 pipeconf |= PIPECONF_ENABLE;
5386
5387         if (intel_crtc->config.double_wide)
5388                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5389
5390         /* only g4x and later have fancy bpc/dither controls */
5391         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5392                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5393                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5394                         pipeconf |= PIPECONF_DITHER_EN |
5395                                     PIPECONF_DITHER_TYPE_SP;
5396
5397                 switch (intel_crtc->config.pipe_bpp) {
5398                 case 18:
5399                         pipeconf |= PIPECONF_6BPC;
5400                         break;
5401                 case 24:
5402                         pipeconf |= PIPECONF_8BPC;
5403                         break;
5404                 case 30:
5405                         pipeconf |= PIPECONF_10BPC;
5406                         break;
5407                 default:
5408                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5409                         BUG();
5410                 }
5411         }
5412
5413         if (HAS_PIPE_CXSR(dev)) {
5414                 if (intel_crtc->lowfreq_avail) {
5415                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5416                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5417                 } else {
5418                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5419                 }
5420         }
5421
5422         if (!IS_GEN2(dev) &&
5423             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5424                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5425         else
5426                 pipeconf |= PIPECONF_PROGRESSIVE;
5427
5428         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5429                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5430
5431         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5432         POSTING_READ(PIPECONF(intel_crtc->pipe));
5433 }
5434
5435 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5436                               int x, int y,
5437                               struct drm_framebuffer *fb)
5438 {
5439         struct drm_device *dev = crtc->dev;
5440         struct drm_i915_private *dev_priv = dev->dev_private;
5441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5442         int pipe = intel_crtc->pipe;
5443         int plane = intel_crtc->plane;
5444         int refclk, num_connectors = 0;
5445         intel_clock_t clock, reduced_clock;
5446         u32 dspcntr;
5447         bool ok, has_reduced_clock = false;
5448         bool is_lvds = false, is_dsi = false;
5449         struct intel_encoder *encoder;
5450         const intel_limit_t *limit;
5451         int ret;
5452
5453         for_each_encoder_on_crtc(dev, crtc, encoder) {
5454                 switch (encoder->type) {
5455                 case INTEL_OUTPUT_LVDS:
5456                         is_lvds = true;
5457                         break;
5458                 case INTEL_OUTPUT_DSI:
5459                         is_dsi = true;
5460                         break;
5461                 }
5462
5463                 num_connectors++;
5464         }
5465
5466         if (is_dsi)
5467                 goto skip_dpll;
5468
5469         if (!intel_crtc->config.clock_set) {
5470                 refclk = i9xx_get_refclk(crtc, num_connectors);
5471
5472                 /*
5473                  * Returns a set of divisors for the desired target clock with
5474                  * the given refclk, or FALSE.  The returned values represent
5475                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5476                  * 2) / p1 / p2.
5477                  */
5478                 limit = intel_limit(crtc, refclk);
5479                 ok = dev_priv->display.find_dpll(limit, crtc,
5480                                                  intel_crtc->config.port_clock,
5481                                                  refclk, NULL, &clock);
5482                 if (!ok) {
5483                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5484                         return -EINVAL;
5485                 }
5486
5487                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5488                         /*
5489                          * Ensure we match the reduced clock's P to the target
5490                          * clock.  If the clocks don't match, we can't switch
5491                          * the display clock by using the FP0/FP1. In such case
5492                          * we will disable the LVDS downclock feature.
5493                          */
5494                         has_reduced_clock =
5495                                 dev_priv->display.find_dpll(limit, crtc,
5496                                                             dev_priv->lvds_downclock,
5497                                                             refclk, &clock,
5498                                                             &reduced_clock);
5499                 }
5500                 /* Compat-code for transition, will disappear. */
5501                 intel_crtc->config.dpll.n = clock.n;
5502                 intel_crtc->config.dpll.m1 = clock.m1;
5503                 intel_crtc->config.dpll.m2 = clock.m2;
5504                 intel_crtc->config.dpll.p1 = clock.p1;
5505                 intel_crtc->config.dpll.p2 = clock.p2;
5506         }
5507
5508         if (IS_GEN2(dev)) {
5509                 i8xx_update_pll(intel_crtc,
5510                                 has_reduced_clock ? &reduced_clock : NULL,
5511                                 num_connectors);
5512         } else if (IS_VALLEYVIEW(dev)) {
5513                 vlv_update_pll(intel_crtc);
5514         } else {
5515                 i9xx_update_pll(intel_crtc,
5516                                 has_reduced_clock ? &reduced_clock : NULL,
5517                                 num_connectors);
5518         }
5519
5520 skip_dpll:
5521         /* Set up the display plane register */
5522         dspcntr = DISPPLANE_GAMMA_ENABLE;
5523
5524         if (!IS_VALLEYVIEW(dev)) {
5525                 if (pipe == 0)
5526                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5527                 else
5528                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5529         }
5530
5531         intel_set_pipe_timings(intel_crtc);
5532
5533         /* pipesrc and dspsize control the size that is scaled from,
5534          * which should always be the user's requested size.
5535          */
5536         I915_WRITE(DSPSIZE(plane),
5537                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5538                    (intel_crtc->config.pipe_src_w - 1));
5539         I915_WRITE(DSPPOS(plane), 0);
5540
5541         i9xx_set_pipeconf(intel_crtc);
5542
5543         I915_WRITE(DSPCNTR(plane), dspcntr);
5544         POSTING_READ(DSPCNTR(plane));
5545
5546         ret = intel_pipe_set_base(crtc, x, y, fb);
5547
5548         return ret;
5549 }
5550
5551 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5552                                  struct intel_crtc_config *pipe_config)
5553 {
5554         struct drm_device *dev = crtc->base.dev;
5555         struct drm_i915_private *dev_priv = dev->dev_private;
5556         uint32_t tmp;
5557
5558         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5559                 return;
5560
5561         tmp = I915_READ(PFIT_CONTROL);
5562         if (!(tmp & PFIT_ENABLE))
5563                 return;
5564
5565         /* Check whether the pfit is attached to our pipe. */
5566         if (INTEL_INFO(dev)->gen < 4) {
5567                 if (crtc->pipe != PIPE_B)
5568                         return;
5569         } else {
5570                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5571                         return;
5572         }
5573
5574         pipe_config->gmch_pfit.control = tmp;
5575         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5576         if (INTEL_INFO(dev)->gen < 5)
5577                 pipe_config->gmch_pfit.lvds_border_bits =
5578                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5579 }
5580
5581 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5582                                struct intel_crtc_config *pipe_config)
5583 {
5584         struct drm_device *dev = crtc->base.dev;
5585         struct drm_i915_private *dev_priv = dev->dev_private;
5586         int pipe = pipe_config->cpu_transcoder;
5587         intel_clock_t clock;
5588         u32 mdiv;
5589         int refclk = 100000;
5590
5591         mutex_lock(&dev_priv->dpio_lock);
5592         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5593         mutex_unlock(&dev_priv->dpio_lock);
5594
5595         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5596         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5597         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5598         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5599         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5600
5601         vlv_clock(refclk, &clock);
5602
5603         /* clock.dot is the fast clock */
5604         pipe_config->port_clock = clock.dot / 5;
5605 }
5606
5607 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5608                                  struct intel_crtc_config *pipe_config)
5609 {
5610         struct drm_device *dev = crtc->base.dev;
5611         struct drm_i915_private *dev_priv = dev->dev_private;
5612         uint32_t tmp;
5613
5614         if (!intel_display_power_enabled(dev_priv,
5615                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5616                 return false;
5617
5618         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5619         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5620
5621         tmp = I915_READ(PIPECONF(crtc->pipe));
5622         if (!(tmp & PIPECONF_ENABLE))
5623                 return false;
5624
5625         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5626                 switch (tmp & PIPECONF_BPC_MASK) {
5627                 case PIPECONF_6BPC:
5628                         pipe_config->pipe_bpp = 18;
5629                         break;
5630                 case PIPECONF_8BPC:
5631                         pipe_config->pipe_bpp = 24;
5632                         break;
5633                 case PIPECONF_10BPC:
5634                         pipe_config->pipe_bpp = 30;
5635                         break;
5636                 default:
5637                         break;
5638                 }
5639         }
5640
5641         if (INTEL_INFO(dev)->gen < 4)
5642                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5643
5644         intel_get_pipe_timings(crtc, pipe_config);
5645
5646         i9xx_get_pfit_config(crtc, pipe_config);
5647
5648         if (INTEL_INFO(dev)->gen >= 4) {
5649                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5650                 pipe_config->pixel_multiplier =
5651                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5652                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5653                 pipe_config->dpll_hw_state.dpll_md = tmp;
5654         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5655                 tmp = I915_READ(DPLL(crtc->pipe));
5656                 pipe_config->pixel_multiplier =
5657                         ((tmp & SDVO_MULTIPLIER_MASK)
5658                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5659         } else {
5660                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5661                  * port and will be fixed up in the encoder->get_config
5662                  * function. */
5663                 pipe_config->pixel_multiplier = 1;
5664         }
5665         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5666         if (!IS_VALLEYVIEW(dev)) {
5667                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5668                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5669         } else {
5670                 /* Mask out read-only status bits. */
5671                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5672                                                      DPLL_PORTC_READY_MASK |
5673                                                      DPLL_PORTB_READY_MASK);
5674         }
5675
5676         if (IS_VALLEYVIEW(dev))
5677                 vlv_crtc_clock_get(crtc, pipe_config);
5678         else
5679                 i9xx_crtc_clock_get(crtc, pipe_config);
5680
5681         return true;
5682 }
5683
5684 static void ironlake_init_pch_refclk(struct drm_device *dev)
5685 {
5686         struct drm_i915_private *dev_priv = dev->dev_private;
5687         struct drm_mode_config *mode_config = &dev->mode_config;
5688         struct intel_encoder *encoder;
5689         u32 val, final;
5690         bool has_lvds = false;
5691         bool has_cpu_edp = false;
5692         bool has_panel = false;
5693         bool has_ck505 = false;
5694         bool can_ssc = false;
5695
5696         /* We need to take the global config into account */
5697         list_for_each_entry(encoder, &mode_config->encoder_list,
5698                             base.head) {
5699                 switch (encoder->type) {
5700                 case INTEL_OUTPUT_LVDS:
5701                         has_panel = true;
5702                         has_lvds = true;
5703                         break;
5704                 case INTEL_OUTPUT_EDP:
5705                         has_panel = true;
5706                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5707                                 has_cpu_edp = true;
5708                         break;
5709                 }
5710         }
5711
5712         if (HAS_PCH_IBX(dev)) {
5713                 has_ck505 = dev_priv->vbt.display_clock_mode;
5714                 can_ssc = has_ck505;
5715         } else {
5716                 has_ck505 = false;
5717                 can_ssc = true;
5718         }
5719
5720         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5721                       has_panel, has_lvds, has_ck505);
5722
5723         /* Ironlake: try to setup display ref clock before DPLL
5724          * enabling. This is only under driver's control after
5725          * PCH B stepping, previous chipset stepping should be
5726          * ignoring this setting.
5727          */
5728         val = I915_READ(PCH_DREF_CONTROL);
5729
5730         /* As we must carefully and slowly disable/enable each source in turn,
5731          * compute the final state we want first and check if we need to
5732          * make any changes at all.
5733          */
5734         final = val;
5735         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5736         if (has_ck505)
5737                 final |= DREF_NONSPREAD_CK505_ENABLE;
5738         else
5739                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5740
5741         final &= ~DREF_SSC_SOURCE_MASK;
5742         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5743         final &= ~DREF_SSC1_ENABLE;
5744
5745         if (has_panel) {
5746                 final |= DREF_SSC_SOURCE_ENABLE;
5747
5748                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5749                         final |= DREF_SSC1_ENABLE;
5750
5751                 if (has_cpu_edp) {
5752                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5753                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5754                         else
5755                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5756                 } else
5757                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5758         } else {
5759                 final |= DREF_SSC_SOURCE_DISABLE;
5760                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5761         }
5762
5763         if (final == val)
5764                 return;
5765
5766         /* Always enable nonspread source */
5767         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5768
5769         if (has_ck505)
5770                 val |= DREF_NONSPREAD_CK505_ENABLE;
5771         else
5772                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5773
5774         if (has_panel) {
5775                 val &= ~DREF_SSC_SOURCE_MASK;
5776                 val |= DREF_SSC_SOURCE_ENABLE;
5777
5778                 /* SSC must be turned on before enabling the CPU output  */
5779                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5780                         DRM_DEBUG_KMS("Using SSC on panel\n");
5781                         val |= DREF_SSC1_ENABLE;
5782                 } else
5783                         val &= ~DREF_SSC1_ENABLE;
5784
5785                 /* Get SSC going before enabling the outputs */
5786                 I915_WRITE(PCH_DREF_CONTROL, val);
5787                 POSTING_READ(PCH_DREF_CONTROL);
5788                 udelay(200);
5789
5790                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5791
5792                 /* Enable CPU source on CPU attached eDP */
5793                 if (has_cpu_edp) {
5794                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5795                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5796                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5797                         }
5798                         else
5799                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5800                 } else
5801                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5802
5803                 I915_WRITE(PCH_DREF_CONTROL, val);
5804                 POSTING_READ(PCH_DREF_CONTROL);
5805                 udelay(200);
5806         } else {
5807                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5808
5809                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5810
5811                 /* Turn off CPU output */
5812                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5813
5814                 I915_WRITE(PCH_DREF_CONTROL, val);
5815                 POSTING_READ(PCH_DREF_CONTROL);
5816                 udelay(200);
5817
5818                 /* Turn off the SSC source */
5819                 val &= ~DREF_SSC_SOURCE_MASK;
5820                 val |= DREF_SSC_SOURCE_DISABLE;
5821
5822                 /* Turn off SSC1 */
5823                 val &= ~DREF_SSC1_ENABLE;
5824
5825                 I915_WRITE(PCH_DREF_CONTROL, val);
5826                 POSTING_READ(PCH_DREF_CONTROL);
5827                 udelay(200);
5828         }
5829
5830         BUG_ON(val != final);
5831 }
5832
5833 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5834 {
5835         uint32_t tmp;
5836
5837         tmp = I915_READ(SOUTH_CHICKEN2);
5838         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5839         I915_WRITE(SOUTH_CHICKEN2, tmp);
5840
5841         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5842                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5843                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5844
5845         tmp = I915_READ(SOUTH_CHICKEN2);
5846         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5847         I915_WRITE(SOUTH_CHICKEN2, tmp);
5848
5849         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5850                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5851                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5852 }
5853
5854 /* WaMPhyProgramming:hsw */
5855 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5856 {
5857         uint32_t tmp;
5858
5859         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5860         tmp &= ~(0xFF << 24);
5861         tmp |= (0x12 << 24);
5862         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5863
5864         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5865         tmp |= (1 << 11);
5866         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5867
5868         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5869         tmp |= (1 << 11);
5870         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5871
5872         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5873         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5874         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5875
5876         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5877         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5878         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5879
5880         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5881         tmp &= ~(7 << 13);
5882         tmp |= (5 << 13);
5883         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5884
5885         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5886         tmp &= ~(7 << 13);
5887         tmp |= (5 << 13);
5888         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5889
5890         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5891         tmp &= ~0xFF;
5892         tmp |= 0x1C;
5893         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5894
5895         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5896         tmp &= ~0xFF;
5897         tmp |= 0x1C;
5898         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5899
5900         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5901         tmp &= ~(0xFF << 16);
5902         tmp |= (0x1C << 16);
5903         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5904
5905         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5906         tmp &= ~(0xFF << 16);
5907         tmp |= (0x1C << 16);
5908         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5909
5910         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5911         tmp |= (1 << 27);
5912         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5913
5914         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5915         tmp |= (1 << 27);
5916         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5917
5918         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5919         tmp &= ~(0xF << 28);
5920         tmp |= (4 << 28);
5921         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5922
5923         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5924         tmp &= ~(0xF << 28);
5925         tmp |= (4 << 28);
5926         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5927 }
5928
5929 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5930  * Programming" based on the parameters passed:
5931  * - Sequence to enable CLKOUT_DP
5932  * - Sequence to enable CLKOUT_DP without spread
5933  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5934  */
5935 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5936                                  bool with_fdi)
5937 {
5938         struct drm_i915_private *dev_priv = dev->dev_private;
5939         uint32_t reg, tmp;
5940
5941         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5942                 with_spread = true;
5943         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5944                  with_fdi, "LP PCH doesn't have FDI\n"))
5945                 with_fdi = false;
5946
5947         mutex_lock(&dev_priv->dpio_lock);
5948
5949         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5950         tmp &= ~SBI_SSCCTL_DISABLE;
5951         tmp |= SBI_SSCCTL_PATHALT;
5952         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5953
5954         udelay(24);
5955
5956         if (with_spread) {
5957                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5958                 tmp &= ~SBI_SSCCTL_PATHALT;
5959                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5960
5961                 if (with_fdi) {
5962                         lpt_reset_fdi_mphy(dev_priv);
5963                         lpt_program_fdi_mphy(dev_priv);
5964                 }
5965         }
5966
5967         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5968                SBI_GEN0 : SBI_DBUFF0;
5969         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5970         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5971         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5972
5973         mutex_unlock(&dev_priv->dpio_lock);
5974 }
5975
5976 /* Sequence to disable CLKOUT_DP */
5977 static void lpt_disable_clkout_dp(struct drm_device *dev)
5978 {
5979         struct drm_i915_private *dev_priv = dev->dev_private;
5980         uint32_t reg, tmp;
5981
5982         mutex_lock(&dev_priv->dpio_lock);
5983
5984         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5985                SBI_GEN0 : SBI_DBUFF0;
5986         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5987         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5988         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5989
5990         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5991         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5992                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5993                         tmp |= SBI_SSCCTL_PATHALT;
5994                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5995                         udelay(32);
5996                 }
5997                 tmp |= SBI_SSCCTL_DISABLE;
5998                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5999         }
6000
6001         mutex_unlock(&dev_priv->dpio_lock);
6002 }
6003
6004 static void lpt_init_pch_refclk(struct drm_device *dev)
6005 {
6006         struct drm_mode_config *mode_config = &dev->mode_config;
6007         struct intel_encoder *encoder;
6008         bool has_vga = false;
6009
6010         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6011                 switch (encoder->type) {
6012                 case INTEL_OUTPUT_ANALOG:
6013                         has_vga = true;
6014                         break;
6015                 }
6016         }
6017
6018         if (has_vga)
6019                 lpt_enable_clkout_dp(dev, true, true);
6020         else
6021                 lpt_disable_clkout_dp(dev);
6022 }
6023
6024 /*
6025  * Initialize reference clocks when the driver loads
6026  */
6027 void intel_init_pch_refclk(struct drm_device *dev)
6028 {
6029         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6030                 ironlake_init_pch_refclk(dev);
6031         else if (HAS_PCH_LPT(dev))
6032                 lpt_init_pch_refclk(dev);
6033 }
6034
6035 static int ironlake_get_refclk(struct drm_crtc *crtc)
6036 {
6037         struct drm_device *dev = crtc->dev;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039         struct intel_encoder *encoder;
6040         int num_connectors = 0;
6041         bool is_lvds = false;
6042
6043         for_each_encoder_on_crtc(dev, crtc, encoder) {
6044                 switch (encoder->type) {
6045                 case INTEL_OUTPUT_LVDS:
6046                         is_lvds = true;
6047                         break;
6048                 }
6049                 num_connectors++;
6050         }
6051
6052         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6053                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6054                               dev_priv->vbt.lvds_ssc_freq);
6055                 return dev_priv->vbt.lvds_ssc_freq;
6056         }
6057
6058         return 120000;
6059 }
6060
6061 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6062 {
6063         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065         int pipe = intel_crtc->pipe;
6066         uint32_t val;
6067
6068         val = 0;
6069
6070         switch (intel_crtc->config.pipe_bpp) {
6071         case 18:
6072                 val |= PIPECONF_6BPC;
6073                 break;
6074         case 24:
6075                 val |= PIPECONF_8BPC;
6076                 break;
6077         case 30:
6078                 val |= PIPECONF_10BPC;
6079                 break;
6080         case 36:
6081                 val |= PIPECONF_12BPC;
6082                 break;
6083         default:
6084                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6085                 BUG();
6086         }
6087
6088         if (intel_crtc->config.dither)
6089                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6090
6091         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6092                 val |= PIPECONF_INTERLACED_ILK;
6093         else
6094                 val |= PIPECONF_PROGRESSIVE;
6095
6096         if (intel_crtc->config.limited_color_range)
6097                 val |= PIPECONF_COLOR_RANGE_SELECT;
6098
6099         I915_WRITE(PIPECONF(pipe), val);
6100         POSTING_READ(PIPECONF(pipe));
6101 }
6102
6103 /*
6104  * Set up the pipe CSC unit.
6105  *
6106  * Currently only full range RGB to limited range RGB conversion
6107  * is supported, but eventually this should handle various
6108  * RGB<->YCbCr scenarios as well.
6109  */
6110 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6111 {
6112         struct drm_device *dev = crtc->dev;
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6115         int pipe = intel_crtc->pipe;
6116         uint16_t coeff = 0x7800; /* 1.0 */
6117
6118         /*
6119          * TODO: Check what kind of values actually come out of the pipe
6120          * with these coeff/postoff values and adjust to get the best
6121          * accuracy. Perhaps we even need to take the bpc value into
6122          * consideration.
6123          */
6124
6125         if (intel_crtc->config.limited_color_range)
6126                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6127
6128         /*
6129          * GY/GU and RY/RU should be the other way around according
6130          * to BSpec, but reality doesn't agree. Just set them up in
6131          * a way that results in the correct picture.
6132          */
6133         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6134         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6135
6136         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6137         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6138
6139         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6140         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6141
6142         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6143         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6144         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6145
6146         if (INTEL_INFO(dev)->gen > 6) {
6147                 uint16_t postoff = 0;
6148
6149                 if (intel_crtc->config.limited_color_range)
6150                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6151
6152                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6153                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6154                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6155
6156                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6157         } else {
6158                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6159
6160                 if (intel_crtc->config.limited_color_range)
6161                         mode |= CSC_BLACK_SCREEN_OFFSET;
6162
6163                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6164         }
6165 }
6166
6167 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6168 {
6169         struct drm_device *dev = crtc->dev;
6170         struct drm_i915_private *dev_priv = dev->dev_private;
6171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6172         enum pipe pipe = intel_crtc->pipe;
6173         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6174         uint32_t val;
6175
6176         val = 0;
6177
6178         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6179                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6180
6181         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6182                 val |= PIPECONF_INTERLACED_ILK;
6183         else
6184                 val |= PIPECONF_PROGRESSIVE;
6185
6186         I915_WRITE(PIPECONF(cpu_transcoder), val);
6187         POSTING_READ(PIPECONF(cpu_transcoder));
6188
6189         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6190         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6191
6192         if (IS_BROADWELL(dev)) {
6193                 val = 0;
6194
6195                 switch (intel_crtc->config.pipe_bpp) {
6196                 case 18:
6197                         val |= PIPEMISC_DITHER_6_BPC;
6198                         break;
6199                 case 24:
6200                         val |= PIPEMISC_DITHER_8_BPC;
6201                         break;
6202                 case 30:
6203                         val |= PIPEMISC_DITHER_10_BPC;
6204                         break;
6205                 case 36:
6206                         val |= PIPEMISC_DITHER_12_BPC;
6207                         break;
6208                 default:
6209                         /* Case prevented by pipe_config_set_bpp. */
6210                         BUG();
6211                 }
6212
6213                 if (intel_crtc->config.dither)
6214                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6215
6216                 I915_WRITE(PIPEMISC(pipe), val);
6217         }
6218 }
6219
6220 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6221                                     intel_clock_t *clock,
6222                                     bool *has_reduced_clock,
6223                                     intel_clock_t *reduced_clock)
6224 {
6225         struct drm_device *dev = crtc->dev;
6226         struct drm_i915_private *dev_priv = dev->dev_private;
6227         struct intel_encoder *intel_encoder;
6228         int refclk;
6229         const intel_limit_t *limit;
6230         bool ret, is_lvds = false;
6231
6232         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6233                 switch (intel_encoder->type) {
6234                 case INTEL_OUTPUT_LVDS:
6235                         is_lvds = true;
6236                         break;
6237                 }
6238         }
6239
6240         refclk = ironlake_get_refclk(crtc);
6241
6242         /*
6243          * Returns a set of divisors for the desired target clock with the given
6244          * refclk, or FALSE.  The returned values represent the clock equation:
6245          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6246          */
6247         limit = intel_limit(crtc, refclk);
6248         ret = dev_priv->display.find_dpll(limit, crtc,
6249                                           to_intel_crtc(crtc)->config.port_clock,
6250                                           refclk, NULL, clock);
6251         if (!ret)
6252                 return false;
6253
6254         if (is_lvds && dev_priv->lvds_downclock_avail) {
6255                 /*
6256                  * Ensure we match the reduced clock's P to the target clock.
6257                  * If the clocks don't match, we can't switch the display clock
6258                  * by using the FP0/FP1. In such case we will disable the LVDS
6259                  * downclock feature.
6260                 */
6261                 *has_reduced_clock =
6262                         dev_priv->display.find_dpll(limit, crtc,
6263                                                     dev_priv->lvds_downclock,
6264                                                     refclk, clock,
6265                                                     reduced_clock);
6266         }
6267
6268         return true;
6269 }
6270
6271 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6272 {
6273         /*
6274          * Account for spread spectrum to avoid
6275          * oversubscribing the link. Max center spread
6276          * is 2.5%; use 5% for safety's sake.
6277          */
6278         u32 bps = target_clock * bpp * 21 / 20;
6279         return DIV_ROUND_UP(bps, link_bw * 8);
6280 }
6281
6282 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6283 {
6284         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6285 }
6286
6287 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6288                                       u32 *fp,
6289                                       intel_clock_t *reduced_clock, u32 *fp2)
6290 {
6291         struct drm_crtc *crtc = &intel_crtc->base;
6292         struct drm_device *dev = crtc->dev;
6293         struct drm_i915_private *dev_priv = dev->dev_private;
6294         struct intel_encoder *intel_encoder;
6295         uint32_t dpll;
6296         int factor, num_connectors = 0;
6297         bool is_lvds = false, is_sdvo = false;
6298
6299         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6300                 switch (intel_encoder->type) {
6301                 case INTEL_OUTPUT_LVDS:
6302                         is_lvds = true;
6303                         break;
6304                 case INTEL_OUTPUT_SDVO:
6305                 case INTEL_OUTPUT_HDMI:
6306                         is_sdvo = true;
6307                         break;
6308                 }
6309
6310                 num_connectors++;
6311         }
6312
6313         /* Enable autotuning of the PLL clock (if permissible) */
6314         factor = 21;
6315         if (is_lvds) {
6316                 if ((intel_panel_use_ssc(dev_priv) &&
6317                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6318                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6319                         factor = 25;
6320         } else if (intel_crtc->config.sdvo_tv_clock)
6321                 factor = 20;
6322
6323         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6324                 *fp |= FP_CB_TUNE;
6325
6326         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6327                 *fp2 |= FP_CB_TUNE;
6328
6329         dpll = 0;
6330
6331         if (is_lvds)
6332                 dpll |= DPLLB_MODE_LVDS;
6333         else
6334                 dpll |= DPLLB_MODE_DAC_SERIAL;
6335
6336         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6337                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6338
6339         if (is_sdvo)
6340                 dpll |= DPLL_SDVO_HIGH_SPEED;
6341         if (intel_crtc->config.has_dp_encoder)
6342                 dpll |= DPLL_SDVO_HIGH_SPEED;
6343
6344         /* compute bitmask from p1 value */
6345         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6346         /* also FPA1 */
6347         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6348
6349         switch (intel_crtc->config.dpll.p2) {
6350         case 5:
6351                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6352                 break;
6353         case 7:
6354                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6355                 break;
6356         case 10:
6357                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6358                 break;
6359         case 14:
6360                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6361                 break;
6362         }
6363
6364         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6365                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6366         else
6367                 dpll |= PLL_REF_INPUT_DREFCLK;
6368
6369         return dpll | DPLL_VCO_ENABLE;
6370 }
6371
6372 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6373                                   int x, int y,
6374                                   struct drm_framebuffer *fb)
6375 {
6376         struct drm_device *dev = crtc->dev;
6377         struct drm_i915_private *dev_priv = dev->dev_private;
6378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379         int pipe = intel_crtc->pipe;
6380         int plane = intel_crtc->plane;
6381         int num_connectors = 0;
6382         intel_clock_t clock, reduced_clock;
6383         u32 dpll = 0, fp = 0, fp2 = 0;
6384         bool ok, has_reduced_clock = false;
6385         bool is_lvds = false;
6386         struct intel_encoder *encoder;
6387         struct intel_shared_dpll *pll;
6388         int ret;
6389
6390         for_each_encoder_on_crtc(dev, crtc, encoder) {
6391                 switch (encoder->type) {
6392                 case INTEL_OUTPUT_LVDS:
6393                         is_lvds = true;
6394                         break;
6395                 }
6396
6397                 num_connectors++;
6398         }
6399
6400         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6401              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6402
6403         ok = ironlake_compute_clocks(crtc, &clock,
6404                                      &has_reduced_clock, &reduced_clock);
6405         if (!ok && !intel_crtc->config.clock_set) {
6406                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6407                 return -EINVAL;
6408         }
6409         /* Compat-code for transition, will disappear. */
6410         if (!intel_crtc->config.clock_set) {
6411                 intel_crtc->config.dpll.n = clock.n;
6412                 intel_crtc->config.dpll.m1 = clock.m1;
6413                 intel_crtc->config.dpll.m2 = clock.m2;
6414                 intel_crtc->config.dpll.p1 = clock.p1;
6415                 intel_crtc->config.dpll.p2 = clock.p2;
6416         }
6417
6418         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6419         if (intel_crtc->config.has_pch_encoder) {
6420                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6421                 if (has_reduced_clock)
6422                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6423
6424                 dpll = ironlake_compute_dpll(intel_crtc,
6425                                              &fp, &reduced_clock,
6426                                              has_reduced_clock ? &fp2 : NULL);
6427
6428                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6429                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6430                 if (has_reduced_clock)
6431                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6432                 else
6433                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6434
6435                 pll = intel_get_shared_dpll(intel_crtc);
6436                 if (pll == NULL) {
6437                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6438                                          pipe_name(pipe));
6439                         return -EINVAL;
6440                 }
6441         } else
6442                 intel_put_shared_dpll(intel_crtc);
6443
6444         if (intel_crtc->config.has_dp_encoder)
6445                 intel_dp_set_m_n(intel_crtc);
6446
6447         if (is_lvds && has_reduced_clock && i915.powersave)
6448                 intel_crtc->lowfreq_avail = true;
6449         else
6450                 intel_crtc->lowfreq_avail = false;
6451
6452         intel_set_pipe_timings(intel_crtc);
6453
6454         if (intel_crtc->config.has_pch_encoder) {
6455                 intel_cpu_transcoder_set_m_n(intel_crtc,
6456                                              &intel_crtc->config.fdi_m_n);
6457         }
6458
6459         ironlake_set_pipeconf(crtc);
6460
6461         /* Set up the display plane register */
6462         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6463         POSTING_READ(DSPCNTR(plane));
6464
6465         ret = intel_pipe_set_base(crtc, x, y, fb);
6466
6467         return ret;
6468 }
6469
6470 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6471                                          struct intel_link_m_n *m_n)
6472 {
6473         struct drm_device *dev = crtc->base.dev;
6474         struct drm_i915_private *dev_priv = dev->dev_private;
6475         enum pipe pipe = crtc->pipe;
6476
6477         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6478         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6479         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6480                 & ~TU_SIZE_MASK;
6481         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6482         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6483                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6484 }
6485
6486 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6487                                          enum transcoder transcoder,
6488                                          struct intel_link_m_n *m_n)
6489 {
6490         struct drm_device *dev = crtc->base.dev;
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492         enum pipe pipe = crtc->pipe;
6493
6494         if (INTEL_INFO(dev)->gen >= 5) {
6495                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6496                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6497                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6498                         & ~TU_SIZE_MASK;
6499                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6500                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6501                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6502         } else {
6503                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6504                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6505                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6506                         & ~TU_SIZE_MASK;
6507                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6508                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6509                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6510         }
6511 }
6512
6513 void intel_dp_get_m_n(struct intel_crtc *crtc,
6514                       struct intel_crtc_config *pipe_config)
6515 {
6516         if (crtc->config.has_pch_encoder)
6517                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6518         else
6519                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6520                                              &pipe_config->dp_m_n);
6521 }
6522
6523 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6524                                         struct intel_crtc_config *pipe_config)
6525 {
6526         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6527                                      &pipe_config->fdi_m_n);
6528 }
6529
6530 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6531                                      struct intel_crtc_config *pipe_config)
6532 {
6533         struct drm_device *dev = crtc->base.dev;
6534         struct drm_i915_private *dev_priv = dev->dev_private;
6535         uint32_t tmp;
6536
6537         tmp = I915_READ(PF_CTL(crtc->pipe));
6538
6539         if (tmp & PF_ENABLE) {
6540                 pipe_config->pch_pfit.enabled = true;
6541                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6542                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6543
6544                 /* We currently do not free assignements of panel fitters on
6545                  * ivb/hsw (since we don't use the higher upscaling modes which
6546                  * differentiates them) so just WARN about this case for now. */
6547                 if (IS_GEN7(dev)) {
6548                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6549                                 PF_PIPE_SEL_IVB(crtc->pipe));
6550                 }
6551         }
6552 }
6553
6554 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6555                                      struct intel_crtc_config *pipe_config)
6556 {
6557         struct drm_device *dev = crtc->base.dev;
6558         struct drm_i915_private *dev_priv = dev->dev_private;
6559         uint32_t tmp;
6560
6561         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6562         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6563
6564         tmp = I915_READ(PIPECONF(crtc->pipe));
6565         if (!(tmp & PIPECONF_ENABLE))
6566                 return false;
6567
6568         switch (tmp & PIPECONF_BPC_MASK) {
6569         case PIPECONF_6BPC:
6570                 pipe_config->pipe_bpp = 18;
6571                 break;
6572         case PIPECONF_8BPC:
6573                 pipe_config->pipe_bpp = 24;
6574                 break;
6575         case PIPECONF_10BPC:
6576                 pipe_config->pipe_bpp = 30;
6577                 break;
6578         case PIPECONF_12BPC:
6579                 pipe_config->pipe_bpp = 36;
6580                 break;
6581         default:
6582                 break;
6583         }
6584
6585         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6586                 struct intel_shared_dpll *pll;
6587
6588                 pipe_config->has_pch_encoder = true;
6589
6590                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6591                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6592                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6593
6594                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6595
6596                 if (HAS_PCH_IBX(dev_priv->dev)) {
6597                         pipe_config->shared_dpll =
6598                                 (enum intel_dpll_id) crtc->pipe;
6599                 } else {
6600                         tmp = I915_READ(PCH_DPLL_SEL);
6601                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6602                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6603                         else
6604                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6605                 }
6606
6607                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6608
6609                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6610                                            &pipe_config->dpll_hw_state));
6611
6612                 tmp = pipe_config->dpll_hw_state.dpll;
6613                 pipe_config->pixel_multiplier =
6614                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6615                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6616
6617                 ironlake_pch_clock_get(crtc, pipe_config);
6618         } else {
6619                 pipe_config->pixel_multiplier = 1;
6620         }
6621
6622         intel_get_pipe_timings(crtc, pipe_config);
6623
6624         ironlake_get_pfit_config(crtc, pipe_config);
6625
6626         return true;
6627 }
6628
6629 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6630 {
6631         struct drm_device *dev = dev_priv->dev;
6632         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6633         struct intel_crtc *crtc;
6634         unsigned long irqflags;
6635         uint32_t val;
6636
6637         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6638                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6639                      pipe_name(crtc->pipe));
6640
6641         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6642         WARN(plls->spll_refcount, "SPLL enabled\n");
6643         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6644         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6645         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6646         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6647              "CPU PWM1 enabled\n");
6648         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6649              "CPU PWM2 enabled\n");
6650         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6651              "PCH PWM1 enabled\n");
6652         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6653              "Utility pin enabled\n");
6654         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6655
6656         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6657         val = I915_READ(DEIMR);
6658         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6659              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6660         val = I915_READ(SDEIMR);
6661         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6662              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6663         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6664 }
6665
6666 /*
6667  * This function implements pieces of two sequences from BSpec:
6668  * - Sequence for display software to disable LCPLL
6669  * - Sequence for display software to allow package C8+
6670  * The steps implemented here are just the steps that actually touch the LCPLL
6671  * register. Callers should take care of disabling all the display engine
6672  * functions, doing the mode unset, fixing interrupts, etc.
6673  */
6674 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6675                               bool switch_to_fclk, bool allow_power_down)
6676 {
6677         uint32_t val;
6678
6679         assert_can_disable_lcpll(dev_priv);
6680
6681         val = I915_READ(LCPLL_CTL);
6682
6683         if (switch_to_fclk) {
6684                 val |= LCPLL_CD_SOURCE_FCLK;
6685                 I915_WRITE(LCPLL_CTL, val);
6686
6687                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6688                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6689                         DRM_ERROR("Switching to FCLK failed\n");
6690
6691                 val = I915_READ(LCPLL_CTL);
6692         }
6693
6694         val |= LCPLL_PLL_DISABLE;
6695         I915_WRITE(LCPLL_CTL, val);
6696         POSTING_READ(LCPLL_CTL);
6697
6698         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6699                 DRM_ERROR("LCPLL still locked\n");
6700
6701         val = I915_READ(D_COMP);
6702         val |= D_COMP_COMP_DISABLE;
6703         mutex_lock(&dev_priv->rps.hw_lock);
6704         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6705                 DRM_ERROR("Failed to disable D_COMP\n");
6706         mutex_unlock(&dev_priv->rps.hw_lock);
6707         POSTING_READ(D_COMP);
6708         ndelay(100);
6709
6710         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6711                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6712
6713         if (allow_power_down) {
6714                 val = I915_READ(LCPLL_CTL);
6715                 val |= LCPLL_POWER_DOWN_ALLOW;
6716                 I915_WRITE(LCPLL_CTL, val);
6717                 POSTING_READ(LCPLL_CTL);
6718         }
6719 }
6720
6721 /*
6722  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6723  * source.
6724  */
6725 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6726 {
6727         uint32_t val;
6728
6729         val = I915_READ(LCPLL_CTL);
6730
6731         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6732                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6733                 return;
6734
6735         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6736          * we'll hang the machine! */
6737         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6738
6739         if (val & LCPLL_POWER_DOWN_ALLOW) {
6740                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6741                 I915_WRITE(LCPLL_CTL, val);
6742                 POSTING_READ(LCPLL_CTL);
6743         }
6744
6745         val = I915_READ(D_COMP);
6746         val |= D_COMP_COMP_FORCE;
6747         val &= ~D_COMP_COMP_DISABLE;
6748         mutex_lock(&dev_priv->rps.hw_lock);
6749         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6750                 DRM_ERROR("Failed to enable D_COMP\n");
6751         mutex_unlock(&dev_priv->rps.hw_lock);
6752         POSTING_READ(D_COMP);
6753
6754         val = I915_READ(LCPLL_CTL);
6755         val &= ~LCPLL_PLL_DISABLE;
6756         I915_WRITE(LCPLL_CTL, val);
6757
6758         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6759                 DRM_ERROR("LCPLL not locked yet\n");
6760
6761         if (val & LCPLL_CD_SOURCE_FCLK) {
6762                 val = I915_READ(LCPLL_CTL);
6763                 val &= ~LCPLL_CD_SOURCE_FCLK;
6764                 I915_WRITE(LCPLL_CTL, val);
6765
6766                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6767                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6768                         DRM_ERROR("Switching back to LCPLL failed\n");
6769         }
6770
6771         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6772 }
6773
6774 void hsw_enable_pc8_work(struct work_struct *__work)
6775 {
6776         struct drm_i915_private *dev_priv =
6777                 container_of(to_delayed_work(__work), struct drm_i915_private,
6778                              pc8.enable_work);
6779         struct drm_device *dev = dev_priv->dev;
6780         uint32_t val;
6781
6782         WARN_ON(!HAS_PC8(dev));
6783
6784         if (dev_priv->pc8.enabled)
6785                 return;
6786
6787         DRM_DEBUG_KMS("Enabling package C8+\n");
6788
6789         dev_priv->pc8.enabled = true;
6790
6791         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6792                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6793                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6794                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6795         }
6796
6797         lpt_disable_clkout_dp(dev);
6798         hsw_pc8_disable_interrupts(dev);
6799         hsw_disable_lcpll(dev_priv, true, true);
6800
6801         intel_runtime_pm_put(dev_priv);
6802 }
6803
6804 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6805 {
6806         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6807         WARN(dev_priv->pc8.disable_count < 1,
6808              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6809
6810         dev_priv->pc8.disable_count--;
6811         if (dev_priv->pc8.disable_count != 0)
6812                 return;
6813
6814         schedule_delayed_work(&dev_priv->pc8.enable_work,
6815                               msecs_to_jiffies(i915.pc8_timeout));
6816 }
6817
6818 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6819 {
6820         struct drm_device *dev = dev_priv->dev;
6821         uint32_t val;
6822
6823         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6824         WARN(dev_priv->pc8.disable_count < 0,
6825              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6826
6827         dev_priv->pc8.disable_count++;
6828         if (dev_priv->pc8.disable_count != 1)
6829                 return;
6830
6831         WARN_ON(!HAS_PC8(dev));
6832
6833         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6834         if (!dev_priv->pc8.enabled)
6835                 return;
6836
6837         DRM_DEBUG_KMS("Disabling package C8+\n");
6838
6839         intel_runtime_pm_get(dev_priv);
6840
6841         hsw_restore_lcpll(dev_priv);
6842         hsw_pc8_restore_interrupts(dev);
6843         lpt_init_pch_refclk(dev);
6844
6845         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6846                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6847                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6848                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6849         }
6850
6851         intel_prepare_ddi(dev);
6852         i915_gem_init_swizzling(dev);
6853         mutex_lock(&dev_priv->rps.hw_lock);
6854         gen6_update_ring_freq(dev);
6855         mutex_unlock(&dev_priv->rps.hw_lock);
6856         dev_priv->pc8.enabled = false;
6857 }
6858
6859 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6860 {
6861         if (!HAS_PC8(dev_priv->dev))
6862                 return;
6863
6864         mutex_lock(&dev_priv->pc8.lock);
6865         __hsw_enable_package_c8(dev_priv);
6866         mutex_unlock(&dev_priv->pc8.lock);
6867 }
6868
6869 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6870 {
6871         if (!HAS_PC8(dev_priv->dev))
6872                 return;
6873
6874         mutex_lock(&dev_priv->pc8.lock);
6875         __hsw_disable_package_c8(dev_priv);
6876         mutex_unlock(&dev_priv->pc8.lock);
6877 }
6878
6879 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6880 {
6881         struct drm_device *dev = dev_priv->dev;
6882         struct intel_crtc *crtc;
6883         uint32_t val;
6884
6885         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6886                 if (crtc->base.enabled)
6887                         return false;
6888
6889         /* This case is still possible since we have the i915.disable_power_well
6890          * parameter and also the KVMr or something else might be requesting the
6891          * power well. */
6892         val = I915_READ(HSW_PWR_WELL_DRIVER);
6893         if (val != 0) {
6894                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6895                 return false;
6896         }
6897
6898         return true;
6899 }
6900
6901 /* Since we're called from modeset_global_resources there's no way to
6902  * symmetrically increase and decrease the refcount, so we use
6903  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6904  * or not.
6905  */
6906 static void hsw_update_package_c8(struct drm_device *dev)
6907 {
6908         struct drm_i915_private *dev_priv = dev->dev_private;
6909         bool allow;
6910
6911         if (!HAS_PC8(dev_priv->dev))
6912                 return;
6913
6914         if (!i915.enable_pc8)
6915                 return;
6916
6917         mutex_lock(&dev_priv->pc8.lock);
6918
6919         allow = hsw_can_enable_package_c8(dev_priv);
6920
6921         if (allow == dev_priv->pc8.requirements_met)
6922                 goto done;
6923
6924         dev_priv->pc8.requirements_met = allow;
6925
6926         if (allow)
6927                 __hsw_enable_package_c8(dev_priv);
6928         else
6929                 __hsw_disable_package_c8(dev_priv);
6930
6931 done:
6932         mutex_unlock(&dev_priv->pc8.lock);
6933 }
6934
6935 static void haswell_modeset_global_resources(struct drm_device *dev)
6936 {
6937         modeset_update_crtc_power_domains(dev);
6938         hsw_update_package_c8(dev);
6939 }
6940
6941 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6942                                  int x, int y,
6943                                  struct drm_framebuffer *fb)
6944 {
6945         struct drm_device *dev = crtc->dev;
6946         struct drm_i915_private *dev_priv = dev->dev_private;
6947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6948         int plane = intel_crtc->plane;
6949         int ret;
6950
6951         if (!intel_ddi_pll_select(intel_crtc))
6952                 return -EINVAL;
6953         intel_ddi_pll_enable(intel_crtc);
6954
6955         if (intel_crtc->config.has_dp_encoder)
6956                 intel_dp_set_m_n(intel_crtc);
6957
6958         intel_crtc->lowfreq_avail = false;
6959
6960         intel_set_pipe_timings(intel_crtc);
6961
6962         if (intel_crtc->config.has_pch_encoder) {
6963                 intel_cpu_transcoder_set_m_n(intel_crtc,
6964                                              &intel_crtc->config.fdi_m_n);
6965         }
6966
6967         haswell_set_pipeconf(crtc);
6968
6969         intel_set_pipe_csc(crtc);
6970
6971         /* Set up the display plane register */
6972         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6973         POSTING_READ(DSPCNTR(plane));
6974
6975         ret = intel_pipe_set_base(crtc, x, y, fb);
6976
6977         return ret;
6978 }
6979
6980 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6981                                     struct intel_crtc_config *pipe_config)
6982 {
6983         struct drm_device *dev = crtc->base.dev;
6984         struct drm_i915_private *dev_priv = dev->dev_private;
6985         enum intel_display_power_domain pfit_domain;
6986         uint32_t tmp;
6987
6988         if (!intel_display_power_enabled(dev_priv,
6989                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6990                 return false;
6991
6992         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6993         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6994
6995         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6996         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6997                 enum pipe trans_edp_pipe;
6998                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6999                 default:
7000                         WARN(1, "unknown pipe linked to edp transcoder\n");
7001                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7002                 case TRANS_DDI_EDP_INPUT_A_ON:
7003                         trans_edp_pipe = PIPE_A;
7004                         break;
7005                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7006                         trans_edp_pipe = PIPE_B;
7007                         break;
7008                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7009                         trans_edp_pipe = PIPE_C;
7010                         break;
7011                 }
7012
7013                 if (trans_edp_pipe == crtc->pipe)
7014                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7015         }
7016
7017         if (!intel_display_power_enabled(dev_priv,
7018                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7019                 return false;
7020
7021         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7022         if (!(tmp & PIPECONF_ENABLE))
7023                 return false;
7024
7025         /*
7026          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7027          * DDI E. So just check whether this pipe is wired to DDI E and whether
7028          * the PCH transcoder is on.
7029          */
7030         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7031         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7032             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7033                 pipe_config->has_pch_encoder = true;
7034
7035                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7036                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7037                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7038
7039                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7040         }
7041
7042         intel_get_pipe_timings(crtc, pipe_config);
7043
7044         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7045         if (intel_display_power_enabled(dev_priv, pfit_domain))
7046                 ironlake_get_pfit_config(crtc, pipe_config);
7047
7048         if (IS_HASWELL(dev))
7049                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7050                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7051
7052         pipe_config->pixel_multiplier = 1;
7053
7054         return true;
7055 }
7056
7057 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7058                                int x, int y,
7059                                struct drm_framebuffer *fb)
7060 {
7061         struct drm_device *dev = crtc->dev;
7062         struct drm_i915_private *dev_priv = dev->dev_private;
7063         struct intel_encoder *encoder;
7064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7065         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7066         int pipe = intel_crtc->pipe;
7067         int ret;
7068
7069         drm_vblank_pre_modeset(dev, pipe);
7070
7071         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7072
7073         drm_vblank_post_modeset(dev, pipe);
7074
7075         if (ret != 0)
7076                 return ret;
7077
7078         for_each_encoder_on_crtc(dev, crtc, encoder) {
7079                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7080                         encoder->base.base.id,
7081                         drm_get_encoder_name(&encoder->base),
7082                         mode->base.id, mode->name);
7083                 encoder->mode_set(encoder);
7084         }
7085
7086         return 0;
7087 }
7088
7089 static struct {
7090         int clock;
7091         u32 config;
7092 } hdmi_audio_clock[] = {
7093         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7094         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7095         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7096         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7097         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7098         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7099         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7100         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7101         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7102         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7103 };
7104
7105 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7106 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7107 {
7108         int i;
7109
7110         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7111                 if (mode->clock == hdmi_audio_clock[i].clock)
7112                         break;
7113         }
7114
7115         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7116                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7117                 i = 1;
7118         }
7119
7120         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7121                       hdmi_audio_clock[i].clock,
7122                       hdmi_audio_clock[i].config);
7123
7124         return hdmi_audio_clock[i].config;
7125 }
7126
7127 static bool intel_eld_uptodate(struct drm_connector *connector,
7128                                int reg_eldv, uint32_t bits_eldv,
7129                                int reg_elda, uint32_t bits_elda,
7130                                int reg_edid)
7131 {
7132         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7133         uint8_t *eld = connector->eld;
7134         uint32_t i;
7135
7136         i = I915_READ(reg_eldv);
7137         i &= bits_eldv;
7138
7139         if (!eld[0])
7140                 return !i;
7141
7142         if (!i)
7143                 return false;
7144
7145         i = I915_READ(reg_elda);
7146         i &= ~bits_elda;
7147         I915_WRITE(reg_elda, i);
7148
7149         for (i = 0; i < eld[2]; i++)
7150                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7151                         return false;
7152
7153         return true;
7154 }
7155
7156 static void g4x_write_eld(struct drm_connector *connector,
7157                           struct drm_crtc *crtc,
7158                           struct drm_display_mode *mode)
7159 {
7160         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7161         uint8_t *eld = connector->eld;
7162         uint32_t eldv;
7163         uint32_t len;
7164         uint32_t i;
7165
7166         i = I915_READ(G4X_AUD_VID_DID);
7167
7168         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7169                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7170         else
7171                 eldv = G4X_ELDV_DEVCTG;
7172
7173         if (intel_eld_uptodate(connector,
7174                                G4X_AUD_CNTL_ST, eldv,
7175                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7176                                G4X_HDMIW_HDMIEDID))
7177                 return;
7178
7179         i = I915_READ(G4X_AUD_CNTL_ST);
7180         i &= ~(eldv | G4X_ELD_ADDR);
7181         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7182         I915_WRITE(G4X_AUD_CNTL_ST, i);
7183
7184         if (!eld[0])
7185                 return;
7186
7187         len = min_t(uint8_t, eld[2], len);
7188         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7189         for (i = 0; i < len; i++)
7190                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7191
7192         i = I915_READ(G4X_AUD_CNTL_ST);
7193         i |= eldv;
7194         I915_WRITE(G4X_AUD_CNTL_ST, i);
7195 }
7196
7197 static void haswell_write_eld(struct drm_connector *connector,
7198                               struct drm_crtc *crtc,
7199                               struct drm_display_mode *mode)
7200 {
7201         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7202         uint8_t *eld = connector->eld;
7203         struct drm_device *dev = crtc->dev;
7204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7205         uint32_t eldv;
7206         uint32_t i;
7207         int len;
7208         int pipe = to_intel_crtc(crtc)->pipe;
7209         int tmp;
7210
7211         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7212         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7213         int aud_config = HSW_AUD_CFG(pipe);
7214         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7215
7216
7217         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7218
7219         /* Audio output enable */
7220         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7221         tmp = I915_READ(aud_cntrl_st2);
7222         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7223         I915_WRITE(aud_cntrl_st2, tmp);
7224
7225         /* Wait for 1 vertical blank */
7226         intel_wait_for_vblank(dev, pipe);
7227
7228         /* Set ELD valid state */
7229         tmp = I915_READ(aud_cntrl_st2);
7230         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7231         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7232         I915_WRITE(aud_cntrl_st2, tmp);
7233         tmp = I915_READ(aud_cntrl_st2);
7234         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7235
7236         /* Enable HDMI mode */
7237         tmp = I915_READ(aud_config);
7238         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7239         /* clear N_programing_enable and N_value_index */
7240         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7241         I915_WRITE(aud_config, tmp);
7242
7243         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7244
7245         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7246         intel_crtc->eld_vld = true;
7247
7248         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7249                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7250                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7251                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7252         } else {
7253                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7254         }
7255
7256         if (intel_eld_uptodate(connector,
7257                                aud_cntrl_st2, eldv,
7258                                aud_cntl_st, IBX_ELD_ADDRESS,
7259                                hdmiw_hdmiedid))
7260                 return;
7261
7262         i = I915_READ(aud_cntrl_st2);
7263         i &= ~eldv;
7264         I915_WRITE(aud_cntrl_st2, i);
7265
7266         if (!eld[0])
7267                 return;
7268
7269         i = I915_READ(aud_cntl_st);
7270         i &= ~IBX_ELD_ADDRESS;
7271         I915_WRITE(aud_cntl_st, i);
7272         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7273         DRM_DEBUG_DRIVER("port num:%d\n", i);
7274
7275         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7276         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7277         for (i = 0; i < len; i++)
7278                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7279
7280         i = I915_READ(aud_cntrl_st2);
7281         i |= eldv;
7282         I915_WRITE(aud_cntrl_st2, i);
7283
7284 }
7285
7286 static void ironlake_write_eld(struct drm_connector *connector,
7287                                struct drm_crtc *crtc,
7288                                struct drm_display_mode *mode)
7289 {
7290         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7291         uint8_t *eld = connector->eld;
7292         uint32_t eldv;
7293         uint32_t i;
7294         int len;
7295         int hdmiw_hdmiedid;
7296         int aud_config;
7297         int aud_cntl_st;
7298         int aud_cntrl_st2;
7299         int pipe = to_intel_crtc(crtc)->pipe;
7300
7301         if (HAS_PCH_IBX(connector->dev)) {
7302                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7303                 aud_config = IBX_AUD_CFG(pipe);
7304                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7305                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7306         } else if (IS_VALLEYVIEW(connector->dev)) {
7307                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7308                 aud_config = VLV_AUD_CFG(pipe);
7309                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7310                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7311         } else {
7312                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7313                 aud_config = CPT_AUD_CFG(pipe);
7314                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7315                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7316         }
7317
7318         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7319
7320         if (IS_VALLEYVIEW(connector->dev))  {
7321                 struct intel_encoder *intel_encoder;
7322                 struct intel_digital_port *intel_dig_port;
7323
7324                 intel_encoder = intel_attached_encoder(connector);
7325                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7326                 i = intel_dig_port->port;
7327         } else {
7328                 i = I915_READ(aud_cntl_st);
7329                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7330                 /* DIP_Port_Select, 0x1 = PortB */
7331         }
7332
7333         if (!i) {
7334                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7335                 /* operate blindly on all ports */
7336                 eldv = IBX_ELD_VALIDB;
7337                 eldv |= IBX_ELD_VALIDB << 4;
7338                 eldv |= IBX_ELD_VALIDB << 8;
7339         } else {
7340                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7341                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7342         }
7343
7344         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7345                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7346                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7347                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7348         } else {
7349                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7350         }
7351
7352         if (intel_eld_uptodate(connector,
7353                                aud_cntrl_st2, eldv,
7354                                aud_cntl_st, IBX_ELD_ADDRESS,
7355                                hdmiw_hdmiedid))
7356                 return;
7357
7358         i = I915_READ(aud_cntrl_st2);
7359         i &= ~eldv;
7360         I915_WRITE(aud_cntrl_st2, i);
7361
7362         if (!eld[0])
7363                 return;
7364
7365         i = I915_READ(aud_cntl_st);
7366         i &= ~IBX_ELD_ADDRESS;
7367         I915_WRITE(aud_cntl_st, i);
7368
7369         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7370         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7371         for (i = 0; i < len; i++)
7372                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7373
7374         i = I915_READ(aud_cntrl_st2);
7375         i |= eldv;
7376         I915_WRITE(aud_cntrl_st2, i);
7377 }
7378
7379 void intel_write_eld(struct drm_encoder *encoder,
7380                      struct drm_display_mode *mode)
7381 {
7382         struct drm_crtc *crtc = encoder->crtc;
7383         struct drm_connector *connector;
7384         struct drm_device *dev = encoder->dev;
7385         struct drm_i915_private *dev_priv = dev->dev_private;
7386
7387         connector = drm_select_eld(encoder, mode);
7388         if (!connector)
7389                 return;
7390
7391         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7392                          connector->base.id,
7393                          drm_get_connector_name(connector),
7394                          connector->encoder->base.id,
7395                          drm_get_encoder_name(connector->encoder));
7396
7397         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7398
7399         if (dev_priv->display.write_eld)
7400                 dev_priv->display.write_eld(connector, crtc, mode);
7401 }
7402
7403 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7404 {
7405         struct drm_device *dev = crtc->dev;
7406         struct drm_i915_private *dev_priv = dev->dev_private;
7407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7408         bool visible = base != 0;
7409         u32 cntl;
7410
7411         if (intel_crtc->cursor_visible == visible)
7412                 return;
7413
7414         cntl = I915_READ(_CURACNTR);
7415         if (visible) {
7416                 /* On these chipsets we can only modify the base whilst
7417                  * the cursor is disabled.
7418                  */
7419                 I915_WRITE(_CURABASE, base);
7420
7421                 cntl &= ~(CURSOR_FORMAT_MASK);
7422                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7423                 cntl |= CURSOR_ENABLE |
7424                         CURSOR_GAMMA_ENABLE |
7425                         CURSOR_FORMAT_ARGB;
7426         } else
7427                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7428         I915_WRITE(_CURACNTR, cntl);
7429
7430         intel_crtc->cursor_visible = visible;
7431 }
7432
7433 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7434 {
7435         struct drm_device *dev = crtc->dev;
7436         struct drm_i915_private *dev_priv = dev->dev_private;
7437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438         int pipe = intel_crtc->pipe;
7439         bool visible = base != 0;
7440
7441         if (intel_crtc->cursor_visible != visible) {
7442                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7443                 if (base) {
7444                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7445                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7446                         cntl |= pipe << 28; /* Connect to correct pipe */
7447                 } else {
7448                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7449                         cntl |= CURSOR_MODE_DISABLE;
7450                 }
7451                 I915_WRITE(CURCNTR(pipe), cntl);
7452
7453                 intel_crtc->cursor_visible = visible;
7454         }
7455         /* and commit changes on next vblank */
7456         POSTING_READ(CURCNTR(pipe));
7457         I915_WRITE(CURBASE(pipe), base);
7458         POSTING_READ(CURBASE(pipe));
7459 }
7460
7461 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7462 {
7463         struct drm_device *dev = crtc->dev;
7464         struct drm_i915_private *dev_priv = dev->dev_private;
7465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7466         int pipe = intel_crtc->pipe;
7467         bool visible = base != 0;
7468
7469         if (intel_crtc->cursor_visible != visible) {
7470                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7471                 if (base) {
7472                         cntl &= ~CURSOR_MODE;
7473                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7474                 } else {
7475                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7476                         cntl |= CURSOR_MODE_DISABLE;
7477                 }
7478                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7479                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7480                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7481                 }
7482                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7483
7484                 intel_crtc->cursor_visible = visible;
7485         }
7486         /* and commit changes on next vblank */
7487         POSTING_READ(CURCNTR_IVB(pipe));
7488         I915_WRITE(CURBASE_IVB(pipe), base);
7489         POSTING_READ(CURBASE_IVB(pipe));
7490 }
7491
7492 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7493 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7494                                      bool on)
7495 {
7496         struct drm_device *dev = crtc->dev;
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7499         int pipe = intel_crtc->pipe;
7500         int x = intel_crtc->cursor_x;
7501         int y = intel_crtc->cursor_y;
7502         u32 base = 0, pos = 0;
7503         bool visible;
7504
7505         if (on)
7506                 base = intel_crtc->cursor_addr;
7507
7508         if (x >= intel_crtc->config.pipe_src_w)
7509                 base = 0;
7510
7511         if (y >= intel_crtc->config.pipe_src_h)
7512                 base = 0;
7513
7514         if (x < 0) {
7515                 if (x + intel_crtc->cursor_width <= 0)
7516                         base = 0;
7517
7518                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7519                 x = -x;
7520         }
7521         pos |= x << CURSOR_X_SHIFT;
7522
7523         if (y < 0) {
7524                 if (y + intel_crtc->cursor_height <= 0)
7525                         base = 0;
7526
7527                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7528                 y = -y;
7529         }
7530         pos |= y << CURSOR_Y_SHIFT;
7531
7532         visible = base != 0;
7533         if (!visible && !intel_crtc->cursor_visible)
7534                 return;
7535
7536         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7537                 I915_WRITE(CURPOS_IVB(pipe), pos);
7538                 ivb_update_cursor(crtc, base);
7539         } else {
7540                 I915_WRITE(CURPOS(pipe), pos);
7541                 if (IS_845G(dev) || IS_I865G(dev))
7542                         i845_update_cursor(crtc, base);
7543                 else
7544                         i9xx_update_cursor(crtc, base);
7545         }
7546 }
7547
7548 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7549                                  struct drm_file *file,
7550                                  uint32_t handle,
7551                                  uint32_t width, uint32_t height)
7552 {
7553         struct drm_device *dev = crtc->dev;
7554         struct drm_i915_private *dev_priv = dev->dev_private;
7555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7556         struct drm_i915_gem_object *obj;
7557         uint32_t addr;
7558         int ret;
7559
7560         /* if we want to turn off the cursor ignore width and height */
7561         if (!handle) {
7562                 DRM_DEBUG_KMS("cursor off\n");
7563                 addr = 0;
7564                 obj = NULL;
7565                 mutex_lock(&dev->struct_mutex);
7566                 goto finish;
7567         }
7568
7569         /* Currently we only support 64x64 cursors */
7570         if (width != 64 || height != 64) {
7571                 DRM_ERROR("we currently only support 64x64 cursors\n");
7572                 return -EINVAL;
7573         }
7574
7575         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7576         if (&obj->base == NULL)
7577                 return -ENOENT;
7578
7579         if (obj->base.size < width * height * 4) {
7580                 DRM_DEBUG_KMS("buffer is to small\n");
7581                 ret = -ENOMEM;
7582                 goto fail;
7583         }
7584
7585         /* we only need to pin inside GTT if cursor is non-phy */
7586         mutex_lock(&dev->struct_mutex);
7587         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7588                 unsigned alignment;
7589
7590                 if (obj->tiling_mode) {
7591                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7592                         ret = -EINVAL;
7593                         goto fail_locked;
7594                 }
7595
7596                 /* Note that the w/a also requires 2 PTE of padding following
7597                  * the bo. We currently fill all unused PTE with the shadow
7598                  * page and so we should always have valid PTE following the
7599                  * cursor preventing the VT-d warning.
7600                  */
7601                 alignment = 0;
7602                 if (need_vtd_wa(dev))
7603                         alignment = 64*1024;
7604
7605                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7606                 if (ret) {
7607                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7608                         goto fail_locked;
7609                 }
7610
7611                 ret = i915_gem_object_put_fence(obj);
7612                 if (ret) {
7613                         DRM_DEBUG_KMS("failed to release fence for cursor");
7614                         goto fail_unpin;
7615                 }
7616
7617                 addr = i915_gem_obj_ggtt_offset(obj);
7618         } else {
7619                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7620                 ret = i915_gem_attach_phys_object(dev, obj,
7621                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7622                                                   align);
7623                 if (ret) {
7624                         DRM_DEBUG_KMS("failed to attach phys object\n");
7625                         goto fail_locked;
7626                 }
7627                 addr = obj->phys_obj->handle->busaddr;
7628         }
7629
7630         if (IS_GEN2(dev))
7631                 I915_WRITE(CURSIZE, (height << 12) | width);
7632
7633  finish:
7634         if (intel_crtc->cursor_bo) {
7635                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7636                         if (intel_crtc->cursor_bo != obj)
7637                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7638                 } else
7639                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7640                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7641         }
7642
7643         mutex_unlock(&dev->struct_mutex);
7644
7645         intel_crtc->cursor_addr = addr;
7646         intel_crtc->cursor_bo = obj;
7647         intel_crtc->cursor_width = width;
7648         intel_crtc->cursor_height = height;
7649
7650         if (intel_crtc->active)
7651                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7652
7653         return 0;
7654 fail_unpin:
7655         i915_gem_object_unpin_from_display_plane(obj);
7656 fail_locked:
7657         mutex_unlock(&dev->struct_mutex);
7658 fail:
7659         drm_gem_object_unreference_unlocked(&obj->base);
7660         return ret;
7661 }
7662
7663 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7664 {
7665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7666
7667         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7668         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7669
7670         if (intel_crtc->active)
7671                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7672
7673         return 0;
7674 }
7675
7676 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7677                                  u16 *blue, uint32_t start, uint32_t size)
7678 {
7679         int end = (start + size > 256) ? 256 : start + size, i;
7680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7681
7682         for (i = start; i < end; i++) {
7683                 intel_crtc->lut_r[i] = red[i] >> 8;
7684                 intel_crtc->lut_g[i] = green[i] >> 8;
7685                 intel_crtc->lut_b[i] = blue[i] >> 8;
7686         }
7687
7688         intel_crtc_load_lut(crtc);
7689 }
7690
7691 /* VESA 640x480x72Hz mode to set on the pipe */
7692 static struct drm_display_mode load_detect_mode = {
7693         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7694                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7695 };
7696
7697 struct drm_framebuffer *
7698 __intel_framebuffer_create(struct drm_device *dev,
7699                            struct drm_mode_fb_cmd2 *mode_cmd,
7700                            struct drm_i915_gem_object *obj)
7701 {
7702         struct intel_framebuffer *intel_fb;
7703         int ret;
7704
7705         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7706         if (!intel_fb) {
7707                 drm_gem_object_unreference_unlocked(&obj->base);
7708                 return ERR_PTR(-ENOMEM);
7709         }
7710
7711         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7712         if (ret)
7713                 goto err;
7714
7715         return &intel_fb->base;
7716 err:
7717         drm_gem_object_unreference_unlocked(&obj->base);
7718         kfree(intel_fb);
7719
7720         return ERR_PTR(ret);
7721 }
7722
7723 static struct drm_framebuffer *
7724 intel_framebuffer_create(struct drm_device *dev,
7725                          struct drm_mode_fb_cmd2 *mode_cmd,
7726                          struct drm_i915_gem_object *obj)
7727 {
7728         struct drm_framebuffer *fb;
7729         int ret;
7730
7731         ret = i915_mutex_lock_interruptible(dev);
7732         if (ret)
7733                 return ERR_PTR(ret);
7734         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7735         mutex_unlock(&dev->struct_mutex);
7736
7737         return fb;
7738 }
7739
7740 static u32
7741 intel_framebuffer_pitch_for_width(int width, int bpp)
7742 {
7743         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7744         return ALIGN(pitch, 64);
7745 }
7746
7747 static u32
7748 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7749 {
7750         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7751         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7752 }
7753
7754 static struct drm_framebuffer *
7755 intel_framebuffer_create_for_mode(struct drm_device *dev,
7756                                   struct drm_display_mode *mode,
7757                                   int depth, int bpp)
7758 {
7759         struct drm_i915_gem_object *obj;
7760         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7761
7762         obj = i915_gem_alloc_object(dev,
7763                                     intel_framebuffer_size_for_mode(mode, bpp));
7764         if (obj == NULL)
7765                 return ERR_PTR(-ENOMEM);
7766
7767         mode_cmd.width = mode->hdisplay;
7768         mode_cmd.height = mode->vdisplay;
7769         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7770                                                                 bpp);
7771         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7772
7773         return intel_framebuffer_create(dev, &mode_cmd, obj);
7774 }
7775
7776 static struct drm_framebuffer *
7777 mode_fits_in_fbdev(struct drm_device *dev,
7778                    struct drm_display_mode *mode)
7779 {
7780 #ifdef CONFIG_DRM_I915_FBDEV
7781         struct drm_i915_private *dev_priv = dev->dev_private;
7782         struct drm_i915_gem_object *obj;
7783         struct drm_framebuffer *fb;
7784
7785         if (!dev_priv->fbdev)
7786                 return NULL;
7787
7788         if (!dev_priv->fbdev->fb)
7789                 return NULL;
7790
7791         obj = dev_priv->fbdev->fb->obj;
7792         BUG_ON(!obj);
7793
7794         fb = &dev_priv->fbdev->fb->base;
7795         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7796                                                                fb->bits_per_pixel))
7797                 return NULL;
7798
7799         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7800                 return NULL;
7801
7802         return fb;
7803 #else
7804         return NULL;
7805 #endif
7806 }
7807
7808 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7809                                 struct drm_display_mode *mode,
7810                                 struct intel_load_detect_pipe *old)
7811 {
7812         struct intel_crtc *intel_crtc;
7813         struct intel_encoder *intel_encoder =
7814                 intel_attached_encoder(connector);
7815         struct drm_crtc *possible_crtc;
7816         struct drm_encoder *encoder = &intel_encoder->base;
7817         struct drm_crtc *crtc = NULL;
7818         struct drm_device *dev = encoder->dev;
7819         struct drm_framebuffer *fb;
7820         int i = -1;
7821
7822         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7823                       connector->base.id, drm_get_connector_name(connector),
7824                       encoder->base.id, drm_get_encoder_name(encoder));
7825
7826         /*
7827          * Algorithm gets a little messy:
7828          *
7829          *   - if the connector already has an assigned crtc, use it (but make
7830          *     sure it's on first)
7831          *
7832          *   - try to find the first unused crtc that can drive this connector,
7833          *     and use that if we find one
7834          */
7835
7836         /* See if we already have a CRTC for this connector */
7837         if (encoder->crtc) {
7838                 crtc = encoder->crtc;
7839
7840                 mutex_lock(&crtc->mutex);
7841
7842                 old->dpms_mode = connector->dpms;
7843                 old->load_detect_temp = false;
7844
7845                 /* Make sure the crtc and connector are running */
7846                 if (connector->dpms != DRM_MODE_DPMS_ON)
7847                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7848
7849                 return true;
7850         }
7851
7852         /* Find an unused one (if possible) */
7853         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7854                 i++;
7855                 if (!(encoder->possible_crtcs & (1 << i)))
7856                         continue;
7857                 if (!possible_crtc->enabled) {
7858                         crtc = possible_crtc;
7859                         break;
7860                 }
7861         }
7862
7863         /*
7864          * If we didn't find an unused CRTC, don't use any.
7865          */
7866         if (!crtc) {
7867                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7868                 return false;
7869         }
7870
7871         mutex_lock(&crtc->mutex);
7872         intel_encoder->new_crtc = to_intel_crtc(crtc);
7873         to_intel_connector(connector)->new_encoder = intel_encoder;
7874
7875         intel_crtc = to_intel_crtc(crtc);
7876         intel_crtc->new_enabled = true;
7877         intel_crtc->new_config = &intel_crtc->config;
7878         old->dpms_mode = connector->dpms;
7879         old->load_detect_temp = true;
7880         old->release_fb = NULL;
7881
7882         if (!mode)
7883                 mode = &load_detect_mode;
7884
7885         /* We need a framebuffer large enough to accommodate all accesses
7886          * that the plane may generate whilst we perform load detection.
7887          * We can not rely on the fbcon either being present (we get called
7888          * during its initialisation to detect all boot displays, or it may
7889          * not even exist) or that it is large enough to satisfy the
7890          * requested mode.
7891          */
7892         fb = mode_fits_in_fbdev(dev, mode);
7893         if (fb == NULL) {
7894                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7895                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7896                 old->release_fb = fb;
7897         } else
7898                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7899         if (IS_ERR(fb)) {
7900                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7901                 goto fail;
7902         }
7903
7904         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7905                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7906                 if (old->release_fb)
7907                         old->release_fb->funcs->destroy(old->release_fb);
7908                 goto fail;
7909         }
7910
7911         /* let the connector get through one full cycle before testing */
7912         intel_wait_for_vblank(dev, intel_crtc->pipe);
7913         return true;
7914
7915  fail:
7916         intel_crtc->new_enabled = crtc->enabled;
7917         if (intel_crtc->new_enabled)
7918                 intel_crtc->new_config = &intel_crtc->config;
7919         else
7920                 intel_crtc->new_config = NULL;
7921         mutex_unlock(&crtc->mutex);
7922         return false;
7923 }
7924
7925 void intel_release_load_detect_pipe(struct drm_connector *connector,
7926                                     struct intel_load_detect_pipe *old)
7927 {
7928         struct intel_encoder *intel_encoder =
7929                 intel_attached_encoder(connector);
7930         struct drm_encoder *encoder = &intel_encoder->base;
7931         struct drm_crtc *crtc = encoder->crtc;
7932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7933
7934         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7935                       connector->base.id, drm_get_connector_name(connector),
7936                       encoder->base.id, drm_get_encoder_name(encoder));
7937
7938         if (old->load_detect_temp) {
7939                 to_intel_connector(connector)->new_encoder = NULL;
7940                 intel_encoder->new_crtc = NULL;
7941                 intel_crtc->new_enabled = false;
7942                 intel_crtc->new_config = NULL;
7943                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7944
7945                 if (old->release_fb) {
7946                         drm_framebuffer_unregister_private(old->release_fb);
7947                         drm_framebuffer_unreference(old->release_fb);
7948                 }
7949
7950                 mutex_unlock(&crtc->mutex);
7951                 return;
7952         }
7953
7954         /* Switch crtc and encoder back off if necessary */
7955         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7956                 connector->funcs->dpms(connector, old->dpms_mode);
7957
7958         mutex_unlock(&crtc->mutex);
7959 }
7960
7961 static int i9xx_pll_refclk(struct drm_device *dev,
7962                            const struct intel_crtc_config *pipe_config)
7963 {
7964         struct drm_i915_private *dev_priv = dev->dev_private;
7965         u32 dpll = pipe_config->dpll_hw_state.dpll;
7966
7967         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7968                 return dev_priv->vbt.lvds_ssc_freq;
7969         else if (HAS_PCH_SPLIT(dev))
7970                 return 120000;
7971         else if (!IS_GEN2(dev))
7972                 return 96000;
7973         else
7974                 return 48000;
7975 }
7976
7977 /* Returns the clock of the currently programmed mode of the given pipe. */
7978 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7979                                 struct intel_crtc_config *pipe_config)
7980 {
7981         struct drm_device *dev = crtc->base.dev;
7982         struct drm_i915_private *dev_priv = dev->dev_private;
7983         int pipe = pipe_config->cpu_transcoder;
7984         u32 dpll = pipe_config->dpll_hw_state.dpll;
7985         u32 fp;
7986         intel_clock_t clock;
7987         int refclk = i9xx_pll_refclk(dev, pipe_config);
7988
7989         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7990                 fp = pipe_config->dpll_hw_state.fp0;
7991         else
7992                 fp = pipe_config->dpll_hw_state.fp1;
7993
7994         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7995         if (IS_PINEVIEW(dev)) {
7996                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7997                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7998         } else {
7999                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8000                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8001         }
8002
8003         if (!IS_GEN2(dev)) {
8004                 if (IS_PINEVIEW(dev))
8005                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8006                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8007                 else
8008                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8009                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8010
8011                 switch (dpll & DPLL_MODE_MASK) {
8012                 case DPLLB_MODE_DAC_SERIAL:
8013                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8014                                 5 : 10;
8015                         break;
8016                 case DPLLB_MODE_LVDS:
8017                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8018                                 7 : 14;
8019                         break;
8020                 default:
8021                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8022                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8023                         return;
8024                 }
8025
8026                 if (IS_PINEVIEW(dev))
8027                         pineview_clock(refclk, &clock);
8028                 else
8029                         i9xx_clock(refclk, &clock);
8030         } else {
8031                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8032                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8033
8034                 if (is_lvds) {
8035                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8036                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8037
8038                         if (lvds & LVDS_CLKB_POWER_UP)
8039                                 clock.p2 = 7;
8040                         else
8041                                 clock.p2 = 14;
8042                 } else {
8043                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8044                                 clock.p1 = 2;
8045                         else {
8046                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8047                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8048                         }
8049                         if (dpll & PLL_P2_DIVIDE_BY_4)
8050                                 clock.p2 = 4;
8051                         else
8052                                 clock.p2 = 2;
8053                 }
8054
8055                 i9xx_clock(refclk, &clock);
8056         }
8057
8058         /*
8059          * This value includes pixel_multiplier. We will use
8060          * port_clock to compute adjusted_mode.crtc_clock in the
8061          * encoder's get_config() function.
8062          */
8063         pipe_config->port_clock = clock.dot;
8064 }
8065
8066 int intel_dotclock_calculate(int link_freq,
8067                              const struct intel_link_m_n *m_n)
8068 {
8069         /*
8070          * The calculation for the data clock is:
8071          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8072          * But we want to avoid losing precison if possible, so:
8073          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8074          *
8075          * and the link clock is simpler:
8076          * link_clock = (m * link_clock) / n
8077          */
8078
8079         if (!m_n->link_n)
8080                 return 0;
8081
8082         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8083 }
8084
8085 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8086                                    struct intel_crtc_config *pipe_config)
8087 {
8088         struct drm_device *dev = crtc->base.dev;
8089
8090         /* read out port_clock from the DPLL */
8091         i9xx_crtc_clock_get(crtc, pipe_config);
8092
8093         /*
8094          * This value does not include pixel_multiplier.
8095          * We will check that port_clock and adjusted_mode.crtc_clock
8096          * agree once we know their relationship in the encoder's
8097          * get_config() function.
8098          */
8099         pipe_config->adjusted_mode.crtc_clock =
8100                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8101                                          &pipe_config->fdi_m_n);
8102 }
8103
8104 /** Returns the currently programmed mode of the given pipe. */
8105 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8106                                              struct drm_crtc *crtc)
8107 {
8108         struct drm_i915_private *dev_priv = dev->dev_private;
8109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8110         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8111         struct drm_display_mode *mode;
8112         struct intel_crtc_config pipe_config;
8113         int htot = I915_READ(HTOTAL(cpu_transcoder));
8114         int hsync = I915_READ(HSYNC(cpu_transcoder));
8115         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8116         int vsync = I915_READ(VSYNC(cpu_transcoder));
8117         enum pipe pipe = intel_crtc->pipe;
8118
8119         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8120         if (!mode)
8121                 return NULL;
8122
8123         /*
8124          * Construct a pipe_config sufficient for getting the clock info
8125          * back out of crtc_clock_get.
8126          *
8127          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8128          * to use a real value here instead.
8129          */
8130         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8131         pipe_config.pixel_multiplier = 1;
8132         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8133         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8134         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8135         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8136
8137         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8138         mode->hdisplay = (htot & 0xffff) + 1;
8139         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8140         mode->hsync_start = (hsync & 0xffff) + 1;
8141         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8142         mode->vdisplay = (vtot & 0xffff) + 1;
8143         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8144         mode->vsync_start = (vsync & 0xffff) + 1;
8145         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8146
8147         drm_mode_set_name(mode);
8148
8149         return mode;
8150 }
8151
8152 static void intel_increase_pllclock(struct drm_crtc *crtc)
8153 {
8154         struct drm_device *dev = crtc->dev;
8155         drm_i915_private_t *dev_priv = dev->dev_private;
8156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8157         int pipe = intel_crtc->pipe;
8158         int dpll_reg = DPLL(pipe);
8159         int dpll;
8160
8161         if (HAS_PCH_SPLIT(dev))
8162                 return;
8163
8164         if (!dev_priv->lvds_downclock_avail)
8165                 return;
8166
8167         dpll = I915_READ(dpll_reg);
8168         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8169                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8170
8171                 assert_panel_unlocked(dev_priv, pipe);
8172
8173                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8174                 I915_WRITE(dpll_reg, dpll);
8175                 intel_wait_for_vblank(dev, pipe);
8176
8177                 dpll = I915_READ(dpll_reg);
8178                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8179                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8180         }
8181 }
8182
8183 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8184 {
8185         struct drm_device *dev = crtc->dev;
8186         drm_i915_private_t *dev_priv = dev->dev_private;
8187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8188
8189         if (HAS_PCH_SPLIT(dev))
8190                 return;
8191
8192         if (!dev_priv->lvds_downclock_avail)
8193                 return;
8194
8195         /*
8196          * Since this is called by a timer, we should never get here in
8197          * the manual case.
8198          */
8199         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8200                 int pipe = intel_crtc->pipe;
8201                 int dpll_reg = DPLL(pipe);
8202                 int dpll;
8203
8204                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8205
8206                 assert_panel_unlocked(dev_priv, pipe);
8207
8208                 dpll = I915_READ(dpll_reg);
8209                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8210                 I915_WRITE(dpll_reg, dpll);
8211                 intel_wait_for_vblank(dev, pipe);
8212                 dpll = I915_READ(dpll_reg);
8213                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8214                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8215         }
8216
8217 }
8218
8219 void intel_mark_busy(struct drm_device *dev)
8220 {
8221         struct drm_i915_private *dev_priv = dev->dev_private;
8222
8223         if (dev_priv->mm.busy)
8224                 return;
8225
8226         hsw_disable_package_c8(dev_priv);
8227         i915_update_gfx_val(dev_priv);
8228         dev_priv->mm.busy = true;
8229 }
8230
8231 void intel_mark_idle(struct drm_device *dev)
8232 {
8233         struct drm_i915_private *dev_priv = dev->dev_private;
8234         struct drm_crtc *crtc;
8235
8236         if (!dev_priv->mm.busy)
8237                 return;
8238
8239         dev_priv->mm.busy = false;
8240
8241         if (!i915.powersave)
8242                 goto out;
8243
8244         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8245                 if (!crtc->fb)
8246                         continue;
8247
8248                 intel_decrease_pllclock(crtc);
8249         }
8250
8251         if (INTEL_INFO(dev)->gen >= 6)
8252                 gen6_rps_idle(dev->dev_private);
8253
8254 out:
8255         hsw_enable_package_c8(dev_priv);
8256 }
8257
8258 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8259                         struct intel_ring_buffer *ring)
8260 {
8261         struct drm_device *dev = obj->base.dev;
8262         struct drm_crtc *crtc;
8263
8264         if (!i915.powersave)
8265                 return;
8266
8267         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8268                 if (!crtc->fb)
8269                         continue;
8270
8271                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8272                         continue;
8273
8274                 intel_increase_pllclock(crtc);
8275                 if (ring && intel_fbc_enabled(dev))
8276                         ring->fbc_dirty = true;
8277         }
8278 }
8279
8280 static void intel_crtc_destroy(struct drm_crtc *crtc)
8281 {
8282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8283         struct drm_device *dev = crtc->dev;
8284         struct intel_unpin_work *work;
8285         unsigned long flags;
8286
8287         spin_lock_irqsave(&dev->event_lock, flags);
8288         work = intel_crtc->unpin_work;
8289         intel_crtc->unpin_work = NULL;
8290         spin_unlock_irqrestore(&dev->event_lock, flags);
8291
8292         if (work) {
8293                 cancel_work_sync(&work->work);
8294                 kfree(work);
8295         }
8296
8297         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8298
8299         drm_crtc_cleanup(crtc);
8300
8301         kfree(intel_crtc);
8302 }
8303
8304 static void intel_unpin_work_fn(struct work_struct *__work)
8305 {
8306         struct intel_unpin_work *work =
8307                 container_of(__work, struct intel_unpin_work, work);
8308         struct drm_device *dev = work->crtc->dev;
8309
8310         mutex_lock(&dev->struct_mutex);
8311         intel_unpin_fb_obj(work->old_fb_obj);
8312         drm_gem_object_unreference(&work->pending_flip_obj->base);
8313         drm_gem_object_unreference(&work->old_fb_obj->base);
8314
8315         intel_update_fbc(dev);
8316         mutex_unlock(&dev->struct_mutex);
8317
8318         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8319         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8320
8321         kfree(work);
8322 }
8323
8324 static void do_intel_finish_page_flip(struct drm_device *dev,
8325                                       struct drm_crtc *crtc)
8326 {
8327         drm_i915_private_t *dev_priv = dev->dev_private;
8328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8329         struct intel_unpin_work *work;
8330         unsigned long flags;
8331
8332         /* Ignore early vblank irqs */
8333         if (intel_crtc == NULL)
8334                 return;
8335
8336         spin_lock_irqsave(&dev->event_lock, flags);
8337         work = intel_crtc->unpin_work;
8338
8339         /* Ensure we don't miss a work->pending update ... */
8340         smp_rmb();
8341
8342         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8343                 spin_unlock_irqrestore(&dev->event_lock, flags);
8344                 return;
8345         }
8346
8347         /* and that the unpin work is consistent wrt ->pending. */
8348         smp_rmb();
8349
8350         intel_crtc->unpin_work = NULL;
8351
8352         if (work->event)
8353                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8354
8355         drm_vblank_put(dev, intel_crtc->pipe);
8356
8357         spin_unlock_irqrestore(&dev->event_lock, flags);
8358
8359         wake_up_all(&dev_priv->pending_flip_queue);
8360
8361         queue_work(dev_priv->wq, &work->work);
8362
8363         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8364 }
8365
8366 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8367 {
8368         drm_i915_private_t *dev_priv = dev->dev_private;
8369         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8370
8371         do_intel_finish_page_flip(dev, crtc);
8372 }
8373
8374 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8375 {
8376         drm_i915_private_t *dev_priv = dev->dev_private;
8377         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8378
8379         do_intel_finish_page_flip(dev, crtc);
8380 }
8381
8382 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8383 {
8384         drm_i915_private_t *dev_priv = dev->dev_private;
8385         struct intel_crtc *intel_crtc =
8386                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8387         unsigned long flags;
8388
8389         /* NB: An MMIO update of the plane base pointer will also
8390          * generate a page-flip completion irq, i.e. every modeset
8391          * is also accompanied by a spurious intel_prepare_page_flip().
8392          */
8393         spin_lock_irqsave(&dev->event_lock, flags);
8394         if (intel_crtc->unpin_work)
8395                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8396         spin_unlock_irqrestore(&dev->event_lock, flags);
8397 }
8398
8399 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8400 {
8401         /* Ensure that the work item is consistent when activating it ... */
8402         smp_wmb();
8403         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8404         /* and that it is marked active as soon as the irq could fire. */
8405         smp_wmb();
8406 }
8407
8408 static int intel_gen2_queue_flip(struct drm_device *dev,
8409                                  struct drm_crtc *crtc,
8410                                  struct drm_framebuffer *fb,
8411                                  struct drm_i915_gem_object *obj,
8412                                  uint32_t flags)
8413 {
8414         struct drm_i915_private *dev_priv = dev->dev_private;
8415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8416         u32 flip_mask;
8417         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8418         int ret;
8419
8420         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8421         if (ret)
8422                 goto err;
8423
8424         ret = intel_ring_begin(ring, 6);
8425         if (ret)
8426                 goto err_unpin;
8427
8428         /* Can't queue multiple flips, so wait for the previous
8429          * one to finish before executing the next.
8430          */
8431         if (intel_crtc->plane)
8432                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8433         else
8434                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8435         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8436         intel_ring_emit(ring, MI_NOOP);
8437         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8438                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8439         intel_ring_emit(ring, fb->pitches[0]);
8440         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8441         intel_ring_emit(ring, 0); /* aux display base address, unused */
8442
8443         intel_mark_page_flip_active(intel_crtc);
8444         __intel_ring_advance(ring);
8445         return 0;
8446
8447 err_unpin:
8448         intel_unpin_fb_obj(obj);
8449 err:
8450         return ret;
8451 }
8452
8453 static int intel_gen3_queue_flip(struct drm_device *dev,
8454                                  struct drm_crtc *crtc,
8455                                  struct drm_framebuffer *fb,
8456                                  struct drm_i915_gem_object *obj,
8457                                  uint32_t flags)
8458 {
8459         struct drm_i915_private *dev_priv = dev->dev_private;
8460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8461         u32 flip_mask;
8462         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8463         int ret;
8464
8465         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8466         if (ret)
8467                 goto err;
8468
8469         ret = intel_ring_begin(ring, 6);
8470         if (ret)
8471                 goto err_unpin;
8472
8473         if (intel_crtc->plane)
8474                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8475         else
8476                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8477         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8478         intel_ring_emit(ring, MI_NOOP);
8479         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8480                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8481         intel_ring_emit(ring, fb->pitches[0]);
8482         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8483         intel_ring_emit(ring, MI_NOOP);
8484
8485         intel_mark_page_flip_active(intel_crtc);
8486         __intel_ring_advance(ring);
8487         return 0;
8488
8489 err_unpin:
8490         intel_unpin_fb_obj(obj);
8491 err:
8492         return ret;
8493 }
8494
8495 static int intel_gen4_queue_flip(struct drm_device *dev,
8496                                  struct drm_crtc *crtc,
8497                                  struct drm_framebuffer *fb,
8498                                  struct drm_i915_gem_object *obj,
8499                                  uint32_t flags)
8500 {
8501         struct drm_i915_private *dev_priv = dev->dev_private;
8502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8503         uint32_t pf, pipesrc;
8504         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8505         int ret;
8506
8507         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8508         if (ret)
8509                 goto err;
8510
8511         ret = intel_ring_begin(ring, 4);
8512         if (ret)
8513                 goto err_unpin;
8514
8515         /* i965+ uses the linear or tiled offsets from the
8516          * Display Registers (which do not change across a page-flip)
8517          * so we need only reprogram the base address.
8518          */
8519         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8520                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8521         intel_ring_emit(ring, fb->pitches[0]);
8522         intel_ring_emit(ring,
8523                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8524                         obj->tiling_mode);
8525
8526         /* XXX Enabling the panel-fitter across page-flip is so far
8527          * untested on non-native modes, so ignore it for now.
8528          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8529          */
8530         pf = 0;
8531         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8532         intel_ring_emit(ring, pf | pipesrc);
8533
8534         intel_mark_page_flip_active(intel_crtc);
8535         __intel_ring_advance(ring);
8536         return 0;
8537
8538 err_unpin:
8539         intel_unpin_fb_obj(obj);
8540 err:
8541         return ret;
8542 }
8543
8544 static int intel_gen6_queue_flip(struct drm_device *dev,
8545                                  struct drm_crtc *crtc,
8546                                  struct drm_framebuffer *fb,
8547                                  struct drm_i915_gem_object *obj,
8548                                  uint32_t flags)
8549 {
8550         struct drm_i915_private *dev_priv = dev->dev_private;
8551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8552         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8553         uint32_t pf, pipesrc;
8554         int ret;
8555
8556         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8557         if (ret)
8558                 goto err;
8559
8560         ret = intel_ring_begin(ring, 4);
8561         if (ret)
8562                 goto err_unpin;
8563
8564         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8565                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8566         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8567         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8568
8569         /* Contrary to the suggestions in the documentation,
8570          * "Enable Panel Fitter" does not seem to be required when page
8571          * flipping with a non-native mode, and worse causes a normal
8572          * modeset to fail.
8573          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8574          */
8575         pf = 0;
8576         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8577         intel_ring_emit(ring, pf | pipesrc);
8578
8579         intel_mark_page_flip_active(intel_crtc);
8580         __intel_ring_advance(ring);
8581         return 0;
8582
8583 err_unpin:
8584         intel_unpin_fb_obj(obj);
8585 err:
8586         return ret;
8587 }
8588
8589 static int intel_gen7_queue_flip(struct drm_device *dev,
8590                                  struct drm_crtc *crtc,
8591                                  struct drm_framebuffer *fb,
8592                                  struct drm_i915_gem_object *obj,
8593                                  uint32_t flags)
8594 {
8595         struct drm_i915_private *dev_priv = dev->dev_private;
8596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8597         struct intel_ring_buffer *ring;
8598         uint32_t plane_bit = 0;
8599         int len, ret;
8600
8601         ring = obj->ring;
8602         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8603                 ring = &dev_priv->ring[BCS];
8604
8605         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8606         if (ret)
8607                 goto err;
8608
8609         switch(intel_crtc->plane) {
8610         case PLANE_A:
8611                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8612                 break;
8613         case PLANE_B:
8614                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8615                 break;
8616         case PLANE_C:
8617                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8618                 break;
8619         default:
8620                 WARN_ONCE(1, "unknown plane in flip command\n");
8621                 ret = -ENODEV;
8622                 goto err_unpin;
8623         }
8624
8625         len = 4;
8626         if (ring->id == RCS)
8627                 len += 6;
8628
8629         ret = intel_ring_begin(ring, len);
8630         if (ret)
8631                 goto err_unpin;
8632
8633         /* Unmask the flip-done completion message. Note that the bspec says that
8634          * we should do this for both the BCS and RCS, and that we must not unmask
8635          * more than one flip event at any time (or ensure that one flip message
8636          * can be sent by waiting for flip-done prior to queueing new flips).
8637          * Experimentation says that BCS works despite DERRMR masking all
8638          * flip-done completion events and that unmasking all planes at once
8639          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8640          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8641          */
8642         if (ring->id == RCS) {
8643                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8644                 intel_ring_emit(ring, DERRMR);
8645                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8646                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8647                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8648                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8649                                 MI_SRM_LRM_GLOBAL_GTT);
8650                 intel_ring_emit(ring, DERRMR);
8651                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8652         }
8653
8654         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8655         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8656         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8657         intel_ring_emit(ring, (MI_NOOP));
8658
8659         intel_mark_page_flip_active(intel_crtc);
8660         __intel_ring_advance(ring);
8661         return 0;
8662
8663 err_unpin:
8664         intel_unpin_fb_obj(obj);
8665 err:
8666         return ret;
8667 }
8668
8669 static int intel_default_queue_flip(struct drm_device *dev,
8670                                     struct drm_crtc *crtc,
8671                                     struct drm_framebuffer *fb,
8672                                     struct drm_i915_gem_object *obj,
8673                                     uint32_t flags)
8674 {
8675         return -ENODEV;
8676 }
8677
8678 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8679                                 struct drm_framebuffer *fb,
8680                                 struct drm_pending_vblank_event *event,
8681                                 uint32_t page_flip_flags)
8682 {
8683         struct drm_device *dev = crtc->dev;
8684         struct drm_i915_private *dev_priv = dev->dev_private;
8685         struct drm_framebuffer *old_fb = crtc->fb;
8686         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8688         struct intel_unpin_work *work;
8689         unsigned long flags;
8690         int ret;
8691
8692         /* Can't change pixel format via MI display flips. */
8693         if (fb->pixel_format != crtc->fb->pixel_format)
8694                 return -EINVAL;
8695
8696         /*
8697          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8698          * Note that pitch changes could also affect these register.
8699          */
8700         if (INTEL_INFO(dev)->gen > 3 &&
8701             (fb->offsets[0] != crtc->fb->offsets[0] ||
8702              fb->pitches[0] != crtc->fb->pitches[0]))
8703                 return -EINVAL;
8704
8705         if (i915_terminally_wedged(&dev_priv->gpu_error))
8706                 goto out_hang;
8707
8708         work = kzalloc(sizeof(*work), GFP_KERNEL);
8709         if (work == NULL)
8710                 return -ENOMEM;
8711
8712         work->event = event;
8713         work->crtc = crtc;
8714         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8715         INIT_WORK(&work->work, intel_unpin_work_fn);
8716
8717         ret = drm_vblank_get(dev, intel_crtc->pipe);
8718         if (ret)
8719                 goto free_work;
8720
8721         /* We borrow the event spin lock for protecting unpin_work */
8722         spin_lock_irqsave(&dev->event_lock, flags);
8723         if (intel_crtc->unpin_work) {
8724                 spin_unlock_irqrestore(&dev->event_lock, flags);
8725                 kfree(work);
8726                 drm_vblank_put(dev, intel_crtc->pipe);
8727
8728                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8729                 return -EBUSY;
8730         }
8731         intel_crtc->unpin_work = work;
8732         spin_unlock_irqrestore(&dev->event_lock, flags);
8733
8734         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8735                 flush_workqueue(dev_priv->wq);
8736
8737         ret = i915_mutex_lock_interruptible(dev);
8738         if (ret)
8739                 goto cleanup;
8740
8741         /* Reference the objects for the scheduled work. */
8742         drm_gem_object_reference(&work->old_fb_obj->base);
8743         drm_gem_object_reference(&obj->base);
8744
8745         crtc->fb = fb;
8746
8747         work->pending_flip_obj = obj;
8748
8749         work->enable_stall_check = true;
8750
8751         atomic_inc(&intel_crtc->unpin_work_count);
8752         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8753
8754         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8755         if (ret)
8756                 goto cleanup_pending;
8757
8758         intel_disable_fbc(dev);
8759         intel_mark_fb_busy(obj, NULL);
8760         mutex_unlock(&dev->struct_mutex);
8761
8762         trace_i915_flip_request(intel_crtc->plane, obj);
8763
8764         return 0;
8765
8766 cleanup_pending:
8767         atomic_dec(&intel_crtc->unpin_work_count);
8768         crtc->fb = old_fb;
8769         drm_gem_object_unreference(&work->old_fb_obj->base);
8770         drm_gem_object_unreference(&obj->base);
8771         mutex_unlock(&dev->struct_mutex);
8772
8773 cleanup:
8774         spin_lock_irqsave(&dev->event_lock, flags);
8775         intel_crtc->unpin_work = NULL;
8776         spin_unlock_irqrestore(&dev->event_lock, flags);
8777
8778         drm_vblank_put(dev, intel_crtc->pipe);
8779 free_work:
8780         kfree(work);
8781
8782         if (ret == -EIO) {
8783 out_hang:
8784                 intel_crtc_wait_for_pending_flips(crtc);
8785                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8786                 if (ret == 0 && event)
8787                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
8788         }
8789         return ret;
8790 }
8791
8792 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8793         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8794         .load_lut = intel_crtc_load_lut,
8795 };
8796
8797 /**
8798  * intel_modeset_update_staged_output_state
8799  *
8800  * Updates the staged output configuration state, e.g. after we've read out the
8801  * current hw state.
8802  */
8803 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8804 {
8805         struct intel_crtc *crtc;
8806         struct intel_encoder *encoder;
8807         struct intel_connector *connector;
8808
8809         list_for_each_entry(connector, &dev->mode_config.connector_list,
8810                             base.head) {
8811                 connector->new_encoder =
8812                         to_intel_encoder(connector->base.encoder);
8813         }
8814
8815         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8816                             base.head) {
8817                 encoder->new_crtc =
8818                         to_intel_crtc(encoder->base.crtc);
8819         }
8820
8821         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8822                             base.head) {
8823                 crtc->new_enabled = crtc->base.enabled;
8824
8825                 if (crtc->new_enabled)
8826                         crtc->new_config = &crtc->config;
8827                 else
8828                         crtc->new_config = NULL;
8829         }
8830 }
8831
8832 /**
8833  * intel_modeset_commit_output_state
8834  *
8835  * This function copies the stage display pipe configuration to the real one.
8836  */
8837 static void intel_modeset_commit_output_state(struct drm_device *dev)
8838 {
8839         struct intel_crtc *crtc;
8840         struct intel_encoder *encoder;
8841         struct intel_connector *connector;
8842
8843         list_for_each_entry(connector, &dev->mode_config.connector_list,
8844                             base.head) {
8845                 connector->base.encoder = &connector->new_encoder->base;
8846         }
8847
8848         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8849                             base.head) {
8850                 encoder->base.crtc = &encoder->new_crtc->base;
8851         }
8852
8853         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8854                             base.head) {
8855                 crtc->base.enabled = crtc->new_enabled;
8856         }
8857 }
8858
8859 static void
8860 connected_sink_compute_bpp(struct intel_connector * connector,
8861                            struct intel_crtc_config *pipe_config)
8862 {
8863         int bpp = pipe_config->pipe_bpp;
8864
8865         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8866                 connector->base.base.id,
8867                 drm_get_connector_name(&connector->base));
8868
8869         /* Don't use an invalid EDID bpc value */
8870         if (connector->base.display_info.bpc &&
8871             connector->base.display_info.bpc * 3 < bpp) {
8872                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8873                               bpp, connector->base.display_info.bpc*3);
8874                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8875         }
8876
8877         /* Clamp bpp to 8 on screens without EDID 1.4 */
8878         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8879                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8880                               bpp);
8881                 pipe_config->pipe_bpp = 24;
8882         }
8883 }
8884
8885 static int
8886 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8887                           struct drm_framebuffer *fb,
8888                           struct intel_crtc_config *pipe_config)
8889 {
8890         struct drm_device *dev = crtc->base.dev;
8891         struct intel_connector *connector;
8892         int bpp;
8893
8894         switch (fb->pixel_format) {
8895         case DRM_FORMAT_C8:
8896                 bpp = 8*3; /* since we go through a colormap */
8897                 break;
8898         case DRM_FORMAT_XRGB1555:
8899         case DRM_FORMAT_ARGB1555:
8900                 /* checked in intel_framebuffer_init already */
8901                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8902                         return -EINVAL;
8903         case DRM_FORMAT_RGB565:
8904                 bpp = 6*3; /* min is 18bpp */
8905                 break;
8906         case DRM_FORMAT_XBGR8888:
8907         case DRM_FORMAT_ABGR8888:
8908                 /* checked in intel_framebuffer_init already */
8909                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8910                         return -EINVAL;
8911         case DRM_FORMAT_XRGB8888:
8912         case DRM_FORMAT_ARGB8888:
8913                 bpp = 8*3;
8914                 break;
8915         case DRM_FORMAT_XRGB2101010:
8916         case DRM_FORMAT_ARGB2101010:
8917         case DRM_FORMAT_XBGR2101010:
8918         case DRM_FORMAT_ABGR2101010:
8919                 /* checked in intel_framebuffer_init already */
8920                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8921                         return -EINVAL;
8922                 bpp = 10*3;
8923                 break;
8924         /* TODO: gen4+ supports 16 bpc floating point, too. */
8925         default:
8926                 DRM_DEBUG_KMS("unsupported depth\n");
8927                 return -EINVAL;
8928         }
8929
8930         pipe_config->pipe_bpp = bpp;
8931
8932         /* Clamp display bpp to EDID value */
8933         list_for_each_entry(connector, &dev->mode_config.connector_list,
8934                             base.head) {
8935                 if (!connector->new_encoder ||
8936                     connector->new_encoder->new_crtc != crtc)
8937                         continue;
8938
8939                 connected_sink_compute_bpp(connector, pipe_config);
8940         }
8941
8942         return bpp;
8943 }
8944
8945 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8946 {
8947         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8948                         "type: 0x%x flags: 0x%x\n",
8949                 mode->crtc_clock,
8950                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8951                 mode->crtc_hsync_end, mode->crtc_htotal,
8952                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8953                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8954 }
8955
8956 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8957                                    struct intel_crtc_config *pipe_config,
8958                                    const char *context)
8959 {
8960         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8961                       context, pipe_name(crtc->pipe));
8962
8963         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8964         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8965                       pipe_config->pipe_bpp, pipe_config->dither);
8966         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8967                       pipe_config->has_pch_encoder,
8968                       pipe_config->fdi_lanes,
8969                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8970                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8971                       pipe_config->fdi_m_n.tu);
8972         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8973                       pipe_config->has_dp_encoder,
8974                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8975                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8976                       pipe_config->dp_m_n.tu);
8977         DRM_DEBUG_KMS("requested mode:\n");
8978         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8979         DRM_DEBUG_KMS("adjusted mode:\n");
8980         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8981         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8982         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8983         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8984                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8985         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8986                       pipe_config->gmch_pfit.control,
8987                       pipe_config->gmch_pfit.pgm_ratios,
8988                       pipe_config->gmch_pfit.lvds_border_bits);
8989         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8990                       pipe_config->pch_pfit.pos,
8991                       pipe_config->pch_pfit.size,
8992                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8993         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8994         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8995 }
8996
8997 static bool check_encoder_cloning(struct drm_crtc *crtc)
8998 {
8999         int num_encoders = 0;
9000         bool uncloneable_encoders = false;
9001         struct intel_encoder *encoder;
9002
9003         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
9004                             base.head) {
9005                 if (&encoder->new_crtc->base != crtc)
9006                         continue;
9007
9008                 num_encoders++;
9009                 if (!encoder->cloneable)
9010                         uncloneable_encoders = true;
9011         }
9012
9013         return !(num_encoders > 1 && uncloneable_encoders);
9014 }
9015
9016 static struct intel_crtc_config *
9017 intel_modeset_pipe_config(struct drm_crtc *crtc,
9018                           struct drm_framebuffer *fb,
9019                           struct drm_display_mode *mode)
9020 {
9021         struct drm_device *dev = crtc->dev;
9022         struct intel_encoder *encoder;
9023         struct intel_crtc_config *pipe_config;
9024         int plane_bpp, ret = -EINVAL;
9025         bool retry = true;
9026
9027         if (!check_encoder_cloning(crtc)) {
9028                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9029                 return ERR_PTR(-EINVAL);
9030         }
9031
9032         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9033         if (!pipe_config)
9034                 return ERR_PTR(-ENOMEM);
9035
9036         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9037         drm_mode_copy(&pipe_config->requested_mode, mode);
9038
9039         pipe_config->cpu_transcoder =
9040                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9041         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9042
9043         /*
9044          * Sanitize sync polarity flags based on requested ones. If neither
9045          * positive or negative polarity is requested, treat this as meaning
9046          * negative polarity.
9047          */
9048         if (!(pipe_config->adjusted_mode.flags &
9049               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9050                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9051
9052         if (!(pipe_config->adjusted_mode.flags &
9053               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9054                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9055
9056         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9057          * plane pixel format and any sink constraints into account. Returns the
9058          * source plane bpp so that dithering can be selected on mismatches
9059          * after encoders and crtc also have had their say. */
9060         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9061                                               fb, pipe_config);
9062         if (plane_bpp < 0)
9063                 goto fail;
9064
9065         /*
9066          * Determine the real pipe dimensions. Note that stereo modes can
9067          * increase the actual pipe size due to the frame doubling and
9068          * insertion of additional space for blanks between the frame. This
9069          * is stored in the crtc timings. We use the requested mode to do this
9070          * computation to clearly distinguish it from the adjusted mode, which
9071          * can be changed by the connectors in the below retry loop.
9072          */
9073         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9074         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9075         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9076
9077 encoder_retry:
9078         /* Ensure the port clock defaults are reset when retrying. */
9079         pipe_config->port_clock = 0;
9080         pipe_config->pixel_multiplier = 1;
9081
9082         /* Fill in default crtc timings, allow encoders to overwrite them. */
9083         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9084
9085         /* Pass our mode to the connectors and the CRTC to give them a chance to
9086          * adjust it according to limitations or connector properties, and also
9087          * a chance to reject the mode entirely.
9088          */
9089         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9090                             base.head) {
9091
9092                 if (&encoder->new_crtc->base != crtc)
9093                         continue;
9094
9095                 if (!(encoder->compute_config(encoder, pipe_config))) {
9096                         DRM_DEBUG_KMS("Encoder config failure\n");
9097                         goto fail;
9098                 }
9099         }
9100
9101         /* Set default port clock if not overwritten by the encoder. Needs to be
9102          * done afterwards in case the encoder adjusts the mode. */
9103         if (!pipe_config->port_clock)
9104                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9105                         * pipe_config->pixel_multiplier;
9106
9107         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9108         if (ret < 0) {
9109                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9110                 goto fail;
9111         }
9112
9113         if (ret == RETRY) {
9114                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9115                         ret = -EINVAL;
9116                         goto fail;
9117                 }
9118
9119                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9120                 retry = false;
9121                 goto encoder_retry;
9122         }
9123
9124         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9125         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9126                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9127
9128         return pipe_config;
9129 fail:
9130         kfree(pipe_config);
9131         return ERR_PTR(ret);
9132 }
9133
9134 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9135  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9136 static void
9137 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9138                              unsigned *prepare_pipes, unsigned *disable_pipes)
9139 {
9140         struct intel_crtc *intel_crtc;
9141         struct drm_device *dev = crtc->dev;
9142         struct intel_encoder *encoder;
9143         struct intel_connector *connector;
9144         struct drm_crtc *tmp_crtc;
9145
9146         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9147
9148         /* Check which crtcs have changed outputs connected to them, these need
9149          * to be part of the prepare_pipes mask. We don't (yet) support global
9150          * modeset across multiple crtcs, so modeset_pipes will only have one
9151          * bit set at most. */
9152         list_for_each_entry(connector, &dev->mode_config.connector_list,
9153                             base.head) {
9154                 if (connector->base.encoder == &connector->new_encoder->base)
9155                         continue;
9156
9157                 if (connector->base.encoder) {
9158                         tmp_crtc = connector->base.encoder->crtc;
9159
9160                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9161                 }
9162
9163                 if (connector->new_encoder)
9164                         *prepare_pipes |=
9165                                 1 << connector->new_encoder->new_crtc->pipe;
9166         }
9167
9168         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9169                             base.head) {
9170                 if (encoder->base.crtc == &encoder->new_crtc->base)
9171                         continue;
9172
9173                 if (encoder->base.crtc) {
9174                         tmp_crtc = encoder->base.crtc;
9175
9176                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9177                 }
9178
9179                 if (encoder->new_crtc)
9180                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9181         }
9182
9183         /* Check for pipes that will be enabled/disabled ... */
9184         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9185                             base.head) {
9186                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9187                         continue;
9188
9189                 if (!intel_crtc->new_enabled)
9190                         *disable_pipes |= 1 << intel_crtc->pipe;
9191                 else
9192                         *prepare_pipes |= 1 << intel_crtc->pipe;
9193         }
9194
9195
9196         /* set_mode is also used to update properties on life display pipes. */
9197         intel_crtc = to_intel_crtc(crtc);
9198         if (intel_crtc->new_enabled)
9199                 *prepare_pipes |= 1 << intel_crtc->pipe;
9200
9201         /*
9202          * For simplicity do a full modeset on any pipe where the output routing
9203          * changed. We could be more clever, but that would require us to be
9204          * more careful with calling the relevant encoder->mode_set functions.
9205          */
9206         if (*prepare_pipes)
9207                 *modeset_pipes = *prepare_pipes;
9208
9209         /* ... and mask these out. */
9210         *modeset_pipes &= ~(*disable_pipes);
9211         *prepare_pipes &= ~(*disable_pipes);
9212
9213         /*
9214          * HACK: We don't (yet) fully support global modesets. intel_set_config
9215          * obies this rule, but the modeset restore mode of
9216          * intel_modeset_setup_hw_state does not.
9217          */
9218         *modeset_pipes &= 1 << intel_crtc->pipe;
9219         *prepare_pipes &= 1 << intel_crtc->pipe;
9220
9221         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9222                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9223 }
9224
9225 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9226 {
9227         struct drm_encoder *encoder;
9228         struct drm_device *dev = crtc->dev;
9229
9230         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9231                 if (encoder->crtc == crtc)
9232                         return true;
9233
9234         return false;
9235 }
9236
9237 static void
9238 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9239 {
9240         struct intel_encoder *intel_encoder;
9241         struct intel_crtc *intel_crtc;
9242         struct drm_connector *connector;
9243
9244         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9245                             base.head) {
9246                 if (!intel_encoder->base.crtc)
9247                         continue;
9248
9249                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9250
9251                 if (prepare_pipes & (1 << intel_crtc->pipe))
9252                         intel_encoder->connectors_active = false;
9253         }
9254
9255         intel_modeset_commit_output_state(dev);
9256
9257         /* Double check state. */
9258         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9259                             base.head) {
9260                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9261                 WARN_ON(intel_crtc->new_config &&
9262                         intel_crtc->new_config != &intel_crtc->config);
9263                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9264         }
9265
9266         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9267                 if (!connector->encoder || !connector->encoder->crtc)
9268                         continue;
9269
9270                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9271
9272                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9273                         struct drm_property *dpms_property =
9274                                 dev->mode_config.dpms_property;
9275
9276                         connector->dpms = DRM_MODE_DPMS_ON;
9277                         drm_object_property_set_value(&connector->base,
9278                                                          dpms_property,
9279                                                          DRM_MODE_DPMS_ON);
9280
9281                         intel_encoder = to_intel_encoder(connector->encoder);
9282                         intel_encoder->connectors_active = true;
9283                 }
9284         }
9285
9286 }
9287
9288 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9289 {
9290         int diff;
9291
9292         if (clock1 == clock2)
9293                 return true;
9294
9295         if (!clock1 || !clock2)
9296                 return false;
9297
9298         diff = abs(clock1 - clock2);
9299
9300         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9301                 return true;
9302
9303         return false;
9304 }
9305
9306 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9307         list_for_each_entry((intel_crtc), \
9308                             &(dev)->mode_config.crtc_list, \
9309                             base.head) \
9310                 if (mask & (1 <<(intel_crtc)->pipe))
9311
9312 static bool
9313 intel_pipe_config_compare(struct drm_device *dev,
9314                           struct intel_crtc_config *current_config,
9315                           struct intel_crtc_config *pipe_config)
9316 {
9317 #define PIPE_CONF_CHECK_X(name) \
9318         if (current_config->name != pipe_config->name) { \
9319                 DRM_ERROR("mismatch in " #name " " \
9320                           "(expected 0x%08x, found 0x%08x)\n", \
9321                           current_config->name, \
9322                           pipe_config->name); \
9323                 return false; \
9324         }
9325
9326 #define PIPE_CONF_CHECK_I(name) \
9327         if (current_config->name != pipe_config->name) { \
9328                 DRM_ERROR("mismatch in " #name " " \
9329                           "(expected %i, found %i)\n", \
9330                           current_config->name, \
9331                           pipe_config->name); \
9332                 return false; \
9333         }
9334
9335 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9336         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9337                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9338                           "(expected %i, found %i)\n", \
9339                           current_config->name & (mask), \
9340                           pipe_config->name & (mask)); \
9341                 return false; \
9342         }
9343
9344 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9345         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9346                 DRM_ERROR("mismatch in " #name " " \
9347                           "(expected %i, found %i)\n", \
9348                           current_config->name, \
9349                           pipe_config->name); \
9350                 return false; \
9351         }
9352
9353 #define PIPE_CONF_QUIRK(quirk)  \
9354         ((current_config->quirks | pipe_config->quirks) & (quirk))
9355
9356         PIPE_CONF_CHECK_I(cpu_transcoder);
9357
9358         PIPE_CONF_CHECK_I(has_pch_encoder);
9359         PIPE_CONF_CHECK_I(fdi_lanes);
9360         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9361         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9362         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9363         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9364         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9365
9366         PIPE_CONF_CHECK_I(has_dp_encoder);
9367         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9368         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9369         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9370         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9371         PIPE_CONF_CHECK_I(dp_m_n.tu);
9372
9373         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9374         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9375         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9376         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9377         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9378         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9379
9380         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9381         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9382         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9383         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9384         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9385         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9386
9387         PIPE_CONF_CHECK_I(pixel_multiplier);
9388
9389         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9390                               DRM_MODE_FLAG_INTERLACE);
9391
9392         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9393                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9394                                       DRM_MODE_FLAG_PHSYNC);
9395                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9396                                       DRM_MODE_FLAG_NHSYNC);
9397                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9398                                       DRM_MODE_FLAG_PVSYNC);
9399                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9400                                       DRM_MODE_FLAG_NVSYNC);
9401         }
9402
9403         PIPE_CONF_CHECK_I(pipe_src_w);
9404         PIPE_CONF_CHECK_I(pipe_src_h);
9405
9406         PIPE_CONF_CHECK_I(gmch_pfit.control);
9407         /* pfit ratios are autocomputed by the hw on gen4+ */
9408         if (INTEL_INFO(dev)->gen < 4)
9409                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9410         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9411         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9412         if (current_config->pch_pfit.enabled) {
9413                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9414                 PIPE_CONF_CHECK_I(pch_pfit.size);
9415         }
9416
9417         /* BDW+ don't expose a synchronous way to read the state */
9418         if (IS_HASWELL(dev))
9419                 PIPE_CONF_CHECK_I(ips_enabled);
9420
9421         PIPE_CONF_CHECK_I(double_wide);
9422
9423         PIPE_CONF_CHECK_I(shared_dpll);
9424         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9425         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9426         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9427         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9428
9429         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9430                 PIPE_CONF_CHECK_I(pipe_bpp);
9431
9432         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9433         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9434
9435 #undef PIPE_CONF_CHECK_X
9436 #undef PIPE_CONF_CHECK_I
9437 #undef PIPE_CONF_CHECK_FLAGS
9438 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9439 #undef PIPE_CONF_QUIRK
9440
9441         return true;
9442 }
9443
9444 static void
9445 check_connector_state(struct drm_device *dev)
9446 {
9447         struct intel_connector *connector;
9448
9449         list_for_each_entry(connector, &dev->mode_config.connector_list,
9450                             base.head) {
9451                 /* This also checks the encoder/connector hw state with the
9452                  * ->get_hw_state callbacks. */
9453                 intel_connector_check_state(connector);
9454
9455                 WARN(&connector->new_encoder->base != connector->base.encoder,
9456                      "connector's staged encoder doesn't match current encoder\n");
9457         }
9458 }
9459
9460 static void
9461 check_encoder_state(struct drm_device *dev)
9462 {
9463         struct intel_encoder *encoder;
9464         struct intel_connector *connector;
9465
9466         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9467                             base.head) {
9468                 bool enabled = false;
9469                 bool active = false;
9470                 enum pipe pipe, tracked_pipe;
9471
9472                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9473                               encoder->base.base.id,
9474                               drm_get_encoder_name(&encoder->base));
9475
9476                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9477                      "encoder's stage crtc doesn't match current crtc\n");
9478                 WARN(encoder->connectors_active && !encoder->base.crtc,
9479                      "encoder's active_connectors set, but no crtc\n");
9480
9481                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9482                                     base.head) {
9483                         if (connector->base.encoder != &encoder->base)
9484                                 continue;
9485                         enabled = true;
9486                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9487                                 active = true;
9488                 }
9489                 WARN(!!encoder->base.crtc != enabled,
9490                      "encoder's enabled state mismatch "
9491                      "(expected %i, found %i)\n",
9492                      !!encoder->base.crtc, enabled);
9493                 WARN(active && !encoder->base.crtc,
9494                      "active encoder with no crtc\n");
9495
9496                 WARN(encoder->connectors_active != active,
9497                      "encoder's computed active state doesn't match tracked active state "
9498                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9499
9500                 active = encoder->get_hw_state(encoder, &pipe);
9501                 WARN(active != encoder->connectors_active,
9502                      "encoder's hw state doesn't match sw tracking "
9503                      "(expected %i, found %i)\n",
9504                      encoder->connectors_active, active);
9505
9506                 if (!encoder->base.crtc)
9507                         continue;
9508
9509                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9510                 WARN(active && pipe != tracked_pipe,
9511                      "active encoder's pipe doesn't match"
9512                      "(expected %i, found %i)\n",
9513                      tracked_pipe, pipe);
9514
9515         }
9516 }
9517
9518 static void
9519 check_crtc_state(struct drm_device *dev)
9520 {
9521         drm_i915_private_t *dev_priv = dev->dev_private;
9522         struct intel_crtc *crtc;
9523         struct intel_encoder *encoder;
9524         struct intel_crtc_config pipe_config;
9525
9526         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9527                             base.head) {
9528                 bool enabled = false;
9529                 bool active = false;
9530
9531                 memset(&pipe_config, 0, sizeof(pipe_config));
9532
9533                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9534                               crtc->base.base.id);
9535
9536                 WARN(crtc->active && !crtc->base.enabled,
9537                      "active crtc, but not enabled in sw tracking\n");
9538
9539                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9540                                     base.head) {
9541                         if (encoder->base.crtc != &crtc->base)
9542                                 continue;
9543                         enabled = true;
9544                         if (encoder->connectors_active)
9545                                 active = true;
9546                 }
9547
9548                 WARN(active != crtc->active,
9549                      "crtc's computed active state doesn't match tracked active state "
9550                      "(expected %i, found %i)\n", active, crtc->active);
9551                 WARN(enabled != crtc->base.enabled,
9552                      "crtc's computed enabled state doesn't match tracked enabled state "
9553                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9554
9555                 active = dev_priv->display.get_pipe_config(crtc,
9556                                                            &pipe_config);
9557
9558                 /* hw state is inconsistent with the pipe A quirk */
9559                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9560                         active = crtc->active;
9561
9562                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9563                                     base.head) {
9564                         enum pipe pipe;
9565                         if (encoder->base.crtc != &crtc->base)
9566                                 continue;
9567                         if (encoder->get_hw_state(encoder, &pipe))
9568                                 encoder->get_config(encoder, &pipe_config);
9569                 }
9570
9571                 WARN(crtc->active != active,
9572                      "crtc active state doesn't match with hw state "
9573                      "(expected %i, found %i)\n", crtc->active, active);
9574
9575                 if (active &&
9576                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9577                         WARN(1, "pipe state doesn't match!\n");
9578                         intel_dump_pipe_config(crtc, &pipe_config,
9579                                                "[hw state]");
9580                         intel_dump_pipe_config(crtc, &crtc->config,
9581                                                "[sw state]");
9582                 }
9583         }
9584 }
9585
9586 static void
9587 check_shared_dpll_state(struct drm_device *dev)
9588 {
9589         drm_i915_private_t *dev_priv = dev->dev_private;
9590         struct intel_crtc *crtc;
9591         struct intel_dpll_hw_state dpll_hw_state;
9592         int i;
9593
9594         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9595                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9596                 int enabled_crtcs = 0, active_crtcs = 0;
9597                 bool active;
9598
9599                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9600
9601                 DRM_DEBUG_KMS("%s\n", pll->name);
9602
9603                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9604
9605                 WARN(pll->active > pll->refcount,
9606                      "more active pll users than references: %i vs %i\n",
9607                      pll->active, pll->refcount);
9608                 WARN(pll->active && !pll->on,
9609                      "pll in active use but not on in sw tracking\n");
9610                 WARN(pll->on && !pll->active,
9611                      "pll in on but not on in use in sw tracking\n");
9612                 WARN(pll->on != active,
9613                      "pll on state mismatch (expected %i, found %i)\n",
9614                      pll->on, active);
9615
9616                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9617                                     base.head) {
9618                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9619                                 enabled_crtcs++;
9620                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9621                                 active_crtcs++;
9622                 }
9623                 WARN(pll->active != active_crtcs,
9624                      "pll active crtcs mismatch (expected %i, found %i)\n",
9625                      pll->active, active_crtcs);
9626                 WARN(pll->refcount != enabled_crtcs,
9627                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9628                      pll->refcount, enabled_crtcs);
9629
9630                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9631                                        sizeof(dpll_hw_state)),
9632                      "pll hw state mismatch\n");
9633         }
9634 }
9635
9636 void
9637 intel_modeset_check_state(struct drm_device *dev)
9638 {
9639         check_connector_state(dev);
9640         check_encoder_state(dev);
9641         check_crtc_state(dev);
9642         check_shared_dpll_state(dev);
9643 }
9644
9645 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9646                                      int dotclock)
9647 {
9648         /*
9649          * FDI already provided one idea for the dotclock.
9650          * Yell if the encoder disagrees.
9651          */
9652         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9653              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9654              pipe_config->adjusted_mode.crtc_clock, dotclock);
9655 }
9656
9657 static int __intel_set_mode(struct drm_crtc *crtc,
9658                             struct drm_display_mode *mode,
9659                             int x, int y, struct drm_framebuffer *fb)
9660 {
9661         struct drm_device *dev = crtc->dev;
9662         drm_i915_private_t *dev_priv = dev->dev_private;
9663         struct drm_display_mode *saved_mode;
9664         struct intel_crtc_config *pipe_config = NULL;
9665         struct intel_crtc *intel_crtc;
9666         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9667         int ret = 0;
9668
9669         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9670         if (!saved_mode)
9671                 return -ENOMEM;
9672
9673         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9674                                      &prepare_pipes, &disable_pipes);
9675
9676         *saved_mode = crtc->mode;
9677
9678         /* Hack: Because we don't (yet) support global modeset on multiple
9679          * crtcs, we don't keep track of the new mode for more than one crtc.
9680          * Hence simply check whether any bit is set in modeset_pipes in all the
9681          * pieces of code that are not yet converted to deal with mutliple crtcs
9682          * changing their mode at the same time. */
9683         if (modeset_pipes) {
9684                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9685                 if (IS_ERR(pipe_config)) {
9686                         ret = PTR_ERR(pipe_config);
9687                         pipe_config = NULL;
9688
9689                         goto out;
9690                 }
9691                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9692                                        "[modeset]");
9693                 to_intel_crtc(crtc)->new_config = pipe_config;
9694         }
9695
9696         /*
9697          * See if the config requires any additional preparation, e.g.
9698          * to adjust global state with pipes off.  We need to do this
9699          * here so we can get the modeset_pipe updated config for the new
9700          * mode set on this crtc.  For other crtcs we need to use the
9701          * adjusted_mode bits in the crtc directly.
9702          */
9703         if (IS_VALLEYVIEW(dev)) {
9704                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9705
9706                 /* may have added more to prepare_pipes than we should */
9707                 prepare_pipes &= ~disable_pipes;
9708         }
9709
9710         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9711                 intel_crtc_disable(&intel_crtc->base);
9712
9713         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9714                 if (intel_crtc->base.enabled)
9715                         dev_priv->display.crtc_disable(&intel_crtc->base);
9716         }
9717
9718         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9719          * to set it here already despite that we pass it down the callchain.
9720          */
9721         if (modeset_pipes) {
9722                 crtc->mode = *mode;
9723                 /* mode_set/enable/disable functions rely on a correct pipe
9724                  * config. */
9725                 to_intel_crtc(crtc)->config = *pipe_config;
9726                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9727
9728                 /*
9729                  * Calculate and store various constants which
9730                  * are later needed by vblank and swap-completion
9731                  * timestamping. They are derived from true hwmode.
9732                  */
9733                 drm_calc_timestamping_constants(crtc,
9734                                                 &pipe_config->adjusted_mode);
9735         }
9736
9737         /* Only after disabling all output pipelines that will be changed can we
9738          * update the the output configuration. */
9739         intel_modeset_update_state(dev, prepare_pipes);
9740
9741         if (dev_priv->display.modeset_global_resources)
9742                 dev_priv->display.modeset_global_resources(dev);
9743
9744         /* Set up the DPLL and any encoders state that needs to adjust or depend
9745          * on the DPLL.
9746          */
9747         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9748                 ret = intel_crtc_mode_set(&intel_crtc->base,
9749                                           x, y, fb);
9750                 if (ret)
9751                         goto done;
9752         }
9753
9754         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9755         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9756                 dev_priv->display.crtc_enable(&intel_crtc->base);
9757
9758         /* FIXME: add subpixel order */
9759 done:
9760         if (ret && crtc->enabled)
9761                 crtc->mode = *saved_mode;
9762
9763 out:
9764         kfree(pipe_config);
9765         kfree(saved_mode);
9766         return ret;
9767 }
9768
9769 static int intel_set_mode(struct drm_crtc *crtc,
9770                           struct drm_display_mode *mode,
9771                           int x, int y, struct drm_framebuffer *fb)
9772 {
9773         int ret;
9774
9775         ret = __intel_set_mode(crtc, mode, x, y, fb);
9776
9777         if (ret == 0)
9778                 intel_modeset_check_state(crtc->dev);
9779
9780         return ret;
9781 }
9782
9783 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9784 {
9785         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9786 }
9787
9788 #undef for_each_intel_crtc_masked
9789
9790 static void intel_set_config_free(struct intel_set_config *config)
9791 {
9792         if (!config)
9793                 return;
9794
9795         kfree(config->save_connector_encoders);
9796         kfree(config->save_encoder_crtcs);
9797         kfree(config->save_crtc_enabled);
9798         kfree(config);
9799 }
9800
9801 static int intel_set_config_save_state(struct drm_device *dev,
9802                                        struct intel_set_config *config)
9803 {
9804         struct drm_crtc *crtc;
9805         struct drm_encoder *encoder;
9806         struct drm_connector *connector;
9807         int count;
9808
9809         config->save_crtc_enabled =
9810                 kcalloc(dev->mode_config.num_crtc,
9811                         sizeof(bool), GFP_KERNEL);
9812         if (!config->save_crtc_enabled)
9813                 return -ENOMEM;
9814
9815         config->save_encoder_crtcs =
9816                 kcalloc(dev->mode_config.num_encoder,
9817                         sizeof(struct drm_crtc *), GFP_KERNEL);
9818         if (!config->save_encoder_crtcs)
9819                 return -ENOMEM;
9820
9821         config->save_connector_encoders =
9822                 kcalloc(dev->mode_config.num_connector,
9823                         sizeof(struct drm_encoder *), GFP_KERNEL);
9824         if (!config->save_connector_encoders)
9825                 return -ENOMEM;
9826
9827         /* Copy data. Note that driver private data is not affected.
9828          * Should anything bad happen only the expected state is
9829          * restored, not the drivers personal bookkeeping.
9830          */
9831         count = 0;
9832         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9833                 config->save_crtc_enabled[count++] = crtc->enabled;
9834         }
9835
9836         count = 0;
9837         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9838                 config->save_encoder_crtcs[count++] = encoder->crtc;
9839         }
9840
9841         count = 0;
9842         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9843                 config->save_connector_encoders[count++] = connector->encoder;
9844         }
9845
9846         return 0;
9847 }
9848
9849 static void intel_set_config_restore_state(struct drm_device *dev,
9850                                            struct intel_set_config *config)
9851 {
9852         struct intel_crtc *crtc;
9853         struct intel_encoder *encoder;
9854         struct intel_connector *connector;
9855         int count;
9856
9857         count = 0;
9858         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9859                 crtc->new_enabled = config->save_crtc_enabled[count++];
9860
9861                 if (crtc->new_enabled)
9862                         crtc->new_config = &crtc->config;
9863                 else
9864                         crtc->new_config = NULL;
9865         }
9866
9867         count = 0;
9868         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9869                 encoder->new_crtc =
9870                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9871         }
9872
9873         count = 0;
9874         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9875                 connector->new_encoder =
9876                         to_intel_encoder(config->save_connector_encoders[count++]);
9877         }
9878 }
9879
9880 static bool
9881 is_crtc_connector_off(struct drm_mode_set *set)
9882 {
9883         int i;
9884
9885         if (set->num_connectors == 0)
9886                 return false;
9887
9888         if (WARN_ON(set->connectors == NULL))
9889                 return false;
9890
9891         for (i = 0; i < set->num_connectors; i++)
9892                 if (set->connectors[i]->encoder &&
9893                     set->connectors[i]->encoder->crtc == set->crtc &&
9894                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9895                         return true;
9896
9897         return false;
9898 }
9899
9900 static void
9901 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9902                                       struct intel_set_config *config)
9903 {
9904
9905         /* We should be able to check here if the fb has the same properties
9906          * and then just flip_or_move it */
9907         if (is_crtc_connector_off(set)) {
9908                 config->mode_changed = true;
9909         } else if (set->crtc->fb != set->fb) {
9910                 /* If we have no fb then treat it as a full mode set */
9911                 if (set->crtc->fb == NULL) {
9912                         struct intel_crtc *intel_crtc =
9913                                 to_intel_crtc(set->crtc);
9914
9915                         if (intel_crtc->active && i915.fastboot) {
9916                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9917                                 config->fb_changed = true;
9918                         } else {
9919                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9920                                 config->mode_changed = true;
9921                         }
9922                 } else if (set->fb == NULL) {
9923                         config->mode_changed = true;
9924                 } else if (set->fb->pixel_format !=
9925                            set->crtc->fb->pixel_format) {
9926                         config->mode_changed = true;
9927                 } else {
9928                         config->fb_changed = true;
9929                 }
9930         }
9931
9932         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9933                 config->fb_changed = true;
9934
9935         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9936                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9937                 drm_mode_debug_printmodeline(&set->crtc->mode);
9938                 drm_mode_debug_printmodeline(set->mode);
9939                 config->mode_changed = true;
9940         }
9941
9942         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9943                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9944 }
9945
9946 static int
9947 intel_modeset_stage_output_state(struct drm_device *dev,
9948                                  struct drm_mode_set *set,
9949                                  struct intel_set_config *config)
9950 {
9951         struct intel_connector *connector;
9952         struct intel_encoder *encoder;
9953         struct intel_crtc *crtc;
9954         int ro;
9955
9956         /* The upper layers ensure that we either disable a crtc or have a list
9957          * of connectors. For paranoia, double-check this. */
9958         WARN_ON(!set->fb && (set->num_connectors != 0));
9959         WARN_ON(set->fb && (set->num_connectors == 0));
9960
9961         list_for_each_entry(connector, &dev->mode_config.connector_list,
9962                             base.head) {
9963                 /* Otherwise traverse passed in connector list and get encoders
9964                  * for them. */
9965                 for (ro = 0; ro < set->num_connectors; ro++) {
9966                         if (set->connectors[ro] == &connector->base) {
9967                                 connector->new_encoder = connector->encoder;
9968                                 break;
9969                         }
9970                 }
9971
9972                 /* If we disable the crtc, disable all its connectors. Also, if
9973                  * the connector is on the changing crtc but not on the new
9974                  * connector list, disable it. */
9975                 if ((!set->fb || ro == set->num_connectors) &&
9976                     connector->base.encoder &&
9977                     connector->base.encoder->crtc == set->crtc) {
9978                         connector->new_encoder = NULL;
9979
9980                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9981                                 connector->base.base.id,
9982                                 drm_get_connector_name(&connector->base));
9983                 }
9984
9985
9986                 if (&connector->new_encoder->base != connector->base.encoder) {
9987                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9988                         config->mode_changed = true;
9989                 }
9990         }
9991         /* connector->new_encoder is now updated for all connectors. */
9992
9993         /* Update crtc of enabled connectors. */
9994         list_for_each_entry(connector, &dev->mode_config.connector_list,
9995                             base.head) {
9996                 struct drm_crtc *new_crtc;
9997
9998                 if (!connector->new_encoder)
9999                         continue;
10000
10001                 new_crtc = connector->new_encoder->base.crtc;
10002
10003                 for (ro = 0; ro < set->num_connectors; ro++) {
10004                         if (set->connectors[ro] == &connector->base)
10005                                 new_crtc = set->crtc;
10006                 }
10007
10008                 /* Make sure the new CRTC will work with the encoder */
10009                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10010                                          new_crtc)) {
10011                         return -EINVAL;
10012                 }
10013                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10014
10015                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10016                         connector->base.base.id,
10017                         drm_get_connector_name(&connector->base),
10018                         new_crtc->base.id);
10019         }
10020
10021         /* Check for any encoders that needs to be disabled. */
10022         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10023                             base.head) {
10024                 int num_connectors = 0;
10025                 list_for_each_entry(connector,
10026                                     &dev->mode_config.connector_list,
10027                                     base.head) {
10028                         if (connector->new_encoder == encoder) {
10029                                 WARN_ON(!connector->new_encoder->new_crtc);
10030                                 num_connectors++;
10031                         }
10032                 }
10033
10034                 if (num_connectors == 0)
10035                         encoder->new_crtc = NULL;
10036                 else if (num_connectors > 1)
10037                         return -EINVAL;
10038
10039                 /* Only now check for crtc changes so we don't miss encoders
10040                  * that will be disabled. */
10041                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10042                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10043                         config->mode_changed = true;
10044                 }
10045         }
10046         /* Now we've also updated encoder->new_crtc for all encoders. */
10047
10048         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10049                             base.head) {
10050                 crtc->new_enabled = false;
10051
10052                 list_for_each_entry(encoder,
10053                                     &dev->mode_config.encoder_list,
10054                                     base.head) {
10055                         if (encoder->new_crtc == crtc) {
10056                                 crtc->new_enabled = true;
10057                                 break;
10058                         }
10059                 }
10060
10061                 if (crtc->new_enabled != crtc->base.enabled) {
10062                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10063                                       crtc->new_enabled ? "en" : "dis");
10064                         config->mode_changed = true;
10065                 }
10066
10067                 if (crtc->new_enabled)
10068                         crtc->new_config = &crtc->config;
10069                 else
10070                         crtc->new_config = NULL;
10071         }
10072
10073         return 0;
10074 }
10075
10076 static void disable_crtc_nofb(struct intel_crtc *crtc)
10077 {
10078         struct drm_device *dev = crtc->base.dev;
10079         struct intel_encoder *encoder;
10080         struct intel_connector *connector;
10081
10082         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10083                       pipe_name(crtc->pipe));
10084
10085         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10086                 if (connector->new_encoder &&
10087                     connector->new_encoder->new_crtc == crtc)
10088                         connector->new_encoder = NULL;
10089         }
10090
10091         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10092                 if (encoder->new_crtc == crtc)
10093                         encoder->new_crtc = NULL;
10094         }
10095
10096         crtc->new_enabled = false;
10097         crtc->new_config = NULL;
10098 }
10099
10100 static int intel_crtc_set_config(struct drm_mode_set *set)
10101 {
10102         struct drm_device *dev;
10103         struct drm_mode_set save_set;
10104         struct intel_set_config *config;
10105         int ret;
10106
10107         BUG_ON(!set);
10108         BUG_ON(!set->crtc);
10109         BUG_ON(!set->crtc->helper_private);
10110
10111         /* Enforce sane interface api - has been abused by the fb helper. */
10112         BUG_ON(!set->mode && set->fb);
10113         BUG_ON(set->fb && set->num_connectors == 0);
10114
10115         if (set->fb) {
10116                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10117                                 set->crtc->base.id, set->fb->base.id,
10118                                 (int)set->num_connectors, set->x, set->y);
10119         } else {
10120                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10121         }
10122
10123         dev = set->crtc->dev;
10124
10125         ret = -ENOMEM;
10126         config = kzalloc(sizeof(*config), GFP_KERNEL);
10127         if (!config)
10128                 goto out_config;
10129
10130         ret = intel_set_config_save_state(dev, config);
10131         if (ret)
10132                 goto out_config;
10133
10134         save_set.crtc = set->crtc;
10135         save_set.mode = &set->crtc->mode;
10136         save_set.x = set->crtc->x;
10137         save_set.y = set->crtc->y;
10138         save_set.fb = set->crtc->fb;
10139
10140         /* Compute whether we need a full modeset, only an fb base update or no
10141          * change at all. In the future we might also check whether only the
10142          * mode changed, e.g. for LVDS where we only change the panel fitter in
10143          * such cases. */
10144         intel_set_config_compute_mode_changes(set, config);
10145
10146         ret = intel_modeset_stage_output_state(dev, set, config);
10147         if (ret)
10148                 goto fail;
10149
10150         if (config->mode_changed) {
10151                 ret = intel_set_mode(set->crtc, set->mode,
10152                                      set->x, set->y, set->fb);
10153         } else if (config->fb_changed) {
10154                 intel_crtc_wait_for_pending_flips(set->crtc);
10155
10156                 ret = intel_pipe_set_base(set->crtc,
10157                                           set->x, set->y, set->fb);
10158                 /*
10159                  * In the fastboot case this may be our only check of the
10160                  * state after boot.  It would be better to only do it on
10161                  * the first update, but we don't have a nice way of doing that
10162                  * (and really, set_config isn't used much for high freq page
10163                  * flipping, so increasing its cost here shouldn't be a big
10164                  * deal).
10165                  */
10166                 if (i915.fastboot && ret == 0)
10167                         intel_modeset_check_state(set->crtc->dev);
10168         }
10169
10170         if (ret) {
10171                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10172                               set->crtc->base.id, ret);
10173 fail:
10174                 intel_set_config_restore_state(dev, config);
10175
10176                 /*
10177                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10178                  * force the pipe off to avoid oopsing in the modeset code
10179                  * due to fb==NULL. This should only happen during boot since
10180                  * we don't yet reconstruct the FB from the hardware state.
10181                  */
10182                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10183                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10184
10185                 /* Try to restore the config */
10186                 if (config->mode_changed &&
10187                     intel_set_mode(save_set.crtc, save_set.mode,
10188                                    save_set.x, save_set.y, save_set.fb))
10189                         DRM_ERROR("failed to restore config after modeset failure\n");
10190         }
10191
10192 out_config:
10193         intel_set_config_free(config);
10194         return ret;
10195 }
10196
10197 static const struct drm_crtc_funcs intel_crtc_funcs = {
10198         .cursor_set = intel_crtc_cursor_set,
10199         .cursor_move = intel_crtc_cursor_move,
10200         .gamma_set = intel_crtc_gamma_set,
10201         .set_config = intel_crtc_set_config,
10202         .destroy = intel_crtc_destroy,
10203         .page_flip = intel_crtc_page_flip,
10204 };
10205
10206 static void intel_cpu_pll_init(struct drm_device *dev)
10207 {
10208         if (HAS_DDI(dev))
10209                 intel_ddi_pll_init(dev);
10210 }
10211
10212 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10213                                       struct intel_shared_dpll *pll,
10214                                       struct intel_dpll_hw_state *hw_state)
10215 {
10216         uint32_t val;
10217
10218         val = I915_READ(PCH_DPLL(pll->id));
10219         hw_state->dpll = val;
10220         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10221         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10222
10223         return val & DPLL_VCO_ENABLE;
10224 }
10225
10226 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10227                                   struct intel_shared_dpll *pll)
10228 {
10229         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10230         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10231 }
10232
10233 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10234                                 struct intel_shared_dpll *pll)
10235 {
10236         /* PCH refclock must be enabled first */
10237         ibx_assert_pch_refclk_enabled(dev_priv);
10238
10239         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10240
10241         /* Wait for the clocks to stabilize. */
10242         POSTING_READ(PCH_DPLL(pll->id));
10243         udelay(150);
10244
10245         /* The pixel multiplier can only be updated once the
10246          * DPLL is enabled and the clocks are stable.
10247          *
10248          * So write it again.
10249          */
10250         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10251         POSTING_READ(PCH_DPLL(pll->id));
10252         udelay(200);
10253 }
10254
10255 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10256                                  struct intel_shared_dpll *pll)
10257 {
10258         struct drm_device *dev = dev_priv->dev;
10259         struct intel_crtc *crtc;
10260
10261         /* Make sure no transcoder isn't still depending on us. */
10262         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10263                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10264                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10265         }
10266
10267         I915_WRITE(PCH_DPLL(pll->id), 0);
10268         POSTING_READ(PCH_DPLL(pll->id));
10269         udelay(200);
10270 }
10271
10272 static char *ibx_pch_dpll_names[] = {
10273         "PCH DPLL A",
10274         "PCH DPLL B",
10275 };
10276
10277 static void ibx_pch_dpll_init(struct drm_device *dev)
10278 {
10279         struct drm_i915_private *dev_priv = dev->dev_private;
10280         int i;
10281
10282         dev_priv->num_shared_dpll = 2;
10283
10284         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10285                 dev_priv->shared_dplls[i].id = i;
10286                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10287                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10288                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10289                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10290                 dev_priv->shared_dplls[i].get_hw_state =
10291                         ibx_pch_dpll_get_hw_state;
10292         }
10293 }
10294
10295 static void intel_shared_dpll_init(struct drm_device *dev)
10296 {
10297         struct drm_i915_private *dev_priv = dev->dev_private;
10298
10299         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10300                 ibx_pch_dpll_init(dev);
10301         else
10302                 dev_priv->num_shared_dpll = 0;
10303
10304         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10305 }
10306
10307 static void intel_crtc_init(struct drm_device *dev, int pipe)
10308 {
10309         drm_i915_private_t *dev_priv = dev->dev_private;
10310         struct intel_crtc *intel_crtc;
10311         int i;
10312
10313         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10314         if (intel_crtc == NULL)
10315                 return;
10316
10317         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10318
10319         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10320         for (i = 0; i < 256; i++) {
10321                 intel_crtc->lut_r[i] = i;
10322                 intel_crtc->lut_g[i] = i;
10323                 intel_crtc->lut_b[i] = i;
10324         }
10325
10326         /*
10327          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10328          * is hooked to plane B. Hence we want plane A feeding pipe B.
10329          */
10330         intel_crtc->pipe = pipe;
10331         intel_crtc->plane = pipe;
10332         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10333                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10334                 intel_crtc->plane = !pipe;
10335         }
10336
10337         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10338                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10339         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10340         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10341
10342         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10343 }
10344
10345 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10346 {
10347         struct drm_encoder *encoder = connector->base.encoder;
10348
10349         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10350
10351         if (!encoder)
10352                 return INVALID_PIPE;
10353
10354         return to_intel_crtc(encoder->crtc)->pipe;
10355 }
10356
10357 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10358                                 struct drm_file *file)
10359 {
10360         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10361         struct drm_mode_object *drmmode_obj;
10362         struct intel_crtc *crtc;
10363
10364         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10365                 return -ENODEV;
10366
10367         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10368                         DRM_MODE_OBJECT_CRTC);
10369
10370         if (!drmmode_obj) {
10371                 DRM_ERROR("no such CRTC id\n");
10372                 return -ENOENT;
10373         }
10374
10375         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10376         pipe_from_crtc_id->pipe = crtc->pipe;
10377
10378         return 0;
10379 }
10380
10381 static int intel_encoder_clones(struct intel_encoder *encoder)
10382 {
10383         struct drm_device *dev = encoder->base.dev;
10384         struct intel_encoder *source_encoder;
10385         int index_mask = 0;
10386         int entry = 0;
10387
10388         list_for_each_entry(source_encoder,
10389                             &dev->mode_config.encoder_list, base.head) {
10390
10391                 if (encoder == source_encoder)
10392                         index_mask |= (1 << entry);
10393
10394                 /* Intel hw has only one MUX where enocoders could be cloned. */
10395                 if (encoder->cloneable && source_encoder->cloneable)
10396                         index_mask |= (1 << entry);
10397
10398                 entry++;
10399         }
10400
10401         return index_mask;
10402 }
10403
10404 static bool has_edp_a(struct drm_device *dev)
10405 {
10406         struct drm_i915_private *dev_priv = dev->dev_private;
10407
10408         if (!IS_MOBILE(dev))
10409                 return false;
10410
10411         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10412                 return false;
10413
10414         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10415                 return false;
10416
10417         return true;
10418 }
10419
10420 const char *intel_output_name(int output)
10421 {
10422         static const char *names[] = {
10423                 [INTEL_OUTPUT_UNUSED] = "Unused",
10424                 [INTEL_OUTPUT_ANALOG] = "Analog",
10425                 [INTEL_OUTPUT_DVO] = "DVO",
10426                 [INTEL_OUTPUT_SDVO] = "SDVO",
10427                 [INTEL_OUTPUT_LVDS] = "LVDS",
10428                 [INTEL_OUTPUT_TVOUT] = "TV",
10429                 [INTEL_OUTPUT_HDMI] = "HDMI",
10430                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10431                 [INTEL_OUTPUT_EDP] = "eDP",
10432                 [INTEL_OUTPUT_DSI] = "DSI",
10433                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10434         };
10435
10436         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10437                 return "Invalid";
10438
10439         return names[output];
10440 }
10441
10442 static void intel_setup_outputs(struct drm_device *dev)
10443 {
10444         struct drm_i915_private *dev_priv = dev->dev_private;
10445         struct intel_encoder *encoder;
10446         bool dpd_is_edp = false;
10447
10448         intel_lvds_init(dev);
10449
10450         if (!IS_ULT(dev))
10451                 intel_crt_init(dev);
10452
10453         if (HAS_DDI(dev)) {
10454                 int found;
10455
10456                 /* Haswell uses DDI functions to detect digital outputs */
10457                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10458                 /* DDI A only supports eDP */
10459                 if (found)
10460                         intel_ddi_init(dev, PORT_A);
10461
10462                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10463                  * register */
10464                 found = I915_READ(SFUSE_STRAP);
10465
10466                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10467                         intel_ddi_init(dev, PORT_B);
10468                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10469                         intel_ddi_init(dev, PORT_C);
10470                 if (found & SFUSE_STRAP_DDID_DETECTED)
10471                         intel_ddi_init(dev, PORT_D);
10472         } else if (HAS_PCH_SPLIT(dev)) {
10473                 int found;
10474                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10475
10476                 if (has_edp_a(dev))
10477                         intel_dp_init(dev, DP_A, PORT_A);
10478
10479                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10480                         /* PCH SDVOB multiplex with HDMIB */
10481                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10482                         if (!found)
10483                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10484                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10485                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10486                 }
10487
10488                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10489                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10490
10491                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10492                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10493
10494                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10495                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10496
10497                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10498                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10499         } else if (IS_VALLEYVIEW(dev)) {
10500                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10501                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10502                                         PORT_B);
10503                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10504                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10505                 }
10506
10507                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10508                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10509                                         PORT_C);
10510                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10511                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10512                 }
10513
10514                 intel_dsi_init(dev);
10515         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10516                 bool found = false;
10517
10518                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10519                         DRM_DEBUG_KMS("probing SDVOB\n");
10520                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10521                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10522                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10523                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10524                         }
10525
10526                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10527                                 intel_dp_init(dev, DP_B, PORT_B);
10528                 }
10529
10530                 /* Before G4X SDVOC doesn't have its own detect register */
10531
10532                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10533                         DRM_DEBUG_KMS("probing SDVOC\n");
10534                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10535                 }
10536
10537                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10538
10539                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10540                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10541                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10542                         }
10543                         if (SUPPORTS_INTEGRATED_DP(dev))
10544                                 intel_dp_init(dev, DP_C, PORT_C);
10545                 }
10546
10547                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10548                     (I915_READ(DP_D) & DP_DETECTED))
10549                         intel_dp_init(dev, DP_D, PORT_D);
10550         } else if (IS_GEN2(dev))
10551                 intel_dvo_init(dev);
10552
10553         if (SUPPORTS_TV(dev))
10554                 intel_tv_init(dev);
10555
10556         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10557                 encoder->base.possible_crtcs = encoder->crtc_mask;
10558                 encoder->base.possible_clones =
10559                         intel_encoder_clones(encoder);
10560         }
10561
10562         intel_init_pch_refclk(dev);
10563
10564         drm_helper_move_panel_connectors_to_head(dev);
10565 }
10566
10567 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10568 {
10569         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10570
10571         drm_framebuffer_cleanup(fb);
10572         WARN_ON(!intel_fb->obj->framebuffer_references--);
10573         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10574         kfree(intel_fb);
10575 }
10576
10577 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10578                                                 struct drm_file *file,
10579                                                 unsigned int *handle)
10580 {
10581         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10582         struct drm_i915_gem_object *obj = intel_fb->obj;
10583
10584         return drm_gem_handle_create(file, &obj->base, handle);
10585 }
10586
10587 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10588         .destroy = intel_user_framebuffer_destroy,
10589         .create_handle = intel_user_framebuffer_create_handle,
10590 };
10591
10592 static int intel_framebuffer_init(struct drm_device *dev,
10593                                   struct intel_framebuffer *intel_fb,
10594                                   struct drm_mode_fb_cmd2 *mode_cmd,
10595                                   struct drm_i915_gem_object *obj)
10596 {
10597         int aligned_height;
10598         int pitch_limit;
10599         int ret;
10600
10601         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10602
10603         if (obj->tiling_mode == I915_TILING_Y) {
10604                 DRM_DEBUG("hardware does not support tiling Y\n");
10605                 return -EINVAL;
10606         }
10607
10608         if (mode_cmd->pitches[0] & 63) {
10609                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10610                           mode_cmd->pitches[0]);
10611                 return -EINVAL;
10612         }
10613
10614         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10615                 pitch_limit = 32*1024;
10616         } else if (INTEL_INFO(dev)->gen >= 4) {
10617                 if (obj->tiling_mode)
10618                         pitch_limit = 16*1024;
10619                 else
10620                         pitch_limit = 32*1024;
10621         } else if (INTEL_INFO(dev)->gen >= 3) {
10622                 if (obj->tiling_mode)
10623                         pitch_limit = 8*1024;
10624                 else
10625                         pitch_limit = 16*1024;
10626         } else
10627                 /* XXX DSPC is limited to 4k tiled */
10628                 pitch_limit = 8*1024;
10629
10630         if (mode_cmd->pitches[0] > pitch_limit) {
10631                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10632                           obj->tiling_mode ? "tiled" : "linear",
10633                           mode_cmd->pitches[0], pitch_limit);
10634                 return -EINVAL;
10635         }
10636
10637         if (obj->tiling_mode != I915_TILING_NONE &&
10638             mode_cmd->pitches[0] != obj->stride) {
10639                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10640                           mode_cmd->pitches[0], obj->stride);
10641                 return -EINVAL;
10642         }
10643
10644         /* Reject formats not supported by any plane early. */
10645         switch (mode_cmd->pixel_format) {
10646         case DRM_FORMAT_C8:
10647         case DRM_FORMAT_RGB565:
10648         case DRM_FORMAT_XRGB8888:
10649         case DRM_FORMAT_ARGB8888:
10650                 break;
10651         case DRM_FORMAT_XRGB1555:
10652         case DRM_FORMAT_ARGB1555:
10653                 if (INTEL_INFO(dev)->gen > 3) {
10654                         DRM_DEBUG("unsupported pixel format: %s\n",
10655                                   drm_get_format_name(mode_cmd->pixel_format));
10656                         return -EINVAL;
10657                 }
10658                 break;
10659         case DRM_FORMAT_XBGR8888:
10660         case DRM_FORMAT_ABGR8888:
10661         case DRM_FORMAT_XRGB2101010:
10662         case DRM_FORMAT_ARGB2101010:
10663         case DRM_FORMAT_XBGR2101010:
10664         case DRM_FORMAT_ABGR2101010:
10665                 if (INTEL_INFO(dev)->gen < 4) {
10666                         DRM_DEBUG("unsupported pixel format: %s\n",
10667                                   drm_get_format_name(mode_cmd->pixel_format));
10668                         return -EINVAL;
10669                 }
10670                 break;
10671         case DRM_FORMAT_YUYV:
10672         case DRM_FORMAT_UYVY:
10673         case DRM_FORMAT_YVYU:
10674         case DRM_FORMAT_VYUY:
10675                 if (INTEL_INFO(dev)->gen < 5) {
10676                         DRM_DEBUG("unsupported pixel format: %s\n",
10677                                   drm_get_format_name(mode_cmd->pixel_format));
10678                         return -EINVAL;
10679                 }
10680                 break;
10681         default:
10682                 DRM_DEBUG("unsupported pixel format: %s\n",
10683                           drm_get_format_name(mode_cmd->pixel_format));
10684                 return -EINVAL;
10685         }
10686
10687         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10688         if (mode_cmd->offsets[0] != 0)
10689                 return -EINVAL;
10690
10691         aligned_height = intel_align_height(dev, mode_cmd->height,
10692                                             obj->tiling_mode);
10693         /* FIXME drm helper for size checks (especially planar formats)? */
10694         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10695                 return -EINVAL;
10696
10697         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10698         intel_fb->obj = obj;
10699         intel_fb->obj->framebuffer_references++;
10700
10701         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10702         if (ret) {
10703                 DRM_ERROR("framebuffer init failed %d\n", ret);
10704                 return ret;
10705         }
10706
10707         return 0;
10708 }
10709
10710 static struct drm_framebuffer *
10711 intel_user_framebuffer_create(struct drm_device *dev,
10712                               struct drm_file *filp,
10713                               struct drm_mode_fb_cmd2 *mode_cmd)
10714 {
10715         struct drm_i915_gem_object *obj;
10716
10717         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10718                                                 mode_cmd->handles[0]));
10719         if (&obj->base == NULL)
10720                 return ERR_PTR(-ENOENT);
10721
10722         return intel_framebuffer_create(dev, mode_cmd, obj);
10723 }
10724
10725 #ifndef CONFIG_DRM_I915_FBDEV
10726 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10727 {
10728 }
10729 #endif
10730
10731 static const struct drm_mode_config_funcs intel_mode_funcs = {
10732         .fb_create = intel_user_framebuffer_create,
10733         .output_poll_changed = intel_fbdev_output_poll_changed,
10734 };
10735
10736 /* Set up chip specific display functions */
10737 static void intel_init_display(struct drm_device *dev)
10738 {
10739         struct drm_i915_private *dev_priv = dev->dev_private;
10740
10741         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10742                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10743         else if (IS_VALLEYVIEW(dev))
10744                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10745         else if (IS_PINEVIEW(dev))
10746                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10747         else
10748                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10749
10750         if (HAS_DDI(dev)) {
10751                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10752                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10753                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10754                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10755                 dev_priv->display.off = haswell_crtc_off;
10756                 dev_priv->display.update_plane = ironlake_update_plane;
10757         } else if (HAS_PCH_SPLIT(dev)) {
10758                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10759                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10760                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10761                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10762                 dev_priv->display.off = ironlake_crtc_off;
10763                 dev_priv->display.update_plane = ironlake_update_plane;
10764         } else if (IS_VALLEYVIEW(dev)) {
10765                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10766                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10767                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10768                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10769                 dev_priv->display.off = i9xx_crtc_off;
10770                 dev_priv->display.update_plane = i9xx_update_plane;
10771         } else {
10772                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10773                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10774                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10775                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10776                 dev_priv->display.off = i9xx_crtc_off;
10777                 dev_priv->display.update_plane = i9xx_update_plane;
10778         }
10779
10780         /* Returns the core display clock speed */
10781         if (IS_VALLEYVIEW(dev))
10782                 dev_priv->display.get_display_clock_speed =
10783                         valleyview_get_display_clock_speed;
10784         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10785                 dev_priv->display.get_display_clock_speed =
10786                         i945_get_display_clock_speed;
10787         else if (IS_I915G(dev))
10788                 dev_priv->display.get_display_clock_speed =
10789                         i915_get_display_clock_speed;
10790         else if (IS_I945GM(dev) || IS_845G(dev))
10791                 dev_priv->display.get_display_clock_speed =
10792                         i9xx_misc_get_display_clock_speed;
10793         else if (IS_PINEVIEW(dev))
10794                 dev_priv->display.get_display_clock_speed =
10795                         pnv_get_display_clock_speed;
10796         else if (IS_I915GM(dev))
10797                 dev_priv->display.get_display_clock_speed =
10798                         i915gm_get_display_clock_speed;
10799         else if (IS_I865G(dev))
10800                 dev_priv->display.get_display_clock_speed =
10801                         i865_get_display_clock_speed;
10802         else if (IS_I85X(dev))
10803                 dev_priv->display.get_display_clock_speed =
10804                         i855_get_display_clock_speed;
10805         else /* 852, 830 */
10806                 dev_priv->display.get_display_clock_speed =
10807                         i830_get_display_clock_speed;
10808
10809         if (HAS_PCH_SPLIT(dev)) {
10810                 if (IS_GEN5(dev)) {
10811                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10812                         dev_priv->display.write_eld = ironlake_write_eld;
10813                 } else if (IS_GEN6(dev)) {
10814                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10815                         dev_priv->display.write_eld = ironlake_write_eld;
10816                 } else if (IS_IVYBRIDGE(dev)) {
10817                         /* FIXME: detect B0+ stepping and use auto training */
10818                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10819                         dev_priv->display.write_eld = ironlake_write_eld;
10820                         dev_priv->display.modeset_global_resources =
10821                                 ivb_modeset_global_resources;
10822                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10823                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10824                         dev_priv->display.write_eld = haswell_write_eld;
10825                         dev_priv->display.modeset_global_resources =
10826                                 haswell_modeset_global_resources;
10827                 }
10828         } else if (IS_G4X(dev)) {
10829                 dev_priv->display.write_eld = g4x_write_eld;
10830         } else if (IS_VALLEYVIEW(dev)) {
10831                 dev_priv->display.modeset_global_resources =
10832                         valleyview_modeset_global_resources;
10833                 dev_priv->display.write_eld = ironlake_write_eld;
10834         }
10835
10836         /* Default just returns -ENODEV to indicate unsupported */
10837         dev_priv->display.queue_flip = intel_default_queue_flip;
10838
10839         switch (INTEL_INFO(dev)->gen) {
10840         case 2:
10841                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10842                 break;
10843
10844         case 3:
10845                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10846                 break;
10847
10848         case 4:
10849         case 5:
10850                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10851                 break;
10852
10853         case 6:
10854                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10855                 break;
10856         case 7:
10857         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10858                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10859                 break;
10860         }
10861
10862         intel_panel_init_backlight_funcs(dev);
10863 }
10864
10865 /*
10866  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10867  * resume, or other times.  This quirk makes sure that's the case for
10868  * affected systems.
10869  */
10870 static void quirk_pipea_force(struct drm_device *dev)
10871 {
10872         struct drm_i915_private *dev_priv = dev->dev_private;
10873
10874         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10875         DRM_INFO("applying pipe a force quirk\n");
10876 }
10877
10878 /*
10879  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10880  */
10881 static void quirk_ssc_force_disable(struct drm_device *dev)
10882 {
10883         struct drm_i915_private *dev_priv = dev->dev_private;
10884         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10885         DRM_INFO("applying lvds SSC disable quirk\n");
10886 }
10887
10888 /*
10889  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10890  * brightness value
10891  */
10892 static void quirk_invert_brightness(struct drm_device *dev)
10893 {
10894         struct drm_i915_private *dev_priv = dev->dev_private;
10895         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10896         DRM_INFO("applying inverted panel brightness quirk\n");
10897 }
10898
10899 struct intel_quirk {
10900         int device;
10901         int subsystem_vendor;
10902         int subsystem_device;
10903         void (*hook)(struct drm_device *dev);
10904 };
10905
10906 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10907 struct intel_dmi_quirk {
10908         void (*hook)(struct drm_device *dev);
10909         const struct dmi_system_id (*dmi_id_list)[];
10910 };
10911
10912 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10913 {
10914         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10915         return 1;
10916 }
10917
10918 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10919         {
10920                 .dmi_id_list = &(const struct dmi_system_id[]) {
10921                         {
10922                                 .callback = intel_dmi_reverse_brightness,
10923                                 .ident = "NCR Corporation",
10924                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10925                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10926                                 },
10927                         },
10928                         { }  /* terminating entry */
10929                 },
10930                 .hook = quirk_invert_brightness,
10931         },
10932 };
10933
10934 static struct intel_quirk intel_quirks[] = {
10935         /* HP Mini needs pipe A force quirk (LP: #322104) */
10936         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10937
10938         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10939         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10940
10941         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10942         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10943
10944         /* 830 needs to leave pipe A & dpll A up */
10945         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10946
10947         /* Lenovo U160 cannot use SSC on LVDS */
10948         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10949
10950         /* Sony Vaio Y cannot use SSC on LVDS */
10951         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10952
10953         /* Acer Aspire 5734Z must invert backlight brightness */
10954         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10955
10956         /* Acer/eMachines G725 */
10957         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10958
10959         /* Acer/eMachines e725 */
10960         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10961
10962         /* Acer/Packard Bell NCL20 */
10963         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10964
10965         /* Acer Aspire 4736Z */
10966         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10967
10968         /* Acer Aspire 5336 */
10969         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
10970 };
10971
10972 static void intel_init_quirks(struct drm_device *dev)
10973 {
10974         struct pci_dev *d = dev->pdev;
10975         int i;
10976
10977         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10978                 struct intel_quirk *q = &intel_quirks[i];
10979
10980                 if (d->device == q->device &&
10981                     (d->subsystem_vendor == q->subsystem_vendor ||
10982                      q->subsystem_vendor == PCI_ANY_ID) &&
10983                     (d->subsystem_device == q->subsystem_device ||
10984                      q->subsystem_device == PCI_ANY_ID))
10985                         q->hook(dev);
10986         }
10987         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10988                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10989                         intel_dmi_quirks[i].hook(dev);
10990         }
10991 }
10992
10993 /* Disable the VGA plane that we never use */
10994 static void i915_disable_vga(struct drm_device *dev)
10995 {
10996         struct drm_i915_private *dev_priv = dev->dev_private;
10997         u8 sr1;
10998         u32 vga_reg = i915_vgacntrl_reg(dev);
10999
11000         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11001         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11002         outb(SR01, VGA_SR_INDEX);
11003         sr1 = inb(VGA_SR_DATA);
11004         outb(sr1 | 1<<5, VGA_SR_DATA);
11005         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11006         udelay(300);
11007
11008         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11009         POSTING_READ(vga_reg);
11010 }
11011
11012 void intel_modeset_init_hw(struct drm_device *dev)
11013 {
11014         intel_prepare_ddi(dev);
11015
11016         intel_init_clock_gating(dev);
11017
11018         intel_reset_dpio(dev);
11019
11020         mutex_lock(&dev->struct_mutex);
11021         intel_enable_gt_powersave(dev);
11022         mutex_unlock(&dev->struct_mutex);
11023 }
11024
11025 void intel_modeset_suspend_hw(struct drm_device *dev)
11026 {
11027         intel_suspend_hw(dev);
11028 }
11029
11030 void intel_modeset_init(struct drm_device *dev)
11031 {
11032         struct drm_i915_private *dev_priv = dev->dev_private;
11033         int sprite, ret;
11034         enum pipe pipe;
11035
11036         drm_mode_config_init(dev);
11037
11038         dev->mode_config.min_width = 0;
11039         dev->mode_config.min_height = 0;
11040
11041         dev->mode_config.preferred_depth = 24;
11042         dev->mode_config.prefer_shadow = 1;
11043
11044         dev->mode_config.funcs = &intel_mode_funcs;
11045
11046         intel_init_quirks(dev);
11047
11048         intel_init_pm(dev);
11049
11050         if (INTEL_INFO(dev)->num_pipes == 0)
11051                 return;
11052
11053         intel_init_display(dev);
11054
11055         if (IS_GEN2(dev)) {
11056                 dev->mode_config.max_width = 2048;
11057                 dev->mode_config.max_height = 2048;
11058         } else if (IS_GEN3(dev)) {
11059                 dev->mode_config.max_width = 4096;
11060                 dev->mode_config.max_height = 4096;
11061         } else {
11062                 dev->mode_config.max_width = 8192;
11063                 dev->mode_config.max_height = 8192;
11064         }
11065         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11066
11067         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11068                       INTEL_INFO(dev)->num_pipes,
11069                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11070
11071         for_each_pipe(pipe) {
11072                 intel_crtc_init(dev, pipe);
11073                 for_each_sprite(pipe, sprite) {
11074                         ret = intel_plane_init(dev, pipe, sprite);
11075                         if (ret)
11076                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11077                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11078                 }
11079         }
11080
11081         intel_init_dpio(dev);
11082         intel_reset_dpio(dev);
11083
11084         intel_cpu_pll_init(dev);
11085         intel_shared_dpll_init(dev);
11086
11087         /* Just disable it once at startup */
11088         i915_disable_vga(dev);
11089         intel_setup_outputs(dev);
11090
11091         /* Just in case the BIOS is doing something questionable. */
11092         intel_disable_fbc(dev);
11093
11094         mutex_lock(&dev->mode_config.mutex);
11095         intel_modeset_setup_hw_state(dev, false);
11096         mutex_unlock(&dev->mode_config.mutex);
11097 }
11098
11099 static void
11100 intel_connector_break_all_links(struct intel_connector *connector)
11101 {
11102         connector->base.dpms = DRM_MODE_DPMS_OFF;
11103         connector->base.encoder = NULL;
11104         connector->encoder->connectors_active = false;
11105         connector->encoder->base.crtc = NULL;
11106 }
11107
11108 static void intel_enable_pipe_a(struct drm_device *dev)
11109 {
11110         struct intel_connector *connector;
11111         struct drm_connector *crt = NULL;
11112         struct intel_load_detect_pipe load_detect_temp;
11113
11114         /* We can't just switch on the pipe A, we need to set things up with a
11115          * proper mode and output configuration. As a gross hack, enable pipe A
11116          * by enabling the load detect pipe once. */
11117         list_for_each_entry(connector,
11118                             &dev->mode_config.connector_list,
11119                             base.head) {
11120                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11121                         crt = &connector->base;
11122                         break;
11123                 }
11124         }
11125
11126         if (!crt)
11127                 return;
11128
11129         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11130                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11131
11132
11133 }
11134
11135 static bool
11136 intel_check_plane_mapping(struct intel_crtc *crtc)
11137 {
11138         struct drm_device *dev = crtc->base.dev;
11139         struct drm_i915_private *dev_priv = dev->dev_private;
11140         u32 reg, val;
11141
11142         if (INTEL_INFO(dev)->num_pipes == 1)
11143                 return true;
11144
11145         reg = DSPCNTR(!crtc->plane);
11146         val = I915_READ(reg);
11147
11148         if ((val & DISPLAY_PLANE_ENABLE) &&
11149             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11150                 return false;
11151
11152         return true;
11153 }
11154
11155 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11156 {
11157         struct drm_device *dev = crtc->base.dev;
11158         struct drm_i915_private *dev_priv = dev->dev_private;
11159         u32 reg;
11160
11161         /* Clear any frame start delays used for debugging left by the BIOS */
11162         reg = PIPECONF(crtc->config.cpu_transcoder);
11163         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11164
11165         /* We need to sanitize the plane -> pipe mapping first because this will
11166          * disable the crtc (and hence change the state) if it is wrong. Note
11167          * that gen4+ has a fixed plane -> pipe mapping.  */
11168         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11169                 struct intel_connector *connector;
11170                 bool plane;
11171
11172                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11173                               crtc->base.base.id);
11174
11175                 /* Pipe has the wrong plane attached and the plane is active.
11176                  * Temporarily change the plane mapping and disable everything
11177                  * ...  */
11178                 plane = crtc->plane;
11179                 crtc->plane = !plane;
11180                 dev_priv->display.crtc_disable(&crtc->base);
11181                 crtc->plane = plane;
11182
11183                 /* ... and break all links. */
11184                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11185                                     base.head) {
11186                         if (connector->encoder->base.crtc != &crtc->base)
11187                                 continue;
11188
11189                         intel_connector_break_all_links(connector);
11190                 }
11191
11192                 WARN_ON(crtc->active);
11193                 crtc->base.enabled = false;
11194         }
11195
11196         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11197             crtc->pipe == PIPE_A && !crtc->active) {
11198                 /* BIOS forgot to enable pipe A, this mostly happens after
11199                  * resume. Force-enable the pipe to fix this, the update_dpms
11200                  * call below we restore the pipe to the right state, but leave
11201                  * the required bits on. */
11202                 intel_enable_pipe_a(dev);
11203         }
11204
11205         /* Adjust the state of the output pipe according to whether we
11206          * have active connectors/encoders. */
11207         intel_crtc_update_dpms(&crtc->base);
11208
11209         if (crtc->active != crtc->base.enabled) {
11210                 struct intel_encoder *encoder;
11211
11212                 /* This can happen either due to bugs in the get_hw_state
11213                  * functions or because the pipe is force-enabled due to the
11214                  * pipe A quirk. */
11215                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11216                               crtc->base.base.id,
11217                               crtc->base.enabled ? "enabled" : "disabled",
11218                               crtc->active ? "enabled" : "disabled");
11219
11220                 crtc->base.enabled = crtc->active;
11221
11222                 /* Because we only establish the connector -> encoder ->
11223                  * crtc links if something is active, this means the
11224                  * crtc is now deactivated. Break the links. connector
11225                  * -> encoder links are only establish when things are
11226                  *  actually up, hence no need to break them. */
11227                 WARN_ON(crtc->active);
11228
11229                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11230                         WARN_ON(encoder->connectors_active);
11231                         encoder->base.crtc = NULL;
11232                 }
11233         }
11234 }
11235
11236 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11237 {
11238         struct intel_connector *connector;
11239         struct drm_device *dev = encoder->base.dev;
11240
11241         /* We need to check both for a crtc link (meaning that the
11242          * encoder is active and trying to read from a pipe) and the
11243          * pipe itself being active. */
11244         bool has_active_crtc = encoder->base.crtc &&
11245                 to_intel_crtc(encoder->base.crtc)->active;
11246
11247         if (encoder->connectors_active && !has_active_crtc) {
11248                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11249                               encoder->base.base.id,
11250                               drm_get_encoder_name(&encoder->base));
11251
11252                 /* Connector is active, but has no active pipe. This is
11253                  * fallout from our resume register restoring. Disable
11254                  * the encoder manually again. */
11255                 if (encoder->base.crtc) {
11256                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11257                                       encoder->base.base.id,
11258                                       drm_get_encoder_name(&encoder->base));
11259                         encoder->disable(encoder);
11260                 }
11261
11262                 /* Inconsistent output/port/pipe state happens presumably due to
11263                  * a bug in one of the get_hw_state functions. Or someplace else
11264                  * in our code, like the register restore mess on resume. Clamp
11265                  * things to off as a safer default. */
11266                 list_for_each_entry(connector,
11267                                     &dev->mode_config.connector_list,
11268                                     base.head) {
11269                         if (connector->encoder != encoder)
11270                                 continue;
11271
11272                         intel_connector_break_all_links(connector);
11273                 }
11274         }
11275         /* Enabled encoders without active connectors will be fixed in
11276          * the crtc fixup. */
11277 }
11278
11279 void i915_redisable_vga_power_on(struct drm_device *dev)
11280 {
11281         struct drm_i915_private *dev_priv = dev->dev_private;
11282         u32 vga_reg = i915_vgacntrl_reg(dev);
11283
11284         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11285                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11286                 i915_disable_vga(dev);
11287         }
11288 }
11289
11290 void i915_redisable_vga(struct drm_device *dev)
11291 {
11292         struct drm_i915_private *dev_priv = dev->dev_private;
11293
11294         /* This function can be called both from intel_modeset_setup_hw_state or
11295          * at a very early point in our resume sequence, where the power well
11296          * structures are not yet restored. Since this function is at a very
11297          * paranoid "someone might have enabled VGA while we were not looking"
11298          * level, just check if the power well is enabled instead of trying to
11299          * follow the "don't touch the power well if we don't need it" policy
11300          * the rest of the driver uses. */
11301         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11302                 return;
11303
11304         i915_redisable_vga_power_on(dev);
11305 }
11306
11307 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11308 {
11309         struct drm_i915_private *dev_priv = dev->dev_private;
11310         enum pipe pipe;
11311         struct intel_crtc *crtc;
11312         struct intel_encoder *encoder;
11313         struct intel_connector *connector;
11314         int i;
11315
11316         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11317                             base.head) {
11318                 memset(&crtc->config, 0, sizeof(crtc->config));
11319
11320                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11321                                                                  &crtc->config);
11322
11323                 crtc->base.enabled = crtc->active;
11324                 crtc->primary_enabled = crtc->active;
11325
11326                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11327                               crtc->base.base.id,
11328                               crtc->active ? "enabled" : "disabled");
11329         }
11330
11331         /* FIXME: Smash this into the new shared dpll infrastructure. */
11332         if (HAS_DDI(dev))
11333                 intel_ddi_setup_hw_pll_state(dev);
11334
11335         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11336                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11337
11338                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11339                 pll->active = 0;
11340                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11341                                     base.head) {
11342                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11343                                 pll->active++;
11344                 }
11345                 pll->refcount = pll->active;
11346
11347                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11348                               pll->name, pll->refcount, pll->on);
11349         }
11350
11351         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11352                             base.head) {
11353                 pipe = 0;
11354
11355                 if (encoder->get_hw_state(encoder, &pipe)) {
11356                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11357                         encoder->base.crtc = &crtc->base;
11358                         encoder->get_config(encoder, &crtc->config);
11359                 } else {
11360                         encoder->base.crtc = NULL;
11361                 }
11362
11363                 encoder->connectors_active = false;
11364                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11365                               encoder->base.base.id,
11366                               drm_get_encoder_name(&encoder->base),
11367                               encoder->base.crtc ? "enabled" : "disabled",
11368                               pipe_name(pipe));
11369         }
11370
11371         list_for_each_entry(connector, &dev->mode_config.connector_list,
11372                             base.head) {
11373                 if (connector->get_hw_state(connector)) {
11374                         connector->base.dpms = DRM_MODE_DPMS_ON;
11375                         connector->encoder->connectors_active = true;
11376                         connector->base.encoder = &connector->encoder->base;
11377                 } else {
11378                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11379                         connector->base.encoder = NULL;
11380                 }
11381                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11382                               connector->base.base.id,
11383                               drm_get_connector_name(&connector->base),
11384                               connector->base.encoder ? "enabled" : "disabled");
11385         }
11386 }
11387
11388 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11389  * and i915 state tracking structures. */
11390 void intel_modeset_setup_hw_state(struct drm_device *dev,
11391                                   bool force_restore)
11392 {
11393         struct drm_i915_private *dev_priv = dev->dev_private;
11394         enum pipe pipe;
11395         struct intel_crtc *crtc;
11396         struct intel_encoder *encoder;
11397         int i;
11398
11399         intel_modeset_readout_hw_state(dev);
11400
11401         /*
11402          * Now that we have the config, copy it to each CRTC struct
11403          * Note that this could go away if we move to using crtc_config
11404          * checking everywhere.
11405          */
11406         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11407                             base.head) {
11408                 if (crtc->active && i915.fastboot) {
11409                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11410                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11411                                       crtc->base.base.id);
11412                         drm_mode_debug_printmodeline(&crtc->base.mode);
11413                 }
11414         }
11415
11416         /* HW state is read out, now we need to sanitize this mess. */
11417         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11418                             base.head) {
11419                 intel_sanitize_encoder(encoder);
11420         }
11421
11422         for_each_pipe(pipe) {
11423                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11424                 intel_sanitize_crtc(crtc);
11425                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11426         }
11427
11428         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11429                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11430
11431                 if (!pll->on || pll->active)
11432                         continue;
11433
11434                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11435
11436                 pll->disable(dev_priv, pll);
11437                 pll->on = false;
11438         }
11439
11440         if (HAS_PCH_SPLIT(dev))
11441                 ilk_wm_get_hw_state(dev);
11442
11443         if (force_restore) {
11444                 i915_redisable_vga(dev);
11445
11446                 /*
11447                  * We need to use raw interfaces for restoring state to avoid
11448                  * checking (bogus) intermediate states.
11449                  */
11450                 for_each_pipe(pipe) {
11451                         struct drm_crtc *crtc =
11452                                 dev_priv->pipe_to_crtc_mapping[pipe];
11453
11454                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11455                                          crtc->fb);
11456                 }
11457         } else {
11458                 intel_modeset_update_staged_output_state(dev);
11459         }
11460
11461         intel_modeset_check_state(dev);
11462 }
11463
11464 void intel_modeset_gem_init(struct drm_device *dev)
11465 {
11466         intel_modeset_init_hw(dev);
11467
11468         intel_setup_overlay(dev);
11469 }
11470
11471 void intel_connector_unregister(struct intel_connector *intel_connector)
11472 {
11473         struct drm_connector *connector = &intel_connector->base;
11474
11475         intel_panel_destroy_backlight(connector);
11476         drm_sysfs_connector_remove(connector);
11477 }
11478
11479 void intel_modeset_cleanup(struct drm_device *dev)
11480 {
11481         struct drm_i915_private *dev_priv = dev->dev_private;
11482         struct drm_crtc *crtc;
11483         struct drm_connector *connector;
11484
11485         /*
11486          * Interrupts and polling as the first thing to avoid creating havoc.
11487          * Too much stuff here (turning of rps, connectors, ...) would
11488          * experience fancy races otherwise.
11489          */
11490         drm_irq_uninstall(dev);
11491         cancel_work_sync(&dev_priv->hotplug_work);
11492         /*
11493          * Due to the hpd irq storm handling the hotplug work can re-arm the
11494          * poll handlers. Hence disable polling after hpd handling is shut down.
11495          */
11496         drm_kms_helper_poll_fini(dev);
11497
11498         mutex_lock(&dev->struct_mutex);
11499
11500         intel_unregister_dsm_handler();
11501
11502         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11503                 /* Skip inactive CRTCs */
11504                 if (!crtc->fb)
11505                         continue;
11506
11507                 intel_increase_pllclock(crtc);
11508         }
11509
11510         intel_disable_fbc(dev);
11511
11512         intel_disable_gt_powersave(dev);
11513
11514         ironlake_teardown_rc6(dev);
11515
11516         mutex_unlock(&dev->struct_mutex);
11517
11518         /* flush any delayed tasks or pending work */
11519         flush_scheduled_work();
11520
11521         /* destroy the backlight and sysfs files before encoders/connectors */
11522         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11523                 struct intel_connector *intel_connector;
11524
11525                 intel_connector = to_intel_connector(connector);
11526                 intel_connector->unregister(intel_connector);
11527         }
11528
11529         drm_mode_config_cleanup(dev);
11530
11531         intel_cleanup_overlay(dev);
11532 }
11533
11534 /*
11535  * Return which encoder is currently attached for connector.
11536  */
11537 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11538 {
11539         return &intel_attached_encoder(connector)->base;
11540 }
11541
11542 void intel_connector_attach_encoder(struct intel_connector *connector,
11543                                     struct intel_encoder *encoder)
11544 {
11545         connector->encoder = encoder;
11546         drm_mode_connector_attach_encoder(&connector->base,
11547                                           &encoder->base);
11548 }
11549
11550 /*
11551  * set vga decode state - true == enable VGA decode
11552  */
11553 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11554 {
11555         struct drm_i915_private *dev_priv = dev->dev_private;
11556         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11557         u16 gmch_ctrl;
11558
11559         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11560                 DRM_ERROR("failed to read control word\n");
11561                 return -EIO;
11562         }
11563
11564         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11565                 return 0;
11566
11567         if (state)
11568                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11569         else
11570                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11571
11572         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11573                 DRM_ERROR("failed to write control word\n");
11574                 return -EIO;
11575         }
11576
11577         return 0;
11578 }
11579
11580 struct intel_display_error_state {
11581
11582         u32 power_well_driver;
11583
11584         int num_transcoders;
11585
11586         struct intel_cursor_error_state {
11587                 u32 control;
11588                 u32 position;
11589                 u32 base;
11590                 u32 size;
11591         } cursor[I915_MAX_PIPES];
11592
11593         struct intel_pipe_error_state {
11594                 bool power_domain_on;
11595                 u32 source;
11596         } pipe[I915_MAX_PIPES];
11597
11598         struct intel_plane_error_state {
11599                 u32 control;
11600                 u32 stride;
11601                 u32 size;
11602                 u32 pos;
11603                 u32 addr;
11604                 u32 surface;
11605                 u32 tile_offset;
11606         } plane[I915_MAX_PIPES];
11607
11608         struct intel_transcoder_error_state {
11609                 bool power_domain_on;
11610                 enum transcoder cpu_transcoder;
11611
11612                 u32 conf;
11613
11614                 u32 htotal;
11615                 u32 hblank;
11616                 u32 hsync;
11617                 u32 vtotal;
11618                 u32 vblank;
11619                 u32 vsync;
11620         } transcoder[4];
11621 };
11622
11623 struct intel_display_error_state *
11624 intel_display_capture_error_state(struct drm_device *dev)
11625 {
11626         drm_i915_private_t *dev_priv = dev->dev_private;
11627         struct intel_display_error_state *error;
11628         int transcoders[] = {
11629                 TRANSCODER_A,
11630                 TRANSCODER_B,
11631                 TRANSCODER_C,
11632                 TRANSCODER_EDP,
11633         };
11634         int i;
11635
11636         if (INTEL_INFO(dev)->num_pipes == 0)
11637                 return NULL;
11638
11639         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11640         if (error == NULL)
11641                 return NULL;
11642
11643         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11644                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11645
11646         for_each_pipe(i) {
11647                 error->pipe[i].power_domain_on =
11648                         intel_display_power_enabled_sw(dev_priv,
11649                                                        POWER_DOMAIN_PIPE(i));
11650                 if (!error->pipe[i].power_domain_on)
11651                         continue;
11652
11653                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11654                         error->cursor[i].control = I915_READ(CURCNTR(i));
11655                         error->cursor[i].position = I915_READ(CURPOS(i));
11656                         error->cursor[i].base = I915_READ(CURBASE(i));
11657                 } else {
11658                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11659                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11660                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11661                 }
11662
11663                 error->plane[i].control = I915_READ(DSPCNTR(i));
11664                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11665                 if (INTEL_INFO(dev)->gen <= 3) {
11666                         error->plane[i].size = I915_READ(DSPSIZE(i));
11667                         error->plane[i].pos = I915_READ(DSPPOS(i));
11668                 }
11669                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11670                         error->plane[i].addr = I915_READ(DSPADDR(i));
11671                 if (INTEL_INFO(dev)->gen >= 4) {
11672                         error->plane[i].surface = I915_READ(DSPSURF(i));
11673                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11674                 }
11675
11676                 error->pipe[i].source = I915_READ(PIPESRC(i));
11677         }
11678
11679         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11680         if (HAS_DDI(dev_priv->dev))
11681                 error->num_transcoders++; /* Account for eDP. */
11682
11683         for (i = 0; i < error->num_transcoders; i++) {
11684                 enum transcoder cpu_transcoder = transcoders[i];
11685
11686                 error->transcoder[i].power_domain_on =
11687                         intel_display_power_enabled_sw(dev_priv,
11688                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11689                 if (!error->transcoder[i].power_domain_on)
11690                         continue;
11691
11692                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11693
11694                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11695                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11696                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11697                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11698                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11699                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11700                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11701         }
11702
11703         return error;
11704 }
11705
11706 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11707
11708 void
11709 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11710                                 struct drm_device *dev,
11711                                 struct intel_display_error_state *error)
11712 {
11713         int i;
11714
11715         if (!error)
11716                 return;
11717
11718         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11719         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11720                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11721                            error->power_well_driver);
11722         for_each_pipe(i) {
11723                 err_printf(m, "Pipe [%d]:\n", i);
11724                 err_printf(m, "  Power: %s\n",
11725                            error->pipe[i].power_domain_on ? "on" : "off");
11726                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11727
11728                 err_printf(m, "Plane [%d]:\n", i);
11729                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11730                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11731                 if (INTEL_INFO(dev)->gen <= 3) {
11732                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11733                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11734                 }
11735                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11736                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11737                 if (INTEL_INFO(dev)->gen >= 4) {
11738                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11739                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11740                 }
11741
11742                 err_printf(m, "Cursor [%d]:\n", i);
11743                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11744                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11745                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11746         }
11747
11748         for (i = 0; i < error->num_transcoders; i++) {
11749                 err_printf(m, "CPU transcoder: %c\n",
11750                            transcoder_name(error->transcoder[i].cpu_transcoder));
11751                 err_printf(m, "  Power: %s\n",
11752                            error->transcoder[i].power_domain_on ? "on" : "off");
11753                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11754                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11755                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11756                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11757                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11758                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11759                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11760         }
11761 }