drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 DRM_DEBUG_KMS("vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455         I915_WRITE(reg, dpll);
1456
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807
1808         /*
1809          * There's no guarantee the pipe will really start running now. It
1810          * depends on the Gen, the output type and the relative order between
1811          * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812          * necessary.
1813          * TODO: audit the previous gens.
1814          */
1815         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816                 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818
1819 /**
1820  * intel_disable_pipe - disable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to disable
1823  *
1824  * Disable @pipe, making sure that various hardware specific requirements
1825  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826  *
1827  * @pipe should be %PIPE_A or %PIPE_B.
1828  *
1829  * Will wait until the pipe has shut down before returning.
1830  */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832                                enum pipe pipe)
1833 {
1834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835                                                                       pipe);
1836         int reg;
1837         u32 val;
1838
1839         /*
1840          * Make sure planes won't keep trying to pump pixels to us,
1841          * or we might hang the display.
1842          */
1843         assert_planes_disabled(dev_priv, pipe);
1844         assert_cursor_disabled(dev_priv, pipe);
1845         assert_sprites_disabled(dev_priv, pipe);
1846
1847         /* Don't disable pipe A or pipe A PLLs if needed */
1848         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849                 return;
1850
1851         reg = PIPECONF(cpu_transcoder);
1852         val = I915_READ(reg);
1853         if ((val & PIPECONF_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861  * Plane regs are double buffered, going from enabled->disabled needs a
1862  * trigger in order to latch.  The display address reg provides this.
1863  */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865                                enum plane plane)
1866 {
1867         struct drm_device *dev = dev_priv->dev;
1868         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870         I915_WRITE(reg, I915_READ(reg));
1871         POSTING_READ(reg);
1872 }
1873
1874 /**
1875  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1876  * @dev_priv: i915 private structure
1877  * @plane: plane to enable
1878  * @pipe: pipe being fed
1879  *
1880  * Enable @plane on @pipe, making sure that @pipe is running first.
1881  */
1882 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1883                                           enum plane plane, enum pipe pipe)
1884 {
1885         struct intel_crtc *intel_crtc =
1886                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887         int reg;
1888         u32 val;
1889
1890         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891         assert_pipe_enabled(dev_priv, pipe);
1892
1893         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894
1895         intel_crtc->primary_enabled = true;
1896
1897         reg = DSPCNTR(plane);
1898         val = I915_READ(reg);
1899         if (val & DISPLAY_PLANE_ENABLE)
1900                 return;
1901
1902         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903         intel_flush_primary_plane(dev_priv, plane);
1904         intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908  * intel_disable_primary_hw_plane - disable the primary hardware plane
1909  * @dev_priv: i915 private structure
1910  * @plane: plane to disable
1911  * @pipe: pipe consuming the data
1912  *
1913  * Disable @plane; should be an independent operation.
1914  */
1915 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1916                                            enum plane plane, enum pipe pipe)
1917 {
1918         struct intel_crtc *intel_crtc =
1919                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920         int reg;
1921         u32 val;
1922
1923         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924
1925         intel_crtc->primary_enabled = false;
1926
1927         reg = DSPCNTR(plane);
1928         val = I915_READ(reg);
1929         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930                 return;
1931
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_primary_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941                 return true;
1942 #endif
1943         return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948         int tile_height;
1949
1950         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951         return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956                            struct drm_i915_gem_object *obj,
1957                            struct intel_ring_buffer *pipelined)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         u32 alignment;
1961         int ret;
1962
1963         switch (obj->tiling_mode) {
1964         case I915_TILING_NONE:
1965                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966                         alignment = 128 * 1024;
1967                 else if (INTEL_INFO(dev)->gen >= 4)
1968                         alignment = 4 * 1024;
1969                 else
1970                         alignment = 64 * 1024;
1971                 break;
1972         case I915_TILING_X:
1973                 /* pin() will align the object as required by fence */
1974                 alignment = 0;
1975                 break;
1976         case I915_TILING_Y:
1977                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978                 return -EINVAL;
1979         default:
1980                 BUG();
1981         }
1982
1983         /* Note that the w/a also requires 64 PTE of padding following the
1984          * bo. We currently fill all unused PTE with the shadow page and so
1985          * we should always have valid PTE following the scanout preventing
1986          * the VT-d warning.
1987          */
1988         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989                 alignment = 256 * 1024;
1990
1991         dev_priv->mm.interruptible = false;
1992         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993         if (ret)
1994                 goto err_interruptible;
1995
1996         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997          * fence, whereas 965+ only requires a fence if using
1998          * framebuffer compression.  For simplicity, we always install
1999          * a fence as the cost is not that onerous.
2000          */
2001         ret = i915_gem_object_get_fence(obj);
2002         if (ret)
2003                 goto err_unpin;
2004
2005         i915_gem_object_pin_fence(obj);
2006
2007         dev_priv->mm.interruptible = true;
2008         return 0;
2009
2010 err_unpin:
2011         i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013         dev_priv->mm.interruptible = true;
2014         return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019         i915_gem_object_unpin_fence(obj);
2020         i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024  * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026                                              unsigned int tiling_mode,
2027                                              unsigned int cpp,
2028                                              unsigned int pitch)
2029 {
2030         if (tiling_mode != I915_TILING_NONE) {
2031                 unsigned int tile_rows, tiles;
2032
2033                 tile_rows = *y / 8;
2034                 *y %= 8;
2035
2036                 tiles = *x / (512/cpp);
2037                 *x %= 512/cpp;
2038
2039                 return tile_rows * pitch * 8 + tiles * 4096;
2040         } else {
2041                 unsigned int offset;
2042
2043                 offset = *y * pitch + *x * cpp;
2044                 *y = 0;
2045                 *x = (offset & 4095) / cpp;
2046                 return offset & -4096;
2047         }
2048 }
2049
2050 int intel_format_to_fourcc(int format)
2051 {
2052         switch (format) {
2053         case DISPPLANE_8BPP:
2054                 return DRM_FORMAT_C8;
2055         case DISPPLANE_BGRX555:
2056                 return DRM_FORMAT_XRGB1555;
2057         case DISPPLANE_BGRX565:
2058                 return DRM_FORMAT_RGB565;
2059         default:
2060         case DISPPLANE_BGRX888:
2061                 return DRM_FORMAT_XRGB8888;
2062         case DISPPLANE_RGBX888:
2063                 return DRM_FORMAT_XBGR8888;
2064         case DISPPLANE_BGRX101010:
2065                 return DRM_FORMAT_XRGB2101010;
2066         case DISPPLANE_RGBX101010:
2067                 return DRM_FORMAT_XBGR2101010;
2068         }
2069 }
2070
2071 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2072                                   struct intel_plane_config *plane_config)
2073 {
2074         struct drm_device *dev = crtc->base.dev;
2075         struct drm_i915_gem_object *obj = NULL;
2076         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2077         u32 base = plane_config->base;
2078
2079         if (plane_config->size == 0)
2080                 return false;
2081
2082         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2083                                                              plane_config->size);
2084         if (!obj)
2085                 return false;
2086
2087         if (plane_config->tiled) {
2088                 obj->tiling_mode = I915_TILING_X;
2089                 obj->stride = crtc->base.fb->pitches[0];
2090         }
2091
2092         mode_cmd.pixel_format = crtc->base.fb->pixel_format;
2093         mode_cmd.width = crtc->base.fb->width;
2094         mode_cmd.height = crtc->base.fb->height;
2095         mode_cmd.pitches[0] = crtc->base.fb->pitches[0];
2096
2097         mutex_lock(&dev->struct_mutex);
2098
2099         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.fb),
2100                                    &mode_cmd, obj)) {
2101                 DRM_DEBUG_KMS("intel fb init failed\n");
2102                 goto out_unref_obj;
2103         }
2104
2105         mutex_unlock(&dev->struct_mutex);
2106
2107         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2108         return true;
2109
2110 out_unref_obj:
2111         drm_gem_object_unreference(&obj->base);
2112         mutex_unlock(&dev->struct_mutex);
2113         return false;
2114 }
2115
2116 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2117                                  struct intel_plane_config *plane_config)
2118 {
2119         struct drm_device *dev = intel_crtc->base.dev;
2120         struct drm_crtc *c;
2121         struct intel_crtc *i;
2122         struct intel_framebuffer *fb;
2123
2124         if (!intel_crtc->base.fb)
2125                 return;
2126
2127         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2128                 return;
2129
2130         kfree(intel_crtc->base.fb);
2131         intel_crtc->base.fb = NULL;
2132
2133         /*
2134          * Failed to alloc the obj, check to see if we should share
2135          * an fb with another CRTC instead
2136          */
2137         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2138                 i = to_intel_crtc(c);
2139
2140                 if (c == &intel_crtc->base)
2141                         continue;
2142
2143                 if (!i->active || !c->fb)
2144                         continue;
2145
2146                 fb = to_intel_framebuffer(c->fb);
2147                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2148                         drm_framebuffer_reference(c->fb);
2149                         intel_crtc->base.fb = c->fb;
2150                         break;
2151                 }
2152         }
2153 }
2154
2155 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2156                                      struct drm_framebuffer *fb,
2157                                      int x, int y)
2158 {
2159         struct drm_device *dev = crtc->dev;
2160         struct drm_i915_private *dev_priv = dev->dev_private;
2161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162         struct intel_framebuffer *intel_fb;
2163         struct drm_i915_gem_object *obj;
2164         int plane = intel_crtc->plane;
2165         unsigned long linear_offset;
2166         u32 dspcntr;
2167         u32 reg;
2168
2169         switch (plane) {
2170         case 0:
2171         case 1:
2172                 break;
2173         default:
2174                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2175                 return -EINVAL;
2176         }
2177
2178         intel_fb = to_intel_framebuffer(fb);
2179         obj = intel_fb->obj;
2180
2181         reg = DSPCNTR(plane);
2182         dspcntr = I915_READ(reg);
2183         /* Mask out pixel format bits in case we change it */
2184         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2185         switch (fb->pixel_format) {
2186         case DRM_FORMAT_C8:
2187                 dspcntr |= DISPPLANE_8BPP;
2188                 break;
2189         case DRM_FORMAT_XRGB1555:
2190         case DRM_FORMAT_ARGB1555:
2191                 dspcntr |= DISPPLANE_BGRX555;
2192                 break;
2193         case DRM_FORMAT_RGB565:
2194                 dspcntr |= DISPPLANE_BGRX565;
2195                 break;
2196         case DRM_FORMAT_XRGB8888:
2197         case DRM_FORMAT_ARGB8888:
2198                 dspcntr |= DISPPLANE_BGRX888;
2199                 break;
2200         case DRM_FORMAT_XBGR8888:
2201         case DRM_FORMAT_ABGR8888:
2202                 dspcntr |= DISPPLANE_RGBX888;
2203                 break;
2204         case DRM_FORMAT_XRGB2101010:
2205         case DRM_FORMAT_ARGB2101010:
2206                 dspcntr |= DISPPLANE_BGRX101010;
2207                 break;
2208         case DRM_FORMAT_XBGR2101010:
2209         case DRM_FORMAT_ABGR2101010:
2210                 dspcntr |= DISPPLANE_RGBX101010;
2211                 break;
2212         default:
2213                 BUG();
2214         }
2215
2216         if (INTEL_INFO(dev)->gen >= 4) {
2217                 if (obj->tiling_mode != I915_TILING_NONE)
2218                         dspcntr |= DISPPLANE_TILED;
2219                 else
2220                         dspcntr &= ~DISPPLANE_TILED;
2221         }
2222
2223         if (IS_G4X(dev))
2224                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2225
2226         I915_WRITE(reg, dspcntr);
2227
2228         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2229
2230         if (INTEL_INFO(dev)->gen >= 4) {
2231                 intel_crtc->dspaddr_offset =
2232                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2233                                                        fb->bits_per_pixel / 8,
2234                                                        fb->pitches[0]);
2235                 linear_offset -= intel_crtc->dspaddr_offset;
2236         } else {
2237                 intel_crtc->dspaddr_offset = linear_offset;
2238         }
2239
2240         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2241                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2242                       fb->pitches[0]);
2243         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2244         if (INTEL_INFO(dev)->gen >= 4) {
2245                 I915_WRITE(DSPSURF(plane),
2246                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2247                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2248                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2249         } else
2250                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2251         POSTING_READ(reg);
2252
2253         return 0;
2254 }
2255
2256 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2257                                          struct drm_framebuffer *fb,
2258                                          int x, int y)
2259 {
2260         struct drm_device *dev = crtc->dev;
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263         struct intel_framebuffer *intel_fb;
2264         struct drm_i915_gem_object *obj;
2265         int plane = intel_crtc->plane;
2266         unsigned long linear_offset;
2267         u32 dspcntr;
2268         u32 reg;
2269
2270         switch (plane) {
2271         case 0:
2272         case 1:
2273         case 2:
2274                 break;
2275         default:
2276                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2277                 return -EINVAL;
2278         }
2279
2280         intel_fb = to_intel_framebuffer(fb);
2281         obj = intel_fb->obj;
2282
2283         reg = DSPCNTR(plane);
2284         dspcntr = I915_READ(reg);
2285         /* Mask out pixel format bits in case we change it */
2286         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2287         switch (fb->pixel_format) {
2288         case DRM_FORMAT_C8:
2289                 dspcntr |= DISPPLANE_8BPP;
2290                 break;
2291         case DRM_FORMAT_RGB565:
2292                 dspcntr |= DISPPLANE_BGRX565;
2293                 break;
2294         case DRM_FORMAT_XRGB8888:
2295         case DRM_FORMAT_ARGB8888:
2296                 dspcntr |= DISPPLANE_BGRX888;
2297                 break;
2298         case DRM_FORMAT_XBGR8888:
2299         case DRM_FORMAT_ABGR8888:
2300                 dspcntr |= DISPPLANE_RGBX888;
2301                 break;
2302         case DRM_FORMAT_XRGB2101010:
2303         case DRM_FORMAT_ARGB2101010:
2304                 dspcntr |= DISPPLANE_BGRX101010;
2305                 break;
2306         case DRM_FORMAT_XBGR2101010:
2307         case DRM_FORMAT_ABGR2101010:
2308                 dspcntr |= DISPPLANE_RGBX101010;
2309                 break;
2310         default:
2311                 BUG();
2312         }
2313
2314         if (obj->tiling_mode != I915_TILING_NONE)
2315                 dspcntr |= DISPPLANE_TILED;
2316         else
2317                 dspcntr &= ~DISPPLANE_TILED;
2318
2319         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2320                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2321         else
2322                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2323
2324         I915_WRITE(reg, dspcntr);
2325
2326         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327         intel_crtc->dspaddr_offset =
2328                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2329                                                fb->bits_per_pixel / 8,
2330                                                fb->pitches[0]);
2331         linear_offset -= intel_crtc->dspaddr_offset;
2332
2333         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2334                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2335                       fb->pitches[0]);
2336         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2337         I915_WRITE(DSPSURF(plane),
2338                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2339         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2340                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2341         } else {
2342                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2343                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2344         }
2345         POSTING_READ(reg);
2346
2347         return 0;
2348 }
2349
2350 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2351 static int
2352 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2353                            int x, int y, enum mode_set_atomic state)
2354 {
2355         struct drm_device *dev = crtc->dev;
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357
2358         if (dev_priv->display.disable_fbc)
2359                 dev_priv->display.disable_fbc(dev);
2360         intel_increase_pllclock(crtc);
2361
2362         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2363 }
2364
2365 void intel_display_handle_reset(struct drm_device *dev)
2366 {
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         struct drm_crtc *crtc;
2369
2370         /*
2371          * Flips in the rings have been nuked by the reset,
2372          * so complete all pending flips so that user space
2373          * will get its events and not get stuck.
2374          *
2375          * Also update the base address of all primary
2376          * planes to the the last fb to make sure we're
2377          * showing the correct fb after a reset.
2378          *
2379          * Need to make two loops over the crtcs so that we
2380          * don't try to grab a crtc mutex before the
2381          * pending_flip_queue really got woken up.
2382          */
2383
2384         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2385                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386                 enum plane plane = intel_crtc->plane;
2387
2388                 intel_prepare_page_flip(dev, plane);
2389                 intel_finish_page_flip_plane(dev, plane);
2390         }
2391
2392         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2393                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394
2395                 mutex_lock(&crtc->mutex);
2396                 /*
2397                  * FIXME: Once we have proper support for primary planes (and
2398                  * disabling them without disabling the entire crtc) allow again
2399                  * a NULL crtc->fb.
2400                  */
2401                 if (intel_crtc->active && crtc->fb)
2402                         dev_priv->display.update_primary_plane(crtc,
2403                                                                crtc->fb,
2404                                                                crtc->x,
2405                                                                crtc->y);
2406                 mutex_unlock(&crtc->mutex);
2407         }
2408 }
2409
2410 static int
2411 intel_finish_fb(struct drm_framebuffer *old_fb)
2412 {
2413         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2414         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2415         bool was_interruptible = dev_priv->mm.interruptible;
2416         int ret;
2417
2418         /* Big Hammer, we also need to ensure that any pending
2419          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2420          * current scanout is retired before unpinning the old
2421          * framebuffer.
2422          *
2423          * This should only fail upon a hung GPU, in which case we
2424          * can safely continue.
2425          */
2426         dev_priv->mm.interruptible = false;
2427         ret = i915_gem_object_finish_gpu(obj);
2428         dev_priv->mm.interruptible = was_interruptible;
2429
2430         return ret;
2431 }
2432
2433 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2434 {
2435         struct drm_device *dev = crtc->dev;
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2438         unsigned long flags;
2439         bool pending;
2440
2441         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2442             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2443                 return false;
2444
2445         spin_lock_irqsave(&dev->event_lock, flags);
2446         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2447         spin_unlock_irqrestore(&dev->event_lock, flags);
2448
2449         return pending;
2450 }
2451
2452 static int
2453 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2454                     struct drm_framebuffer *fb)
2455 {
2456         struct drm_device *dev = crtc->dev;
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2459         struct drm_framebuffer *old_fb;
2460         int ret;
2461
2462         if (intel_crtc_has_pending_flip(crtc)) {
2463                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2464                 return -EBUSY;
2465         }
2466
2467         /* no fb bound */
2468         if (!fb) {
2469                 DRM_ERROR("No FB bound\n");
2470                 return 0;
2471         }
2472
2473         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2474                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2475                           plane_name(intel_crtc->plane),
2476                           INTEL_INFO(dev)->num_pipes);
2477                 return -EINVAL;
2478         }
2479
2480         mutex_lock(&dev->struct_mutex);
2481         ret = intel_pin_and_fence_fb_obj(dev,
2482                                          to_intel_framebuffer(fb)->obj,
2483                                          NULL);
2484         mutex_unlock(&dev->struct_mutex);
2485         if (ret != 0) {
2486                 DRM_ERROR("pin & fence failed\n");
2487                 return ret;
2488         }
2489
2490         /*
2491          * Update pipe size and adjust fitter if needed: the reason for this is
2492          * that in compute_mode_changes we check the native mode (not the pfit
2493          * mode) to see if we can flip rather than do a full mode set. In the
2494          * fastboot case, we'll flip, but if we don't update the pipesrc and
2495          * pfit state, we'll end up with a big fb scanned out into the wrong
2496          * sized surface.
2497          *
2498          * To fix this properly, we need to hoist the checks up into
2499          * compute_mode_changes (or above), check the actual pfit state and
2500          * whether the platform allows pfit disable with pipe active, and only
2501          * then update the pipesrc and pfit state, even on the flip path.
2502          */
2503         if (i915.fastboot) {
2504                 const struct drm_display_mode *adjusted_mode =
2505                         &intel_crtc->config.adjusted_mode;
2506
2507                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2508                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2509                            (adjusted_mode->crtc_vdisplay - 1));
2510                 if (!intel_crtc->config.pch_pfit.enabled &&
2511                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2512                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2513                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2514                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2515                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2516                 }
2517                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2518                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2519         }
2520
2521         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522         if (ret) {
2523                 mutex_lock(&dev->struct_mutex);
2524                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2525                 mutex_unlock(&dev->struct_mutex);
2526                 DRM_ERROR("failed to update base address\n");
2527                 return ret;
2528         }
2529
2530         old_fb = crtc->fb;
2531         crtc->fb = fb;
2532         crtc->x = x;
2533         crtc->y = y;
2534
2535         if (old_fb) {
2536                 if (intel_crtc->active && old_fb != fb)
2537                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2538                 mutex_lock(&dev->struct_mutex);
2539                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2540                 mutex_unlock(&dev->struct_mutex);
2541         }
2542
2543         mutex_lock(&dev->struct_mutex);
2544         intel_update_fbc(dev);
2545         intel_edp_psr_update(dev);
2546         mutex_unlock(&dev->struct_mutex);
2547
2548         return 0;
2549 }
2550
2551 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2552 {
2553         struct drm_device *dev = crtc->dev;
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556         int pipe = intel_crtc->pipe;
2557         u32 reg, temp;
2558
2559         /* enable normal train */
2560         reg = FDI_TX_CTL(pipe);
2561         temp = I915_READ(reg);
2562         if (IS_IVYBRIDGE(dev)) {
2563                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2564                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2565         } else {
2566                 temp &= ~FDI_LINK_TRAIN_NONE;
2567                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2568         }
2569         I915_WRITE(reg, temp);
2570
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         if (HAS_PCH_CPT(dev)) {
2574                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2576         } else {
2577                 temp &= ~FDI_LINK_TRAIN_NONE;
2578                 temp |= FDI_LINK_TRAIN_NONE;
2579         }
2580         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2581
2582         /* wait one idle pattern time */
2583         POSTING_READ(reg);
2584         udelay(1000);
2585
2586         /* IVB wants error correction enabled */
2587         if (IS_IVYBRIDGE(dev))
2588                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2589                            FDI_FE_ERRC_ENABLE);
2590 }
2591
2592 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2593 {
2594         return crtc->base.enabled && crtc->active &&
2595                 crtc->config.has_pch_encoder;
2596 }
2597
2598 static void ivb_modeset_global_resources(struct drm_device *dev)
2599 {
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_crtc *pipe_B_crtc =
2602                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2603         struct intel_crtc *pipe_C_crtc =
2604                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2605         uint32_t temp;
2606
2607         /*
2608          * When everything is off disable fdi C so that we could enable fdi B
2609          * with all lanes. Note that we don't care about enabled pipes without
2610          * an enabled pch encoder.
2611          */
2612         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2613             !pipe_has_enabled_pch(pipe_C_crtc)) {
2614                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2615                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2616
2617                 temp = I915_READ(SOUTH_CHICKEN1);
2618                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2619                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2620                 I915_WRITE(SOUTH_CHICKEN1, temp);
2621         }
2622 }
2623
2624 /* The FDI link training functions for ILK/Ibexpeak. */
2625 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2626 {
2627         struct drm_device *dev = crtc->dev;
2628         struct drm_i915_private *dev_priv = dev->dev_private;
2629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2630         int pipe = intel_crtc->pipe;
2631         int plane = intel_crtc->plane;
2632         u32 reg, temp, tries;
2633
2634         /* FDI needs bits from pipe & plane first */
2635         assert_pipe_enabled(dev_priv, pipe);
2636         assert_plane_enabled(dev_priv, plane);
2637
2638         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639            for train result */
2640         reg = FDI_RX_IMR(pipe);
2641         temp = I915_READ(reg);
2642         temp &= ~FDI_RX_SYMBOL_LOCK;
2643         temp &= ~FDI_RX_BIT_LOCK;
2644         I915_WRITE(reg, temp);
2645         I915_READ(reg);
2646         udelay(150);
2647
2648         /* enable CPU FDI TX and PCH FDI RX */
2649         reg = FDI_TX_CTL(pipe);
2650         temp = I915_READ(reg);
2651         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2652         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2653         temp &= ~FDI_LINK_TRAIN_NONE;
2654         temp |= FDI_LINK_TRAIN_PATTERN_1;
2655         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2656
2657         reg = FDI_RX_CTL(pipe);
2658         temp = I915_READ(reg);
2659         temp &= ~FDI_LINK_TRAIN_NONE;
2660         temp |= FDI_LINK_TRAIN_PATTERN_1;
2661         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2662
2663         POSTING_READ(reg);
2664         udelay(150);
2665
2666         /* Ironlake workaround, enable clock pointer after FDI enable*/
2667         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2668         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2669                    FDI_RX_PHASE_SYNC_POINTER_EN);
2670
2671         reg = FDI_RX_IIR(pipe);
2672         for (tries = 0; tries < 5; tries++) {
2673                 temp = I915_READ(reg);
2674                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676                 if ((temp & FDI_RX_BIT_LOCK)) {
2677                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2678                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2679                         break;
2680                 }
2681         }
2682         if (tries == 5)
2683                 DRM_ERROR("FDI train 1 fail!\n");
2684
2685         /* Train 2 */
2686         reg = FDI_TX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_LINK_TRAIN_NONE;
2689         temp |= FDI_LINK_TRAIN_PATTERN_2;
2690         I915_WRITE(reg, temp);
2691
2692         reg = FDI_RX_CTL(pipe);
2693         temp = I915_READ(reg);
2694         temp &= ~FDI_LINK_TRAIN_NONE;
2695         temp |= FDI_LINK_TRAIN_PATTERN_2;
2696         I915_WRITE(reg, temp);
2697
2698         POSTING_READ(reg);
2699         udelay(150);
2700
2701         reg = FDI_RX_IIR(pipe);
2702         for (tries = 0; tries < 5; tries++) {
2703                 temp = I915_READ(reg);
2704                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705
2706                 if (temp & FDI_RX_SYMBOL_LOCK) {
2707                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2709                         break;
2710                 }
2711         }
2712         if (tries == 5)
2713                 DRM_ERROR("FDI train 2 fail!\n");
2714
2715         DRM_DEBUG_KMS("FDI train done\n");
2716
2717 }
2718
2719 static const int snb_b_fdi_train_param[] = {
2720         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2721         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2722         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2723         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2724 };
2725
2726 /* The FDI link training functions for SNB/Cougarpoint. */
2727 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2728 {
2729         struct drm_device *dev = crtc->dev;
2730         struct drm_i915_private *dev_priv = dev->dev_private;
2731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2732         int pipe = intel_crtc->pipe;
2733         u32 reg, temp, i, retry;
2734
2735         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2736            for train result */
2737         reg = FDI_RX_IMR(pipe);
2738         temp = I915_READ(reg);
2739         temp &= ~FDI_RX_SYMBOL_LOCK;
2740         temp &= ~FDI_RX_BIT_LOCK;
2741         I915_WRITE(reg, temp);
2742
2743         POSTING_READ(reg);
2744         udelay(150);
2745
2746         /* enable CPU FDI TX and PCH FDI RX */
2747         reg = FDI_TX_CTL(pipe);
2748         temp = I915_READ(reg);
2749         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2750         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2751         temp &= ~FDI_LINK_TRAIN_NONE;
2752         temp |= FDI_LINK_TRAIN_PATTERN_1;
2753         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2754         /* SNB-B */
2755         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2756         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2757
2758         I915_WRITE(FDI_RX_MISC(pipe),
2759                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2760
2761         reg = FDI_RX_CTL(pipe);
2762         temp = I915_READ(reg);
2763         if (HAS_PCH_CPT(dev)) {
2764                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2765                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2766         } else {
2767                 temp &= ~FDI_LINK_TRAIN_NONE;
2768                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2769         }
2770         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2771
2772         POSTING_READ(reg);
2773         udelay(150);
2774
2775         for (i = 0; i < 4; i++) {
2776                 reg = FDI_TX_CTL(pipe);
2777                 temp = I915_READ(reg);
2778                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779                 temp |= snb_b_fdi_train_param[i];
2780                 I915_WRITE(reg, temp);
2781
2782                 POSTING_READ(reg);
2783                 udelay(500);
2784
2785                 for (retry = 0; retry < 5; retry++) {
2786                         reg = FDI_RX_IIR(pipe);
2787                         temp = I915_READ(reg);
2788                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789                         if (temp & FDI_RX_BIT_LOCK) {
2790                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2792                                 break;
2793                         }
2794                         udelay(50);
2795                 }
2796                 if (retry < 5)
2797                         break;
2798         }
2799         if (i == 4)
2800                 DRM_ERROR("FDI train 1 fail!\n");
2801
2802         /* Train 2 */
2803         reg = FDI_TX_CTL(pipe);
2804         temp = I915_READ(reg);
2805         temp &= ~FDI_LINK_TRAIN_NONE;
2806         temp |= FDI_LINK_TRAIN_PATTERN_2;
2807         if (IS_GEN6(dev)) {
2808                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2809                 /* SNB-B */
2810                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2811         }
2812         I915_WRITE(reg, temp);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         if (HAS_PCH_CPT(dev)) {
2817                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2818                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2819         } else {
2820                 temp &= ~FDI_LINK_TRAIN_NONE;
2821                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2822         }
2823         I915_WRITE(reg, temp);
2824
2825         POSTING_READ(reg);
2826         udelay(150);
2827
2828         for (i = 0; i < 4; i++) {
2829                 reg = FDI_TX_CTL(pipe);
2830                 temp = I915_READ(reg);
2831                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2832                 temp |= snb_b_fdi_train_param[i];
2833                 I915_WRITE(reg, temp);
2834
2835                 POSTING_READ(reg);
2836                 udelay(500);
2837
2838                 for (retry = 0; retry < 5; retry++) {
2839                         reg = FDI_RX_IIR(pipe);
2840                         temp = I915_READ(reg);
2841                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2842                         if (temp & FDI_RX_SYMBOL_LOCK) {
2843                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2844                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2845                                 break;
2846                         }
2847                         udelay(50);
2848                 }
2849                 if (retry < 5)
2850                         break;
2851         }
2852         if (i == 4)
2853                 DRM_ERROR("FDI train 2 fail!\n");
2854
2855         DRM_DEBUG_KMS("FDI train done.\n");
2856 }
2857
2858 /* Manual link training for Ivy Bridge A0 parts */
2859 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2860 {
2861         struct drm_device *dev = crtc->dev;
2862         struct drm_i915_private *dev_priv = dev->dev_private;
2863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864         int pipe = intel_crtc->pipe;
2865         u32 reg, temp, i, j;
2866
2867         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2868            for train result */
2869         reg = FDI_RX_IMR(pipe);
2870         temp = I915_READ(reg);
2871         temp &= ~FDI_RX_SYMBOL_LOCK;
2872         temp &= ~FDI_RX_BIT_LOCK;
2873         I915_WRITE(reg, temp);
2874
2875         POSTING_READ(reg);
2876         udelay(150);
2877
2878         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2879                       I915_READ(FDI_RX_IIR(pipe)));
2880
2881         /* Try each vswing and preemphasis setting twice before moving on */
2882         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2883                 /* disable first in case we need to retry */
2884                 reg = FDI_TX_CTL(pipe);
2885                 temp = I915_READ(reg);
2886                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2887                 temp &= ~FDI_TX_ENABLE;
2888                 I915_WRITE(reg, temp);
2889
2890                 reg = FDI_RX_CTL(pipe);
2891                 temp = I915_READ(reg);
2892                 temp &= ~FDI_LINK_TRAIN_AUTO;
2893                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2894                 temp &= ~FDI_RX_ENABLE;
2895                 I915_WRITE(reg, temp);
2896
2897                 /* enable CPU FDI TX and PCH FDI RX */
2898                 reg = FDI_TX_CTL(pipe);
2899                 temp = I915_READ(reg);
2900                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2901                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2902                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2903                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2904                 temp |= snb_b_fdi_train_param[j/2];
2905                 temp |= FDI_COMPOSITE_SYNC;
2906                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2907
2908                 I915_WRITE(FDI_RX_MISC(pipe),
2909                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2910
2911                 reg = FDI_RX_CTL(pipe);
2912                 temp = I915_READ(reg);
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914                 temp |= FDI_COMPOSITE_SYNC;
2915                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2916
2917                 POSTING_READ(reg);
2918                 udelay(1); /* should be 0.5us */
2919
2920                 for (i = 0; i < 4; i++) {
2921                         reg = FDI_RX_IIR(pipe);
2922                         temp = I915_READ(reg);
2923                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2924
2925                         if (temp & FDI_RX_BIT_LOCK ||
2926                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2927                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2928                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2929                                               i);
2930                                 break;
2931                         }
2932                         udelay(1); /* should be 0.5us */
2933                 }
2934                 if (i == 4) {
2935                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2936                         continue;
2937                 }
2938
2939                 /* Train 2 */
2940                 reg = FDI_TX_CTL(pipe);
2941                 temp = I915_READ(reg);
2942                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2943                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2944                 I915_WRITE(reg, temp);
2945
2946                 reg = FDI_RX_CTL(pipe);
2947                 temp = I915_READ(reg);
2948                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2950                 I915_WRITE(reg, temp);
2951
2952                 POSTING_READ(reg);
2953                 udelay(2); /* should be 1.5us */
2954
2955                 for (i = 0; i < 4; i++) {
2956                         reg = FDI_RX_IIR(pipe);
2957                         temp = I915_READ(reg);
2958                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2959
2960                         if (temp & FDI_RX_SYMBOL_LOCK ||
2961                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2962                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2963                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2964                                               i);
2965                                 goto train_done;
2966                         }
2967                         udelay(2); /* should be 1.5us */
2968                 }
2969                 if (i == 4)
2970                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2971         }
2972
2973 train_done:
2974         DRM_DEBUG_KMS("FDI train done.\n");
2975 }
2976
2977 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2978 {
2979         struct drm_device *dev = intel_crtc->base.dev;
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         int pipe = intel_crtc->pipe;
2982         u32 reg, temp;
2983
2984
2985         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2986         reg = FDI_RX_CTL(pipe);
2987         temp = I915_READ(reg);
2988         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2989         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2990         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2991         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2992
2993         POSTING_READ(reg);
2994         udelay(200);
2995
2996         /* Switch from Rawclk to PCDclk */
2997         temp = I915_READ(reg);
2998         I915_WRITE(reg, temp | FDI_PCDCLK);
2999
3000         POSTING_READ(reg);
3001         udelay(200);
3002
3003         /* Enable CPU FDI TX PLL, always on for Ironlake */
3004         reg = FDI_TX_CTL(pipe);
3005         temp = I915_READ(reg);
3006         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3007                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3008
3009                 POSTING_READ(reg);
3010                 udelay(100);
3011         }
3012 }
3013
3014 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3015 {
3016         struct drm_device *dev = intel_crtc->base.dev;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         int pipe = intel_crtc->pipe;
3019         u32 reg, temp;
3020
3021         /* Switch from PCDclk to Rawclk */
3022         reg = FDI_RX_CTL(pipe);
3023         temp = I915_READ(reg);
3024         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3025
3026         /* Disable CPU FDI TX PLL */
3027         reg = FDI_TX_CTL(pipe);
3028         temp = I915_READ(reg);
3029         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3030
3031         POSTING_READ(reg);
3032         udelay(100);
3033
3034         reg = FDI_RX_CTL(pipe);
3035         temp = I915_READ(reg);
3036         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3037
3038         /* Wait for the clocks to turn off. */
3039         POSTING_READ(reg);
3040         udelay(100);
3041 }
3042
3043 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3044 {
3045         struct drm_device *dev = crtc->dev;
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048         int pipe = intel_crtc->pipe;
3049         u32 reg, temp;
3050
3051         /* disable CPU FDI tx and PCH FDI rx */
3052         reg = FDI_TX_CTL(pipe);
3053         temp = I915_READ(reg);
3054         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3055         POSTING_READ(reg);
3056
3057         reg = FDI_RX_CTL(pipe);
3058         temp = I915_READ(reg);
3059         temp &= ~(0x7 << 16);
3060         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3061         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3062
3063         POSTING_READ(reg);
3064         udelay(100);
3065
3066         /* Ironlake workaround, disable clock pointer after downing FDI */
3067         if (HAS_PCH_IBX(dev)) {
3068                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3069         }
3070
3071         /* still set train pattern 1 */
3072         reg = FDI_TX_CTL(pipe);
3073         temp = I915_READ(reg);
3074         temp &= ~FDI_LINK_TRAIN_NONE;
3075         temp |= FDI_LINK_TRAIN_PATTERN_1;
3076         I915_WRITE(reg, temp);
3077
3078         reg = FDI_RX_CTL(pipe);
3079         temp = I915_READ(reg);
3080         if (HAS_PCH_CPT(dev)) {
3081                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3082                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3083         } else {
3084                 temp &= ~FDI_LINK_TRAIN_NONE;
3085                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3086         }
3087         /* BPC in FDI rx is consistent with that in PIPECONF */
3088         temp &= ~(0x07 << 16);
3089         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3090         I915_WRITE(reg, temp);
3091
3092         POSTING_READ(reg);
3093         udelay(100);
3094 }
3095
3096 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3097 {
3098         struct intel_crtc *crtc;
3099
3100         /* Note that we don't need to be called with mode_config.lock here
3101          * as our list of CRTC objects is static for the lifetime of the
3102          * device and so cannot disappear as we iterate. Similarly, we can
3103          * happily treat the predicates as racy, atomic checks as userspace
3104          * cannot claim and pin a new fb without at least acquring the
3105          * struct_mutex and so serialising with us.
3106          */
3107         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3108                 if (atomic_read(&crtc->unpin_work_count) == 0)
3109                         continue;
3110
3111                 if (crtc->unpin_work)
3112                         intel_wait_for_vblank(dev, crtc->pipe);
3113
3114                 return true;
3115         }
3116
3117         return false;
3118 }
3119
3120 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124
3125         if (crtc->fb == NULL)
3126                 return;
3127
3128         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3129
3130         wait_event(dev_priv->pending_flip_queue,
3131                    !intel_crtc_has_pending_flip(crtc));
3132
3133         mutex_lock(&dev->struct_mutex);
3134         intel_finish_fb(crtc->fb);
3135         mutex_unlock(&dev->struct_mutex);
3136 }
3137
3138 /* Program iCLKIP clock to the desired frequency */
3139 static void lpt_program_iclkip(struct drm_crtc *crtc)
3140 {
3141         struct drm_device *dev = crtc->dev;
3142         struct drm_i915_private *dev_priv = dev->dev_private;
3143         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3144         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3145         u32 temp;
3146
3147         mutex_lock(&dev_priv->dpio_lock);
3148
3149         /* It is necessary to ungate the pixclk gate prior to programming
3150          * the divisors, and gate it back when it is done.
3151          */
3152         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3153
3154         /* Disable SSCCTL */
3155         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3156                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3157                                 SBI_SSCCTL_DISABLE,
3158                         SBI_ICLK);
3159
3160         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3161         if (clock == 20000) {
3162                 auxdiv = 1;
3163                 divsel = 0x41;
3164                 phaseinc = 0x20;
3165         } else {
3166                 /* The iCLK virtual clock root frequency is in MHz,
3167                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3168                  * divisors, it is necessary to divide one by another, so we
3169                  * convert the virtual clock precision to KHz here for higher
3170                  * precision.
3171                  */
3172                 u32 iclk_virtual_root_freq = 172800 * 1000;
3173                 u32 iclk_pi_range = 64;
3174                 u32 desired_divisor, msb_divisor_value, pi_value;
3175
3176                 desired_divisor = (iclk_virtual_root_freq / clock);
3177                 msb_divisor_value = desired_divisor / iclk_pi_range;
3178                 pi_value = desired_divisor % iclk_pi_range;
3179
3180                 auxdiv = 0;
3181                 divsel = msb_divisor_value - 2;
3182                 phaseinc = pi_value;
3183         }
3184
3185         /* This should not happen with any sane values */
3186         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3187                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3188         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3189                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3190
3191         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3192                         clock,
3193                         auxdiv,
3194                         divsel,
3195                         phasedir,
3196                         phaseinc);
3197
3198         /* Program SSCDIVINTPHASE6 */
3199         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3200         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3201         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3202         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3203         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3204         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3205         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3206         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3207
3208         /* Program SSCAUXDIV */
3209         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3210         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3211         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3212         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3213
3214         /* Enable modulator and associated divider */
3215         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3216         temp &= ~SBI_SSCCTL_DISABLE;
3217         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3218
3219         /* Wait for initialization time */
3220         udelay(24);
3221
3222         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3223
3224         mutex_unlock(&dev_priv->dpio_lock);
3225 }
3226
3227 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3228                                                 enum pipe pch_transcoder)
3229 {
3230         struct drm_device *dev = crtc->base.dev;
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3233
3234         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3235                    I915_READ(HTOTAL(cpu_transcoder)));
3236         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3237                    I915_READ(HBLANK(cpu_transcoder)));
3238         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3239                    I915_READ(HSYNC(cpu_transcoder)));
3240
3241         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3242                    I915_READ(VTOTAL(cpu_transcoder)));
3243         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3244                    I915_READ(VBLANK(cpu_transcoder)));
3245         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3246                    I915_READ(VSYNC(cpu_transcoder)));
3247         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3248                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3249 }
3250
3251 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3252 {
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         uint32_t temp;
3255
3256         temp = I915_READ(SOUTH_CHICKEN1);
3257         if (temp & FDI_BC_BIFURCATION_SELECT)
3258                 return;
3259
3260         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3261         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3262
3263         temp |= FDI_BC_BIFURCATION_SELECT;
3264         DRM_DEBUG_KMS("enabling fdi C rx\n");
3265         I915_WRITE(SOUTH_CHICKEN1, temp);
3266         POSTING_READ(SOUTH_CHICKEN1);
3267 }
3268
3269 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3270 {
3271         struct drm_device *dev = intel_crtc->base.dev;
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274         switch (intel_crtc->pipe) {
3275         case PIPE_A:
3276                 break;
3277         case PIPE_B:
3278                 if (intel_crtc->config.fdi_lanes > 2)
3279                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3280                 else
3281                         cpt_enable_fdi_bc_bifurcation(dev);
3282
3283                 break;
3284         case PIPE_C:
3285                 cpt_enable_fdi_bc_bifurcation(dev);
3286
3287                 break;
3288         default:
3289                 BUG();
3290         }
3291 }
3292
3293 /*
3294  * Enable PCH resources required for PCH ports:
3295  *   - PCH PLLs
3296  *   - FDI training & RX/TX
3297  *   - update transcoder timings
3298  *   - DP transcoding bits
3299  *   - transcoder
3300  */
3301 static void ironlake_pch_enable(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         int pipe = intel_crtc->pipe;
3307         u32 reg, temp;
3308
3309         assert_pch_transcoder_disabled(dev_priv, pipe);
3310
3311         if (IS_IVYBRIDGE(dev))
3312                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3313
3314         /* Write the TU size bits before fdi link training, so that error
3315          * detection works. */
3316         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3317                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3318
3319         /* For PCH output, training FDI link */
3320         dev_priv->display.fdi_link_train(crtc);
3321
3322         /* We need to program the right clock selection before writing the pixel
3323          * mutliplier into the DPLL. */
3324         if (HAS_PCH_CPT(dev)) {
3325                 u32 sel;
3326
3327                 temp = I915_READ(PCH_DPLL_SEL);
3328                 temp |= TRANS_DPLL_ENABLE(pipe);
3329                 sel = TRANS_DPLLB_SEL(pipe);
3330                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3331                         temp |= sel;
3332                 else
3333                         temp &= ~sel;
3334                 I915_WRITE(PCH_DPLL_SEL, temp);
3335         }
3336
3337         /* XXX: pch pll's can be enabled any time before we enable the PCH
3338          * transcoder, and we actually should do this to not upset any PCH
3339          * transcoder that already use the clock when we share it.
3340          *
3341          * Note that enable_shared_dpll tries to do the right thing, but
3342          * get_shared_dpll unconditionally resets the pll - we need that to have
3343          * the right LVDS enable sequence. */
3344         ironlake_enable_shared_dpll(intel_crtc);
3345
3346         /* set transcoder timing, panel must allow it */
3347         assert_panel_unlocked(dev_priv, pipe);
3348         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3349
3350         intel_fdi_normal_train(crtc);
3351
3352         /* For PCH DP, enable TRANS_DP_CTL */
3353         if (HAS_PCH_CPT(dev) &&
3354             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3355              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3356                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3357                 reg = TRANS_DP_CTL(pipe);
3358                 temp = I915_READ(reg);
3359                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3360                           TRANS_DP_SYNC_MASK |
3361                           TRANS_DP_BPC_MASK);
3362                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3363                          TRANS_DP_ENH_FRAMING);
3364                 temp |= bpc << 9; /* same format but at 11:9 */
3365
3366                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3367                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3368                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3369                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3370
3371                 switch (intel_trans_dp_port_sel(crtc)) {
3372                 case PCH_DP_B:
3373                         temp |= TRANS_DP_PORT_SEL_B;
3374                         break;
3375                 case PCH_DP_C:
3376                         temp |= TRANS_DP_PORT_SEL_C;
3377                         break;
3378                 case PCH_DP_D:
3379                         temp |= TRANS_DP_PORT_SEL_D;
3380                         break;
3381                 default:
3382                         BUG();
3383                 }
3384
3385                 I915_WRITE(reg, temp);
3386         }
3387
3388         ironlake_enable_pch_transcoder(dev_priv, pipe);
3389 }
3390
3391 static void lpt_pch_enable(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3397
3398         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3399
3400         lpt_program_iclkip(crtc);
3401
3402         /* Set transcoder timing. */
3403         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3404
3405         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3406 }
3407
3408 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3409 {
3410         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3411
3412         if (pll == NULL)
3413                 return;
3414
3415         if (pll->refcount == 0) {
3416                 WARN(1, "bad %s refcount\n", pll->name);
3417                 return;
3418         }
3419
3420         if (--pll->refcount == 0) {
3421                 WARN_ON(pll->on);
3422                 WARN_ON(pll->active);
3423         }
3424
3425         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3426 }
3427
3428 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3429 {
3430         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3431         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3432         enum intel_dpll_id i;
3433
3434         if (pll) {
3435                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3436                               crtc->base.base.id, pll->name);
3437                 intel_put_shared_dpll(crtc);
3438         }
3439
3440         if (HAS_PCH_IBX(dev_priv->dev)) {
3441                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3442                 i = (enum intel_dpll_id) crtc->pipe;
3443                 pll = &dev_priv->shared_dplls[i];
3444
3445                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3446                               crtc->base.base.id, pll->name);
3447
3448                 goto found;
3449         }
3450
3451         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3452                 pll = &dev_priv->shared_dplls[i];
3453
3454                 /* Only want to check enabled timings first */
3455                 if (pll->refcount == 0)
3456                         continue;
3457
3458                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3459                            sizeof(pll->hw_state)) == 0) {
3460                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3461                                       crtc->base.base.id,
3462                                       pll->name, pll->refcount, pll->active);
3463
3464                         goto found;
3465                 }
3466         }
3467
3468         /* Ok no matching timings, maybe there's a free one? */
3469         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3470                 pll = &dev_priv->shared_dplls[i];
3471                 if (pll->refcount == 0) {
3472                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3473                                       crtc->base.base.id, pll->name);
3474                         goto found;
3475                 }
3476         }
3477
3478         return NULL;
3479
3480 found:
3481         crtc->config.shared_dpll = i;
3482         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3483                          pipe_name(crtc->pipe));
3484
3485         if (pll->active == 0) {
3486                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3487                        sizeof(pll->hw_state));
3488
3489                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3490                 WARN_ON(pll->on);
3491                 assert_shared_dpll_disabled(dev_priv, pll);
3492
3493                 pll->mode_set(dev_priv, pll);
3494         }
3495         pll->refcount++;
3496
3497         return pll;
3498 }
3499
3500 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3501 {
3502         struct drm_i915_private *dev_priv = dev->dev_private;
3503         int dslreg = PIPEDSL(pipe);
3504         u32 temp;
3505
3506         temp = I915_READ(dslreg);
3507         udelay(500);
3508         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3509                 if (wait_for(I915_READ(dslreg) != temp, 5))
3510                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3511         }
3512 }
3513
3514 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->base.dev;
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518         int pipe = crtc->pipe;
3519
3520         if (crtc->config.pch_pfit.enabled) {
3521                 /* Force use of hard-coded filter coefficients
3522                  * as some pre-programmed values are broken,
3523                  * e.g. x201.
3524                  */
3525                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3526                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3527                                                  PF_PIPE_SEL_IVB(pipe));
3528                 else
3529                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3530                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3531                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3532         }
3533 }
3534
3535 static void intel_enable_planes(struct drm_crtc *crtc)
3536 {
3537         struct drm_device *dev = crtc->dev;
3538         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3539         struct intel_plane *intel_plane;
3540
3541         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3542                 if (intel_plane->pipe == pipe)
3543                         intel_plane_restore(&intel_plane->base);
3544 }
3545
3546 static void intel_disable_planes(struct drm_crtc *crtc)
3547 {
3548         struct drm_device *dev = crtc->dev;
3549         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3550         struct intel_plane *intel_plane;
3551
3552         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3553                 if (intel_plane->pipe == pipe)
3554                         intel_plane_disable(&intel_plane->base);
3555 }
3556
3557 void hsw_enable_ips(struct intel_crtc *crtc)
3558 {
3559         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3560
3561         if (!crtc->config.ips_enabled)
3562                 return;
3563
3564         /* We can only enable IPS after we enable a plane and wait for a vblank.
3565          * We guarantee that the plane is enabled by calling intel_enable_ips
3566          * only after intel_enable_plane. And intel_enable_plane already waits
3567          * for a vblank, so all we need to do here is to enable the IPS bit. */
3568         assert_plane_enabled(dev_priv, crtc->plane);
3569         if (IS_BROADWELL(crtc->base.dev)) {
3570                 mutex_lock(&dev_priv->rps.hw_lock);
3571                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3572                 mutex_unlock(&dev_priv->rps.hw_lock);
3573                 /* Quoting Art Runyan: "its not safe to expect any particular
3574                  * value in IPS_CTL bit 31 after enabling IPS through the
3575                  * mailbox." Moreover, the mailbox may return a bogus state,
3576                  * so we need to just enable it and continue on.
3577                  */
3578         } else {
3579                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3580                 /* The bit only becomes 1 in the next vblank, so this wait here
3581                  * is essentially intel_wait_for_vblank. If we don't have this
3582                  * and don't wait for vblanks until the end of crtc_enable, then
3583                  * the HW state readout code will complain that the expected
3584                  * IPS_CTL value is not the one we read. */
3585                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3586                         DRM_ERROR("Timed out waiting for IPS enable\n");
3587         }
3588 }
3589
3590 void hsw_disable_ips(struct intel_crtc *crtc)
3591 {
3592         struct drm_device *dev = crtc->base.dev;
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595         if (!crtc->config.ips_enabled)
3596                 return;
3597
3598         assert_plane_enabled(dev_priv, crtc->plane);
3599         if (IS_BROADWELL(crtc->base.dev)) {
3600                 mutex_lock(&dev_priv->rps.hw_lock);
3601                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3602                 mutex_unlock(&dev_priv->rps.hw_lock);
3603         } else {
3604                 I915_WRITE(IPS_CTL, 0);
3605                 POSTING_READ(IPS_CTL);
3606         }
3607
3608         /* We need to wait for a vblank before we can disable the plane. */
3609         intel_wait_for_vblank(dev, crtc->pipe);
3610 }
3611
3612 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3613 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3614 {
3615         struct drm_device *dev = crtc->dev;
3616         struct drm_i915_private *dev_priv = dev->dev_private;
3617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618         enum pipe pipe = intel_crtc->pipe;
3619         int palreg = PALETTE(pipe);
3620         int i;
3621         bool reenable_ips = false;
3622
3623         /* The clocks have to be on to load the palette. */
3624         if (!crtc->enabled || !intel_crtc->active)
3625                 return;
3626
3627         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3628                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3629                         assert_dsi_pll_enabled(dev_priv);
3630                 else
3631                         assert_pll_enabled(dev_priv, pipe);
3632         }
3633
3634         /* use legacy palette for Ironlake */
3635         if (HAS_PCH_SPLIT(dev))
3636                 palreg = LGC_PALETTE(pipe);
3637
3638         /* Workaround : Do not read or write the pipe palette/gamma data while
3639          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3640          */
3641         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3642             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3643              GAMMA_MODE_MODE_SPLIT)) {
3644                 hsw_disable_ips(intel_crtc);
3645                 reenable_ips = true;
3646         }
3647
3648         for (i = 0; i < 256; i++) {
3649                 I915_WRITE(palreg + 4 * i,
3650                            (intel_crtc->lut_r[i] << 16) |
3651                            (intel_crtc->lut_g[i] << 8) |
3652                            intel_crtc->lut_b[i]);
3653         }
3654
3655         if (reenable_ips)
3656                 hsw_enable_ips(intel_crtc);
3657 }
3658
3659 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3660 {
3661         struct drm_device *dev = crtc->dev;
3662         struct drm_i915_private *dev_priv = dev->dev_private;
3663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664         struct intel_encoder *encoder;
3665         int pipe = intel_crtc->pipe;
3666         int plane = intel_crtc->plane;
3667
3668         WARN_ON(!crtc->enabled);
3669
3670         if (intel_crtc->active)
3671                 return;
3672
3673         intel_crtc->active = true;
3674
3675         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3676         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3677
3678         for_each_encoder_on_crtc(dev, crtc, encoder)
3679                 if (encoder->pre_enable)
3680                         encoder->pre_enable(encoder);
3681
3682         if (intel_crtc->config.has_pch_encoder) {
3683                 /* Note: FDI PLL enabling _must_ be done before we enable the
3684                  * cpu pipes, hence this is separate from all the other fdi/pch
3685                  * enabling. */
3686                 ironlake_fdi_pll_enable(intel_crtc);
3687         } else {
3688                 assert_fdi_tx_disabled(dev_priv, pipe);
3689                 assert_fdi_rx_disabled(dev_priv, pipe);
3690         }
3691
3692         ironlake_pfit_enable(intel_crtc);
3693
3694         /*
3695          * On ILK+ LUT must be loaded before the pipe is running but with
3696          * clocks enabled
3697          */
3698         intel_crtc_load_lut(crtc);
3699
3700         intel_update_watermarks(crtc);
3701         intel_enable_pipe(intel_crtc);
3702         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3703         intel_enable_planes(crtc);
3704         intel_crtc_update_cursor(crtc, true);
3705
3706         if (intel_crtc->config.has_pch_encoder)
3707                 ironlake_pch_enable(crtc);
3708
3709         mutex_lock(&dev->struct_mutex);
3710         intel_update_fbc(dev);
3711         mutex_unlock(&dev->struct_mutex);
3712
3713         for_each_encoder_on_crtc(dev, crtc, encoder)
3714                 encoder->enable(encoder);
3715
3716         if (HAS_PCH_CPT(dev))
3717                 cpt_verify_modeset(dev, intel_crtc->pipe);
3718
3719         /*
3720          * There seems to be a race in PCH platform hw (at least on some
3721          * outputs) where an enabled pipe still completes any pageflip right
3722          * away (as if the pipe is off) instead of waiting for vblank. As soon
3723          * as the first vblank happend, everything works as expected. Hence just
3724          * wait for one vblank before returning to avoid strange things
3725          * happening.
3726          */
3727         intel_wait_for_vblank(dev, intel_crtc->pipe);
3728 }
3729
3730 /* IPS only exists on ULT machines and is tied to pipe A. */
3731 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3732 {
3733         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3734 }
3735
3736 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_private *dev_priv = dev->dev_private;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742         int plane = intel_crtc->plane;
3743
3744         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3745         intel_enable_planes(crtc);
3746         intel_crtc_update_cursor(crtc, true);
3747
3748         hsw_enable_ips(intel_crtc);
3749
3750         mutex_lock(&dev->struct_mutex);
3751         intel_update_fbc(dev);
3752         mutex_unlock(&dev->struct_mutex);
3753 }
3754
3755 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3756 {
3757         struct drm_device *dev = crtc->dev;
3758         struct drm_i915_private *dev_priv = dev->dev_private;
3759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3760         int pipe = intel_crtc->pipe;
3761         int plane = intel_crtc->plane;
3762
3763         intel_crtc_wait_for_pending_flips(crtc);
3764         drm_vblank_off(dev, pipe);
3765
3766         /* FBC must be disabled before disabling the plane on HSW. */
3767         if (dev_priv->fbc.plane == plane)
3768                 intel_disable_fbc(dev);
3769
3770         hsw_disable_ips(intel_crtc);
3771
3772         intel_crtc_update_cursor(crtc, false);
3773         intel_disable_planes(crtc);
3774         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3775 }
3776
3777 /*
3778  * This implements the workaround described in the "notes" section of the mode
3779  * set sequence documentation. When going from no pipes or single pipe to
3780  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3781  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3782  */
3783 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3784 {
3785         struct drm_device *dev = crtc->base.dev;
3786         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3787
3788         /* We want to get the other_active_crtc only if there's only 1 other
3789          * active crtc. */
3790         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3791                 if (!crtc_it->active || crtc_it == crtc)
3792                         continue;
3793
3794                 if (other_active_crtc)
3795                         return;
3796
3797                 other_active_crtc = crtc_it;
3798         }
3799         if (!other_active_crtc)
3800                 return;
3801
3802         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3803         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3804 }
3805
3806 static void haswell_crtc_enable(struct drm_crtc *crtc)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3811         struct intel_encoder *encoder;
3812         int pipe = intel_crtc->pipe;
3813
3814         WARN_ON(!crtc->enabled);
3815
3816         if (intel_crtc->active)
3817                 return;
3818
3819         intel_crtc->active = true;
3820
3821         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3822         if (intel_crtc->config.has_pch_encoder)
3823                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3824
3825         if (intel_crtc->config.has_pch_encoder)
3826                 dev_priv->display.fdi_link_train(crtc);
3827
3828         for_each_encoder_on_crtc(dev, crtc, encoder)
3829                 if (encoder->pre_enable)
3830                         encoder->pre_enable(encoder);
3831
3832         intel_ddi_enable_pipe_clock(intel_crtc);
3833
3834         ironlake_pfit_enable(intel_crtc);
3835
3836         /*
3837          * On ILK+ LUT must be loaded before the pipe is running but with
3838          * clocks enabled
3839          */
3840         intel_crtc_load_lut(crtc);
3841
3842         intel_ddi_set_pipe_settings(crtc);
3843         intel_ddi_enable_transcoder_func(crtc);
3844
3845         intel_update_watermarks(crtc);
3846         intel_enable_pipe(intel_crtc);
3847
3848         if (intel_crtc->config.has_pch_encoder)
3849                 lpt_pch_enable(crtc);
3850
3851         for_each_encoder_on_crtc(dev, crtc, encoder) {
3852                 encoder->enable(encoder);
3853                 intel_opregion_notify_encoder(encoder, true);
3854         }
3855
3856         /* If we change the relative order between pipe/planes enabling, we need
3857          * to change the workaround. */
3858         haswell_mode_set_planes_workaround(intel_crtc);
3859         haswell_crtc_enable_planes(crtc);
3860 }
3861
3862 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3863 {
3864         struct drm_device *dev = crtc->base.dev;
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         int pipe = crtc->pipe;
3867
3868         /* To avoid upsetting the power well on haswell only disable the pfit if
3869          * it's in use. The hw state code will make sure we get this right. */
3870         if (crtc->config.pch_pfit.enabled) {
3871                 I915_WRITE(PF_CTL(pipe), 0);
3872                 I915_WRITE(PF_WIN_POS(pipe), 0);
3873                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3874         }
3875 }
3876
3877 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3878 {
3879         struct drm_device *dev = crtc->dev;
3880         struct drm_i915_private *dev_priv = dev->dev_private;
3881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3882         struct intel_encoder *encoder;
3883         int pipe = intel_crtc->pipe;
3884         int plane = intel_crtc->plane;
3885         u32 reg, temp;
3886
3887
3888         if (!intel_crtc->active)
3889                 return;
3890
3891         for_each_encoder_on_crtc(dev, crtc, encoder)
3892                 encoder->disable(encoder);
3893
3894         intel_crtc_wait_for_pending_flips(crtc);
3895         drm_vblank_off(dev, pipe);
3896
3897         if (dev_priv->fbc.plane == plane)
3898                 intel_disable_fbc(dev);
3899
3900         intel_crtc_update_cursor(crtc, false);
3901         intel_disable_planes(crtc);
3902         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3903
3904         if (intel_crtc->config.has_pch_encoder)
3905                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3906
3907         intel_disable_pipe(dev_priv, pipe);
3908
3909         ironlake_pfit_disable(intel_crtc);
3910
3911         for_each_encoder_on_crtc(dev, crtc, encoder)
3912                 if (encoder->post_disable)
3913                         encoder->post_disable(encoder);
3914
3915         if (intel_crtc->config.has_pch_encoder) {
3916                 ironlake_fdi_disable(crtc);
3917
3918                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3919                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3920
3921                 if (HAS_PCH_CPT(dev)) {
3922                         /* disable TRANS_DP_CTL */
3923                         reg = TRANS_DP_CTL(pipe);
3924                         temp = I915_READ(reg);
3925                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3926                                   TRANS_DP_PORT_SEL_MASK);
3927                         temp |= TRANS_DP_PORT_SEL_NONE;
3928                         I915_WRITE(reg, temp);
3929
3930                         /* disable DPLL_SEL */
3931                         temp = I915_READ(PCH_DPLL_SEL);
3932                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3933                         I915_WRITE(PCH_DPLL_SEL, temp);
3934                 }
3935
3936                 /* disable PCH DPLL */
3937                 intel_disable_shared_dpll(intel_crtc);
3938
3939                 ironlake_fdi_pll_disable(intel_crtc);
3940         }
3941
3942         intel_crtc->active = false;
3943         intel_update_watermarks(crtc);
3944
3945         mutex_lock(&dev->struct_mutex);
3946         intel_update_fbc(dev);
3947         mutex_unlock(&dev->struct_mutex);
3948 }
3949
3950 static void haswell_crtc_disable(struct drm_crtc *crtc)
3951 {
3952         struct drm_device *dev = crtc->dev;
3953         struct drm_i915_private *dev_priv = dev->dev_private;
3954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955         struct intel_encoder *encoder;
3956         int pipe = intel_crtc->pipe;
3957         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3958
3959         if (!intel_crtc->active)
3960                 return;
3961
3962         haswell_crtc_disable_planes(crtc);
3963
3964         for_each_encoder_on_crtc(dev, crtc, encoder) {
3965                 intel_opregion_notify_encoder(encoder, false);
3966                 encoder->disable(encoder);
3967         }
3968
3969         if (intel_crtc->config.has_pch_encoder)
3970                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3971         intel_disable_pipe(dev_priv, pipe);
3972
3973         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3974
3975         ironlake_pfit_disable(intel_crtc);
3976
3977         intel_ddi_disable_pipe_clock(intel_crtc);
3978
3979         for_each_encoder_on_crtc(dev, crtc, encoder)
3980                 if (encoder->post_disable)
3981                         encoder->post_disable(encoder);
3982
3983         if (intel_crtc->config.has_pch_encoder) {
3984                 lpt_disable_pch_transcoder(dev_priv);
3985                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3986                 intel_ddi_fdi_disable(crtc);
3987         }
3988
3989         intel_crtc->active = false;
3990         intel_update_watermarks(crtc);
3991
3992         mutex_lock(&dev->struct_mutex);
3993         intel_update_fbc(dev);
3994         mutex_unlock(&dev->struct_mutex);
3995 }
3996
3997 static void ironlake_crtc_off(struct drm_crtc *crtc)
3998 {
3999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4000         intel_put_shared_dpll(intel_crtc);
4001 }
4002
4003 static void haswell_crtc_off(struct drm_crtc *crtc)
4004 {
4005         intel_ddi_put_crtc_pll(crtc);
4006 }
4007
4008 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4009 {
4010         if (!enable && intel_crtc->overlay) {
4011                 struct drm_device *dev = intel_crtc->base.dev;
4012                 struct drm_i915_private *dev_priv = dev->dev_private;
4013
4014                 mutex_lock(&dev->struct_mutex);
4015                 dev_priv->mm.interruptible = false;
4016                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4017                 dev_priv->mm.interruptible = true;
4018                 mutex_unlock(&dev->struct_mutex);
4019         }
4020
4021         /* Let userspace switch the overlay on again. In most cases userspace
4022          * has to recompute where to put it anyway.
4023          */
4024 }
4025
4026 /**
4027  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
4028  * cursor plane briefly if not already running after enabling the display
4029  * plane.
4030  * This workaround avoids occasional blank screens when self refresh is
4031  * enabled.
4032  */
4033 static void
4034 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
4035 {
4036         u32 cntl = I915_READ(CURCNTR(pipe));
4037
4038         if ((cntl & CURSOR_MODE) == 0) {
4039                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4040
4041                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4042                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4043                 intel_wait_for_vblank(dev_priv->dev, pipe);
4044                 I915_WRITE(CURCNTR(pipe), cntl);
4045                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4046                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4047         }
4048 }
4049
4050 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4051 {
4052         struct drm_device *dev = crtc->base.dev;
4053         struct drm_i915_private *dev_priv = dev->dev_private;
4054         struct intel_crtc_config *pipe_config = &crtc->config;
4055
4056         if (!crtc->config.gmch_pfit.control)
4057                 return;
4058
4059         /*
4060          * The panel fitter should only be adjusted whilst the pipe is disabled,
4061          * according to register description and PRM.
4062          */
4063         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4064         assert_pipe_disabled(dev_priv, crtc->pipe);
4065
4066         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4067         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4068
4069         /* Border color in case we don't scale up to the full screen. Black by
4070          * default, change to something else for debugging. */
4071         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4072 }
4073
4074 #define for_each_power_domain(domain, mask)                             \
4075         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4076                 if ((1 << (domain)) & (mask))
4077
4078 enum intel_display_power_domain
4079 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4080 {
4081         struct drm_device *dev = intel_encoder->base.dev;
4082         struct intel_digital_port *intel_dig_port;
4083
4084         switch (intel_encoder->type) {
4085         case INTEL_OUTPUT_UNKNOWN:
4086                 /* Only DDI platforms should ever use this output type */
4087                 WARN_ON_ONCE(!HAS_DDI(dev));
4088         case INTEL_OUTPUT_DISPLAYPORT:
4089         case INTEL_OUTPUT_HDMI:
4090         case INTEL_OUTPUT_EDP:
4091                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4092                 switch (intel_dig_port->port) {
4093                 case PORT_A:
4094                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4095                 case PORT_B:
4096                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4097                 case PORT_C:
4098                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4099                 case PORT_D:
4100                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4101                 default:
4102                         WARN_ON_ONCE(1);
4103                         return POWER_DOMAIN_PORT_OTHER;
4104                 }
4105         case INTEL_OUTPUT_ANALOG:
4106                 return POWER_DOMAIN_PORT_CRT;
4107         case INTEL_OUTPUT_DSI:
4108                 return POWER_DOMAIN_PORT_DSI;
4109         default:
4110                 return POWER_DOMAIN_PORT_OTHER;
4111         }
4112 }
4113
4114 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct intel_encoder *intel_encoder;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         enum pipe pipe = intel_crtc->pipe;
4120         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4121         unsigned long mask;
4122         enum transcoder transcoder;
4123
4124         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4125
4126         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4127         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4128         if (pfit_enabled)
4129                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4130
4131         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4132                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4133
4134         return mask;
4135 }
4136
4137 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4138                                   bool enable)
4139 {
4140         if (dev_priv->power_domains.init_power_on == enable)
4141                 return;
4142
4143         if (enable)
4144                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4145         else
4146                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4147
4148         dev_priv->power_domains.init_power_on = enable;
4149 }
4150
4151 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4152 {
4153         struct drm_i915_private *dev_priv = dev->dev_private;
4154         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4155         struct intel_crtc *crtc;
4156
4157         /*
4158          * First get all needed power domains, then put all unneeded, to avoid
4159          * any unnecessary toggling of the power wells.
4160          */
4161         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4162                 enum intel_display_power_domain domain;
4163
4164                 if (!crtc->base.enabled)
4165                         continue;
4166
4167                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4168
4169                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4170                         intel_display_power_get(dev_priv, domain);
4171         }
4172
4173         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4174                 enum intel_display_power_domain domain;
4175
4176                 for_each_power_domain(domain, crtc->enabled_power_domains)
4177                         intel_display_power_put(dev_priv, domain);
4178
4179                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4180         }
4181
4182         intel_display_set_init_power(dev_priv, false);
4183 }
4184
4185 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4186 {
4187         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4188
4189         /* Obtain SKU information */
4190         mutex_lock(&dev_priv->dpio_lock);
4191         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4192                 CCK_FUSE_HPLL_FREQ_MASK;
4193         mutex_unlock(&dev_priv->dpio_lock);
4194
4195         return vco_freq[hpll_freq];
4196 }
4197
4198 /* Adjust CDclk dividers to allow high res or save power if possible */
4199 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4200 {
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         u32 val, cmd;
4203
4204         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4205                 cmd = 2;
4206         else if (cdclk == 266)
4207                 cmd = 1;
4208         else
4209                 cmd = 0;
4210
4211         mutex_lock(&dev_priv->rps.hw_lock);
4212         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4213         val &= ~DSPFREQGUAR_MASK;
4214         val |= (cmd << DSPFREQGUAR_SHIFT);
4215         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4216         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4217                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4218                      50)) {
4219                 DRM_ERROR("timed out waiting for CDclk change\n");
4220         }
4221         mutex_unlock(&dev_priv->rps.hw_lock);
4222
4223         if (cdclk == 400) {
4224                 u32 divider, vco;
4225
4226                 vco = valleyview_get_vco(dev_priv);
4227                 divider = ((vco << 1) / cdclk) - 1;
4228
4229                 mutex_lock(&dev_priv->dpio_lock);
4230                 /* adjust cdclk divider */
4231                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4232                 val &= ~0xf;
4233                 val |= divider;
4234                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4235                 mutex_unlock(&dev_priv->dpio_lock);
4236         }
4237
4238         mutex_lock(&dev_priv->dpio_lock);
4239         /* adjust self-refresh exit latency value */
4240         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4241         val &= ~0x7f;
4242
4243         /*
4244          * For high bandwidth configs, we set a higher latency in the bunit
4245          * so that the core display fetch happens in time to avoid underruns.
4246          */
4247         if (cdclk == 400)
4248                 val |= 4500 / 250; /* 4.5 usec */
4249         else
4250                 val |= 3000 / 250; /* 3.0 usec */
4251         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4252         mutex_unlock(&dev_priv->dpio_lock);
4253
4254         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4255         intel_i2c_reset(dev);
4256 }
4257
4258 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4259 {
4260         int cur_cdclk, vco;
4261         int divider;
4262
4263         vco = valleyview_get_vco(dev_priv);
4264
4265         mutex_lock(&dev_priv->dpio_lock);
4266         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4267         mutex_unlock(&dev_priv->dpio_lock);
4268
4269         divider &= 0xf;
4270
4271         cur_cdclk = (vco << 1) / (divider + 1);
4272
4273         return cur_cdclk;
4274 }
4275
4276 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4277                                  int max_pixclk)
4278 {
4279         int cur_cdclk;
4280
4281         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4282
4283         /*
4284          * Really only a few cases to deal with, as only 4 CDclks are supported:
4285          *   200MHz
4286          *   267MHz
4287          *   320MHz
4288          *   400MHz
4289          * So we check to see whether we're above 90% of the lower bin and
4290          * adjust if needed.
4291          */
4292         if (max_pixclk > 288000) {
4293                 return 400;
4294         } else if (max_pixclk > 240000) {
4295                 return 320;
4296         } else
4297                 return 266;
4298         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4299 }
4300
4301 /* compute the max pixel clock for new configuration */
4302 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4303 {
4304         struct drm_device *dev = dev_priv->dev;
4305         struct intel_crtc *intel_crtc;
4306         int max_pixclk = 0;
4307
4308         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4309                             base.head) {
4310                 if (intel_crtc->new_enabled)
4311                         max_pixclk = max(max_pixclk,
4312                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4313         }
4314
4315         return max_pixclk;
4316 }
4317
4318 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4319                                             unsigned *prepare_pipes)
4320 {
4321         struct drm_i915_private *dev_priv = dev->dev_private;
4322         struct intel_crtc *intel_crtc;
4323         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4324         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4325
4326         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4327                 return;
4328
4329         /* disable/enable all currently active pipes while we change cdclk */
4330         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4331                             base.head)
4332                 if (intel_crtc->base.enabled)
4333                         *prepare_pipes |= (1 << intel_crtc->pipe);
4334 }
4335
4336 static void valleyview_modeset_global_resources(struct drm_device *dev)
4337 {
4338         struct drm_i915_private *dev_priv = dev->dev_private;
4339         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4340         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4341         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4342
4343         if (req_cdclk != cur_cdclk)
4344                 valleyview_set_cdclk(dev, req_cdclk);
4345         modeset_update_crtc_power_domains(dev);
4346 }
4347
4348 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4349 {
4350         struct drm_device *dev = crtc->dev;
4351         struct drm_i915_private *dev_priv = dev->dev_private;
4352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4353         struct intel_encoder *encoder;
4354         int pipe = intel_crtc->pipe;
4355         int plane = intel_crtc->plane;
4356         bool is_dsi;
4357
4358         WARN_ON(!crtc->enabled);
4359
4360         if (intel_crtc->active)
4361                 return;
4362
4363         intel_crtc->active = true;
4364
4365         for_each_encoder_on_crtc(dev, crtc, encoder)
4366                 if (encoder->pre_pll_enable)
4367                         encoder->pre_pll_enable(encoder);
4368
4369         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4370
4371         if (!is_dsi)
4372                 vlv_enable_pll(intel_crtc);
4373
4374         for_each_encoder_on_crtc(dev, crtc, encoder)
4375                 if (encoder->pre_enable)
4376                         encoder->pre_enable(encoder);
4377
4378         i9xx_pfit_enable(intel_crtc);
4379
4380         intel_crtc_load_lut(crtc);
4381
4382         intel_update_watermarks(crtc);
4383         intel_enable_pipe(intel_crtc);
4384         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4385         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4386         intel_enable_planes(crtc);
4387         intel_crtc_update_cursor(crtc, true);
4388
4389         intel_update_fbc(dev);
4390
4391         for_each_encoder_on_crtc(dev, crtc, encoder)
4392                 encoder->enable(encoder);
4393 }
4394
4395 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4396 {
4397         struct drm_device *dev = crtc->dev;
4398         struct drm_i915_private *dev_priv = dev->dev_private;
4399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4400         struct intel_encoder *encoder;
4401         int pipe = intel_crtc->pipe;
4402         int plane = intel_crtc->plane;
4403
4404         WARN_ON(!crtc->enabled);
4405
4406         if (intel_crtc->active)
4407                 return;
4408
4409         intel_crtc->active = true;
4410
4411         for_each_encoder_on_crtc(dev, crtc, encoder)
4412                 if (encoder->pre_enable)
4413                         encoder->pre_enable(encoder);
4414
4415         i9xx_enable_pll(intel_crtc);
4416
4417         i9xx_pfit_enable(intel_crtc);
4418
4419         intel_crtc_load_lut(crtc);
4420
4421         intel_update_watermarks(crtc);
4422         intel_enable_pipe(intel_crtc);
4423         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4424         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4425         intel_enable_planes(crtc);
4426         /* The fixup needs to happen before cursor is enabled */
4427         if (IS_G4X(dev))
4428                 g4x_fixup_plane(dev_priv, pipe);
4429         intel_crtc_update_cursor(crtc, true);
4430
4431         /* Give the overlay scaler a chance to enable if it's on this pipe */
4432         intel_crtc_dpms_overlay(intel_crtc, true);
4433
4434         intel_update_fbc(dev);
4435
4436         for_each_encoder_on_crtc(dev, crtc, encoder)
4437                 encoder->enable(encoder);
4438 }
4439
4440 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4441 {
4442         struct drm_device *dev = crtc->base.dev;
4443         struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445         if (!crtc->config.gmch_pfit.control)
4446                 return;
4447
4448         assert_pipe_disabled(dev_priv, crtc->pipe);
4449
4450         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4451                          I915_READ(PFIT_CONTROL));
4452         I915_WRITE(PFIT_CONTROL, 0);
4453 }
4454
4455 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4456 {
4457         struct drm_device *dev = crtc->dev;
4458         struct drm_i915_private *dev_priv = dev->dev_private;
4459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4460         struct intel_encoder *encoder;
4461         int pipe = intel_crtc->pipe;
4462         int plane = intel_crtc->plane;
4463
4464         if (!intel_crtc->active)
4465                 return;
4466
4467         for_each_encoder_on_crtc(dev, crtc, encoder)
4468                 encoder->disable(encoder);
4469
4470         /* Give the overlay scaler a chance to disable if it's on this pipe */
4471         intel_crtc_wait_for_pending_flips(crtc);
4472         drm_vblank_off(dev, pipe);
4473
4474         if (dev_priv->fbc.plane == plane)
4475                 intel_disable_fbc(dev);
4476
4477         intel_crtc_dpms_overlay(intel_crtc, false);
4478         intel_crtc_update_cursor(crtc, false);
4479         intel_disable_planes(crtc);
4480         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4481
4482         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4483         intel_disable_pipe(dev_priv, pipe);
4484
4485         i9xx_pfit_disable(intel_crtc);
4486
4487         for_each_encoder_on_crtc(dev, crtc, encoder)
4488                 if (encoder->post_disable)
4489                         encoder->post_disable(encoder);
4490
4491         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4492                 vlv_disable_pll(dev_priv, pipe);
4493         else if (!IS_VALLEYVIEW(dev))
4494                 i9xx_disable_pll(dev_priv, pipe);
4495
4496         intel_crtc->active = false;
4497         intel_update_watermarks(crtc);
4498
4499         intel_update_fbc(dev);
4500 }
4501
4502 static void i9xx_crtc_off(struct drm_crtc *crtc)
4503 {
4504 }
4505
4506 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4507                                     bool enabled)
4508 {
4509         struct drm_device *dev = crtc->dev;
4510         struct drm_i915_master_private *master_priv;
4511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4512         int pipe = intel_crtc->pipe;
4513
4514         if (!dev->primary->master)
4515                 return;
4516
4517         master_priv = dev->primary->master->driver_priv;
4518         if (!master_priv->sarea_priv)
4519                 return;
4520
4521         switch (pipe) {
4522         case 0:
4523                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4524                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4525                 break;
4526         case 1:
4527                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4528                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4529                 break;
4530         default:
4531                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4532                 break;
4533         }
4534 }
4535
4536 /**
4537  * Sets the power management mode of the pipe and plane.
4538  */
4539 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4540 {
4541         struct drm_device *dev = crtc->dev;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         struct intel_encoder *intel_encoder;
4544         bool enable = false;
4545
4546         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4547                 enable |= intel_encoder->connectors_active;
4548
4549         if (enable)
4550                 dev_priv->display.crtc_enable(crtc);
4551         else
4552                 dev_priv->display.crtc_disable(crtc);
4553
4554         intel_crtc_update_sarea(crtc, enable);
4555 }
4556
4557 static void intel_crtc_disable(struct drm_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         struct drm_connector *connector;
4561         struct drm_i915_private *dev_priv = dev->dev_private;
4562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4563
4564         /* crtc should still be enabled when we disable it. */
4565         WARN_ON(!crtc->enabled);
4566
4567         dev_priv->display.crtc_disable(crtc);
4568         intel_crtc->eld_vld = false;
4569         intel_crtc_update_sarea(crtc, false);
4570         dev_priv->display.off(crtc);
4571
4572         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4573         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4574         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4575
4576         if (crtc->fb) {
4577                 mutex_lock(&dev->struct_mutex);
4578                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4579                 mutex_unlock(&dev->struct_mutex);
4580                 crtc->fb = NULL;
4581         }
4582
4583         /* Update computed state. */
4584         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4585                 if (!connector->encoder || !connector->encoder->crtc)
4586                         continue;
4587
4588                 if (connector->encoder->crtc != crtc)
4589                         continue;
4590
4591                 connector->dpms = DRM_MODE_DPMS_OFF;
4592                 to_intel_encoder(connector->encoder)->connectors_active = false;
4593         }
4594 }
4595
4596 void intel_encoder_destroy(struct drm_encoder *encoder)
4597 {
4598         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4599
4600         drm_encoder_cleanup(encoder);
4601         kfree(intel_encoder);
4602 }
4603
4604 /* Simple dpms helper for encoders with just one connector, no cloning and only
4605  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4606  * state of the entire output pipe. */
4607 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4608 {
4609         if (mode == DRM_MODE_DPMS_ON) {
4610                 encoder->connectors_active = true;
4611
4612                 intel_crtc_update_dpms(encoder->base.crtc);
4613         } else {
4614                 encoder->connectors_active = false;
4615
4616                 intel_crtc_update_dpms(encoder->base.crtc);
4617         }
4618 }
4619
4620 /* Cross check the actual hw state with our own modeset state tracking (and it's
4621  * internal consistency). */
4622 static void intel_connector_check_state(struct intel_connector *connector)
4623 {
4624         if (connector->get_hw_state(connector)) {
4625                 struct intel_encoder *encoder = connector->encoder;
4626                 struct drm_crtc *crtc;
4627                 bool encoder_enabled;
4628                 enum pipe pipe;
4629
4630                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4631                               connector->base.base.id,
4632                               drm_get_connector_name(&connector->base));
4633
4634                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4635                      "wrong connector dpms state\n");
4636                 WARN(connector->base.encoder != &encoder->base,
4637                      "active connector not linked to encoder\n");
4638                 WARN(!encoder->connectors_active,
4639                      "encoder->connectors_active not set\n");
4640
4641                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4642                 WARN(!encoder_enabled, "encoder not enabled\n");
4643                 if (WARN_ON(!encoder->base.crtc))
4644                         return;
4645
4646                 crtc = encoder->base.crtc;
4647
4648                 WARN(!crtc->enabled, "crtc not enabled\n");
4649                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4650                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4651                      "encoder active on the wrong pipe\n");
4652         }
4653 }
4654
4655 /* Even simpler default implementation, if there's really no special case to
4656  * consider. */
4657 void intel_connector_dpms(struct drm_connector *connector, int mode)
4658 {
4659         /* All the simple cases only support two dpms states. */
4660         if (mode != DRM_MODE_DPMS_ON)
4661                 mode = DRM_MODE_DPMS_OFF;
4662
4663         if (mode == connector->dpms)
4664                 return;
4665
4666         connector->dpms = mode;
4667
4668         /* Only need to change hw state when actually enabled */
4669         if (connector->encoder)
4670                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4671
4672         intel_modeset_check_state(connector->dev);
4673 }
4674
4675 /* Simple connector->get_hw_state implementation for encoders that support only
4676  * one connector and no cloning and hence the encoder state determines the state
4677  * of the connector. */
4678 bool intel_connector_get_hw_state(struct intel_connector *connector)
4679 {
4680         enum pipe pipe = 0;
4681         struct intel_encoder *encoder = connector->encoder;
4682
4683         return encoder->get_hw_state(encoder, &pipe);
4684 }
4685
4686 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4687                                      struct intel_crtc_config *pipe_config)
4688 {
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690         struct intel_crtc *pipe_B_crtc =
4691                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4692
4693         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4694                       pipe_name(pipe), pipe_config->fdi_lanes);
4695         if (pipe_config->fdi_lanes > 4) {
4696                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4697                               pipe_name(pipe), pipe_config->fdi_lanes);
4698                 return false;
4699         }
4700
4701         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4702                 if (pipe_config->fdi_lanes > 2) {
4703                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4704                                       pipe_config->fdi_lanes);
4705                         return false;
4706                 } else {
4707                         return true;
4708                 }
4709         }
4710
4711         if (INTEL_INFO(dev)->num_pipes == 2)
4712                 return true;
4713
4714         /* Ivybridge 3 pipe is really complicated */
4715         switch (pipe) {
4716         case PIPE_A:
4717                 return true;
4718         case PIPE_B:
4719                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4720                     pipe_config->fdi_lanes > 2) {
4721                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4722                                       pipe_name(pipe), pipe_config->fdi_lanes);
4723                         return false;
4724                 }
4725                 return true;
4726         case PIPE_C:
4727                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4728                     pipe_B_crtc->config.fdi_lanes <= 2) {
4729                         if (pipe_config->fdi_lanes > 2) {
4730                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4731                                               pipe_name(pipe), pipe_config->fdi_lanes);
4732                                 return false;
4733                         }
4734                 } else {
4735                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4736                         return false;
4737                 }
4738                 return true;
4739         default:
4740                 BUG();
4741         }
4742 }
4743
4744 #define RETRY 1
4745 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4746                                        struct intel_crtc_config *pipe_config)
4747 {
4748         struct drm_device *dev = intel_crtc->base.dev;
4749         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4750         int lane, link_bw, fdi_dotclock;
4751         bool setup_ok, needs_recompute = false;
4752
4753 retry:
4754         /* FDI is a binary signal running at ~2.7GHz, encoding
4755          * each output octet as 10 bits. The actual frequency
4756          * is stored as a divider into a 100MHz clock, and the
4757          * mode pixel clock is stored in units of 1KHz.
4758          * Hence the bw of each lane in terms of the mode signal
4759          * is:
4760          */
4761         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4762
4763         fdi_dotclock = adjusted_mode->crtc_clock;
4764
4765         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4766                                            pipe_config->pipe_bpp);
4767
4768         pipe_config->fdi_lanes = lane;
4769
4770         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4771                                link_bw, &pipe_config->fdi_m_n);
4772
4773         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4774                                             intel_crtc->pipe, pipe_config);
4775         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4776                 pipe_config->pipe_bpp -= 2*3;
4777                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4778                               pipe_config->pipe_bpp);
4779                 needs_recompute = true;
4780                 pipe_config->bw_constrained = true;
4781
4782                 goto retry;
4783         }
4784
4785         if (needs_recompute)
4786                 return RETRY;
4787
4788         return setup_ok ? 0 : -EINVAL;
4789 }
4790
4791 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4792                                    struct intel_crtc_config *pipe_config)
4793 {
4794         pipe_config->ips_enabled = i915.enable_ips &&
4795                                    hsw_crtc_supports_ips(crtc) &&
4796                                    pipe_config->pipe_bpp <= 24;
4797 }
4798
4799 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4800                                      struct intel_crtc_config *pipe_config)
4801 {
4802         struct drm_device *dev = crtc->base.dev;
4803         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4804
4805         /* FIXME should check pixel clock limits on all platforms */
4806         if (INTEL_INFO(dev)->gen < 4) {
4807                 struct drm_i915_private *dev_priv = dev->dev_private;
4808                 int clock_limit =
4809                         dev_priv->display.get_display_clock_speed(dev);
4810
4811                 /*
4812                  * Enable pixel doubling when the dot clock
4813                  * is > 90% of the (display) core speed.
4814                  *
4815                  * GDG double wide on either pipe,
4816                  * otherwise pipe A only.
4817                  */
4818                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4819                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4820                         clock_limit *= 2;
4821                         pipe_config->double_wide = true;
4822                 }
4823
4824                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4825                         return -EINVAL;
4826         }
4827
4828         /*
4829          * Pipe horizontal size must be even in:
4830          * - DVO ganged mode
4831          * - LVDS dual channel mode
4832          * - Double wide pipe
4833          */
4834         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4835              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4836                 pipe_config->pipe_src_w &= ~1;
4837
4838         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4839          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4840          */
4841         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4842                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4843                 return -EINVAL;
4844
4845         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4846                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4847         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4848                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4849                  * for lvds. */
4850                 pipe_config->pipe_bpp = 8*3;
4851         }
4852
4853         if (HAS_IPS(dev))
4854                 hsw_compute_ips_config(crtc, pipe_config);
4855
4856         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4857          * clock survives for now. */
4858         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4859                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4860
4861         if (pipe_config->has_pch_encoder)
4862                 return ironlake_fdi_compute_config(crtc, pipe_config);
4863
4864         return 0;
4865 }
4866
4867 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4868 {
4869         return 400000; /* FIXME */
4870 }
4871
4872 static int i945_get_display_clock_speed(struct drm_device *dev)
4873 {
4874         return 400000;
4875 }
4876
4877 static int i915_get_display_clock_speed(struct drm_device *dev)
4878 {
4879         return 333000;
4880 }
4881
4882 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4883 {
4884         return 200000;
4885 }
4886
4887 static int pnv_get_display_clock_speed(struct drm_device *dev)
4888 {
4889         u16 gcfgc = 0;
4890
4891         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4892
4893         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4894         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4895                 return 267000;
4896         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4897                 return 333000;
4898         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4899                 return 444000;
4900         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4901                 return 200000;
4902         default:
4903                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4904         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4905                 return 133000;
4906         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4907                 return 167000;
4908         }
4909 }
4910
4911 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4912 {
4913         u16 gcfgc = 0;
4914
4915         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4916
4917         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4918                 return 133000;
4919         else {
4920                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4921                 case GC_DISPLAY_CLOCK_333_MHZ:
4922                         return 333000;
4923                 default:
4924                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4925                         return 190000;
4926                 }
4927         }
4928 }
4929
4930 static int i865_get_display_clock_speed(struct drm_device *dev)
4931 {
4932         return 266000;
4933 }
4934
4935 static int i855_get_display_clock_speed(struct drm_device *dev)
4936 {
4937         u16 hpllcc = 0;
4938         /* Assume that the hardware is in the high speed state.  This
4939          * should be the default.
4940          */
4941         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4942         case GC_CLOCK_133_200:
4943         case GC_CLOCK_100_200:
4944                 return 200000;
4945         case GC_CLOCK_166_250:
4946                 return 250000;
4947         case GC_CLOCK_100_133:
4948                 return 133000;
4949         }
4950
4951         /* Shouldn't happen */
4952         return 0;
4953 }
4954
4955 static int i830_get_display_clock_speed(struct drm_device *dev)
4956 {
4957         return 133000;
4958 }
4959
4960 static void
4961 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4962 {
4963         while (*num > DATA_LINK_M_N_MASK ||
4964                *den > DATA_LINK_M_N_MASK) {
4965                 *num >>= 1;
4966                 *den >>= 1;
4967         }
4968 }
4969
4970 static void compute_m_n(unsigned int m, unsigned int n,
4971                         uint32_t *ret_m, uint32_t *ret_n)
4972 {
4973         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4974         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4975         intel_reduce_m_n_ratio(ret_m, ret_n);
4976 }
4977
4978 void
4979 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4980                        int pixel_clock, int link_clock,
4981                        struct intel_link_m_n *m_n)
4982 {
4983         m_n->tu = 64;
4984
4985         compute_m_n(bits_per_pixel * pixel_clock,
4986                     link_clock * nlanes * 8,
4987                     &m_n->gmch_m, &m_n->gmch_n);
4988
4989         compute_m_n(pixel_clock, link_clock,
4990                     &m_n->link_m, &m_n->link_n);
4991 }
4992
4993 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4994 {
4995         if (i915.panel_use_ssc >= 0)
4996                 return i915.panel_use_ssc != 0;
4997         return dev_priv->vbt.lvds_use_ssc
4998                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4999 }
5000
5001 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5002 {
5003         struct drm_device *dev = crtc->dev;
5004         struct drm_i915_private *dev_priv = dev->dev_private;
5005         int refclk;
5006
5007         if (IS_VALLEYVIEW(dev)) {
5008                 refclk = 100000;
5009         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5010             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5011                 refclk = dev_priv->vbt.lvds_ssc_freq;
5012                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5013         } else if (!IS_GEN2(dev)) {
5014                 refclk = 96000;
5015         } else {
5016                 refclk = 48000;
5017         }
5018
5019         return refclk;
5020 }
5021
5022 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5023 {
5024         return (1 << dpll->n) << 16 | dpll->m2;
5025 }
5026
5027 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5028 {
5029         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5030 }
5031
5032 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5033                                      intel_clock_t *reduced_clock)
5034 {
5035         struct drm_device *dev = crtc->base.dev;
5036         struct drm_i915_private *dev_priv = dev->dev_private;
5037         int pipe = crtc->pipe;
5038         u32 fp, fp2 = 0;
5039
5040         if (IS_PINEVIEW(dev)) {
5041                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5042                 if (reduced_clock)
5043                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5044         } else {
5045                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5046                 if (reduced_clock)
5047                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5048         }
5049
5050         I915_WRITE(FP0(pipe), fp);
5051         crtc->config.dpll_hw_state.fp0 = fp;
5052
5053         crtc->lowfreq_avail = false;
5054         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5055             reduced_clock && i915.powersave) {
5056                 I915_WRITE(FP1(pipe), fp2);
5057                 crtc->config.dpll_hw_state.fp1 = fp2;
5058                 crtc->lowfreq_avail = true;
5059         } else {
5060                 I915_WRITE(FP1(pipe), fp);
5061                 crtc->config.dpll_hw_state.fp1 = fp;
5062         }
5063 }
5064
5065 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5066                 pipe)
5067 {
5068         u32 reg_val;
5069
5070         /*
5071          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5072          * and set it to a reasonable value instead.
5073          */
5074         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5075         reg_val &= 0xffffff00;
5076         reg_val |= 0x00000030;
5077         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5078
5079         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5080         reg_val &= 0x8cffffff;
5081         reg_val = 0x8c000000;
5082         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5083
5084         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5085         reg_val &= 0xffffff00;
5086         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5087
5088         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5089         reg_val &= 0x00ffffff;
5090         reg_val |= 0xb0000000;
5091         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5092 }
5093
5094 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5095                                          struct intel_link_m_n *m_n)
5096 {
5097         struct drm_device *dev = crtc->base.dev;
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099         int pipe = crtc->pipe;
5100
5101         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5102         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5103         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5104         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5105 }
5106
5107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5108                                          struct intel_link_m_n *m_n)
5109 {
5110         struct drm_device *dev = crtc->base.dev;
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         int pipe = crtc->pipe;
5113         enum transcoder transcoder = crtc->config.cpu_transcoder;
5114
5115         if (INTEL_INFO(dev)->gen >= 5) {
5116                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5117                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5118                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5119                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5120         } else {
5121                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5122                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5123                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5124                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5125         }
5126 }
5127
5128 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5129 {
5130         if (crtc->config.has_pch_encoder)
5131                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5132         else
5133                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5134 }
5135
5136 static void vlv_update_pll(struct intel_crtc *crtc)
5137 {
5138         struct drm_device *dev = crtc->base.dev;
5139         struct drm_i915_private *dev_priv = dev->dev_private;
5140         int pipe = crtc->pipe;
5141         u32 dpll, mdiv;
5142         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5143         u32 coreclk, reg_val, dpll_md;
5144
5145         mutex_lock(&dev_priv->dpio_lock);
5146
5147         bestn = crtc->config.dpll.n;
5148         bestm1 = crtc->config.dpll.m1;
5149         bestm2 = crtc->config.dpll.m2;
5150         bestp1 = crtc->config.dpll.p1;
5151         bestp2 = crtc->config.dpll.p2;
5152
5153         /* See eDP HDMI DPIO driver vbios notes doc */
5154
5155         /* PLL B needs special handling */
5156         if (pipe)
5157                 vlv_pllb_recal_opamp(dev_priv, pipe);
5158
5159         /* Set up Tx target for periodic Rcomp update */
5160         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5161
5162         /* Disable target IRef on PLL */
5163         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5164         reg_val &= 0x00ffffff;
5165         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5166
5167         /* Disable fast lock */
5168         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5169
5170         /* Set idtafcrecal before PLL is enabled */
5171         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5172         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5173         mdiv |= ((bestn << DPIO_N_SHIFT));
5174         mdiv |= (1 << DPIO_K_SHIFT);
5175
5176         /*
5177          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5178          * but we don't support that).
5179          * Note: don't use the DAC post divider as it seems unstable.
5180          */
5181         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5182         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5183
5184         mdiv |= DPIO_ENABLE_CALIBRATION;
5185         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5186
5187         /* Set HBR and RBR LPF coefficients */
5188         if (crtc->config.port_clock == 162000 ||
5189             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5190             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5191                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5192                                  0x009f0003);
5193         else
5194                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5195                                  0x00d0000f);
5196
5197         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5198             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5199                 /* Use SSC source */
5200                 if (!pipe)
5201                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5202                                          0x0df40000);
5203                 else
5204                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5205                                          0x0df70000);
5206         } else { /* HDMI or VGA */
5207                 /* Use bend source */
5208                 if (!pipe)
5209                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5210                                          0x0df70000);
5211                 else
5212                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5213                                          0x0df40000);
5214         }
5215
5216         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5217         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5218         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5219             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5220                 coreclk |= 0x01000000;
5221         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5222
5223         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5224
5225         /*
5226          * Enable DPIO clock input. We should never disable the reference
5227          * clock for pipe B, since VGA hotplug / manual detection depends
5228          * on it.
5229          */
5230         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5231                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5232         /* We should never disable this, set it here for state tracking */
5233         if (pipe == PIPE_B)
5234                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5235         dpll |= DPLL_VCO_ENABLE;
5236         crtc->config.dpll_hw_state.dpll = dpll;
5237
5238         dpll_md = (crtc->config.pixel_multiplier - 1)
5239                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5240         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5241
5242         if (crtc->config.has_dp_encoder)
5243                 intel_dp_set_m_n(crtc);
5244
5245         mutex_unlock(&dev_priv->dpio_lock);
5246 }
5247
5248 static void i9xx_update_pll(struct intel_crtc *crtc,
5249                             intel_clock_t *reduced_clock,
5250                             int num_connectors)
5251 {
5252         struct drm_device *dev = crtc->base.dev;
5253         struct drm_i915_private *dev_priv = dev->dev_private;
5254         u32 dpll;
5255         bool is_sdvo;
5256         struct dpll *clock = &crtc->config.dpll;
5257
5258         i9xx_update_pll_dividers(crtc, reduced_clock);
5259
5260         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5261                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5262
5263         dpll = DPLL_VGA_MODE_DIS;
5264
5265         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5266                 dpll |= DPLLB_MODE_LVDS;
5267         else
5268                 dpll |= DPLLB_MODE_DAC_SERIAL;
5269
5270         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5271                 dpll |= (crtc->config.pixel_multiplier - 1)
5272                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5273         }
5274
5275         if (is_sdvo)
5276                 dpll |= DPLL_SDVO_HIGH_SPEED;
5277
5278         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5279                 dpll |= DPLL_SDVO_HIGH_SPEED;
5280
5281         /* compute bitmask from p1 value */
5282         if (IS_PINEVIEW(dev))
5283                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5284         else {
5285                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5286                 if (IS_G4X(dev) && reduced_clock)
5287                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5288         }
5289         switch (clock->p2) {
5290         case 5:
5291                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5292                 break;
5293         case 7:
5294                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5295                 break;
5296         case 10:
5297                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5298                 break;
5299         case 14:
5300                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5301                 break;
5302         }
5303         if (INTEL_INFO(dev)->gen >= 4)
5304                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5305
5306         if (crtc->config.sdvo_tv_clock)
5307                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5308         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5309                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5310                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5311         else
5312                 dpll |= PLL_REF_INPUT_DREFCLK;
5313
5314         dpll |= DPLL_VCO_ENABLE;
5315         crtc->config.dpll_hw_state.dpll = dpll;
5316
5317         if (INTEL_INFO(dev)->gen >= 4) {
5318                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5319                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5320                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5321         }
5322
5323         if (crtc->config.has_dp_encoder)
5324                 intel_dp_set_m_n(crtc);
5325 }
5326
5327 static void i8xx_update_pll(struct intel_crtc *crtc,
5328                             intel_clock_t *reduced_clock,
5329                             int num_connectors)
5330 {
5331         struct drm_device *dev = crtc->base.dev;
5332         struct drm_i915_private *dev_priv = dev->dev_private;
5333         u32 dpll;
5334         struct dpll *clock = &crtc->config.dpll;
5335
5336         i9xx_update_pll_dividers(crtc, reduced_clock);
5337
5338         dpll = DPLL_VGA_MODE_DIS;
5339
5340         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5341                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5342         } else {
5343                 if (clock->p1 == 2)
5344                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5345                 else
5346                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5347                 if (clock->p2 == 4)
5348                         dpll |= PLL_P2_DIVIDE_BY_4;
5349         }
5350
5351         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5352                 dpll |= DPLL_DVO_2X_MODE;
5353
5354         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5355                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5356                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5357         else
5358                 dpll |= PLL_REF_INPUT_DREFCLK;
5359
5360         dpll |= DPLL_VCO_ENABLE;
5361         crtc->config.dpll_hw_state.dpll = dpll;
5362 }
5363
5364 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5365 {
5366         struct drm_device *dev = intel_crtc->base.dev;
5367         struct drm_i915_private *dev_priv = dev->dev_private;
5368         enum pipe pipe = intel_crtc->pipe;
5369         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5370         struct drm_display_mode *adjusted_mode =
5371                 &intel_crtc->config.adjusted_mode;
5372         uint32_t crtc_vtotal, crtc_vblank_end;
5373         int vsyncshift = 0;
5374
5375         /* We need to be careful not to changed the adjusted mode, for otherwise
5376          * the hw state checker will get angry at the mismatch. */
5377         crtc_vtotal = adjusted_mode->crtc_vtotal;
5378         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5379
5380         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5381                 /* the chip adds 2 halflines automatically */
5382                 crtc_vtotal -= 1;
5383                 crtc_vblank_end -= 1;
5384
5385                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5386                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5387                 else
5388                         vsyncshift = adjusted_mode->crtc_hsync_start -
5389                                 adjusted_mode->crtc_htotal / 2;
5390                 if (vsyncshift < 0)
5391                         vsyncshift += adjusted_mode->crtc_htotal;
5392         }
5393
5394         if (INTEL_INFO(dev)->gen > 3)
5395                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5396
5397         I915_WRITE(HTOTAL(cpu_transcoder),
5398                    (adjusted_mode->crtc_hdisplay - 1) |
5399                    ((adjusted_mode->crtc_htotal - 1) << 16));
5400         I915_WRITE(HBLANK(cpu_transcoder),
5401                    (adjusted_mode->crtc_hblank_start - 1) |
5402                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5403         I915_WRITE(HSYNC(cpu_transcoder),
5404                    (adjusted_mode->crtc_hsync_start - 1) |
5405                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5406
5407         I915_WRITE(VTOTAL(cpu_transcoder),
5408                    (adjusted_mode->crtc_vdisplay - 1) |
5409                    ((crtc_vtotal - 1) << 16));
5410         I915_WRITE(VBLANK(cpu_transcoder),
5411                    (adjusted_mode->crtc_vblank_start - 1) |
5412                    ((crtc_vblank_end - 1) << 16));
5413         I915_WRITE(VSYNC(cpu_transcoder),
5414                    (adjusted_mode->crtc_vsync_start - 1) |
5415                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5416
5417         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5418          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5419          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5420          * bits. */
5421         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5422             (pipe == PIPE_B || pipe == PIPE_C))
5423                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5424
5425         /* pipesrc controls the size that is scaled from, which should
5426          * always be the user's requested size.
5427          */
5428         I915_WRITE(PIPESRC(pipe),
5429                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5430                    (intel_crtc->config.pipe_src_h - 1));
5431 }
5432
5433 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5434                                    struct intel_crtc_config *pipe_config)
5435 {
5436         struct drm_device *dev = crtc->base.dev;
5437         struct drm_i915_private *dev_priv = dev->dev_private;
5438         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5439         uint32_t tmp;
5440
5441         tmp = I915_READ(HTOTAL(cpu_transcoder));
5442         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5443         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5444         tmp = I915_READ(HBLANK(cpu_transcoder));
5445         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5446         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5447         tmp = I915_READ(HSYNC(cpu_transcoder));
5448         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5449         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5450
5451         tmp = I915_READ(VTOTAL(cpu_transcoder));
5452         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5453         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5454         tmp = I915_READ(VBLANK(cpu_transcoder));
5455         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5456         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5457         tmp = I915_READ(VSYNC(cpu_transcoder));
5458         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5459         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5460
5461         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5462                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5463                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5464                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5465         }
5466
5467         tmp = I915_READ(PIPESRC(crtc->pipe));
5468         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5469         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5470
5471         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5472         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5473 }
5474
5475 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5476                                  struct intel_crtc_config *pipe_config)
5477 {
5478         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5479         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5480         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5481         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5482
5483         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5484         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5485         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5486         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5487
5488         mode->flags = pipe_config->adjusted_mode.flags;
5489
5490         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5491         mode->flags |= pipe_config->adjusted_mode.flags;
5492 }
5493
5494 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5495 {
5496         struct drm_device *dev = intel_crtc->base.dev;
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498         uint32_t pipeconf;
5499
5500         pipeconf = 0;
5501
5502         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5503             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5504                 pipeconf |= PIPECONF_ENABLE;
5505
5506         if (intel_crtc->config.double_wide)
5507                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5508
5509         /* only g4x and later have fancy bpc/dither controls */
5510         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5511                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5512                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5513                         pipeconf |= PIPECONF_DITHER_EN |
5514                                     PIPECONF_DITHER_TYPE_SP;
5515
5516                 switch (intel_crtc->config.pipe_bpp) {
5517                 case 18:
5518                         pipeconf |= PIPECONF_6BPC;
5519                         break;
5520                 case 24:
5521                         pipeconf |= PIPECONF_8BPC;
5522                         break;
5523                 case 30:
5524                         pipeconf |= PIPECONF_10BPC;
5525                         break;
5526                 default:
5527                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5528                         BUG();
5529                 }
5530         }
5531
5532         if (HAS_PIPE_CXSR(dev)) {
5533                 if (intel_crtc->lowfreq_avail) {
5534                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5535                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5536                 } else {
5537                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5538                 }
5539         }
5540
5541         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5542                 if (INTEL_INFO(dev)->gen < 4 ||
5543                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5544                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5545                 else
5546                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5547         } else
5548                 pipeconf |= PIPECONF_PROGRESSIVE;
5549
5550         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5551                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5552
5553         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5554         POSTING_READ(PIPECONF(intel_crtc->pipe));
5555 }
5556
5557 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5558                               int x, int y,
5559                               struct drm_framebuffer *fb)
5560 {
5561         struct drm_device *dev = crtc->dev;
5562         struct drm_i915_private *dev_priv = dev->dev_private;
5563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5564         int pipe = intel_crtc->pipe;
5565         int plane = intel_crtc->plane;
5566         int refclk, num_connectors = 0;
5567         intel_clock_t clock, reduced_clock;
5568         u32 dspcntr;
5569         bool ok, has_reduced_clock = false;
5570         bool is_lvds = false, is_dsi = false;
5571         struct intel_encoder *encoder;
5572         const intel_limit_t *limit;
5573         int ret;
5574
5575         for_each_encoder_on_crtc(dev, crtc, encoder) {
5576                 switch (encoder->type) {
5577                 case INTEL_OUTPUT_LVDS:
5578                         is_lvds = true;
5579                         break;
5580                 case INTEL_OUTPUT_DSI:
5581                         is_dsi = true;
5582                         break;
5583                 }
5584
5585                 num_connectors++;
5586         }
5587
5588         if (is_dsi)
5589                 goto skip_dpll;
5590
5591         if (!intel_crtc->config.clock_set) {
5592                 refclk = i9xx_get_refclk(crtc, num_connectors);
5593
5594                 /*
5595                  * Returns a set of divisors for the desired target clock with
5596                  * the given refclk, or FALSE.  The returned values represent
5597                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5598                  * 2) / p1 / p2.
5599                  */
5600                 limit = intel_limit(crtc, refclk);
5601                 ok = dev_priv->display.find_dpll(limit, crtc,
5602                                                  intel_crtc->config.port_clock,
5603                                                  refclk, NULL, &clock);
5604                 if (!ok) {
5605                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5606                         return -EINVAL;
5607                 }
5608
5609                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5610                         /*
5611                          * Ensure we match the reduced clock's P to the target
5612                          * clock.  If the clocks don't match, we can't switch
5613                          * the display clock by using the FP0/FP1. In such case
5614                          * we will disable the LVDS downclock feature.
5615                          */
5616                         has_reduced_clock =
5617                                 dev_priv->display.find_dpll(limit, crtc,
5618                                                             dev_priv->lvds_downclock,
5619                                                             refclk, &clock,
5620                                                             &reduced_clock);
5621                 }
5622                 /* Compat-code for transition, will disappear. */
5623                 intel_crtc->config.dpll.n = clock.n;
5624                 intel_crtc->config.dpll.m1 = clock.m1;
5625                 intel_crtc->config.dpll.m2 = clock.m2;
5626                 intel_crtc->config.dpll.p1 = clock.p1;
5627                 intel_crtc->config.dpll.p2 = clock.p2;
5628         }
5629
5630         if (IS_GEN2(dev)) {
5631                 i8xx_update_pll(intel_crtc,
5632                                 has_reduced_clock ? &reduced_clock : NULL,
5633                                 num_connectors);
5634         } else if (IS_VALLEYVIEW(dev)) {
5635                 vlv_update_pll(intel_crtc);
5636         } else {
5637                 i9xx_update_pll(intel_crtc,
5638                                 has_reduced_clock ? &reduced_clock : NULL,
5639                                 num_connectors);
5640         }
5641
5642 skip_dpll:
5643         /* Set up the display plane register */
5644         dspcntr = DISPPLANE_GAMMA_ENABLE;
5645
5646         if (!IS_VALLEYVIEW(dev)) {
5647                 if (pipe == 0)
5648                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5649                 else
5650                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5651         }
5652
5653         intel_set_pipe_timings(intel_crtc);
5654
5655         /* pipesrc and dspsize control the size that is scaled from,
5656          * which should always be the user's requested size.
5657          */
5658         I915_WRITE(DSPSIZE(plane),
5659                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5660                    (intel_crtc->config.pipe_src_w - 1));
5661         I915_WRITE(DSPPOS(plane), 0);
5662
5663         i9xx_set_pipeconf(intel_crtc);
5664
5665         I915_WRITE(DSPCNTR(plane), dspcntr);
5666         POSTING_READ(DSPCNTR(plane));
5667
5668         ret = intel_pipe_set_base(crtc, x, y, fb);
5669
5670         return ret;
5671 }
5672
5673 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5674                                  struct intel_crtc_config *pipe_config)
5675 {
5676         struct drm_device *dev = crtc->base.dev;
5677         struct drm_i915_private *dev_priv = dev->dev_private;
5678         uint32_t tmp;
5679
5680         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5681                 return;
5682
5683         tmp = I915_READ(PFIT_CONTROL);
5684         if (!(tmp & PFIT_ENABLE))
5685                 return;
5686
5687         /* Check whether the pfit is attached to our pipe. */
5688         if (INTEL_INFO(dev)->gen < 4) {
5689                 if (crtc->pipe != PIPE_B)
5690                         return;
5691         } else {
5692                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5693                         return;
5694         }
5695
5696         pipe_config->gmch_pfit.control = tmp;
5697         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5698         if (INTEL_INFO(dev)->gen < 5)
5699                 pipe_config->gmch_pfit.lvds_border_bits =
5700                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5701 }
5702
5703 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5704                                struct intel_crtc_config *pipe_config)
5705 {
5706         struct drm_device *dev = crtc->base.dev;
5707         struct drm_i915_private *dev_priv = dev->dev_private;
5708         int pipe = pipe_config->cpu_transcoder;
5709         intel_clock_t clock;
5710         u32 mdiv;
5711         int refclk = 100000;
5712
5713         mutex_lock(&dev_priv->dpio_lock);
5714         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5715         mutex_unlock(&dev_priv->dpio_lock);
5716
5717         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5718         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5719         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5720         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5721         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5722
5723         vlv_clock(refclk, &clock);
5724
5725         /* clock.dot is the fast clock */
5726         pipe_config->port_clock = clock.dot / 5;
5727 }
5728
5729 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5730                                   struct intel_plane_config *plane_config)
5731 {
5732         struct drm_device *dev = crtc->base.dev;
5733         struct drm_i915_private *dev_priv = dev->dev_private;
5734         u32 val, base, offset;
5735         int pipe = crtc->pipe, plane = crtc->plane;
5736         int fourcc, pixel_format;
5737         int aligned_height;
5738
5739         crtc->base.fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5740         if (!crtc->base.fb) {
5741                 DRM_DEBUG_KMS("failed to alloc fb\n");
5742                 return;
5743         }
5744
5745         val = I915_READ(DSPCNTR(plane));
5746
5747         if (INTEL_INFO(dev)->gen >= 4)
5748                 if (val & DISPPLANE_TILED)
5749                         plane_config->tiled = true;
5750
5751         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5752         fourcc = intel_format_to_fourcc(pixel_format);
5753         crtc->base.fb->pixel_format = fourcc;
5754         crtc->base.fb->bits_per_pixel =
5755                 drm_format_plane_cpp(fourcc, 0) * 8;
5756
5757         if (INTEL_INFO(dev)->gen >= 4) {
5758                 if (plane_config->tiled)
5759                         offset = I915_READ(DSPTILEOFF(plane));
5760                 else
5761                         offset = I915_READ(DSPLINOFF(plane));
5762                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5763         } else {
5764                 base = I915_READ(DSPADDR(plane));
5765         }
5766         plane_config->base = base;
5767
5768         val = I915_READ(PIPESRC(pipe));
5769         crtc->base.fb->width = ((val >> 16) & 0xfff) + 1;
5770         crtc->base.fb->height = ((val >> 0) & 0xfff) + 1;
5771
5772         val = I915_READ(DSPSTRIDE(pipe));
5773         crtc->base.fb->pitches[0] = val & 0xffffff80;
5774
5775         aligned_height = intel_align_height(dev, crtc->base.fb->height,
5776                                             plane_config->tiled);
5777
5778         plane_config->size = ALIGN(crtc->base.fb->pitches[0] *
5779                                    aligned_height, PAGE_SIZE);
5780
5781         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5782                       pipe, plane, crtc->base.fb->width,
5783                       crtc->base.fb->height,
5784                       crtc->base.fb->bits_per_pixel, base,
5785                       crtc->base.fb->pitches[0],
5786                       plane_config->size);
5787
5788 }
5789
5790 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5791                                  struct intel_crtc_config *pipe_config)
5792 {
5793         struct drm_device *dev = crtc->base.dev;
5794         struct drm_i915_private *dev_priv = dev->dev_private;
5795         uint32_t tmp;
5796
5797         if (!intel_display_power_enabled(dev_priv,
5798                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5799                 return false;
5800
5801         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5802         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5803
5804         tmp = I915_READ(PIPECONF(crtc->pipe));
5805         if (!(tmp & PIPECONF_ENABLE))
5806                 return false;
5807
5808         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5809                 switch (tmp & PIPECONF_BPC_MASK) {
5810                 case PIPECONF_6BPC:
5811                         pipe_config->pipe_bpp = 18;
5812                         break;
5813                 case PIPECONF_8BPC:
5814                         pipe_config->pipe_bpp = 24;
5815                         break;
5816                 case PIPECONF_10BPC:
5817                         pipe_config->pipe_bpp = 30;
5818                         break;
5819                 default:
5820                         break;
5821                 }
5822         }
5823
5824         if (INTEL_INFO(dev)->gen < 4)
5825                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5826
5827         intel_get_pipe_timings(crtc, pipe_config);
5828
5829         i9xx_get_pfit_config(crtc, pipe_config);
5830
5831         if (INTEL_INFO(dev)->gen >= 4) {
5832                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5833                 pipe_config->pixel_multiplier =
5834                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5835                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5836                 pipe_config->dpll_hw_state.dpll_md = tmp;
5837         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5838                 tmp = I915_READ(DPLL(crtc->pipe));
5839                 pipe_config->pixel_multiplier =
5840                         ((tmp & SDVO_MULTIPLIER_MASK)
5841                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5842         } else {
5843                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5844                  * port and will be fixed up in the encoder->get_config
5845                  * function. */
5846                 pipe_config->pixel_multiplier = 1;
5847         }
5848         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5849         if (!IS_VALLEYVIEW(dev)) {
5850                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5851                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5852         } else {
5853                 /* Mask out read-only status bits. */
5854                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5855                                                      DPLL_PORTC_READY_MASK |
5856                                                      DPLL_PORTB_READY_MASK);
5857         }
5858
5859         if (IS_VALLEYVIEW(dev))
5860                 vlv_crtc_clock_get(crtc, pipe_config);
5861         else
5862                 i9xx_crtc_clock_get(crtc, pipe_config);
5863
5864         return true;
5865 }
5866
5867 static void ironlake_init_pch_refclk(struct drm_device *dev)
5868 {
5869         struct drm_i915_private *dev_priv = dev->dev_private;
5870         struct drm_mode_config *mode_config = &dev->mode_config;
5871         struct intel_encoder *encoder;
5872         u32 val, final;
5873         bool has_lvds = false;
5874         bool has_cpu_edp = false;
5875         bool has_panel = false;
5876         bool has_ck505 = false;
5877         bool can_ssc = false;
5878
5879         /* We need to take the global config into account */
5880         list_for_each_entry(encoder, &mode_config->encoder_list,
5881                             base.head) {
5882                 switch (encoder->type) {
5883                 case INTEL_OUTPUT_LVDS:
5884                         has_panel = true;
5885                         has_lvds = true;
5886                         break;
5887                 case INTEL_OUTPUT_EDP:
5888                         has_panel = true;
5889                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5890                                 has_cpu_edp = true;
5891                         break;
5892                 }
5893         }
5894
5895         if (HAS_PCH_IBX(dev)) {
5896                 has_ck505 = dev_priv->vbt.display_clock_mode;
5897                 can_ssc = has_ck505;
5898         } else {
5899                 has_ck505 = false;
5900                 can_ssc = true;
5901         }
5902
5903         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5904                       has_panel, has_lvds, has_ck505);
5905
5906         /* Ironlake: try to setup display ref clock before DPLL
5907          * enabling. This is only under driver's control after
5908          * PCH B stepping, previous chipset stepping should be
5909          * ignoring this setting.
5910          */
5911         val = I915_READ(PCH_DREF_CONTROL);
5912
5913         /* As we must carefully and slowly disable/enable each source in turn,
5914          * compute the final state we want first and check if we need to
5915          * make any changes at all.
5916          */
5917         final = val;
5918         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5919         if (has_ck505)
5920                 final |= DREF_NONSPREAD_CK505_ENABLE;
5921         else
5922                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5923
5924         final &= ~DREF_SSC_SOURCE_MASK;
5925         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5926         final &= ~DREF_SSC1_ENABLE;
5927
5928         if (has_panel) {
5929                 final |= DREF_SSC_SOURCE_ENABLE;
5930
5931                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5932                         final |= DREF_SSC1_ENABLE;
5933
5934                 if (has_cpu_edp) {
5935                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5936                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5937                         else
5938                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5939                 } else
5940                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5941         } else {
5942                 final |= DREF_SSC_SOURCE_DISABLE;
5943                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5944         }
5945
5946         if (final == val)
5947                 return;
5948
5949         /* Always enable nonspread source */
5950         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5951
5952         if (has_ck505)
5953                 val |= DREF_NONSPREAD_CK505_ENABLE;
5954         else
5955                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5956
5957         if (has_panel) {
5958                 val &= ~DREF_SSC_SOURCE_MASK;
5959                 val |= DREF_SSC_SOURCE_ENABLE;
5960
5961                 /* SSC must be turned on before enabling the CPU output  */
5962                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5963                         DRM_DEBUG_KMS("Using SSC on panel\n");
5964                         val |= DREF_SSC1_ENABLE;
5965                 } else
5966                         val &= ~DREF_SSC1_ENABLE;
5967
5968                 /* Get SSC going before enabling the outputs */
5969                 I915_WRITE(PCH_DREF_CONTROL, val);
5970                 POSTING_READ(PCH_DREF_CONTROL);
5971                 udelay(200);
5972
5973                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5974
5975                 /* Enable CPU source on CPU attached eDP */
5976                 if (has_cpu_edp) {
5977                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5978                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5979                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5980                         }
5981                         else
5982                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5983                 } else
5984                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5985
5986                 I915_WRITE(PCH_DREF_CONTROL, val);
5987                 POSTING_READ(PCH_DREF_CONTROL);
5988                 udelay(200);
5989         } else {
5990                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5991
5992                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5993
5994                 /* Turn off CPU output */
5995                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5996
5997                 I915_WRITE(PCH_DREF_CONTROL, val);
5998                 POSTING_READ(PCH_DREF_CONTROL);
5999                 udelay(200);
6000
6001                 /* Turn off the SSC source */
6002                 val &= ~DREF_SSC_SOURCE_MASK;
6003                 val |= DREF_SSC_SOURCE_DISABLE;
6004
6005                 /* Turn off SSC1 */
6006                 val &= ~DREF_SSC1_ENABLE;
6007
6008                 I915_WRITE(PCH_DREF_CONTROL, val);
6009                 POSTING_READ(PCH_DREF_CONTROL);
6010                 udelay(200);
6011         }
6012
6013         BUG_ON(val != final);
6014 }
6015
6016 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6017 {
6018         uint32_t tmp;
6019
6020         tmp = I915_READ(SOUTH_CHICKEN2);
6021         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6022         I915_WRITE(SOUTH_CHICKEN2, tmp);
6023
6024         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6025                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6026                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6027
6028         tmp = I915_READ(SOUTH_CHICKEN2);
6029         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6030         I915_WRITE(SOUTH_CHICKEN2, tmp);
6031
6032         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6033                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6034                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6035 }
6036
6037 /* WaMPhyProgramming:hsw */
6038 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6039 {
6040         uint32_t tmp;
6041
6042         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6043         tmp &= ~(0xFF << 24);
6044         tmp |= (0x12 << 24);
6045         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6046
6047         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6048         tmp |= (1 << 11);
6049         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6050
6051         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6052         tmp |= (1 << 11);
6053         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6054
6055         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6056         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6057         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6058
6059         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6060         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6061         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6062
6063         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6064         tmp &= ~(7 << 13);
6065         tmp |= (5 << 13);
6066         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6067
6068         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6069         tmp &= ~(7 << 13);
6070         tmp |= (5 << 13);
6071         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6072
6073         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6074         tmp &= ~0xFF;
6075         tmp |= 0x1C;
6076         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6077
6078         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6079         tmp &= ~0xFF;
6080         tmp |= 0x1C;
6081         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6082
6083         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6084         tmp &= ~(0xFF << 16);
6085         tmp |= (0x1C << 16);
6086         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6087
6088         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6089         tmp &= ~(0xFF << 16);
6090         tmp |= (0x1C << 16);
6091         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6092
6093         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6094         tmp |= (1 << 27);
6095         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6096
6097         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6098         tmp |= (1 << 27);
6099         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6100
6101         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6102         tmp &= ~(0xF << 28);
6103         tmp |= (4 << 28);
6104         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6105
6106         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6107         tmp &= ~(0xF << 28);
6108         tmp |= (4 << 28);
6109         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6110 }
6111
6112 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6113  * Programming" based on the parameters passed:
6114  * - Sequence to enable CLKOUT_DP
6115  * - Sequence to enable CLKOUT_DP without spread
6116  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6117  */
6118 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6119                                  bool with_fdi)
6120 {
6121         struct drm_i915_private *dev_priv = dev->dev_private;
6122         uint32_t reg, tmp;
6123
6124         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6125                 with_spread = true;
6126         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6127                  with_fdi, "LP PCH doesn't have FDI\n"))
6128                 with_fdi = false;
6129
6130         mutex_lock(&dev_priv->dpio_lock);
6131
6132         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6133         tmp &= ~SBI_SSCCTL_DISABLE;
6134         tmp |= SBI_SSCCTL_PATHALT;
6135         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6136
6137         udelay(24);
6138
6139         if (with_spread) {
6140                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6141                 tmp &= ~SBI_SSCCTL_PATHALT;
6142                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6143
6144                 if (with_fdi) {
6145                         lpt_reset_fdi_mphy(dev_priv);
6146                         lpt_program_fdi_mphy(dev_priv);
6147                 }
6148         }
6149
6150         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6151                SBI_GEN0 : SBI_DBUFF0;
6152         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6153         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6154         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6155
6156         mutex_unlock(&dev_priv->dpio_lock);
6157 }
6158
6159 /* Sequence to disable CLKOUT_DP */
6160 static void lpt_disable_clkout_dp(struct drm_device *dev)
6161 {
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163         uint32_t reg, tmp;
6164
6165         mutex_lock(&dev_priv->dpio_lock);
6166
6167         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6168                SBI_GEN0 : SBI_DBUFF0;
6169         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6170         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6171         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6172
6173         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6174         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6175                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6176                         tmp |= SBI_SSCCTL_PATHALT;
6177                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6178                         udelay(32);
6179                 }
6180                 tmp |= SBI_SSCCTL_DISABLE;
6181                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6182         }
6183
6184         mutex_unlock(&dev_priv->dpio_lock);
6185 }
6186
6187 static void lpt_init_pch_refclk(struct drm_device *dev)
6188 {
6189         struct drm_mode_config *mode_config = &dev->mode_config;
6190         struct intel_encoder *encoder;
6191         bool has_vga = false;
6192
6193         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6194                 switch (encoder->type) {
6195                 case INTEL_OUTPUT_ANALOG:
6196                         has_vga = true;
6197                         break;
6198                 }
6199         }
6200
6201         if (has_vga)
6202                 lpt_enable_clkout_dp(dev, true, true);
6203         else
6204                 lpt_disable_clkout_dp(dev);
6205 }
6206
6207 /*
6208  * Initialize reference clocks when the driver loads
6209  */
6210 void intel_init_pch_refclk(struct drm_device *dev)
6211 {
6212         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6213                 ironlake_init_pch_refclk(dev);
6214         else if (HAS_PCH_LPT(dev))
6215                 lpt_init_pch_refclk(dev);
6216 }
6217
6218 static int ironlake_get_refclk(struct drm_crtc *crtc)
6219 {
6220         struct drm_device *dev = crtc->dev;
6221         struct drm_i915_private *dev_priv = dev->dev_private;
6222         struct intel_encoder *encoder;
6223         int num_connectors = 0;
6224         bool is_lvds = false;
6225
6226         for_each_encoder_on_crtc(dev, crtc, encoder) {
6227                 switch (encoder->type) {
6228                 case INTEL_OUTPUT_LVDS:
6229                         is_lvds = true;
6230                         break;
6231                 }
6232                 num_connectors++;
6233         }
6234
6235         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6236                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6237                               dev_priv->vbt.lvds_ssc_freq);
6238                 return dev_priv->vbt.lvds_ssc_freq;
6239         }
6240
6241         return 120000;
6242 }
6243
6244 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6245 {
6246         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6248         int pipe = intel_crtc->pipe;
6249         uint32_t val;
6250
6251         val = 0;
6252
6253         switch (intel_crtc->config.pipe_bpp) {
6254         case 18:
6255                 val |= PIPECONF_6BPC;
6256                 break;
6257         case 24:
6258                 val |= PIPECONF_8BPC;
6259                 break;
6260         case 30:
6261                 val |= PIPECONF_10BPC;
6262                 break;
6263         case 36:
6264                 val |= PIPECONF_12BPC;
6265                 break;
6266         default:
6267                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6268                 BUG();
6269         }
6270
6271         if (intel_crtc->config.dither)
6272                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6273
6274         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6275                 val |= PIPECONF_INTERLACED_ILK;
6276         else
6277                 val |= PIPECONF_PROGRESSIVE;
6278
6279         if (intel_crtc->config.limited_color_range)
6280                 val |= PIPECONF_COLOR_RANGE_SELECT;
6281
6282         I915_WRITE(PIPECONF(pipe), val);
6283         POSTING_READ(PIPECONF(pipe));
6284 }
6285
6286 /*
6287  * Set up the pipe CSC unit.
6288  *
6289  * Currently only full range RGB to limited range RGB conversion
6290  * is supported, but eventually this should handle various
6291  * RGB<->YCbCr scenarios as well.
6292  */
6293 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6294 {
6295         struct drm_device *dev = crtc->dev;
6296         struct drm_i915_private *dev_priv = dev->dev_private;
6297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298         int pipe = intel_crtc->pipe;
6299         uint16_t coeff = 0x7800; /* 1.0 */
6300
6301         /*
6302          * TODO: Check what kind of values actually come out of the pipe
6303          * with these coeff/postoff values and adjust to get the best
6304          * accuracy. Perhaps we even need to take the bpc value into
6305          * consideration.
6306          */
6307
6308         if (intel_crtc->config.limited_color_range)
6309                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6310
6311         /*
6312          * GY/GU and RY/RU should be the other way around according
6313          * to BSpec, but reality doesn't agree. Just set them up in
6314          * a way that results in the correct picture.
6315          */
6316         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6317         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6318
6319         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6320         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6321
6322         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6323         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6324
6325         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6326         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6327         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6328
6329         if (INTEL_INFO(dev)->gen > 6) {
6330                 uint16_t postoff = 0;
6331
6332                 if (intel_crtc->config.limited_color_range)
6333                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6334
6335                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6336                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6337                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6338
6339                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6340         } else {
6341                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6342
6343                 if (intel_crtc->config.limited_color_range)
6344                         mode |= CSC_BLACK_SCREEN_OFFSET;
6345
6346                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6347         }
6348 }
6349
6350 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6351 {
6352         struct drm_device *dev = crtc->dev;
6353         struct drm_i915_private *dev_priv = dev->dev_private;
6354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355         enum pipe pipe = intel_crtc->pipe;
6356         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6357         uint32_t val;
6358
6359         val = 0;
6360
6361         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6362                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6363
6364         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6365                 val |= PIPECONF_INTERLACED_ILK;
6366         else
6367                 val |= PIPECONF_PROGRESSIVE;
6368
6369         I915_WRITE(PIPECONF(cpu_transcoder), val);
6370         POSTING_READ(PIPECONF(cpu_transcoder));
6371
6372         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6373         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6374
6375         if (IS_BROADWELL(dev)) {
6376                 val = 0;
6377
6378                 switch (intel_crtc->config.pipe_bpp) {
6379                 case 18:
6380                         val |= PIPEMISC_DITHER_6_BPC;
6381                         break;
6382                 case 24:
6383                         val |= PIPEMISC_DITHER_8_BPC;
6384                         break;
6385                 case 30:
6386                         val |= PIPEMISC_DITHER_10_BPC;
6387                         break;
6388                 case 36:
6389                         val |= PIPEMISC_DITHER_12_BPC;
6390                         break;
6391                 default:
6392                         /* Case prevented by pipe_config_set_bpp. */
6393                         BUG();
6394                 }
6395
6396                 if (intel_crtc->config.dither)
6397                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6398
6399                 I915_WRITE(PIPEMISC(pipe), val);
6400         }
6401 }
6402
6403 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6404                                     intel_clock_t *clock,
6405                                     bool *has_reduced_clock,
6406                                     intel_clock_t *reduced_clock)
6407 {
6408         struct drm_device *dev = crtc->dev;
6409         struct drm_i915_private *dev_priv = dev->dev_private;
6410         struct intel_encoder *intel_encoder;
6411         int refclk;
6412         const intel_limit_t *limit;
6413         bool ret, is_lvds = false;
6414
6415         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6416                 switch (intel_encoder->type) {
6417                 case INTEL_OUTPUT_LVDS:
6418                         is_lvds = true;
6419                         break;
6420                 }
6421         }
6422
6423         refclk = ironlake_get_refclk(crtc);
6424
6425         /*
6426          * Returns a set of divisors for the desired target clock with the given
6427          * refclk, or FALSE.  The returned values represent the clock equation:
6428          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6429          */
6430         limit = intel_limit(crtc, refclk);
6431         ret = dev_priv->display.find_dpll(limit, crtc,
6432                                           to_intel_crtc(crtc)->config.port_clock,
6433                                           refclk, NULL, clock);
6434         if (!ret)
6435                 return false;
6436
6437         if (is_lvds && dev_priv->lvds_downclock_avail) {
6438                 /*
6439                  * Ensure we match the reduced clock's P to the target clock.
6440                  * If the clocks don't match, we can't switch the display clock
6441                  * by using the FP0/FP1. In such case we will disable the LVDS
6442                  * downclock feature.
6443                 */
6444                 *has_reduced_clock =
6445                         dev_priv->display.find_dpll(limit, crtc,
6446                                                     dev_priv->lvds_downclock,
6447                                                     refclk, clock,
6448                                                     reduced_clock);
6449         }
6450
6451         return true;
6452 }
6453
6454 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6455 {
6456         /*
6457          * Account for spread spectrum to avoid
6458          * oversubscribing the link. Max center spread
6459          * is 2.5%; use 5% for safety's sake.
6460          */
6461         u32 bps = target_clock * bpp * 21 / 20;
6462         return DIV_ROUND_UP(bps, link_bw * 8);
6463 }
6464
6465 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6466 {
6467         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6468 }
6469
6470 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6471                                       u32 *fp,
6472                                       intel_clock_t *reduced_clock, u32 *fp2)
6473 {
6474         struct drm_crtc *crtc = &intel_crtc->base;
6475         struct drm_device *dev = crtc->dev;
6476         struct drm_i915_private *dev_priv = dev->dev_private;
6477         struct intel_encoder *intel_encoder;
6478         uint32_t dpll;
6479         int factor, num_connectors = 0;
6480         bool is_lvds = false, is_sdvo = false;
6481
6482         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6483                 switch (intel_encoder->type) {
6484                 case INTEL_OUTPUT_LVDS:
6485                         is_lvds = true;
6486                         break;
6487                 case INTEL_OUTPUT_SDVO:
6488                 case INTEL_OUTPUT_HDMI:
6489                         is_sdvo = true;
6490                         break;
6491                 }
6492
6493                 num_connectors++;
6494         }
6495
6496         /* Enable autotuning of the PLL clock (if permissible) */
6497         factor = 21;
6498         if (is_lvds) {
6499                 if ((intel_panel_use_ssc(dev_priv) &&
6500                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6501                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6502                         factor = 25;
6503         } else if (intel_crtc->config.sdvo_tv_clock)
6504                 factor = 20;
6505
6506         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6507                 *fp |= FP_CB_TUNE;
6508
6509         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6510                 *fp2 |= FP_CB_TUNE;
6511
6512         dpll = 0;
6513
6514         if (is_lvds)
6515                 dpll |= DPLLB_MODE_LVDS;
6516         else
6517                 dpll |= DPLLB_MODE_DAC_SERIAL;
6518
6519         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6520                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6521
6522         if (is_sdvo)
6523                 dpll |= DPLL_SDVO_HIGH_SPEED;
6524         if (intel_crtc->config.has_dp_encoder)
6525                 dpll |= DPLL_SDVO_HIGH_SPEED;
6526
6527         /* compute bitmask from p1 value */
6528         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6529         /* also FPA1 */
6530         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6531
6532         switch (intel_crtc->config.dpll.p2) {
6533         case 5:
6534                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6535                 break;
6536         case 7:
6537                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6538                 break;
6539         case 10:
6540                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6541                 break;
6542         case 14:
6543                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6544                 break;
6545         }
6546
6547         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6548                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6549         else
6550                 dpll |= PLL_REF_INPUT_DREFCLK;
6551
6552         return dpll | DPLL_VCO_ENABLE;
6553 }
6554
6555 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6556                                   int x, int y,
6557                                   struct drm_framebuffer *fb)
6558 {
6559         struct drm_device *dev = crtc->dev;
6560         struct drm_i915_private *dev_priv = dev->dev_private;
6561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6562         int pipe = intel_crtc->pipe;
6563         int plane = intel_crtc->plane;
6564         int num_connectors = 0;
6565         intel_clock_t clock, reduced_clock;
6566         u32 dpll = 0, fp = 0, fp2 = 0;
6567         bool ok, has_reduced_clock = false;
6568         bool is_lvds = false;
6569         struct intel_encoder *encoder;
6570         struct intel_shared_dpll *pll;
6571         int ret;
6572
6573         for_each_encoder_on_crtc(dev, crtc, encoder) {
6574                 switch (encoder->type) {
6575                 case INTEL_OUTPUT_LVDS:
6576                         is_lvds = true;
6577                         break;
6578                 }
6579
6580                 num_connectors++;
6581         }
6582
6583         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6584              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6585
6586         ok = ironlake_compute_clocks(crtc, &clock,
6587                                      &has_reduced_clock, &reduced_clock);
6588         if (!ok && !intel_crtc->config.clock_set) {
6589                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6590                 return -EINVAL;
6591         }
6592         /* Compat-code for transition, will disappear. */
6593         if (!intel_crtc->config.clock_set) {
6594                 intel_crtc->config.dpll.n = clock.n;
6595                 intel_crtc->config.dpll.m1 = clock.m1;
6596                 intel_crtc->config.dpll.m2 = clock.m2;
6597                 intel_crtc->config.dpll.p1 = clock.p1;
6598                 intel_crtc->config.dpll.p2 = clock.p2;
6599         }
6600
6601         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6602         if (intel_crtc->config.has_pch_encoder) {
6603                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6604                 if (has_reduced_clock)
6605                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6606
6607                 dpll = ironlake_compute_dpll(intel_crtc,
6608                                              &fp, &reduced_clock,
6609                                              has_reduced_clock ? &fp2 : NULL);
6610
6611                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6612                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6613                 if (has_reduced_clock)
6614                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6615                 else
6616                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6617
6618                 pll = intel_get_shared_dpll(intel_crtc);
6619                 if (pll == NULL) {
6620                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6621                                          pipe_name(pipe));
6622                         return -EINVAL;
6623                 }
6624         } else
6625                 intel_put_shared_dpll(intel_crtc);
6626
6627         if (intel_crtc->config.has_dp_encoder)
6628                 intel_dp_set_m_n(intel_crtc);
6629
6630         if (is_lvds && has_reduced_clock && i915.powersave)
6631                 intel_crtc->lowfreq_avail = true;
6632         else
6633                 intel_crtc->lowfreq_avail = false;
6634
6635         intel_set_pipe_timings(intel_crtc);
6636
6637         if (intel_crtc->config.has_pch_encoder) {
6638                 intel_cpu_transcoder_set_m_n(intel_crtc,
6639                                              &intel_crtc->config.fdi_m_n);
6640         }
6641
6642         ironlake_set_pipeconf(crtc);
6643
6644         /* Set up the display plane register */
6645         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6646         POSTING_READ(DSPCNTR(plane));
6647
6648         ret = intel_pipe_set_base(crtc, x, y, fb);
6649
6650         return ret;
6651 }
6652
6653 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6654                                          struct intel_link_m_n *m_n)
6655 {
6656         struct drm_device *dev = crtc->base.dev;
6657         struct drm_i915_private *dev_priv = dev->dev_private;
6658         enum pipe pipe = crtc->pipe;
6659
6660         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6661         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6662         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6663                 & ~TU_SIZE_MASK;
6664         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6665         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6666                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6667 }
6668
6669 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6670                                          enum transcoder transcoder,
6671                                          struct intel_link_m_n *m_n)
6672 {
6673         struct drm_device *dev = crtc->base.dev;
6674         struct drm_i915_private *dev_priv = dev->dev_private;
6675         enum pipe pipe = crtc->pipe;
6676
6677         if (INTEL_INFO(dev)->gen >= 5) {
6678                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6679                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6680                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6681                         & ~TU_SIZE_MASK;
6682                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6683                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6684                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6685         } else {
6686                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6687                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6688                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6689                         & ~TU_SIZE_MASK;
6690                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6691                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6692                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6693         }
6694 }
6695
6696 void intel_dp_get_m_n(struct intel_crtc *crtc,
6697                       struct intel_crtc_config *pipe_config)
6698 {
6699         if (crtc->config.has_pch_encoder)
6700                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6701         else
6702                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6703                                              &pipe_config->dp_m_n);
6704 }
6705
6706 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6707                                         struct intel_crtc_config *pipe_config)
6708 {
6709         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6710                                      &pipe_config->fdi_m_n);
6711 }
6712
6713 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6714                                      struct intel_crtc_config *pipe_config)
6715 {
6716         struct drm_device *dev = crtc->base.dev;
6717         struct drm_i915_private *dev_priv = dev->dev_private;
6718         uint32_t tmp;
6719
6720         tmp = I915_READ(PF_CTL(crtc->pipe));
6721
6722         if (tmp & PF_ENABLE) {
6723                 pipe_config->pch_pfit.enabled = true;
6724                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6725                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6726
6727                 /* We currently do not free assignements of panel fitters on
6728                  * ivb/hsw (since we don't use the higher upscaling modes which
6729                  * differentiates them) so just WARN about this case for now. */
6730                 if (IS_GEN7(dev)) {
6731                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6732                                 PF_PIPE_SEL_IVB(crtc->pipe));
6733                 }
6734         }
6735 }
6736
6737 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6738                                       struct intel_plane_config *plane_config)
6739 {
6740         struct drm_device *dev = crtc->base.dev;
6741         struct drm_i915_private *dev_priv = dev->dev_private;
6742         u32 val, base, offset;
6743         int pipe = crtc->pipe, plane = crtc->plane;
6744         int fourcc, pixel_format;
6745         int aligned_height;
6746
6747         crtc->base.fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6748         if (!crtc->base.fb) {
6749                 DRM_DEBUG_KMS("failed to alloc fb\n");
6750                 return;
6751         }
6752
6753         val = I915_READ(DSPCNTR(plane));
6754
6755         if (INTEL_INFO(dev)->gen >= 4)
6756                 if (val & DISPPLANE_TILED)
6757                         plane_config->tiled = true;
6758
6759         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6760         fourcc = intel_format_to_fourcc(pixel_format);
6761         crtc->base.fb->pixel_format = fourcc;
6762         crtc->base.fb->bits_per_pixel =
6763                 drm_format_plane_cpp(fourcc, 0) * 8;
6764
6765         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6766         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6767                 offset = I915_READ(DSPOFFSET(plane));
6768         } else {
6769                 if (plane_config->tiled)
6770                         offset = I915_READ(DSPTILEOFF(plane));
6771                 else
6772                         offset = I915_READ(DSPLINOFF(plane));
6773         }
6774         plane_config->base = base;
6775
6776         val = I915_READ(PIPESRC(pipe));
6777         crtc->base.fb->width = ((val >> 16) & 0xfff) + 1;
6778         crtc->base.fb->height = ((val >> 0) & 0xfff) + 1;
6779
6780         val = I915_READ(DSPSTRIDE(pipe));
6781         crtc->base.fb->pitches[0] = val & 0xffffff80;
6782
6783         aligned_height = intel_align_height(dev, crtc->base.fb->height,
6784                                             plane_config->tiled);
6785
6786         plane_config->size = ALIGN(crtc->base.fb->pitches[0] *
6787                                    aligned_height, PAGE_SIZE);
6788
6789         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6790                       pipe, plane, crtc->base.fb->width,
6791                       crtc->base.fb->height,
6792                       crtc->base.fb->bits_per_pixel, base,
6793                       crtc->base.fb->pitches[0],
6794                       plane_config->size);
6795 }
6796
6797 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6798                                      struct intel_crtc_config *pipe_config)
6799 {
6800         struct drm_device *dev = crtc->base.dev;
6801         struct drm_i915_private *dev_priv = dev->dev_private;
6802         uint32_t tmp;
6803
6804         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6805         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6806
6807         tmp = I915_READ(PIPECONF(crtc->pipe));
6808         if (!(tmp & PIPECONF_ENABLE))
6809                 return false;
6810
6811         switch (tmp & PIPECONF_BPC_MASK) {
6812         case PIPECONF_6BPC:
6813                 pipe_config->pipe_bpp = 18;
6814                 break;
6815         case PIPECONF_8BPC:
6816                 pipe_config->pipe_bpp = 24;
6817                 break;
6818         case PIPECONF_10BPC:
6819                 pipe_config->pipe_bpp = 30;
6820                 break;
6821         case PIPECONF_12BPC:
6822                 pipe_config->pipe_bpp = 36;
6823                 break;
6824         default:
6825                 break;
6826         }
6827
6828         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6829                 struct intel_shared_dpll *pll;
6830
6831                 pipe_config->has_pch_encoder = true;
6832
6833                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6834                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6835                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6836
6837                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6838
6839                 if (HAS_PCH_IBX(dev_priv->dev)) {
6840                         pipe_config->shared_dpll =
6841                                 (enum intel_dpll_id) crtc->pipe;
6842                 } else {
6843                         tmp = I915_READ(PCH_DPLL_SEL);
6844                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6845                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6846                         else
6847                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6848                 }
6849
6850                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6851
6852                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6853                                            &pipe_config->dpll_hw_state));
6854
6855                 tmp = pipe_config->dpll_hw_state.dpll;
6856                 pipe_config->pixel_multiplier =
6857                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6858                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6859
6860                 ironlake_pch_clock_get(crtc, pipe_config);
6861         } else {
6862                 pipe_config->pixel_multiplier = 1;
6863         }
6864
6865         intel_get_pipe_timings(crtc, pipe_config);
6866
6867         ironlake_get_pfit_config(crtc, pipe_config);
6868
6869         return true;
6870 }
6871
6872 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6873 {
6874         struct drm_device *dev = dev_priv->dev;
6875         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6876         struct intel_crtc *crtc;
6877         unsigned long irqflags;
6878         uint32_t val;
6879
6880         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6881                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6882                      pipe_name(crtc->pipe));
6883
6884         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6885         WARN(plls->spll_refcount, "SPLL enabled\n");
6886         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6887         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6888         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6889         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6890              "CPU PWM1 enabled\n");
6891         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6892              "CPU PWM2 enabled\n");
6893         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6894              "PCH PWM1 enabled\n");
6895         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6896              "Utility pin enabled\n");
6897         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6898
6899         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6900         val = I915_READ(DEIMR);
6901         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6902              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6903         val = I915_READ(SDEIMR);
6904         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6905              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6906         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6907 }
6908
6909 /*
6910  * This function implements pieces of two sequences from BSpec:
6911  * - Sequence for display software to disable LCPLL
6912  * - Sequence for display software to allow package C8+
6913  * The steps implemented here are just the steps that actually touch the LCPLL
6914  * register. Callers should take care of disabling all the display engine
6915  * functions, doing the mode unset, fixing interrupts, etc.
6916  */
6917 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6918                               bool switch_to_fclk, bool allow_power_down)
6919 {
6920         uint32_t val;
6921
6922         assert_can_disable_lcpll(dev_priv);
6923
6924         val = I915_READ(LCPLL_CTL);
6925
6926         if (switch_to_fclk) {
6927                 val |= LCPLL_CD_SOURCE_FCLK;
6928                 I915_WRITE(LCPLL_CTL, val);
6929
6930                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6931                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6932                         DRM_ERROR("Switching to FCLK failed\n");
6933
6934                 val = I915_READ(LCPLL_CTL);
6935         }
6936
6937         val |= LCPLL_PLL_DISABLE;
6938         I915_WRITE(LCPLL_CTL, val);
6939         POSTING_READ(LCPLL_CTL);
6940
6941         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6942                 DRM_ERROR("LCPLL still locked\n");
6943
6944         val = I915_READ(D_COMP);
6945         val |= D_COMP_COMP_DISABLE;
6946         mutex_lock(&dev_priv->rps.hw_lock);
6947         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6948                 DRM_ERROR("Failed to disable D_COMP\n");
6949         mutex_unlock(&dev_priv->rps.hw_lock);
6950         POSTING_READ(D_COMP);
6951         ndelay(100);
6952
6953         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6954                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6955
6956         if (allow_power_down) {
6957                 val = I915_READ(LCPLL_CTL);
6958                 val |= LCPLL_POWER_DOWN_ALLOW;
6959                 I915_WRITE(LCPLL_CTL, val);
6960                 POSTING_READ(LCPLL_CTL);
6961         }
6962 }
6963
6964 /*
6965  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6966  * source.
6967  */
6968 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6969 {
6970         uint32_t val;
6971         unsigned long irqflags;
6972
6973         val = I915_READ(LCPLL_CTL);
6974
6975         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6976                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6977                 return;
6978
6979         /*
6980          * Make sure we're not on PC8 state before disabling PC8, otherwise
6981          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6982          *
6983          * The other problem is that hsw_restore_lcpll() is called as part of
6984          * the runtime PM resume sequence, so we can't just call
6985          * gen6_gt_force_wake_get() because that function calls
6986          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6987          * while we are on the resume sequence. So to solve this problem we have
6988          * to call special forcewake code that doesn't touch runtime PM and
6989          * doesn't enable the forcewake delayed work.
6990          */
6991         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6992         if (dev_priv->uncore.forcewake_count++ == 0)
6993                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6994         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6995
6996         if (val & LCPLL_POWER_DOWN_ALLOW) {
6997                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6998                 I915_WRITE(LCPLL_CTL, val);
6999                 POSTING_READ(LCPLL_CTL);
7000         }
7001
7002         val = I915_READ(D_COMP);
7003         val |= D_COMP_COMP_FORCE;
7004         val &= ~D_COMP_COMP_DISABLE;
7005         mutex_lock(&dev_priv->rps.hw_lock);
7006         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
7007                 DRM_ERROR("Failed to enable D_COMP\n");
7008         mutex_unlock(&dev_priv->rps.hw_lock);
7009         POSTING_READ(D_COMP);
7010
7011         val = I915_READ(LCPLL_CTL);
7012         val &= ~LCPLL_PLL_DISABLE;
7013         I915_WRITE(LCPLL_CTL, val);
7014
7015         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7016                 DRM_ERROR("LCPLL not locked yet\n");
7017
7018         if (val & LCPLL_CD_SOURCE_FCLK) {
7019                 val = I915_READ(LCPLL_CTL);
7020                 val &= ~LCPLL_CD_SOURCE_FCLK;
7021                 I915_WRITE(LCPLL_CTL, val);
7022
7023                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7024                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7025                         DRM_ERROR("Switching back to LCPLL failed\n");
7026         }
7027
7028         /* See the big comment above. */
7029         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7030         if (--dev_priv->uncore.forcewake_count == 0)
7031                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7032         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7033 }
7034
7035 /*
7036  * Package states C8 and deeper are really deep PC states that can only be
7037  * reached when all the devices on the system allow it, so even if the graphics
7038  * device allows PC8+, it doesn't mean the system will actually get to these
7039  * states. Our driver only allows PC8+ when going into runtime PM.
7040  *
7041  * The requirements for PC8+ are that all the outputs are disabled, the power
7042  * well is disabled and most interrupts are disabled, and these are also
7043  * requirements for runtime PM. When these conditions are met, we manually do
7044  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7045  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7046  * hang the machine.
7047  *
7048  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7049  * the state of some registers, so when we come back from PC8+ we need to
7050  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7051  * need to take care of the registers kept by RC6. Notice that this happens even
7052  * if we don't put the device in PCI D3 state (which is what currently happens
7053  * because of the runtime PM support).
7054  *
7055  * For more, read "Display Sequences for Package C8" on the hardware
7056  * documentation.
7057  */
7058 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7059 {
7060         struct drm_device *dev = dev_priv->dev;
7061         uint32_t val;
7062
7063         WARN_ON(!HAS_PC8(dev));
7064
7065         DRM_DEBUG_KMS("Enabling package C8+\n");
7066
7067         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7068                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7069                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7070                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7071         }
7072
7073         lpt_disable_clkout_dp(dev);
7074         hsw_runtime_pm_disable_interrupts(dev);
7075         hsw_disable_lcpll(dev_priv, true, true);
7076 }
7077
7078 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7079 {
7080         struct drm_device *dev = dev_priv->dev;
7081         uint32_t val;
7082
7083         WARN_ON(!HAS_PC8(dev));
7084
7085         DRM_DEBUG_KMS("Disabling package C8+\n");
7086
7087         hsw_restore_lcpll(dev_priv);
7088         hsw_runtime_pm_restore_interrupts(dev);
7089         lpt_init_pch_refclk(dev);
7090
7091         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7092                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7093                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7094                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7095         }
7096
7097         intel_prepare_ddi(dev);
7098         i915_gem_init_swizzling(dev);
7099         mutex_lock(&dev_priv->rps.hw_lock);
7100         gen6_update_ring_freq(dev);
7101         mutex_unlock(&dev_priv->rps.hw_lock);
7102 }
7103
7104 static void haswell_modeset_global_resources(struct drm_device *dev)
7105 {
7106         modeset_update_crtc_power_domains(dev);
7107 }
7108
7109 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7110                                  int x, int y,
7111                                  struct drm_framebuffer *fb)
7112 {
7113         struct drm_device *dev = crtc->dev;
7114         struct drm_i915_private *dev_priv = dev->dev_private;
7115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7116         int plane = intel_crtc->plane;
7117         int ret;
7118
7119         if (!intel_ddi_pll_select(intel_crtc))
7120                 return -EINVAL;
7121         intel_ddi_pll_enable(intel_crtc);
7122
7123         if (intel_crtc->config.has_dp_encoder)
7124                 intel_dp_set_m_n(intel_crtc);
7125
7126         intel_crtc->lowfreq_avail = false;
7127
7128         intel_set_pipe_timings(intel_crtc);
7129
7130         if (intel_crtc->config.has_pch_encoder) {
7131                 intel_cpu_transcoder_set_m_n(intel_crtc,
7132                                              &intel_crtc->config.fdi_m_n);
7133         }
7134
7135         haswell_set_pipeconf(crtc);
7136
7137         intel_set_pipe_csc(crtc);
7138
7139         /* Set up the display plane register */
7140         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7141         POSTING_READ(DSPCNTR(plane));
7142
7143         ret = intel_pipe_set_base(crtc, x, y, fb);
7144
7145         return ret;
7146 }
7147
7148 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7149                                     struct intel_crtc_config *pipe_config)
7150 {
7151         struct drm_device *dev = crtc->base.dev;
7152         struct drm_i915_private *dev_priv = dev->dev_private;
7153         enum intel_display_power_domain pfit_domain;
7154         uint32_t tmp;
7155
7156         if (!intel_display_power_enabled(dev_priv,
7157                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7158                 return false;
7159
7160         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7161         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7162
7163         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7164         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7165                 enum pipe trans_edp_pipe;
7166                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7167                 default:
7168                         WARN(1, "unknown pipe linked to edp transcoder\n");
7169                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7170                 case TRANS_DDI_EDP_INPUT_A_ON:
7171                         trans_edp_pipe = PIPE_A;
7172                         break;
7173                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7174                         trans_edp_pipe = PIPE_B;
7175                         break;
7176                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7177                         trans_edp_pipe = PIPE_C;
7178                         break;
7179                 }
7180
7181                 if (trans_edp_pipe == crtc->pipe)
7182                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7183         }
7184
7185         if (!intel_display_power_enabled(dev_priv,
7186                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7187                 return false;
7188
7189         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7190         if (!(tmp & PIPECONF_ENABLE))
7191                 return false;
7192
7193         /*
7194          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7195          * DDI E. So just check whether this pipe is wired to DDI E and whether
7196          * the PCH transcoder is on.
7197          */
7198         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7199         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7200             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7201                 pipe_config->has_pch_encoder = true;
7202
7203                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7204                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7205                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7206
7207                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7208         }
7209
7210         intel_get_pipe_timings(crtc, pipe_config);
7211
7212         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7213         if (intel_display_power_enabled(dev_priv, pfit_domain))
7214                 ironlake_get_pfit_config(crtc, pipe_config);
7215
7216         if (IS_HASWELL(dev))
7217                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7218                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7219
7220         pipe_config->pixel_multiplier = 1;
7221
7222         return true;
7223 }
7224
7225 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7226                                int x, int y,
7227                                struct drm_framebuffer *fb)
7228 {
7229         struct drm_device *dev = crtc->dev;
7230         struct drm_i915_private *dev_priv = dev->dev_private;
7231         struct intel_encoder *encoder;
7232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7233         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7234         int pipe = intel_crtc->pipe;
7235         int ret;
7236
7237         drm_vblank_pre_modeset(dev, pipe);
7238
7239         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7240
7241         drm_vblank_post_modeset(dev, pipe);
7242
7243         if (ret != 0)
7244                 return ret;
7245
7246         for_each_encoder_on_crtc(dev, crtc, encoder) {
7247                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7248                         encoder->base.base.id,
7249                         drm_get_encoder_name(&encoder->base),
7250                         mode->base.id, mode->name);
7251                 encoder->mode_set(encoder);
7252         }
7253
7254         return 0;
7255 }
7256
7257 static struct {
7258         int clock;
7259         u32 config;
7260 } hdmi_audio_clock[] = {
7261         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7262         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7263         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7264         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7265         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7266         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7267         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7268         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7269         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7270         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7271 };
7272
7273 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7274 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7275 {
7276         int i;
7277
7278         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7279                 if (mode->clock == hdmi_audio_clock[i].clock)
7280                         break;
7281         }
7282
7283         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7284                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7285                 i = 1;
7286         }
7287
7288         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7289                       hdmi_audio_clock[i].clock,
7290                       hdmi_audio_clock[i].config);
7291
7292         return hdmi_audio_clock[i].config;
7293 }
7294
7295 static bool intel_eld_uptodate(struct drm_connector *connector,
7296                                int reg_eldv, uint32_t bits_eldv,
7297                                int reg_elda, uint32_t bits_elda,
7298                                int reg_edid)
7299 {
7300         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7301         uint8_t *eld = connector->eld;
7302         uint32_t i;
7303
7304         i = I915_READ(reg_eldv);
7305         i &= bits_eldv;
7306
7307         if (!eld[0])
7308                 return !i;
7309
7310         if (!i)
7311                 return false;
7312
7313         i = I915_READ(reg_elda);
7314         i &= ~bits_elda;
7315         I915_WRITE(reg_elda, i);
7316
7317         for (i = 0; i < eld[2]; i++)
7318                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7319                         return false;
7320
7321         return true;
7322 }
7323
7324 static void g4x_write_eld(struct drm_connector *connector,
7325                           struct drm_crtc *crtc,
7326                           struct drm_display_mode *mode)
7327 {
7328         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7329         uint8_t *eld = connector->eld;
7330         uint32_t eldv;
7331         uint32_t len;
7332         uint32_t i;
7333
7334         i = I915_READ(G4X_AUD_VID_DID);
7335
7336         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7337                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7338         else
7339                 eldv = G4X_ELDV_DEVCTG;
7340
7341         if (intel_eld_uptodate(connector,
7342                                G4X_AUD_CNTL_ST, eldv,
7343                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7344                                G4X_HDMIW_HDMIEDID))
7345                 return;
7346
7347         i = I915_READ(G4X_AUD_CNTL_ST);
7348         i &= ~(eldv | G4X_ELD_ADDR);
7349         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7350         I915_WRITE(G4X_AUD_CNTL_ST, i);
7351
7352         if (!eld[0])
7353                 return;
7354
7355         len = min_t(uint8_t, eld[2], len);
7356         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7357         for (i = 0; i < len; i++)
7358                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7359
7360         i = I915_READ(G4X_AUD_CNTL_ST);
7361         i |= eldv;
7362         I915_WRITE(G4X_AUD_CNTL_ST, i);
7363 }
7364
7365 static void haswell_write_eld(struct drm_connector *connector,
7366                               struct drm_crtc *crtc,
7367                               struct drm_display_mode *mode)
7368 {
7369         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7370         uint8_t *eld = connector->eld;
7371         struct drm_device *dev = crtc->dev;
7372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7373         uint32_t eldv;
7374         uint32_t i;
7375         int len;
7376         int pipe = to_intel_crtc(crtc)->pipe;
7377         int tmp;
7378
7379         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7380         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7381         int aud_config = HSW_AUD_CFG(pipe);
7382         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7383
7384
7385         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7386
7387         /* Audio output enable */
7388         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7389         tmp = I915_READ(aud_cntrl_st2);
7390         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7391         I915_WRITE(aud_cntrl_st2, tmp);
7392
7393         /* Wait for 1 vertical blank */
7394         intel_wait_for_vblank(dev, pipe);
7395
7396         /* Set ELD valid state */
7397         tmp = I915_READ(aud_cntrl_st2);
7398         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7399         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7400         I915_WRITE(aud_cntrl_st2, tmp);
7401         tmp = I915_READ(aud_cntrl_st2);
7402         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7403
7404         /* Enable HDMI mode */
7405         tmp = I915_READ(aud_config);
7406         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7407         /* clear N_programing_enable and N_value_index */
7408         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7409         I915_WRITE(aud_config, tmp);
7410
7411         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7412
7413         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7414         intel_crtc->eld_vld = true;
7415
7416         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7417                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7418                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7419                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7420         } else {
7421                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7422         }
7423
7424         if (intel_eld_uptodate(connector,
7425                                aud_cntrl_st2, eldv,
7426                                aud_cntl_st, IBX_ELD_ADDRESS,
7427                                hdmiw_hdmiedid))
7428                 return;
7429
7430         i = I915_READ(aud_cntrl_st2);
7431         i &= ~eldv;
7432         I915_WRITE(aud_cntrl_st2, i);
7433
7434         if (!eld[0])
7435                 return;
7436
7437         i = I915_READ(aud_cntl_st);
7438         i &= ~IBX_ELD_ADDRESS;
7439         I915_WRITE(aud_cntl_st, i);
7440         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7441         DRM_DEBUG_DRIVER("port num:%d\n", i);
7442
7443         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7444         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7445         for (i = 0; i < len; i++)
7446                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7447
7448         i = I915_READ(aud_cntrl_st2);
7449         i |= eldv;
7450         I915_WRITE(aud_cntrl_st2, i);
7451
7452 }
7453
7454 static void ironlake_write_eld(struct drm_connector *connector,
7455                                struct drm_crtc *crtc,
7456                                struct drm_display_mode *mode)
7457 {
7458         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7459         uint8_t *eld = connector->eld;
7460         uint32_t eldv;
7461         uint32_t i;
7462         int len;
7463         int hdmiw_hdmiedid;
7464         int aud_config;
7465         int aud_cntl_st;
7466         int aud_cntrl_st2;
7467         int pipe = to_intel_crtc(crtc)->pipe;
7468
7469         if (HAS_PCH_IBX(connector->dev)) {
7470                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7471                 aud_config = IBX_AUD_CFG(pipe);
7472                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7473                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7474         } else if (IS_VALLEYVIEW(connector->dev)) {
7475                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7476                 aud_config = VLV_AUD_CFG(pipe);
7477                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7478                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7479         } else {
7480                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7481                 aud_config = CPT_AUD_CFG(pipe);
7482                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7483                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7484         }
7485
7486         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7487
7488         if (IS_VALLEYVIEW(connector->dev))  {
7489                 struct intel_encoder *intel_encoder;
7490                 struct intel_digital_port *intel_dig_port;
7491
7492                 intel_encoder = intel_attached_encoder(connector);
7493                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7494                 i = intel_dig_port->port;
7495         } else {
7496                 i = I915_READ(aud_cntl_st);
7497                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7498                 /* DIP_Port_Select, 0x1 = PortB */
7499         }
7500
7501         if (!i) {
7502                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7503                 /* operate blindly on all ports */
7504                 eldv = IBX_ELD_VALIDB;
7505                 eldv |= IBX_ELD_VALIDB << 4;
7506                 eldv |= IBX_ELD_VALIDB << 8;
7507         } else {
7508                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7509                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7510         }
7511
7512         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7513                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7514                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7515                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7516         } else {
7517                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7518         }
7519
7520         if (intel_eld_uptodate(connector,
7521                                aud_cntrl_st2, eldv,
7522                                aud_cntl_st, IBX_ELD_ADDRESS,
7523                                hdmiw_hdmiedid))
7524                 return;
7525
7526         i = I915_READ(aud_cntrl_st2);
7527         i &= ~eldv;
7528         I915_WRITE(aud_cntrl_st2, i);
7529
7530         if (!eld[0])
7531                 return;
7532
7533         i = I915_READ(aud_cntl_st);
7534         i &= ~IBX_ELD_ADDRESS;
7535         I915_WRITE(aud_cntl_st, i);
7536
7537         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7538         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7539         for (i = 0; i < len; i++)
7540                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7541
7542         i = I915_READ(aud_cntrl_st2);
7543         i |= eldv;
7544         I915_WRITE(aud_cntrl_st2, i);
7545 }
7546
7547 void intel_write_eld(struct drm_encoder *encoder,
7548                      struct drm_display_mode *mode)
7549 {
7550         struct drm_crtc *crtc = encoder->crtc;
7551         struct drm_connector *connector;
7552         struct drm_device *dev = encoder->dev;
7553         struct drm_i915_private *dev_priv = dev->dev_private;
7554
7555         connector = drm_select_eld(encoder, mode);
7556         if (!connector)
7557                 return;
7558
7559         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7560                          connector->base.id,
7561                          drm_get_connector_name(connector),
7562                          connector->encoder->base.id,
7563                          drm_get_encoder_name(connector->encoder));
7564
7565         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7566
7567         if (dev_priv->display.write_eld)
7568                 dev_priv->display.write_eld(connector, crtc, mode);
7569 }
7570
7571 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7572 {
7573         struct drm_device *dev = crtc->dev;
7574         struct drm_i915_private *dev_priv = dev->dev_private;
7575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7576         bool visible = base != 0;
7577         u32 cntl;
7578
7579         if (intel_crtc->cursor_visible == visible)
7580                 return;
7581
7582         cntl = I915_READ(_CURACNTR);
7583         if (visible) {
7584                 /* On these chipsets we can only modify the base whilst
7585                  * the cursor is disabled.
7586                  */
7587                 I915_WRITE(_CURABASE, base);
7588
7589                 cntl &= ~(CURSOR_FORMAT_MASK);
7590                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7591                 cntl |= CURSOR_ENABLE |
7592                         CURSOR_GAMMA_ENABLE |
7593                         CURSOR_FORMAT_ARGB;
7594         } else
7595                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7596         I915_WRITE(_CURACNTR, cntl);
7597
7598         intel_crtc->cursor_visible = visible;
7599 }
7600
7601 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7602 {
7603         struct drm_device *dev = crtc->dev;
7604         struct drm_i915_private *dev_priv = dev->dev_private;
7605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7606         int pipe = intel_crtc->pipe;
7607         bool visible = base != 0;
7608
7609         if (intel_crtc->cursor_visible != visible) {
7610                 int16_t width = intel_crtc->cursor_width;
7611                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7612                 if (base) {
7613                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7614                         cntl |= MCURSOR_GAMMA_ENABLE;
7615
7616                         switch (width) {
7617                         case 64:
7618                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7619                                 break;
7620                         case 128:
7621                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7622                                 break;
7623                         case 256:
7624                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7625                                 break;
7626                         default:
7627                                 WARN_ON(1);
7628                                 return;
7629                         }
7630                         cntl |= pipe << 28; /* Connect to correct pipe */
7631                 } else {
7632                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7633                         cntl |= CURSOR_MODE_DISABLE;
7634                 }
7635                 I915_WRITE(CURCNTR(pipe), cntl);
7636
7637                 intel_crtc->cursor_visible = visible;
7638         }
7639         /* and commit changes on next vblank */
7640         POSTING_READ(CURCNTR(pipe));
7641         I915_WRITE(CURBASE(pipe), base);
7642         POSTING_READ(CURBASE(pipe));
7643 }
7644
7645 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7646 {
7647         struct drm_device *dev = crtc->dev;
7648         struct drm_i915_private *dev_priv = dev->dev_private;
7649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7650         int pipe = intel_crtc->pipe;
7651         bool visible = base != 0;
7652
7653         if (intel_crtc->cursor_visible != visible) {
7654                 int16_t width = intel_crtc->cursor_width;
7655                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7656                 if (base) {
7657                         cntl &= ~CURSOR_MODE;
7658                         cntl |= MCURSOR_GAMMA_ENABLE;
7659                         switch (width) {
7660                         case 64:
7661                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7662                                 break;
7663                         case 128:
7664                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7665                                 break;
7666                         case 256:
7667                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7668                                 break;
7669                         default:
7670                                 WARN_ON(1);
7671                                 return;
7672                         }
7673                 } else {
7674                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7675                         cntl |= CURSOR_MODE_DISABLE;
7676                 }
7677                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7678                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7679                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7680                 }
7681                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7682
7683                 intel_crtc->cursor_visible = visible;
7684         }
7685         /* and commit changes on next vblank */
7686         POSTING_READ(CURCNTR_IVB(pipe));
7687         I915_WRITE(CURBASE_IVB(pipe), base);
7688         POSTING_READ(CURBASE_IVB(pipe));
7689 }
7690
7691 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7692 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7693                                      bool on)
7694 {
7695         struct drm_device *dev = crtc->dev;
7696         struct drm_i915_private *dev_priv = dev->dev_private;
7697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7698         int pipe = intel_crtc->pipe;
7699         int x = intel_crtc->cursor_x;
7700         int y = intel_crtc->cursor_y;
7701         u32 base = 0, pos = 0;
7702         bool visible;
7703
7704         if (on)
7705                 base = intel_crtc->cursor_addr;
7706
7707         if (x >= intel_crtc->config.pipe_src_w)
7708                 base = 0;
7709
7710         if (y >= intel_crtc->config.pipe_src_h)
7711                 base = 0;
7712
7713         if (x < 0) {
7714                 if (x + intel_crtc->cursor_width <= 0)
7715                         base = 0;
7716
7717                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7718                 x = -x;
7719         }
7720         pos |= x << CURSOR_X_SHIFT;
7721
7722         if (y < 0) {
7723                 if (y + intel_crtc->cursor_height <= 0)
7724                         base = 0;
7725
7726                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7727                 y = -y;
7728         }
7729         pos |= y << CURSOR_Y_SHIFT;
7730
7731         visible = base != 0;
7732         if (!visible && !intel_crtc->cursor_visible)
7733                 return;
7734
7735         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7736                 I915_WRITE(CURPOS_IVB(pipe), pos);
7737                 ivb_update_cursor(crtc, base);
7738         } else {
7739                 I915_WRITE(CURPOS(pipe), pos);
7740                 if (IS_845G(dev) || IS_I865G(dev))
7741                         i845_update_cursor(crtc, base);
7742                 else
7743                         i9xx_update_cursor(crtc, base);
7744         }
7745 }
7746
7747 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7748                                  struct drm_file *file,
7749                                  uint32_t handle,
7750                                  uint32_t width, uint32_t height)
7751 {
7752         struct drm_device *dev = crtc->dev;
7753         struct drm_i915_private *dev_priv = dev->dev_private;
7754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7755         struct drm_i915_gem_object *obj;
7756         unsigned old_width;
7757         uint32_t addr;
7758         int ret;
7759
7760         /* if we want to turn off the cursor ignore width and height */
7761         if (!handle) {
7762                 DRM_DEBUG_KMS("cursor off\n");
7763                 addr = 0;
7764                 obj = NULL;
7765                 mutex_lock(&dev->struct_mutex);
7766                 goto finish;
7767         }
7768
7769         /* Check for which cursor types we support */
7770         if (!((width == 64 && height == 64) ||
7771                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7772                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7773                 DRM_DEBUG("Cursor dimension not supported\n");
7774                 return -EINVAL;
7775         }
7776
7777         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7778         if (&obj->base == NULL)
7779                 return -ENOENT;
7780
7781         if (obj->base.size < width * height * 4) {
7782                 DRM_DEBUG_KMS("buffer is to small\n");
7783                 ret = -ENOMEM;
7784                 goto fail;
7785         }
7786
7787         /* we only need to pin inside GTT if cursor is non-phy */
7788         mutex_lock(&dev->struct_mutex);
7789         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7790                 unsigned alignment;
7791
7792                 if (obj->tiling_mode) {
7793                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7794                         ret = -EINVAL;
7795                         goto fail_locked;
7796                 }
7797
7798                 /* Note that the w/a also requires 2 PTE of padding following
7799                  * the bo. We currently fill all unused PTE with the shadow
7800                  * page and so we should always have valid PTE following the
7801                  * cursor preventing the VT-d warning.
7802                  */
7803                 alignment = 0;
7804                 if (need_vtd_wa(dev))
7805                         alignment = 64*1024;
7806
7807                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7808                 if (ret) {
7809                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7810                         goto fail_locked;
7811                 }
7812
7813                 ret = i915_gem_object_put_fence(obj);
7814                 if (ret) {
7815                         DRM_DEBUG_KMS("failed to release fence for cursor");
7816                         goto fail_unpin;
7817                 }
7818
7819                 addr = i915_gem_obj_ggtt_offset(obj);
7820         } else {
7821                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7822                 ret = i915_gem_attach_phys_object(dev, obj,
7823                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7824                                                   align);
7825                 if (ret) {
7826                         DRM_DEBUG_KMS("failed to attach phys object\n");
7827                         goto fail_locked;
7828                 }
7829                 addr = obj->phys_obj->handle->busaddr;
7830         }
7831
7832         if (IS_GEN2(dev))
7833                 I915_WRITE(CURSIZE, (height << 12) | width);
7834
7835  finish:
7836         if (intel_crtc->cursor_bo) {
7837                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7838                         if (intel_crtc->cursor_bo != obj)
7839                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7840                 } else
7841                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7842                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7843         }
7844
7845         mutex_unlock(&dev->struct_mutex);
7846
7847         old_width = intel_crtc->cursor_width;
7848
7849         intel_crtc->cursor_addr = addr;
7850         intel_crtc->cursor_bo = obj;
7851         intel_crtc->cursor_width = width;
7852         intel_crtc->cursor_height = height;
7853
7854         if (intel_crtc->active) {
7855                 if (old_width != width)
7856                         intel_update_watermarks(crtc);
7857                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7858         }
7859
7860         return 0;
7861 fail_unpin:
7862         i915_gem_object_unpin_from_display_plane(obj);
7863 fail_locked:
7864         mutex_unlock(&dev->struct_mutex);
7865 fail:
7866         drm_gem_object_unreference_unlocked(&obj->base);
7867         return ret;
7868 }
7869
7870 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7871 {
7872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7873
7874         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7875         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7876
7877         if (intel_crtc->active)
7878                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7879
7880         return 0;
7881 }
7882
7883 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7884                                  u16 *blue, uint32_t start, uint32_t size)
7885 {
7886         int end = (start + size > 256) ? 256 : start + size, i;
7887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7888
7889         for (i = start; i < end; i++) {
7890                 intel_crtc->lut_r[i] = red[i] >> 8;
7891                 intel_crtc->lut_g[i] = green[i] >> 8;
7892                 intel_crtc->lut_b[i] = blue[i] >> 8;
7893         }
7894
7895         intel_crtc_load_lut(crtc);
7896 }
7897
7898 /* VESA 640x480x72Hz mode to set on the pipe */
7899 static struct drm_display_mode load_detect_mode = {
7900         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7901                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7902 };
7903
7904 struct drm_framebuffer *
7905 __intel_framebuffer_create(struct drm_device *dev,
7906                            struct drm_mode_fb_cmd2 *mode_cmd,
7907                            struct drm_i915_gem_object *obj)
7908 {
7909         struct intel_framebuffer *intel_fb;
7910         int ret;
7911
7912         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7913         if (!intel_fb) {
7914                 drm_gem_object_unreference_unlocked(&obj->base);
7915                 return ERR_PTR(-ENOMEM);
7916         }
7917
7918         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7919         if (ret)
7920                 goto err;
7921
7922         return &intel_fb->base;
7923 err:
7924         drm_gem_object_unreference_unlocked(&obj->base);
7925         kfree(intel_fb);
7926
7927         return ERR_PTR(ret);
7928 }
7929
7930 static struct drm_framebuffer *
7931 intel_framebuffer_create(struct drm_device *dev,
7932                          struct drm_mode_fb_cmd2 *mode_cmd,
7933                          struct drm_i915_gem_object *obj)
7934 {
7935         struct drm_framebuffer *fb;
7936         int ret;
7937
7938         ret = i915_mutex_lock_interruptible(dev);
7939         if (ret)
7940                 return ERR_PTR(ret);
7941         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7942         mutex_unlock(&dev->struct_mutex);
7943
7944         return fb;
7945 }
7946
7947 static u32
7948 intel_framebuffer_pitch_for_width(int width, int bpp)
7949 {
7950         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7951         return ALIGN(pitch, 64);
7952 }
7953
7954 static u32
7955 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7956 {
7957         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7958         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7959 }
7960
7961 static struct drm_framebuffer *
7962 intel_framebuffer_create_for_mode(struct drm_device *dev,
7963                                   struct drm_display_mode *mode,
7964                                   int depth, int bpp)
7965 {
7966         struct drm_i915_gem_object *obj;
7967         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7968
7969         obj = i915_gem_alloc_object(dev,
7970                                     intel_framebuffer_size_for_mode(mode, bpp));
7971         if (obj == NULL)
7972                 return ERR_PTR(-ENOMEM);
7973
7974         mode_cmd.width = mode->hdisplay;
7975         mode_cmd.height = mode->vdisplay;
7976         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7977                                                                 bpp);
7978         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7979
7980         return intel_framebuffer_create(dev, &mode_cmd, obj);
7981 }
7982
7983 static struct drm_framebuffer *
7984 mode_fits_in_fbdev(struct drm_device *dev,
7985                    struct drm_display_mode *mode)
7986 {
7987 #ifdef CONFIG_DRM_I915_FBDEV
7988         struct drm_i915_private *dev_priv = dev->dev_private;
7989         struct drm_i915_gem_object *obj;
7990         struct drm_framebuffer *fb;
7991
7992         if (!dev_priv->fbdev)
7993                 return NULL;
7994
7995         if (!dev_priv->fbdev->fb)
7996                 return NULL;
7997
7998         obj = dev_priv->fbdev->fb->obj;
7999         BUG_ON(!obj);
8000
8001         fb = &dev_priv->fbdev->fb->base;
8002         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8003                                                                fb->bits_per_pixel))
8004                 return NULL;
8005
8006         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8007                 return NULL;
8008
8009         return fb;
8010 #else
8011         return NULL;
8012 #endif
8013 }
8014
8015 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8016                                 struct drm_display_mode *mode,
8017                                 struct intel_load_detect_pipe *old)
8018 {
8019         struct intel_crtc *intel_crtc;
8020         struct intel_encoder *intel_encoder =
8021                 intel_attached_encoder(connector);
8022         struct drm_crtc *possible_crtc;
8023         struct drm_encoder *encoder = &intel_encoder->base;
8024         struct drm_crtc *crtc = NULL;
8025         struct drm_device *dev = encoder->dev;
8026         struct drm_framebuffer *fb;
8027         int i = -1;
8028
8029         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8030                       connector->base.id, drm_get_connector_name(connector),
8031                       encoder->base.id, drm_get_encoder_name(encoder));
8032
8033         /*
8034          * Algorithm gets a little messy:
8035          *
8036          *   - if the connector already has an assigned crtc, use it (but make
8037          *     sure it's on first)
8038          *
8039          *   - try to find the first unused crtc that can drive this connector,
8040          *     and use that if we find one
8041          */
8042
8043         /* See if we already have a CRTC for this connector */
8044         if (encoder->crtc) {
8045                 crtc = encoder->crtc;
8046
8047                 mutex_lock(&crtc->mutex);
8048
8049                 old->dpms_mode = connector->dpms;
8050                 old->load_detect_temp = false;
8051
8052                 /* Make sure the crtc and connector are running */
8053                 if (connector->dpms != DRM_MODE_DPMS_ON)
8054                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8055
8056                 return true;
8057         }
8058
8059         /* Find an unused one (if possible) */
8060         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8061                 i++;
8062                 if (!(encoder->possible_crtcs & (1 << i)))
8063                         continue;
8064                 if (!possible_crtc->enabled) {
8065                         crtc = possible_crtc;
8066                         break;
8067                 }
8068         }
8069
8070         /*
8071          * If we didn't find an unused CRTC, don't use any.
8072          */
8073         if (!crtc) {
8074                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8075                 return false;
8076         }
8077
8078         mutex_lock(&crtc->mutex);
8079         intel_encoder->new_crtc = to_intel_crtc(crtc);
8080         to_intel_connector(connector)->new_encoder = intel_encoder;
8081
8082         intel_crtc = to_intel_crtc(crtc);
8083         intel_crtc->new_enabled = true;
8084         intel_crtc->new_config = &intel_crtc->config;
8085         old->dpms_mode = connector->dpms;
8086         old->load_detect_temp = true;
8087         old->release_fb = NULL;
8088
8089         if (!mode)
8090                 mode = &load_detect_mode;
8091
8092         /* We need a framebuffer large enough to accommodate all accesses
8093          * that the plane may generate whilst we perform load detection.
8094          * We can not rely on the fbcon either being present (we get called
8095          * during its initialisation to detect all boot displays, or it may
8096          * not even exist) or that it is large enough to satisfy the
8097          * requested mode.
8098          */
8099         fb = mode_fits_in_fbdev(dev, mode);
8100         if (fb == NULL) {
8101                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8102                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8103                 old->release_fb = fb;
8104         } else
8105                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8106         if (IS_ERR(fb)) {
8107                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8108                 goto fail;
8109         }
8110
8111         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8112                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8113                 if (old->release_fb)
8114                         old->release_fb->funcs->destroy(old->release_fb);
8115                 goto fail;
8116         }
8117
8118         /* let the connector get through one full cycle before testing */
8119         intel_wait_for_vblank(dev, intel_crtc->pipe);
8120         return true;
8121
8122  fail:
8123         intel_crtc->new_enabled = crtc->enabled;
8124         if (intel_crtc->new_enabled)
8125                 intel_crtc->new_config = &intel_crtc->config;
8126         else
8127                 intel_crtc->new_config = NULL;
8128         mutex_unlock(&crtc->mutex);
8129         return false;
8130 }
8131
8132 void intel_release_load_detect_pipe(struct drm_connector *connector,
8133                                     struct intel_load_detect_pipe *old)
8134 {
8135         struct intel_encoder *intel_encoder =
8136                 intel_attached_encoder(connector);
8137         struct drm_encoder *encoder = &intel_encoder->base;
8138         struct drm_crtc *crtc = encoder->crtc;
8139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8140
8141         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8142                       connector->base.id, drm_get_connector_name(connector),
8143                       encoder->base.id, drm_get_encoder_name(encoder));
8144
8145         if (old->load_detect_temp) {
8146                 to_intel_connector(connector)->new_encoder = NULL;
8147                 intel_encoder->new_crtc = NULL;
8148                 intel_crtc->new_enabled = false;
8149                 intel_crtc->new_config = NULL;
8150                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8151
8152                 if (old->release_fb) {
8153                         drm_framebuffer_unregister_private(old->release_fb);
8154                         drm_framebuffer_unreference(old->release_fb);
8155                 }
8156
8157                 mutex_unlock(&crtc->mutex);
8158                 return;
8159         }
8160
8161         /* Switch crtc and encoder back off if necessary */
8162         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8163                 connector->funcs->dpms(connector, old->dpms_mode);
8164
8165         mutex_unlock(&crtc->mutex);
8166 }
8167
8168 static int i9xx_pll_refclk(struct drm_device *dev,
8169                            const struct intel_crtc_config *pipe_config)
8170 {
8171         struct drm_i915_private *dev_priv = dev->dev_private;
8172         u32 dpll = pipe_config->dpll_hw_state.dpll;
8173
8174         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8175                 return dev_priv->vbt.lvds_ssc_freq;
8176         else if (HAS_PCH_SPLIT(dev))
8177                 return 120000;
8178         else if (!IS_GEN2(dev))
8179                 return 96000;
8180         else
8181                 return 48000;
8182 }
8183
8184 /* Returns the clock of the currently programmed mode of the given pipe. */
8185 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8186                                 struct intel_crtc_config *pipe_config)
8187 {
8188         struct drm_device *dev = crtc->base.dev;
8189         struct drm_i915_private *dev_priv = dev->dev_private;
8190         int pipe = pipe_config->cpu_transcoder;
8191         u32 dpll = pipe_config->dpll_hw_state.dpll;
8192         u32 fp;
8193         intel_clock_t clock;
8194         int refclk = i9xx_pll_refclk(dev, pipe_config);
8195
8196         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8197                 fp = pipe_config->dpll_hw_state.fp0;
8198         else
8199                 fp = pipe_config->dpll_hw_state.fp1;
8200
8201         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8202         if (IS_PINEVIEW(dev)) {
8203                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8204                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8205         } else {
8206                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8207                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8208         }
8209
8210         if (!IS_GEN2(dev)) {
8211                 if (IS_PINEVIEW(dev))
8212                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8213                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8214                 else
8215                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8216                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8217
8218                 switch (dpll & DPLL_MODE_MASK) {
8219                 case DPLLB_MODE_DAC_SERIAL:
8220                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8221                                 5 : 10;
8222                         break;
8223                 case DPLLB_MODE_LVDS:
8224                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8225                                 7 : 14;
8226                         break;
8227                 default:
8228                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8229                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8230                         return;
8231                 }
8232
8233                 if (IS_PINEVIEW(dev))
8234                         pineview_clock(refclk, &clock);
8235                 else
8236                         i9xx_clock(refclk, &clock);
8237         } else {
8238                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8239                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8240
8241                 if (is_lvds) {
8242                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8243                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8244
8245                         if (lvds & LVDS_CLKB_POWER_UP)
8246                                 clock.p2 = 7;
8247                         else
8248                                 clock.p2 = 14;
8249                 } else {
8250                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8251                                 clock.p1 = 2;
8252                         else {
8253                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8254                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8255                         }
8256                         if (dpll & PLL_P2_DIVIDE_BY_4)
8257                                 clock.p2 = 4;
8258                         else
8259                                 clock.p2 = 2;
8260                 }
8261
8262                 i9xx_clock(refclk, &clock);
8263         }
8264
8265         /*
8266          * This value includes pixel_multiplier. We will use
8267          * port_clock to compute adjusted_mode.crtc_clock in the
8268          * encoder's get_config() function.
8269          */
8270         pipe_config->port_clock = clock.dot;
8271 }
8272
8273 int intel_dotclock_calculate(int link_freq,
8274                              const struct intel_link_m_n *m_n)
8275 {
8276         /*
8277          * The calculation for the data clock is:
8278          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8279          * But we want to avoid losing precison if possible, so:
8280          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8281          *
8282          * and the link clock is simpler:
8283          * link_clock = (m * link_clock) / n
8284          */
8285
8286         if (!m_n->link_n)
8287                 return 0;
8288
8289         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8290 }
8291
8292 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8293                                    struct intel_crtc_config *pipe_config)
8294 {
8295         struct drm_device *dev = crtc->base.dev;
8296
8297         /* read out port_clock from the DPLL */
8298         i9xx_crtc_clock_get(crtc, pipe_config);
8299
8300         /*
8301          * This value does not include pixel_multiplier.
8302          * We will check that port_clock and adjusted_mode.crtc_clock
8303          * agree once we know their relationship in the encoder's
8304          * get_config() function.
8305          */
8306         pipe_config->adjusted_mode.crtc_clock =
8307                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8308                                          &pipe_config->fdi_m_n);
8309 }
8310
8311 /** Returns the currently programmed mode of the given pipe. */
8312 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8313                                              struct drm_crtc *crtc)
8314 {
8315         struct drm_i915_private *dev_priv = dev->dev_private;
8316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8317         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8318         struct drm_display_mode *mode;
8319         struct intel_crtc_config pipe_config;
8320         int htot = I915_READ(HTOTAL(cpu_transcoder));
8321         int hsync = I915_READ(HSYNC(cpu_transcoder));
8322         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8323         int vsync = I915_READ(VSYNC(cpu_transcoder));
8324         enum pipe pipe = intel_crtc->pipe;
8325
8326         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8327         if (!mode)
8328                 return NULL;
8329
8330         /*
8331          * Construct a pipe_config sufficient for getting the clock info
8332          * back out of crtc_clock_get.
8333          *
8334          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8335          * to use a real value here instead.
8336          */
8337         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8338         pipe_config.pixel_multiplier = 1;
8339         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8340         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8341         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8342         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8343
8344         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8345         mode->hdisplay = (htot & 0xffff) + 1;
8346         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8347         mode->hsync_start = (hsync & 0xffff) + 1;
8348         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8349         mode->vdisplay = (vtot & 0xffff) + 1;
8350         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8351         mode->vsync_start = (vsync & 0xffff) + 1;
8352         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8353
8354         drm_mode_set_name(mode);
8355
8356         return mode;
8357 }
8358
8359 static void intel_increase_pllclock(struct drm_crtc *crtc)
8360 {
8361         struct drm_device *dev = crtc->dev;
8362         struct drm_i915_private *dev_priv = dev->dev_private;
8363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8364         int pipe = intel_crtc->pipe;
8365         int dpll_reg = DPLL(pipe);
8366         int dpll;
8367
8368         if (HAS_PCH_SPLIT(dev))
8369                 return;
8370
8371         if (!dev_priv->lvds_downclock_avail)
8372                 return;
8373
8374         dpll = I915_READ(dpll_reg);
8375         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8376                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8377
8378                 assert_panel_unlocked(dev_priv, pipe);
8379
8380                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8381                 I915_WRITE(dpll_reg, dpll);
8382                 intel_wait_for_vblank(dev, pipe);
8383
8384                 dpll = I915_READ(dpll_reg);
8385                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8386                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8387         }
8388 }
8389
8390 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8391 {
8392         struct drm_device *dev = crtc->dev;
8393         struct drm_i915_private *dev_priv = dev->dev_private;
8394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8395
8396         if (HAS_PCH_SPLIT(dev))
8397                 return;
8398
8399         if (!dev_priv->lvds_downclock_avail)
8400                 return;
8401
8402         /*
8403          * Since this is called by a timer, we should never get here in
8404          * the manual case.
8405          */
8406         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8407                 int pipe = intel_crtc->pipe;
8408                 int dpll_reg = DPLL(pipe);
8409                 int dpll;
8410
8411                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8412
8413                 assert_panel_unlocked(dev_priv, pipe);
8414
8415                 dpll = I915_READ(dpll_reg);
8416                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8417                 I915_WRITE(dpll_reg, dpll);
8418                 intel_wait_for_vblank(dev, pipe);
8419                 dpll = I915_READ(dpll_reg);
8420                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8421                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8422         }
8423
8424 }
8425
8426 void intel_mark_busy(struct drm_device *dev)
8427 {
8428         struct drm_i915_private *dev_priv = dev->dev_private;
8429
8430         if (dev_priv->mm.busy)
8431                 return;
8432
8433         intel_runtime_pm_get(dev_priv);
8434         i915_update_gfx_val(dev_priv);
8435         dev_priv->mm.busy = true;
8436 }
8437
8438 void intel_mark_idle(struct drm_device *dev)
8439 {
8440         struct drm_i915_private *dev_priv = dev->dev_private;
8441         struct drm_crtc *crtc;
8442
8443         if (!dev_priv->mm.busy)
8444                 return;
8445
8446         dev_priv->mm.busy = false;
8447
8448         if (!i915.powersave)
8449                 goto out;
8450
8451         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8452                 if (!crtc->fb)
8453                         continue;
8454
8455                 intel_decrease_pllclock(crtc);
8456         }
8457
8458         if (INTEL_INFO(dev)->gen >= 6)
8459                 gen6_rps_idle(dev->dev_private);
8460
8461 out:
8462         intel_runtime_pm_put(dev_priv);
8463 }
8464
8465 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8466                         struct intel_ring_buffer *ring)
8467 {
8468         struct drm_device *dev = obj->base.dev;
8469         struct drm_crtc *crtc;
8470
8471         if (!i915.powersave)
8472                 return;
8473
8474         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8475                 if (!crtc->fb)
8476                         continue;
8477
8478                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8479                         continue;
8480
8481                 intel_increase_pllclock(crtc);
8482                 if (ring && intel_fbc_enabled(dev))
8483                         ring->fbc_dirty = true;
8484         }
8485 }
8486
8487 static void intel_crtc_destroy(struct drm_crtc *crtc)
8488 {
8489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8490         struct drm_device *dev = crtc->dev;
8491         struct intel_unpin_work *work;
8492         unsigned long flags;
8493
8494         spin_lock_irqsave(&dev->event_lock, flags);
8495         work = intel_crtc->unpin_work;
8496         intel_crtc->unpin_work = NULL;
8497         spin_unlock_irqrestore(&dev->event_lock, flags);
8498
8499         if (work) {
8500                 cancel_work_sync(&work->work);
8501                 kfree(work);
8502         }
8503
8504         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8505
8506         drm_crtc_cleanup(crtc);
8507
8508         kfree(intel_crtc);
8509 }
8510
8511 static void intel_unpin_work_fn(struct work_struct *__work)
8512 {
8513         struct intel_unpin_work *work =
8514                 container_of(__work, struct intel_unpin_work, work);
8515         struct drm_device *dev = work->crtc->dev;
8516
8517         mutex_lock(&dev->struct_mutex);
8518         intel_unpin_fb_obj(work->old_fb_obj);
8519         drm_gem_object_unreference(&work->pending_flip_obj->base);
8520         drm_gem_object_unreference(&work->old_fb_obj->base);
8521
8522         intel_update_fbc(dev);
8523         mutex_unlock(&dev->struct_mutex);
8524
8525         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8526         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8527
8528         kfree(work);
8529 }
8530
8531 static void do_intel_finish_page_flip(struct drm_device *dev,
8532                                       struct drm_crtc *crtc)
8533 {
8534         struct drm_i915_private *dev_priv = dev->dev_private;
8535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8536         struct intel_unpin_work *work;
8537         unsigned long flags;
8538
8539         /* Ignore early vblank irqs */
8540         if (intel_crtc == NULL)
8541                 return;
8542
8543         spin_lock_irqsave(&dev->event_lock, flags);
8544         work = intel_crtc->unpin_work;
8545
8546         /* Ensure we don't miss a work->pending update ... */
8547         smp_rmb();
8548
8549         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8550                 spin_unlock_irqrestore(&dev->event_lock, flags);
8551                 return;
8552         }
8553
8554         /* and that the unpin work is consistent wrt ->pending. */
8555         smp_rmb();
8556
8557         intel_crtc->unpin_work = NULL;
8558
8559         if (work->event)
8560                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8561
8562         drm_vblank_put(dev, intel_crtc->pipe);
8563
8564         spin_unlock_irqrestore(&dev->event_lock, flags);
8565
8566         wake_up_all(&dev_priv->pending_flip_queue);
8567
8568         queue_work(dev_priv->wq, &work->work);
8569
8570         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8571 }
8572
8573 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8574 {
8575         struct drm_i915_private *dev_priv = dev->dev_private;
8576         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8577
8578         do_intel_finish_page_flip(dev, crtc);
8579 }
8580
8581 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8582 {
8583         struct drm_i915_private *dev_priv = dev->dev_private;
8584         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8585
8586         do_intel_finish_page_flip(dev, crtc);
8587 }
8588
8589 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8590 {
8591         struct drm_i915_private *dev_priv = dev->dev_private;
8592         struct intel_crtc *intel_crtc =
8593                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8594         unsigned long flags;
8595
8596         /* NB: An MMIO update of the plane base pointer will also
8597          * generate a page-flip completion irq, i.e. every modeset
8598          * is also accompanied by a spurious intel_prepare_page_flip().
8599          */
8600         spin_lock_irqsave(&dev->event_lock, flags);
8601         if (intel_crtc->unpin_work)
8602                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8603         spin_unlock_irqrestore(&dev->event_lock, flags);
8604 }
8605
8606 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8607 {
8608         /* Ensure that the work item is consistent when activating it ... */
8609         smp_wmb();
8610         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8611         /* and that it is marked active as soon as the irq could fire. */
8612         smp_wmb();
8613 }
8614
8615 static int intel_gen2_queue_flip(struct drm_device *dev,
8616                                  struct drm_crtc *crtc,
8617                                  struct drm_framebuffer *fb,
8618                                  struct drm_i915_gem_object *obj,
8619                                  uint32_t flags)
8620 {
8621         struct drm_i915_private *dev_priv = dev->dev_private;
8622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623         u32 flip_mask;
8624         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8625         int ret;
8626
8627         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8628         if (ret)
8629                 goto err;
8630
8631         ret = intel_ring_begin(ring, 6);
8632         if (ret)
8633                 goto err_unpin;
8634
8635         /* Can't queue multiple flips, so wait for the previous
8636          * one to finish before executing the next.
8637          */
8638         if (intel_crtc->plane)
8639                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8640         else
8641                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8642         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8643         intel_ring_emit(ring, MI_NOOP);
8644         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8645                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8646         intel_ring_emit(ring, fb->pitches[0]);
8647         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8648         intel_ring_emit(ring, 0); /* aux display base address, unused */
8649
8650         intel_mark_page_flip_active(intel_crtc);
8651         __intel_ring_advance(ring);
8652         return 0;
8653
8654 err_unpin:
8655         intel_unpin_fb_obj(obj);
8656 err:
8657         return ret;
8658 }
8659
8660 static int intel_gen3_queue_flip(struct drm_device *dev,
8661                                  struct drm_crtc *crtc,
8662                                  struct drm_framebuffer *fb,
8663                                  struct drm_i915_gem_object *obj,
8664                                  uint32_t flags)
8665 {
8666         struct drm_i915_private *dev_priv = dev->dev_private;
8667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8668         u32 flip_mask;
8669         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8670         int ret;
8671
8672         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8673         if (ret)
8674                 goto err;
8675
8676         ret = intel_ring_begin(ring, 6);
8677         if (ret)
8678                 goto err_unpin;
8679
8680         if (intel_crtc->plane)
8681                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8682         else
8683                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8684         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8685         intel_ring_emit(ring, MI_NOOP);
8686         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8687                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8688         intel_ring_emit(ring, fb->pitches[0]);
8689         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8690         intel_ring_emit(ring, MI_NOOP);
8691
8692         intel_mark_page_flip_active(intel_crtc);
8693         __intel_ring_advance(ring);
8694         return 0;
8695
8696 err_unpin:
8697         intel_unpin_fb_obj(obj);
8698 err:
8699         return ret;
8700 }
8701
8702 static int intel_gen4_queue_flip(struct drm_device *dev,
8703                                  struct drm_crtc *crtc,
8704                                  struct drm_framebuffer *fb,
8705                                  struct drm_i915_gem_object *obj,
8706                                  uint32_t flags)
8707 {
8708         struct drm_i915_private *dev_priv = dev->dev_private;
8709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8710         uint32_t pf, pipesrc;
8711         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8712         int ret;
8713
8714         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8715         if (ret)
8716                 goto err;
8717
8718         ret = intel_ring_begin(ring, 4);
8719         if (ret)
8720                 goto err_unpin;
8721
8722         /* i965+ uses the linear or tiled offsets from the
8723          * Display Registers (which do not change across a page-flip)
8724          * so we need only reprogram the base address.
8725          */
8726         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8727                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8728         intel_ring_emit(ring, fb->pitches[0]);
8729         intel_ring_emit(ring,
8730                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8731                         obj->tiling_mode);
8732
8733         /* XXX Enabling the panel-fitter across page-flip is so far
8734          * untested on non-native modes, so ignore it for now.
8735          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8736          */
8737         pf = 0;
8738         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8739         intel_ring_emit(ring, pf | pipesrc);
8740
8741         intel_mark_page_flip_active(intel_crtc);
8742         __intel_ring_advance(ring);
8743         return 0;
8744
8745 err_unpin:
8746         intel_unpin_fb_obj(obj);
8747 err:
8748         return ret;
8749 }
8750
8751 static int intel_gen6_queue_flip(struct drm_device *dev,
8752                                  struct drm_crtc *crtc,
8753                                  struct drm_framebuffer *fb,
8754                                  struct drm_i915_gem_object *obj,
8755                                  uint32_t flags)
8756 {
8757         struct drm_i915_private *dev_priv = dev->dev_private;
8758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8759         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8760         uint32_t pf, pipesrc;
8761         int ret;
8762
8763         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8764         if (ret)
8765                 goto err;
8766
8767         ret = intel_ring_begin(ring, 4);
8768         if (ret)
8769                 goto err_unpin;
8770
8771         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8772                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8773         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8774         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8775
8776         /* Contrary to the suggestions in the documentation,
8777          * "Enable Panel Fitter" does not seem to be required when page
8778          * flipping with a non-native mode, and worse causes a normal
8779          * modeset to fail.
8780          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8781          */
8782         pf = 0;
8783         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8784         intel_ring_emit(ring, pf | pipesrc);
8785
8786         intel_mark_page_flip_active(intel_crtc);
8787         __intel_ring_advance(ring);
8788         return 0;
8789
8790 err_unpin:
8791         intel_unpin_fb_obj(obj);
8792 err:
8793         return ret;
8794 }
8795
8796 static int intel_gen7_queue_flip(struct drm_device *dev,
8797                                  struct drm_crtc *crtc,
8798                                  struct drm_framebuffer *fb,
8799                                  struct drm_i915_gem_object *obj,
8800                                  uint32_t flags)
8801 {
8802         struct drm_i915_private *dev_priv = dev->dev_private;
8803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8804         struct intel_ring_buffer *ring;
8805         uint32_t plane_bit = 0;
8806         int len, ret;
8807
8808         ring = obj->ring;
8809         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8810                 ring = &dev_priv->ring[BCS];
8811
8812         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8813         if (ret)
8814                 goto err;
8815
8816         switch(intel_crtc->plane) {
8817         case PLANE_A:
8818                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8819                 break;
8820         case PLANE_B:
8821                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8822                 break;
8823         case PLANE_C:
8824                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8825                 break;
8826         default:
8827                 WARN_ONCE(1, "unknown plane in flip command\n");
8828                 ret = -ENODEV;
8829                 goto err_unpin;
8830         }
8831
8832         len = 4;
8833         if (ring->id == RCS)
8834                 len += 6;
8835
8836         /*
8837          * BSpec MI_DISPLAY_FLIP for IVB:
8838          * "The full packet must be contained within the same cache line."
8839          *
8840          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8841          * cacheline, if we ever start emitting more commands before
8842          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8843          * then do the cacheline alignment, and finally emit the
8844          * MI_DISPLAY_FLIP.
8845          */
8846         ret = intel_ring_cacheline_align(ring);
8847         if (ret)
8848                 goto err_unpin;
8849
8850         ret = intel_ring_begin(ring, len);
8851         if (ret)
8852                 goto err_unpin;
8853
8854         /* Unmask the flip-done completion message. Note that the bspec says that
8855          * we should do this for both the BCS and RCS, and that we must not unmask
8856          * more than one flip event at any time (or ensure that one flip message
8857          * can be sent by waiting for flip-done prior to queueing new flips).
8858          * Experimentation says that BCS works despite DERRMR masking all
8859          * flip-done completion events and that unmasking all planes at once
8860          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8861          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8862          */
8863         if (ring->id == RCS) {
8864                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8865                 intel_ring_emit(ring, DERRMR);
8866                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8867                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8868                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8869                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8870                                 MI_SRM_LRM_GLOBAL_GTT);
8871                 intel_ring_emit(ring, DERRMR);
8872                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8873         }
8874
8875         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8876         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8877         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8878         intel_ring_emit(ring, (MI_NOOP));
8879
8880         intel_mark_page_flip_active(intel_crtc);
8881         __intel_ring_advance(ring);
8882         return 0;
8883
8884 err_unpin:
8885         intel_unpin_fb_obj(obj);
8886 err:
8887         return ret;
8888 }
8889
8890 static int intel_default_queue_flip(struct drm_device *dev,
8891                                     struct drm_crtc *crtc,
8892                                     struct drm_framebuffer *fb,
8893                                     struct drm_i915_gem_object *obj,
8894                                     uint32_t flags)
8895 {
8896         return -ENODEV;
8897 }
8898
8899 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8900                                 struct drm_framebuffer *fb,
8901                                 struct drm_pending_vblank_event *event,
8902                                 uint32_t page_flip_flags)
8903 {
8904         struct drm_device *dev = crtc->dev;
8905         struct drm_i915_private *dev_priv = dev->dev_private;
8906         struct drm_framebuffer *old_fb = crtc->fb;
8907         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8909         struct intel_unpin_work *work;
8910         unsigned long flags;
8911         int ret;
8912
8913         /* Can't change pixel format via MI display flips. */
8914         if (fb->pixel_format != crtc->fb->pixel_format)
8915                 return -EINVAL;
8916
8917         /*
8918          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8919          * Note that pitch changes could also affect these register.
8920          */
8921         if (INTEL_INFO(dev)->gen > 3 &&
8922             (fb->offsets[0] != crtc->fb->offsets[0] ||
8923              fb->pitches[0] != crtc->fb->pitches[0]))
8924                 return -EINVAL;
8925
8926         if (i915_terminally_wedged(&dev_priv->gpu_error))
8927                 goto out_hang;
8928
8929         work = kzalloc(sizeof(*work), GFP_KERNEL);
8930         if (work == NULL)
8931                 return -ENOMEM;
8932
8933         work->event = event;
8934         work->crtc = crtc;
8935         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8936         INIT_WORK(&work->work, intel_unpin_work_fn);
8937
8938         ret = drm_vblank_get(dev, intel_crtc->pipe);
8939         if (ret)
8940                 goto free_work;
8941
8942         /* We borrow the event spin lock for protecting unpin_work */
8943         spin_lock_irqsave(&dev->event_lock, flags);
8944         if (intel_crtc->unpin_work) {
8945                 spin_unlock_irqrestore(&dev->event_lock, flags);
8946                 kfree(work);
8947                 drm_vblank_put(dev, intel_crtc->pipe);
8948
8949                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8950                 return -EBUSY;
8951         }
8952         intel_crtc->unpin_work = work;
8953         spin_unlock_irqrestore(&dev->event_lock, flags);
8954
8955         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8956                 flush_workqueue(dev_priv->wq);
8957
8958         ret = i915_mutex_lock_interruptible(dev);
8959         if (ret)
8960                 goto cleanup;
8961
8962         /* Reference the objects for the scheduled work. */
8963         drm_gem_object_reference(&work->old_fb_obj->base);
8964         drm_gem_object_reference(&obj->base);
8965
8966         crtc->fb = fb;
8967
8968         work->pending_flip_obj = obj;
8969
8970         work->enable_stall_check = true;
8971
8972         atomic_inc(&intel_crtc->unpin_work_count);
8973         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8974
8975         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8976         if (ret)
8977                 goto cleanup_pending;
8978
8979         intel_disable_fbc(dev);
8980         intel_mark_fb_busy(obj, NULL);
8981         mutex_unlock(&dev->struct_mutex);
8982
8983         trace_i915_flip_request(intel_crtc->plane, obj);
8984
8985         return 0;
8986
8987 cleanup_pending:
8988         atomic_dec(&intel_crtc->unpin_work_count);
8989         crtc->fb = old_fb;
8990         drm_gem_object_unreference(&work->old_fb_obj->base);
8991         drm_gem_object_unreference(&obj->base);
8992         mutex_unlock(&dev->struct_mutex);
8993
8994 cleanup:
8995         spin_lock_irqsave(&dev->event_lock, flags);
8996         intel_crtc->unpin_work = NULL;
8997         spin_unlock_irqrestore(&dev->event_lock, flags);
8998
8999         drm_vblank_put(dev, intel_crtc->pipe);
9000 free_work:
9001         kfree(work);
9002
9003         if (ret == -EIO) {
9004 out_hang:
9005                 intel_crtc_wait_for_pending_flips(crtc);
9006                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9007                 if (ret == 0 && event)
9008                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9009         }
9010         return ret;
9011 }
9012
9013 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9014         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9015         .load_lut = intel_crtc_load_lut,
9016 };
9017
9018 /**
9019  * intel_modeset_update_staged_output_state
9020  *
9021  * Updates the staged output configuration state, e.g. after we've read out the
9022  * current hw state.
9023  */
9024 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9025 {
9026         struct intel_crtc *crtc;
9027         struct intel_encoder *encoder;
9028         struct intel_connector *connector;
9029
9030         list_for_each_entry(connector, &dev->mode_config.connector_list,
9031                             base.head) {
9032                 connector->new_encoder =
9033                         to_intel_encoder(connector->base.encoder);
9034         }
9035
9036         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9037                             base.head) {
9038                 encoder->new_crtc =
9039                         to_intel_crtc(encoder->base.crtc);
9040         }
9041
9042         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9043                             base.head) {
9044                 crtc->new_enabled = crtc->base.enabled;
9045
9046                 if (crtc->new_enabled)
9047                         crtc->new_config = &crtc->config;
9048                 else
9049                         crtc->new_config = NULL;
9050         }
9051 }
9052
9053 /**
9054  * intel_modeset_commit_output_state
9055  *
9056  * This function copies the stage display pipe configuration to the real one.
9057  */
9058 static void intel_modeset_commit_output_state(struct drm_device *dev)
9059 {
9060         struct intel_crtc *crtc;
9061         struct intel_encoder *encoder;
9062         struct intel_connector *connector;
9063
9064         list_for_each_entry(connector, &dev->mode_config.connector_list,
9065                             base.head) {
9066                 connector->base.encoder = &connector->new_encoder->base;
9067         }
9068
9069         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9070                             base.head) {
9071                 encoder->base.crtc = &encoder->new_crtc->base;
9072         }
9073
9074         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9075                             base.head) {
9076                 crtc->base.enabled = crtc->new_enabled;
9077         }
9078 }
9079
9080 static void
9081 connected_sink_compute_bpp(struct intel_connector * connector,
9082                            struct intel_crtc_config *pipe_config)
9083 {
9084         int bpp = pipe_config->pipe_bpp;
9085
9086         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9087                 connector->base.base.id,
9088                 drm_get_connector_name(&connector->base));
9089
9090         /* Don't use an invalid EDID bpc value */
9091         if (connector->base.display_info.bpc &&
9092             connector->base.display_info.bpc * 3 < bpp) {
9093                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9094                               bpp, connector->base.display_info.bpc*3);
9095                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9096         }
9097
9098         /* Clamp bpp to 8 on screens without EDID 1.4 */
9099         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9100                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9101                               bpp);
9102                 pipe_config->pipe_bpp = 24;
9103         }
9104 }
9105
9106 static int
9107 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9108                           struct drm_framebuffer *fb,
9109                           struct intel_crtc_config *pipe_config)
9110 {
9111         struct drm_device *dev = crtc->base.dev;
9112         struct intel_connector *connector;
9113         int bpp;
9114
9115         switch (fb->pixel_format) {
9116         case DRM_FORMAT_C8:
9117                 bpp = 8*3; /* since we go through a colormap */
9118                 break;
9119         case DRM_FORMAT_XRGB1555:
9120         case DRM_FORMAT_ARGB1555:
9121                 /* checked in intel_framebuffer_init already */
9122                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9123                         return -EINVAL;
9124         case DRM_FORMAT_RGB565:
9125                 bpp = 6*3; /* min is 18bpp */
9126                 break;
9127         case DRM_FORMAT_XBGR8888:
9128         case DRM_FORMAT_ABGR8888:
9129                 /* checked in intel_framebuffer_init already */
9130                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9131                         return -EINVAL;
9132         case DRM_FORMAT_XRGB8888:
9133         case DRM_FORMAT_ARGB8888:
9134                 bpp = 8*3;
9135                 break;
9136         case DRM_FORMAT_XRGB2101010:
9137         case DRM_FORMAT_ARGB2101010:
9138         case DRM_FORMAT_XBGR2101010:
9139         case DRM_FORMAT_ABGR2101010:
9140                 /* checked in intel_framebuffer_init already */
9141                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9142                         return -EINVAL;
9143                 bpp = 10*3;
9144                 break;
9145         /* TODO: gen4+ supports 16 bpc floating point, too. */
9146         default:
9147                 DRM_DEBUG_KMS("unsupported depth\n");
9148                 return -EINVAL;
9149         }
9150
9151         pipe_config->pipe_bpp = bpp;
9152
9153         /* Clamp display bpp to EDID value */
9154         list_for_each_entry(connector, &dev->mode_config.connector_list,
9155                             base.head) {
9156                 if (!connector->new_encoder ||
9157                     connector->new_encoder->new_crtc != crtc)
9158                         continue;
9159
9160                 connected_sink_compute_bpp(connector, pipe_config);
9161         }
9162
9163         return bpp;
9164 }
9165
9166 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9167 {
9168         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9169                         "type: 0x%x flags: 0x%x\n",
9170                 mode->crtc_clock,
9171                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9172                 mode->crtc_hsync_end, mode->crtc_htotal,
9173                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9174                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9175 }
9176
9177 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9178                                    struct intel_crtc_config *pipe_config,
9179                                    const char *context)
9180 {
9181         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9182                       context, pipe_name(crtc->pipe));
9183
9184         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9185         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9186                       pipe_config->pipe_bpp, pipe_config->dither);
9187         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9188                       pipe_config->has_pch_encoder,
9189                       pipe_config->fdi_lanes,
9190                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9191                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9192                       pipe_config->fdi_m_n.tu);
9193         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9194                       pipe_config->has_dp_encoder,
9195                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9196                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9197                       pipe_config->dp_m_n.tu);
9198         DRM_DEBUG_KMS("requested mode:\n");
9199         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9200         DRM_DEBUG_KMS("adjusted mode:\n");
9201         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9202         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9203         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9204         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9205                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9206         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9207                       pipe_config->gmch_pfit.control,
9208                       pipe_config->gmch_pfit.pgm_ratios,
9209                       pipe_config->gmch_pfit.lvds_border_bits);
9210         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9211                       pipe_config->pch_pfit.pos,
9212                       pipe_config->pch_pfit.size,
9213                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9214         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9215         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9216 }
9217
9218 static bool encoders_cloneable(const struct intel_encoder *a,
9219                                const struct intel_encoder *b)
9220 {
9221         /* masks could be asymmetric, so check both ways */
9222         return a == b || (a->cloneable & (1 << b->type) &&
9223                           b->cloneable & (1 << a->type));
9224 }
9225
9226 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9227                                          struct intel_encoder *encoder)
9228 {
9229         struct drm_device *dev = crtc->base.dev;
9230         struct intel_encoder *source_encoder;
9231
9232         list_for_each_entry(source_encoder,
9233                             &dev->mode_config.encoder_list, base.head) {
9234                 if (source_encoder->new_crtc != crtc)
9235                         continue;
9236
9237                 if (!encoders_cloneable(encoder, source_encoder))
9238                         return false;
9239         }
9240
9241         return true;
9242 }
9243
9244 static bool check_encoder_cloning(struct intel_crtc *crtc)
9245 {
9246         struct drm_device *dev = crtc->base.dev;
9247         struct intel_encoder *encoder;
9248
9249         list_for_each_entry(encoder,
9250                             &dev->mode_config.encoder_list, base.head) {
9251                 if (encoder->new_crtc != crtc)
9252                         continue;
9253
9254                 if (!check_single_encoder_cloning(crtc, encoder))
9255                         return false;
9256         }
9257
9258         return true;
9259 }
9260
9261 static struct intel_crtc_config *
9262 intel_modeset_pipe_config(struct drm_crtc *crtc,
9263                           struct drm_framebuffer *fb,
9264                           struct drm_display_mode *mode)
9265 {
9266         struct drm_device *dev = crtc->dev;
9267         struct intel_encoder *encoder;
9268         struct intel_crtc_config *pipe_config;
9269         int plane_bpp, ret = -EINVAL;
9270         bool retry = true;
9271
9272         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9273                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9274                 return ERR_PTR(-EINVAL);
9275         }
9276
9277         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9278         if (!pipe_config)
9279                 return ERR_PTR(-ENOMEM);
9280
9281         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9282         drm_mode_copy(&pipe_config->requested_mode, mode);
9283
9284         pipe_config->cpu_transcoder =
9285                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9286         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9287
9288         /*
9289          * Sanitize sync polarity flags based on requested ones. If neither
9290          * positive or negative polarity is requested, treat this as meaning
9291          * negative polarity.
9292          */
9293         if (!(pipe_config->adjusted_mode.flags &
9294               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9295                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9296
9297         if (!(pipe_config->adjusted_mode.flags &
9298               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9299                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9300
9301         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9302          * plane pixel format and any sink constraints into account. Returns the
9303          * source plane bpp so that dithering can be selected on mismatches
9304          * after encoders and crtc also have had their say. */
9305         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9306                                               fb, pipe_config);
9307         if (plane_bpp < 0)
9308                 goto fail;
9309
9310         /*
9311          * Determine the real pipe dimensions. Note that stereo modes can
9312          * increase the actual pipe size due to the frame doubling and
9313          * insertion of additional space for blanks between the frame. This
9314          * is stored in the crtc timings. We use the requested mode to do this
9315          * computation to clearly distinguish it from the adjusted mode, which
9316          * can be changed by the connectors in the below retry loop.
9317          */
9318         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9319         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9320         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9321
9322 encoder_retry:
9323         /* Ensure the port clock defaults are reset when retrying. */
9324         pipe_config->port_clock = 0;
9325         pipe_config->pixel_multiplier = 1;
9326
9327         /* Fill in default crtc timings, allow encoders to overwrite them. */
9328         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9329
9330         /* Pass our mode to the connectors and the CRTC to give them a chance to
9331          * adjust it according to limitations or connector properties, and also
9332          * a chance to reject the mode entirely.
9333          */
9334         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9335                             base.head) {
9336
9337                 if (&encoder->new_crtc->base != crtc)
9338                         continue;
9339
9340                 if (!(encoder->compute_config(encoder, pipe_config))) {
9341                         DRM_DEBUG_KMS("Encoder config failure\n");
9342                         goto fail;
9343                 }
9344         }
9345
9346         /* Set default port clock if not overwritten by the encoder. Needs to be
9347          * done afterwards in case the encoder adjusts the mode. */
9348         if (!pipe_config->port_clock)
9349                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9350                         * pipe_config->pixel_multiplier;
9351
9352         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9353         if (ret < 0) {
9354                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9355                 goto fail;
9356         }
9357
9358         if (ret == RETRY) {
9359                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9360                         ret = -EINVAL;
9361                         goto fail;
9362                 }
9363
9364                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9365                 retry = false;
9366                 goto encoder_retry;
9367         }
9368
9369         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9370         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9371                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9372
9373         return pipe_config;
9374 fail:
9375         kfree(pipe_config);
9376         return ERR_PTR(ret);
9377 }
9378
9379 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9380  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9381 static void
9382 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9383                              unsigned *prepare_pipes, unsigned *disable_pipes)
9384 {
9385         struct intel_crtc *intel_crtc;
9386         struct drm_device *dev = crtc->dev;
9387         struct intel_encoder *encoder;
9388         struct intel_connector *connector;
9389         struct drm_crtc *tmp_crtc;
9390
9391         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9392
9393         /* Check which crtcs have changed outputs connected to them, these need
9394          * to be part of the prepare_pipes mask. We don't (yet) support global
9395          * modeset across multiple crtcs, so modeset_pipes will only have one
9396          * bit set at most. */
9397         list_for_each_entry(connector, &dev->mode_config.connector_list,
9398                             base.head) {
9399                 if (connector->base.encoder == &connector->new_encoder->base)
9400                         continue;
9401
9402                 if (connector->base.encoder) {
9403                         tmp_crtc = connector->base.encoder->crtc;
9404
9405                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9406                 }
9407
9408                 if (connector->new_encoder)
9409                         *prepare_pipes |=
9410                                 1 << connector->new_encoder->new_crtc->pipe;
9411         }
9412
9413         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9414                             base.head) {
9415                 if (encoder->base.crtc == &encoder->new_crtc->base)
9416                         continue;
9417
9418                 if (encoder->base.crtc) {
9419                         tmp_crtc = encoder->base.crtc;
9420
9421                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9422                 }
9423
9424                 if (encoder->new_crtc)
9425                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9426         }
9427
9428         /* Check for pipes that will be enabled/disabled ... */
9429         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9430                             base.head) {
9431                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9432                         continue;
9433
9434                 if (!intel_crtc->new_enabled)
9435                         *disable_pipes |= 1 << intel_crtc->pipe;
9436                 else
9437                         *prepare_pipes |= 1 << intel_crtc->pipe;
9438         }
9439
9440
9441         /* set_mode is also used to update properties on life display pipes. */
9442         intel_crtc = to_intel_crtc(crtc);
9443         if (intel_crtc->new_enabled)
9444                 *prepare_pipes |= 1 << intel_crtc->pipe;
9445
9446         /*
9447          * For simplicity do a full modeset on any pipe where the output routing
9448          * changed. We could be more clever, but that would require us to be
9449          * more careful with calling the relevant encoder->mode_set functions.
9450          */
9451         if (*prepare_pipes)
9452                 *modeset_pipes = *prepare_pipes;
9453
9454         /* ... and mask these out. */
9455         *modeset_pipes &= ~(*disable_pipes);
9456         *prepare_pipes &= ~(*disable_pipes);
9457
9458         /*
9459          * HACK: We don't (yet) fully support global modesets. intel_set_config
9460          * obies this rule, but the modeset restore mode of
9461          * intel_modeset_setup_hw_state does not.
9462          */
9463         *modeset_pipes &= 1 << intel_crtc->pipe;
9464         *prepare_pipes &= 1 << intel_crtc->pipe;
9465
9466         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9467                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9468 }
9469
9470 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9471 {
9472         struct drm_encoder *encoder;
9473         struct drm_device *dev = crtc->dev;
9474
9475         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9476                 if (encoder->crtc == crtc)
9477                         return true;
9478
9479         return false;
9480 }
9481
9482 static void
9483 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9484 {
9485         struct intel_encoder *intel_encoder;
9486         struct intel_crtc *intel_crtc;
9487         struct drm_connector *connector;
9488
9489         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9490                             base.head) {
9491                 if (!intel_encoder->base.crtc)
9492                         continue;
9493
9494                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9495
9496                 if (prepare_pipes & (1 << intel_crtc->pipe))
9497                         intel_encoder->connectors_active = false;
9498         }
9499
9500         intel_modeset_commit_output_state(dev);
9501
9502         /* Double check state. */
9503         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9504                             base.head) {
9505                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9506                 WARN_ON(intel_crtc->new_config &&
9507                         intel_crtc->new_config != &intel_crtc->config);
9508                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9509         }
9510
9511         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9512                 if (!connector->encoder || !connector->encoder->crtc)
9513                         continue;
9514
9515                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9516
9517                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9518                         struct drm_property *dpms_property =
9519                                 dev->mode_config.dpms_property;
9520
9521                         connector->dpms = DRM_MODE_DPMS_ON;
9522                         drm_object_property_set_value(&connector->base,
9523                                                          dpms_property,
9524                                                          DRM_MODE_DPMS_ON);
9525
9526                         intel_encoder = to_intel_encoder(connector->encoder);
9527                         intel_encoder->connectors_active = true;
9528                 }
9529         }
9530
9531 }
9532
9533 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9534 {
9535         int diff;
9536
9537         if (clock1 == clock2)
9538                 return true;
9539
9540         if (!clock1 || !clock2)
9541                 return false;
9542
9543         diff = abs(clock1 - clock2);
9544
9545         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9546                 return true;
9547
9548         return false;
9549 }
9550
9551 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9552         list_for_each_entry((intel_crtc), \
9553                             &(dev)->mode_config.crtc_list, \
9554                             base.head) \
9555                 if (mask & (1 <<(intel_crtc)->pipe))
9556
9557 static bool
9558 intel_pipe_config_compare(struct drm_device *dev,
9559                           struct intel_crtc_config *current_config,
9560                           struct intel_crtc_config *pipe_config)
9561 {
9562 #define PIPE_CONF_CHECK_X(name) \
9563         if (current_config->name != pipe_config->name) { \
9564                 DRM_ERROR("mismatch in " #name " " \
9565                           "(expected 0x%08x, found 0x%08x)\n", \
9566                           current_config->name, \
9567                           pipe_config->name); \
9568                 return false; \
9569         }
9570
9571 #define PIPE_CONF_CHECK_I(name) \
9572         if (current_config->name != pipe_config->name) { \
9573                 DRM_ERROR("mismatch in " #name " " \
9574                           "(expected %i, found %i)\n", \
9575                           current_config->name, \
9576                           pipe_config->name); \
9577                 return false; \
9578         }
9579
9580 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9581         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9582                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9583                           "(expected %i, found %i)\n", \
9584                           current_config->name & (mask), \
9585                           pipe_config->name & (mask)); \
9586                 return false; \
9587         }
9588
9589 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9590         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9591                 DRM_ERROR("mismatch in " #name " " \
9592                           "(expected %i, found %i)\n", \
9593                           current_config->name, \
9594                           pipe_config->name); \
9595                 return false; \
9596         }
9597
9598 #define PIPE_CONF_QUIRK(quirk)  \
9599         ((current_config->quirks | pipe_config->quirks) & (quirk))
9600
9601         PIPE_CONF_CHECK_I(cpu_transcoder);
9602
9603         PIPE_CONF_CHECK_I(has_pch_encoder);
9604         PIPE_CONF_CHECK_I(fdi_lanes);
9605         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9606         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9607         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9608         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9609         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9610
9611         PIPE_CONF_CHECK_I(has_dp_encoder);
9612         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9613         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9614         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9615         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9616         PIPE_CONF_CHECK_I(dp_m_n.tu);
9617
9618         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9619         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9620         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9621         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9622         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9623         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9624
9625         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9626         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9627         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9628         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9629         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9630         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9631
9632         PIPE_CONF_CHECK_I(pixel_multiplier);
9633
9634         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9635                               DRM_MODE_FLAG_INTERLACE);
9636
9637         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9638                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9639                                       DRM_MODE_FLAG_PHSYNC);
9640                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9641                                       DRM_MODE_FLAG_NHSYNC);
9642                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9643                                       DRM_MODE_FLAG_PVSYNC);
9644                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9645                                       DRM_MODE_FLAG_NVSYNC);
9646         }
9647
9648         PIPE_CONF_CHECK_I(pipe_src_w);
9649         PIPE_CONF_CHECK_I(pipe_src_h);
9650
9651         PIPE_CONF_CHECK_I(gmch_pfit.control);
9652         /* pfit ratios are autocomputed by the hw on gen4+ */
9653         if (INTEL_INFO(dev)->gen < 4)
9654                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9655         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9656         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9657         if (current_config->pch_pfit.enabled) {
9658                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9659                 PIPE_CONF_CHECK_I(pch_pfit.size);
9660         }
9661
9662         /* BDW+ don't expose a synchronous way to read the state */
9663         if (IS_HASWELL(dev))
9664                 PIPE_CONF_CHECK_I(ips_enabled);
9665
9666         PIPE_CONF_CHECK_I(double_wide);
9667
9668         PIPE_CONF_CHECK_I(shared_dpll);
9669         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9670         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9671         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9672         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9673
9674         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9675                 PIPE_CONF_CHECK_I(pipe_bpp);
9676
9677         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9678         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9679
9680 #undef PIPE_CONF_CHECK_X
9681 #undef PIPE_CONF_CHECK_I
9682 #undef PIPE_CONF_CHECK_FLAGS
9683 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9684 #undef PIPE_CONF_QUIRK
9685
9686         return true;
9687 }
9688
9689 static void
9690 check_connector_state(struct drm_device *dev)
9691 {
9692         struct intel_connector *connector;
9693
9694         list_for_each_entry(connector, &dev->mode_config.connector_list,
9695                             base.head) {
9696                 /* This also checks the encoder/connector hw state with the
9697                  * ->get_hw_state callbacks. */
9698                 intel_connector_check_state(connector);
9699
9700                 WARN(&connector->new_encoder->base != connector->base.encoder,
9701                      "connector's staged encoder doesn't match current encoder\n");
9702         }
9703 }
9704
9705 static void
9706 check_encoder_state(struct drm_device *dev)
9707 {
9708         struct intel_encoder *encoder;
9709         struct intel_connector *connector;
9710
9711         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9712                             base.head) {
9713                 bool enabled = false;
9714                 bool active = false;
9715                 enum pipe pipe, tracked_pipe;
9716
9717                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9718                               encoder->base.base.id,
9719                               drm_get_encoder_name(&encoder->base));
9720
9721                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9722                      "encoder's stage crtc doesn't match current crtc\n");
9723                 WARN(encoder->connectors_active && !encoder->base.crtc,
9724                      "encoder's active_connectors set, but no crtc\n");
9725
9726                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9727                                     base.head) {
9728                         if (connector->base.encoder != &encoder->base)
9729                                 continue;
9730                         enabled = true;
9731                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9732                                 active = true;
9733                 }
9734                 WARN(!!encoder->base.crtc != enabled,
9735                      "encoder's enabled state mismatch "
9736                      "(expected %i, found %i)\n",
9737                      !!encoder->base.crtc, enabled);
9738                 WARN(active && !encoder->base.crtc,
9739                      "active encoder with no crtc\n");
9740
9741                 WARN(encoder->connectors_active != active,
9742                      "encoder's computed active state doesn't match tracked active state "
9743                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9744
9745                 active = encoder->get_hw_state(encoder, &pipe);
9746                 WARN(active != encoder->connectors_active,
9747                      "encoder's hw state doesn't match sw tracking "
9748                      "(expected %i, found %i)\n",
9749                      encoder->connectors_active, active);
9750
9751                 if (!encoder->base.crtc)
9752                         continue;
9753
9754                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9755                 WARN(active && pipe != tracked_pipe,
9756                      "active encoder's pipe doesn't match"
9757                      "(expected %i, found %i)\n",
9758                      tracked_pipe, pipe);
9759
9760         }
9761 }
9762
9763 static void
9764 check_crtc_state(struct drm_device *dev)
9765 {
9766         struct drm_i915_private *dev_priv = dev->dev_private;
9767         struct intel_crtc *crtc;
9768         struct intel_encoder *encoder;
9769         struct intel_crtc_config pipe_config;
9770
9771         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9772                             base.head) {
9773                 bool enabled = false;
9774                 bool active = false;
9775
9776                 memset(&pipe_config, 0, sizeof(pipe_config));
9777
9778                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9779                               crtc->base.base.id);
9780
9781                 WARN(crtc->active && !crtc->base.enabled,
9782                      "active crtc, but not enabled in sw tracking\n");
9783
9784                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9785                                     base.head) {
9786                         if (encoder->base.crtc != &crtc->base)
9787                                 continue;
9788                         enabled = true;
9789                         if (encoder->connectors_active)
9790                                 active = true;
9791                 }
9792
9793                 WARN(active != crtc->active,
9794                      "crtc's computed active state doesn't match tracked active state "
9795                      "(expected %i, found %i)\n", active, crtc->active);
9796                 WARN(enabled != crtc->base.enabled,
9797                      "crtc's computed enabled state doesn't match tracked enabled state "
9798                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9799
9800                 active = dev_priv->display.get_pipe_config(crtc,
9801                                                            &pipe_config);
9802
9803                 /* hw state is inconsistent with the pipe A quirk */
9804                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9805                         active = crtc->active;
9806
9807                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9808                                     base.head) {
9809                         enum pipe pipe;
9810                         if (encoder->base.crtc != &crtc->base)
9811                                 continue;
9812                         if (encoder->get_hw_state(encoder, &pipe))
9813                                 encoder->get_config(encoder, &pipe_config);
9814                 }
9815
9816                 WARN(crtc->active != active,
9817                      "crtc active state doesn't match with hw state "
9818                      "(expected %i, found %i)\n", crtc->active, active);
9819
9820                 if (active &&
9821                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9822                         WARN(1, "pipe state doesn't match!\n");
9823                         intel_dump_pipe_config(crtc, &pipe_config,
9824                                                "[hw state]");
9825                         intel_dump_pipe_config(crtc, &crtc->config,
9826                                                "[sw state]");
9827                 }
9828         }
9829 }
9830
9831 static void
9832 check_shared_dpll_state(struct drm_device *dev)
9833 {
9834         struct drm_i915_private *dev_priv = dev->dev_private;
9835         struct intel_crtc *crtc;
9836         struct intel_dpll_hw_state dpll_hw_state;
9837         int i;
9838
9839         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9840                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9841                 int enabled_crtcs = 0, active_crtcs = 0;
9842                 bool active;
9843
9844                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9845
9846                 DRM_DEBUG_KMS("%s\n", pll->name);
9847
9848                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9849
9850                 WARN(pll->active > pll->refcount,
9851                      "more active pll users than references: %i vs %i\n",
9852                      pll->active, pll->refcount);
9853                 WARN(pll->active && !pll->on,
9854                      "pll in active use but not on in sw tracking\n");
9855                 WARN(pll->on && !pll->active,
9856                      "pll in on but not on in use in sw tracking\n");
9857                 WARN(pll->on != active,
9858                      "pll on state mismatch (expected %i, found %i)\n",
9859                      pll->on, active);
9860
9861                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9862                                     base.head) {
9863                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9864                                 enabled_crtcs++;
9865                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9866                                 active_crtcs++;
9867                 }
9868                 WARN(pll->active != active_crtcs,
9869                      "pll active crtcs mismatch (expected %i, found %i)\n",
9870                      pll->active, active_crtcs);
9871                 WARN(pll->refcount != enabled_crtcs,
9872                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9873                      pll->refcount, enabled_crtcs);
9874
9875                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9876                                        sizeof(dpll_hw_state)),
9877                      "pll hw state mismatch\n");
9878         }
9879 }
9880
9881 void
9882 intel_modeset_check_state(struct drm_device *dev)
9883 {
9884         check_connector_state(dev);
9885         check_encoder_state(dev);
9886         check_crtc_state(dev);
9887         check_shared_dpll_state(dev);
9888 }
9889
9890 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9891                                      int dotclock)
9892 {
9893         /*
9894          * FDI already provided one idea for the dotclock.
9895          * Yell if the encoder disagrees.
9896          */
9897         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9898              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9899              pipe_config->adjusted_mode.crtc_clock, dotclock);
9900 }
9901
9902 static int __intel_set_mode(struct drm_crtc *crtc,
9903                             struct drm_display_mode *mode,
9904                             int x, int y, struct drm_framebuffer *fb)
9905 {
9906         struct drm_device *dev = crtc->dev;
9907         struct drm_i915_private *dev_priv = dev->dev_private;
9908         struct drm_display_mode *saved_mode;
9909         struct intel_crtc_config *pipe_config = NULL;
9910         struct intel_crtc *intel_crtc;
9911         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9912         int ret = 0;
9913
9914         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9915         if (!saved_mode)
9916                 return -ENOMEM;
9917
9918         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9919                                      &prepare_pipes, &disable_pipes);
9920
9921         *saved_mode = crtc->mode;
9922
9923         /* Hack: Because we don't (yet) support global modeset on multiple
9924          * crtcs, we don't keep track of the new mode for more than one crtc.
9925          * Hence simply check whether any bit is set in modeset_pipes in all the
9926          * pieces of code that are not yet converted to deal with mutliple crtcs
9927          * changing their mode at the same time. */
9928         if (modeset_pipes) {
9929                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9930                 if (IS_ERR(pipe_config)) {
9931                         ret = PTR_ERR(pipe_config);
9932                         pipe_config = NULL;
9933
9934                         goto out;
9935                 }
9936                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9937                                        "[modeset]");
9938                 to_intel_crtc(crtc)->new_config = pipe_config;
9939         }
9940
9941         /*
9942          * See if the config requires any additional preparation, e.g.
9943          * to adjust global state with pipes off.  We need to do this
9944          * here so we can get the modeset_pipe updated config for the new
9945          * mode set on this crtc.  For other crtcs we need to use the
9946          * adjusted_mode bits in the crtc directly.
9947          */
9948         if (IS_VALLEYVIEW(dev)) {
9949                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9950
9951                 /* may have added more to prepare_pipes than we should */
9952                 prepare_pipes &= ~disable_pipes;
9953         }
9954
9955         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9956                 intel_crtc_disable(&intel_crtc->base);
9957
9958         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9959                 if (intel_crtc->base.enabled)
9960                         dev_priv->display.crtc_disable(&intel_crtc->base);
9961         }
9962
9963         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9964          * to set it here already despite that we pass it down the callchain.
9965          */
9966         if (modeset_pipes) {
9967                 crtc->mode = *mode;
9968                 /* mode_set/enable/disable functions rely on a correct pipe
9969                  * config. */
9970                 to_intel_crtc(crtc)->config = *pipe_config;
9971                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9972
9973                 /*
9974                  * Calculate and store various constants which
9975                  * are later needed by vblank and swap-completion
9976                  * timestamping. They are derived from true hwmode.
9977                  */
9978                 drm_calc_timestamping_constants(crtc,
9979                                                 &pipe_config->adjusted_mode);
9980         }
9981
9982         /* Only after disabling all output pipelines that will be changed can we
9983          * update the the output configuration. */
9984         intel_modeset_update_state(dev, prepare_pipes);
9985
9986         if (dev_priv->display.modeset_global_resources)
9987                 dev_priv->display.modeset_global_resources(dev);
9988
9989         /* Set up the DPLL and any encoders state that needs to adjust or depend
9990          * on the DPLL.
9991          */
9992         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9993                 ret = intel_crtc_mode_set(&intel_crtc->base,
9994                                           x, y, fb);
9995                 if (ret)
9996                         goto done;
9997         }
9998
9999         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10000         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10001                 dev_priv->display.crtc_enable(&intel_crtc->base);
10002
10003         /* FIXME: add subpixel order */
10004 done:
10005         if (ret && crtc->enabled)
10006                 crtc->mode = *saved_mode;
10007
10008 out:
10009         kfree(pipe_config);
10010         kfree(saved_mode);
10011         return ret;
10012 }
10013
10014 static int intel_set_mode(struct drm_crtc *crtc,
10015                           struct drm_display_mode *mode,
10016                           int x, int y, struct drm_framebuffer *fb)
10017 {
10018         int ret;
10019
10020         ret = __intel_set_mode(crtc, mode, x, y, fb);
10021
10022         if (ret == 0)
10023                 intel_modeset_check_state(crtc->dev);
10024
10025         return ret;
10026 }
10027
10028 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10029 {
10030         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
10031 }
10032
10033 #undef for_each_intel_crtc_masked
10034
10035 static void intel_set_config_free(struct intel_set_config *config)
10036 {
10037         if (!config)
10038                 return;
10039
10040         kfree(config->save_connector_encoders);
10041         kfree(config->save_encoder_crtcs);
10042         kfree(config->save_crtc_enabled);
10043         kfree(config);
10044 }
10045
10046 static int intel_set_config_save_state(struct drm_device *dev,
10047                                        struct intel_set_config *config)
10048 {
10049         struct drm_crtc *crtc;
10050         struct drm_encoder *encoder;
10051         struct drm_connector *connector;
10052         int count;
10053
10054         config->save_crtc_enabled =
10055                 kcalloc(dev->mode_config.num_crtc,
10056                         sizeof(bool), GFP_KERNEL);
10057         if (!config->save_crtc_enabled)
10058                 return -ENOMEM;
10059
10060         config->save_encoder_crtcs =
10061                 kcalloc(dev->mode_config.num_encoder,
10062                         sizeof(struct drm_crtc *), GFP_KERNEL);
10063         if (!config->save_encoder_crtcs)
10064                 return -ENOMEM;
10065
10066         config->save_connector_encoders =
10067                 kcalloc(dev->mode_config.num_connector,
10068                         sizeof(struct drm_encoder *), GFP_KERNEL);
10069         if (!config->save_connector_encoders)
10070                 return -ENOMEM;
10071
10072         /* Copy data. Note that driver private data is not affected.
10073          * Should anything bad happen only the expected state is
10074          * restored, not the drivers personal bookkeeping.
10075          */
10076         count = 0;
10077         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10078                 config->save_crtc_enabled[count++] = crtc->enabled;
10079         }
10080
10081         count = 0;
10082         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10083                 config->save_encoder_crtcs[count++] = encoder->crtc;
10084         }
10085
10086         count = 0;
10087         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10088                 config->save_connector_encoders[count++] = connector->encoder;
10089         }
10090
10091         return 0;
10092 }
10093
10094 static void intel_set_config_restore_state(struct drm_device *dev,
10095                                            struct intel_set_config *config)
10096 {
10097         struct intel_crtc *crtc;
10098         struct intel_encoder *encoder;
10099         struct intel_connector *connector;
10100         int count;
10101
10102         count = 0;
10103         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10104                 crtc->new_enabled = config->save_crtc_enabled[count++];
10105
10106                 if (crtc->new_enabled)
10107                         crtc->new_config = &crtc->config;
10108                 else
10109                         crtc->new_config = NULL;
10110         }
10111
10112         count = 0;
10113         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10114                 encoder->new_crtc =
10115                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10116         }
10117
10118         count = 0;
10119         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10120                 connector->new_encoder =
10121                         to_intel_encoder(config->save_connector_encoders[count++]);
10122         }
10123 }
10124
10125 static bool
10126 is_crtc_connector_off(struct drm_mode_set *set)
10127 {
10128         int i;
10129
10130         if (set->num_connectors == 0)
10131                 return false;
10132
10133         if (WARN_ON(set->connectors == NULL))
10134                 return false;
10135
10136         for (i = 0; i < set->num_connectors; i++)
10137                 if (set->connectors[i]->encoder &&
10138                     set->connectors[i]->encoder->crtc == set->crtc &&
10139                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10140                         return true;
10141
10142         return false;
10143 }
10144
10145 static void
10146 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10147                                       struct intel_set_config *config)
10148 {
10149
10150         /* We should be able to check here if the fb has the same properties
10151          * and then just flip_or_move it */
10152         if (is_crtc_connector_off(set)) {
10153                 config->mode_changed = true;
10154         } else if (set->crtc->fb != set->fb) {
10155                 /* If we have no fb then treat it as a full mode set */
10156                 if (set->crtc->fb == NULL) {
10157                         struct intel_crtc *intel_crtc =
10158                                 to_intel_crtc(set->crtc);
10159
10160                         if (intel_crtc->active && i915.fastboot) {
10161                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10162                                 config->fb_changed = true;
10163                         } else {
10164                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10165                                 config->mode_changed = true;
10166                         }
10167                 } else if (set->fb == NULL) {
10168                         config->mode_changed = true;
10169                 } else if (set->fb->pixel_format !=
10170                            set->crtc->fb->pixel_format) {
10171                         config->mode_changed = true;
10172                 } else {
10173                         config->fb_changed = true;
10174                 }
10175         }
10176
10177         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10178                 config->fb_changed = true;
10179
10180         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10181                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10182                 drm_mode_debug_printmodeline(&set->crtc->mode);
10183                 drm_mode_debug_printmodeline(set->mode);
10184                 config->mode_changed = true;
10185         }
10186
10187         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10188                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10189 }
10190
10191 static int
10192 intel_modeset_stage_output_state(struct drm_device *dev,
10193                                  struct drm_mode_set *set,
10194                                  struct intel_set_config *config)
10195 {
10196         struct intel_connector *connector;
10197         struct intel_encoder *encoder;
10198         struct intel_crtc *crtc;
10199         int ro;
10200
10201         /* The upper layers ensure that we either disable a crtc or have a list
10202          * of connectors. For paranoia, double-check this. */
10203         WARN_ON(!set->fb && (set->num_connectors != 0));
10204         WARN_ON(set->fb && (set->num_connectors == 0));
10205
10206         list_for_each_entry(connector, &dev->mode_config.connector_list,
10207                             base.head) {
10208                 /* Otherwise traverse passed in connector list and get encoders
10209                  * for them. */
10210                 for (ro = 0; ro < set->num_connectors; ro++) {
10211                         if (set->connectors[ro] == &connector->base) {
10212                                 connector->new_encoder = connector->encoder;
10213                                 break;
10214                         }
10215                 }
10216
10217                 /* If we disable the crtc, disable all its connectors. Also, if
10218                  * the connector is on the changing crtc but not on the new
10219                  * connector list, disable it. */
10220                 if ((!set->fb || ro == set->num_connectors) &&
10221                     connector->base.encoder &&
10222                     connector->base.encoder->crtc == set->crtc) {
10223                         connector->new_encoder = NULL;
10224
10225                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10226                                 connector->base.base.id,
10227                                 drm_get_connector_name(&connector->base));
10228                 }
10229
10230
10231                 if (&connector->new_encoder->base != connector->base.encoder) {
10232                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10233                         config->mode_changed = true;
10234                 }
10235         }
10236         /* connector->new_encoder is now updated for all connectors. */
10237
10238         /* Update crtc of enabled connectors. */
10239         list_for_each_entry(connector, &dev->mode_config.connector_list,
10240                             base.head) {
10241                 struct drm_crtc *new_crtc;
10242
10243                 if (!connector->new_encoder)
10244                         continue;
10245
10246                 new_crtc = connector->new_encoder->base.crtc;
10247
10248                 for (ro = 0; ro < set->num_connectors; ro++) {
10249                         if (set->connectors[ro] == &connector->base)
10250                                 new_crtc = set->crtc;
10251                 }
10252
10253                 /* Make sure the new CRTC will work with the encoder */
10254                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10255                                          new_crtc)) {
10256                         return -EINVAL;
10257                 }
10258                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10259
10260                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10261                         connector->base.base.id,
10262                         drm_get_connector_name(&connector->base),
10263                         new_crtc->base.id);
10264         }
10265
10266         /* Check for any encoders that needs to be disabled. */
10267         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10268                             base.head) {
10269                 int num_connectors = 0;
10270                 list_for_each_entry(connector,
10271                                     &dev->mode_config.connector_list,
10272                                     base.head) {
10273                         if (connector->new_encoder == encoder) {
10274                                 WARN_ON(!connector->new_encoder->new_crtc);
10275                                 num_connectors++;
10276                         }
10277                 }
10278
10279                 if (num_connectors == 0)
10280                         encoder->new_crtc = NULL;
10281                 else if (num_connectors > 1)
10282                         return -EINVAL;
10283
10284                 /* Only now check for crtc changes so we don't miss encoders
10285                  * that will be disabled. */
10286                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10287                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10288                         config->mode_changed = true;
10289                 }
10290         }
10291         /* Now we've also updated encoder->new_crtc for all encoders. */
10292
10293         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10294                             base.head) {
10295                 crtc->new_enabled = false;
10296
10297                 list_for_each_entry(encoder,
10298                                     &dev->mode_config.encoder_list,
10299                                     base.head) {
10300                         if (encoder->new_crtc == crtc) {
10301                                 crtc->new_enabled = true;
10302                                 break;
10303                         }
10304                 }
10305
10306                 if (crtc->new_enabled != crtc->base.enabled) {
10307                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10308                                       crtc->new_enabled ? "en" : "dis");
10309                         config->mode_changed = true;
10310                 }
10311
10312                 if (crtc->new_enabled)
10313                         crtc->new_config = &crtc->config;
10314                 else
10315                         crtc->new_config = NULL;
10316         }
10317
10318         return 0;
10319 }
10320
10321 static void disable_crtc_nofb(struct intel_crtc *crtc)
10322 {
10323         struct drm_device *dev = crtc->base.dev;
10324         struct intel_encoder *encoder;
10325         struct intel_connector *connector;
10326
10327         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10328                       pipe_name(crtc->pipe));
10329
10330         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10331                 if (connector->new_encoder &&
10332                     connector->new_encoder->new_crtc == crtc)
10333                         connector->new_encoder = NULL;
10334         }
10335
10336         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10337                 if (encoder->new_crtc == crtc)
10338                         encoder->new_crtc = NULL;
10339         }
10340
10341         crtc->new_enabled = false;
10342         crtc->new_config = NULL;
10343 }
10344
10345 static int intel_crtc_set_config(struct drm_mode_set *set)
10346 {
10347         struct drm_device *dev;
10348         struct drm_mode_set save_set;
10349         struct intel_set_config *config;
10350         int ret;
10351
10352         BUG_ON(!set);
10353         BUG_ON(!set->crtc);
10354         BUG_ON(!set->crtc->helper_private);
10355
10356         /* Enforce sane interface api - has been abused by the fb helper. */
10357         BUG_ON(!set->mode && set->fb);
10358         BUG_ON(set->fb && set->num_connectors == 0);
10359
10360         if (set->fb) {
10361                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10362                                 set->crtc->base.id, set->fb->base.id,
10363                                 (int)set->num_connectors, set->x, set->y);
10364         } else {
10365                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10366         }
10367
10368         dev = set->crtc->dev;
10369
10370         ret = -ENOMEM;
10371         config = kzalloc(sizeof(*config), GFP_KERNEL);
10372         if (!config)
10373                 goto out_config;
10374
10375         ret = intel_set_config_save_state(dev, config);
10376         if (ret)
10377                 goto out_config;
10378
10379         save_set.crtc = set->crtc;
10380         save_set.mode = &set->crtc->mode;
10381         save_set.x = set->crtc->x;
10382         save_set.y = set->crtc->y;
10383         save_set.fb = set->crtc->fb;
10384
10385         /* Compute whether we need a full modeset, only an fb base update or no
10386          * change at all. In the future we might also check whether only the
10387          * mode changed, e.g. for LVDS where we only change the panel fitter in
10388          * such cases. */
10389         intel_set_config_compute_mode_changes(set, config);
10390
10391         ret = intel_modeset_stage_output_state(dev, set, config);
10392         if (ret)
10393                 goto fail;
10394
10395         if (config->mode_changed) {
10396                 ret = intel_set_mode(set->crtc, set->mode,
10397                                      set->x, set->y, set->fb);
10398         } else if (config->fb_changed) {
10399                 intel_crtc_wait_for_pending_flips(set->crtc);
10400
10401                 ret = intel_pipe_set_base(set->crtc,
10402                                           set->x, set->y, set->fb);
10403                 /*
10404                  * In the fastboot case this may be our only check of the
10405                  * state after boot.  It would be better to only do it on
10406                  * the first update, but we don't have a nice way of doing that
10407                  * (and really, set_config isn't used much for high freq page
10408                  * flipping, so increasing its cost here shouldn't be a big
10409                  * deal).
10410                  */
10411                 if (i915.fastboot && ret == 0)
10412                         intel_modeset_check_state(set->crtc->dev);
10413         }
10414
10415         if (ret) {
10416                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10417                               set->crtc->base.id, ret);
10418 fail:
10419                 intel_set_config_restore_state(dev, config);
10420
10421                 /*
10422                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10423                  * force the pipe off to avoid oopsing in the modeset code
10424                  * due to fb==NULL. This should only happen during boot since
10425                  * we don't yet reconstruct the FB from the hardware state.
10426                  */
10427                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10428                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10429
10430                 /* Try to restore the config */
10431                 if (config->mode_changed &&
10432                     intel_set_mode(save_set.crtc, save_set.mode,
10433                                    save_set.x, save_set.y, save_set.fb))
10434                         DRM_ERROR("failed to restore config after modeset failure\n");
10435         }
10436
10437 out_config:
10438         intel_set_config_free(config);
10439         return ret;
10440 }
10441
10442 static const struct drm_crtc_funcs intel_crtc_funcs = {
10443         .cursor_set = intel_crtc_cursor_set,
10444         .cursor_move = intel_crtc_cursor_move,
10445         .gamma_set = intel_crtc_gamma_set,
10446         .set_config = intel_crtc_set_config,
10447         .destroy = intel_crtc_destroy,
10448         .page_flip = intel_crtc_page_flip,
10449 };
10450
10451 static void intel_cpu_pll_init(struct drm_device *dev)
10452 {
10453         if (HAS_DDI(dev))
10454                 intel_ddi_pll_init(dev);
10455 }
10456
10457 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10458                                       struct intel_shared_dpll *pll,
10459                                       struct intel_dpll_hw_state *hw_state)
10460 {
10461         uint32_t val;
10462
10463         val = I915_READ(PCH_DPLL(pll->id));
10464         hw_state->dpll = val;
10465         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10466         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10467
10468         return val & DPLL_VCO_ENABLE;
10469 }
10470
10471 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10472                                   struct intel_shared_dpll *pll)
10473 {
10474         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10475         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10476 }
10477
10478 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10479                                 struct intel_shared_dpll *pll)
10480 {
10481         /* PCH refclock must be enabled first */
10482         ibx_assert_pch_refclk_enabled(dev_priv);
10483
10484         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10485
10486         /* Wait for the clocks to stabilize. */
10487         POSTING_READ(PCH_DPLL(pll->id));
10488         udelay(150);
10489
10490         /* The pixel multiplier can only be updated once the
10491          * DPLL is enabled and the clocks are stable.
10492          *
10493          * So write it again.
10494          */
10495         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10496         POSTING_READ(PCH_DPLL(pll->id));
10497         udelay(200);
10498 }
10499
10500 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10501                                  struct intel_shared_dpll *pll)
10502 {
10503         struct drm_device *dev = dev_priv->dev;
10504         struct intel_crtc *crtc;
10505
10506         /* Make sure no transcoder isn't still depending on us. */
10507         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10508                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10509                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10510         }
10511
10512         I915_WRITE(PCH_DPLL(pll->id), 0);
10513         POSTING_READ(PCH_DPLL(pll->id));
10514         udelay(200);
10515 }
10516
10517 static char *ibx_pch_dpll_names[] = {
10518         "PCH DPLL A",
10519         "PCH DPLL B",
10520 };
10521
10522 static void ibx_pch_dpll_init(struct drm_device *dev)
10523 {
10524         struct drm_i915_private *dev_priv = dev->dev_private;
10525         int i;
10526
10527         dev_priv->num_shared_dpll = 2;
10528
10529         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10530                 dev_priv->shared_dplls[i].id = i;
10531                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10532                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10533                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10534                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10535                 dev_priv->shared_dplls[i].get_hw_state =
10536                         ibx_pch_dpll_get_hw_state;
10537         }
10538 }
10539
10540 static void intel_shared_dpll_init(struct drm_device *dev)
10541 {
10542         struct drm_i915_private *dev_priv = dev->dev_private;
10543
10544         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10545                 ibx_pch_dpll_init(dev);
10546         else
10547                 dev_priv->num_shared_dpll = 0;
10548
10549         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10550 }
10551
10552 static void intel_crtc_init(struct drm_device *dev, int pipe)
10553 {
10554         struct drm_i915_private *dev_priv = dev->dev_private;
10555         struct intel_crtc *intel_crtc;
10556         int i;
10557
10558         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10559         if (intel_crtc == NULL)
10560                 return;
10561
10562         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10563
10564         if (IS_GEN2(dev)) {
10565                 intel_crtc->max_cursor_width = GEN2_CURSOR_WIDTH;
10566                 intel_crtc->max_cursor_height = GEN2_CURSOR_HEIGHT;
10567         } else {
10568                 intel_crtc->max_cursor_width = CURSOR_WIDTH;
10569                 intel_crtc->max_cursor_height = CURSOR_HEIGHT;
10570         }
10571         dev->mode_config.cursor_width = intel_crtc->max_cursor_width;
10572         dev->mode_config.cursor_height = intel_crtc->max_cursor_height;
10573
10574         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10575         for (i = 0; i < 256; i++) {
10576                 intel_crtc->lut_r[i] = i;
10577                 intel_crtc->lut_g[i] = i;
10578                 intel_crtc->lut_b[i] = i;
10579         }
10580
10581         /*
10582          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10583          * is hooked to plane B. Hence we want plane A feeding pipe B.
10584          */
10585         intel_crtc->pipe = pipe;
10586         intel_crtc->plane = pipe;
10587         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10588                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10589                 intel_crtc->plane = !pipe;
10590         }
10591
10592         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10593                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10594         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10595         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10596
10597         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10598 }
10599
10600 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10601 {
10602         struct drm_encoder *encoder = connector->base.encoder;
10603
10604         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10605
10606         if (!encoder)
10607                 return INVALID_PIPE;
10608
10609         return to_intel_crtc(encoder->crtc)->pipe;
10610 }
10611
10612 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10613                                 struct drm_file *file)
10614 {
10615         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10616         struct drm_mode_object *drmmode_obj;
10617         struct intel_crtc *crtc;
10618
10619         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10620                 return -ENODEV;
10621
10622         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10623                         DRM_MODE_OBJECT_CRTC);
10624
10625         if (!drmmode_obj) {
10626                 DRM_ERROR("no such CRTC id\n");
10627                 return -ENOENT;
10628         }
10629
10630         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10631         pipe_from_crtc_id->pipe = crtc->pipe;
10632
10633         return 0;
10634 }
10635
10636 static int intel_encoder_clones(struct intel_encoder *encoder)
10637 {
10638         struct drm_device *dev = encoder->base.dev;
10639         struct intel_encoder *source_encoder;
10640         int index_mask = 0;
10641         int entry = 0;
10642
10643         list_for_each_entry(source_encoder,
10644                             &dev->mode_config.encoder_list, base.head) {
10645                 if (encoders_cloneable(encoder, source_encoder))
10646                         index_mask |= (1 << entry);
10647
10648                 entry++;
10649         }
10650
10651         return index_mask;
10652 }
10653
10654 static bool has_edp_a(struct drm_device *dev)
10655 {
10656         struct drm_i915_private *dev_priv = dev->dev_private;
10657
10658         if (!IS_MOBILE(dev))
10659                 return false;
10660
10661         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10662                 return false;
10663
10664         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10665                 return false;
10666
10667         return true;
10668 }
10669
10670 const char *intel_output_name(int output)
10671 {
10672         static const char *names[] = {
10673                 [INTEL_OUTPUT_UNUSED] = "Unused",
10674                 [INTEL_OUTPUT_ANALOG] = "Analog",
10675                 [INTEL_OUTPUT_DVO] = "DVO",
10676                 [INTEL_OUTPUT_SDVO] = "SDVO",
10677                 [INTEL_OUTPUT_LVDS] = "LVDS",
10678                 [INTEL_OUTPUT_TVOUT] = "TV",
10679                 [INTEL_OUTPUT_HDMI] = "HDMI",
10680                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10681                 [INTEL_OUTPUT_EDP] = "eDP",
10682                 [INTEL_OUTPUT_DSI] = "DSI",
10683                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10684         };
10685
10686         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10687                 return "Invalid";
10688
10689         return names[output];
10690 }
10691
10692 static void intel_setup_outputs(struct drm_device *dev)
10693 {
10694         struct drm_i915_private *dev_priv = dev->dev_private;
10695         struct intel_encoder *encoder;
10696         bool dpd_is_edp = false;
10697
10698         intel_lvds_init(dev);
10699
10700         if (!IS_ULT(dev))
10701                 intel_crt_init(dev);
10702
10703         if (HAS_DDI(dev)) {
10704                 int found;
10705
10706                 /* Haswell uses DDI functions to detect digital outputs */
10707                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10708                 /* DDI A only supports eDP */
10709                 if (found)
10710                         intel_ddi_init(dev, PORT_A);
10711
10712                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10713                  * register */
10714                 found = I915_READ(SFUSE_STRAP);
10715
10716                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10717                         intel_ddi_init(dev, PORT_B);
10718                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10719                         intel_ddi_init(dev, PORT_C);
10720                 if (found & SFUSE_STRAP_DDID_DETECTED)
10721                         intel_ddi_init(dev, PORT_D);
10722         } else if (HAS_PCH_SPLIT(dev)) {
10723                 int found;
10724                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10725
10726                 if (has_edp_a(dev))
10727                         intel_dp_init(dev, DP_A, PORT_A);
10728
10729                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10730                         /* PCH SDVOB multiplex with HDMIB */
10731                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10732                         if (!found)
10733                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10734                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10735                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10736                 }
10737
10738                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10739                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10740
10741                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10742                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10743
10744                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10745                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10746
10747                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10748                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10749         } else if (IS_VALLEYVIEW(dev)) {
10750                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10751                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10752                                         PORT_B);
10753                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10754                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10755                 }
10756
10757                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10758                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10759                                         PORT_C);
10760                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10761                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10762                 }
10763
10764                 intel_dsi_init(dev);
10765         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10766                 bool found = false;
10767
10768                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10769                         DRM_DEBUG_KMS("probing SDVOB\n");
10770                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10771                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10772                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10773                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10774                         }
10775
10776                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10777                                 intel_dp_init(dev, DP_B, PORT_B);
10778                 }
10779
10780                 /* Before G4X SDVOC doesn't have its own detect register */
10781
10782                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10783                         DRM_DEBUG_KMS("probing SDVOC\n");
10784                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10785                 }
10786
10787                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10788
10789                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10790                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10791                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10792                         }
10793                         if (SUPPORTS_INTEGRATED_DP(dev))
10794                                 intel_dp_init(dev, DP_C, PORT_C);
10795                 }
10796
10797                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10798                     (I915_READ(DP_D) & DP_DETECTED))
10799                         intel_dp_init(dev, DP_D, PORT_D);
10800         } else if (IS_GEN2(dev))
10801                 intel_dvo_init(dev);
10802
10803         if (SUPPORTS_TV(dev))
10804                 intel_tv_init(dev);
10805
10806         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10807                 encoder->base.possible_crtcs = encoder->crtc_mask;
10808                 encoder->base.possible_clones =
10809                         intel_encoder_clones(encoder);
10810         }
10811
10812         intel_init_pch_refclk(dev);
10813
10814         drm_helper_move_panel_connectors_to_head(dev);
10815 }
10816
10817 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10818 {
10819         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10820
10821         drm_framebuffer_cleanup(fb);
10822         WARN_ON(!intel_fb->obj->framebuffer_references--);
10823         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10824         kfree(intel_fb);
10825 }
10826
10827 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10828                                                 struct drm_file *file,
10829                                                 unsigned int *handle)
10830 {
10831         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10832         struct drm_i915_gem_object *obj = intel_fb->obj;
10833
10834         return drm_gem_handle_create(file, &obj->base, handle);
10835 }
10836
10837 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10838         .destroy = intel_user_framebuffer_destroy,
10839         .create_handle = intel_user_framebuffer_create_handle,
10840 };
10841
10842 static int intel_framebuffer_init(struct drm_device *dev,
10843                                   struct intel_framebuffer *intel_fb,
10844                                   struct drm_mode_fb_cmd2 *mode_cmd,
10845                                   struct drm_i915_gem_object *obj)
10846 {
10847         int aligned_height;
10848         int pitch_limit;
10849         int ret;
10850
10851         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10852
10853         if (obj->tiling_mode == I915_TILING_Y) {
10854                 DRM_DEBUG("hardware does not support tiling Y\n");
10855                 return -EINVAL;
10856         }
10857
10858         if (mode_cmd->pitches[0] & 63) {
10859                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10860                           mode_cmd->pitches[0]);
10861                 return -EINVAL;
10862         }
10863
10864         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10865                 pitch_limit = 32*1024;
10866         } else if (INTEL_INFO(dev)->gen >= 4) {
10867                 if (obj->tiling_mode)
10868                         pitch_limit = 16*1024;
10869                 else
10870                         pitch_limit = 32*1024;
10871         } else if (INTEL_INFO(dev)->gen >= 3) {
10872                 if (obj->tiling_mode)
10873                         pitch_limit = 8*1024;
10874                 else
10875                         pitch_limit = 16*1024;
10876         } else
10877                 /* XXX DSPC is limited to 4k tiled */
10878                 pitch_limit = 8*1024;
10879
10880         if (mode_cmd->pitches[0] > pitch_limit) {
10881                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10882                           obj->tiling_mode ? "tiled" : "linear",
10883                           mode_cmd->pitches[0], pitch_limit);
10884                 return -EINVAL;
10885         }
10886
10887         if (obj->tiling_mode != I915_TILING_NONE &&
10888             mode_cmd->pitches[0] != obj->stride) {
10889                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10890                           mode_cmd->pitches[0], obj->stride);
10891                 return -EINVAL;
10892         }
10893
10894         /* Reject formats not supported by any plane early. */
10895         switch (mode_cmd->pixel_format) {
10896         case DRM_FORMAT_C8:
10897         case DRM_FORMAT_RGB565:
10898         case DRM_FORMAT_XRGB8888:
10899         case DRM_FORMAT_ARGB8888:
10900                 break;
10901         case DRM_FORMAT_XRGB1555:
10902         case DRM_FORMAT_ARGB1555:
10903                 if (INTEL_INFO(dev)->gen > 3) {
10904                         DRM_DEBUG("unsupported pixel format: %s\n",
10905                                   drm_get_format_name(mode_cmd->pixel_format));
10906                         return -EINVAL;
10907                 }
10908                 break;
10909         case DRM_FORMAT_XBGR8888:
10910         case DRM_FORMAT_ABGR8888:
10911         case DRM_FORMAT_XRGB2101010:
10912         case DRM_FORMAT_ARGB2101010:
10913         case DRM_FORMAT_XBGR2101010:
10914         case DRM_FORMAT_ABGR2101010:
10915                 if (INTEL_INFO(dev)->gen < 4) {
10916                         DRM_DEBUG("unsupported pixel format: %s\n",
10917                                   drm_get_format_name(mode_cmd->pixel_format));
10918                         return -EINVAL;
10919                 }
10920                 break;
10921         case DRM_FORMAT_YUYV:
10922         case DRM_FORMAT_UYVY:
10923         case DRM_FORMAT_YVYU:
10924         case DRM_FORMAT_VYUY:
10925                 if (INTEL_INFO(dev)->gen < 5) {
10926                         DRM_DEBUG("unsupported pixel format: %s\n",
10927                                   drm_get_format_name(mode_cmd->pixel_format));
10928                         return -EINVAL;
10929                 }
10930                 break;
10931         default:
10932                 DRM_DEBUG("unsupported pixel format: %s\n",
10933                           drm_get_format_name(mode_cmd->pixel_format));
10934                 return -EINVAL;
10935         }
10936
10937         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10938         if (mode_cmd->offsets[0] != 0)
10939                 return -EINVAL;
10940
10941         aligned_height = intel_align_height(dev, mode_cmd->height,
10942                                             obj->tiling_mode);
10943         /* FIXME drm helper for size checks (especially planar formats)? */
10944         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10945                 return -EINVAL;
10946
10947         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10948         intel_fb->obj = obj;
10949         intel_fb->obj->framebuffer_references++;
10950
10951         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10952         if (ret) {
10953                 DRM_ERROR("framebuffer init failed %d\n", ret);
10954                 return ret;
10955         }
10956
10957         return 0;
10958 }
10959
10960 static struct drm_framebuffer *
10961 intel_user_framebuffer_create(struct drm_device *dev,
10962                               struct drm_file *filp,
10963                               struct drm_mode_fb_cmd2 *mode_cmd)
10964 {
10965         struct drm_i915_gem_object *obj;
10966
10967         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10968                                                 mode_cmd->handles[0]));
10969         if (&obj->base == NULL)
10970                 return ERR_PTR(-ENOENT);
10971
10972         return intel_framebuffer_create(dev, mode_cmd, obj);
10973 }
10974
10975 #ifndef CONFIG_DRM_I915_FBDEV
10976 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10977 {
10978 }
10979 #endif
10980
10981 static const struct drm_mode_config_funcs intel_mode_funcs = {
10982         .fb_create = intel_user_framebuffer_create,
10983         .output_poll_changed = intel_fbdev_output_poll_changed,
10984 };
10985
10986 /* Set up chip specific display functions */
10987 static void intel_init_display(struct drm_device *dev)
10988 {
10989         struct drm_i915_private *dev_priv = dev->dev_private;
10990
10991         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10992                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10993         else if (IS_VALLEYVIEW(dev))
10994                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10995         else if (IS_PINEVIEW(dev))
10996                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10997         else
10998                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10999
11000         if (HAS_DDI(dev)) {
11001                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11002                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11003                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11004                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11005                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11006                 dev_priv->display.off = haswell_crtc_off;
11007                 dev_priv->display.update_primary_plane =
11008                         ironlake_update_primary_plane;
11009         } else if (HAS_PCH_SPLIT(dev)) {
11010                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11011                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11012                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11013                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11014                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11015                 dev_priv->display.off = ironlake_crtc_off;
11016                 dev_priv->display.update_primary_plane =
11017                         ironlake_update_primary_plane;
11018         } else if (IS_VALLEYVIEW(dev)) {
11019                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11020                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11021                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11022                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11023                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11024                 dev_priv->display.off = i9xx_crtc_off;
11025                 dev_priv->display.update_primary_plane =
11026                         i9xx_update_primary_plane;
11027         } else {
11028                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11029                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11030                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11031                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11032                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11033                 dev_priv->display.off = i9xx_crtc_off;
11034                 dev_priv->display.update_primary_plane =
11035                         i9xx_update_primary_plane;
11036         }
11037
11038         /* Returns the core display clock speed */
11039         if (IS_VALLEYVIEW(dev))
11040                 dev_priv->display.get_display_clock_speed =
11041                         valleyview_get_display_clock_speed;
11042         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11043                 dev_priv->display.get_display_clock_speed =
11044                         i945_get_display_clock_speed;
11045         else if (IS_I915G(dev))
11046                 dev_priv->display.get_display_clock_speed =
11047                         i915_get_display_clock_speed;
11048         else if (IS_I945GM(dev) || IS_845G(dev))
11049                 dev_priv->display.get_display_clock_speed =
11050                         i9xx_misc_get_display_clock_speed;
11051         else if (IS_PINEVIEW(dev))
11052                 dev_priv->display.get_display_clock_speed =
11053                         pnv_get_display_clock_speed;
11054         else if (IS_I915GM(dev))
11055                 dev_priv->display.get_display_clock_speed =
11056                         i915gm_get_display_clock_speed;
11057         else if (IS_I865G(dev))
11058                 dev_priv->display.get_display_clock_speed =
11059                         i865_get_display_clock_speed;
11060         else if (IS_I85X(dev))
11061                 dev_priv->display.get_display_clock_speed =
11062                         i855_get_display_clock_speed;
11063         else /* 852, 830 */
11064                 dev_priv->display.get_display_clock_speed =
11065                         i830_get_display_clock_speed;
11066
11067         if (HAS_PCH_SPLIT(dev)) {
11068                 if (IS_GEN5(dev)) {
11069                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11070                         dev_priv->display.write_eld = ironlake_write_eld;
11071                 } else if (IS_GEN6(dev)) {
11072                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11073                         dev_priv->display.write_eld = ironlake_write_eld;
11074                 } else if (IS_IVYBRIDGE(dev)) {
11075                         /* FIXME: detect B0+ stepping and use auto training */
11076                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11077                         dev_priv->display.write_eld = ironlake_write_eld;
11078                         dev_priv->display.modeset_global_resources =
11079                                 ivb_modeset_global_resources;
11080                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11081                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11082                         dev_priv->display.write_eld = haswell_write_eld;
11083                         dev_priv->display.modeset_global_resources =
11084                                 haswell_modeset_global_resources;
11085                 }
11086         } else if (IS_G4X(dev)) {
11087                 dev_priv->display.write_eld = g4x_write_eld;
11088         } else if (IS_VALLEYVIEW(dev)) {
11089                 dev_priv->display.modeset_global_resources =
11090                         valleyview_modeset_global_resources;
11091                 dev_priv->display.write_eld = ironlake_write_eld;
11092         }
11093
11094         /* Default just returns -ENODEV to indicate unsupported */
11095         dev_priv->display.queue_flip = intel_default_queue_flip;
11096
11097         switch (INTEL_INFO(dev)->gen) {
11098         case 2:
11099                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11100                 break;
11101
11102         case 3:
11103                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11104                 break;
11105
11106         case 4:
11107         case 5:
11108                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11109                 break;
11110
11111         case 6:
11112                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11113                 break;
11114         case 7:
11115         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11116                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11117                 break;
11118         }
11119
11120         intel_panel_init_backlight_funcs(dev);
11121 }
11122
11123 /*
11124  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11125  * resume, or other times.  This quirk makes sure that's the case for
11126  * affected systems.
11127  */
11128 static void quirk_pipea_force(struct drm_device *dev)
11129 {
11130         struct drm_i915_private *dev_priv = dev->dev_private;
11131
11132         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11133         DRM_INFO("applying pipe a force quirk\n");
11134 }
11135
11136 /*
11137  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11138  */
11139 static void quirk_ssc_force_disable(struct drm_device *dev)
11140 {
11141         struct drm_i915_private *dev_priv = dev->dev_private;
11142         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11143         DRM_INFO("applying lvds SSC disable quirk\n");
11144 }
11145
11146 /*
11147  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11148  * brightness value
11149  */
11150 static void quirk_invert_brightness(struct drm_device *dev)
11151 {
11152         struct drm_i915_private *dev_priv = dev->dev_private;
11153         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11154         DRM_INFO("applying inverted panel brightness quirk\n");
11155 }
11156
11157 struct intel_quirk {
11158         int device;
11159         int subsystem_vendor;
11160         int subsystem_device;
11161         void (*hook)(struct drm_device *dev);
11162 };
11163
11164 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11165 struct intel_dmi_quirk {
11166         void (*hook)(struct drm_device *dev);
11167         const struct dmi_system_id (*dmi_id_list)[];
11168 };
11169
11170 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11171 {
11172         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11173         return 1;
11174 }
11175
11176 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11177         {
11178                 .dmi_id_list = &(const struct dmi_system_id[]) {
11179                         {
11180                                 .callback = intel_dmi_reverse_brightness,
11181                                 .ident = "NCR Corporation",
11182                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11183                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11184                                 },
11185                         },
11186                         { }  /* terminating entry */
11187                 },
11188                 .hook = quirk_invert_brightness,
11189         },
11190 };
11191
11192 static struct intel_quirk intel_quirks[] = {
11193         /* HP Mini needs pipe A force quirk (LP: #322104) */
11194         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11195
11196         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11197         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11198
11199         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11200         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11201
11202         /* 830 needs to leave pipe A & dpll A up */
11203         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11204
11205         /* Lenovo U160 cannot use SSC on LVDS */
11206         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11207
11208         /* Sony Vaio Y cannot use SSC on LVDS */
11209         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11210
11211         /* Acer Aspire 5734Z must invert backlight brightness */
11212         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11213
11214         /* Acer/eMachines G725 */
11215         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11216
11217         /* Acer/eMachines e725 */
11218         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11219
11220         /* Acer/Packard Bell NCL20 */
11221         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11222
11223         /* Acer Aspire 4736Z */
11224         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11225
11226         /* Acer Aspire 5336 */
11227         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11228 };
11229
11230 static void intel_init_quirks(struct drm_device *dev)
11231 {
11232         struct pci_dev *d = dev->pdev;
11233         int i;
11234
11235         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11236                 struct intel_quirk *q = &intel_quirks[i];
11237
11238                 if (d->device == q->device &&
11239                     (d->subsystem_vendor == q->subsystem_vendor ||
11240                      q->subsystem_vendor == PCI_ANY_ID) &&
11241                     (d->subsystem_device == q->subsystem_device ||
11242                      q->subsystem_device == PCI_ANY_ID))
11243                         q->hook(dev);
11244         }
11245         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11246                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11247                         intel_dmi_quirks[i].hook(dev);
11248         }
11249 }
11250
11251 /* Disable the VGA plane that we never use */
11252 static void i915_disable_vga(struct drm_device *dev)
11253 {
11254         struct drm_i915_private *dev_priv = dev->dev_private;
11255         u8 sr1;
11256         u32 vga_reg = i915_vgacntrl_reg(dev);
11257
11258         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11259         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11260         outb(SR01, VGA_SR_INDEX);
11261         sr1 = inb(VGA_SR_DATA);
11262         outb(sr1 | 1<<5, VGA_SR_DATA);
11263         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11264         udelay(300);
11265
11266         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11267         POSTING_READ(vga_reg);
11268 }
11269
11270 void intel_modeset_init_hw(struct drm_device *dev)
11271 {
11272         intel_prepare_ddi(dev);
11273
11274         intel_init_clock_gating(dev);
11275
11276         intel_reset_dpio(dev);
11277
11278         mutex_lock(&dev->struct_mutex);
11279         intel_enable_gt_powersave(dev);
11280         mutex_unlock(&dev->struct_mutex);
11281 }
11282
11283 void intel_modeset_suspend_hw(struct drm_device *dev)
11284 {
11285         intel_suspend_hw(dev);
11286 }
11287
11288 void intel_modeset_init(struct drm_device *dev)
11289 {
11290         struct drm_i915_private *dev_priv = dev->dev_private;
11291         int sprite, ret;
11292         enum pipe pipe;
11293         struct intel_crtc *crtc;
11294
11295         drm_mode_config_init(dev);
11296
11297         dev->mode_config.min_width = 0;
11298         dev->mode_config.min_height = 0;
11299
11300         dev->mode_config.preferred_depth = 24;
11301         dev->mode_config.prefer_shadow = 1;
11302
11303         dev->mode_config.funcs = &intel_mode_funcs;
11304
11305         intel_init_quirks(dev);
11306
11307         intel_init_pm(dev);
11308
11309         if (INTEL_INFO(dev)->num_pipes == 0)
11310                 return;
11311
11312         intel_init_display(dev);
11313
11314         if (IS_GEN2(dev)) {
11315                 dev->mode_config.max_width = 2048;
11316                 dev->mode_config.max_height = 2048;
11317         } else if (IS_GEN3(dev)) {
11318                 dev->mode_config.max_width = 4096;
11319                 dev->mode_config.max_height = 4096;
11320         } else {
11321                 dev->mode_config.max_width = 8192;
11322                 dev->mode_config.max_height = 8192;
11323         }
11324         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11325
11326         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11327                       INTEL_INFO(dev)->num_pipes,
11328                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11329
11330         for_each_pipe(pipe) {
11331                 intel_crtc_init(dev, pipe);
11332                 for_each_sprite(pipe, sprite) {
11333                         ret = intel_plane_init(dev, pipe, sprite);
11334                         if (ret)
11335                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11336                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11337                 }
11338         }
11339
11340         intel_init_dpio(dev);
11341         intel_reset_dpio(dev);
11342
11343         intel_cpu_pll_init(dev);
11344         intel_shared_dpll_init(dev);
11345
11346         /* Just disable it once at startup */
11347         i915_disable_vga(dev);
11348         intel_setup_outputs(dev);
11349
11350         /* Just in case the BIOS is doing something questionable. */
11351         intel_disable_fbc(dev);
11352
11353         mutex_lock(&dev->mode_config.mutex);
11354         intel_modeset_setup_hw_state(dev, false);
11355         mutex_unlock(&dev->mode_config.mutex);
11356
11357         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11358                             base.head) {
11359                 if (!crtc->active)
11360                         continue;
11361
11362                 /*
11363                  * Note that reserving the BIOS fb up front prevents us
11364                  * from stuffing other stolen allocations like the ring
11365                  * on top.  This prevents some ugliness at boot time, and
11366                  * can even allow for smooth boot transitions if the BIOS
11367                  * fb is large enough for the active pipe configuration.
11368                  */
11369                 if (dev_priv->display.get_plane_config) {
11370                         dev_priv->display.get_plane_config(crtc,
11371                                                            &crtc->plane_config);
11372                         /*
11373                          * If the fb is shared between multiple heads, we'll
11374                          * just get the first one.
11375                          */
11376                         intel_find_plane_obj(crtc, &crtc->plane_config);
11377                 }
11378         }
11379 }
11380
11381 static void
11382 intel_connector_break_all_links(struct intel_connector *connector)
11383 {
11384         connector->base.dpms = DRM_MODE_DPMS_OFF;
11385         connector->base.encoder = NULL;
11386         connector->encoder->connectors_active = false;
11387         connector->encoder->base.crtc = NULL;
11388 }
11389
11390 static void intel_enable_pipe_a(struct drm_device *dev)
11391 {
11392         struct intel_connector *connector;
11393         struct drm_connector *crt = NULL;
11394         struct intel_load_detect_pipe load_detect_temp;
11395
11396         /* We can't just switch on the pipe A, we need to set things up with a
11397          * proper mode and output configuration. As a gross hack, enable pipe A
11398          * by enabling the load detect pipe once. */
11399         list_for_each_entry(connector,
11400                             &dev->mode_config.connector_list,
11401                             base.head) {
11402                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11403                         crt = &connector->base;
11404                         break;
11405                 }
11406         }
11407
11408         if (!crt)
11409                 return;
11410
11411         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11412                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11413
11414
11415 }
11416
11417 static bool
11418 intel_check_plane_mapping(struct intel_crtc *crtc)
11419 {
11420         struct drm_device *dev = crtc->base.dev;
11421         struct drm_i915_private *dev_priv = dev->dev_private;
11422         u32 reg, val;
11423
11424         if (INTEL_INFO(dev)->num_pipes == 1)
11425                 return true;
11426
11427         reg = DSPCNTR(!crtc->plane);
11428         val = I915_READ(reg);
11429
11430         if ((val & DISPLAY_PLANE_ENABLE) &&
11431             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11432                 return false;
11433
11434         return true;
11435 }
11436
11437 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11438 {
11439         struct drm_device *dev = crtc->base.dev;
11440         struct drm_i915_private *dev_priv = dev->dev_private;
11441         u32 reg;
11442
11443         /* Clear any frame start delays used for debugging left by the BIOS */
11444         reg = PIPECONF(crtc->config.cpu_transcoder);
11445         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11446
11447         /* We need to sanitize the plane -> pipe mapping first because this will
11448          * disable the crtc (and hence change the state) if it is wrong. Note
11449          * that gen4+ has a fixed plane -> pipe mapping.  */
11450         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11451                 struct intel_connector *connector;
11452                 bool plane;
11453
11454                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11455                               crtc->base.base.id);
11456
11457                 /* Pipe has the wrong plane attached and the plane is active.
11458                  * Temporarily change the plane mapping and disable everything
11459                  * ...  */
11460                 plane = crtc->plane;
11461                 crtc->plane = !plane;
11462                 dev_priv->display.crtc_disable(&crtc->base);
11463                 crtc->plane = plane;
11464
11465                 /* ... and break all links. */
11466                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11467                                     base.head) {
11468                         if (connector->encoder->base.crtc != &crtc->base)
11469                                 continue;
11470
11471                         intel_connector_break_all_links(connector);
11472                 }
11473
11474                 WARN_ON(crtc->active);
11475                 crtc->base.enabled = false;
11476         }
11477
11478         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11479             crtc->pipe == PIPE_A && !crtc->active) {
11480                 /* BIOS forgot to enable pipe A, this mostly happens after
11481                  * resume. Force-enable the pipe to fix this, the update_dpms
11482                  * call below we restore the pipe to the right state, but leave
11483                  * the required bits on. */
11484                 intel_enable_pipe_a(dev);
11485         }
11486
11487         /* Adjust the state of the output pipe according to whether we
11488          * have active connectors/encoders. */
11489         intel_crtc_update_dpms(&crtc->base);
11490
11491         if (crtc->active != crtc->base.enabled) {
11492                 struct intel_encoder *encoder;
11493
11494                 /* This can happen either due to bugs in the get_hw_state
11495                  * functions or because the pipe is force-enabled due to the
11496                  * pipe A quirk. */
11497                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11498                               crtc->base.base.id,
11499                               crtc->base.enabled ? "enabled" : "disabled",
11500                               crtc->active ? "enabled" : "disabled");
11501
11502                 crtc->base.enabled = crtc->active;
11503
11504                 /* Because we only establish the connector -> encoder ->
11505                  * crtc links if something is active, this means the
11506                  * crtc is now deactivated. Break the links. connector
11507                  * -> encoder links are only establish when things are
11508                  *  actually up, hence no need to break them. */
11509                 WARN_ON(crtc->active);
11510
11511                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11512                         WARN_ON(encoder->connectors_active);
11513                         encoder->base.crtc = NULL;
11514                 }
11515         }
11516         if (crtc->active) {
11517                 /*
11518                  * We start out with underrun reporting disabled to avoid races.
11519                  * For correct bookkeeping mark this on active crtcs.
11520                  *
11521                  * No protection against concurrent access is required - at
11522                  * worst a fifo underrun happens which also sets this to false.
11523                  */
11524                 crtc->cpu_fifo_underrun_disabled = true;
11525                 crtc->pch_fifo_underrun_disabled = true;
11526         }
11527 }
11528
11529 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11530 {
11531         struct intel_connector *connector;
11532         struct drm_device *dev = encoder->base.dev;
11533
11534         /* We need to check both for a crtc link (meaning that the
11535          * encoder is active and trying to read from a pipe) and the
11536          * pipe itself being active. */
11537         bool has_active_crtc = encoder->base.crtc &&
11538                 to_intel_crtc(encoder->base.crtc)->active;
11539
11540         if (encoder->connectors_active && !has_active_crtc) {
11541                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11542                               encoder->base.base.id,
11543                               drm_get_encoder_name(&encoder->base));
11544
11545                 /* Connector is active, but has no active pipe. This is
11546                  * fallout from our resume register restoring. Disable
11547                  * the encoder manually again. */
11548                 if (encoder->base.crtc) {
11549                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11550                                       encoder->base.base.id,
11551                                       drm_get_encoder_name(&encoder->base));
11552                         encoder->disable(encoder);
11553                 }
11554
11555                 /* Inconsistent output/port/pipe state happens presumably due to
11556                  * a bug in one of the get_hw_state functions. Or someplace else
11557                  * in our code, like the register restore mess on resume. Clamp
11558                  * things to off as a safer default. */
11559                 list_for_each_entry(connector,
11560                                     &dev->mode_config.connector_list,
11561                                     base.head) {
11562                         if (connector->encoder != encoder)
11563                                 continue;
11564
11565                         intel_connector_break_all_links(connector);
11566                 }
11567         }
11568         /* Enabled encoders without active connectors will be fixed in
11569          * the crtc fixup. */
11570 }
11571
11572 void i915_redisable_vga_power_on(struct drm_device *dev)
11573 {
11574         struct drm_i915_private *dev_priv = dev->dev_private;
11575         u32 vga_reg = i915_vgacntrl_reg(dev);
11576
11577         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11578                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11579                 i915_disable_vga(dev);
11580         }
11581 }
11582
11583 void i915_redisable_vga(struct drm_device *dev)
11584 {
11585         struct drm_i915_private *dev_priv = dev->dev_private;
11586
11587         /* This function can be called both from intel_modeset_setup_hw_state or
11588          * at a very early point in our resume sequence, where the power well
11589          * structures are not yet restored. Since this function is at a very
11590          * paranoid "someone might have enabled VGA while we were not looking"
11591          * level, just check if the power well is enabled instead of trying to
11592          * follow the "don't touch the power well if we don't need it" policy
11593          * the rest of the driver uses. */
11594         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11595                 return;
11596
11597         i915_redisable_vga_power_on(dev);
11598 }
11599
11600 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11601 {
11602         struct drm_i915_private *dev_priv = dev->dev_private;
11603         enum pipe pipe;
11604         struct intel_crtc *crtc;
11605         struct intel_encoder *encoder;
11606         struct intel_connector *connector;
11607         int i;
11608
11609         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11610                             base.head) {
11611                 memset(&crtc->config, 0, sizeof(crtc->config));
11612
11613                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11614                                                                  &crtc->config);
11615
11616                 crtc->base.enabled = crtc->active;
11617                 crtc->primary_enabled = crtc->active;
11618
11619                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11620                               crtc->base.base.id,
11621                               crtc->active ? "enabled" : "disabled");
11622         }
11623
11624         /* FIXME: Smash this into the new shared dpll infrastructure. */
11625         if (HAS_DDI(dev))
11626                 intel_ddi_setup_hw_pll_state(dev);
11627
11628         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11629                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11630
11631                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11632                 pll->active = 0;
11633                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11634                                     base.head) {
11635                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11636                                 pll->active++;
11637                 }
11638                 pll->refcount = pll->active;
11639
11640                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11641                               pll->name, pll->refcount, pll->on);
11642         }
11643
11644         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11645                             base.head) {
11646                 pipe = 0;
11647
11648                 if (encoder->get_hw_state(encoder, &pipe)) {
11649                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11650                         encoder->base.crtc = &crtc->base;
11651                         encoder->get_config(encoder, &crtc->config);
11652                 } else {
11653                         encoder->base.crtc = NULL;
11654                 }
11655
11656                 encoder->connectors_active = false;
11657                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11658                               encoder->base.base.id,
11659                               drm_get_encoder_name(&encoder->base),
11660                               encoder->base.crtc ? "enabled" : "disabled",
11661                               pipe_name(pipe));
11662         }
11663
11664         list_for_each_entry(connector, &dev->mode_config.connector_list,
11665                             base.head) {
11666                 if (connector->get_hw_state(connector)) {
11667                         connector->base.dpms = DRM_MODE_DPMS_ON;
11668                         connector->encoder->connectors_active = true;
11669                         connector->base.encoder = &connector->encoder->base;
11670                 } else {
11671                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11672                         connector->base.encoder = NULL;
11673                 }
11674                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11675                               connector->base.base.id,
11676                               drm_get_connector_name(&connector->base),
11677                               connector->base.encoder ? "enabled" : "disabled");
11678         }
11679 }
11680
11681 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11682  * and i915 state tracking structures. */
11683 void intel_modeset_setup_hw_state(struct drm_device *dev,
11684                                   bool force_restore)
11685 {
11686         struct drm_i915_private *dev_priv = dev->dev_private;
11687         enum pipe pipe;
11688         struct intel_crtc *crtc;
11689         struct intel_encoder *encoder;
11690         int i;
11691
11692         intel_modeset_readout_hw_state(dev);
11693
11694         /*
11695          * Now that we have the config, copy it to each CRTC struct
11696          * Note that this could go away if we move to using crtc_config
11697          * checking everywhere.
11698          */
11699         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11700                             base.head) {
11701                 if (crtc->active && i915.fastboot) {
11702                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11703                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11704                                       crtc->base.base.id);
11705                         drm_mode_debug_printmodeline(&crtc->base.mode);
11706                 }
11707         }
11708
11709         /* HW state is read out, now we need to sanitize this mess. */
11710         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11711                             base.head) {
11712                 intel_sanitize_encoder(encoder);
11713         }
11714
11715         for_each_pipe(pipe) {
11716                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11717                 intel_sanitize_crtc(crtc);
11718                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11719         }
11720
11721         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11722                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11723
11724                 if (!pll->on || pll->active)
11725                         continue;
11726
11727                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11728
11729                 pll->disable(dev_priv, pll);
11730                 pll->on = false;
11731         }
11732
11733         if (HAS_PCH_SPLIT(dev))
11734                 ilk_wm_get_hw_state(dev);
11735
11736         if (force_restore) {
11737                 i915_redisable_vga(dev);
11738
11739                 /*
11740                  * We need to use raw interfaces for restoring state to avoid
11741                  * checking (bogus) intermediate states.
11742                  */
11743                 for_each_pipe(pipe) {
11744                         struct drm_crtc *crtc =
11745                                 dev_priv->pipe_to_crtc_mapping[pipe];
11746
11747                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11748                                          crtc->fb);
11749                 }
11750         } else {
11751                 intel_modeset_update_staged_output_state(dev);
11752         }
11753
11754         intel_modeset_check_state(dev);
11755 }
11756
11757 void intel_modeset_gem_init(struct drm_device *dev)
11758 {
11759         struct drm_crtc *c;
11760         struct intel_framebuffer *fb;
11761
11762         intel_modeset_init_hw(dev);
11763
11764         intel_setup_overlay(dev);
11765
11766         /*
11767          * Make sure any fbs we allocated at startup are properly
11768          * pinned & fenced.  When we do the allocation it's too early
11769          * for this.
11770          */
11771         mutex_lock(&dev->struct_mutex);
11772         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11773                 if (!c->fb)
11774                         continue;
11775
11776                 fb = to_intel_framebuffer(c->fb);
11777                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11778                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11779                                   to_intel_crtc(c)->pipe);
11780                         drm_framebuffer_unreference(c->fb);
11781                         c->fb = NULL;
11782                 }
11783         }
11784         mutex_unlock(&dev->struct_mutex);
11785 }
11786
11787 void intel_connector_unregister(struct intel_connector *intel_connector)
11788 {
11789         struct drm_connector *connector = &intel_connector->base;
11790
11791         intel_panel_destroy_backlight(connector);
11792         drm_sysfs_connector_remove(connector);
11793 }
11794
11795 void intel_modeset_cleanup(struct drm_device *dev)
11796 {
11797         struct drm_i915_private *dev_priv = dev->dev_private;
11798         struct drm_crtc *crtc;
11799         struct drm_connector *connector;
11800
11801         /*
11802          * Interrupts and polling as the first thing to avoid creating havoc.
11803          * Too much stuff here (turning of rps, connectors, ...) would
11804          * experience fancy races otherwise.
11805          */
11806         drm_irq_uninstall(dev);
11807         cancel_work_sync(&dev_priv->hotplug_work);
11808         /*
11809          * Due to the hpd irq storm handling the hotplug work can re-arm the
11810          * poll handlers. Hence disable polling after hpd handling is shut down.
11811          */
11812         drm_kms_helper_poll_fini(dev);
11813
11814         mutex_lock(&dev->struct_mutex);
11815
11816         intel_unregister_dsm_handler();
11817
11818         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11819                 /* Skip inactive CRTCs */
11820                 if (!crtc->fb)
11821                         continue;
11822
11823                 intel_increase_pllclock(crtc);
11824         }
11825
11826         intel_disable_fbc(dev);
11827
11828         intel_disable_gt_powersave(dev);
11829
11830         ironlake_teardown_rc6(dev);
11831
11832         mutex_unlock(&dev->struct_mutex);
11833
11834         /* flush any delayed tasks or pending work */
11835         flush_scheduled_work();
11836
11837         /* destroy the backlight and sysfs files before encoders/connectors */
11838         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11839                 struct intel_connector *intel_connector;
11840
11841                 intel_connector = to_intel_connector(connector);
11842                 intel_connector->unregister(intel_connector);
11843         }
11844
11845         drm_mode_config_cleanup(dev);
11846
11847         intel_cleanup_overlay(dev);
11848 }
11849
11850 /*
11851  * Return which encoder is currently attached for connector.
11852  */
11853 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11854 {
11855         return &intel_attached_encoder(connector)->base;
11856 }
11857
11858 void intel_connector_attach_encoder(struct intel_connector *connector,
11859                                     struct intel_encoder *encoder)
11860 {
11861         connector->encoder = encoder;
11862         drm_mode_connector_attach_encoder(&connector->base,
11863                                           &encoder->base);
11864 }
11865
11866 /*
11867  * set vga decode state - true == enable VGA decode
11868  */
11869 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11870 {
11871         struct drm_i915_private *dev_priv = dev->dev_private;
11872         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11873         u16 gmch_ctrl;
11874
11875         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11876                 DRM_ERROR("failed to read control word\n");
11877                 return -EIO;
11878         }
11879
11880         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11881                 return 0;
11882
11883         if (state)
11884                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11885         else
11886                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11887
11888         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11889                 DRM_ERROR("failed to write control word\n");
11890                 return -EIO;
11891         }
11892
11893         return 0;
11894 }
11895
11896 struct intel_display_error_state {
11897
11898         u32 power_well_driver;
11899
11900         int num_transcoders;
11901
11902         struct intel_cursor_error_state {
11903                 u32 control;
11904                 u32 position;
11905                 u32 base;
11906                 u32 size;
11907         } cursor[I915_MAX_PIPES];
11908
11909         struct intel_pipe_error_state {
11910                 bool power_domain_on;
11911                 u32 source;
11912         } pipe[I915_MAX_PIPES];
11913
11914         struct intel_plane_error_state {
11915                 u32 control;
11916                 u32 stride;
11917                 u32 size;
11918                 u32 pos;
11919                 u32 addr;
11920                 u32 surface;
11921                 u32 tile_offset;
11922         } plane[I915_MAX_PIPES];
11923
11924         struct intel_transcoder_error_state {
11925                 bool power_domain_on;
11926                 enum transcoder cpu_transcoder;
11927
11928                 u32 conf;
11929
11930                 u32 htotal;
11931                 u32 hblank;
11932                 u32 hsync;
11933                 u32 vtotal;
11934                 u32 vblank;
11935                 u32 vsync;
11936         } transcoder[4];
11937 };
11938
11939 struct intel_display_error_state *
11940 intel_display_capture_error_state(struct drm_device *dev)
11941 {
11942         struct drm_i915_private *dev_priv = dev->dev_private;
11943         struct intel_display_error_state *error;
11944         int transcoders[] = {
11945                 TRANSCODER_A,
11946                 TRANSCODER_B,
11947                 TRANSCODER_C,
11948                 TRANSCODER_EDP,
11949         };
11950         int i;
11951
11952         if (INTEL_INFO(dev)->num_pipes == 0)
11953                 return NULL;
11954
11955         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11956         if (error == NULL)
11957                 return NULL;
11958
11959         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11960                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11961
11962         for_each_pipe(i) {
11963                 error->pipe[i].power_domain_on =
11964                         intel_display_power_enabled_sw(dev_priv,
11965                                                        POWER_DOMAIN_PIPE(i));
11966                 if (!error->pipe[i].power_domain_on)
11967                         continue;
11968
11969                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11970                         error->cursor[i].control = I915_READ(CURCNTR(i));
11971                         error->cursor[i].position = I915_READ(CURPOS(i));
11972                         error->cursor[i].base = I915_READ(CURBASE(i));
11973                 } else {
11974                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11975                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11976                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11977                 }
11978
11979                 error->plane[i].control = I915_READ(DSPCNTR(i));
11980                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11981                 if (INTEL_INFO(dev)->gen <= 3) {
11982                         error->plane[i].size = I915_READ(DSPSIZE(i));
11983                         error->plane[i].pos = I915_READ(DSPPOS(i));
11984                 }
11985                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11986                         error->plane[i].addr = I915_READ(DSPADDR(i));
11987                 if (INTEL_INFO(dev)->gen >= 4) {
11988                         error->plane[i].surface = I915_READ(DSPSURF(i));
11989                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11990                 }
11991
11992                 error->pipe[i].source = I915_READ(PIPESRC(i));
11993         }
11994
11995         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11996         if (HAS_DDI(dev_priv->dev))
11997                 error->num_transcoders++; /* Account for eDP. */
11998
11999         for (i = 0; i < error->num_transcoders; i++) {
12000                 enum transcoder cpu_transcoder = transcoders[i];
12001
12002                 error->transcoder[i].power_domain_on =
12003                         intel_display_power_enabled_sw(dev_priv,
12004                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12005                 if (!error->transcoder[i].power_domain_on)
12006                         continue;
12007
12008                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12009
12010                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12011                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12012                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12013                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12014                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12015                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12016                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12017         }
12018
12019         return error;
12020 }
12021
12022 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12023
12024 void
12025 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12026                                 struct drm_device *dev,
12027                                 struct intel_display_error_state *error)
12028 {
12029         int i;
12030
12031         if (!error)
12032                 return;
12033
12034         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12035         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12036                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12037                            error->power_well_driver);
12038         for_each_pipe(i) {
12039                 err_printf(m, "Pipe [%d]:\n", i);
12040                 err_printf(m, "  Power: %s\n",
12041                            error->pipe[i].power_domain_on ? "on" : "off");
12042                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12043
12044                 err_printf(m, "Plane [%d]:\n", i);
12045                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12046                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12047                 if (INTEL_INFO(dev)->gen <= 3) {
12048                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12049                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12050                 }
12051                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12052                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12053                 if (INTEL_INFO(dev)->gen >= 4) {
12054                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12055                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12056                 }
12057
12058                 err_printf(m, "Cursor [%d]:\n", i);
12059                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12060                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12061                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12062         }
12063
12064         for (i = 0; i < error->num_transcoders; i++) {
12065                 err_printf(m, "CPU transcoder: %c\n",
12066                            transcoder_name(error->transcoder[i].cpu_transcoder));
12067                 err_printf(m, "  Power: %s\n",
12068                            error->transcoder[i].power_domain_on ? "on" : "off");
12069                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12070                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12071                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12072                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12073                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12074                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12075                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12076         }
12077 }