drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 /* For ILK+ */
 913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 914                            struct intel_pch_pll *pll,
 915                            struct intel_crtc *crtc,
 916                            bool state)
 917 {
 918         u32 val;
 919         bool cur_state;
 920
 921         if (HAS_PCH_LPT(dev_priv->dev)) {
 922                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 923                 return;
 924         }
 925
 926         if (WARN (!pll,
 927                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 928                 return;
 929
 930         val = I915_READ(pll->pll_reg);
 931         cur_state = !!(val & DPLL_VCO_ENABLE);
 932         WARN(cur_state != state,
 933              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 934              pll->pll_reg, state_string(state), state_string(cur_state), val);
 935
 936         /* Make sure the selected PLL is correctly attached to the transcoder */
 937         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 938                 u32 pch_dpll;
 939
 940                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 941                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 942                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 943                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 944                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 945                         cur_state = !!(val >> (4*crtc->pipe + 3));
 946                         WARN(cur_state != state,
 947                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 948                              pll->pll_reg == _PCH_DPLL_B,
 949                              state_string(state),
 950                              pipe_name(crtc->pipe),
 951                              val);
 952                 }
 953         }
 954 }
 955 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 956 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 957
 958 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 959                           enum pipe pipe, bool state)
 960 {
 961         int reg;
 962         u32 val;
 963         bool cur_state;
 964         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 965                                                                       pipe);
 966
 967         if (HAS_DDI(dev_priv->dev)) {
 968                 /* DDI does not have a specific FDI_TX register */
 969                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 970                 val = I915_READ(reg);
 971                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 972         } else {
 973                 reg = FDI_TX_CTL(pipe);
 974                 val = I915_READ(reg);
 975                 cur_state = !!(val & FDI_TX_ENABLE);
 976         }
 977         WARN(cur_state != state,
 978              "FDI TX state assertion failure (expected %s, current %s)\n",
 979              state_string(state), state_string(cur_state));
 980 }
 981 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 982 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 983
 984 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 985                           enum pipe pipe, bool state)
 986 {
 987         int reg;
 988         u32 val;
 989         bool cur_state;
 990
 991         reg = FDI_RX_CTL(pipe);
 992         val = I915_READ(reg);
 993         cur_state = !!(val & FDI_RX_ENABLE);
 994         WARN(cur_state != state,
 995              "FDI RX state assertion failure (expected %s, current %s)\n",
 996              state_string(state), state_string(cur_state));
 997 }
 998 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 999 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         /* ILK FDI PLL is always enabled */
1008         if (dev_priv->info->gen == 5)
1009                 return;
1010
1011         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1012         if (HAS_DDI(dev_priv->dev))
1013                 return;
1014
1015         reg = FDI_TX_CTL(pipe);
1016         val = I915_READ(reg);
1017         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
1020 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         reg = FDI_RX_CTL(pipe);
1027         val = I915_READ(reg);
1028         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032                                   enum pipe pipe)
1033 {
1034         int pp_reg, lvds_reg;
1035         u32 val;
1036         enum pipe panel_pipe = PIPE_A;
1037         bool locked = true;
1038
1039         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040                 pp_reg = PCH_PP_CONTROL;
1041                 lvds_reg = PCH_LVDS;
1042         } else {
1043                 pp_reg = PP_CONTROL;
1044                 lvds_reg = LVDS;
1045         }
1046
1047         val = I915_READ(pp_reg);
1048         if (!(val & PANEL_POWER_ON) ||
1049             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050                 locked = false;
1051
1052         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053                 panel_pipe = PIPE_B;
1054
1055         WARN(panel_pipe == pipe && locked,
1056              "panel assertion failure, pipe %c regs locked\n",
1057              pipe_name(pipe));
1058 }
1059
1060 void assert_pipe(struct drm_i915_private *dev_priv,
1061                  enum pipe pipe, bool state)
1062 {
1063         int reg;
1064         u32 val;
1065         bool cur_state;
1066         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067                                                                       pipe);
1068
1069         /* if we need the pipe A quirk it must be always on */
1070         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071                 state = true;
1072
1073         if (!intel_display_power_enabled(dev_priv->dev,
1074                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1075                 cur_state = false;
1076         } else {
1077                 reg = PIPECONF(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & PIPECONF_ENABLE);
1080         }
1081
1082         WARN(cur_state != state,
1083              "pipe %c assertion failure (expected %s, current %s)\n",
1084              pipe_name(pipe), state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_plane(struct drm_i915_private *dev_priv,
1088                          enum plane plane, bool state)
1089 {
1090         int reg;
1091         u32 val;
1092         bool cur_state;
1093
1094         reg = DSPCNTR(plane);
1095         val = I915_READ(reg);
1096         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097         WARN(cur_state != state,
1098              "plane %c assertion failure (expected %s, current %s)\n",
1099              plane_name(plane), state_string(state), state_string(cur_state));
1100 }
1101
1102 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
1105 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106                                    enum pipe pipe)
1107 {
1108         int reg, i;
1109         u32 val;
1110         int cur_pipe;
1111
1112         /* Planes are fixed to pipes on ILK+ */
1113         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1114                 reg = DSPCNTR(pipe);
1115                 val = I915_READ(reg);
1116                 WARN((val & DISPLAY_PLANE_ENABLE),
1117                      "plane %c assertion failure, should be disabled but not\n",
1118                      plane_name(pipe));
1119                 return;
1120         }
1121
1122         /* Need to check both planes against the pipe */
1123         for (i = 0; i < 2; i++) {
1124                 reg = DSPCNTR(i);
1125                 val = I915_READ(reg);
1126                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127                         DISPPLANE_SEL_PIPE_SHIFT;
1128                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1129                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130                      plane_name(i), pipe_name(pipe));
1131         }
1132 }
1133
1134 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135                                     enum pipe pipe)
1136 {
1137         int reg, i;
1138         u32 val;
1139
1140         if (!IS_VALLEYVIEW(dev_priv->dev))
1141                 return;
1142
1143         /* Need to check both planes against the pipe */
1144         for (i = 0; i < dev_priv->num_plane; i++) {
1145                 reg = SPCNTR(pipe, i);
1146                 val = I915_READ(reg);
1147                 WARN((val & SP_ENABLE),
1148                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149                      sprite_name(pipe, i), pipe_name(pipe));
1150         }
1151 }
1152
1153 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154 {
1155         u32 val;
1156         bool enabled;
1157
1158         if (HAS_PCH_LPT(dev_priv->dev)) {
1159                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160                 return;
1161         }
1162
1163         val = I915_READ(PCH_DREF_CONTROL);
1164         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165                             DREF_SUPERSPREAD_SOURCE_MASK));
1166         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167 }
1168
1169 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170                                            enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174         bool enabled;
1175
1176         reg = PCH_TRANSCONF(pipe);
1177         val = I915_READ(reg);
1178         enabled = !!(val & TRANS_ENABLE);
1179         WARN(enabled,
1180              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181              pipe_name(pipe));
1182 }
1183
1184 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185                             enum pipe pipe, u32 port_sel, u32 val)
1186 {
1187         if ((val & DP_PORT_EN) == 0)
1188                 return false;
1189
1190         if (HAS_PCH_CPT(dev_priv->dev)) {
1191                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194                         return false;
1195         } else {
1196                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197                         return false;
1198         }
1199         return true;
1200 }
1201
1202 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203                               enum pipe pipe, u32 val)
1204 {
1205         if ((val & SDVO_ENABLE) == 0)
1206                 return false;
1207
1208         if (HAS_PCH_CPT(dev_priv->dev)) {
1209                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1210                         return false;
1211         } else {
1212                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1213                         return false;
1214         }
1215         return true;
1216 }
1217
1218 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219                               enum pipe pipe, u32 val)
1220 {
1221         if ((val & LVDS_PORT_EN) == 0)
1222                 return false;
1223
1224         if (HAS_PCH_CPT(dev_priv->dev)) {
1225                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226                         return false;
1227         } else {
1228                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229                         return false;
1230         }
1231         return true;
1232 }
1233
1234 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235                               enum pipe pipe, u32 val)
1236 {
1237         if ((val & ADPA_DAC_ENABLE) == 0)
1238                 return false;
1239         if (HAS_PCH_CPT(dev_priv->dev)) {
1240                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241                         return false;
1242         } else {
1243                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244                         return false;
1245         }
1246         return true;
1247 }
1248
1249 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1250                                    enum pipe pipe, int reg, u32 port_sel)
1251 {
1252         u32 val = I915_READ(reg);
1253         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1254              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1255              reg, pipe_name(pipe));
1256
1257         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258              && (val & DP_PIPEB_SELECT),
1259              "IBX PCH dp port still using transcoder B\n");
1260 }
1261
1262 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263                                      enum pipe pipe, int reg)
1264 {
1265         u32 val = I915_READ(reg);
1266         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1267              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1268              reg, pipe_name(pipe));
1269
1270         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1271              && (val & SDVO_PIPE_B_SELECT),
1272              "IBX PCH hdmi port still using transcoder B\n");
1273 }
1274
1275 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276                                       enum pipe pipe)
1277 {
1278         int reg;
1279         u32 val;
1280
1281         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1284
1285         reg = PCH_ADPA;
1286         val = I915_READ(reg);
1287         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1288              "PCH VGA enabled on transcoder %c, should be disabled\n",
1289              pipe_name(pipe));
1290
1291         reg = PCH_LVDS;
1292         val = I915_READ(reg);
1293         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1294              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1295              pipe_name(pipe));
1296
1297         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1300 }
1301
1302 /**
1303  * intel_enable_pll - enable a PLL
1304  * @dev_priv: i915 private structure
1305  * @pipe: pipe PLL to enable
1306  *
1307  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1308  * make sure the PLL reg is writable first though, since the panel write
1309  * protect mechanism may be enabled.
1310  *
1311  * Note!  This is for pre-ILK only.
1312  *
1313  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1314  */
1315 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319
1320         assert_pipe_disabled(dev_priv, pipe);
1321
1322         /* No really, not for ILK+ */
1323         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1324
1325         /* PLL is protected by panel, make sure we can write it */
1326         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327                 assert_panel_unlocked(dev_priv, pipe);
1328
1329         reg = DPLL(pipe);
1330         val = I915_READ(reg);
1331         val |= DPLL_VCO_ENABLE;
1332
1333         /* We do this three times for luck */
1334         I915_WRITE(reg, val);
1335         POSTING_READ(reg);
1336         udelay(150); /* wait for warmup */
1337         I915_WRITE(reg, val);
1338         POSTING_READ(reg);
1339         udelay(150); /* wait for warmup */
1340         I915_WRITE(reg, val);
1341         POSTING_READ(reg);
1342         udelay(150); /* wait for warmup */
1343 }
1344
1345 /**
1346  * intel_disable_pll - disable a PLL
1347  * @dev_priv: i915 private structure
1348  * @pipe: pipe PLL to disable
1349  *
1350  * Disable the PLL for @pipe, making sure the pipe is off first.
1351  *
1352  * Note!  This is for pre-ILK only.
1353  */
1354 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355 {
1356         int reg;
1357         u32 val;
1358
1359         /* Don't disable pipe A or pipe A PLLs if needed */
1360         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361                 return;
1362
1363         /* Make sure the pipe isn't still relying on us */
1364         assert_pipe_disabled(dev_priv, pipe);
1365
1366         reg = DPLL(pipe);
1367         val = I915_READ(reg);
1368         val &= ~DPLL_VCO_ENABLE;
1369         I915_WRITE(reg, val);
1370         POSTING_READ(reg);
1371 }
1372
1373 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374 {
1375         u32 port_mask;
1376
1377         if (!port)
1378                 port_mask = DPLL_PORTB_READY_MASK;
1379         else
1380                 port_mask = DPLL_PORTC_READY_MASK;
1381
1382         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384                      'B' + port, I915_READ(DPLL(0)));
1385 }
1386
1387 /**
1388  * ironlake_enable_pch_pll - enable PCH PLL
1389  * @dev_priv: i915 private structure
1390  * @pipe: pipe PLL to enable
1391  *
1392  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393  * drives the transcoder clock.
1394  */
1395 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1396 {
1397         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1398         struct intel_pch_pll *pll;
1399         int reg;
1400         u32 val;
1401
1402         /* PCH PLLs only available on ILK, SNB and IVB */
1403         BUG_ON(dev_priv->info->gen < 5);
1404         pll = intel_crtc->pch_pll;
1405         if (pll == NULL)
1406                 return;
1407
1408         if (WARN_ON(pll->refcount == 0))
1409                 return;
1410
1411         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412                       pll->pll_reg, pll->active, pll->on,
1413                       intel_crtc->base.base.id);
1414
1415         /* PCH refclock must be enabled first */
1416         assert_pch_refclk_enabled(dev_priv);
1417
1418         if (pll->active++ && pll->on) {
1419                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1420                 return;
1421         }
1422
1423         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425         reg = pll->pll_reg;
1426         val = I915_READ(reg);
1427         val |= DPLL_VCO_ENABLE;
1428         I915_WRITE(reg, val);
1429         POSTING_READ(reg);
1430         udelay(200);
1431
1432         pll->on = true;
1433 }
1434
1435 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1436 {
1437         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1439         int reg;
1440         u32 val;
1441
1442         /* PCH only available on ILK+ */
1443         BUG_ON(dev_priv->info->gen < 5);
1444         if (pll == NULL)
1445                return;
1446
1447         if (WARN_ON(pll->refcount == 0))
1448                 return;
1449
1450         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451                       pll->pll_reg, pll->active, pll->on,
1452                       intel_crtc->base.base.id);
1453
1454         if (WARN_ON(pll->active == 0)) {
1455                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1456                 return;
1457         }
1458
1459         if (--pll->active) {
1460                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1461                 return;
1462         }
1463
1464         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466         /* Make sure transcoder isn't still depending on us */
1467         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1468
1469         reg = pll->pll_reg;
1470         val = I915_READ(reg);
1471         val &= ~DPLL_VCO_ENABLE;
1472         I915_WRITE(reg, val);
1473         POSTING_READ(reg);
1474         udelay(200);
1475
1476         pll->on = false;
1477 }
1478
1479 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480                                            enum pipe pipe)
1481 {
1482         struct drm_device *dev = dev_priv->dev;
1483         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1484         uint32_t reg, val, pipeconf_val;
1485
1486         /* PCH only available on ILK+ */
1487         BUG_ON(dev_priv->info->gen < 5);
1488
1489         /* Make sure PCH DPLL is enabled */
1490         assert_pch_pll_enabled(dev_priv,
1491                                to_intel_crtc(crtc)->pch_pll,
1492                                to_intel_crtc(crtc));
1493
1494         /* FDI must be feeding us bits for PCH ports */
1495         assert_fdi_tx_enabled(dev_priv, pipe);
1496         assert_fdi_rx_enabled(dev_priv, pipe);
1497
1498         if (HAS_PCH_CPT(dev)) {
1499                 /* Workaround: Set the timing override bit before enabling the
1500                  * pch transcoder. */
1501                 reg = TRANS_CHICKEN2(pipe);
1502                 val = I915_READ(reg);
1503                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504                 I915_WRITE(reg, val);
1505         }
1506
1507         reg = PCH_TRANSCONF(pipe);
1508         val = I915_READ(reg);
1509         pipeconf_val = I915_READ(PIPECONF(pipe));
1510
1511         if (HAS_PCH_IBX(dev_priv->dev)) {
1512                 /*
1513                  * make the BPC in transcoder be consistent with
1514                  * that in pipeconf reg.
1515                  */
1516                 val &= ~PIPECONF_BPC_MASK;
1517                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1518         }
1519
1520         val &= ~TRANS_INTERLACE_MASK;
1521         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1522                 if (HAS_PCH_IBX(dev_priv->dev) &&
1523                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524                         val |= TRANS_LEGACY_INTERLACED_ILK;
1525                 else
1526                         val |= TRANS_INTERLACED;
1527         else
1528                 val |= TRANS_PROGRESSIVE;
1529
1530         I915_WRITE(reg, val | TRANS_ENABLE);
1531         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1532                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1533 }
1534
1535 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536                                       enum transcoder cpu_transcoder)
1537 {
1538         u32 val, pipeconf_val;
1539
1540         /* PCH only available on ILK+ */
1541         BUG_ON(dev_priv->info->gen < 5);
1542
1543         /* FDI must be feeding us bits for PCH ports */
1544         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1545         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1546
1547         /* Workaround: set timing override bit. */
1548         val = I915_READ(_TRANSA_CHICKEN2);
1549         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1550         I915_WRITE(_TRANSA_CHICKEN2, val);
1551
1552         val = TRANS_ENABLE;
1553         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1554
1555         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556             PIPECONF_INTERLACED_ILK)
1557                 val |= TRANS_INTERLACED;
1558         else
1559                 val |= TRANS_PROGRESSIVE;
1560
1561         I915_WRITE(LPT_TRANSCONF, val);
1562         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1563                 DRM_ERROR("Failed to enable PCH transcoder\n");
1564 }
1565
1566 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567                                             enum pipe pipe)
1568 {
1569         struct drm_device *dev = dev_priv->dev;
1570         uint32_t reg, val;
1571
1572         /* FDI relies on the transcoder */
1573         assert_fdi_tx_disabled(dev_priv, pipe);
1574         assert_fdi_rx_disabled(dev_priv, pipe);
1575
1576         /* Ports must be off as well */
1577         assert_pch_ports_disabled(dev_priv, pipe);
1578
1579         reg = PCH_TRANSCONF(pipe);
1580         val = I915_READ(reg);
1581         val &= ~TRANS_ENABLE;
1582         I915_WRITE(reg, val);
1583         /* wait for PCH transcoder off, transcoder state */
1584         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1585                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1586
1587         if (!HAS_PCH_IBX(dev)) {
1588                 /* Workaround: Clear the timing override chicken bit again. */
1589                 reg = TRANS_CHICKEN2(pipe);
1590                 val = I915_READ(reg);
1591                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592                 I915_WRITE(reg, val);
1593         }
1594 }
1595
1596 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1597 {
1598         u32 val;
1599
1600         val = I915_READ(LPT_TRANSCONF);
1601         val &= ~TRANS_ENABLE;
1602         I915_WRITE(LPT_TRANSCONF, val);
1603         /* wait for PCH transcoder off, transcoder state */
1604         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1605                 DRM_ERROR("Failed to disable PCH transcoder\n");
1606
1607         /* Workaround: clear timing override bit. */
1608         val = I915_READ(_TRANSA_CHICKEN2);
1609         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1610         I915_WRITE(_TRANSA_CHICKEN2, val);
1611 }
1612
1613 /**
1614  * intel_enable_pipe - enable a pipe, asserting requirements
1615  * @dev_priv: i915 private structure
1616  * @pipe: pipe to enable
1617  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1618  *
1619  * Enable @pipe, making sure that various hardware specific requirements
1620  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621  *
1622  * @pipe should be %PIPE_A or %PIPE_B.
1623  *
1624  * Will wait until the pipe is actually running (i.e. first vblank) before
1625  * returning.
1626  */
1627 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628                               bool pch_port)
1629 {
1630         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631                                                                       pipe);
1632         enum pipe pch_transcoder;
1633         int reg;
1634         u32 val;
1635
1636         assert_planes_disabled(dev_priv, pipe);
1637         assert_sprites_disabled(dev_priv, pipe);
1638
1639         if (HAS_PCH_LPT(dev_priv->dev))
1640                 pch_transcoder = TRANSCODER_A;
1641         else
1642                 pch_transcoder = pipe;
1643
1644         /*
1645          * A pipe without a PLL won't actually be able to drive bits from
1646          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1647          * need the check.
1648          */
1649         if (!HAS_PCH_SPLIT(dev_priv->dev))
1650                 assert_pll_enabled(dev_priv, pipe);
1651         else {
1652                 if (pch_port) {
1653                         /* if driving the PCH, we need FDI enabled */
1654                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1655                         assert_fdi_tx_pll_enabled(dev_priv,
1656                                                   (enum pipe) cpu_transcoder);
1657                 }
1658                 /* FIXME: assert CPU port conditions for SNB+ */
1659         }
1660
1661         reg = PIPECONF(cpu_transcoder);
1662         val = I915_READ(reg);
1663         if (val & PIPECONF_ENABLE)
1664                 return;
1665
1666         I915_WRITE(reg, val | PIPECONF_ENABLE);
1667         intel_wait_for_vblank(dev_priv->dev, pipe);
1668 }
1669
1670 /**
1671  * intel_disable_pipe - disable a pipe, asserting requirements
1672  * @dev_priv: i915 private structure
1673  * @pipe: pipe to disable
1674  *
1675  * Disable @pipe, making sure that various hardware specific requirements
1676  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677  *
1678  * @pipe should be %PIPE_A or %PIPE_B.
1679  *
1680  * Will wait until the pipe has shut down before returning.
1681  */
1682 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683                                enum pipe pipe)
1684 {
1685         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686                                                                       pipe);
1687         int reg;
1688         u32 val;
1689
1690         /*
1691          * Make sure planes won't keep trying to pump pixels to us,
1692          * or we might hang the display.
1693          */
1694         assert_planes_disabled(dev_priv, pipe);
1695         assert_sprites_disabled(dev_priv, pipe);
1696
1697         /* Don't disable pipe A or pipe A PLLs if needed */
1698         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699                 return;
1700
1701         reg = PIPECONF(cpu_transcoder);
1702         val = I915_READ(reg);
1703         if ((val & PIPECONF_ENABLE) == 0)
1704                 return;
1705
1706         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1707         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708 }
1709
1710 /*
1711  * Plane regs are double buffered, going from enabled->disabled needs a
1712  * trigger in order to latch.  The display address reg provides this.
1713  */
1714 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1715                                       enum plane plane)
1716 {
1717         if (dev_priv->info->gen >= 4)
1718                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719         else
1720                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1721 }
1722
1723 /**
1724  * intel_enable_plane - enable a display plane on a given pipe
1725  * @dev_priv: i915 private structure
1726  * @plane: plane to enable
1727  * @pipe: pipe being fed
1728  *
1729  * Enable @plane on @pipe, making sure that @pipe is running first.
1730  */
1731 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732                                enum plane plane, enum pipe pipe)
1733 {
1734         int reg;
1735         u32 val;
1736
1737         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738         assert_pipe_enabled(dev_priv, pipe);
1739
1740         reg = DSPCNTR(plane);
1741         val = I915_READ(reg);
1742         if (val & DISPLAY_PLANE_ENABLE)
1743                 return;
1744
1745         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1746         intel_flush_display_plane(dev_priv, plane);
1747         intel_wait_for_vblank(dev_priv->dev, pipe);
1748 }
1749
1750 /**
1751  * intel_disable_plane - disable a display plane
1752  * @dev_priv: i915 private structure
1753  * @plane: plane to disable
1754  * @pipe: pipe consuming the data
1755  *
1756  * Disable @plane; should be an independent operation.
1757  */
1758 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759                                 enum plane plane, enum pipe pipe)
1760 {
1761         int reg;
1762         u32 val;
1763
1764         reg = DSPCNTR(plane);
1765         val = I915_READ(reg);
1766         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767                 return;
1768
1769         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1770         intel_flush_display_plane(dev_priv, plane);
1771         intel_wait_for_vblank(dev_priv->dev, pipe);
1772 }
1773
1774 static bool need_vtd_wa(struct drm_device *dev)
1775 {
1776 #ifdef CONFIG_INTEL_IOMMU
1777         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778                 return true;
1779 #endif
1780         return false;
1781 }
1782
1783 int
1784 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1785                            struct drm_i915_gem_object *obj,
1786                            struct intel_ring_buffer *pipelined)
1787 {
1788         struct drm_i915_private *dev_priv = dev->dev_private;
1789         u32 alignment;
1790         int ret;
1791
1792         switch (obj->tiling_mode) {
1793         case I915_TILING_NONE:
1794                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795                         alignment = 128 * 1024;
1796                 else if (INTEL_INFO(dev)->gen >= 4)
1797                         alignment = 4 * 1024;
1798                 else
1799                         alignment = 64 * 1024;
1800                 break;
1801         case I915_TILING_X:
1802                 /* pin() will align the object as required by fence */
1803                 alignment = 0;
1804                 break;
1805         case I915_TILING_Y:
1806                 /* Despite that we check this in framebuffer_init userspace can
1807                  * screw us over and change the tiling after the fact. Only
1808                  * pinned buffers can't change their tiling. */
1809                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1810                 return -EINVAL;
1811         default:
1812                 BUG();
1813         }
1814
1815         /* Note that the w/a also requires 64 PTE of padding following the
1816          * bo. We currently fill all unused PTE with the shadow page and so
1817          * we should always have valid PTE following the scanout preventing
1818          * the VT-d warning.
1819          */
1820         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821                 alignment = 256 * 1024;
1822
1823         dev_priv->mm.interruptible = false;
1824         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1825         if (ret)
1826                 goto err_interruptible;
1827
1828         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829          * fence, whereas 965+ only requires a fence if using
1830          * framebuffer compression.  For simplicity, we always install
1831          * a fence as the cost is not that onerous.
1832          */
1833         ret = i915_gem_object_get_fence(obj);
1834         if (ret)
1835                 goto err_unpin;
1836
1837         i915_gem_object_pin_fence(obj);
1838
1839         dev_priv->mm.interruptible = true;
1840         return 0;
1841
1842 err_unpin:
1843         i915_gem_object_unpin(obj);
1844 err_interruptible:
1845         dev_priv->mm.interruptible = true;
1846         return ret;
1847 }
1848
1849 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850 {
1851         i915_gem_object_unpin_fence(obj);
1852         i915_gem_object_unpin(obj);
1853 }
1854
1855 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856  * is assumed to be a power-of-two. */
1857 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858                                              unsigned int tiling_mode,
1859                                              unsigned int cpp,
1860                                              unsigned int pitch)
1861 {
1862         if (tiling_mode != I915_TILING_NONE) {
1863                 unsigned int tile_rows, tiles;
1864
1865                 tile_rows = *y / 8;
1866                 *y %= 8;
1867
1868                 tiles = *x / (512/cpp);
1869                 *x %= 512/cpp;
1870
1871                 return tile_rows * pitch * 8 + tiles * 4096;
1872         } else {
1873                 unsigned int offset;
1874
1875                 offset = *y * pitch + *x * cpp;
1876                 *y = 0;
1877                 *x = (offset & 4095) / cpp;
1878                 return offset & -4096;
1879         }
1880 }
1881
1882 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883                              int x, int y)
1884 {
1885         struct drm_device *dev = crtc->dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888         struct intel_framebuffer *intel_fb;
1889         struct drm_i915_gem_object *obj;
1890         int plane = intel_crtc->plane;
1891         unsigned long linear_offset;
1892         u32 dspcntr;
1893         u32 reg;
1894
1895         switch (plane) {
1896         case 0:
1897         case 1:
1898                 break;
1899         default:
1900                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1901                 return -EINVAL;
1902         }
1903
1904         intel_fb = to_intel_framebuffer(fb);
1905         obj = intel_fb->obj;
1906
1907         reg = DSPCNTR(plane);
1908         dspcntr = I915_READ(reg);
1909         /* Mask out pixel format bits in case we change it */
1910         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1911         switch (fb->pixel_format) {
1912         case DRM_FORMAT_C8:
1913                 dspcntr |= DISPPLANE_8BPP;
1914                 break;
1915         case DRM_FORMAT_XRGB1555:
1916         case DRM_FORMAT_ARGB1555:
1917                 dspcntr |= DISPPLANE_BGRX555;
1918                 break;
1919         case DRM_FORMAT_RGB565:
1920                 dspcntr |= DISPPLANE_BGRX565;
1921                 break;
1922         case DRM_FORMAT_XRGB8888:
1923         case DRM_FORMAT_ARGB8888:
1924                 dspcntr |= DISPPLANE_BGRX888;
1925                 break;
1926         case DRM_FORMAT_XBGR8888:
1927         case DRM_FORMAT_ABGR8888:
1928                 dspcntr |= DISPPLANE_RGBX888;
1929                 break;
1930         case DRM_FORMAT_XRGB2101010:
1931         case DRM_FORMAT_ARGB2101010:
1932                 dspcntr |= DISPPLANE_BGRX101010;
1933                 break;
1934         case DRM_FORMAT_XBGR2101010:
1935         case DRM_FORMAT_ABGR2101010:
1936                 dspcntr |= DISPPLANE_RGBX101010;
1937                 break;
1938         default:
1939                 BUG();
1940         }
1941
1942         if (INTEL_INFO(dev)->gen >= 4) {
1943                 if (obj->tiling_mode != I915_TILING_NONE)
1944                         dspcntr |= DISPPLANE_TILED;
1945                 else
1946                         dspcntr &= ~DISPPLANE_TILED;
1947         }
1948
1949         I915_WRITE(reg, dspcntr);
1950
1951         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1952
1953         if (INTEL_INFO(dev)->gen >= 4) {
1954                 intel_crtc->dspaddr_offset =
1955                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956                                                        fb->bits_per_pixel / 8,
1957                                                        fb->pitches[0]);
1958                 linear_offset -= intel_crtc->dspaddr_offset;
1959         } else {
1960                 intel_crtc->dspaddr_offset = linear_offset;
1961         }
1962
1963         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1965         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1966         if (INTEL_INFO(dev)->gen >= 4) {
1967                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1969                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1970                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1971         } else
1972                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1973         POSTING_READ(reg);
1974
1975         return 0;
1976 }
1977
1978 static int ironlake_update_plane(struct drm_crtc *crtc,
1979                                  struct drm_framebuffer *fb, int x, int y)
1980 {
1981         struct drm_device *dev = crtc->dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984         struct intel_framebuffer *intel_fb;
1985         struct drm_i915_gem_object *obj;
1986         int plane = intel_crtc->plane;
1987         unsigned long linear_offset;
1988         u32 dspcntr;
1989         u32 reg;
1990
1991         switch (plane) {
1992         case 0:
1993         case 1:
1994         case 2:
1995                 break;
1996         default:
1997                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1998                 return -EINVAL;
1999         }
2000
2001         intel_fb = to_intel_framebuffer(fb);
2002         obj = intel_fb->obj;
2003
2004         reg = DSPCNTR(plane);
2005         dspcntr = I915_READ(reg);
2006         /* Mask out pixel format bits in case we change it */
2007         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2008         switch (fb->pixel_format) {
2009         case DRM_FORMAT_C8:
2010                 dspcntr |= DISPPLANE_8BPP;
2011                 break;
2012         case DRM_FORMAT_RGB565:
2013                 dspcntr |= DISPPLANE_BGRX565;
2014                 break;
2015         case DRM_FORMAT_XRGB8888:
2016         case DRM_FORMAT_ARGB8888:
2017                 dspcntr |= DISPPLANE_BGRX888;
2018                 break;
2019         case DRM_FORMAT_XBGR8888:
2020         case DRM_FORMAT_ABGR8888:
2021                 dspcntr |= DISPPLANE_RGBX888;
2022                 break;
2023         case DRM_FORMAT_XRGB2101010:
2024         case DRM_FORMAT_ARGB2101010:
2025                 dspcntr |= DISPPLANE_BGRX101010;
2026                 break;
2027         case DRM_FORMAT_XBGR2101010:
2028         case DRM_FORMAT_ABGR2101010:
2029                 dspcntr |= DISPPLANE_RGBX101010;
2030                 break;
2031         default:
2032                 BUG();
2033         }
2034
2035         if (obj->tiling_mode != I915_TILING_NONE)
2036                 dspcntr |= DISPPLANE_TILED;
2037         else
2038                 dspcntr &= ~DISPPLANE_TILED;
2039
2040         /* must disable */
2041         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043         I915_WRITE(reg, dspcntr);
2044
2045         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2046         intel_crtc->dspaddr_offset =
2047                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048                                                fb->bits_per_pixel / 8,
2049                                                fb->pitches[0]);
2050         linear_offset -= intel_crtc->dspaddr_offset;
2051
2052         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2054         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2055         I915_MODIFY_DISPBASE(DSPSURF(plane),
2056                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2057         if (IS_HASWELL(dev)) {
2058                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059         } else {
2060                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062         }
2063         POSTING_READ(reg);
2064
2065         return 0;
2066 }
2067
2068 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2069 static int
2070 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071                            int x, int y, enum mode_set_atomic state)
2072 {
2073         struct drm_device *dev = crtc->dev;
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075
2076         if (dev_priv->display.disable_fbc)
2077                 dev_priv->display.disable_fbc(dev);
2078         intel_increase_pllclock(crtc);
2079
2080         return dev_priv->display.update_plane(crtc, fb, x, y);
2081 }
2082
2083 void intel_display_handle_reset(struct drm_device *dev)
2084 {
2085         struct drm_i915_private *dev_priv = dev->dev_private;
2086         struct drm_crtc *crtc;
2087
2088         /*
2089          * Flips in the rings have been nuked by the reset,
2090          * so complete all pending flips so that user space
2091          * will get its events and not get stuck.
2092          *
2093          * Also update the base address of all primary
2094          * planes to the the last fb to make sure we're
2095          * showing the correct fb after a reset.
2096          *
2097          * Need to make two loops over the crtcs so that we
2098          * don't try to grab a crtc mutex before the
2099          * pending_flip_queue really got woken up.
2100          */
2101
2102         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104                 enum plane plane = intel_crtc->plane;
2105
2106                 intel_prepare_page_flip(dev, plane);
2107                 intel_finish_page_flip_plane(dev, plane);
2108         }
2109
2110         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113                 mutex_lock(&crtc->mutex);
2114                 if (intel_crtc->active)
2115                         dev_priv->display.update_plane(crtc, crtc->fb,
2116                                                        crtc->x, crtc->y);
2117                 mutex_unlock(&crtc->mutex);
2118         }
2119 }
2120
2121 static int
2122 intel_finish_fb(struct drm_framebuffer *old_fb)
2123 {
2124         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126         bool was_interruptible = dev_priv->mm.interruptible;
2127         int ret;
2128
2129         /* Big Hammer, we also need to ensure that any pending
2130          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131          * current scanout is retired before unpinning the old
2132          * framebuffer.
2133          *
2134          * This should only fail upon a hung GPU, in which case we
2135          * can safely continue.
2136          */
2137         dev_priv->mm.interruptible = false;
2138         ret = i915_gem_object_finish_gpu(obj);
2139         dev_priv->mm.interruptible = was_interruptible;
2140
2141         return ret;
2142 }
2143
2144 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145 {
2146         struct drm_device *dev = crtc->dev;
2147         struct drm_i915_master_private *master_priv;
2148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150         if (!dev->primary->master)
2151                 return;
2152
2153         master_priv = dev->primary->master->driver_priv;
2154         if (!master_priv->sarea_priv)
2155                 return;
2156
2157         switch (intel_crtc->pipe) {
2158         case 0:
2159                 master_priv->sarea_priv->pipeA_x = x;
2160                 master_priv->sarea_priv->pipeA_y = y;
2161                 break;
2162         case 1:
2163                 master_priv->sarea_priv->pipeB_x = x;
2164                 master_priv->sarea_priv->pipeB_y = y;
2165                 break;
2166         default:
2167                 break;
2168         }
2169 }
2170
2171 static int
2172 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2173                     struct drm_framebuffer *fb)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         struct drm_framebuffer *old_fb;
2179         int ret;
2180
2181         /* no fb bound */
2182         if (!fb) {
2183                 DRM_ERROR("No FB bound\n");
2184                 return 0;
2185         }
2186
2187         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2188                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189                           plane_name(intel_crtc->plane),
2190                           INTEL_INFO(dev)->num_pipes);
2191                 return -EINVAL;
2192         }
2193
2194         mutex_lock(&dev->struct_mutex);
2195         ret = intel_pin_and_fence_fb_obj(dev,
2196                                          to_intel_framebuffer(fb)->obj,
2197                                          NULL);
2198         if (ret != 0) {
2199                 mutex_unlock(&dev->struct_mutex);
2200                 DRM_ERROR("pin & fence failed\n");
2201                 return ret;
2202         }
2203
2204         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2205         if (ret) {
2206                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2207                 mutex_unlock(&dev->struct_mutex);
2208                 DRM_ERROR("failed to update base address\n");
2209                 return ret;
2210         }
2211
2212         old_fb = crtc->fb;
2213         crtc->fb = fb;
2214         crtc->x = x;
2215         crtc->y = y;
2216
2217         if (old_fb) {
2218                 if (intel_crtc->active && old_fb != fb)
2219                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2220                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2221         }
2222
2223         intel_update_fbc(dev);
2224         mutex_unlock(&dev->struct_mutex);
2225
2226         intel_crtc_update_sarea_pos(crtc, x, y);
2227
2228         return 0;
2229 }
2230
2231 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236         int pipe = intel_crtc->pipe;
2237         u32 reg, temp;
2238
2239         /* enable normal train */
2240         reg = FDI_TX_CTL(pipe);
2241         temp = I915_READ(reg);
2242         if (IS_IVYBRIDGE(dev)) {
2243                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2245         } else {
2246                 temp &= ~FDI_LINK_TRAIN_NONE;
2247                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2248         }
2249         I915_WRITE(reg, temp);
2250
2251         reg = FDI_RX_CTL(pipe);
2252         temp = I915_READ(reg);
2253         if (HAS_PCH_CPT(dev)) {
2254                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256         } else {
2257                 temp &= ~FDI_LINK_TRAIN_NONE;
2258                 temp |= FDI_LINK_TRAIN_NONE;
2259         }
2260         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262         /* wait one idle pattern time */
2263         POSTING_READ(reg);
2264         udelay(1000);
2265
2266         /* IVB wants error correction enabled */
2267         if (IS_IVYBRIDGE(dev))
2268                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269                            FDI_FE_ERRC_ENABLE);
2270 }
2271
2272 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273 {
2274         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275 }
2276
2277 static void ivb_modeset_global_resources(struct drm_device *dev)
2278 {
2279         struct drm_i915_private *dev_priv = dev->dev_private;
2280         struct intel_crtc *pipe_B_crtc =
2281                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282         struct intel_crtc *pipe_C_crtc =
2283                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284         uint32_t temp;
2285
2286         /*
2287          * When everything is off disable fdi C so that we could enable fdi B
2288          * with all lanes. Note that we don't care about enabled pipes without
2289          * an enabled pch encoder.
2290          */
2291         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292             !pipe_has_enabled_pch(pipe_C_crtc)) {
2293                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296                 temp = I915_READ(SOUTH_CHICKEN1);
2297                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299                 I915_WRITE(SOUTH_CHICKEN1, temp);
2300         }
2301 }
2302
2303 /* The FDI link training functions for ILK/Ibexpeak. */
2304 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305 {
2306         struct drm_device *dev = crtc->dev;
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309         int pipe = intel_crtc->pipe;
2310         int plane = intel_crtc->plane;
2311         u32 reg, temp, tries;
2312
2313         /* FDI needs bits from pipe & plane first */
2314         assert_pipe_enabled(dev_priv, pipe);
2315         assert_plane_enabled(dev_priv, plane);
2316
2317         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318            for train result */
2319         reg = FDI_RX_IMR(pipe);
2320         temp = I915_READ(reg);
2321         temp &= ~FDI_RX_SYMBOL_LOCK;
2322         temp &= ~FDI_RX_BIT_LOCK;
2323         I915_WRITE(reg, temp);
2324         I915_READ(reg);
2325         udelay(150);
2326
2327         /* enable CPU FDI TX and PCH FDI RX */
2328         reg = FDI_TX_CTL(pipe);
2329         temp = I915_READ(reg);
2330         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2332         temp &= ~FDI_LINK_TRAIN_NONE;
2333         temp |= FDI_LINK_TRAIN_PATTERN_1;
2334         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2335
2336         reg = FDI_RX_CTL(pipe);
2337         temp = I915_READ(reg);
2338         temp &= ~FDI_LINK_TRAIN_NONE;
2339         temp |= FDI_LINK_TRAIN_PATTERN_1;
2340         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342         POSTING_READ(reg);
2343         udelay(150);
2344
2345         /* Ironlake workaround, enable clock pointer after FDI enable*/
2346         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348                    FDI_RX_PHASE_SYNC_POINTER_EN);
2349
2350         reg = FDI_RX_IIR(pipe);
2351         for (tries = 0; tries < 5; tries++) {
2352                 temp = I915_READ(reg);
2353                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355                 if ((temp & FDI_RX_BIT_LOCK)) {
2356                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2357                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2358                         break;
2359                 }
2360         }
2361         if (tries == 5)
2362                 DRM_ERROR("FDI train 1 fail!\n");
2363
2364         /* Train 2 */
2365         reg = FDI_TX_CTL(pipe);
2366         temp = I915_READ(reg);
2367         temp &= ~FDI_LINK_TRAIN_NONE;
2368         temp |= FDI_LINK_TRAIN_PATTERN_2;
2369         I915_WRITE(reg, temp);
2370
2371         reg = FDI_RX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~FDI_LINK_TRAIN_NONE;
2374         temp |= FDI_LINK_TRAIN_PATTERN_2;
2375         I915_WRITE(reg, temp);
2376
2377         POSTING_READ(reg);
2378         udelay(150);
2379
2380         reg = FDI_RX_IIR(pipe);
2381         for (tries = 0; tries < 5; tries++) {
2382                 temp = I915_READ(reg);
2383                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385                 if (temp & FDI_RX_SYMBOL_LOCK) {
2386                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2387                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2388                         break;
2389                 }
2390         }
2391         if (tries == 5)
2392                 DRM_ERROR("FDI train 2 fail!\n");
2393
2394         DRM_DEBUG_KMS("FDI train done\n");
2395
2396 }
2397
2398 static const int snb_b_fdi_train_param[] = {
2399         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403 };
2404
2405 /* The FDI link training functions for SNB/Cougarpoint. */
2406 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407 {
2408         struct drm_device *dev = crtc->dev;
2409         struct drm_i915_private *dev_priv = dev->dev_private;
2410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411         int pipe = intel_crtc->pipe;
2412         u32 reg, temp, i, retry;
2413
2414         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415            for train result */
2416         reg = FDI_RX_IMR(pipe);
2417         temp = I915_READ(reg);
2418         temp &= ~FDI_RX_SYMBOL_LOCK;
2419         temp &= ~FDI_RX_BIT_LOCK;
2420         I915_WRITE(reg, temp);
2421
2422         POSTING_READ(reg);
2423         udelay(150);
2424
2425         /* enable CPU FDI TX and PCH FDI RX */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2430         temp &= ~FDI_LINK_TRAIN_NONE;
2431         temp |= FDI_LINK_TRAIN_PATTERN_1;
2432         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433         /* SNB-B */
2434         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2435         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436
2437         I915_WRITE(FDI_RX_MISC(pipe),
2438                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
2440         reg = FDI_RX_CTL(pipe);
2441         temp = I915_READ(reg);
2442         if (HAS_PCH_CPT(dev)) {
2443                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445         } else {
2446                 temp &= ~FDI_LINK_TRAIN_NONE;
2447                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448         }
2449         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451         POSTING_READ(reg);
2452         udelay(150);
2453
2454         for (i = 0; i < 4; i++) {
2455                 reg = FDI_TX_CTL(pipe);
2456                 temp = I915_READ(reg);
2457                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458                 temp |= snb_b_fdi_train_param[i];
2459                 I915_WRITE(reg, temp);
2460
2461                 POSTING_READ(reg);
2462                 udelay(500);
2463
2464                 for (retry = 0; retry < 5; retry++) {
2465                         reg = FDI_RX_IIR(pipe);
2466                         temp = I915_READ(reg);
2467                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468                         if (temp & FDI_RX_BIT_LOCK) {
2469                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471                                 break;
2472                         }
2473                         udelay(50);
2474                 }
2475                 if (retry < 5)
2476                         break;
2477         }
2478         if (i == 4)
2479                 DRM_ERROR("FDI train 1 fail!\n");
2480
2481         /* Train 2 */
2482         reg = FDI_TX_CTL(pipe);
2483         temp = I915_READ(reg);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_2;
2486         if (IS_GEN6(dev)) {
2487                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488                 /* SNB-B */
2489                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490         }
2491         I915_WRITE(reg, temp);
2492
2493         reg = FDI_RX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         if (HAS_PCH_CPT(dev)) {
2496                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498         } else {
2499                 temp &= ~FDI_LINK_TRAIN_NONE;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501         }
2502         I915_WRITE(reg, temp);
2503
2504         POSTING_READ(reg);
2505         udelay(150);
2506
2507         for (i = 0; i < 4; i++) {
2508                 reg = FDI_TX_CTL(pipe);
2509                 temp = I915_READ(reg);
2510                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511                 temp |= snb_b_fdi_train_param[i];
2512                 I915_WRITE(reg, temp);
2513
2514                 POSTING_READ(reg);
2515                 udelay(500);
2516
2517                 for (retry = 0; retry < 5; retry++) {
2518                         reg = FDI_RX_IIR(pipe);
2519                         temp = I915_READ(reg);
2520                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521                         if (temp & FDI_RX_SYMBOL_LOCK) {
2522                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524                                 break;
2525                         }
2526                         udelay(50);
2527                 }
2528                 if (retry < 5)
2529                         break;
2530         }
2531         if (i == 4)
2532                 DRM_ERROR("FDI train 2 fail!\n");
2533
2534         DRM_DEBUG_KMS("FDI train done.\n");
2535 }
2536
2537 /* Manual link training for Ivy Bridge A0 parts */
2538 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539 {
2540         struct drm_device *dev = crtc->dev;
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543         int pipe = intel_crtc->pipe;
2544         u32 reg, temp, i;
2545
2546         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547            for train result */
2548         reg = FDI_RX_IMR(pipe);
2549         temp = I915_READ(reg);
2550         temp &= ~FDI_RX_SYMBOL_LOCK;
2551         temp &= ~FDI_RX_BIT_LOCK;
2552         I915_WRITE(reg, temp);
2553
2554         POSTING_READ(reg);
2555         udelay(150);
2556
2557         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558                       I915_READ(FDI_RX_IIR(pipe)));
2559
2560         /* enable CPU FDI TX and PCH FDI RX */
2561         reg = FDI_TX_CTL(pipe);
2562         temp = I915_READ(reg);
2563         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2565         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569         temp |= FDI_COMPOSITE_SYNC;
2570         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
2572         I915_WRITE(FDI_RX_MISC(pipe),
2573                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
2575         reg = FDI_RX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_LINK_TRAIN_AUTO;
2578         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580         temp |= FDI_COMPOSITE_SYNC;
2581         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583         POSTING_READ(reg);
2584         udelay(150);
2585
2586         for (i = 0; i < 4; i++) {
2587                 reg = FDI_TX_CTL(pipe);
2588                 temp = I915_READ(reg);
2589                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590                 temp |= snb_b_fdi_train_param[i];
2591                 I915_WRITE(reg, temp);
2592
2593                 POSTING_READ(reg);
2594                 udelay(500);
2595
2596                 reg = FDI_RX_IIR(pipe);
2597                 temp = I915_READ(reg);
2598                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600                 if (temp & FDI_RX_BIT_LOCK ||
2601                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2603                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2604                         break;
2605                 }
2606         }
2607         if (i == 4)
2608                 DRM_ERROR("FDI train 1 fail!\n");
2609
2610         /* Train 2 */
2611         reg = FDI_TX_CTL(pipe);
2612         temp = I915_READ(reg);
2613         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617         I915_WRITE(reg, temp);
2618
2619         reg = FDI_RX_CTL(pipe);
2620         temp = I915_READ(reg);
2621         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623         I915_WRITE(reg, temp);
2624
2625         POSTING_READ(reg);
2626         udelay(150);
2627
2628         for (i = 0; i < 4; i++) {
2629                 reg = FDI_TX_CTL(pipe);
2630                 temp = I915_READ(reg);
2631                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632                 temp |= snb_b_fdi_train_param[i];
2633                 I915_WRITE(reg, temp);
2634
2635                 POSTING_READ(reg);
2636                 udelay(500);
2637
2638                 reg = FDI_RX_IIR(pipe);
2639                 temp = I915_READ(reg);
2640                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642                 if (temp & FDI_RX_SYMBOL_LOCK) {
2643                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2644                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2645                         break;
2646                 }
2647         }
2648         if (i == 4)
2649                 DRM_ERROR("FDI train 2 fail!\n");
2650
2651         DRM_DEBUG_KMS("FDI train done.\n");
2652 }
2653
2654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2655 {
2656         struct drm_device *dev = intel_crtc->base.dev;
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         int pipe = intel_crtc->pipe;
2659         u32 reg, temp;
2660
2661
2662         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2663         reg = FDI_RX_CTL(pipe);
2664         temp = I915_READ(reg);
2665         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2667         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2668         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670         POSTING_READ(reg);
2671         udelay(200);
2672
2673         /* Switch from Rawclk to PCDclk */
2674         temp = I915_READ(reg);
2675         I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677         POSTING_READ(reg);
2678         udelay(200);
2679
2680         /* Enable CPU FDI TX PLL, always on for Ironlake */
2681         reg = FDI_TX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2685
2686                 POSTING_READ(reg);
2687                 udelay(100);
2688         }
2689 }
2690
2691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692 {
2693         struct drm_device *dev = intel_crtc->base.dev;
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         int pipe = intel_crtc->pipe;
2696         u32 reg, temp;
2697
2698         /* Switch from PCDclk to Rawclk */
2699         reg = FDI_RX_CTL(pipe);
2700         temp = I915_READ(reg);
2701         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703         /* Disable CPU FDI TX PLL */
2704         reg = FDI_TX_CTL(pipe);
2705         temp = I915_READ(reg);
2706         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708         POSTING_READ(reg);
2709         udelay(100);
2710
2711         reg = FDI_RX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715         /* Wait for the clocks to turn off. */
2716         POSTING_READ(reg);
2717         udelay(100);
2718 }
2719
2720 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721 {
2722         struct drm_device *dev = crtc->dev;
2723         struct drm_i915_private *dev_priv = dev->dev_private;
2724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725         int pipe = intel_crtc->pipe;
2726         u32 reg, temp;
2727
2728         /* disable CPU FDI tx and PCH FDI rx */
2729         reg = FDI_TX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732         POSTING_READ(reg);
2733
2734         reg = FDI_RX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         temp &= ~(0x7 << 16);
2737         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2738         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740         POSTING_READ(reg);
2741         udelay(100);
2742
2743         /* Ironlake workaround, disable clock pointer after downing FDI */
2744         if (HAS_PCH_IBX(dev)) {
2745                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2746         }
2747
2748         /* still set train pattern 1 */
2749         reg = FDI_TX_CTL(pipe);
2750         temp = I915_READ(reg);
2751         temp &= ~FDI_LINK_TRAIN_NONE;
2752         temp |= FDI_LINK_TRAIN_PATTERN_1;
2753         I915_WRITE(reg, temp);
2754
2755         reg = FDI_RX_CTL(pipe);
2756         temp = I915_READ(reg);
2757         if (HAS_PCH_CPT(dev)) {
2758                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760         } else {
2761                 temp &= ~FDI_LINK_TRAIN_NONE;
2762                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763         }
2764         /* BPC in FDI rx is consistent with that in PIPECONF */
2765         temp &= ~(0x07 << 16);
2766         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2767         I915_WRITE(reg, temp);
2768
2769         POSTING_READ(reg);
2770         udelay(100);
2771 }
2772
2773 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         unsigned long flags;
2779         bool pending;
2780
2781         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2783                 return false;
2784
2785         spin_lock_irqsave(&dev->event_lock, flags);
2786         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787         spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789         return pending;
2790 }
2791
2792 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793 {
2794         struct drm_device *dev = crtc->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796
2797         if (crtc->fb == NULL)
2798                 return;
2799
2800         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
2802         wait_event(dev_priv->pending_flip_queue,
2803                    !intel_crtc_has_pending_flip(crtc));
2804
2805         mutex_lock(&dev->struct_mutex);
2806         intel_finish_fb(crtc->fb);
2807         mutex_unlock(&dev->struct_mutex);
2808 }
2809
2810 /* Program iCLKIP clock to the desired frequency */
2811 static void lpt_program_iclkip(struct drm_crtc *crtc)
2812 {
2813         struct drm_device *dev = crtc->dev;
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816         u32 temp;
2817
2818         mutex_lock(&dev_priv->dpio_lock);
2819
2820         /* It is necessary to ungate the pixclk gate prior to programming
2821          * the divisors, and gate it back when it is done.
2822          */
2823         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825         /* Disable SSCCTL */
2826         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2827                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828                                 SBI_SSCCTL_DISABLE,
2829                         SBI_ICLK);
2830
2831         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832         if (crtc->mode.clock == 20000) {
2833                 auxdiv = 1;
2834                 divsel = 0x41;
2835                 phaseinc = 0x20;
2836         } else {
2837                 /* The iCLK virtual clock root frequency is in MHz,
2838                  * but the crtc->mode.clock in in KHz. To get the divisors,
2839                  * it is necessary to divide one by another, so we
2840                  * convert the virtual clock precision to KHz here for higher
2841                  * precision.
2842                  */
2843                 u32 iclk_virtual_root_freq = 172800 * 1000;
2844                 u32 iclk_pi_range = 64;
2845                 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848                 msb_divisor_value = desired_divisor / iclk_pi_range;
2849                 pi_value = desired_divisor % iclk_pi_range;
2850
2851                 auxdiv = 0;
2852                 divsel = msb_divisor_value - 2;
2853                 phaseinc = pi_value;
2854         }
2855
2856         /* This should not happen with any sane values */
2857         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863                         crtc->mode.clock,
2864                         auxdiv,
2865                         divsel,
2866                         phasedir,
2867                         phaseinc);
2868
2869         /* Program SSCDIVINTPHASE6 */
2870         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2871         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2877         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2878
2879         /* Program SSCAUXDIV */
2880         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2881         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2883         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2884
2885         /* Enable modulator and associated divider */
2886         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2887         temp &= ~SBI_SSCCTL_DISABLE;
2888         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2889
2890         /* Wait for initialization time */
2891         udelay(24);
2892
2893         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2894
2895         mutex_unlock(&dev_priv->dpio_lock);
2896 }
2897
2898 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899                                                 enum pipe pch_transcoder)
2900 {
2901         struct drm_device *dev = crtc->base.dev;
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906                    I915_READ(HTOTAL(cpu_transcoder)));
2907         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908                    I915_READ(HBLANK(cpu_transcoder)));
2909         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910                    I915_READ(HSYNC(cpu_transcoder)));
2911
2912         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913                    I915_READ(VTOTAL(cpu_transcoder)));
2914         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915                    I915_READ(VBLANK(cpu_transcoder)));
2916         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917                    I915_READ(VSYNC(cpu_transcoder)));
2918         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920 }
2921
2922 /*
2923  * Enable PCH resources required for PCH ports:
2924  *   - PCH PLLs
2925  *   - FDI training & RX/TX
2926  *   - update transcoder timings
2927  *   - DP transcoding bits
2928  *   - transcoder
2929  */
2930 static void ironlake_pch_enable(struct drm_crtc *crtc)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935         int pipe = intel_crtc->pipe;
2936         u32 reg, temp;
2937
2938         assert_pch_transcoder_disabled(dev_priv, pipe);
2939
2940         /* Write the TU size bits before fdi link training, so that error
2941          * detection works. */
2942         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
2945         /* For PCH output, training FDI link */
2946         dev_priv->display.fdi_link_train(crtc);
2947
2948         /* XXX: pch pll's can be enabled any time before we enable the PCH
2949          * transcoder, and we actually should do this to not upset any PCH
2950          * transcoder that already use the clock when we share it.
2951          *
2952          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953          * unconditionally resets the pll - we need that to have the right LVDS
2954          * enable sequence. */
2955         ironlake_enable_pch_pll(intel_crtc);
2956
2957         if (HAS_PCH_CPT(dev)) {
2958                 u32 sel;
2959
2960                 temp = I915_READ(PCH_DPLL_SEL);
2961                 switch (pipe) {
2962                 default:
2963                 case 0:
2964                         temp |= TRANSA_DPLL_ENABLE;
2965                         sel = TRANSA_DPLLB_SEL;
2966                         break;
2967                 case 1:
2968                         temp |= TRANSB_DPLL_ENABLE;
2969                         sel = TRANSB_DPLLB_SEL;
2970                         break;
2971                 case 2:
2972                         temp |= TRANSC_DPLL_ENABLE;
2973                         sel = TRANSC_DPLLB_SEL;
2974                         break;
2975                 }
2976                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977                         temp |= sel;
2978                 else
2979                         temp &= ~sel;
2980                 I915_WRITE(PCH_DPLL_SEL, temp);
2981         }
2982
2983         /* set transcoder timing, panel must allow it */
2984         assert_panel_unlocked(dev_priv, pipe);
2985         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2986
2987         intel_fdi_normal_train(crtc);
2988
2989         /* For PCH DP, enable TRANS_DP_CTL */
2990         if (HAS_PCH_CPT(dev) &&
2991             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2993                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2994                 reg = TRANS_DP_CTL(pipe);
2995                 temp = I915_READ(reg);
2996                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2997                           TRANS_DP_SYNC_MASK |
2998                           TRANS_DP_BPC_MASK);
2999                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000                          TRANS_DP_ENH_FRAMING);
3001                 temp |= bpc << 9; /* same format but at 11:9 */
3002
3003                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3004                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3005                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3006                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3007
3008                 switch (intel_trans_dp_port_sel(crtc)) {
3009                 case PCH_DP_B:
3010                         temp |= TRANS_DP_PORT_SEL_B;
3011                         break;
3012                 case PCH_DP_C:
3013                         temp |= TRANS_DP_PORT_SEL_C;
3014                         break;
3015                 case PCH_DP_D:
3016                         temp |= TRANS_DP_PORT_SEL_D;
3017                         break;
3018                 default:
3019                         BUG();
3020                 }
3021
3022                 I915_WRITE(reg, temp);
3023         }
3024
3025         ironlake_enable_pch_transcoder(dev_priv, pipe);
3026 }
3027
3028 static void lpt_pch_enable(struct drm_crtc *crtc)
3029 {
3030         struct drm_device *dev = crtc->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3033         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3034
3035         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3036
3037         lpt_program_iclkip(crtc);
3038
3039         /* Set transcoder timing. */
3040         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3041
3042         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3043 }
3044
3045 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046 {
3047         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049         if (pll == NULL)
3050                 return;
3051
3052         if (pll->refcount == 0) {
3053                 WARN(1, "bad PCH PLL refcount\n");
3054                 return;
3055         }
3056
3057         --pll->refcount;
3058         intel_crtc->pch_pll = NULL;
3059 }
3060
3061 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062 {
3063         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064         struct intel_pch_pll *pll;
3065         int i;
3066
3067         pll = intel_crtc->pch_pll;
3068         if (pll) {
3069                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070                               intel_crtc->base.base.id, pll->pll_reg);
3071                 goto prepare;
3072         }
3073
3074         if (HAS_PCH_IBX(dev_priv->dev)) {
3075                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076                 i = intel_crtc->pipe;
3077                 pll = &dev_priv->pch_plls[i];
3078
3079                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080                               intel_crtc->base.base.id, pll->pll_reg);
3081
3082                 goto found;
3083         }
3084
3085         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086                 pll = &dev_priv->pch_plls[i];
3087
3088                 /* Only want to check enabled timings first */
3089                 if (pll->refcount == 0)
3090                         continue;
3091
3092                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093                     fp == I915_READ(pll->fp0_reg)) {
3094                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095                                       intel_crtc->base.base.id,
3096                                       pll->pll_reg, pll->refcount, pll->active);
3097
3098                         goto found;
3099                 }
3100         }
3101
3102         /* Ok no matching timings, maybe there's a free one? */
3103         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104                 pll = &dev_priv->pch_plls[i];
3105                 if (pll->refcount == 0) {
3106                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107                                       intel_crtc->base.base.id, pll->pll_reg);
3108                         goto found;
3109                 }
3110         }
3111
3112         return NULL;
3113
3114 found:
3115         intel_crtc->pch_pll = pll;
3116         pll->refcount++;
3117         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3118 prepare: /* separate function? */
3119         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3120
3121         /* Wait for the clocks to stabilize before rewriting the regs */
3122         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3123         POSTING_READ(pll->pll_reg);
3124         udelay(150);
3125
3126         I915_WRITE(pll->fp0_reg, fp);
3127         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3128         pll->on = false;
3129         return pll;
3130 }
3131
3132 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3133 {
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135         int dslreg = PIPEDSL(pipe);
3136         u32 temp;
3137
3138         temp = I915_READ(dslreg);
3139         udelay(500);
3140         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3141                 if (wait_for(I915_READ(dslreg) != temp, 5))
3142                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3143         }
3144 }
3145
3146 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147 {
3148         struct drm_device *dev = crtc->base.dev;
3149         struct drm_i915_private *dev_priv = dev->dev_private;
3150         int pipe = crtc->pipe;
3151
3152         if (crtc->config.pch_pfit.size) {
3153                 /* Force use of hard-coded filter coefficients
3154                  * as some pre-programmed values are broken,
3155                  * e.g. x201.
3156                  */
3157                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159                                                  PF_PIPE_SEL_IVB(pipe));
3160                 else
3161                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164         }
3165 }
3166
3167 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3168 {
3169         struct drm_device *dev = crtc->dev;
3170         struct drm_i915_private *dev_priv = dev->dev_private;
3171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172         struct intel_encoder *encoder;
3173         int pipe = intel_crtc->pipe;
3174         int plane = intel_crtc->plane;
3175         u32 temp;
3176
3177         WARN_ON(!crtc->enabled);
3178
3179         if (intel_crtc->active)
3180                 return;
3181
3182         intel_crtc->active = true;
3183
3184         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3185         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3186
3187         intel_update_watermarks(dev);
3188
3189         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3190                 temp = I915_READ(PCH_LVDS);
3191                 if ((temp & LVDS_PORT_EN) == 0)
3192                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3193         }
3194
3195
3196         if (intel_crtc->config.has_pch_encoder) {
3197                 /* Note: FDI PLL enabling _must_ be done before we enable the
3198                  * cpu pipes, hence this is separate from all the other fdi/pch
3199                  * enabling. */
3200                 ironlake_fdi_pll_enable(intel_crtc);
3201         } else {
3202                 assert_fdi_tx_disabled(dev_priv, pipe);
3203                 assert_fdi_rx_disabled(dev_priv, pipe);
3204         }
3205
3206         for_each_encoder_on_crtc(dev, crtc, encoder)
3207                 if (encoder->pre_enable)
3208                         encoder->pre_enable(encoder);
3209
3210         /* Enable panel fitting for LVDS */
3211         ironlake_pfit_enable(intel_crtc);
3212
3213         /*
3214          * On ILK+ LUT must be loaded before the pipe is running but with
3215          * clocks enabled
3216          */
3217         intel_crtc_load_lut(crtc);
3218
3219         intel_enable_pipe(dev_priv, pipe,
3220                           intel_crtc->config.has_pch_encoder);
3221         intel_enable_plane(dev_priv, plane, pipe);
3222
3223         if (intel_crtc->config.has_pch_encoder)
3224                 ironlake_pch_enable(crtc);
3225
3226         mutex_lock(&dev->struct_mutex);
3227         intel_update_fbc(dev);
3228         mutex_unlock(&dev->struct_mutex);
3229
3230         intel_crtc_update_cursor(crtc, true);
3231
3232         for_each_encoder_on_crtc(dev, crtc, encoder)
3233                 encoder->enable(encoder);
3234
3235         if (HAS_PCH_CPT(dev))
3236                 cpt_verify_modeset(dev, intel_crtc->pipe);
3237
3238         /*
3239          * There seems to be a race in PCH platform hw (at least on some
3240          * outputs) where an enabled pipe still completes any pageflip right
3241          * away (as if the pipe is off) instead of waiting for vblank. As soon
3242          * as the first vblank happend, everything works as expected. Hence just
3243          * wait for one vblank before returning to avoid strange things
3244          * happening.
3245          */
3246         intel_wait_for_vblank(dev, intel_crtc->pipe);
3247 }
3248
3249 /* IPS only exists on ULT machines and is tied to pipe A. */
3250 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3251 {
3252         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3253 }
3254
3255 static void hsw_enable_ips(struct intel_crtc *crtc)
3256 {
3257         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258
3259         if (!crtc->config.ips_enabled)
3260                 return;
3261
3262         /* We can only enable IPS after we enable a plane and wait for a vblank.
3263          * We guarantee that the plane is enabled by calling intel_enable_ips
3264          * only after intel_enable_plane. And intel_enable_plane already waits
3265          * for a vblank, so all we need to do here is to enable the IPS bit. */
3266         assert_plane_enabled(dev_priv, crtc->plane);
3267         I915_WRITE(IPS_CTL, IPS_ENABLE);
3268 }
3269
3270 static void hsw_disable_ips(struct intel_crtc *crtc)
3271 {
3272         struct drm_device *dev = crtc->base.dev;
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274
3275         if (!crtc->config.ips_enabled)
3276                 return;
3277
3278         assert_plane_enabled(dev_priv, crtc->plane);
3279         I915_WRITE(IPS_CTL, 0);
3280
3281         /* We need to wait for a vblank before we can disable the plane. */
3282         intel_wait_for_vblank(dev, crtc->pipe);
3283 }
3284
3285 static void haswell_crtc_enable(struct drm_crtc *crtc)
3286 {
3287         struct drm_device *dev = crtc->dev;
3288         struct drm_i915_private *dev_priv = dev->dev_private;
3289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290         struct intel_encoder *encoder;
3291         int pipe = intel_crtc->pipe;
3292         int plane = intel_crtc->plane;
3293
3294         WARN_ON(!crtc->enabled);
3295
3296         if (intel_crtc->active)
3297                 return;
3298
3299         intel_crtc->active = true;
3300
3301         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3302         if (intel_crtc->config.has_pch_encoder)
3303                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3304
3305         intel_update_watermarks(dev);
3306
3307         if (intel_crtc->config.has_pch_encoder)
3308                 dev_priv->display.fdi_link_train(crtc);
3309
3310         for_each_encoder_on_crtc(dev, crtc, encoder)
3311                 if (encoder->pre_enable)
3312                         encoder->pre_enable(encoder);
3313
3314         intel_ddi_enable_pipe_clock(intel_crtc);
3315
3316         /* Enable panel fitting for eDP */
3317         ironlake_pfit_enable(intel_crtc);
3318
3319         /*
3320          * On ILK+ LUT must be loaded before the pipe is running but with
3321          * clocks enabled
3322          */
3323         intel_crtc_load_lut(crtc);
3324
3325         intel_ddi_set_pipe_settings(crtc);
3326         intel_ddi_enable_transcoder_func(crtc);
3327
3328         intel_enable_pipe(dev_priv, pipe,
3329                           intel_crtc->config.has_pch_encoder);
3330         intel_enable_plane(dev_priv, plane, pipe);
3331
3332         hsw_enable_ips(intel_crtc);
3333
3334         if (intel_crtc->config.has_pch_encoder)
3335                 lpt_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         intel_crtc_update_cursor(crtc, true);
3342
3343         for_each_encoder_on_crtc(dev, crtc, encoder)
3344                 encoder->enable(encoder);
3345
3346         /*
3347          * There seems to be a race in PCH platform hw (at least on some
3348          * outputs) where an enabled pipe still completes any pageflip right
3349          * away (as if the pipe is off) instead of waiting for vblank. As soon
3350          * as the first vblank happend, everything works as expected. Hence just
3351          * wait for one vblank before returning to avoid strange things
3352          * happening.
3353          */
3354         intel_wait_for_vblank(dev, intel_crtc->pipe);
3355 }
3356
3357 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358 {
3359         struct drm_device *dev = crtc->base.dev;
3360         struct drm_i915_private *dev_priv = dev->dev_private;
3361         int pipe = crtc->pipe;
3362
3363         /* To avoid upsetting the power well on haswell only disable the pfit if
3364          * it's in use. The hw state code will make sure we get this right. */
3365         if (crtc->config.pch_pfit.size) {
3366                 I915_WRITE(PF_CTL(pipe), 0);
3367                 I915_WRITE(PF_WIN_POS(pipe), 0);
3368                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369         }
3370 }
3371
3372 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373 {
3374         struct drm_device *dev = crtc->dev;
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377         struct intel_encoder *encoder;
3378         int pipe = intel_crtc->pipe;
3379         int plane = intel_crtc->plane;
3380         u32 reg, temp;
3381
3382
3383         if (!intel_crtc->active)
3384                 return;
3385
3386         for_each_encoder_on_crtc(dev, crtc, encoder)
3387                 encoder->disable(encoder);
3388
3389         intel_crtc_wait_for_pending_flips(crtc);
3390         drm_vblank_off(dev, pipe);
3391         intel_crtc_update_cursor(crtc, false);
3392
3393         intel_disable_plane(dev_priv, plane, pipe);
3394
3395         if (dev_priv->cfb_plane == plane)
3396                 intel_disable_fbc(dev);
3397
3398         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3399         intel_disable_pipe(dev_priv, pipe);
3400
3401         ironlake_pfit_disable(intel_crtc);
3402
3403         for_each_encoder_on_crtc(dev, crtc, encoder)
3404                 if (encoder->post_disable)
3405                         encoder->post_disable(encoder);
3406
3407         ironlake_fdi_disable(crtc);
3408
3409         ironlake_disable_pch_transcoder(dev_priv, pipe);
3410         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3411
3412         if (HAS_PCH_CPT(dev)) {
3413                 /* disable TRANS_DP_CTL */
3414                 reg = TRANS_DP_CTL(pipe);
3415                 temp = I915_READ(reg);
3416                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3417                 temp |= TRANS_DP_PORT_SEL_NONE;
3418                 I915_WRITE(reg, temp);
3419
3420                 /* disable DPLL_SEL */
3421                 temp = I915_READ(PCH_DPLL_SEL);
3422                 switch (pipe) {
3423                 case 0:
3424                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3425                         break;
3426                 case 1:
3427                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3428                         break;
3429                 case 2:
3430                         /* C shares PLL A or B */
3431                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3432                         break;
3433                 default:
3434                         BUG(); /* wtf */
3435                 }
3436                 I915_WRITE(PCH_DPLL_SEL, temp);
3437         }
3438
3439         /* disable PCH DPLL */
3440         intel_disable_pch_pll(intel_crtc);
3441
3442         ironlake_fdi_pll_disable(intel_crtc);
3443
3444         intel_crtc->active = false;
3445         intel_update_watermarks(dev);
3446
3447         mutex_lock(&dev->struct_mutex);
3448         intel_update_fbc(dev);
3449         mutex_unlock(&dev->struct_mutex);
3450 }
3451
3452 static void haswell_crtc_disable(struct drm_crtc *crtc)
3453 {
3454         struct drm_device *dev = crtc->dev;
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457         struct intel_encoder *encoder;
3458         int pipe = intel_crtc->pipe;
3459         int plane = intel_crtc->plane;
3460         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3461
3462         if (!intel_crtc->active)
3463                 return;
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 encoder->disable(encoder);
3467
3468         intel_crtc_wait_for_pending_flips(crtc);
3469         drm_vblank_off(dev, pipe);
3470         intel_crtc_update_cursor(crtc, false);
3471
3472         /* FBC must be disabled before disabling the plane on HSW. */
3473         if (dev_priv->cfb_plane == plane)
3474                 intel_disable_fbc(dev);
3475
3476         hsw_disable_ips(intel_crtc);
3477
3478         intel_disable_plane(dev_priv, plane, pipe);
3479
3480         if (intel_crtc->config.has_pch_encoder)
3481                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3482         intel_disable_pipe(dev_priv, pipe);
3483
3484         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3485
3486         ironlake_pfit_disable(intel_crtc);
3487
3488         intel_ddi_disable_pipe_clock(intel_crtc);
3489
3490         for_each_encoder_on_crtc(dev, crtc, encoder)
3491                 if (encoder->post_disable)
3492                         encoder->post_disable(encoder);
3493
3494         if (intel_crtc->config.has_pch_encoder) {
3495                 lpt_disable_pch_transcoder(dev_priv);
3496                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3497                 intel_ddi_fdi_disable(crtc);
3498         }
3499
3500         intel_crtc->active = false;
3501         intel_update_watermarks(dev);
3502
3503         mutex_lock(&dev->struct_mutex);
3504         intel_update_fbc(dev);
3505         mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void ironlake_crtc_off(struct drm_crtc *crtc)
3509 {
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         intel_put_pch_pll(intel_crtc);
3512 }
3513
3514 static void haswell_crtc_off(struct drm_crtc *crtc)
3515 {
3516         intel_ddi_put_crtc_pll(crtc);
3517 }
3518
3519 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520 {
3521         if (!enable && intel_crtc->overlay) {
3522                 struct drm_device *dev = intel_crtc->base.dev;
3523                 struct drm_i915_private *dev_priv = dev->dev_private;
3524
3525                 mutex_lock(&dev->struct_mutex);
3526                 dev_priv->mm.interruptible = false;
3527                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528                 dev_priv->mm.interruptible = true;
3529                 mutex_unlock(&dev->struct_mutex);
3530         }
3531
3532         /* Let userspace switch the overlay on again. In most cases userspace
3533          * has to recompute where to put it anyway.
3534          */
3535 }
3536
3537 /**
3538  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3539  * cursor plane briefly if not already running after enabling the display
3540  * plane.
3541  * This workaround avoids occasional blank screens when self refresh is
3542  * enabled.
3543  */
3544 static void
3545 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3546 {
3547         u32 cntl = I915_READ(CURCNTR(pipe));
3548
3549         if ((cntl & CURSOR_MODE) == 0) {
3550                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3551
3552                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3553                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3554                 intel_wait_for_vblank(dev_priv->dev, pipe);
3555                 I915_WRITE(CURCNTR(pipe), cntl);
3556                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3557                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3558         }
3559 }
3560
3561 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3562 {
3563         struct drm_device *dev = crtc->base.dev;
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565         struct intel_crtc_config *pipe_config = &crtc->config;
3566
3567         if (!crtc->config.gmch_pfit.control)
3568                 return;
3569
3570         /*
3571          * The panel fitter should only be adjusted whilst the pipe is disabled,
3572          * according to register description and PRM.
3573          */
3574         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3575         assert_pipe_disabled(dev_priv, crtc->pipe);
3576
3577         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3578         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3579
3580         /* Border color in case we don't scale up to the full screen. Black by
3581          * default, change to something else for debugging. */
3582         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3583 }
3584
3585 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3586 {
3587         struct drm_device *dev = crtc->dev;
3588         struct drm_i915_private *dev_priv = dev->dev_private;
3589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590         struct intel_encoder *encoder;
3591         int pipe = intel_crtc->pipe;
3592         int plane = intel_crtc->plane;
3593
3594         WARN_ON(!crtc->enabled);
3595
3596         if (intel_crtc->active)
3597                 return;
3598
3599         intel_crtc->active = true;
3600         intel_update_watermarks(dev);
3601
3602         mutex_lock(&dev_priv->dpio_lock);
3603
3604         for_each_encoder_on_crtc(dev, crtc, encoder)
3605                 if (encoder->pre_pll_enable)
3606                         encoder->pre_pll_enable(encoder);
3607
3608         intel_enable_pll(dev_priv, pipe);
3609
3610         for_each_encoder_on_crtc(dev, crtc, encoder)
3611                 if (encoder->pre_enable)
3612                         encoder->pre_enable(encoder);
3613
3614         /* VLV wants encoder enabling _before_ the pipe is up. */
3615         for_each_encoder_on_crtc(dev, crtc, encoder)
3616                 encoder->enable(encoder);
3617
3618         /* Enable panel fitting for eDP */
3619         i9xx_pfit_enable(intel_crtc);
3620
3621         intel_enable_pipe(dev_priv, pipe, false);
3622         intel_enable_plane(dev_priv, plane, pipe);
3623
3624         intel_crtc_load_lut(crtc);
3625         intel_update_fbc(dev);
3626
3627         /* Give the overlay scaler a chance to enable if it's on this pipe */
3628         intel_crtc_dpms_overlay(intel_crtc, true);
3629         intel_crtc_update_cursor(crtc, true);
3630
3631         mutex_unlock(&dev_priv->dpio_lock);
3632 }
3633
3634 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3635 {
3636         struct drm_device *dev = crtc->dev;
3637         struct drm_i915_private *dev_priv = dev->dev_private;
3638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639         struct intel_encoder *encoder;
3640         int pipe = intel_crtc->pipe;
3641         int plane = intel_crtc->plane;
3642
3643         WARN_ON(!crtc->enabled);
3644
3645         if (intel_crtc->active)
3646                 return;
3647
3648         intel_crtc->active = true;
3649         intel_update_watermarks(dev);
3650
3651         intel_enable_pll(dev_priv, pipe);
3652
3653         for_each_encoder_on_crtc(dev, crtc, encoder)
3654                 if (encoder->pre_enable)
3655                         encoder->pre_enable(encoder);
3656
3657         /* Enable panel fitting for LVDS */
3658         i9xx_pfit_enable(intel_crtc);
3659
3660         intel_enable_pipe(dev_priv, pipe, false);
3661         intel_enable_plane(dev_priv, plane, pipe);
3662         if (IS_G4X(dev))
3663                 g4x_fixup_plane(dev_priv, pipe);
3664
3665         intel_crtc_load_lut(crtc);
3666         intel_update_fbc(dev);
3667
3668         /* Give the overlay scaler a chance to enable if it's on this pipe */
3669         intel_crtc_dpms_overlay(intel_crtc, true);
3670         intel_crtc_update_cursor(crtc, true);
3671
3672         for_each_encoder_on_crtc(dev, crtc, encoder)
3673                 encoder->enable(encoder);
3674 }
3675
3676 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677 {
3678         struct drm_device *dev = crtc->base.dev;
3679         struct drm_i915_private *dev_priv = dev->dev_private;
3680
3681         if (!crtc->config.gmch_pfit.control)
3682                 return;
3683
3684         assert_pipe_disabled(dev_priv, crtc->pipe);
3685
3686         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687                          I915_READ(PFIT_CONTROL));
3688         I915_WRITE(PFIT_CONTROL, 0);
3689 }
3690
3691 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692 {
3693         struct drm_device *dev = crtc->dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696         struct intel_encoder *encoder;
3697         int pipe = intel_crtc->pipe;
3698         int plane = intel_crtc->plane;
3699
3700         if (!intel_crtc->active)
3701                 return;
3702
3703         for_each_encoder_on_crtc(dev, crtc, encoder)
3704                 encoder->disable(encoder);
3705
3706         /* Give the overlay scaler a chance to disable if it's on this pipe */
3707         intel_crtc_wait_for_pending_flips(crtc);
3708         drm_vblank_off(dev, pipe);
3709         intel_crtc_dpms_overlay(intel_crtc, false);
3710         intel_crtc_update_cursor(crtc, false);
3711
3712         if (dev_priv->cfb_plane == plane)
3713                 intel_disable_fbc(dev);
3714
3715         intel_disable_plane(dev_priv, plane, pipe);
3716         intel_disable_pipe(dev_priv, pipe);
3717
3718         i9xx_pfit_disable(intel_crtc);
3719
3720         for_each_encoder_on_crtc(dev, crtc, encoder)
3721                 if (encoder->post_disable)
3722                         encoder->post_disable(encoder);
3723
3724         intel_disable_pll(dev_priv, pipe);
3725
3726         intel_crtc->active = false;
3727         intel_update_fbc(dev);
3728         intel_update_watermarks(dev);
3729 }
3730
3731 static void i9xx_crtc_off(struct drm_crtc *crtc)
3732 {
3733 }
3734
3735 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736                                     bool enabled)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_master_private *master_priv;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742
3743         if (!dev->primary->master)
3744                 return;
3745
3746         master_priv = dev->primary->master->driver_priv;
3747         if (!master_priv->sarea_priv)
3748                 return;
3749
3750         switch (pipe) {
3751         case 0:
3752                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754                 break;
3755         case 1:
3756                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758                 break;
3759         default:
3760                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3761                 break;
3762         }
3763 }
3764
3765 /**
3766  * Sets the power management mode of the pipe and plane.
3767  */
3768 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769 {
3770         struct drm_device *dev = crtc->dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         struct intel_encoder *intel_encoder;
3773         bool enable = false;
3774
3775         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776                 enable |= intel_encoder->connectors_active;
3777
3778         if (enable)
3779                 dev_priv->display.crtc_enable(crtc);
3780         else
3781                 dev_priv->display.crtc_disable(crtc);
3782
3783         intel_crtc_update_sarea(crtc, enable);
3784 }
3785
3786 static void intel_crtc_disable(struct drm_crtc *crtc)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_connector *connector;
3790         struct drm_i915_private *dev_priv = dev->dev_private;
3791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792
3793         /* crtc should still be enabled when we disable it. */
3794         WARN_ON(!crtc->enabled);
3795
3796         dev_priv->display.crtc_disable(crtc);
3797         intel_crtc->eld_vld = false;
3798         intel_crtc_update_sarea(crtc, false);
3799         dev_priv->display.off(crtc);
3800
3801         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3803
3804         if (crtc->fb) {
3805                 mutex_lock(&dev->struct_mutex);
3806                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3807                 mutex_unlock(&dev->struct_mutex);
3808                 crtc->fb = NULL;
3809         }
3810
3811         /* Update computed state. */
3812         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813                 if (!connector->encoder || !connector->encoder->crtc)
3814                         continue;
3815
3816                 if (connector->encoder->crtc != crtc)
3817                         continue;
3818
3819                 connector->dpms = DRM_MODE_DPMS_OFF;
3820                 to_intel_encoder(connector->encoder)->connectors_active = false;
3821         }
3822 }
3823
3824 void intel_modeset_disable(struct drm_device *dev)
3825 {
3826         struct drm_crtc *crtc;
3827
3828         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829                 if (crtc->enabled)
3830                         intel_crtc_disable(crtc);
3831         }
3832 }
3833
3834 void intel_encoder_destroy(struct drm_encoder *encoder)
3835 {
3836         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3837
3838         drm_encoder_cleanup(encoder);
3839         kfree(intel_encoder);
3840 }
3841
3842 /* Simple dpms helper for encodres with just one connector, no cloning and only
3843  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844  * state of the entire output pipe. */
3845 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3846 {
3847         if (mode == DRM_MODE_DPMS_ON) {
3848                 encoder->connectors_active = true;
3849
3850                 intel_crtc_update_dpms(encoder->base.crtc);
3851         } else {
3852                 encoder->connectors_active = false;
3853
3854                 intel_crtc_update_dpms(encoder->base.crtc);
3855         }
3856 }
3857
3858 /* Cross check the actual hw state with our own modeset state tracking (and it's
3859  * internal consistency). */
3860 static void intel_connector_check_state(struct intel_connector *connector)
3861 {
3862         if (connector->get_hw_state(connector)) {
3863                 struct intel_encoder *encoder = connector->encoder;
3864                 struct drm_crtc *crtc;
3865                 bool encoder_enabled;
3866                 enum pipe pipe;
3867
3868                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869                               connector->base.base.id,
3870                               drm_get_connector_name(&connector->base));
3871
3872                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873                      "wrong connector dpms state\n");
3874                 WARN(connector->base.encoder != &encoder->base,
3875                      "active connector not linked to encoder\n");
3876                 WARN(!encoder->connectors_active,
3877                      "encoder->connectors_active not set\n");
3878
3879                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880                 WARN(!encoder_enabled, "encoder not enabled\n");
3881                 if (WARN_ON(!encoder->base.crtc))
3882                         return;
3883
3884                 crtc = encoder->base.crtc;
3885
3886                 WARN(!crtc->enabled, "crtc not enabled\n");
3887                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889                      "encoder active on the wrong pipe\n");
3890         }
3891 }
3892
3893 /* Even simpler default implementation, if there's really no special case to
3894  * consider. */
3895 void intel_connector_dpms(struct drm_connector *connector, int mode)
3896 {
3897         struct intel_encoder *encoder = intel_attached_encoder(connector);
3898
3899         /* All the simple cases only support two dpms states. */
3900         if (mode != DRM_MODE_DPMS_ON)
3901                 mode = DRM_MODE_DPMS_OFF;
3902
3903         if (mode == connector->dpms)
3904                 return;
3905
3906         connector->dpms = mode;
3907
3908         /* Only need to change hw state when actually enabled */
3909         if (encoder->base.crtc)
3910                 intel_encoder_dpms(encoder, mode);
3911         else
3912                 WARN_ON(encoder->connectors_active != false);
3913
3914         intel_modeset_check_state(connector->dev);
3915 }
3916
3917 /* Simple connector->get_hw_state implementation for encoders that support only
3918  * one connector and no cloning and hence the encoder state determines the state
3919  * of the connector. */
3920 bool intel_connector_get_hw_state(struct intel_connector *connector)
3921 {
3922         enum pipe pipe = 0;
3923         struct intel_encoder *encoder = connector->encoder;
3924
3925         return encoder->get_hw_state(encoder, &pipe);
3926 }
3927
3928 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929                                      struct intel_crtc_config *pipe_config)
3930 {
3931         struct drm_i915_private *dev_priv = dev->dev_private;
3932         struct intel_crtc *pipe_B_crtc =
3933                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936                       pipe_name(pipe), pipe_config->fdi_lanes);
3937         if (pipe_config->fdi_lanes > 4) {
3938                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939                               pipe_name(pipe), pipe_config->fdi_lanes);
3940                 return false;
3941         }
3942
3943         if (IS_HASWELL(dev)) {
3944                 if (pipe_config->fdi_lanes > 2) {
3945                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946                                       pipe_config->fdi_lanes);
3947                         return false;
3948                 } else {
3949                         return true;
3950                 }
3951         }
3952
3953         if (INTEL_INFO(dev)->num_pipes == 2)
3954                 return true;
3955
3956         /* Ivybridge 3 pipe is really complicated */
3957         switch (pipe) {
3958         case PIPE_A:
3959                 return true;
3960         case PIPE_B:
3961                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962                     pipe_config->fdi_lanes > 2) {
3963                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964                                       pipe_name(pipe), pipe_config->fdi_lanes);
3965                         return false;
3966                 }
3967                 return true;
3968         case PIPE_C:
3969                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3970                     pipe_B_crtc->config.fdi_lanes <= 2) {
3971                         if (pipe_config->fdi_lanes > 2) {
3972                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973                                               pipe_name(pipe), pipe_config->fdi_lanes);
3974                                 return false;
3975                         }
3976                 } else {
3977                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978                         return false;
3979                 }
3980                 return true;
3981         default:
3982                 BUG();
3983         }
3984 }
3985
3986 #define RETRY 1
3987 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988                                        struct intel_crtc_config *pipe_config)
3989 {
3990         struct drm_device *dev = intel_crtc->base.dev;
3991         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3992         int lane, link_bw, fdi_dotclock;
3993         bool setup_ok, needs_recompute = false;
3994
3995 retry:
3996         /* FDI is a binary signal running at ~2.7GHz, encoding
3997          * each output octet as 10 bits. The actual frequency
3998          * is stored as a divider into a 100MHz clock, and the
3999          * mode pixel clock is stored in units of 1KHz.
4000          * Hence the bw of each lane in terms of the mode signal
4001          * is:
4002          */
4003         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
4005         fdi_dotclock = adjusted_mode->clock;
4006         if (pipe_config->pixel_multiplier > 1)
4007                 fdi_dotclock /= pipe_config->pixel_multiplier;
4008
4009         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4010                                            pipe_config->pipe_bpp);
4011
4012         pipe_config->fdi_lanes = lane;
4013
4014         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4015                                link_bw, &pipe_config->fdi_m_n);
4016
4017         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4018                                             intel_crtc->pipe, pipe_config);
4019         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4020                 pipe_config->pipe_bpp -= 2*3;
4021                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4022                               pipe_config->pipe_bpp);
4023                 needs_recompute = true;
4024                 pipe_config->bw_constrained = true;
4025
4026                 goto retry;
4027         }
4028
4029         if (needs_recompute)
4030                 return RETRY;
4031
4032         return setup_ok ? 0 : -EINVAL;
4033 }
4034
4035 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4036                                    struct intel_crtc_config *pipe_config)
4037 {
4038         pipe_config->ips_enabled = i915_enable_ips &&
4039                                    hsw_crtc_supports_ips(crtc) &&
4040                                    pipe_config->pipe_bpp == 24;
4041 }
4042
4043 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4044                                      struct intel_crtc_config *pipe_config)
4045 {
4046         struct drm_device *dev = crtc->dev;
4047         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4049
4050         if (HAS_PCH_SPLIT(dev)) {
4051                 /* FDI link clock is fixed at 2.7G */
4052                 if (pipe_config->requested_mode.clock * 3
4053                     > IRONLAKE_FDI_FREQ * 4)
4054                         return -EINVAL;
4055         }
4056
4057         /* All interlaced capable intel hw wants timings in frames. Note though
4058          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059          * timings, so we need to be careful not to clobber these.*/
4060         if (!pipe_config->timings_set)
4061                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4062
4063         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4064          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4065          */
4066         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4068                 return -EINVAL;
4069
4070         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4071                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4072         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4073                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074                  * for lvds. */
4075                 pipe_config->pipe_bpp = 8*3;
4076         }
4077
4078         if (IS_HASWELL(dev))
4079                 hsw_compute_ips_config(intel_crtc, pipe_config);
4080
4081         if (pipe_config->has_pch_encoder)
4082                 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4083
4084         return 0;
4085 }
4086
4087 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4088 {
4089         return 400000; /* FIXME */
4090 }
4091
4092 static int i945_get_display_clock_speed(struct drm_device *dev)
4093 {
4094         return 400000;
4095 }
4096
4097 static int i915_get_display_clock_speed(struct drm_device *dev)
4098 {
4099         return 333000;
4100 }
4101
4102 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4103 {
4104         return 200000;
4105 }
4106
4107 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4108 {
4109         u16 gcfgc = 0;
4110
4111         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4112
4113         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4114                 return 133000;
4115         else {
4116                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4117                 case GC_DISPLAY_CLOCK_333_MHZ:
4118                         return 333000;
4119                 default:
4120                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4121                         return 190000;
4122                 }
4123         }
4124 }
4125
4126 static int i865_get_display_clock_speed(struct drm_device *dev)
4127 {
4128         return 266000;
4129 }
4130
4131 static int i855_get_display_clock_speed(struct drm_device *dev)
4132 {
4133         u16 hpllcc = 0;
4134         /* Assume that the hardware is in the high speed state.  This
4135          * should be the default.
4136          */
4137         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4138         case GC_CLOCK_133_200:
4139         case GC_CLOCK_100_200:
4140                 return 200000;
4141         case GC_CLOCK_166_250:
4142                 return 250000;
4143         case GC_CLOCK_100_133:
4144                 return 133000;
4145         }
4146
4147         /* Shouldn't happen */
4148         return 0;
4149 }
4150
4151 static int i830_get_display_clock_speed(struct drm_device *dev)
4152 {
4153         return 133000;
4154 }
4155
4156 static void
4157 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4158 {
4159         while (*num > DATA_LINK_M_N_MASK ||
4160                *den > DATA_LINK_M_N_MASK) {
4161                 *num >>= 1;
4162                 *den >>= 1;
4163         }
4164 }
4165
4166 static void compute_m_n(unsigned int m, unsigned int n,
4167                         uint32_t *ret_m, uint32_t *ret_n)
4168 {
4169         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4170         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4171         intel_reduce_m_n_ratio(ret_m, ret_n);
4172 }
4173
4174 void
4175 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4176                        int pixel_clock, int link_clock,
4177                        struct intel_link_m_n *m_n)
4178 {
4179         m_n->tu = 64;
4180
4181         compute_m_n(bits_per_pixel * pixel_clock,
4182                     link_clock * nlanes * 8,
4183                     &m_n->gmch_m, &m_n->gmch_n);
4184
4185         compute_m_n(pixel_clock, link_clock,
4186                     &m_n->link_m, &m_n->link_n);
4187 }
4188
4189 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4190 {
4191         if (i915_panel_use_ssc >= 0)
4192                 return i915_panel_use_ssc != 0;
4193         return dev_priv->vbt.lvds_use_ssc
4194                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4195 }
4196
4197 static int vlv_get_refclk(struct drm_crtc *crtc)
4198 {
4199         struct drm_device *dev = crtc->dev;
4200         struct drm_i915_private *dev_priv = dev->dev_private;
4201         int refclk = 27000; /* for DP & HDMI */
4202
4203         return 100000; /* only one validated so far */
4204
4205         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4206                 refclk = 96000;
4207         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4208                 if (intel_panel_use_ssc(dev_priv))
4209                         refclk = 100000;
4210                 else
4211                         refclk = 96000;
4212         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4213                 refclk = 100000;
4214         }
4215
4216         return refclk;
4217 }
4218
4219 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4220 {
4221         struct drm_device *dev = crtc->dev;
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         int refclk;
4224
4225         if (IS_VALLEYVIEW(dev)) {
4226                 refclk = vlv_get_refclk(crtc);
4227         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4228             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4229                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4230                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4231                               refclk / 1000);
4232         } else if (!IS_GEN2(dev)) {
4233                 refclk = 96000;
4234         } else {
4235                 refclk = 48000;
4236         }
4237
4238         return refclk;
4239 }
4240
4241 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4242 {
4243         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4244 }
4245
4246 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4247 {
4248         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4249 }
4250
4251 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4252                                      intel_clock_t *reduced_clock)
4253 {
4254         struct drm_device *dev = crtc->base.dev;
4255         struct drm_i915_private *dev_priv = dev->dev_private;
4256         int pipe = crtc->pipe;
4257         u32 fp, fp2 = 0;
4258
4259         if (IS_PINEVIEW(dev)) {
4260                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4261                 if (reduced_clock)
4262                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4263         } else {
4264                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4265                 if (reduced_clock)
4266                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4267         }
4268
4269         I915_WRITE(FP0(pipe), fp);
4270
4271         crtc->lowfreq_avail = false;
4272         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4273             reduced_clock && i915_powersave) {
4274                 I915_WRITE(FP1(pipe), fp2);
4275                 crtc->lowfreq_avail = true;
4276         } else {
4277                 I915_WRITE(FP1(pipe), fp);
4278         }
4279 }
4280
4281 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4282 {
4283         u32 reg_val;
4284
4285         /*
4286          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4287          * and set it to a reasonable value instead.
4288          */
4289         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4290         reg_val &= 0xffffff00;
4291         reg_val |= 0x00000030;
4292         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4293
4294         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4295         reg_val &= 0x8cffffff;
4296         reg_val = 0x8c000000;
4297         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4298
4299         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4300         reg_val &= 0xffffff00;
4301         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4302
4303         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4304         reg_val &= 0x00ffffff;
4305         reg_val |= 0xb0000000;
4306         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4307 }
4308
4309 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4310                                          struct intel_link_m_n *m_n)
4311 {
4312         struct drm_device *dev = crtc->base.dev;
4313         struct drm_i915_private *dev_priv = dev->dev_private;
4314         int pipe = crtc->pipe;
4315
4316         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4317         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4318         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4319         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4320 }
4321
4322 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4323                                          struct intel_link_m_n *m_n)
4324 {
4325         struct drm_device *dev = crtc->base.dev;
4326         struct drm_i915_private *dev_priv = dev->dev_private;
4327         int pipe = crtc->pipe;
4328         enum transcoder transcoder = crtc->config.cpu_transcoder;
4329
4330         if (INTEL_INFO(dev)->gen >= 5) {
4331                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4332                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4333                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4334                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4335         } else {
4336                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4338                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4339                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4340         }
4341 }
4342
4343 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4344 {
4345         if (crtc->config.has_pch_encoder)
4346                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4347         else
4348                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4349 }
4350
4351 static void vlv_update_pll(struct intel_crtc *crtc)
4352 {
4353         struct drm_device *dev = crtc->base.dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct intel_encoder *encoder;
4356         int pipe = crtc->pipe;
4357         u32 dpll, mdiv;
4358         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4359         bool is_hdmi;
4360         u32 coreclk, reg_val, dpll_md;
4361
4362         mutex_lock(&dev_priv->dpio_lock);
4363
4364         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4365
4366         bestn = crtc->config.dpll.n;
4367         bestm1 = crtc->config.dpll.m1;
4368         bestm2 = crtc->config.dpll.m2;
4369         bestp1 = crtc->config.dpll.p1;
4370         bestp2 = crtc->config.dpll.p2;
4371
4372         /* See eDP HDMI DPIO driver vbios notes doc */
4373
4374         /* PLL B needs special handling */
4375         if (pipe)
4376                 vlv_pllb_recal_opamp(dev_priv);
4377
4378         /* Set up Tx target for periodic Rcomp update */
4379         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4380
4381         /* Disable target IRef on PLL */
4382         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4383         reg_val &= 0x00ffffff;
4384         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4385
4386         /* Disable fast lock */
4387         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4388
4389         /* Set idtafcrecal before PLL is enabled */
4390         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4391         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4392         mdiv |= ((bestn << DPIO_N_SHIFT));
4393         mdiv |= (1 << DPIO_K_SHIFT);
4394
4395         /*
4396          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4397          * but we don't support that).
4398          * Note: don't use the DAC post divider as it seems unstable.
4399          */
4400         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4401         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4402
4403         mdiv |= DPIO_ENABLE_CALIBRATION;
4404         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4405
4406         /* Set HBR and RBR LPF coefficients */
4407         if (crtc->config.port_clock == 162000 ||
4408             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4409                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4410                                  0x005f0021);
4411         else
4412                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4413                                  0x00d0000f);
4414
4415         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417                 /* Use SSC source */
4418                 if (!pipe)
4419                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4420                                          0x0df40000);
4421                 else
4422                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4423                                          0x0df70000);
4424         } else { /* HDMI or VGA */
4425                 /* Use bend source */
4426                 if (!pipe)
4427                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4428                                          0x0df70000);
4429                 else
4430                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4431                                          0x0df40000);
4432         }
4433
4434         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4435         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438                 coreclk |= 0x01000000;
4439         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4440
4441         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4442
4443         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444                 if (encoder->pre_pll_enable)
4445                         encoder->pre_pll_enable(encoder);
4446
4447         /* Enable DPIO clock input */
4448         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4450         if (pipe)
4451                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4452
4453         dpll |= DPLL_VCO_ENABLE;
4454         I915_WRITE(DPLL(pipe), dpll);
4455         POSTING_READ(DPLL(pipe));
4456         udelay(150);
4457
4458         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4459                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4460
4461         dpll_md = 0;
4462         if (crtc->config.pixel_multiplier > 1) {
4463                 dpll_md = (crtc->config.pixel_multiplier - 1)
4464                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4465         }
4466         I915_WRITE(DPLL_MD(pipe), dpll_md);
4467         POSTING_READ(DPLL_MD(pipe));
4468
4469         if (crtc->config.has_dp_encoder)
4470                 intel_dp_set_m_n(crtc);
4471
4472         mutex_unlock(&dev_priv->dpio_lock);
4473 }
4474
4475 static void i9xx_update_pll(struct intel_crtc *crtc,
4476                             intel_clock_t *reduced_clock,
4477                             int num_connectors)
4478 {
4479         struct drm_device *dev = crtc->base.dev;
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481         struct intel_encoder *encoder;
4482         int pipe = crtc->pipe;
4483         u32 dpll;
4484         bool is_sdvo;
4485         struct dpll *clock = &crtc->config.dpll;
4486
4487         i9xx_update_pll_dividers(crtc, reduced_clock);
4488
4489         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4490                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4491
4492         dpll = DPLL_VGA_MODE_DIS;
4493
4494         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4495                 dpll |= DPLLB_MODE_LVDS;
4496         else
4497                 dpll |= DPLLB_MODE_DAC_SERIAL;
4498
4499         if ((crtc->config.pixel_multiplier > 1) &&
4500             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4501                 dpll |= (crtc->config.pixel_multiplier - 1)
4502                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4503         }
4504
4505         if (is_sdvo)
4506                 dpll |= DPLL_DVO_HIGH_SPEED;
4507
4508         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4509                 dpll |= DPLL_DVO_HIGH_SPEED;
4510
4511         /* compute bitmask from p1 value */
4512         if (IS_PINEVIEW(dev))
4513                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4514         else {
4515                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4516                 if (IS_G4X(dev) && reduced_clock)
4517                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4518         }
4519         switch (clock->p2) {
4520         case 5:
4521                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4522                 break;
4523         case 7:
4524                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4525                 break;
4526         case 10:
4527                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4528                 break;
4529         case 14:
4530                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4531                 break;
4532         }
4533         if (INTEL_INFO(dev)->gen >= 4)
4534                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4535
4536         if (crtc->config.sdvo_tv_clock)
4537                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4538         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4539                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4540                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4541         else
4542                 dpll |= PLL_REF_INPUT_DREFCLK;
4543
4544         dpll |= DPLL_VCO_ENABLE;
4545         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4546         POSTING_READ(DPLL(pipe));
4547         udelay(150);
4548
4549         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4550                 if (encoder->pre_pll_enable)
4551                         encoder->pre_pll_enable(encoder);
4552
4553         if (crtc->config.has_dp_encoder)
4554                 intel_dp_set_m_n(crtc);
4555
4556         I915_WRITE(DPLL(pipe), dpll);
4557
4558         /* Wait for the clocks to stabilize. */
4559         POSTING_READ(DPLL(pipe));
4560         udelay(150);
4561
4562         if (INTEL_INFO(dev)->gen >= 4) {
4563                 u32 dpll_md = 0;
4564                 if (crtc->config.pixel_multiplier > 1) {
4565                         dpll_md = (crtc->config.pixel_multiplier - 1)
4566                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4567                 }
4568                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4569         } else {
4570                 /* The pixel multiplier can only be updated once the
4571                  * DPLL is enabled and the clocks are stable.
4572                  *
4573                  * So write it again.
4574                  */
4575                 I915_WRITE(DPLL(pipe), dpll);
4576         }
4577 }
4578
4579 static void i8xx_update_pll(struct intel_crtc *crtc,
4580                             intel_clock_t *reduced_clock,
4581                             int num_connectors)
4582 {
4583         struct drm_device *dev = crtc->base.dev;
4584         struct drm_i915_private *dev_priv = dev->dev_private;
4585         struct intel_encoder *encoder;
4586         int pipe = crtc->pipe;
4587         u32 dpll;
4588         struct dpll *clock = &crtc->config.dpll;
4589
4590         i9xx_update_pll_dividers(crtc, reduced_clock);
4591
4592         dpll = DPLL_VGA_MODE_DIS;
4593
4594         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4595                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596         } else {
4597                 if (clock->p1 == 2)
4598                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4599                 else
4600                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4601                 if (clock->p2 == 4)
4602                         dpll |= PLL_P2_DIVIDE_BY_4;
4603         }
4604
4605         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4606                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4607                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4608         else
4609                 dpll |= PLL_REF_INPUT_DREFCLK;
4610
4611         dpll |= DPLL_VCO_ENABLE;
4612         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4613         POSTING_READ(DPLL(pipe));
4614         udelay(150);
4615
4616         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4617                 if (encoder->pre_pll_enable)
4618                         encoder->pre_pll_enable(encoder);
4619
4620         I915_WRITE(DPLL(pipe), dpll);
4621
4622         /* Wait for the clocks to stabilize. */
4623         POSTING_READ(DPLL(pipe));
4624         udelay(150);
4625
4626         /* The pixel multiplier can only be updated once the
4627          * DPLL is enabled and the clocks are stable.
4628          *
4629          * So write it again.
4630          */
4631         I915_WRITE(DPLL(pipe), dpll);
4632 }
4633
4634 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4635 {
4636         struct drm_device *dev = intel_crtc->base.dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638         enum pipe pipe = intel_crtc->pipe;
4639         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4640         struct drm_display_mode *adjusted_mode =
4641                 &intel_crtc->config.adjusted_mode;
4642         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4643         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4644
4645         /* We need to be careful not to changed the adjusted mode, for otherwise
4646          * the hw state checker will get angry at the mismatch. */
4647         crtc_vtotal = adjusted_mode->crtc_vtotal;
4648         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4649
4650         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4651                 /* the chip adds 2 halflines automatically */
4652                 crtc_vtotal -= 1;
4653                 crtc_vblank_end -= 1;
4654                 vsyncshift = adjusted_mode->crtc_hsync_start
4655                              - adjusted_mode->crtc_htotal / 2;
4656         } else {
4657                 vsyncshift = 0;
4658         }
4659
4660         if (INTEL_INFO(dev)->gen > 3)
4661                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4662
4663         I915_WRITE(HTOTAL(cpu_transcoder),
4664                    (adjusted_mode->crtc_hdisplay - 1) |
4665                    ((adjusted_mode->crtc_htotal - 1) << 16));
4666         I915_WRITE(HBLANK(cpu_transcoder),
4667                    (adjusted_mode->crtc_hblank_start - 1) |
4668                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4669         I915_WRITE(HSYNC(cpu_transcoder),
4670                    (adjusted_mode->crtc_hsync_start - 1) |
4671                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4672
4673         I915_WRITE(VTOTAL(cpu_transcoder),
4674                    (adjusted_mode->crtc_vdisplay - 1) |
4675                    ((crtc_vtotal - 1) << 16));
4676         I915_WRITE(VBLANK(cpu_transcoder),
4677                    (adjusted_mode->crtc_vblank_start - 1) |
4678                    ((crtc_vblank_end - 1) << 16));
4679         I915_WRITE(VSYNC(cpu_transcoder),
4680                    (adjusted_mode->crtc_vsync_start - 1) |
4681                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4682
4683         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4684          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4685          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4686          * bits. */
4687         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4688             (pipe == PIPE_B || pipe == PIPE_C))
4689                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4690
4691         /* pipesrc controls the size that is scaled from, which should
4692          * always be the user's requested size.
4693          */
4694         I915_WRITE(PIPESRC(pipe),
4695                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4696 }
4697
4698 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4699                                    struct intel_crtc_config *pipe_config)
4700 {
4701         struct drm_device *dev = crtc->base.dev;
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4704         uint32_t tmp;
4705
4706         tmp = I915_READ(HTOTAL(cpu_transcoder));
4707         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4708         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4709         tmp = I915_READ(HBLANK(cpu_transcoder));
4710         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4711         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4712         tmp = I915_READ(HSYNC(cpu_transcoder));
4713         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4714         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4715
4716         tmp = I915_READ(VTOTAL(cpu_transcoder));
4717         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4718         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4719         tmp = I915_READ(VBLANK(cpu_transcoder));
4720         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4721         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4722         tmp = I915_READ(VSYNC(cpu_transcoder));
4723         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4724         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4725
4726         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4727                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4728                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4729                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4730         }
4731
4732         tmp = I915_READ(PIPESRC(crtc->pipe));
4733         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4734         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4735 }
4736
4737 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4738 {
4739         struct drm_device *dev = intel_crtc->base.dev;
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         uint32_t pipeconf;
4742
4743         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4744
4745         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4746                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4747                  * core speed.
4748                  *
4749                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4750                  * pipe == 0 check?
4751                  */
4752                 if (intel_crtc->config.requested_mode.clock >
4753                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4754                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4755                 else
4756                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4757         }
4758
4759         /* only g4x and later have fancy bpc/dither controls */
4760         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4761                 pipeconf &= ~(PIPECONF_BPC_MASK |
4762                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4763
4764                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4765                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4766                         pipeconf |= PIPECONF_DITHER_EN |
4767                                     PIPECONF_DITHER_TYPE_SP;
4768
4769                 switch (intel_crtc->config.pipe_bpp) {
4770                 case 18:
4771                         pipeconf |= PIPECONF_6BPC;
4772                         break;
4773                 case 24:
4774                         pipeconf |= PIPECONF_8BPC;
4775                         break;
4776                 case 30:
4777                         pipeconf |= PIPECONF_10BPC;
4778                         break;
4779                 default:
4780                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4781                         BUG();
4782                 }
4783         }
4784
4785         if (HAS_PIPE_CXSR(dev)) {
4786                 if (intel_crtc->lowfreq_avail) {
4787                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4788                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4789                 } else {
4790                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4791                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4792                 }
4793         }
4794
4795         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4796         if (!IS_GEN2(dev) &&
4797             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4798                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4799         else
4800                 pipeconf |= PIPECONF_PROGRESSIVE;
4801
4802         if (IS_VALLEYVIEW(dev)) {
4803                 if (intel_crtc->config.limited_color_range)
4804                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4805                 else
4806                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4807         }
4808
4809         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4810         POSTING_READ(PIPECONF(intel_crtc->pipe));
4811 }
4812
4813 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4814                               int x, int y,
4815                               struct drm_framebuffer *fb)
4816 {
4817         struct drm_device *dev = crtc->dev;
4818         struct drm_i915_private *dev_priv = dev->dev_private;
4819         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4820         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4821         int pipe = intel_crtc->pipe;
4822         int plane = intel_crtc->plane;
4823         int refclk, num_connectors = 0;
4824         intel_clock_t clock, reduced_clock;
4825         u32 dspcntr;
4826         bool ok, has_reduced_clock = false;
4827         bool is_lvds = false;
4828         struct intel_encoder *encoder;
4829         const intel_limit_t *limit;
4830         int ret;
4831
4832         for_each_encoder_on_crtc(dev, crtc, encoder) {
4833                 switch (encoder->type) {
4834                 case INTEL_OUTPUT_LVDS:
4835                         is_lvds = true;
4836                         break;
4837                 }
4838
4839                 num_connectors++;
4840         }
4841
4842         refclk = i9xx_get_refclk(crtc, num_connectors);
4843
4844         /*
4845          * Returns a set of divisors for the desired target clock with the given
4846          * refclk, or FALSE.  The returned values represent the clock equation:
4847          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4848          */
4849         limit = intel_limit(crtc, refclk);
4850         ok = dev_priv->display.find_dpll(limit, crtc,
4851                                          intel_crtc->config.port_clock,
4852                                          refclk, NULL, &clock);
4853         if (!ok && !intel_crtc->config.clock_set) {
4854                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4855                 return -EINVAL;
4856         }
4857
4858         /* Ensure that the cursor is valid for the new mode before changing... */
4859         intel_crtc_update_cursor(crtc, true);
4860
4861         if (is_lvds && dev_priv->lvds_downclock_avail) {
4862                 /*
4863                  * Ensure we match the reduced clock's P to the target clock.
4864                  * If the clocks don't match, we can't switch the display clock
4865                  * by using the FP0/FP1. In such case we will disable the LVDS
4866                  * downclock feature.
4867                 */
4868                 has_reduced_clock =
4869                         dev_priv->display.find_dpll(limit, crtc,
4870                                                     dev_priv->lvds_downclock,
4871                                                     refclk, &clock,
4872                                                     &reduced_clock);
4873         }
4874         /* Compat-code for transition, will disappear. */
4875         if (!intel_crtc->config.clock_set) {
4876                 intel_crtc->config.dpll.n = clock.n;
4877                 intel_crtc->config.dpll.m1 = clock.m1;
4878                 intel_crtc->config.dpll.m2 = clock.m2;
4879                 intel_crtc->config.dpll.p1 = clock.p1;
4880                 intel_crtc->config.dpll.p2 = clock.p2;
4881         }
4882
4883         if (IS_GEN2(dev))
4884                 i8xx_update_pll(intel_crtc,
4885                                 has_reduced_clock ? &reduced_clock : NULL,
4886                                 num_connectors);
4887         else if (IS_VALLEYVIEW(dev))
4888                 vlv_update_pll(intel_crtc);
4889         else
4890                 i9xx_update_pll(intel_crtc,
4891                                 has_reduced_clock ? &reduced_clock : NULL,
4892                                 num_connectors);
4893
4894         /* Set up the display plane register */
4895         dspcntr = DISPPLANE_GAMMA_ENABLE;
4896
4897         if (!IS_VALLEYVIEW(dev)) {
4898                 if (pipe == 0)
4899                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4900                 else
4901                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4902         }
4903
4904         intel_set_pipe_timings(intel_crtc);
4905
4906         /* pipesrc and dspsize control the size that is scaled from,
4907          * which should always be the user's requested size.
4908          */
4909         I915_WRITE(DSPSIZE(plane),
4910                    ((mode->vdisplay - 1) << 16) |
4911                    (mode->hdisplay - 1));
4912         I915_WRITE(DSPPOS(plane), 0);
4913
4914         i9xx_set_pipeconf(intel_crtc);
4915
4916         I915_WRITE(DSPCNTR(plane), dspcntr);
4917         POSTING_READ(DSPCNTR(plane));
4918
4919         ret = intel_pipe_set_base(crtc, x, y, fb);
4920
4921         intel_update_watermarks(dev);
4922
4923         return ret;
4924 }
4925
4926 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4927                                  struct intel_crtc_config *pipe_config)
4928 {
4929         struct drm_device *dev = crtc->base.dev;
4930         struct drm_i915_private *dev_priv = dev->dev_private;
4931         uint32_t tmp;
4932
4933         tmp = I915_READ(PFIT_CONTROL);
4934
4935         if (INTEL_INFO(dev)->gen < 4) {
4936                 if (crtc->pipe != PIPE_B)
4937                         return;
4938
4939                 /* gen2/3 store dither state in pfit control, needs to match */
4940                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4941         } else {
4942                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4943                         return;
4944         }
4945
4946         if (!(tmp & PFIT_ENABLE))
4947                 return;
4948
4949         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4950         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4951         if (INTEL_INFO(dev)->gen < 5)
4952                 pipe_config->gmch_pfit.lvds_border_bits =
4953                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4954 }
4955
4956 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4957                                  struct intel_crtc_config *pipe_config)
4958 {
4959         struct drm_device *dev = crtc->base.dev;
4960         struct drm_i915_private *dev_priv = dev->dev_private;
4961         uint32_t tmp;
4962
4963         pipe_config->cpu_transcoder = crtc->pipe;
4964
4965         tmp = I915_READ(PIPECONF(crtc->pipe));
4966         if (!(tmp & PIPECONF_ENABLE))
4967                 return false;
4968
4969         intel_get_pipe_timings(crtc, pipe_config);
4970
4971         i9xx_get_pfit_config(crtc, pipe_config);
4972
4973         return true;
4974 }
4975
4976 static void ironlake_init_pch_refclk(struct drm_device *dev)
4977 {
4978         struct drm_i915_private *dev_priv = dev->dev_private;
4979         struct drm_mode_config *mode_config = &dev->mode_config;
4980         struct intel_encoder *encoder;
4981         u32 val, final;
4982         bool has_lvds = false;
4983         bool has_cpu_edp = false;
4984         bool has_panel = false;
4985         bool has_ck505 = false;
4986         bool can_ssc = false;
4987
4988         /* We need to take the global config into account */
4989         list_for_each_entry(encoder, &mode_config->encoder_list,
4990                             base.head) {
4991                 switch (encoder->type) {
4992                 case INTEL_OUTPUT_LVDS:
4993                         has_panel = true;
4994                         has_lvds = true;
4995                         break;
4996                 case INTEL_OUTPUT_EDP:
4997                         has_panel = true;
4998                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4999                                 has_cpu_edp = true;
5000                         break;
5001                 }
5002         }
5003
5004         if (HAS_PCH_IBX(dev)) {
5005                 has_ck505 = dev_priv->vbt.display_clock_mode;
5006                 can_ssc = has_ck505;
5007         } else {
5008                 has_ck505 = false;
5009                 can_ssc = true;
5010         }
5011
5012         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5013                       has_panel, has_lvds, has_ck505);
5014
5015         /* Ironlake: try to setup display ref clock before DPLL
5016          * enabling. This is only under driver's control after
5017          * PCH B stepping, previous chipset stepping should be
5018          * ignoring this setting.
5019          */
5020         val = I915_READ(PCH_DREF_CONTROL);
5021
5022         /* As we must carefully and slowly disable/enable each source in turn,
5023          * compute the final state we want first and check if we need to
5024          * make any changes at all.
5025          */
5026         final = val;
5027         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5028         if (has_ck505)
5029                 final |= DREF_NONSPREAD_CK505_ENABLE;
5030         else
5031                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5032
5033         final &= ~DREF_SSC_SOURCE_MASK;
5034         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5035         final &= ~DREF_SSC1_ENABLE;
5036
5037         if (has_panel) {
5038                 final |= DREF_SSC_SOURCE_ENABLE;
5039
5040                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5041                         final |= DREF_SSC1_ENABLE;
5042
5043                 if (has_cpu_edp) {
5044                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5045                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5046                         else
5047                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5048                 } else
5049                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5050         } else {
5051                 final |= DREF_SSC_SOURCE_DISABLE;
5052                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053         }
5054
5055         if (final == val)
5056                 return;
5057
5058         /* Always enable nonspread source */
5059         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5060
5061         if (has_ck505)
5062                 val |= DREF_NONSPREAD_CK505_ENABLE;
5063         else
5064                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5065
5066         if (has_panel) {
5067                 val &= ~DREF_SSC_SOURCE_MASK;
5068                 val |= DREF_SSC_SOURCE_ENABLE;
5069
5070                 /* SSC must be turned on before enabling the CPU output  */
5071                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5072                         DRM_DEBUG_KMS("Using SSC on panel\n");
5073                         val |= DREF_SSC1_ENABLE;
5074                 } else
5075                         val &= ~DREF_SSC1_ENABLE;
5076
5077                 /* Get SSC going before enabling the outputs */
5078                 I915_WRITE(PCH_DREF_CONTROL, val);
5079                 POSTING_READ(PCH_DREF_CONTROL);
5080                 udelay(200);
5081
5082                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5083
5084                 /* Enable CPU source on CPU attached eDP */
5085                 if (has_cpu_edp) {
5086                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5087                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5088                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5089                         }
5090                         else
5091                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5092                 } else
5093                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5094
5095                 I915_WRITE(PCH_DREF_CONTROL, val);
5096                 POSTING_READ(PCH_DREF_CONTROL);
5097                 udelay(200);
5098         } else {
5099                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5100
5101                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5102
5103                 /* Turn off CPU output */
5104                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5105
5106                 I915_WRITE(PCH_DREF_CONTROL, val);
5107                 POSTING_READ(PCH_DREF_CONTROL);
5108                 udelay(200);
5109
5110                 /* Turn off the SSC source */
5111                 val &= ~DREF_SSC_SOURCE_MASK;
5112                 val |= DREF_SSC_SOURCE_DISABLE;
5113
5114                 /* Turn off SSC1 */
5115                 val &= ~DREF_SSC1_ENABLE;
5116
5117                 I915_WRITE(PCH_DREF_CONTROL, val);
5118                 POSTING_READ(PCH_DREF_CONTROL);
5119                 udelay(200);
5120         }
5121
5122         BUG_ON(val != final);
5123 }
5124
5125 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5126 static void lpt_init_pch_refclk(struct drm_device *dev)
5127 {
5128         struct drm_i915_private *dev_priv = dev->dev_private;
5129         struct drm_mode_config *mode_config = &dev->mode_config;
5130         struct intel_encoder *encoder;
5131         bool has_vga = false;
5132         bool is_sdv = false;
5133         u32 tmp;
5134
5135         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5136                 switch (encoder->type) {
5137                 case INTEL_OUTPUT_ANALOG:
5138                         has_vga = true;
5139                         break;
5140                 }
5141         }
5142
5143         if (!has_vga)
5144                 return;
5145
5146         mutex_lock(&dev_priv->dpio_lock);
5147
5148         /* XXX: Rip out SDV support once Haswell ships for real. */
5149         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5150                 is_sdv = true;
5151
5152         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5153         tmp &= ~SBI_SSCCTL_DISABLE;
5154         tmp |= SBI_SSCCTL_PATHALT;
5155         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5156
5157         udelay(24);
5158
5159         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5160         tmp &= ~SBI_SSCCTL_PATHALT;
5161         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5162
5163         if (!is_sdv) {
5164                 tmp = I915_READ(SOUTH_CHICKEN2);
5165                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5166                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5167
5168                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5169                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5170                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5171
5172                 tmp = I915_READ(SOUTH_CHICKEN2);
5173                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5174                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5175
5176                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5177                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5178                                        100))
5179                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5180         }
5181
5182         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5183         tmp &= ~(0xFF << 24);
5184         tmp |= (0x12 << 24);
5185         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5186
5187         if (is_sdv) {
5188                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5189                 tmp |= 0x7FFF;
5190                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5191         }
5192
5193         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5194         tmp |= (1 << 11);
5195         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5196
5197         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5198         tmp |= (1 << 11);
5199         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5200
5201         if (is_sdv) {
5202                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5203                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5204                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5205
5206                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5207                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5208                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5209
5210                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5211                 tmp |= (0x3F << 8);
5212                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5213
5214                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5215                 tmp |= (0x3F << 8);
5216                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5217         }
5218
5219         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5220         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5221         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5222
5223         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5224         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5226
5227         if (!is_sdv) {
5228                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5229                 tmp &= ~(7 << 13);
5230                 tmp |= (5 << 13);
5231                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5232
5233                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5234                 tmp &= ~(7 << 13);
5235                 tmp |= (5 << 13);
5236                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5237         }
5238
5239         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5240         tmp &= ~0xFF;
5241         tmp |= 0x1C;
5242         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5243
5244         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5245         tmp &= ~0xFF;
5246         tmp |= 0x1C;
5247         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5248
5249         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5250         tmp &= ~(0xFF << 16);
5251         tmp |= (0x1C << 16);
5252         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5253
5254         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5255         tmp &= ~(0xFF << 16);
5256         tmp |= (0x1C << 16);
5257         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5258
5259         if (!is_sdv) {
5260                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5261                 tmp |= (1 << 27);
5262                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5263
5264                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5265                 tmp |= (1 << 27);
5266                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5267
5268                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5269                 tmp &= ~(0xF << 28);
5270                 tmp |= (4 << 28);
5271                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5272
5273                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5274                 tmp &= ~(0xF << 28);
5275                 tmp |= (4 << 28);
5276                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5277         }
5278
5279         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5280         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5281         tmp |= SBI_DBUFF0_ENABLE;
5282         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5283
5284         mutex_unlock(&dev_priv->dpio_lock);
5285 }
5286
5287 /*
5288  * Initialize reference clocks when the driver loads
5289  */
5290 void intel_init_pch_refclk(struct drm_device *dev)
5291 {
5292         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5293                 ironlake_init_pch_refclk(dev);
5294         else if (HAS_PCH_LPT(dev))
5295                 lpt_init_pch_refclk(dev);
5296 }
5297
5298 static int ironlake_get_refclk(struct drm_crtc *crtc)
5299 {
5300         struct drm_device *dev = crtc->dev;
5301         struct drm_i915_private *dev_priv = dev->dev_private;
5302         struct intel_encoder *encoder;
5303         int num_connectors = 0;
5304         bool is_lvds = false;
5305
5306         for_each_encoder_on_crtc(dev, crtc, encoder) {
5307                 switch (encoder->type) {
5308                 case INTEL_OUTPUT_LVDS:
5309                         is_lvds = true;
5310                         break;
5311                 }
5312                 num_connectors++;
5313         }
5314
5315         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5316                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5317                               dev_priv->vbt.lvds_ssc_freq);
5318                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5319         }
5320
5321         return 120000;
5322 }
5323
5324 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5325 {
5326         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328         int pipe = intel_crtc->pipe;
5329         uint32_t val;
5330
5331         val = I915_READ(PIPECONF(pipe));
5332
5333         val &= ~PIPECONF_BPC_MASK;
5334         switch (intel_crtc->config.pipe_bpp) {
5335         case 18:
5336                 val |= PIPECONF_6BPC;
5337                 break;
5338         case 24:
5339                 val |= PIPECONF_8BPC;
5340                 break;
5341         case 30:
5342                 val |= PIPECONF_10BPC;
5343                 break;
5344         case 36:
5345                 val |= PIPECONF_12BPC;
5346                 break;
5347         default:
5348                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5349                 BUG();
5350         }
5351
5352         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5353         if (intel_crtc->config.dither)
5354                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5355
5356         val &= ~PIPECONF_INTERLACE_MASK;
5357         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5358                 val |= PIPECONF_INTERLACED_ILK;
5359         else
5360                 val |= PIPECONF_PROGRESSIVE;
5361
5362         if (intel_crtc->config.limited_color_range)
5363                 val |= PIPECONF_COLOR_RANGE_SELECT;
5364         else
5365                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5366
5367         I915_WRITE(PIPECONF(pipe), val);
5368         POSTING_READ(PIPECONF(pipe));
5369 }
5370
5371 /*
5372  * Set up the pipe CSC unit.
5373  *
5374  * Currently only full range RGB to limited range RGB conversion
5375  * is supported, but eventually this should handle various
5376  * RGB<->YCbCr scenarios as well.
5377  */
5378 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5379 {
5380         struct drm_device *dev = crtc->dev;
5381         struct drm_i915_private *dev_priv = dev->dev_private;
5382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383         int pipe = intel_crtc->pipe;
5384         uint16_t coeff = 0x7800; /* 1.0 */
5385
5386         /*
5387          * TODO: Check what kind of values actually come out of the pipe
5388          * with these coeff/postoff values and adjust to get the best
5389          * accuracy. Perhaps we even need to take the bpc value into
5390          * consideration.
5391          */
5392
5393         if (intel_crtc->config.limited_color_range)
5394                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5395
5396         /*
5397          * GY/GU and RY/RU should be the other way around according
5398          * to BSpec, but reality doesn't agree. Just set them up in
5399          * a way that results in the correct picture.
5400          */
5401         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5402         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5403
5404         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5405         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5406
5407         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5408         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5409
5410         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5411         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5412         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5413
5414         if (INTEL_INFO(dev)->gen > 6) {
5415                 uint16_t postoff = 0;
5416
5417                 if (intel_crtc->config.limited_color_range)
5418                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5419
5420                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5421                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5422                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5423
5424                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5425         } else {
5426                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5427
5428                 if (intel_crtc->config.limited_color_range)
5429                         mode |= CSC_BLACK_SCREEN_OFFSET;
5430
5431                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5432         }
5433 }
5434
5435 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5436 {
5437         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5440         uint32_t val;
5441
5442         val = I915_READ(PIPECONF(cpu_transcoder));
5443
5444         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5445         if (intel_crtc->config.dither)
5446                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5447
5448         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5449         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5450                 val |= PIPECONF_INTERLACED_ILK;
5451         else
5452                 val |= PIPECONF_PROGRESSIVE;
5453
5454         I915_WRITE(PIPECONF(cpu_transcoder), val);
5455         POSTING_READ(PIPECONF(cpu_transcoder));
5456 }
5457
5458 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5459                                     intel_clock_t *clock,
5460                                     bool *has_reduced_clock,
5461                                     intel_clock_t *reduced_clock)
5462 {
5463         struct drm_device *dev = crtc->dev;
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         struct intel_encoder *intel_encoder;
5466         int refclk;
5467         const intel_limit_t *limit;
5468         bool ret, is_lvds = false;
5469
5470         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5471                 switch (intel_encoder->type) {
5472                 case INTEL_OUTPUT_LVDS:
5473                         is_lvds = true;
5474                         break;
5475                 }
5476         }
5477
5478         refclk = ironlake_get_refclk(crtc);
5479
5480         /*
5481          * Returns a set of divisors for the desired target clock with the given
5482          * refclk, or FALSE.  The returned values represent the clock equation:
5483          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5484          */
5485         limit = intel_limit(crtc, refclk);
5486         ret = dev_priv->display.find_dpll(limit, crtc,
5487                                           to_intel_crtc(crtc)->config.port_clock,
5488                                           refclk, NULL, clock);
5489         if (!ret)
5490                 return false;
5491
5492         if (is_lvds && dev_priv->lvds_downclock_avail) {
5493                 /*
5494                  * Ensure we match the reduced clock's P to the target clock.
5495                  * If the clocks don't match, we can't switch the display clock
5496                  * by using the FP0/FP1. In such case we will disable the LVDS
5497                  * downclock feature.
5498                 */
5499                 *has_reduced_clock =
5500                         dev_priv->display.find_dpll(limit, crtc,
5501                                                     dev_priv->lvds_downclock,
5502                                                     refclk, clock,
5503                                                     reduced_clock);
5504         }
5505
5506         return true;
5507 }
5508
5509 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5510 {
5511         struct drm_i915_private *dev_priv = dev->dev_private;
5512         uint32_t temp;
5513
5514         temp = I915_READ(SOUTH_CHICKEN1);
5515         if (temp & FDI_BC_BIFURCATION_SELECT)
5516                 return;
5517
5518         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5519         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5520
5521         temp |= FDI_BC_BIFURCATION_SELECT;
5522         DRM_DEBUG_KMS("enabling fdi C rx\n");
5523         I915_WRITE(SOUTH_CHICKEN1, temp);
5524         POSTING_READ(SOUTH_CHICKEN1);
5525 }
5526
5527 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5528 {
5529         struct drm_device *dev = intel_crtc->base.dev;
5530         struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532         switch (intel_crtc->pipe) {
5533         case PIPE_A:
5534                 break;
5535         case PIPE_B:
5536                 if (intel_crtc->config.fdi_lanes > 2)
5537                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5538                 else
5539                         cpt_enable_fdi_bc_bifurcation(dev);
5540
5541                 break;
5542         case PIPE_C:
5543                 cpt_enable_fdi_bc_bifurcation(dev);
5544
5545                 break;
5546         default:
5547                 BUG();
5548         }
5549 }
5550
5551 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5552 {
5553         /*
5554          * Account for spread spectrum to avoid
5555          * oversubscribing the link. Max center spread
5556          * is 2.5%; use 5% for safety's sake.
5557          */
5558         u32 bps = target_clock * bpp * 21 / 20;
5559         return bps / (link_bw * 8) + 1;
5560 }
5561
5562 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5563 {
5564         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5565 }
5566
5567 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5568                                       u32 *fp,
5569                                       intel_clock_t *reduced_clock, u32 *fp2)
5570 {
5571         struct drm_crtc *crtc = &intel_crtc->base;
5572         struct drm_device *dev = crtc->dev;
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574         struct intel_encoder *intel_encoder;
5575         uint32_t dpll;
5576         int factor, num_connectors = 0;
5577         bool is_lvds = false, is_sdvo = false;
5578
5579         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5580                 switch (intel_encoder->type) {
5581                 case INTEL_OUTPUT_LVDS:
5582                         is_lvds = true;
5583                         break;
5584                 case INTEL_OUTPUT_SDVO:
5585                 case INTEL_OUTPUT_HDMI:
5586                         is_sdvo = true;
5587                         break;
5588                 }
5589
5590                 num_connectors++;
5591         }
5592
5593         /* Enable autotuning of the PLL clock (if permissible) */
5594         factor = 21;
5595         if (is_lvds) {
5596                 if ((intel_panel_use_ssc(dev_priv) &&
5597                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5598                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5599                         factor = 25;
5600         } else if (intel_crtc->config.sdvo_tv_clock)
5601                 factor = 20;
5602
5603         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5604                 *fp |= FP_CB_TUNE;
5605
5606         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5607                 *fp2 |= FP_CB_TUNE;
5608
5609         dpll = 0;
5610
5611         if (is_lvds)
5612                 dpll |= DPLLB_MODE_LVDS;
5613         else
5614                 dpll |= DPLLB_MODE_DAC_SERIAL;
5615
5616         if (intel_crtc->config.pixel_multiplier > 1) {
5617                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5618                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5619         }
5620
5621         if (is_sdvo)
5622                 dpll |= DPLL_DVO_HIGH_SPEED;
5623         if (intel_crtc->config.has_dp_encoder)
5624                 dpll |= DPLL_DVO_HIGH_SPEED;
5625
5626         /* compute bitmask from p1 value */
5627         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5628         /* also FPA1 */
5629         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5630
5631         switch (intel_crtc->config.dpll.p2) {
5632         case 5:
5633                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5634                 break;
5635         case 7:
5636                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5637                 break;
5638         case 10:
5639                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5640                 break;
5641         case 14:
5642                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5643                 break;
5644         }
5645
5646         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5647                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5648         else
5649                 dpll |= PLL_REF_INPUT_DREFCLK;
5650
5651         return dpll;
5652 }
5653
5654 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5655                                   int x, int y,
5656                                   struct drm_framebuffer *fb)
5657 {
5658         struct drm_device *dev = crtc->dev;
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5661         int pipe = intel_crtc->pipe;
5662         int plane = intel_crtc->plane;
5663         int num_connectors = 0;
5664         intel_clock_t clock, reduced_clock;
5665         u32 dpll = 0, fp = 0, fp2 = 0;
5666         bool ok, has_reduced_clock = false;
5667         bool is_lvds = false;
5668         struct intel_encoder *encoder;
5669         int ret;
5670
5671         for_each_encoder_on_crtc(dev, crtc, encoder) {
5672                 switch (encoder->type) {
5673                 case INTEL_OUTPUT_LVDS:
5674                         is_lvds = true;
5675                         break;
5676                 }
5677
5678                 num_connectors++;
5679         }
5680
5681         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5682              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5683
5684         ok = ironlake_compute_clocks(crtc, &clock,
5685                                      &has_reduced_clock, &reduced_clock);
5686         if (!ok && !intel_crtc->config.clock_set) {
5687                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5688                 return -EINVAL;
5689         }
5690         /* Compat-code for transition, will disappear. */
5691         if (!intel_crtc->config.clock_set) {
5692                 intel_crtc->config.dpll.n = clock.n;
5693                 intel_crtc->config.dpll.m1 = clock.m1;
5694                 intel_crtc->config.dpll.m2 = clock.m2;
5695                 intel_crtc->config.dpll.p1 = clock.p1;
5696                 intel_crtc->config.dpll.p2 = clock.p2;
5697         }
5698
5699         /* Ensure that the cursor is valid for the new mode before changing... */
5700         intel_crtc_update_cursor(crtc, true);
5701
5702         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5703         if (intel_crtc->config.has_pch_encoder) {
5704                 struct intel_pch_pll *pll;
5705
5706                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5707                 if (has_reduced_clock)
5708                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5709
5710                 dpll = ironlake_compute_dpll(intel_crtc,
5711                                              &fp, &reduced_clock,
5712                                              has_reduced_clock ? &fp2 : NULL);
5713
5714                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5715                 if (pll == NULL) {
5716                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5717                                          pipe_name(pipe));
5718                         return -EINVAL;
5719                 }
5720         } else
5721                 intel_put_pch_pll(intel_crtc);
5722
5723         if (intel_crtc->config.has_dp_encoder)
5724                 intel_dp_set_m_n(intel_crtc);
5725
5726         for_each_encoder_on_crtc(dev, crtc, encoder)
5727                 if (encoder->pre_pll_enable)
5728                         encoder->pre_pll_enable(encoder);
5729
5730         if (intel_crtc->pch_pll) {
5731                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5732
5733                 /* Wait for the clocks to stabilize. */
5734                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5735                 udelay(150);
5736
5737                 /* The pixel multiplier can only be updated once the
5738                  * DPLL is enabled and the clocks are stable.
5739                  *
5740                  * So write it again.
5741                  */
5742                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5743         }
5744
5745         intel_crtc->lowfreq_avail = false;
5746         if (intel_crtc->pch_pll) {
5747                 if (is_lvds && has_reduced_clock && i915_powersave) {
5748                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5749                         intel_crtc->lowfreq_avail = true;
5750                 } else {
5751                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5752                 }
5753         }
5754
5755         intel_set_pipe_timings(intel_crtc);
5756
5757         if (intel_crtc->config.has_pch_encoder) {
5758                 intel_cpu_transcoder_set_m_n(intel_crtc,
5759                                              &intel_crtc->config.fdi_m_n);
5760         }
5761
5762         if (IS_IVYBRIDGE(dev))
5763                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5764
5765         ironlake_set_pipeconf(crtc);
5766
5767         /* Set up the display plane register */
5768         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5769         POSTING_READ(DSPCNTR(plane));
5770
5771         ret = intel_pipe_set_base(crtc, x, y, fb);
5772
5773         intel_update_watermarks(dev);
5774
5775         return ret;
5776 }
5777
5778 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5779                                         struct intel_crtc_config *pipe_config)
5780 {
5781         struct drm_device *dev = crtc->base.dev;
5782         struct drm_i915_private *dev_priv = dev->dev_private;
5783         enum transcoder transcoder = pipe_config->cpu_transcoder;
5784
5785         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5786         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5787         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5788                                         & ~TU_SIZE_MASK;
5789         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5790         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5791                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5792 }
5793
5794 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5795                                      struct intel_crtc_config *pipe_config)
5796 {
5797         struct drm_device *dev = crtc->base.dev;
5798         struct drm_i915_private *dev_priv = dev->dev_private;
5799         uint32_t tmp;
5800
5801         tmp = I915_READ(PF_CTL(crtc->pipe));
5802
5803         if (tmp & PF_ENABLE) {
5804                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5805                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5806         }
5807 }
5808
5809 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5810                                      struct intel_crtc_config *pipe_config)
5811 {
5812         struct drm_device *dev = crtc->base.dev;
5813         struct drm_i915_private *dev_priv = dev->dev_private;
5814         uint32_t tmp;
5815
5816         pipe_config->cpu_transcoder = crtc->pipe;
5817
5818         tmp = I915_READ(PIPECONF(crtc->pipe));
5819         if (!(tmp & PIPECONF_ENABLE))
5820                 return false;
5821
5822         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5823                 pipe_config->has_pch_encoder = true;
5824
5825                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5826                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5827                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5828
5829                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5830         }
5831
5832         intel_get_pipe_timings(crtc, pipe_config);
5833
5834         ironlake_get_pfit_config(crtc, pipe_config);
5835
5836         return true;
5837 }
5838
5839 static void haswell_modeset_global_resources(struct drm_device *dev)
5840 {
5841         bool enable = false;
5842         struct intel_crtc *crtc;
5843
5844         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5845                 if (!crtc->base.enabled)
5846                         continue;
5847
5848                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5849                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5850                         enable = true;
5851         }
5852
5853         intel_set_power_well(dev, enable);
5854 }
5855
5856 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5857                                  int x, int y,
5858                                  struct drm_framebuffer *fb)
5859 {
5860         struct drm_device *dev = crtc->dev;
5861         struct drm_i915_private *dev_priv = dev->dev_private;
5862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5863         int pipe = intel_crtc->pipe;
5864         int plane = intel_crtc->plane;
5865         int num_connectors = 0;
5866         bool is_cpu_edp = false;
5867         struct intel_encoder *encoder;
5868         int ret;
5869
5870         for_each_encoder_on_crtc(dev, crtc, encoder) {
5871                 switch (encoder->type) {
5872                 case INTEL_OUTPUT_EDP:
5873                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5874                                 is_cpu_edp = true;
5875                         break;
5876                 }
5877
5878                 num_connectors++;
5879         }
5880
5881         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5882              num_connectors, pipe_name(pipe));
5883
5884         if (!intel_ddi_pll_mode_set(crtc))
5885                 return -EINVAL;
5886
5887         /* Ensure that the cursor is valid for the new mode before changing... */
5888         intel_crtc_update_cursor(crtc, true);
5889
5890         if (intel_crtc->config.has_dp_encoder)
5891                 intel_dp_set_m_n(intel_crtc);
5892
5893         intel_crtc->lowfreq_avail = false;
5894
5895         intel_set_pipe_timings(intel_crtc);
5896
5897         if (intel_crtc->config.has_pch_encoder) {
5898                 intel_cpu_transcoder_set_m_n(intel_crtc,
5899                                              &intel_crtc->config.fdi_m_n);
5900         }
5901
5902         haswell_set_pipeconf(crtc);
5903
5904         intel_set_pipe_csc(crtc);
5905
5906         /* Set up the display plane register */
5907         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5908         POSTING_READ(DSPCNTR(plane));
5909
5910         ret = intel_pipe_set_base(crtc, x, y, fb);
5911
5912         intel_update_watermarks(dev);
5913
5914         return ret;
5915 }
5916
5917 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5918                                     struct intel_crtc_config *pipe_config)
5919 {
5920         struct drm_device *dev = crtc->base.dev;
5921         struct drm_i915_private *dev_priv = dev->dev_private;
5922         enum intel_display_power_domain pfit_domain;
5923         uint32_t tmp;
5924
5925         pipe_config->cpu_transcoder = crtc->pipe;
5926         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5927         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5928                 enum pipe trans_edp_pipe;
5929                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5930                 default:
5931                         WARN(1, "unknown pipe linked to edp transcoder\n");
5932                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5933                 case TRANS_DDI_EDP_INPUT_A_ON:
5934                         trans_edp_pipe = PIPE_A;
5935                         break;
5936                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5937                         trans_edp_pipe = PIPE_B;
5938                         break;
5939                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5940                         trans_edp_pipe = PIPE_C;
5941                         break;
5942                 }
5943
5944                 if (trans_edp_pipe == crtc->pipe)
5945                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5946         }
5947
5948         if (!intel_display_power_enabled(dev,
5949                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5950                 return false;
5951
5952         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5953         if (!(tmp & PIPECONF_ENABLE))
5954                 return false;
5955
5956         /*
5957          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5958          * DDI E. So just check whether this pipe is wired to DDI E and whether
5959          * the PCH transcoder is on.
5960          */
5961         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5962         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5963             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5964                 pipe_config->has_pch_encoder = true;
5965
5966                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5967                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5968                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5969
5970                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5971         }
5972
5973         intel_get_pipe_timings(crtc, pipe_config);
5974
5975         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5976         if (intel_display_power_enabled(dev, pfit_domain))
5977                 ironlake_get_pfit_config(crtc, pipe_config);
5978
5979         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5980                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
5981
5982         return true;
5983 }
5984
5985 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5986                                int x, int y,
5987                                struct drm_framebuffer *fb)
5988 {
5989         struct drm_device *dev = crtc->dev;
5990         struct drm_i915_private *dev_priv = dev->dev_private;
5991         struct drm_encoder_helper_funcs *encoder_funcs;
5992         struct intel_encoder *encoder;
5993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994         struct drm_display_mode *adjusted_mode =
5995                 &intel_crtc->config.adjusted_mode;
5996         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5997         int pipe = intel_crtc->pipe;
5998         int ret;
5999
6000         drm_vblank_pre_modeset(dev, pipe);
6001
6002         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6003
6004         drm_vblank_post_modeset(dev, pipe);
6005
6006         if (ret != 0)
6007                 return ret;
6008
6009         for_each_encoder_on_crtc(dev, crtc, encoder) {
6010                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6011                         encoder->base.base.id,
6012                         drm_get_encoder_name(&encoder->base),
6013                         mode->base.id, mode->name);
6014                 if (encoder->mode_set) {
6015                         encoder->mode_set(encoder);
6016                 } else {
6017                         encoder_funcs = encoder->base.helper_private;
6018                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6019                 }
6020         }
6021
6022         return 0;
6023 }
6024
6025 static bool intel_eld_uptodate(struct drm_connector *connector,
6026                                int reg_eldv, uint32_t bits_eldv,
6027                                int reg_elda, uint32_t bits_elda,
6028                                int reg_edid)
6029 {
6030         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6031         uint8_t *eld = connector->eld;
6032         uint32_t i;
6033
6034         i = I915_READ(reg_eldv);
6035         i &= bits_eldv;
6036
6037         if (!eld[0])
6038                 return !i;
6039
6040         if (!i)
6041                 return false;
6042
6043         i = I915_READ(reg_elda);
6044         i &= ~bits_elda;
6045         I915_WRITE(reg_elda, i);
6046
6047         for (i = 0; i < eld[2]; i++)
6048                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6049                         return false;
6050
6051         return true;
6052 }
6053
6054 static void g4x_write_eld(struct drm_connector *connector,
6055                           struct drm_crtc *crtc)
6056 {
6057         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6058         uint8_t *eld = connector->eld;
6059         uint32_t eldv;
6060         uint32_t len;
6061         uint32_t i;
6062
6063         i = I915_READ(G4X_AUD_VID_DID);
6064
6065         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6066                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6067         else
6068                 eldv = G4X_ELDV_DEVCTG;
6069
6070         if (intel_eld_uptodate(connector,
6071                                G4X_AUD_CNTL_ST, eldv,
6072                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6073                                G4X_HDMIW_HDMIEDID))
6074                 return;
6075
6076         i = I915_READ(G4X_AUD_CNTL_ST);
6077         i &= ~(eldv | G4X_ELD_ADDR);
6078         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6079         I915_WRITE(G4X_AUD_CNTL_ST, i);
6080
6081         if (!eld[0])
6082                 return;
6083
6084         len = min_t(uint8_t, eld[2], len);
6085         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6086         for (i = 0; i < len; i++)
6087                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6088
6089         i = I915_READ(G4X_AUD_CNTL_ST);
6090         i |= eldv;
6091         I915_WRITE(G4X_AUD_CNTL_ST, i);
6092 }
6093
6094 static void haswell_write_eld(struct drm_connector *connector,
6095                                      struct drm_crtc *crtc)
6096 {
6097         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6098         uint8_t *eld = connector->eld;
6099         struct drm_device *dev = crtc->dev;
6100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101         uint32_t eldv;
6102         uint32_t i;
6103         int len;
6104         int pipe = to_intel_crtc(crtc)->pipe;
6105         int tmp;
6106
6107         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6108         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6109         int aud_config = HSW_AUD_CFG(pipe);
6110         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6111
6112
6113         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6114
6115         /* Audio output enable */
6116         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6117         tmp = I915_READ(aud_cntrl_st2);
6118         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6119         I915_WRITE(aud_cntrl_st2, tmp);
6120
6121         /* Wait for 1 vertical blank */
6122         intel_wait_for_vblank(dev, pipe);
6123
6124         /* Set ELD valid state */
6125         tmp = I915_READ(aud_cntrl_st2);
6126         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6127         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6128         I915_WRITE(aud_cntrl_st2, tmp);
6129         tmp = I915_READ(aud_cntrl_st2);
6130         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6131
6132         /* Enable HDMI mode */
6133         tmp = I915_READ(aud_config);
6134         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6135         /* clear N_programing_enable and N_value_index */
6136         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6137         I915_WRITE(aud_config, tmp);
6138
6139         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6140
6141         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6142         intel_crtc->eld_vld = true;
6143
6144         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6145                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6146                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6147                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6148         } else
6149                 I915_WRITE(aud_config, 0);
6150
6151         if (intel_eld_uptodate(connector,
6152                                aud_cntrl_st2, eldv,
6153                                aud_cntl_st, IBX_ELD_ADDRESS,
6154                                hdmiw_hdmiedid))
6155                 return;
6156
6157         i = I915_READ(aud_cntrl_st2);
6158         i &= ~eldv;
6159         I915_WRITE(aud_cntrl_st2, i);
6160
6161         if (!eld[0])
6162                 return;
6163
6164         i = I915_READ(aud_cntl_st);
6165         i &= ~IBX_ELD_ADDRESS;
6166         I915_WRITE(aud_cntl_st, i);
6167         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6168         DRM_DEBUG_DRIVER("port num:%d\n", i);
6169
6170         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6171         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6172         for (i = 0; i < len; i++)
6173                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6174
6175         i = I915_READ(aud_cntrl_st2);
6176         i |= eldv;
6177         I915_WRITE(aud_cntrl_st2, i);
6178
6179 }
6180
6181 static void ironlake_write_eld(struct drm_connector *connector,
6182                                      struct drm_crtc *crtc)
6183 {
6184         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6185         uint8_t *eld = connector->eld;
6186         uint32_t eldv;
6187         uint32_t i;
6188         int len;
6189         int hdmiw_hdmiedid;
6190         int aud_config;
6191         int aud_cntl_st;
6192         int aud_cntrl_st2;
6193         int pipe = to_intel_crtc(crtc)->pipe;
6194
6195         if (HAS_PCH_IBX(connector->dev)) {
6196                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6197                 aud_config = IBX_AUD_CFG(pipe);
6198                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6199                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6200         } else {
6201                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6202                 aud_config = CPT_AUD_CFG(pipe);
6203                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6204                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6205         }
6206
6207         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6208
6209         i = I915_READ(aud_cntl_st);
6210         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6211         if (!i) {
6212                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6213                 /* operate blindly on all ports */
6214                 eldv = IBX_ELD_VALIDB;
6215                 eldv |= IBX_ELD_VALIDB << 4;
6216                 eldv |= IBX_ELD_VALIDB << 8;
6217         } else {
6218                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6219                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6220         }
6221
6222         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6223                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6224                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6225                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6226         } else
6227                 I915_WRITE(aud_config, 0);
6228
6229         if (intel_eld_uptodate(connector,
6230                                aud_cntrl_st2, eldv,
6231                                aud_cntl_st, IBX_ELD_ADDRESS,
6232                                hdmiw_hdmiedid))
6233                 return;
6234
6235         i = I915_READ(aud_cntrl_st2);
6236         i &= ~eldv;
6237         I915_WRITE(aud_cntrl_st2, i);
6238
6239         if (!eld[0])
6240                 return;
6241
6242         i = I915_READ(aud_cntl_st);
6243         i &= ~IBX_ELD_ADDRESS;
6244         I915_WRITE(aud_cntl_st, i);
6245
6246         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6247         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6248         for (i = 0; i < len; i++)
6249                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6250
6251         i = I915_READ(aud_cntrl_st2);
6252         i |= eldv;
6253         I915_WRITE(aud_cntrl_st2, i);
6254 }
6255
6256 void intel_write_eld(struct drm_encoder *encoder,
6257                      struct drm_display_mode *mode)
6258 {
6259         struct drm_crtc *crtc = encoder->crtc;
6260         struct drm_connector *connector;
6261         struct drm_device *dev = encoder->dev;
6262         struct drm_i915_private *dev_priv = dev->dev_private;
6263
6264         connector = drm_select_eld(encoder, mode);
6265         if (!connector)
6266                 return;
6267
6268         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6269                          connector->base.id,
6270                          drm_get_connector_name(connector),
6271                          connector->encoder->base.id,
6272                          drm_get_encoder_name(connector->encoder));
6273
6274         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6275
6276         if (dev_priv->display.write_eld)
6277                 dev_priv->display.write_eld(connector, crtc);
6278 }
6279
6280 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6281 void intel_crtc_load_lut(struct drm_crtc *crtc)
6282 {
6283         struct drm_device *dev = crtc->dev;
6284         struct drm_i915_private *dev_priv = dev->dev_private;
6285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286         enum pipe pipe = intel_crtc->pipe;
6287         int palreg = PALETTE(pipe);
6288         int i;
6289         bool reenable_ips = false;
6290
6291         /* The clocks have to be on to load the palette. */
6292         if (!crtc->enabled || !intel_crtc->active)
6293                 return;
6294
6295         /* use legacy palette for Ironlake */
6296         if (HAS_PCH_SPLIT(dev))
6297                 palreg = LGC_PALETTE(pipe);
6298
6299         /* Workaround : Do not read or write the pipe palette/gamma data while
6300          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6301          */
6302         if (intel_crtc->config.ips_enabled &&
6303             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6304              GAMMA_MODE_MODE_SPLIT)) {
6305                 hsw_disable_ips(intel_crtc);
6306                 reenable_ips = true;
6307         }
6308
6309         for (i = 0; i < 256; i++) {
6310                 I915_WRITE(palreg + 4 * i,
6311                            (intel_crtc->lut_r[i] << 16) |
6312                            (intel_crtc->lut_g[i] << 8) |
6313                            intel_crtc->lut_b[i]);
6314         }
6315
6316         if (reenable_ips)
6317                 hsw_enable_ips(intel_crtc);
6318 }
6319
6320 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6321 {
6322         struct drm_device *dev = crtc->dev;
6323         struct drm_i915_private *dev_priv = dev->dev_private;
6324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6325         bool visible = base != 0;
6326         u32 cntl;
6327
6328         if (intel_crtc->cursor_visible == visible)
6329                 return;
6330
6331         cntl = I915_READ(_CURACNTR);
6332         if (visible) {
6333                 /* On these chipsets we can only modify the base whilst
6334                  * the cursor is disabled.
6335                  */
6336                 I915_WRITE(_CURABASE, base);
6337
6338                 cntl &= ~(CURSOR_FORMAT_MASK);
6339                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6340                 cntl |= CURSOR_ENABLE |
6341                         CURSOR_GAMMA_ENABLE |
6342                         CURSOR_FORMAT_ARGB;
6343         } else
6344                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6345         I915_WRITE(_CURACNTR, cntl);
6346
6347         intel_crtc->cursor_visible = visible;
6348 }
6349
6350 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6351 {
6352         struct drm_device *dev = crtc->dev;
6353         struct drm_i915_private *dev_priv = dev->dev_private;
6354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355         int pipe = intel_crtc->pipe;
6356         bool visible = base != 0;
6357
6358         if (intel_crtc->cursor_visible != visible) {
6359                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6360                 if (base) {
6361                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6362                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6363                         cntl |= pipe << 28; /* Connect to correct pipe */
6364                 } else {
6365                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6366                         cntl |= CURSOR_MODE_DISABLE;
6367                 }
6368                 I915_WRITE(CURCNTR(pipe), cntl);
6369
6370                 intel_crtc->cursor_visible = visible;
6371         }
6372         /* and commit changes on next vblank */
6373         I915_WRITE(CURBASE(pipe), base);
6374 }
6375
6376 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6377 {
6378         struct drm_device *dev = crtc->dev;
6379         struct drm_i915_private *dev_priv = dev->dev_private;
6380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381         int pipe = intel_crtc->pipe;
6382         bool visible = base != 0;
6383
6384         if (intel_crtc->cursor_visible != visible) {
6385                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6386                 if (base) {
6387                         cntl &= ~CURSOR_MODE;
6388                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6389                 } else {
6390                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6391                         cntl |= CURSOR_MODE_DISABLE;
6392                 }
6393                 if (IS_HASWELL(dev))
6394                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6395                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6396
6397                 intel_crtc->cursor_visible = visible;
6398         }
6399         /* and commit changes on next vblank */
6400         I915_WRITE(CURBASE_IVB(pipe), base);
6401 }
6402
6403 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6404 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6405                                      bool on)
6406 {
6407         struct drm_device *dev = crtc->dev;
6408         struct drm_i915_private *dev_priv = dev->dev_private;
6409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6410         int pipe = intel_crtc->pipe;
6411         int x = intel_crtc->cursor_x;
6412         int y = intel_crtc->cursor_y;
6413         u32 base, pos;
6414         bool visible;
6415
6416         pos = 0;
6417
6418         if (on && crtc->enabled && crtc->fb) {
6419                 base = intel_crtc->cursor_addr;
6420                 if (x > (int) crtc->fb->width)
6421                         base = 0;
6422
6423                 if (y > (int) crtc->fb->height)
6424                         base = 0;
6425         } else
6426                 base = 0;
6427
6428         if (x < 0) {
6429                 if (x + intel_crtc->cursor_width < 0)
6430                         base = 0;
6431
6432                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6433                 x = -x;
6434         }
6435         pos |= x << CURSOR_X_SHIFT;
6436
6437         if (y < 0) {
6438                 if (y + intel_crtc->cursor_height < 0)
6439                         base = 0;
6440
6441                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6442                 y = -y;
6443         }
6444         pos |= y << CURSOR_Y_SHIFT;
6445
6446         visible = base != 0;
6447         if (!visible && !intel_crtc->cursor_visible)
6448                 return;
6449
6450         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6451                 I915_WRITE(CURPOS_IVB(pipe), pos);
6452                 ivb_update_cursor(crtc, base);
6453         } else {
6454                 I915_WRITE(CURPOS(pipe), pos);
6455                 if (IS_845G(dev) || IS_I865G(dev))
6456                         i845_update_cursor(crtc, base);
6457                 else
6458                         i9xx_update_cursor(crtc, base);
6459         }
6460 }
6461
6462 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6463                                  struct drm_file *file,
6464                                  uint32_t handle,
6465                                  uint32_t width, uint32_t height)
6466 {
6467         struct drm_device *dev = crtc->dev;
6468         struct drm_i915_private *dev_priv = dev->dev_private;
6469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6470         struct drm_i915_gem_object *obj;
6471         uint32_t addr;
6472         int ret;
6473
6474         /* if we want to turn off the cursor ignore width and height */
6475         if (!handle) {
6476                 DRM_DEBUG_KMS("cursor off\n");
6477                 addr = 0;
6478                 obj = NULL;
6479                 mutex_lock(&dev->struct_mutex);
6480                 goto finish;
6481         }
6482
6483         /* Currently we only support 64x64 cursors */
6484         if (width != 64 || height != 64) {
6485                 DRM_ERROR("we currently only support 64x64 cursors\n");
6486                 return -EINVAL;
6487         }
6488
6489         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6490         if (&obj->base == NULL)
6491                 return -ENOENT;
6492
6493         if (obj->base.size < width * height * 4) {
6494                 DRM_ERROR("buffer is to small\n");
6495                 ret = -ENOMEM;
6496                 goto fail;
6497         }
6498
6499         /* we only need to pin inside GTT if cursor is non-phy */
6500         mutex_lock(&dev->struct_mutex);
6501         if (!dev_priv->info->cursor_needs_physical) {
6502                 unsigned alignment;
6503
6504                 if (obj->tiling_mode) {
6505                         DRM_ERROR("cursor cannot be tiled\n");
6506                         ret = -EINVAL;
6507                         goto fail_locked;
6508                 }
6509
6510                 /* Note that the w/a also requires 2 PTE of padding following
6511                  * the bo. We currently fill all unused PTE with the shadow
6512                  * page and so we should always have valid PTE following the
6513                  * cursor preventing the VT-d warning.
6514                  */
6515                 alignment = 0;
6516                 if (need_vtd_wa(dev))
6517                         alignment = 64*1024;
6518
6519                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6520                 if (ret) {
6521                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6522                         goto fail_locked;
6523                 }
6524
6525                 ret = i915_gem_object_put_fence(obj);
6526                 if (ret) {
6527                         DRM_ERROR("failed to release fence for cursor");
6528                         goto fail_unpin;
6529                 }
6530
6531                 addr = obj->gtt_offset;
6532         } else {
6533                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6534                 ret = i915_gem_attach_phys_object(dev, obj,
6535                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6536                                                   align);
6537                 if (ret) {
6538                         DRM_ERROR("failed to attach phys object\n");
6539                         goto fail_locked;
6540                 }
6541                 addr = obj->phys_obj->handle->busaddr;
6542         }
6543
6544         if (IS_GEN2(dev))
6545                 I915_WRITE(CURSIZE, (height << 12) | width);
6546
6547  finish:
6548         if (intel_crtc->cursor_bo) {
6549                 if (dev_priv->info->cursor_needs_physical) {
6550                         if (intel_crtc->cursor_bo != obj)
6551                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6552                 } else
6553                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6554                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6555         }
6556
6557         mutex_unlock(&dev->struct_mutex);
6558
6559         intel_crtc->cursor_addr = addr;
6560         intel_crtc->cursor_bo = obj;
6561         intel_crtc->cursor_width = width;
6562         intel_crtc->cursor_height = height;
6563
6564         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6565
6566         return 0;
6567 fail_unpin:
6568         i915_gem_object_unpin(obj);
6569 fail_locked:
6570         mutex_unlock(&dev->struct_mutex);
6571 fail:
6572         drm_gem_object_unreference_unlocked(&obj->base);
6573         return ret;
6574 }
6575
6576 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6577 {
6578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6579
6580         intel_crtc->cursor_x = x;
6581         intel_crtc->cursor_y = y;
6582
6583         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6584
6585         return 0;
6586 }
6587
6588 /** Sets the color ramps on behalf of RandR */
6589 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6590                                  u16 blue, int regno)
6591 {
6592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6593
6594         intel_crtc->lut_r[regno] = red >> 8;
6595         intel_crtc->lut_g[regno] = green >> 8;
6596         intel_crtc->lut_b[regno] = blue >> 8;
6597 }
6598
6599 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6600                              u16 *blue, int regno)
6601 {
6602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6603
6604         *red = intel_crtc->lut_r[regno] << 8;
6605         *green = intel_crtc->lut_g[regno] << 8;
6606         *blue = intel_crtc->lut_b[regno] << 8;
6607 }
6608
6609 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6610                                  u16 *blue, uint32_t start, uint32_t size)
6611 {
6612         int end = (start + size > 256) ? 256 : start + size, i;
6613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6614
6615         for (i = start; i < end; i++) {
6616                 intel_crtc->lut_r[i] = red[i] >> 8;
6617                 intel_crtc->lut_g[i] = green[i] >> 8;
6618                 intel_crtc->lut_b[i] = blue[i] >> 8;
6619         }
6620
6621         intel_crtc_load_lut(crtc);
6622 }
6623
6624 /* VESA 640x480x72Hz mode to set on the pipe */
6625 static struct drm_display_mode load_detect_mode = {
6626         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6627                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6628 };
6629
6630 static struct drm_framebuffer *
6631 intel_framebuffer_create(struct drm_device *dev,
6632                          struct drm_mode_fb_cmd2 *mode_cmd,
6633                          struct drm_i915_gem_object *obj)
6634 {
6635         struct intel_framebuffer *intel_fb;
6636         int ret;
6637
6638         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6639         if (!intel_fb) {
6640                 drm_gem_object_unreference_unlocked(&obj->base);
6641                 return ERR_PTR(-ENOMEM);
6642         }
6643
6644         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6645         if (ret) {
6646                 drm_gem_object_unreference_unlocked(&obj->base);
6647                 kfree(intel_fb);
6648                 return ERR_PTR(ret);
6649         }
6650
6651         return &intel_fb->base;
6652 }
6653
6654 static u32
6655 intel_framebuffer_pitch_for_width(int width, int bpp)
6656 {
6657         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6658         return ALIGN(pitch, 64);
6659 }
6660
6661 static u32
6662 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6663 {
6664         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6665         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6666 }
6667
6668 static struct drm_framebuffer *
6669 intel_framebuffer_create_for_mode(struct drm_device *dev,
6670                                   struct drm_display_mode *mode,
6671                                   int depth, int bpp)
6672 {
6673         struct drm_i915_gem_object *obj;
6674         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6675
6676         obj = i915_gem_alloc_object(dev,
6677                                     intel_framebuffer_size_for_mode(mode, bpp));
6678         if (obj == NULL)
6679                 return ERR_PTR(-ENOMEM);
6680
6681         mode_cmd.width = mode->hdisplay;
6682         mode_cmd.height = mode->vdisplay;
6683         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6684                                                                 bpp);
6685         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6686
6687         return intel_framebuffer_create(dev, &mode_cmd, obj);
6688 }
6689
6690 static struct drm_framebuffer *
6691 mode_fits_in_fbdev(struct drm_device *dev,
6692                    struct drm_display_mode *mode)
6693 {
6694         struct drm_i915_private *dev_priv = dev->dev_private;
6695         struct drm_i915_gem_object *obj;
6696         struct drm_framebuffer *fb;
6697
6698         if (dev_priv->fbdev == NULL)
6699                 return NULL;
6700
6701         obj = dev_priv->fbdev->ifb.obj;
6702         if (obj == NULL)
6703                 return NULL;
6704
6705         fb = &dev_priv->fbdev->ifb.base;
6706         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6707                                                                fb->bits_per_pixel))
6708                 return NULL;
6709
6710         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6711                 return NULL;
6712
6713         return fb;
6714 }
6715
6716 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6717                                 struct drm_display_mode *mode,
6718                                 struct intel_load_detect_pipe *old)
6719 {
6720         struct intel_crtc *intel_crtc;
6721         struct intel_encoder *intel_encoder =
6722                 intel_attached_encoder(connector);
6723         struct drm_crtc *possible_crtc;
6724         struct drm_encoder *encoder = &intel_encoder->base;
6725         struct drm_crtc *crtc = NULL;
6726         struct drm_device *dev = encoder->dev;
6727         struct drm_framebuffer *fb;
6728         int i = -1;
6729
6730         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6731                       connector->base.id, drm_get_connector_name(connector),
6732                       encoder->base.id, drm_get_encoder_name(encoder));
6733
6734         /*
6735          * Algorithm gets a little messy:
6736          *
6737          *   - if the connector already has an assigned crtc, use it (but make
6738          *     sure it's on first)
6739          *
6740          *   - try to find the first unused crtc that can drive this connector,
6741          *     and use that if we find one
6742          */
6743
6744         /* See if we already have a CRTC for this connector */
6745         if (encoder->crtc) {
6746                 crtc = encoder->crtc;
6747
6748                 mutex_lock(&crtc->mutex);
6749
6750                 old->dpms_mode = connector->dpms;
6751                 old->load_detect_temp = false;
6752
6753                 /* Make sure the crtc and connector are running */
6754                 if (connector->dpms != DRM_MODE_DPMS_ON)
6755                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6756
6757                 return true;
6758         }
6759
6760         /* Find an unused one (if possible) */
6761         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6762                 i++;
6763                 if (!(encoder->possible_crtcs & (1 << i)))
6764                         continue;
6765                 if (!possible_crtc->enabled) {
6766                         crtc = possible_crtc;
6767                         break;
6768                 }
6769         }
6770
6771         /*
6772          * If we didn't find an unused CRTC, don't use any.
6773          */
6774         if (!crtc) {
6775                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6776                 return false;
6777         }
6778
6779         mutex_lock(&crtc->mutex);
6780         intel_encoder->new_crtc = to_intel_crtc(crtc);
6781         to_intel_connector(connector)->new_encoder = intel_encoder;
6782
6783         intel_crtc = to_intel_crtc(crtc);
6784         old->dpms_mode = connector->dpms;
6785         old->load_detect_temp = true;
6786         old->release_fb = NULL;
6787
6788         if (!mode)
6789                 mode = &load_detect_mode;
6790
6791         /* We need a framebuffer large enough to accommodate all accesses
6792          * that the plane may generate whilst we perform load detection.
6793          * We can not rely on the fbcon either being present (we get called
6794          * during its initialisation to detect all boot displays, or it may
6795          * not even exist) or that it is large enough to satisfy the
6796          * requested mode.
6797          */
6798         fb = mode_fits_in_fbdev(dev, mode);
6799         if (fb == NULL) {
6800                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6801                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6802                 old->release_fb = fb;
6803         } else
6804                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6805         if (IS_ERR(fb)) {
6806                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6807                 mutex_unlock(&crtc->mutex);
6808                 return false;
6809         }
6810
6811         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6812                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6813                 if (old->release_fb)
6814                         old->release_fb->funcs->destroy(old->release_fb);
6815                 mutex_unlock(&crtc->mutex);
6816                 return false;
6817         }
6818
6819         /* let the connector get through one full cycle before testing */
6820         intel_wait_for_vblank(dev, intel_crtc->pipe);
6821         return true;
6822 }
6823
6824 void intel_release_load_detect_pipe(struct drm_connector *connector,
6825                                     struct intel_load_detect_pipe *old)
6826 {
6827         struct intel_encoder *intel_encoder =
6828                 intel_attached_encoder(connector);
6829         struct drm_encoder *encoder = &intel_encoder->base;
6830         struct drm_crtc *crtc = encoder->crtc;
6831
6832         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6833                       connector->base.id, drm_get_connector_name(connector),
6834                       encoder->base.id, drm_get_encoder_name(encoder));
6835
6836         if (old->load_detect_temp) {
6837                 to_intel_connector(connector)->new_encoder = NULL;
6838                 intel_encoder->new_crtc = NULL;
6839                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6840
6841                 if (old->release_fb) {
6842                         drm_framebuffer_unregister_private(old->release_fb);
6843                         drm_framebuffer_unreference(old->release_fb);
6844                 }
6845
6846                 mutex_unlock(&crtc->mutex);
6847                 return;
6848         }
6849
6850         /* Switch crtc and encoder back off if necessary */
6851         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6852                 connector->funcs->dpms(connector, old->dpms_mode);
6853
6854         mutex_unlock(&crtc->mutex);
6855 }
6856
6857 /* Returns the clock of the currently programmed mode of the given pipe. */
6858 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6859 {
6860         struct drm_i915_private *dev_priv = dev->dev_private;
6861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6862         int pipe = intel_crtc->pipe;
6863         u32 dpll = I915_READ(DPLL(pipe));
6864         u32 fp;
6865         intel_clock_t clock;
6866
6867         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6868                 fp = I915_READ(FP0(pipe));
6869         else
6870                 fp = I915_READ(FP1(pipe));
6871
6872         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6873         if (IS_PINEVIEW(dev)) {
6874                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6875                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6876         } else {
6877                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6878                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6879         }
6880
6881         if (!IS_GEN2(dev)) {
6882                 if (IS_PINEVIEW(dev))
6883                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6884                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6885                 else
6886                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6887                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6888
6889                 switch (dpll & DPLL_MODE_MASK) {
6890                 case DPLLB_MODE_DAC_SERIAL:
6891                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6892                                 5 : 10;
6893                         break;
6894                 case DPLLB_MODE_LVDS:
6895                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6896                                 7 : 14;
6897                         break;
6898                 default:
6899                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6900                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6901                         return 0;
6902                 }
6903
6904                 if (IS_PINEVIEW(dev))
6905                         pineview_clock(96000, &clock);
6906                 else
6907                         i9xx_clock(96000, &clock);
6908         } else {
6909                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6910
6911                 if (is_lvds) {
6912                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6913                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6914                         clock.p2 = 14;
6915
6916                         if ((dpll & PLL_REF_INPUT_MASK) ==
6917                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6918                                 /* XXX: might not be 66MHz */
6919                                 i9xx_clock(66000, &clock);
6920                         } else
6921                                 i9xx_clock(48000, &clock);
6922                 } else {
6923                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6924                                 clock.p1 = 2;
6925                         else {
6926                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6927                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6928                         }
6929                         if (dpll & PLL_P2_DIVIDE_BY_4)
6930                                 clock.p2 = 4;
6931                         else
6932                                 clock.p2 = 2;
6933
6934                         i9xx_clock(48000, &clock);
6935                 }
6936         }
6937
6938         /* XXX: It would be nice to validate the clocks, but we can't reuse
6939          * i830PllIsValid() because it relies on the xf86_config connector
6940          * configuration being accurate, which it isn't necessarily.
6941          */
6942
6943         return clock.dot;
6944 }
6945
6946 /** Returns the currently programmed mode of the given pipe. */
6947 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6948                                              struct drm_crtc *crtc)
6949 {
6950         struct drm_i915_private *dev_priv = dev->dev_private;
6951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6952         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6953         struct drm_display_mode *mode;
6954         int htot = I915_READ(HTOTAL(cpu_transcoder));
6955         int hsync = I915_READ(HSYNC(cpu_transcoder));
6956         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6957         int vsync = I915_READ(VSYNC(cpu_transcoder));
6958
6959         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6960         if (!mode)
6961                 return NULL;
6962
6963         mode->clock = intel_crtc_clock_get(dev, crtc);
6964         mode->hdisplay = (htot & 0xffff) + 1;
6965         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6966         mode->hsync_start = (hsync & 0xffff) + 1;
6967         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6968         mode->vdisplay = (vtot & 0xffff) + 1;
6969         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6970         mode->vsync_start = (vsync & 0xffff) + 1;
6971         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6972
6973         drm_mode_set_name(mode);
6974
6975         return mode;
6976 }
6977
6978 static void intel_increase_pllclock(struct drm_crtc *crtc)
6979 {
6980         struct drm_device *dev = crtc->dev;
6981         drm_i915_private_t *dev_priv = dev->dev_private;
6982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6983         int pipe = intel_crtc->pipe;
6984         int dpll_reg = DPLL(pipe);
6985         int dpll;
6986
6987         if (HAS_PCH_SPLIT(dev))
6988                 return;
6989
6990         if (!dev_priv->lvds_downclock_avail)
6991                 return;
6992
6993         dpll = I915_READ(dpll_reg);
6994         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6995                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6996
6997                 assert_panel_unlocked(dev_priv, pipe);
6998
6999                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7000                 I915_WRITE(dpll_reg, dpll);
7001                 intel_wait_for_vblank(dev, pipe);
7002
7003                 dpll = I915_READ(dpll_reg);
7004                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7005                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7006         }
7007 }
7008
7009 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7010 {
7011         struct drm_device *dev = crtc->dev;
7012         drm_i915_private_t *dev_priv = dev->dev_private;
7013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7014
7015         if (HAS_PCH_SPLIT(dev))
7016                 return;
7017
7018         if (!dev_priv->lvds_downclock_avail)
7019                 return;
7020
7021         /*
7022          * Since this is called by a timer, we should never get here in
7023          * the manual case.
7024          */
7025         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7026                 int pipe = intel_crtc->pipe;
7027                 int dpll_reg = DPLL(pipe);
7028                 int dpll;
7029
7030                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7031
7032                 assert_panel_unlocked(dev_priv, pipe);
7033
7034                 dpll = I915_READ(dpll_reg);
7035                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7036                 I915_WRITE(dpll_reg, dpll);
7037                 intel_wait_for_vblank(dev, pipe);
7038                 dpll = I915_READ(dpll_reg);
7039                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7040                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7041         }
7042
7043 }
7044
7045 void intel_mark_busy(struct drm_device *dev)
7046 {
7047         i915_update_gfx_val(dev->dev_private);
7048 }
7049
7050 void intel_mark_idle(struct drm_device *dev)
7051 {
7052         struct drm_crtc *crtc;
7053
7054         if (!i915_powersave)
7055                 return;
7056
7057         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7058                 if (!crtc->fb)
7059                         continue;
7060
7061                 intel_decrease_pllclock(crtc);
7062         }
7063 }
7064
7065 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7066 {
7067         struct drm_device *dev = obj->base.dev;
7068         struct drm_crtc *crtc;
7069
7070         if (!i915_powersave)
7071                 return;
7072
7073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7074                 if (!crtc->fb)
7075                         continue;
7076
7077                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7078                         intel_increase_pllclock(crtc);
7079         }
7080 }
7081
7082 static void intel_crtc_destroy(struct drm_crtc *crtc)
7083 {
7084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7085         struct drm_device *dev = crtc->dev;
7086         struct intel_unpin_work *work;
7087         unsigned long flags;
7088
7089         spin_lock_irqsave(&dev->event_lock, flags);
7090         work = intel_crtc->unpin_work;
7091         intel_crtc->unpin_work = NULL;
7092         spin_unlock_irqrestore(&dev->event_lock, flags);
7093
7094         if (work) {
7095                 cancel_work_sync(&work->work);
7096                 kfree(work);
7097         }
7098
7099         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7100
7101         drm_crtc_cleanup(crtc);
7102
7103         kfree(intel_crtc);
7104 }
7105
7106 static void intel_unpin_work_fn(struct work_struct *__work)
7107 {
7108         struct intel_unpin_work *work =
7109                 container_of(__work, struct intel_unpin_work, work);
7110         struct drm_device *dev = work->crtc->dev;
7111
7112         mutex_lock(&dev->struct_mutex);
7113         intel_unpin_fb_obj(work->old_fb_obj);
7114         drm_gem_object_unreference(&work->pending_flip_obj->base);
7115         drm_gem_object_unreference(&work->old_fb_obj->base);
7116
7117         intel_update_fbc(dev);
7118         mutex_unlock(&dev->struct_mutex);
7119
7120         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7121         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7122
7123         kfree(work);
7124 }
7125
7126 static void do_intel_finish_page_flip(struct drm_device *dev,
7127                                       struct drm_crtc *crtc)
7128 {
7129         drm_i915_private_t *dev_priv = dev->dev_private;
7130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7131         struct intel_unpin_work *work;
7132         unsigned long flags;
7133
7134         /* Ignore early vblank irqs */
7135         if (intel_crtc == NULL)
7136                 return;
7137
7138         spin_lock_irqsave(&dev->event_lock, flags);
7139         work = intel_crtc->unpin_work;
7140
7141         /* Ensure we don't miss a work->pending update ... */
7142         smp_rmb();
7143
7144         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7145                 spin_unlock_irqrestore(&dev->event_lock, flags);
7146                 return;
7147         }
7148
7149         /* and that the unpin work is consistent wrt ->pending. */
7150         smp_rmb();
7151
7152         intel_crtc->unpin_work = NULL;
7153
7154         if (work->event)
7155                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7156
7157         drm_vblank_put(dev, intel_crtc->pipe);
7158
7159         spin_unlock_irqrestore(&dev->event_lock, flags);
7160
7161         wake_up_all(&dev_priv->pending_flip_queue);
7162
7163         queue_work(dev_priv->wq, &work->work);
7164
7165         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7166 }
7167
7168 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7169 {
7170         drm_i915_private_t *dev_priv = dev->dev_private;
7171         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7172
7173         do_intel_finish_page_flip(dev, crtc);
7174 }
7175
7176 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7177 {
7178         drm_i915_private_t *dev_priv = dev->dev_private;
7179         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7180
7181         do_intel_finish_page_flip(dev, crtc);
7182 }
7183
7184 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7185 {
7186         drm_i915_private_t *dev_priv = dev->dev_private;
7187         struct intel_crtc *intel_crtc =
7188                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7189         unsigned long flags;
7190
7191         /* NB: An MMIO update of the plane base pointer will also
7192          * generate a page-flip completion irq, i.e. every modeset
7193          * is also accompanied by a spurious intel_prepare_page_flip().
7194          */
7195         spin_lock_irqsave(&dev->event_lock, flags);
7196         if (intel_crtc->unpin_work)
7197                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7198         spin_unlock_irqrestore(&dev->event_lock, flags);
7199 }
7200
7201 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7202 {
7203         /* Ensure that the work item is consistent when activating it ... */
7204         smp_wmb();
7205         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7206         /* and that it is marked active as soon as the irq could fire. */
7207         smp_wmb();
7208 }
7209
7210 static int intel_gen2_queue_flip(struct drm_device *dev,
7211                                  struct drm_crtc *crtc,
7212                                  struct drm_framebuffer *fb,
7213                                  struct drm_i915_gem_object *obj)
7214 {
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217         u32 flip_mask;
7218         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7219         int ret;
7220
7221         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7222         if (ret)
7223                 goto err;
7224
7225         ret = intel_ring_begin(ring, 6);
7226         if (ret)
7227                 goto err_unpin;
7228
7229         /* Can't queue multiple flips, so wait for the previous
7230          * one to finish before executing the next.
7231          */
7232         if (intel_crtc->plane)
7233                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7234         else
7235                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7236         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7237         intel_ring_emit(ring, MI_NOOP);
7238         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7239                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7240         intel_ring_emit(ring, fb->pitches[0]);
7241         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7242         intel_ring_emit(ring, 0); /* aux display base address, unused */
7243
7244         intel_mark_page_flip_active(intel_crtc);
7245         intel_ring_advance(ring);
7246         return 0;
7247
7248 err_unpin:
7249         intel_unpin_fb_obj(obj);
7250 err:
7251         return ret;
7252 }
7253
7254 static int intel_gen3_queue_flip(struct drm_device *dev,
7255                                  struct drm_crtc *crtc,
7256                                  struct drm_framebuffer *fb,
7257                                  struct drm_i915_gem_object *obj)
7258 {
7259         struct drm_i915_private *dev_priv = dev->dev_private;
7260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7261         u32 flip_mask;
7262         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7263         int ret;
7264
7265         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7266         if (ret)
7267                 goto err;
7268
7269         ret = intel_ring_begin(ring, 6);
7270         if (ret)
7271                 goto err_unpin;
7272
7273         if (intel_crtc->plane)
7274                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7275         else
7276                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7277         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7278         intel_ring_emit(ring, MI_NOOP);
7279         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7280                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7281         intel_ring_emit(ring, fb->pitches[0]);
7282         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7283         intel_ring_emit(ring, MI_NOOP);
7284
7285         intel_mark_page_flip_active(intel_crtc);
7286         intel_ring_advance(ring);
7287         return 0;
7288
7289 err_unpin:
7290         intel_unpin_fb_obj(obj);
7291 err:
7292         return ret;
7293 }
7294
7295 static int intel_gen4_queue_flip(struct drm_device *dev,
7296                                  struct drm_crtc *crtc,
7297                                  struct drm_framebuffer *fb,
7298                                  struct drm_i915_gem_object *obj)
7299 {
7300         struct drm_i915_private *dev_priv = dev->dev_private;
7301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7302         uint32_t pf, pipesrc;
7303         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7304         int ret;
7305
7306         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7307         if (ret)
7308                 goto err;
7309
7310         ret = intel_ring_begin(ring, 4);
7311         if (ret)
7312                 goto err_unpin;
7313
7314         /* i965+ uses the linear or tiled offsets from the
7315          * Display Registers (which do not change across a page-flip)
7316          * so we need only reprogram the base address.
7317          */
7318         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7319                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7320         intel_ring_emit(ring, fb->pitches[0]);
7321         intel_ring_emit(ring,
7322                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7323                         obj->tiling_mode);
7324
7325         /* XXX Enabling the panel-fitter across page-flip is so far
7326          * untested on non-native modes, so ignore it for now.
7327          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7328          */
7329         pf = 0;
7330         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7331         intel_ring_emit(ring, pf | pipesrc);
7332
7333         intel_mark_page_flip_active(intel_crtc);
7334         intel_ring_advance(ring);
7335         return 0;
7336
7337 err_unpin:
7338         intel_unpin_fb_obj(obj);
7339 err:
7340         return ret;
7341 }
7342
7343 static int intel_gen6_queue_flip(struct drm_device *dev,
7344                                  struct drm_crtc *crtc,
7345                                  struct drm_framebuffer *fb,
7346                                  struct drm_i915_gem_object *obj)
7347 {
7348         struct drm_i915_private *dev_priv = dev->dev_private;
7349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7350         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7351         uint32_t pf, pipesrc;
7352         int ret;
7353
7354         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7355         if (ret)
7356                 goto err;
7357
7358         ret = intel_ring_begin(ring, 4);
7359         if (ret)
7360                 goto err_unpin;
7361
7362         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7363                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7364         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7365         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7366
7367         /* Contrary to the suggestions in the documentation,
7368          * "Enable Panel Fitter" does not seem to be required when page
7369          * flipping with a non-native mode, and worse causes a normal
7370          * modeset to fail.
7371          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7372          */
7373         pf = 0;
7374         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7375         intel_ring_emit(ring, pf | pipesrc);
7376
7377         intel_mark_page_flip_active(intel_crtc);
7378         intel_ring_advance(ring);
7379         return 0;
7380
7381 err_unpin:
7382         intel_unpin_fb_obj(obj);
7383 err:
7384         return ret;
7385 }
7386
7387 /*
7388  * On gen7 we currently use the blit ring because (in early silicon at least)
7389  * the render ring doesn't give us interrpts for page flip completion, which
7390  * means clients will hang after the first flip is queued.  Fortunately the
7391  * blit ring generates interrupts properly, so use it instead.
7392  */
7393 static int intel_gen7_queue_flip(struct drm_device *dev,
7394                                  struct drm_crtc *crtc,
7395                                  struct drm_framebuffer *fb,
7396                                  struct drm_i915_gem_object *obj)
7397 {
7398         struct drm_i915_private *dev_priv = dev->dev_private;
7399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7400         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7401         uint32_t plane_bit = 0;
7402         int ret;
7403
7404         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7405         if (ret)
7406                 goto err;
7407
7408         switch(intel_crtc->plane) {
7409         case PLANE_A:
7410                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7411                 break;
7412         case PLANE_B:
7413                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7414                 break;
7415         case PLANE_C:
7416                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7417                 break;
7418         default:
7419                 WARN_ONCE(1, "unknown plane in flip command\n");
7420                 ret = -ENODEV;
7421                 goto err_unpin;
7422         }
7423
7424         ret = intel_ring_begin(ring, 4);
7425         if (ret)
7426                 goto err_unpin;
7427
7428         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7429         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7430         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7431         intel_ring_emit(ring, (MI_NOOP));
7432
7433         intel_mark_page_flip_active(intel_crtc);
7434         intel_ring_advance(ring);
7435         return 0;
7436
7437 err_unpin:
7438         intel_unpin_fb_obj(obj);
7439 err:
7440         return ret;
7441 }
7442
7443 static int intel_default_queue_flip(struct drm_device *dev,
7444                                     struct drm_crtc *crtc,
7445                                     struct drm_framebuffer *fb,
7446                                     struct drm_i915_gem_object *obj)
7447 {
7448         return -ENODEV;
7449 }
7450
7451 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7452                                 struct drm_framebuffer *fb,
7453                                 struct drm_pending_vblank_event *event)
7454 {
7455         struct drm_device *dev = crtc->dev;
7456         struct drm_i915_private *dev_priv = dev->dev_private;
7457         struct drm_framebuffer *old_fb = crtc->fb;
7458         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7460         struct intel_unpin_work *work;
7461         unsigned long flags;
7462         int ret;
7463
7464         /* Can't change pixel format via MI display flips. */
7465         if (fb->pixel_format != crtc->fb->pixel_format)
7466                 return -EINVAL;
7467
7468         /*
7469          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7470          * Note that pitch changes could also affect these register.
7471          */
7472         if (INTEL_INFO(dev)->gen > 3 &&
7473             (fb->offsets[0] != crtc->fb->offsets[0] ||
7474              fb->pitches[0] != crtc->fb->pitches[0]))
7475                 return -EINVAL;
7476
7477         work = kzalloc(sizeof *work, GFP_KERNEL);
7478         if (work == NULL)
7479                 return -ENOMEM;
7480
7481         work->event = event;
7482         work->crtc = crtc;
7483         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7484         INIT_WORK(&work->work, intel_unpin_work_fn);
7485
7486         ret = drm_vblank_get(dev, intel_crtc->pipe);
7487         if (ret)
7488                 goto free_work;
7489
7490         /* We borrow the event spin lock for protecting unpin_work */
7491         spin_lock_irqsave(&dev->event_lock, flags);
7492         if (intel_crtc->unpin_work) {
7493                 spin_unlock_irqrestore(&dev->event_lock, flags);
7494                 kfree(work);
7495                 drm_vblank_put(dev, intel_crtc->pipe);
7496
7497                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7498                 return -EBUSY;
7499         }
7500         intel_crtc->unpin_work = work;
7501         spin_unlock_irqrestore(&dev->event_lock, flags);
7502
7503         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7504                 flush_workqueue(dev_priv->wq);
7505
7506         ret = i915_mutex_lock_interruptible(dev);
7507         if (ret)
7508                 goto cleanup;
7509
7510         /* Reference the objects for the scheduled work. */
7511         drm_gem_object_reference(&work->old_fb_obj->base);
7512         drm_gem_object_reference(&obj->base);
7513
7514         crtc->fb = fb;
7515
7516         work->pending_flip_obj = obj;
7517
7518         work->enable_stall_check = true;
7519
7520         atomic_inc(&intel_crtc->unpin_work_count);
7521         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7522
7523         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7524         if (ret)
7525                 goto cleanup_pending;
7526
7527         intel_disable_fbc(dev);
7528         intel_mark_fb_busy(obj);
7529         mutex_unlock(&dev->struct_mutex);
7530
7531         trace_i915_flip_request(intel_crtc->plane, obj);
7532
7533         return 0;
7534
7535 cleanup_pending:
7536         atomic_dec(&intel_crtc->unpin_work_count);
7537         crtc->fb = old_fb;
7538         drm_gem_object_unreference(&work->old_fb_obj->base);
7539         drm_gem_object_unreference(&obj->base);
7540         mutex_unlock(&dev->struct_mutex);
7541
7542 cleanup:
7543         spin_lock_irqsave(&dev->event_lock, flags);
7544         intel_crtc->unpin_work = NULL;
7545         spin_unlock_irqrestore(&dev->event_lock, flags);
7546
7547         drm_vblank_put(dev, intel_crtc->pipe);
7548 free_work:
7549         kfree(work);
7550
7551         return ret;
7552 }
7553
7554 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7555         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7556         .load_lut = intel_crtc_load_lut,
7557 };
7558
7559 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7560 {
7561         struct intel_encoder *other_encoder;
7562         struct drm_crtc *crtc = &encoder->new_crtc->base;
7563
7564         if (WARN_ON(!crtc))
7565                 return false;
7566
7567         list_for_each_entry(other_encoder,
7568                             &crtc->dev->mode_config.encoder_list,
7569                             base.head) {
7570
7571                 if (&other_encoder->new_crtc->base != crtc ||
7572                     encoder == other_encoder)
7573                         continue;
7574                 else
7575                         return true;
7576         }
7577
7578         return false;
7579 }
7580
7581 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7582                                   struct drm_crtc *crtc)
7583 {
7584         struct drm_device *dev;
7585         struct drm_crtc *tmp;
7586         int crtc_mask = 1;
7587
7588         WARN(!crtc, "checking null crtc?\n");
7589
7590         dev = crtc->dev;
7591
7592         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7593                 if (tmp == crtc)
7594                         break;
7595                 crtc_mask <<= 1;
7596         }
7597
7598         if (encoder->possible_crtcs & crtc_mask)
7599                 return true;
7600         return false;
7601 }
7602
7603 /**
7604  * intel_modeset_update_staged_output_state
7605  *
7606  * Updates the staged output configuration state, e.g. after we've read out the
7607  * current hw state.
7608  */
7609 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7610 {
7611         struct intel_encoder *encoder;
7612         struct intel_connector *connector;
7613
7614         list_for_each_entry(connector, &dev->mode_config.connector_list,
7615                             base.head) {
7616                 connector->new_encoder =
7617                         to_intel_encoder(connector->base.encoder);
7618         }
7619
7620         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7621                             base.head) {
7622                 encoder->new_crtc =
7623                         to_intel_crtc(encoder->base.crtc);
7624         }
7625 }
7626
7627 /**
7628  * intel_modeset_commit_output_state
7629  *
7630  * This function copies the stage display pipe configuration to the real one.
7631  */
7632 static void intel_modeset_commit_output_state(struct drm_device *dev)
7633 {
7634         struct intel_encoder *encoder;
7635         struct intel_connector *connector;
7636
7637         list_for_each_entry(connector, &dev->mode_config.connector_list,
7638                             base.head) {
7639                 connector->base.encoder = &connector->new_encoder->base;
7640         }
7641
7642         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7643                             base.head) {
7644                 encoder->base.crtc = &encoder->new_crtc->base;
7645         }
7646 }
7647
7648 static void
7649 connected_sink_compute_bpp(struct intel_connector * connector,
7650                            struct intel_crtc_config *pipe_config)
7651 {
7652         int bpp = pipe_config->pipe_bpp;
7653
7654         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7655                 connector->base.base.id,
7656                 drm_get_connector_name(&connector->base));
7657
7658         /* Don't use an invalid EDID bpc value */
7659         if (connector->base.display_info.bpc &&
7660             connector->base.display_info.bpc * 3 < bpp) {
7661                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7662                               bpp, connector->base.display_info.bpc*3);
7663                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7664         }
7665
7666         /* Clamp bpp to 8 on screens without EDID 1.4 */
7667         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7668                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7669                               bpp);
7670                 pipe_config->pipe_bpp = 24;
7671         }
7672 }
7673
7674 static int
7675 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7676                           struct drm_framebuffer *fb,
7677                           struct intel_crtc_config *pipe_config)
7678 {
7679         struct drm_device *dev = crtc->base.dev;
7680         struct intel_connector *connector;
7681         int bpp;
7682
7683         switch (fb->pixel_format) {
7684         case DRM_FORMAT_C8:
7685                 bpp = 8*3; /* since we go through a colormap */
7686                 break;
7687         case DRM_FORMAT_XRGB1555:
7688         case DRM_FORMAT_ARGB1555:
7689                 /* checked in intel_framebuffer_init already */
7690                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7691                         return -EINVAL;
7692         case DRM_FORMAT_RGB565:
7693                 bpp = 6*3; /* min is 18bpp */
7694                 break;
7695         case DRM_FORMAT_XBGR8888:
7696         case DRM_FORMAT_ABGR8888:
7697                 /* checked in intel_framebuffer_init already */
7698                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7699                         return -EINVAL;
7700         case DRM_FORMAT_XRGB8888:
7701         case DRM_FORMAT_ARGB8888:
7702                 bpp = 8*3;
7703                 break;
7704         case DRM_FORMAT_XRGB2101010:
7705         case DRM_FORMAT_ARGB2101010:
7706         case DRM_FORMAT_XBGR2101010:
7707         case DRM_FORMAT_ABGR2101010:
7708                 /* checked in intel_framebuffer_init already */
7709                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7710                         return -EINVAL;
7711                 bpp = 10*3;
7712                 break;
7713         /* TODO: gen4+ supports 16 bpc floating point, too. */
7714         default:
7715                 DRM_DEBUG_KMS("unsupported depth\n");
7716                 return -EINVAL;
7717         }
7718
7719         pipe_config->pipe_bpp = bpp;
7720
7721         /* Clamp display bpp to EDID value */
7722         list_for_each_entry(connector, &dev->mode_config.connector_list,
7723                             base.head) {
7724                 if (!connector->new_encoder ||
7725                     connector->new_encoder->new_crtc != crtc)
7726                         continue;
7727
7728                 connected_sink_compute_bpp(connector, pipe_config);
7729         }
7730
7731         return bpp;
7732 }
7733
7734 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7735                                    struct intel_crtc_config *pipe_config,
7736                                    const char *context)
7737 {
7738         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7739                       context, pipe_name(crtc->pipe));
7740
7741         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7742         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7743                       pipe_config->pipe_bpp, pipe_config->dither);
7744         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7745                       pipe_config->has_pch_encoder,
7746                       pipe_config->fdi_lanes,
7747                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7748                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7749                       pipe_config->fdi_m_n.tu);
7750         DRM_DEBUG_KMS("requested mode:\n");
7751         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7752         DRM_DEBUG_KMS("adjusted mode:\n");
7753         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7754         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7755                       pipe_config->gmch_pfit.control,
7756                       pipe_config->gmch_pfit.pgm_ratios,
7757                       pipe_config->gmch_pfit.lvds_border_bits);
7758         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7759                       pipe_config->pch_pfit.pos,
7760                       pipe_config->pch_pfit.size);
7761         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7762 }
7763
7764 static struct intel_crtc_config *
7765 intel_modeset_pipe_config(struct drm_crtc *crtc,
7766                           struct drm_framebuffer *fb,
7767                           struct drm_display_mode *mode)
7768 {
7769         struct drm_device *dev = crtc->dev;
7770         struct drm_encoder_helper_funcs *encoder_funcs;
7771         struct intel_encoder *encoder;
7772         struct intel_crtc_config *pipe_config;
7773         int plane_bpp, ret = -EINVAL;
7774         bool retry = true;
7775
7776         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7777         if (!pipe_config)
7778                 return ERR_PTR(-ENOMEM);
7779
7780         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7781         drm_mode_copy(&pipe_config->requested_mode, mode);
7782         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7783
7784         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7785          * plane pixel format and any sink constraints into account. Returns the
7786          * source plane bpp so that dithering can be selected on mismatches
7787          * after encoders and crtc also have had their say. */
7788         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7789                                               fb, pipe_config);
7790         if (plane_bpp < 0)
7791                 goto fail;
7792
7793 encoder_retry:
7794         /* Ensure the port clock default is reset when retrying. */
7795         pipe_config->port_clock = 0;
7796
7797         /* Pass our mode to the connectors and the CRTC to give them a chance to
7798          * adjust it according to limitations or connector properties, and also
7799          * a chance to reject the mode entirely.
7800          */
7801         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7802                             base.head) {
7803
7804                 if (&encoder->new_crtc->base != crtc)
7805                         continue;
7806
7807                 if (encoder->compute_config) {
7808                         if (!(encoder->compute_config(encoder, pipe_config))) {
7809                                 DRM_DEBUG_KMS("Encoder config failure\n");
7810                                 goto fail;
7811                         }
7812
7813                         continue;
7814                 }
7815
7816                 encoder_funcs = encoder->base.helper_private;
7817                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7818                                                 &pipe_config->requested_mode,
7819                                                 &pipe_config->adjusted_mode))) {
7820                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7821                         goto fail;
7822                 }
7823         }
7824
7825         /* Set default port clock if not overwritten by the encoder. Needs to be
7826          * done afterwards in case the encoder adjusts the mode. */
7827         if (!pipe_config->port_clock)
7828                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7829
7830         ret = intel_crtc_compute_config(crtc, pipe_config);
7831         if (ret < 0) {
7832                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7833                 goto fail;
7834         }
7835
7836         if (ret == RETRY) {
7837                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7838                         ret = -EINVAL;
7839                         goto fail;
7840                 }
7841
7842                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7843                 retry = false;
7844                 goto encoder_retry;
7845         }
7846
7847         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7848         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7849                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7850
7851         return pipe_config;
7852 fail:
7853         kfree(pipe_config);
7854         return ERR_PTR(ret);
7855 }
7856
7857 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7858  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7859 static void
7860 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7861                              unsigned *prepare_pipes, unsigned *disable_pipes)
7862 {
7863         struct intel_crtc *intel_crtc;
7864         struct drm_device *dev = crtc->dev;
7865         struct intel_encoder *encoder;
7866         struct intel_connector *connector;
7867         struct drm_crtc *tmp_crtc;
7868
7869         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7870
7871         /* Check which crtcs have changed outputs connected to them, these need
7872          * to be part of the prepare_pipes mask. We don't (yet) support global
7873          * modeset across multiple crtcs, so modeset_pipes will only have one
7874          * bit set at most. */
7875         list_for_each_entry(connector, &dev->mode_config.connector_list,
7876                             base.head) {
7877                 if (connector->base.encoder == &connector->new_encoder->base)
7878                         continue;
7879
7880                 if (connector->base.encoder) {
7881                         tmp_crtc = connector->base.encoder->crtc;
7882
7883                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7884                 }
7885
7886                 if (connector->new_encoder)
7887                         *prepare_pipes |=
7888                                 1 << connector->new_encoder->new_crtc->pipe;
7889         }
7890
7891         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7892                             base.head) {
7893                 if (encoder->base.crtc == &encoder->new_crtc->base)
7894                         continue;
7895
7896                 if (encoder->base.crtc) {
7897                         tmp_crtc = encoder->base.crtc;
7898
7899                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7900                 }
7901
7902                 if (encoder->new_crtc)
7903                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7904         }
7905
7906         /* Check for any pipes that will be fully disabled ... */
7907         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7908                             base.head) {
7909                 bool used = false;
7910
7911                 /* Don't try to disable disabled crtcs. */
7912                 if (!intel_crtc->base.enabled)
7913                         continue;
7914
7915                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7916                                     base.head) {
7917                         if (encoder->new_crtc == intel_crtc)
7918                                 used = true;
7919                 }
7920
7921                 if (!used)
7922                         *disable_pipes |= 1 << intel_crtc->pipe;
7923         }
7924
7925
7926         /* set_mode is also used to update properties on life display pipes. */
7927         intel_crtc = to_intel_crtc(crtc);
7928         if (crtc->enabled)
7929                 *prepare_pipes |= 1 << intel_crtc->pipe;
7930
7931         /*
7932          * For simplicity do a full modeset on any pipe where the output routing
7933          * changed. We could be more clever, but that would require us to be
7934          * more careful with calling the relevant encoder->mode_set functions.
7935          */
7936         if (*prepare_pipes)
7937                 *modeset_pipes = *prepare_pipes;
7938
7939         /* ... and mask these out. */
7940         *modeset_pipes &= ~(*disable_pipes);
7941         *prepare_pipes &= ~(*disable_pipes);
7942
7943         /*
7944          * HACK: We don't (yet) fully support global modesets. intel_set_config
7945          * obies this rule, but the modeset restore mode of
7946          * intel_modeset_setup_hw_state does not.
7947          */
7948         *modeset_pipes &= 1 << intel_crtc->pipe;
7949         *prepare_pipes &= 1 << intel_crtc->pipe;
7950
7951         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7952                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7953 }
7954
7955 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7956 {
7957         struct drm_encoder *encoder;
7958         struct drm_device *dev = crtc->dev;
7959
7960         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7961                 if (encoder->crtc == crtc)
7962                         return true;
7963
7964         return false;
7965 }
7966
7967 static void
7968 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7969 {
7970         struct intel_encoder *intel_encoder;
7971         struct intel_crtc *intel_crtc;
7972         struct drm_connector *connector;
7973
7974         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7975                             base.head) {
7976                 if (!intel_encoder->base.crtc)
7977                         continue;
7978
7979                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7980
7981                 if (prepare_pipes & (1 << intel_crtc->pipe))
7982                         intel_encoder->connectors_active = false;
7983         }
7984
7985         intel_modeset_commit_output_state(dev);
7986
7987         /* Update computed state. */
7988         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7989                             base.head) {
7990                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7991         }
7992
7993         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7994                 if (!connector->encoder || !connector->encoder->crtc)
7995                         continue;
7996
7997                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7998
7999                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8000                         struct drm_property *dpms_property =
8001                                 dev->mode_config.dpms_property;
8002
8003                         connector->dpms = DRM_MODE_DPMS_ON;
8004                         drm_object_property_set_value(&connector->base,
8005                                                          dpms_property,
8006                                                          DRM_MODE_DPMS_ON);
8007
8008                         intel_encoder = to_intel_encoder(connector->encoder);
8009                         intel_encoder->connectors_active = true;
8010                 }
8011         }
8012
8013 }
8014
8015 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8016         list_for_each_entry((intel_crtc), \
8017                             &(dev)->mode_config.crtc_list, \
8018                             base.head) \
8019                 if (mask & (1 <<(intel_crtc)->pipe))
8020
8021 static bool
8022 intel_pipe_config_compare(struct drm_device *dev,
8023                           struct intel_crtc_config *current_config,
8024                           struct intel_crtc_config *pipe_config)
8025 {
8026 #define PIPE_CONF_CHECK_I(name) \
8027         if (current_config->name != pipe_config->name) { \
8028                 DRM_ERROR("mismatch in " #name " " \
8029                           "(expected %i, found %i)\n", \
8030                           current_config->name, \
8031                           pipe_config->name); \
8032                 return false; \
8033         }
8034
8035 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8036         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8037                 DRM_ERROR("mismatch in " #name " " \
8038                           "(expected %i, found %i)\n", \
8039                           current_config->name & (mask), \
8040                           pipe_config->name & (mask)); \
8041                 return false; \
8042         }
8043
8044         PIPE_CONF_CHECK_I(cpu_transcoder);
8045
8046         PIPE_CONF_CHECK_I(has_pch_encoder);
8047         PIPE_CONF_CHECK_I(fdi_lanes);
8048         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8049         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8050         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8051         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8052         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8053
8054         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8055         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8056         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8057         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8058         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8059         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8060
8061         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8062         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8063         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8064         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8065         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8066         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8067
8068         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8069                               DRM_MODE_FLAG_INTERLACE);
8070
8071         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8072                               DRM_MODE_FLAG_PHSYNC);
8073         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8074                               DRM_MODE_FLAG_NHSYNC);
8075         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8076                               DRM_MODE_FLAG_PVSYNC);
8077         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8078                               DRM_MODE_FLAG_NVSYNC);
8079
8080         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8081         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8082
8083         PIPE_CONF_CHECK_I(gmch_pfit.control);
8084         /* pfit ratios are autocomputed by the hw on gen4+ */
8085         if (INTEL_INFO(dev)->gen < 4)
8086                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8087         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8088         PIPE_CONF_CHECK_I(pch_pfit.pos);
8089         PIPE_CONF_CHECK_I(pch_pfit.size);
8090
8091         PIPE_CONF_CHECK_I(ips_enabled);
8092
8093 #undef PIPE_CONF_CHECK_I
8094 #undef PIPE_CONF_CHECK_FLAGS
8095
8096         return true;
8097 }
8098
8099 void
8100 intel_modeset_check_state(struct drm_device *dev)
8101 {
8102         drm_i915_private_t *dev_priv = dev->dev_private;
8103         struct intel_crtc *crtc;
8104         struct intel_encoder *encoder;
8105         struct intel_connector *connector;
8106         struct intel_crtc_config pipe_config;
8107
8108         list_for_each_entry(connector, &dev->mode_config.connector_list,
8109                             base.head) {
8110                 /* This also checks the encoder/connector hw state with the
8111                  * ->get_hw_state callbacks. */
8112                 intel_connector_check_state(connector);
8113
8114                 WARN(&connector->new_encoder->base != connector->base.encoder,
8115                      "connector's staged encoder doesn't match current encoder\n");
8116         }
8117
8118         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8119                             base.head) {
8120                 bool enabled = false;
8121                 bool active = false;
8122                 enum pipe pipe, tracked_pipe;
8123
8124                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8125                               encoder->base.base.id,
8126                               drm_get_encoder_name(&encoder->base));
8127
8128                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8129                      "encoder's stage crtc doesn't match current crtc\n");
8130                 WARN(encoder->connectors_active && !encoder->base.crtc,
8131                      "encoder's active_connectors set, but no crtc\n");
8132
8133                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8134                                     base.head) {
8135                         if (connector->base.encoder != &encoder->base)
8136                                 continue;
8137                         enabled = true;
8138                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8139                                 active = true;
8140                 }
8141                 WARN(!!encoder->base.crtc != enabled,
8142                      "encoder's enabled state mismatch "
8143                      "(expected %i, found %i)\n",
8144                      !!encoder->base.crtc, enabled);
8145                 WARN(active && !encoder->base.crtc,
8146                      "active encoder with no crtc\n");
8147
8148                 WARN(encoder->connectors_active != active,
8149                      "encoder's computed active state doesn't match tracked active state "
8150                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8151
8152                 active = encoder->get_hw_state(encoder, &pipe);
8153                 WARN(active != encoder->connectors_active,
8154                      "encoder's hw state doesn't match sw tracking "
8155                      "(expected %i, found %i)\n",
8156                      encoder->connectors_active, active);
8157
8158                 if (!encoder->base.crtc)
8159                         continue;
8160
8161                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8162                 WARN(active && pipe != tracked_pipe,
8163                      "active encoder's pipe doesn't match"
8164                      "(expected %i, found %i)\n",
8165                      tracked_pipe, pipe);
8166
8167         }
8168
8169         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8170                             base.head) {
8171                 bool enabled = false;
8172                 bool active = false;
8173
8174                 memset(&pipe_config, 0, sizeof(pipe_config));
8175
8176                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8177                               crtc->base.base.id);
8178
8179                 WARN(crtc->active && !crtc->base.enabled,
8180                      "active crtc, but not enabled in sw tracking\n");
8181
8182                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8183                                     base.head) {
8184                         if (encoder->base.crtc != &crtc->base)
8185                                 continue;
8186                         enabled = true;
8187                         if (encoder->connectors_active)
8188                                 active = true;
8189                         if (encoder->get_config)
8190                                 encoder->get_config(encoder, &pipe_config);
8191                 }
8192                 WARN(active != crtc->active,
8193                      "crtc's computed active state doesn't match tracked active state "
8194                      "(expected %i, found %i)\n", active, crtc->active);
8195                 WARN(enabled != crtc->base.enabled,
8196                      "crtc's computed enabled state doesn't match tracked enabled state "
8197                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8198
8199                 active = dev_priv->display.get_pipe_config(crtc,
8200                                                            &pipe_config);
8201                 WARN(crtc->active != active,
8202                      "crtc active state doesn't match with hw state "
8203                      "(expected %i, found %i)\n", crtc->active, active);
8204
8205                 if (active &&
8206                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8207                         WARN(1, "pipe state doesn't match!\n");
8208                         intel_dump_pipe_config(crtc, &pipe_config,
8209                                                "[hw state]");
8210                         intel_dump_pipe_config(crtc, &crtc->config,
8211                                                "[sw state]");
8212                 }
8213         }
8214 }
8215
8216 static int __intel_set_mode(struct drm_crtc *crtc,
8217                             struct drm_display_mode *mode,
8218                             int x, int y, struct drm_framebuffer *fb)
8219 {
8220         struct drm_device *dev = crtc->dev;
8221         drm_i915_private_t *dev_priv = dev->dev_private;
8222         struct drm_display_mode *saved_mode, *saved_hwmode;
8223         struct intel_crtc_config *pipe_config = NULL;
8224         struct intel_crtc *intel_crtc;
8225         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8226         int ret = 0;
8227
8228         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8229         if (!saved_mode)
8230                 return -ENOMEM;
8231         saved_hwmode = saved_mode + 1;
8232
8233         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8234                                      &prepare_pipes, &disable_pipes);
8235
8236         *saved_hwmode = crtc->hwmode;
8237         *saved_mode = crtc->mode;
8238
8239         /* Hack: Because we don't (yet) support global modeset on multiple
8240          * crtcs, we don't keep track of the new mode for more than one crtc.
8241          * Hence simply check whether any bit is set in modeset_pipes in all the
8242          * pieces of code that are not yet converted to deal with mutliple crtcs
8243          * changing their mode at the same time. */
8244         if (modeset_pipes) {
8245                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8246                 if (IS_ERR(pipe_config)) {
8247                         ret = PTR_ERR(pipe_config);
8248                         pipe_config = NULL;
8249
8250                         goto out;
8251                 }
8252                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8253                                        "[modeset]");
8254         }
8255
8256         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8257                 intel_crtc_disable(&intel_crtc->base);
8258
8259         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8260                 if (intel_crtc->base.enabled)
8261                         dev_priv->display.crtc_disable(&intel_crtc->base);
8262         }
8263
8264         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8265          * to set it here already despite that we pass it down the callchain.
8266          */
8267         if (modeset_pipes) {
8268                 crtc->mode = *mode;
8269                 /* mode_set/enable/disable functions rely on a correct pipe
8270                  * config. */
8271                 to_intel_crtc(crtc)->config = *pipe_config;
8272         }
8273
8274         /* Only after disabling all output pipelines that will be changed can we
8275          * update the the output configuration. */
8276         intel_modeset_update_state(dev, prepare_pipes);
8277
8278         if (dev_priv->display.modeset_global_resources)
8279                 dev_priv->display.modeset_global_resources(dev);
8280
8281         /* Set up the DPLL and any encoders state that needs to adjust or depend
8282          * on the DPLL.
8283          */
8284         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8285                 ret = intel_crtc_mode_set(&intel_crtc->base,
8286                                           x, y, fb);
8287                 if (ret)
8288                         goto done;
8289         }
8290
8291         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8292         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8293                 dev_priv->display.crtc_enable(&intel_crtc->base);
8294
8295         if (modeset_pipes) {
8296                 /* Store real post-adjustment hardware mode. */
8297                 crtc->hwmode = pipe_config->adjusted_mode;
8298
8299                 /* Calculate and store various constants which
8300                  * are later needed by vblank and swap-completion
8301                  * timestamping. They are derived from true hwmode.
8302                  */
8303                 drm_calc_timestamping_constants(crtc);
8304         }
8305
8306         /* FIXME: add subpixel order */
8307 done:
8308         if (ret && crtc->enabled) {
8309                 crtc->hwmode = *saved_hwmode;
8310                 crtc->mode = *saved_mode;
8311         }
8312
8313 out:
8314         kfree(pipe_config);
8315         kfree(saved_mode);
8316         return ret;
8317 }
8318
8319 int intel_set_mode(struct drm_crtc *crtc,
8320                      struct drm_display_mode *mode,
8321                      int x, int y, struct drm_framebuffer *fb)
8322 {
8323         int ret;
8324
8325         ret = __intel_set_mode(crtc, mode, x, y, fb);
8326
8327         if (ret == 0)
8328                 intel_modeset_check_state(crtc->dev);
8329
8330         return ret;
8331 }
8332
8333 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8334 {
8335         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8336 }
8337
8338 #undef for_each_intel_crtc_masked
8339
8340 static void intel_set_config_free(struct intel_set_config *config)
8341 {
8342         if (!config)
8343                 return;
8344
8345         kfree(config->save_connector_encoders);
8346         kfree(config->save_encoder_crtcs);
8347         kfree(config);
8348 }
8349
8350 static int intel_set_config_save_state(struct drm_device *dev,
8351                                        struct intel_set_config *config)
8352 {
8353         struct drm_encoder *encoder;
8354         struct drm_connector *connector;
8355         int count;
8356
8357         config->save_encoder_crtcs =
8358                 kcalloc(dev->mode_config.num_encoder,
8359                         sizeof(struct drm_crtc *), GFP_KERNEL);
8360         if (!config->save_encoder_crtcs)
8361                 return -ENOMEM;
8362
8363         config->save_connector_encoders =
8364                 kcalloc(dev->mode_config.num_connector,
8365                         sizeof(struct drm_encoder *), GFP_KERNEL);
8366         if (!config->save_connector_encoders)
8367                 return -ENOMEM;
8368
8369         /* Copy data. Note that driver private data is not affected.
8370          * Should anything bad happen only the expected state is
8371          * restored, not the drivers personal bookkeeping.
8372          */
8373         count = 0;
8374         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8375                 config->save_encoder_crtcs[count++] = encoder->crtc;
8376         }
8377
8378         count = 0;
8379         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8380                 config->save_connector_encoders[count++] = connector->encoder;
8381         }
8382
8383         return 0;
8384 }
8385
8386 static void intel_set_config_restore_state(struct drm_device *dev,
8387                                            struct intel_set_config *config)
8388 {
8389         struct intel_encoder *encoder;
8390         struct intel_connector *connector;
8391         int count;
8392
8393         count = 0;
8394         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8395                 encoder->new_crtc =
8396                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8397         }
8398
8399         count = 0;
8400         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8401                 connector->new_encoder =
8402                         to_intel_encoder(config->save_connector_encoders[count++]);
8403         }
8404 }
8405
8406 static void
8407 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8408                                       struct intel_set_config *config)
8409 {
8410
8411         /* We should be able to check here if the fb has the same properties
8412          * and then just flip_or_move it */
8413         if (set->crtc->fb != set->fb) {
8414                 /* If we have no fb then treat it as a full mode set */
8415                 if (set->crtc->fb == NULL) {
8416                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8417                         config->mode_changed = true;
8418                 } else if (set->fb == NULL) {
8419                         config->mode_changed = true;
8420                 } else if (set->fb->pixel_format !=
8421                            set->crtc->fb->pixel_format) {
8422                         config->mode_changed = true;
8423                 } else
8424                         config->fb_changed = true;
8425         }
8426
8427         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8428                 config->fb_changed = true;
8429
8430         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8431                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8432                 drm_mode_debug_printmodeline(&set->crtc->mode);
8433                 drm_mode_debug_printmodeline(set->mode);
8434                 config->mode_changed = true;
8435         }
8436 }
8437
8438 static int
8439 intel_modeset_stage_output_state(struct drm_device *dev,
8440                                  struct drm_mode_set *set,
8441                                  struct intel_set_config *config)
8442 {
8443         struct drm_crtc *new_crtc;
8444         struct intel_connector *connector;
8445         struct intel_encoder *encoder;
8446         int count, ro;
8447
8448         /* The upper layers ensure that we either disable a crtc or have a list
8449          * of connectors. For paranoia, double-check this. */
8450         WARN_ON(!set->fb && (set->num_connectors != 0));
8451         WARN_ON(set->fb && (set->num_connectors == 0));
8452
8453         count = 0;
8454         list_for_each_entry(connector, &dev->mode_config.connector_list,
8455                             base.head) {
8456                 /* Otherwise traverse passed in connector list and get encoders
8457                  * for them. */
8458                 for (ro = 0; ro < set->num_connectors; ro++) {
8459                         if (set->connectors[ro] == &connector->base) {
8460                                 connector->new_encoder = connector->encoder;
8461                                 break;
8462                         }
8463                 }
8464
8465                 /* If we disable the crtc, disable all its connectors. Also, if
8466                  * the connector is on the changing crtc but not on the new
8467                  * connector list, disable it. */
8468                 if ((!set->fb || ro == set->num_connectors) &&
8469                     connector->base.encoder &&
8470                     connector->base.encoder->crtc == set->crtc) {
8471                         connector->new_encoder = NULL;
8472
8473                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8474                                 connector->base.base.id,
8475                                 drm_get_connector_name(&connector->base));
8476                 }
8477
8478
8479                 if (&connector->new_encoder->base != connector->base.encoder) {
8480                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8481                         config->mode_changed = true;
8482                 }
8483         }
8484         /* connector->new_encoder is now updated for all connectors. */
8485
8486         /* Update crtc of enabled connectors. */
8487         count = 0;
8488         list_for_each_entry(connector, &dev->mode_config.connector_list,
8489                             base.head) {
8490                 if (!connector->new_encoder)
8491                         continue;
8492
8493                 new_crtc = connector->new_encoder->base.crtc;
8494
8495                 for (ro = 0; ro < set->num_connectors; ro++) {
8496                         if (set->connectors[ro] == &connector->base)
8497                                 new_crtc = set->crtc;
8498                 }
8499
8500                 /* Make sure the new CRTC will work with the encoder */
8501                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8502                                            new_crtc)) {
8503                         return -EINVAL;
8504                 }
8505                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8506
8507                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8508                         connector->base.base.id,
8509                         drm_get_connector_name(&connector->base),
8510                         new_crtc->base.id);
8511         }
8512
8513         /* Check for any encoders that needs to be disabled. */
8514         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8515                             base.head) {
8516                 list_for_each_entry(connector,
8517                                     &dev->mode_config.connector_list,
8518                                     base.head) {
8519                         if (connector->new_encoder == encoder) {
8520                                 WARN_ON(!connector->new_encoder->new_crtc);
8521
8522                                 goto next_encoder;
8523                         }
8524                 }
8525                 encoder->new_crtc = NULL;
8526 next_encoder:
8527                 /* Only now check for crtc changes so we don't miss encoders
8528                  * that will be disabled. */
8529                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8530                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8531                         config->mode_changed = true;
8532                 }
8533         }
8534         /* Now we've also updated encoder->new_crtc for all encoders. */
8535
8536         return 0;
8537 }
8538
8539 static int intel_crtc_set_config(struct drm_mode_set *set)
8540 {
8541         struct drm_device *dev;
8542         struct drm_mode_set save_set;
8543         struct intel_set_config *config;
8544         int ret;
8545
8546         BUG_ON(!set);
8547         BUG_ON(!set->crtc);
8548         BUG_ON(!set->crtc->helper_private);
8549
8550         /* Enforce sane interface api - has been abused by the fb helper. */
8551         BUG_ON(!set->mode && set->fb);
8552         BUG_ON(set->fb && set->num_connectors == 0);
8553
8554         if (set->fb) {
8555                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8556                                 set->crtc->base.id, set->fb->base.id,
8557                                 (int)set->num_connectors, set->x, set->y);
8558         } else {
8559                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8560         }
8561
8562         dev = set->crtc->dev;
8563
8564         ret = -ENOMEM;
8565         config = kzalloc(sizeof(*config), GFP_KERNEL);
8566         if (!config)
8567                 goto out_config;
8568
8569         ret = intel_set_config_save_state(dev, config);
8570         if (ret)
8571                 goto out_config;
8572
8573         save_set.crtc = set->crtc;
8574         save_set.mode = &set->crtc->mode;
8575         save_set.x = set->crtc->x;
8576         save_set.y = set->crtc->y;
8577         save_set.fb = set->crtc->fb;
8578
8579         /* Compute whether we need a full modeset, only an fb base update or no
8580          * change at all. In the future we might also check whether only the
8581          * mode changed, e.g. for LVDS where we only change the panel fitter in
8582          * such cases. */
8583         intel_set_config_compute_mode_changes(set, config);
8584
8585         ret = intel_modeset_stage_output_state(dev, set, config);
8586         if (ret)
8587                 goto fail;
8588
8589         if (config->mode_changed) {
8590                 ret = intel_set_mode(set->crtc, set->mode,
8591                                      set->x, set->y, set->fb);
8592                 if (ret) {
8593                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8594                                   set->crtc->base.id, ret);
8595                         goto fail;
8596                 }
8597         } else if (config->fb_changed) {
8598                 intel_crtc_wait_for_pending_flips(set->crtc);
8599
8600                 ret = intel_pipe_set_base(set->crtc,
8601                                           set->x, set->y, set->fb);
8602         }
8603
8604         intel_set_config_free(config);
8605
8606         return 0;
8607
8608 fail:
8609         intel_set_config_restore_state(dev, config);
8610
8611         /* Try to restore the config */
8612         if (config->mode_changed &&
8613             intel_set_mode(save_set.crtc, save_set.mode,
8614                            save_set.x, save_set.y, save_set.fb))
8615                 DRM_ERROR("failed to restore config after modeset failure\n");
8616
8617 out_config:
8618         intel_set_config_free(config);
8619         return ret;
8620 }
8621
8622 static const struct drm_crtc_funcs intel_crtc_funcs = {
8623         .cursor_set = intel_crtc_cursor_set,
8624         .cursor_move = intel_crtc_cursor_move,
8625         .gamma_set = intel_crtc_gamma_set,
8626         .set_config = intel_crtc_set_config,
8627         .destroy = intel_crtc_destroy,
8628         .page_flip = intel_crtc_page_flip,
8629 };
8630
8631 static void intel_cpu_pll_init(struct drm_device *dev)
8632 {
8633         if (HAS_DDI(dev))
8634                 intel_ddi_pll_init(dev);
8635 }
8636
8637 static void intel_pch_pll_init(struct drm_device *dev)
8638 {
8639         drm_i915_private_t *dev_priv = dev->dev_private;
8640         int i;
8641
8642         if (dev_priv->num_pch_pll == 0) {
8643                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8644                 return;
8645         }
8646
8647         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8648                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8649                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8650                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8651         }
8652 }
8653
8654 static void intel_crtc_init(struct drm_device *dev, int pipe)
8655 {
8656         drm_i915_private_t *dev_priv = dev->dev_private;
8657         struct intel_crtc *intel_crtc;
8658         int i;
8659
8660         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8661         if (intel_crtc == NULL)
8662                 return;
8663
8664         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8665
8666         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8667         for (i = 0; i < 256; i++) {
8668                 intel_crtc->lut_r[i] = i;
8669                 intel_crtc->lut_g[i] = i;
8670                 intel_crtc->lut_b[i] = i;
8671         }
8672
8673         /* Swap pipes & planes for FBC on pre-965 */
8674         intel_crtc->pipe = pipe;
8675         intel_crtc->plane = pipe;
8676         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8677                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8678                 intel_crtc->plane = !pipe;
8679         }
8680
8681         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8682                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8683         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8684         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8685
8686         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8687 }
8688
8689 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8690                                 struct drm_file *file)
8691 {
8692         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8693         struct drm_mode_object *drmmode_obj;
8694         struct intel_crtc *crtc;
8695
8696         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8697                 return -ENODEV;
8698
8699         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8700                         DRM_MODE_OBJECT_CRTC);
8701
8702         if (!drmmode_obj) {
8703                 DRM_ERROR("no such CRTC id\n");
8704                 return -EINVAL;
8705         }
8706
8707         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8708         pipe_from_crtc_id->pipe = crtc->pipe;
8709
8710         return 0;
8711 }
8712
8713 static int intel_encoder_clones(struct intel_encoder *encoder)
8714 {
8715         struct drm_device *dev = encoder->base.dev;
8716         struct intel_encoder *source_encoder;
8717         int index_mask = 0;
8718         int entry = 0;
8719
8720         list_for_each_entry(source_encoder,
8721                             &dev->mode_config.encoder_list, base.head) {
8722
8723                 if (encoder == source_encoder)
8724                         index_mask |= (1 << entry);
8725
8726                 /* Intel hw has only one MUX where enocoders could be cloned. */
8727                 if (encoder->cloneable && source_encoder->cloneable)
8728                         index_mask |= (1 << entry);
8729
8730                 entry++;
8731         }
8732
8733         return index_mask;
8734 }
8735
8736 static bool has_edp_a(struct drm_device *dev)
8737 {
8738         struct drm_i915_private *dev_priv = dev->dev_private;
8739
8740         if (!IS_MOBILE(dev))
8741                 return false;
8742
8743         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8744                 return false;
8745
8746         if (IS_GEN5(dev) &&
8747             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8748                 return false;
8749
8750         return true;
8751 }
8752
8753 static void intel_setup_outputs(struct drm_device *dev)
8754 {
8755         struct drm_i915_private *dev_priv = dev->dev_private;
8756         struct intel_encoder *encoder;
8757         bool dpd_is_edp = false;
8758         bool has_lvds;
8759
8760         has_lvds = intel_lvds_init(dev);
8761         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8762                 /* disable the panel fitter on everything but LVDS */
8763                 I915_WRITE(PFIT_CONTROL, 0);
8764         }
8765
8766         if (!IS_ULT(dev))
8767                 intel_crt_init(dev);
8768
8769         if (HAS_DDI(dev)) {
8770                 int found;
8771
8772                 /* Haswell uses DDI functions to detect digital outputs */
8773                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8774                 /* DDI A only supports eDP */
8775                 if (found)
8776                         intel_ddi_init(dev, PORT_A);
8777
8778                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8779                  * register */
8780                 found = I915_READ(SFUSE_STRAP);
8781
8782                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8783                         intel_ddi_init(dev, PORT_B);
8784                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8785                         intel_ddi_init(dev, PORT_C);
8786                 if (found & SFUSE_STRAP_DDID_DETECTED)
8787                         intel_ddi_init(dev, PORT_D);
8788         } else if (HAS_PCH_SPLIT(dev)) {
8789                 int found;
8790                 dpd_is_edp = intel_dpd_is_edp(dev);
8791
8792                 if (has_edp_a(dev))
8793                         intel_dp_init(dev, DP_A, PORT_A);
8794
8795                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8796                         /* PCH SDVOB multiplex with HDMIB */
8797                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8798                         if (!found)
8799                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8800                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8801                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8802                 }
8803
8804                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8805                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8806
8807                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8808                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8809
8810                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8811                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8812
8813                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8814                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8815         } else if (IS_VALLEYVIEW(dev)) {
8816                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8817                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8818                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8819
8820                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8821                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8822                                         PORT_B);
8823                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8824                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8825                 }
8826         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8827                 bool found = false;
8828
8829                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8830                         DRM_DEBUG_KMS("probing SDVOB\n");
8831                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8832                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8833                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8834                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8835                         }
8836
8837                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8838                                 intel_dp_init(dev, DP_B, PORT_B);
8839                 }
8840
8841                 /* Before G4X SDVOC doesn't have its own detect register */
8842
8843                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8844                         DRM_DEBUG_KMS("probing SDVOC\n");
8845                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8846                 }
8847
8848                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8849
8850                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8851                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8852                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8853                         }
8854                         if (SUPPORTS_INTEGRATED_DP(dev))
8855                                 intel_dp_init(dev, DP_C, PORT_C);
8856                 }
8857
8858                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8859                     (I915_READ(DP_D) & DP_DETECTED))
8860                         intel_dp_init(dev, DP_D, PORT_D);
8861         } else if (IS_GEN2(dev))
8862                 intel_dvo_init(dev);
8863
8864         if (SUPPORTS_TV(dev))
8865                 intel_tv_init(dev);
8866
8867         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8868                 encoder->base.possible_crtcs = encoder->crtc_mask;
8869                 encoder->base.possible_clones =
8870                         intel_encoder_clones(encoder);
8871         }
8872
8873         intel_init_pch_refclk(dev);
8874
8875         drm_helper_move_panel_connectors_to_head(dev);
8876 }
8877
8878 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8879 {
8880         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8881
8882         drm_framebuffer_cleanup(fb);
8883         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8884
8885         kfree(intel_fb);
8886 }
8887
8888 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8889                                                 struct drm_file *file,
8890                                                 unsigned int *handle)
8891 {
8892         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8893         struct drm_i915_gem_object *obj = intel_fb->obj;
8894
8895         return drm_gem_handle_create(file, &obj->base, handle);
8896 }
8897
8898 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8899         .destroy = intel_user_framebuffer_destroy,
8900         .create_handle = intel_user_framebuffer_create_handle,
8901 };
8902
8903 int intel_framebuffer_init(struct drm_device *dev,
8904                            struct intel_framebuffer *intel_fb,
8905                            struct drm_mode_fb_cmd2 *mode_cmd,
8906                            struct drm_i915_gem_object *obj)
8907 {
8908         int ret;
8909
8910         if (obj->tiling_mode == I915_TILING_Y) {
8911                 DRM_DEBUG("hardware does not support tiling Y\n");
8912                 return -EINVAL;
8913         }
8914
8915         if (mode_cmd->pitches[0] & 63) {
8916                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8917                           mode_cmd->pitches[0]);
8918                 return -EINVAL;
8919         }
8920
8921         /* FIXME <= Gen4 stride limits are bit unclear */
8922         if (mode_cmd->pitches[0] > 32768) {
8923                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8924                           mode_cmd->pitches[0]);
8925                 return -EINVAL;
8926         }
8927
8928         if (obj->tiling_mode != I915_TILING_NONE &&
8929             mode_cmd->pitches[0] != obj->stride) {
8930                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8931                           mode_cmd->pitches[0], obj->stride);
8932                 return -EINVAL;
8933         }
8934
8935         /* Reject formats not supported by any plane early. */
8936         switch (mode_cmd->pixel_format) {
8937         case DRM_FORMAT_C8:
8938         case DRM_FORMAT_RGB565:
8939         case DRM_FORMAT_XRGB8888:
8940         case DRM_FORMAT_ARGB8888:
8941                 break;
8942         case DRM_FORMAT_XRGB1555:
8943         case DRM_FORMAT_ARGB1555:
8944                 if (INTEL_INFO(dev)->gen > 3) {
8945                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8946                         return -EINVAL;
8947                 }
8948                 break;
8949         case DRM_FORMAT_XBGR8888:
8950         case DRM_FORMAT_ABGR8888:
8951         case DRM_FORMAT_XRGB2101010:
8952         case DRM_FORMAT_ARGB2101010:
8953         case DRM_FORMAT_XBGR2101010:
8954         case DRM_FORMAT_ABGR2101010:
8955                 if (INTEL_INFO(dev)->gen < 4) {
8956                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8957                         return -EINVAL;
8958                 }
8959                 break;
8960         case DRM_FORMAT_YUYV:
8961         case DRM_FORMAT_UYVY:
8962         case DRM_FORMAT_YVYU:
8963         case DRM_FORMAT_VYUY:
8964                 if (INTEL_INFO(dev)->gen < 5) {
8965                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8966                         return -EINVAL;
8967                 }
8968                 break;
8969         default:
8970                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8971                 return -EINVAL;
8972         }
8973
8974         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8975         if (mode_cmd->offsets[0] != 0)
8976                 return -EINVAL;
8977
8978         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8979         intel_fb->obj = obj;
8980
8981         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8982         if (ret) {
8983                 DRM_ERROR("framebuffer init failed %d\n", ret);
8984                 return ret;
8985         }
8986
8987         return 0;
8988 }
8989
8990 static struct drm_framebuffer *
8991 intel_user_framebuffer_create(struct drm_device *dev,
8992                               struct drm_file *filp,
8993                               struct drm_mode_fb_cmd2 *mode_cmd)
8994 {
8995         struct drm_i915_gem_object *obj;
8996
8997         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8998                                                 mode_cmd->handles[0]));
8999         if (&obj->base == NULL)
9000                 return ERR_PTR(-ENOENT);
9001
9002         return intel_framebuffer_create(dev, mode_cmd, obj);
9003 }
9004
9005 static const struct drm_mode_config_funcs intel_mode_funcs = {
9006         .fb_create = intel_user_framebuffer_create,
9007         .output_poll_changed = intel_fb_output_poll_changed,
9008 };
9009
9010 /* Set up chip specific display functions */
9011 static void intel_init_display(struct drm_device *dev)
9012 {
9013         struct drm_i915_private *dev_priv = dev->dev_private;
9014
9015         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9016                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9017         else if (IS_VALLEYVIEW(dev))
9018                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9019         else if (IS_PINEVIEW(dev))
9020                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9021         else
9022                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9023
9024         if (HAS_DDI(dev)) {
9025                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9026                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9027                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9028                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9029                 dev_priv->display.off = haswell_crtc_off;
9030                 dev_priv->display.update_plane = ironlake_update_plane;
9031         } else if (HAS_PCH_SPLIT(dev)) {
9032                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9033                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9034                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9035                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9036                 dev_priv->display.off = ironlake_crtc_off;
9037                 dev_priv->display.update_plane = ironlake_update_plane;
9038         } else if (IS_VALLEYVIEW(dev)) {
9039                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9040                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9041                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9042                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9043                 dev_priv->display.off = i9xx_crtc_off;
9044                 dev_priv->display.update_plane = i9xx_update_plane;
9045         } else {
9046                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9047                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9048                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9049                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9050                 dev_priv->display.off = i9xx_crtc_off;
9051                 dev_priv->display.update_plane = i9xx_update_plane;
9052         }
9053
9054         /* Returns the core display clock speed */
9055         if (IS_VALLEYVIEW(dev))
9056                 dev_priv->display.get_display_clock_speed =
9057                         valleyview_get_display_clock_speed;
9058         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9059                 dev_priv->display.get_display_clock_speed =
9060                         i945_get_display_clock_speed;
9061         else if (IS_I915G(dev))
9062                 dev_priv->display.get_display_clock_speed =
9063                         i915_get_display_clock_speed;
9064         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9065                 dev_priv->display.get_display_clock_speed =
9066                         i9xx_misc_get_display_clock_speed;
9067         else if (IS_I915GM(dev))
9068                 dev_priv->display.get_display_clock_speed =
9069                         i915gm_get_display_clock_speed;
9070         else if (IS_I865G(dev))
9071                 dev_priv->display.get_display_clock_speed =
9072                         i865_get_display_clock_speed;
9073         else if (IS_I85X(dev))
9074                 dev_priv->display.get_display_clock_speed =
9075                         i855_get_display_clock_speed;
9076         else /* 852, 830 */
9077                 dev_priv->display.get_display_clock_speed =
9078                         i830_get_display_clock_speed;
9079
9080         if (HAS_PCH_SPLIT(dev)) {
9081                 if (IS_GEN5(dev)) {
9082                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9083                         dev_priv->display.write_eld = ironlake_write_eld;
9084                 } else if (IS_GEN6(dev)) {
9085                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9086                         dev_priv->display.write_eld = ironlake_write_eld;
9087                 } else if (IS_IVYBRIDGE(dev)) {
9088                         /* FIXME: detect B0+ stepping and use auto training */
9089                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9090                         dev_priv->display.write_eld = ironlake_write_eld;
9091                         dev_priv->display.modeset_global_resources =
9092                                 ivb_modeset_global_resources;
9093                 } else if (IS_HASWELL(dev)) {
9094                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9095                         dev_priv->display.write_eld = haswell_write_eld;
9096                         dev_priv->display.modeset_global_resources =
9097                                 haswell_modeset_global_resources;
9098                 }
9099         } else if (IS_G4X(dev)) {
9100                 dev_priv->display.write_eld = g4x_write_eld;
9101         }
9102
9103         /* Default just returns -ENODEV to indicate unsupported */
9104         dev_priv->display.queue_flip = intel_default_queue_flip;
9105
9106         switch (INTEL_INFO(dev)->gen) {
9107         case 2:
9108                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9109                 break;
9110
9111         case 3:
9112                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9113                 break;
9114
9115         case 4:
9116         case 5:
9117                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9118                 break;
9119
9120         case 6:
9121                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9122                 break;
9123         case 7:
9124                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9125                 break;
9126         }
9127 }
9128
9129 /*
9130  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9131  * resume, or other times.  This quirk makes sure that's the case for
9132  * affected systems.
9133  */
9134 static void quirk_pipea_force(struct drm_device *dev)
9135 {
9136         struct drm_i915_private *dev_priv = dev->dev_private;
9137
9138         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9139         DRM_INFO("applying pipe a force quirk\n");
9140 }
9141
9142 /*
9143  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9144  */
9145 static void quirk_ssc_force_disable(struct drm_device *dev)
9146 {
9147         struct drm_i915_private *dev_priv = dev->dev_private;
9148         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9149         DRM_INFO("applying lvds SSC disable quirk\n");
9150 }
9151
9152 /*
9153  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9154  * brightness value
9155  */
9156 static void quirk_invert_brightness(struct drm_device *dev)
9157 {
9158         struct drm_i915_private *dev_priv = dev->dev_private;
9159         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9160         DRM_INFO("applying inverted panel brightness quirk\n");
9161 }
9162
9163 struct intel_quirk {
9164         int device;
9165         int subsystem_vendor;
9166         int subsystem_device;
9167         void (*hook)(struct drm_device *dev);
9168 };
9169
9170 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9171 struct intel_dmi_quirk {
9172         void (*hook)(struct drm_device *dev);
9173         const struct dmi_system_id (*dmi_id_list)[];
9174 };
9175
9176 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9177 {
9178         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9179         return 1;
9180 }
9181
9182 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9183         {
9184                 .dmi_id_list = &(const struct dmi_system_id[]) {
9185                         {
9186                                 .callback = intel_dmi_reverse_brightness,
9187                                 .ident = "NCR Corporation",
9188                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9189                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9190                                 },
9191                         },
9192                         { }  /* terminating entry */
9193                 },
9194                 .hook = quirk_invert_brightness,
9195         },
9196 };
9197
9198 static struct intel_quirk intel_quirks[] = {
9199         /* HP Mini needs pipe A force quirk (LP: #322104) */
9200         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9201
9202         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9203         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9204
9205         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9206         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9207
9208         /* 830/845 need to leave pipe A & dpll A up */
9209         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9210         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9211
9212         /* Lenovo U160 cannot use SSC on LVDS */
9213         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9214
9215         /* Sony Vaio Y cannot use SSC on LVDS */
9216         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9217
9218         /* Acer Aspire 5734Z must invert backlight brightness */
9219         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9220
9221         /* Acer/eMachines G725 */
9222         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9223
9224         /* Acer/eMachines e725 */
9225         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9226
9227         /* Acer/Packard Bell NCL20 */
9228         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9229
9230         /* Acer Aspire 4736Z */
9231         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9232 };
9233
9234 static void intel_init_quirks(struct drm_device *dev)
9235 {
9236         struct pci_dev *d = dev->pdev;
9237         int i;
9238
9239         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9240                 struct intel_quirk *q = &intel_quirks[i];
9241
9242                 if (d->device == q->device &&
9243                     (d->subsystem_vendor == q->subsystem_vendor ||
9244                      q->subsystem_vendor == PCI_ANY_ID) &&
9245                     (d->subsystem_device == q->subsystem_device ||
9246                      q->subsystem_device == PCI_ANY_ID))
9247                         q->hook(dev);
9248         }
9249         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9250                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9251                         intel_dmi_quirks[i].hook(dev);
9252         }
9253 }
9254
9255 /* Disable the VGA plane that we never use */
9256 static void i915_disable_vga(struct drm_device *dev)
9257 {
9258         struct drm_i915_private *dev_priv = dev->dev_private;
9259         u8 sr1;
9260         u32 vga_reg = i915_vgacntrl_reg(dev);
9261
9262         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9263         outb(SR01, VGA_SR_INDEX);
9264         sr1 = inb(VGA_SR_DATA);
9265         outb(sr1 | 1<<5, VGA_SR_DATA);
9266         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9267         udelay(300);
9268
9269         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9270         POSTING_READ(vga_reg);
9271 }
9272
9273 void intel_modeset_init_hw(struct drm_device *dev)
9274 {
9275         intel_init_power_well(dev);
9276
9277         intel_prepare_ddi(dev);
9278
9279         intel_init_clock_gating(dev);
9280
9281         mutex_lock(&dev->struct_mutex);
9282         intel_enable_gt_powersave(dev);
9283         mutex_unlock(&dev->struct_mutex);
9284 }
9285
9286 void intel_modeset_suspend_hw(struct drm_device *dev)
9287 {
9288         intel_suspend_hw(dev);
9289 }
9290
9291 void intel_modeset_init(struct drm_device *dev)
9292 {
9293         struct drm_i915_private *dev_priv = dev->dev_private;
9294         int i, j, ret;
9295
9296         drm_mode_config_init(dev);
9297
9298         dev->mode_config.min_width = 0;
9299         dev->mode_config.min_height = 0;
9300
9301         dev->mode_config.preferred_depth = 24;
9302         dev->mode_config.prefer_shadow = 1;
9303
9304         dev->mode_config.funcs = &intel_mode_funcs;
9305
9306         intel_init_quirks(dev);
9307
9308         intel_init_pm(dev);
9309
9310         if (INTEL_INFO(dev)->num_pipes == 0)
9311                 return;
9312
9313         intel_init_display(dev);
9314
9315         if (IS_GEN2(dev)) {
9316                 dev->mode_config.max_width = 2048;
9317                 dev->mode_config.max_height = 2048;
9318         } else if (IS_GEN3(dev)) {
9319                 dev->mode_config.max_width = 4096;
9320                 dev->mode_config.max_height = 4096;
9321         } else {
9322                 dev->mode_config.max_width = 8192;
9323                 dev->mode_config.max_height = 8192;
9324         }
9325         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9326
9327         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9328                       INTEL_INFO(dev)->num_pipes,
9329                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9330
9331         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9332                 intel_crtc_init(dev, i);
9333                 for (j = 0; j < dev_priv->num_plane; j++) {
9334                         ret = intel_plane_init(dev, i, j);
9335                         if (ret)
9336                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9337                                               pipe_name(i), sprite_name(i, j), ret);
9338                 }
9339         }
9340
9341         intel_cpu_pll_init(dev);
9342         intel_pch_pll_init(dev);
9343
9344         /* Just disable it once at startup */
9345         i915_disable_vga(dev);
9346         intel_setup_outputs(dev);
9347
9348         /* Just in case the BIOS is doing something questionable. */
9349         intel_disable_fbc(dev);
9350 }
9351
9352 static void
9353 intel_connector_break_all_links(struct intel_connector *connector)
9354 {
9355         connector->base.dpms = DRM_MODE_DPMS_OFF;
9356         connector->base.encoder = NULL;
9357         connector->encoder->connectors_active = false;
9358         connector->encoder->base.crtc = NULL;
9359 }
9360
9361 static void intel_enable_pipe_a(struct drm_device *dev)
9362 {
9363         struct intel_connector *connector;
9364         struct drm_connector *crt = NULL;
9365         struct intel_load_detect_pipe load_detect_temp;
9366
9367         /* We can't just switch on the pipe A, we need to set things up with a
9368          * proper mode and output configuration. As a gross hack, enable pipe A
9369          * by enabling the load detect pipe once. */
9370         list_for_each_entry(connector,
9371                             &dev->mode_config.connector_list,
9372                             base.head) {
9373                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9374                         crt = &connector->base;
9375                         break;
9376                 }
9377         }
9378
9379         if (!crt)
9380                 return;
9381
9382         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9383                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9384
9385
9386 }
9387
9388 static bool
9389 intel_check_plane_mapping(struct intel_crtc *crtc)
9390 {
9391         struct drm_device *dev = crtc->base.dev;
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         u32 reg, val;
9394
9395         if (INTEL_INFO(dev)->num_pipes == 1)
9396                 return true;
9397
9398         reg = DSPCNTR(!crtc->plane);
9399         val = I915_READ(reg);
9400
9401         if ((val & DISPLAY_PLANE_ENABLE) &&
9402             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9403                 return false;
9404
9405         return true;
9406 }
9407
9408 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9409 {
9410         struct drm_device *dev = crtc->base.dev;
9411         struct drm_i915_private *dev_priv = dev->dev_private;
9412         u32 reg;
9413
9414         /* Clear any frame start delays used for debugging left by the BIOS */
9415         reg = PIPECONF(crtc->config.cpu_transcoder);
9416         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9417
9418         /* We need to sanitize the plane -> pipe mapping first because this will
9419          * disable the crtc (and hence change the state) if it is wrong. Note
9420          * that gen4+ has a fixed plane -> pipe mapping.  */
9421         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9422                 struct intel_connector *connector;
9423                 bool plane;
9424
9425                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9426                               crtc->base.base.id);
9427
9428                 /* Pipe has the wrong plane attached and the plane is active.
9429                  * Temporarily change the plane mapping and disable everything
9430                  * ...  */
9431                 plane = crtc->plane;
9432                 crtc->plane = !plane;
9433                 dev_priv->display.crtc_disable(&crtc->base);
9434                 crtc->plane = plane;
9435
9436                 /* ... and break all links. */
9437                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9438                                     base.head) {
9439                         if (connector->encoder->base.crtc != &crtc->base)
9440                                 continue;
9441
9442                         intel_connector_break_all_links(connector);
9443                 }
9444
9445                 WARN_ON(crtc->active);
9446                 crtc->base.enabled = false;
9447         }
9448
9449         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9450             crtc->pipe == PIPE_A && !crtc->active) {
9451                 /* BIOS forgot to enable pipe A, this mostly happens after
9452                  * resume. Force-enable the pipe to fix this, the update_dpms
9453                  * call below we restore the pipe to the right state, but leave
9454                  * the required bits on. */
9455                 intel_enable_pipe_a(dev);
9456         }
9457
9458         /* Adjust the state of the output pipe according to whether we
9459          * have active connectors/encoders. */
9460         intel_crtc_update_dpms(&crtc->base);
9461
9462         if (crtc->active != crtc->base.enabled) {
9463                 struct intel_encoder *encoder;
9464
9465                 /* This can happen either due to bugs in the get_hw_state
9466                  * functions or because the pipe is force-enabled due to the
9467                  * pipe A quirk. */
9468                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9469                               crtc->base.base.id,
9470                               crtc->base.enabled ? "enabled" : "disabled",
9471                               crtc->active ? "enabled" : "disabled");
9472
9473                 crtc->base.enabled = crtc->active;
9474
9475                 /* Because we only establish the connector -> encoder ->
9476                  * crtc links if something is active, this means the
9477                  * crtc is now deactivated. Break the links. connector
9478                  * -> encoder links are only establish when things are
9479                  *  actually up, hence no need to break them. */
9480                 WARN_ON(crtc->active);
9481
9482                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9483                         WARN_ON(encoder->connectors_active);
9484                         encoder->base.crtc = NULL;
9485                 }
9486         }
9487 }
9488
9489 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9490 {
9491         struct intel_connector *connector;
9492         struct drm_device *dev = encoder->base.dev;
9493
9494         /* We need to check both for a crtc link (meaning that the
9495          * encoder is active and trying to read from a pipe) and the
9496          * pipe itself being active. */
9497         bool has_active_crtc = encoder->base.crtc &&
9498                 to_intel_crtc(encoder->base.crtc)->active;
9499
9500         if (encoder->connectors_active && !has_active_crtc) {
9501                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9502                               encoder->base.base.id,
9503                               drm_get_encoder_name(&encoder->base));
9504
9505                 /* Connector is active, but has no active pipe. This is
9506                  * fallout from our resume register restoring. Disable
9507                  * the encoder manually again. */
9508                 if (encoder->base.crtc) {
9509                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9510                                       encoder->base.base.id,
9511                                       drm_get_encoder_name(&encoder->base));
9512                         encoder->disable(encoder);
9513                 }
9514
9515                 /* Inconsistent output/port/pipe state happens presumably due to
9516                  * a bug in one of the get_hw_state functions. Or someplace else
9517                  * in our code, like the register restore mess on resume. Clamp
9518                  * things to off as a safer default. */
9519                 list_for_each_entry(connector,
9520                                     &dev->mode_config.connector_list,
9521                                     base.head) {
9522                         if (connector->encoder != encoder)
9523                                 continue;
9524
9525                         intel_connector_break_all_links(connector);
9526                 }
9527         }
9528         /* Enabled encoders without active connectors will be fixed in
9529          * the crtc fixup. */
9530 }
9531
9532 void i915_redisable_vga(struct drm_device *dev)
9533 {
9534         struct drm_i915_private *dev_priv = dev->dev_private;
9535         u32 vga_reg = i915_vgacntrl_reg(dev);
9536
9537         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9538                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9539                 i915_disable_vga(dev);
9540         }
9541 }
9542
9543 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9544  * and i915 state tracking structures. */
9545 void intel_modeset_setup_hw_state(struct drm_device *dev,
9546                                   bool force_restore)
9547 {
9548         struct drm_i915_private *dev_priv = dev->dev_private;
9549         enum pipe pipe;
9550         struct drm_plane *plane;
9551         struct intel_crtc *crtc;
9552         struct intel_encoder *encoder;
9553         struct intel_connector *connector;
9554
9555         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9556                             base.head) {
9557                 memset(&crtc->config, 0, sizeof(crtc->config));
9558
9559                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9560                                                                  &crtc->config);
9561
9562                 crtc->base.enabled = crtc->active;
9563
9564                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9565                               crtc->base.base.id,
9566                               crtc->active ? "enabled" : "disabled");
9567         }
9568
9569         if (HAS_DDI(dev))
9570                 intel_ddi_setup_hw_pll_state(dev);
9571
9572         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9573                             base.head) {
9574                 pipe = 0;
9575
9576                 if (encoder->get_hw_state(encoder, &pipe)) {
9577                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9578                         encoder->base.crtc = &crtc->base;
9579                         if (encoder->get_config)
9580                                 encoder->get_config(encoder, &crtc->config);
9581                 } else {
9582                         encoder->base.crtc = NULL;
9583                 }
9584
9585                 encoder->connectors_active = false;
9586                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9587                               encoder->base.base.id,
9588                               drm_get_encoder_name(&encoder->base),
9589                               encoder->base.crtc ? "enabled" : "disabled",
9590                               pipe);
9591         }
9592
9593         list_for_each_entry(connector, &dev->mode_config.connector_list,
9594                             base.head) {
9595                 if (connector->get_hw_state(connector)) {
9596                         connector->base.dpms = DRM_MODE_DPMS_ON;
9597                         connector->encoder->connectors_active = true;
9598                         connector->base.encoder = &connector->encoder->base;
9599                 } else {
9600                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9601                         connector->base.encoder = NULL;
9602                 }
9603                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9604                               connector->base.base.id,
9605                               drm_get_connector_name(&connector->base),
9606                               connector->base.encoder ? "enabled" : "disabled");
9607         }
9608
9609         /* HW state is read out, now we need to sanitize this mess. */
9610         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9611                             base.head) {
9612                 intel_sanitize_encoder(encoder);
9613         }
9614
9615         for_each_pipe(pipe) {
9616                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9617                 intel_sanitize_crtc(crtc);
9618                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9619         }
9620
9621         if (force_restore) {
9622                 /*
9623                  * We need to use raw interfaces for restoring state to avoid
9624                  * checking (bogus) intermediate states.
9625                  */
9626                 for_each_pipe(pipe) {
9627                         struct drm_crtc *crtc =
9628                                 dev_priv->pipe_to_crtc_mapping[pipe];
9629
9630                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9631                                          crtc->fb);
9632                 }
9633                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9634                         intel_plane_restore(plane);
9635
9636                 i915_redisable_vga(dev);
9637         } else {
9638                 intel_modeset_update_staged_output_state(dev);
9639         }
9640
9641         intel_modeset_check_state(dev);
9642
9643         drm_mode_config_reset(dev);
9644 }
9645
9646 void intel_modeset_gem_init(struct drm_device *dev)
9647 {
9648         intel_modeset_init_hw(dev);
9649
9650         intel_setup_overlay(dev);
9651
9652         intel_modeset_setup_hw_state(dev, false);
9653 }
9654
9655 void intel_modeset_cleanup(struct drm_device *dev)
9656 {
9657         struct drm_i915_private *dev_priv = dev->dev_private;
9658         struct drm_crtc *crtc;
9659         struct intel_crtc *intel_crtc;
9660
9661         /*
9662          * Interrupts and polling as the first thing to avoid creating havoc.
9663          * Too much stuff here (turning of rps, connectors, ...) would
9664          * experience fancy races otherwise.
9665          */
9666         drm_irq_uninstall(dev);
9667         cancel_work_sync(&dev_priv->hotplug_work);
9668         /*
9669          * Due to the hpd irq storm handling the hotplug work can re-arm the
9670          * poll handlers. Hence disable polling after hpd handling is shut down.
9671          */
9672         drm_kms_helper_poll_fini(dev);
9673
9674         mutex_lock(&dev->struct_mutex);
9675
9676         intel_unregister_dsm_handler();
9677
9678         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9679                 /* Skip inactive CRTCs */
9680                 if (!crtc->fb)
9681                         continue;
9682
9683                 intel_crtc = to_intel_crtc(crtc);
9684                 intel_increase_pllclock(crtc);
9685         }
9686
9687         intel_disable_fbc(dev);
9688
9689         intel_disable_gt_powersave(dev);
9690
9691         ironlake_teardown_rc6(dev);
9692
9693         mutex_unlock(&dev->struct_mutex);
9694
9695         /* flush any delayed tasks or pending work */
9696         flush_scheduled_work();
9697
9698         /* destroy backlight, if any, before the connectors */
9699         intel_panel_destroy_backlight(dev);
9700
9701         drm_mode_config_cleanup(dev);
9702
9703         intel_cleanup_overlay(dev);
9704 }
9705
9706 /*
9707  * Return which encoder is currently attached for connector.
9708  */
9709 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9710 {
9711         return &intel_attached_encoder(connector)->base;
9712 }
9713
9714 void intel_connector_attach_encoder(struct intel_connector *connector,
9715                                     struct intel_encoder *encoder)
9716 {
9717         connector->encoder = encoder;
9718         drm_mode_connector_attach_encoder(&connector->base,
9719                                           &encoder->base);
9720 }
9721
9722 /*
9723  * set vga decode state - true == enable VGA decode
9724  */
9725 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9726 {
9727         struct drm_i915_private *dev_priv = dev->dev_private;
9728         u16 gmch_ctrl;
9729
9730         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9731         if (state)
9732                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9733         else
9734                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9735         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9736         return 0;
9737 }
9738
9739 #ifdef CONFIG_DEBUG_FS
9740 #include <linux/seq_file.h>
9741
9742 struct intel_display_error_state {
9743
9744         u32 power_well_driver;
9745
9746         struct intel_cursor_error_state {
9747                 u32 control;
9748                 u32 position;
9749                 u32 base;
9750                 u32 size;
9751         } cursor[I915_MAX_PIPES];
9752
9753         struct intel_pipe_error_state {
9754                 enum transcoder cpu_transcoder;
9755                 u32 conf;
9756                 u32 source;
9757
9758                 u32 htotal;
9759                 u32 hblank;
9760                 u32 hsync;
9761                 u32 vtotal;
9762                 u32 vblank;
9763                 u32 vsync;
9764         } pipe[I915_MAX_PIPES];
9765
9766         struct intel_plane_error_state {
9767                 u32 control;
9768                 u32 stride;
9769                 u32 size;
9770                 u32 pos;
9771                 u32 addr;
9772                 u32 surface;
9773                 u32 tile_offset;
9774         } plane[I915_MAX_PIPES];
9775 };
9776
9777 struct intel_display_error_state *
9778 intel_display_capture_error_state(struct drm_device *dev)
9779 {
9780         drm_i915_private_t *dev_priv = dev->dev_private;
9781         struct intel_display_error_state *error;
9782         enum transcoder cpu_transcoder;
9783         int i;
9784
9785         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9786         if (error == NULL)
9787                 return NULL;
9788
9789         if (HAS_POWER_WELL(dev))
9790                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9791
9792         for_each_pipe(i) {
9793                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9794                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9795
9796                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9797                         error->cursor[i].control = I915_READ(CURCNTR(i));
9798                         error->cursor[i].position = I915_READ(CURPOS(i));
9799                         error->cursor[i].base = I915_READ(CURBASE(i));
9800                 } else {
9801                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9802                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9803                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9804                 }
9805
9806                 error->plane[i].control = I915_READ(DSPCNTR(i));
9807                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9808                 if (INTEL_INFO(dev)->gen <= 3) {
9809                         error->plane[i].size = I915_READ(DSPSIZE(i));
9810                         error->plane[i].pos = I915_READ(DSPPOS(i));
9811                 }
9812                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9813                         error->plane[i].addr = I915_READ(DSPADDR(i));
9814                 if (INTEL_INFO(dev)->gen >= 4) {
9815                         error->plane[i].surface = I915_READ(DSPSURF(i));
9816                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9817                 }
9818
9819                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9820                 error->pipe[i].source = I915_READ(PIPESRC(i));
9821                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9822                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9823                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9824                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9825                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9826                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9827         }
9828
9829         /* In the code above we read the registers without checking if the power
9830          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9831          * prevent the next I915_WRITE from detecting it and printing an error
9832          * message. */
9833         if (HAS_POWER_WELL(dev))
9834                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9835
9836         return error;
9837 }
9838
9839 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9840
9841 void
9842 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9843                                 struct drm_device *dev,
9844                                 struct intel_display_error_state *error)
9845 {
9846         int i;
9847
9848         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9849         if (HAS_POWER_WELL(dev))
9850                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9851                            error->power_well_driver);
9852         for_each_pipe(i) {
9853                 err_printf(m, "Pipe [%d]:\n", i);
9854                 err_printf(m, "  CPU transcoder: %c\n",
9855                            transcoder_name(error->pipe[i].cpu_transcoder));
9856                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9857                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9858                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9859                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9860                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9861                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9862                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9863                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9864
9865                 err_printf(m, "Plane [%d]:\n", i);
9866                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9867                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9868                 if (INTEL_INFO(dev)->gen <= 3) {
9869                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9870                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9871                 }
9872                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9873                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9874                 if (INTEL_INFO(dev)->gen >= 4) {
9875                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9876                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9877                 }
9878
9879                 err_printf(m, "Cursor [%d]:\n", i);
9880                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9881                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9882                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9883         }
9884 }
9885 #endif