drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_gem_dmabuf.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 119         struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int bxt_calc_cdclk(int max_pixclk);
 127
 128 struct intel_limit {
 129         struct {
 130                 int min, max;
 131         } dot, vco, n, m, m1, m2, p, p1;
 132
 133         struct {
 134                 int dot_limit;
 135                 int p2_slow, p2_fast;
 136         } p2;
 137 };
 138
 139 /* returns HPLL frequency in kHz */
 140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 141 {
 142         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 143
 144         /* Obtain SKU information */
 145         mutex_lock(&dev_priv->sb_lock);
 146         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 147                 CCK_FUSE_HPLL_FREQ_MASK;
 148         mutex_unlock(&dev_priv->sb_lock);
 149
 150         return vco_freq[hpll_freq] * 1000;
 151 }
 152
 153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 154                       const char *name, u32 reg, int ref_freq)
 155 {
 156         u32 val;
 157         int divider;
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 170 }
 171
 172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 173                                   const char *name, u32 reg)
 174 {
 175         if (dev_priv->hpll_freq == 0)
 176                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 177
 178         return vlv_get_cck_clock(dev_priv, name, reg,
 179                                  dev_priv->hpll_freq);
 180 }
 181
 182 static int
 183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 184 {
 185         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 186 }
 187
 188 static int
 189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 190 {
 191         /* RAWCLK_FREQ_VLV register updated from power well code */
 192         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 193                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 194 }
 195
 196 static int
 197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 198 {
 199         uint32_t clkcfg;
 200
 201         /* hrawclock is 1/4 the FSB frequency */
 202         clkcfg = I915_READ(CLKCFG);
 203         switch (clkcfg & CLKCFG_FSB_MASK) {
 204         case CLKCFG_FSB_400:
 205                 return 100000;
 206         case CLKCFG_FSB_533:
 207                 return 133333;
 208         case CLKCFG_FSB_667:
 209                 return 166667;
 210         case CLKCFG_FSB_800:
 211                 return 200000;
 212         case CLKCFG_FSB_1067:
 213                 return 266667;
 214         case CLKCFG_FSB_1333:
 215                 return 333333;
 216         /* these two are just a guess; one of them might be right */
 217         case CLKCFG_FSB_1600:
 218         case CLKCFG_FSB_1600_ALT:
 219                 return 400000;
 220         default:
 221                 return 133333;
 222         }
 223 }
 224
 225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 226 {
 227         if (HAS_PCH_SPLIT(dev_priv))
 228                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 229         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 230                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 231         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 232                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 233         else
 234                 return; /* no rawclk on other platforms, or no need to know it */
 235
 236         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 237 }
 238
 239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 240 {
 241         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 242                 return;
 243
 244         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 245                                                       CCK_CZ_CLOCK_CONTROL);
 246
 247         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 248 }
 249
 250 static inline u32 /* units of 100MHz */
 251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 252                     const struct intel_crtc_state *pipe_config)
 253 {
 254         if (HAS_DDI(dev_priv))
 255                 return pipe_config->port_clock; /* SPLL */
 256         else if (IS_GEN5(dev_priv))
 257                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 258         else
 259                 return 270000;
 260 }
 261
 262 static const struct intel_limit intel_limits_i8xx_dac = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 2, .max = 33 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 4, .p2_fast = 2 },
 273 };
 274
 275 static const struct intel_limit intel_limits_i8xx_dvo = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 908000, .max = 1512000 },
 278         .n = { .min = 2, .max = 16 },
 279         .m = { .min = 96, .max = 140 },
 280         .m1 = { .min = 18, .max = 26 },
 281         .m2 = { .min = 6, .max = 16 },
 282         .p = { .min = 4, .max = 128 },
 283         .p1 = { .min = 2, .max = 33 },
 284         .p2 = { .dot_limit = 165000,
 285                 .p2_slow = 4, .p2_fast = 4 },
 286 };
 287
 288 static const struct intel_limit intel_limits_i8xx_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 908000, .max = 1512000 },
 291         .n = { .min = 2, .max = 16 },
 292         .m = { .min = 96, .max = 140 },
 293         .m1 = { .min = 18, .max = 26 },
 294         .m2 = { .min = 6, .max = 16 },
 295         .p = { .min = 4, .max = 128 },
 296         .p1 = { .min = 1, .max = 6 },
 297         .p2 = { .dot_limit = 165000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301 static const struct intel_limit intel_limits_i9xx_sdvo = {
 302         .dot = { .min = 20000, .max = 400000 },
 303         .vco = { .min = 1400000, .max = 2800000 },
 304         .n = { .min = 1, .max = 6 },
 305         .m = { .min = 70, .max = 120 },
 306         .m1 = { .min = 8, .max = 18 },
 307         .m2 = { .min = 3, .max = 7 },
 308         .p = { .min = 5, .max = 80 },
 309         .p1 = { .min = 1, .max = 8 },
 310         .p2 = { .dot_limit = 200000,
 311                 .p2_slow = 10, .p2_fast = 5 },
 312 };
 313
 314 static const struct intel_limit intel_limits_i9xx_lvds = {
 315         .dot = { .min = 20000, .max = 400000 },
 316         .vco = { .min = 1400000, .max = 2800000 },
 317         .n = { .min = 1, .max = 6 },
 318         .m = { .min = 70, .max = 120 },
 319         .m1 = { .min = 8, .max = 18 },
 320         .m2 = { .min = 3, .max = 7 },
 321         .p = { .min = 7, .max = 98 },
 322         .p1 = { .min = 1, .max = 8 },
 323         .p2 = { .dot_limit = 112000,
 324                 .p2_slow = 14, .p2_fast = 7 },
 325 };
 326
 327
 328 static const struct intel_limit intel_limits_g4x_sdvo = {
 329         .dot = { .min = 25000, .max = 270000 },
 330         .vco = { .min = 1750000, .max = 3500000},
 331         .n = { .min = 1, .max = 4 },
 332         .m = { .min = 104, .max = 138 },
 333         .m1 = { .min = 17, .max = 23 },
 334         .m2 = { .min = 5, .max = 11 },
 335         .p = { .min = 10, .max = 30 },
 336         .p1 = { .min = 1, .max = 3},
 337         .p2 = { .dot_limit = 270000,
 338                 .p2_slow = 10,
 339                 .p2_fast = 10
 340         },
 341 };
 342
 343 static const struct intel_limit intel_limits_g4x_hdmi = {
 344         .dot = { .min = 22000, .max = 400000 },
 345         .vco = { .min = 1750000, .max = 3500000},
 346         .n = { .min = 1, .max = 4 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 16, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 5, .max = 80 },
 351         .p1 = { .min = 1, .max = 8},
 352         .p2 = { .dot_limit = 165000,
 353                 .p2_slow = 10, .p2_fast = 5 },
 354 };
 355
 356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 357         .dot = { .min = 20000, .max = 115000 },
 358         .vco = { .min = 1750000, .max = 3500000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 104, .max = 138 },
 361         .m1 = { .min = 17, .max = 23 },
 362         .m2 = { .min = 5, .max = 11 },
 363         .p = { .min = 28, .max = 112 },
 364         .p1 = { .min = 2, .max = 8 },
 365         .p2 = { .dot_limit = 0,
 366                 .p2_slow = 14, .p2_fast = 14
 367         },
 368 };
 369
 370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 371         .dot = { .min = 80000, .max = 224000 },
 372         .vco = { .min = 1750000, .max = 3500000 },
 373         .n = { .min = 1, .max = 3 },
 374         .m = { .min = 104, .max = 138 },
 375         .m1 = { .min = 17, .max = 23 },
 376         .m2 = { .min = 5, .max = 11 },
 377         .p = { .min = 14, .max = 42 },
 378         .p1 = { .min = 2, .max = 6 },
 379         .p2 = { .dot_limit = 0,
 380                 .p2_slow = 7, .p2_fast = 7
 381         },
 382 };
 383
 384 static const struct intel_limit intel_limits_pineview_sdvo = {
 385         .dot = { .min = 20000, .max = 400000},
 386         .vco = { .min = 1700000, .max = 3500000 },
 387         /* Pineview's Ncounter is a ring counter */
 388         .n = { .min = 3, .max = 6 },
 389         .m = { .min = 2, .max = 256 },
 390         /* Pineview only has one combined m divider, which we treat as m2. */
 391         .m1 = { .min = 0, .max = 0 },
 392         .m2 = { .min = 0, .max = 254 },
 393         .p = { .min = 5, .max = 80 },
 394         .p1 = { .min = 1, .max = 8 },
 395         .p2 = { .dot_limit = 200000,
 396                 .p2_slow = 10, .p2_fast = 5 },
 397 };
 398
 399 static const struct intel_limit intel_limits_pineview_lvds = {
 400         .dot = { .min = 20000, .max = 400000 },
 401         .vco = { .min = 1700000, .max = 3500000 },
 402         .n = { .min = 3, .max = 6 },
 403         .m = { .min = 2, .max = 256 },
 404         .m1 = { .min = 0, .max = 0 },
 405         .m2 = { .min = 0, .max = 254 },
 406         .p = { .min = 7, .max = 112 },
 407         .p1 = { .min = 1, .max = 8 },
 408         .p2 = { .dot_limit = 112000,
 409                 .p2_slow = 14, .p2_fast = 14 },
 410 };
 411
 412 /* Ironlake / Sandybridge
 413  *
 414  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 415  * the range value for them is (actual_value - 2).
 416  */
 417 static const struct intel_limit intel_limits_ironlake_dac = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 5 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 5, .max = 80 },
 425         .p1 = { .min = 1, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 10, .p2_fast = 5 },
 428 };
 429
 430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 3 },
 434         .m = { .min = 79, .max = 118 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 127 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 56 },
 451         .p1 = { .min = 2, .max = 8 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 /* LVDS 100mhz refclk limits. */
 457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 458         .dot = { .min = 25000, .max = 350000 },
 459         .vco = { .min = 1760000, .max = 3510000 },
 460         .n = { .min = 1, .max = 2 },
 461         .m = { .min = 79, .max = 126 },
 462         .m1 = { .min = 12, .max = 22 },
 463         .m2 = { .min = 5, .max = 9 },
 464         .p = { .min = 28, .max = 112 },
 465         .p1 = { .min = 2, .max = 8 },
 466         .p2 = { .dot_limit = 225000,
 467                 .p2_slow = 14, .p2_fast = 14 },
 468 };
 469
 470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 471         .dot = { .min = 25000, .max = 350000 },
 472         .vco = { .min = 1760000, .max = 3510000 },
 473         .n = { .min = 1, .max = 3 },
 474         .m = { .min = 79, .max = 126 },
 475         .m1 = { .min = 12, .max = 22 },
 476         .m2 = { .min = 5, .max = 9 },
 477         .p = { .min = 14, .max = 42 },
 478         .p1 = { .min = 2, .max = 6 },
 479         .p2 = { .dot_limit = 225000,
 480                 .p2_slow = 7, .p2_fast = 7 },
 481 };
 482
 483 static const struct intel_limit intel_limits_vlv = {
 484          /*
 485           * These are the data rate limits (measured in fast clocks)
 486           * since those are the strictest limits we have. The fast
 487           * clock and actual rate limits are more relaxed, so checking
 488           * them would make no difference.
 489           */
 490         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 491         .vco = { .min = 4000000, .max = 6000000 },
 492         .n = { .min = 1, .max = 7 },
 493         .m1 = { .min = 2, .max = 3 },
 494         .m2 = { .min = 11, .max = 156 },
 495         .p1 = { .min = 2, .max = 3 },
 496         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 497 };
 498
 499 static const struct intel_limit intel_limits_chv = {
 500         /*
 501          * These are the data rate limits (measured in fast clocks)
 502          * since those are the strictest limits we have.  The fast
 503          * clock and actual rate limits are more relaxed, so checking
 504          * them would make no difference.
 505          */
 506         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 507         .vco = { .min = 4800000, .max = 6480000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 511         .p1 = { .min = 2, .max = 4 },
 512         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 513 };
 514
 515 static const struct intel_limit intel_limits_bxt = {
 516         /* FIXME: find real dot limits */
 517         .dot = { .min = 0, .max = INT_MAX },
 518         .vco = { .min = 4800000, .max = 6700000 },
 519         .n = { .min = 1, .max = 1 },
 520         .m1 = { .min = 2, .max = 2 },
 521         /* FIXME: find real m2 limits */
 522         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 523         .p1 = { .min = 2, .max = 4 },
 524         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 525 };
 526
 527 static bool
 528 needs_modeset(struct drm_crtc_state *state)
 529 {
 530         return drm_atomic_crtc_needs_modeset(state);
 531 }
 532
 533 /*
 534  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 535  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 536  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 537  * The helpers' return value is the rate of the clock that is fed to the
 538  * display engine's pipe which can be the above fast dot clock rate or a
 539  * divided-down version of it.
 540  */
 541 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 542 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 543 {
 544         clock->m = clock->m2 + 2;
 545         clock->p = clock->p1 * clock->p2;
 546         if (WARN_ON(clock->n == 0 || clock->p == 0))
 547                 return 0;
 548         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 549         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 550
 551         return clock->dot;
 552 }
 553
 554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 555 {
 556         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 557 }
 558
 559 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 560 {
 561         clock->m = i9xx_dpll_compute_m(clock);
 562         clock->p = clock->p1 * clock->p2;
 563         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 564                 return 0;
 565         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 566         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 567
 568         return clock->dot;
 569 }
 570
 571 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 572 {
 573         clock->m = clock->m1 * clock->m2;
 574         clock->p = clock->p1 * clock->p2;
 575         if (WARN_ON(clock->n == 0 || clock->p == 0))
 576                 return 0;
 577         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 578         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 579
 580         return clock->dot / 5;
 581 }
 582
 583 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 584 {
 585         clock->m = clock->m1 * clock->m2;
 586         clock->p = clock->p1 * clock->p2;
 587         if (WARN_ON(clock->n == 0 || clock->p == 0))
 588                 return 0;
 589         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 590                         clock->n << 22);
 591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 592
 593         return clock->dot / 5;
 594 }
 595
 596 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 597 /**
 598  * Returns whether the given set of divisors are valid for a given refclk with
 599  * the given connectors.
 600  */
 601
 602 static bool intel_PLL_is_valid(struct drm_device *dev,
 603                                const struct intel_limit *limit,
 604                                const struct dpll *clock)
 605 {
 606         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 607                 INTELPllInvalid("n out of range\n");
 608         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 609                 INTELPllInvalid("p1 out of range\n");
 610         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 611                 INTELPllInvalid("m2 out of range\n");
 612         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 613                 INTELPllInvalid("m1 out of range\n");
 614
 615         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 616             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 617                 if (clock->m1 <= clock->m2)
 618                         INTELPllInvalid("m1 <= m2\n");
 619
 620         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 621                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 622                         INTELPllInvalid("p out of range\n");
 623                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 624                         INTELPllInvalid("m out of range\n");
 625         }
 626
 627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 628                 INTELPllInvalid("vco out of range\n");
 629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 630          * connector, etc., rather than just a single range.
 631          */
 632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 633                 INTELPllInvalid("dot out of range\n");
 634
 635         return true;
 636 }
 637
 638 static int
 639 i9xx_select_p2_div(const struct intel_limit *limit,
 640                    const struct intel_crtc_state *crtc_state,
 641                    int target)
 642 {
 643         struct drm_device *dev = crtc_state->base.crtc->dev;
 644
 645         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 646                 /*
 647                  * For LVDS just rely on its current settings for dual-channel.
 648                  * We haven't figured out how to reliably set up different
 649                  * single/dual channel state, if we even can.
 650                  */
 651                 if (intel_is_dual_link_lvds(dev))
 652                         return limit->p2.p2_fast;
 653                 else
 654                         return limit->p2.p2_slow;
 655         } else {
 656                 if (target < limit->p2.dot_limit)
 657                         return limit->p2.p2_slow;
 658                 else
 659                         return limit->p2.p2_fast;
 660         }
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 i9xx_find_best_dpll(const struct intel_limit *limit,
 675                     struct intel_crtc_state *crtc_state,
 676                     int target, int refclk, struct dpll *match_clock,
 677                     struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         if (clock.m2 >= clock.m1)
 692                                 break;
 693                         for (clock.n = limit->n.min;
 694                              clock.n <= limit->n.max; clock.n++) {
 695                                 for (clock.p1 = limit->p1.min;
 696                                         clock.p1 <= limit->p1.max; clock.p1++) {
 697                                         int this_err;
 698
 699                                         i9xx_calc_dpll_params(refclk, &clock);
 700                                         if (!intel_PLL_is_valid(dev, limit,
 701                                                                 &clock))
 702                                                 continue;
 703                                         if (match_clock &&
 704                                             clock.p != match_clock->p)
 705                                                 continue;
 706
 707                                         this_err = abs(clock.dot - target);
 708                                         if (this_err < err) {
 709                                                 *best_clock = clock;
 710                                                 err = this_err;
 711                                         }
 712                                 }
 713                         }
 714                 }
 715         }
 716
 717         return (err != target);
 718 }
 719
 720 /*
 721  * Returns a set of divisors for the desired target clock with the given
 722  * refclk, or FALSE.  The returned values represent the clock equation:
 723  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 724  *
 725  * Target and reference clocks are specified in kHz.
 726  *
 727  * If match_clock is provided, then best_clock P divider must match the P
 728  * divider from @match_clock used for LVDS downclocking.
 729  */
 730 static bool
 731 pnv_find_best_dpll(const struct intel_limit *limit,
 732                    struct intel_crtc_state *crtc_state,
 733                    int target, int refclk, struct dpll *match_clock,
 734                    struct dpll *best_clock)
 735 {
 736         struct drm_device *dev = crtc_state->base.crtc->dev;
 737         struct dpll clock;
 738         int err = target;
 739
 740         memset(best_clock, 0, sizeof(*best_clock));
 741
 742         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 743
 744         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 745              clock.m1++) {
 746                 for (clock.m2 = limit->m2.min;
 747                      clock.m2 <= limit->m2.max; clock.m2++) {
 748                         for (clock.n = limit->n.min;
 749                              clock.n <= limit->n.max; clock.n++) {
 750                                 for (clock.p1 = limit->p1.min;
 751                                         clock.p1 <= limit->p1.max; clock.p1++) {
 752                                         int this_err;
 753
 754                                         pnv_calc_dpll_params(refclk, &clock);
 755                                         if (!intel_PLL_is_valid(dev, limit,
 756                                                                 &clock))
 757                                                 continue;
 758                                         if (match_clock &&
 759                                             clock.p != match_clock->p)
 760                                                 continue;
 761
 762                                         this_err = abs(clock.dot - target);
 763                                         if (this_err < err) {
 764                                                 *best_clock = clock;
 765                                                 err = this_err;
 766                                         }
 767                                 }
 768                         }
 769                 }
 770         }
 771
 772         return (err != target);
 773 }
 774
 775 /*
 776  * Returns a set of divisors for the desired target clock with the given
 777  * refclk, or FALSE.  The returned values represent the clock equation:
 778  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 779  *
 780  * Target and reference clocks are specified in kHz.
 781  *
 782  * If match_clock is provided, then best_clock P divider must match the P
 783  * divider from @match_clock used for LVDS downclocking.
 784  */
 785 static bool
 786 g4x_find_best_dpll(const struct intel_limit *limit,
 787                    struct intel_crtc_state *crtc_state,
 788                    int target, int refclk, struct dpll *match_clock,
 789                    struct dpll *best_clock)
 790 {
 791         struct drm_device *dev = crtc_state->base.crtc->dev;
 792         struct dpll clock;
 793         int max_n;
 794         bool found = false;
 795         /* approximately equals target * 0.00585 */
 796         int err_most = (target >> 8) + (target >> 9);
 797
 798         memset(best_clock, 0, sizeof(*best_clock));
 799
 800         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 801
 802         max_n = limit->n.max;
 803         /* based on hardware requirement, prefer smaller n to precision */
 804         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 805                 /* based on hardware requirement, prefere larger m1,m2 */
 806                 for (clock.m1 = limit->m1.max;
 807                      clock.m1 >= limit->m1.min; clock.m1--) {
 808                         for (clock.m2 = limit->m2.max;
 809                              clock.m2 >= limit->m2.min; clock.m2--) {
 810                                 for (clock.p1 = limit->p1.max;
 811                                      clock.p1 >= limit->p1.min; clock.p1--) {
 812                                         int this_err;
 813
 814                                         i9xx_calc_dpll_params(refclk, &clock);
 815                                         if (!intel_PLL_is_valid(dev, limit,
 816                                                                 &clock))
 817                                                 continue;
 818
 819                                         this_err = abs(clock.dot - target);
 820                                         if (this_err < err_most) {
 821                                                 *best_clock = clock;
 822                                                 err_most = this_err;
 823                                                 max_n = clock.n;
 824                                                 found = true;
 825                                         }
 826                                 }
 827                         }
 828                 }
 829         }
 830         return found;
 831 }
 832
 833 /*
 834  * Check if the calculated PLL configuration is more optimal compared to the
 835  * best configuration and error found so far. Return the calculated error.
 836  */
 837 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 838                                const struct dpll *calculated_clock,
 839                                const struct dpll *best_clock,
 840                                unsigned int best_error_ppm,
 841                                unsigned int *error_ppm)
 842 {
 843         /*
 844          * For CHV ignore the error and consider only the P value.
 845          * Prefer a bigger P value based on HW requirements.
 846          */
 847         if (IS_CHERRYVIEW(dev)) {
 848                 *error_ppm = 0;
 849
 850                 return calculated_clock->p > best_clock->p;
 851         }
 852
 853         if (WARN_ON_ONCE(!target_freq))
 854                 return false;
 855
 856         *error_ppm = div_u64(1000000ULL *
 857                                 abs(target_freq - calculated_clock->dot),
 858                              target_freq);
 859         /*
 860          * Prefer a better P value over a better (smaller) error if the error
 861          * is small. Ensure this preference for future configurations too by
 862          * setting the error to 0.
 863          */
 864         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 865                 *error_ppm = 0;
 866
 867                 return true;
 868         }
 869
 870         return *error_ppm + 10 < best_error_ppm;
 871 }
 872
 873 /*
 874  * Returns a set of divisors for the desired target clock with the given
 875  * refclk, or FALSE.  The returned values represent the clock equation:
 876  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 877  */
 878 static bool
 879 vlv_find_best_dpll(const struct intel_limit *limit,
 880                    struct intel_crtc_state *crtc_state,
 881                    int target, int refclk, struct dpll *match_clock,
 882                    struct dpll *best_clock)
 883 {
 884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 885         struct drm_device *dev = crtc->base.dev;
 886         struct dpll clock;
 887         unsigned int bestppm = 1000000;
 888         /* min update 19.2 MHz */
 889         int max_n = min(limit->n.max, refclk / 19200);
 890         bool found = false;
 891
 892         target *= 5; /* fast clock */
 893
 894         memset(best_clock, 0, sizeof(*best_clock));
 895
 896         /* based on hardware requirement, prefer smaller n to precision */
 897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 898                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 899                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 900                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 901                                 clock.p = clock.p1 * clock.p2;
 902                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 903                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 904                                         unsigned int ppm;
 905
 906                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 907                                                                      refclk * clock.m1);
 908
 909                                         vlv_calc_dpll_params(refclk, &clock);
 910
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         if (!vlv_PLL_is_optimal(dev, target,
 916                                                                 &clock,
 917                                                                 best_clock,
 918                                                                 bestppm, &ppm))
 919                                                 continue;
 920
 921                                         *best_clock = clock;
 922                                         bestppm = ppm;
 923                                         found = true;
 924                                 }
 925                         }
 926                 }
 927         }
 928
 929         return found;
 930 }
 931
 932 /*
 933  * Returns a set of divisors for the desired target clock with the given
 934  * refclk, or FALSE.  The returned values represent the clock equation:
 935  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 936  */
 937 static bool
 938 chv_find_best_dpll(const struct intel_limit *limit,
 939                    struct intel_crtc_state *crtc_state,
 940                    int target, int refclk, struct dpll *match_clock,
 941                    struct dpll *best_clock)
 942 {
 943         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 944         struct drm_device *dev = crtc->base.dev;
 945         unsigned int best_error_ppm;
 946         struct dpll clock;
 947         uint64_t m2;
 948         int found = false;
 949
 950         memset(best_clock, 0, sizeof(*best_clock));
 951         best_error_ppm = 1000000;
 952
 953         /*
 954          * Based on hardware doc, the n always set to 1, and m1 always
 955          * set to 2.  If requires to support 200Mhz refclk, we need to
 956          * revisit this because n may not 1 anymore.
 957          */
 958         clock.n = 1, clock.m1 = 2;
 959         target *= 5;    /* fast clock */
 960
 961         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 962                 for (clock.p2 = limit->p2.p2_fast;
 963                                 clock.p2 >= limit->p2.p2_slow;
 964                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 965                         unsigned int error_ppm;
 966
 967                         clock.p = clock.p1 * clock.p2;
 968
 969                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 970                                         clock.n) << 22, refclk * clock.m1);
 971
 972                         if (m2 > INT_MAX/clock.m1)
 973                                 continue;
 974
 975                         clock.m2 = m2;
 976
 977                         chv_calc_dpll_params(refclk, &clock);
 978
 979                         if (!intel_PLL_is_valid(dev, limit, &clock))
 980                                 continue;
 981
 982                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 983                                                 best_error_ppm, &error_ppm))
 984                                 continue;
 985
 986                         *best_clock = clock;
 987                         best_error_ppm = error_ppm;
 988                         found = true;
 989                 }
 990         }
 991
 992         return found;
 993 }
 994
 995 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 996                         struct dpll *best_clock)
 997 {
 998         int refclk = 100000;
 999         const struct intel_limit *limit = &intel_limits_bxt;
1000
1001         return chv_find_best_dpll(limit, crtc_state,
1002                                   target_clock, refclk, NULL, best_clock);
1003 }
1004
1005 bool intel_crtc_active(struct drm_crtc *crtc)
1006 {
1007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008
1009         /* Be paranoid as we can arrive here with only partial
1010          * state retrieved from the hardware during setup.
1011          *
1012          * We can ditch the adjusted_mode.crtc_clock check as soon
1013          * as Haswell has gained clock readout/fastboot support.
1014          *
1015          * We can ditch the crtc->primary->fb check as soon as we can
1016          * properly reconstruct framebuffers.
1017          *
1018          * FIXME: The intel_crtc->active here should be switched to
1019          * crtc->state->active once we have proper CRTC states wired up
1020          * for atomic.
1021          */
1022         return intel_crtc->active && crtc->primary->state->fb &&
1023                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1024 }
1025
1026 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1027                                              enum pipe pipe)
1028 {
1029         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1031
1032         return intel_crtc->config->cpu_transcoder;
1033 }
1034
1035 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(dev);
1038         i915_reg_t reg = PIPEDSL(pipe);
1039         u32 line1, line2;
1040         u32 line_mask;
1041
1042         if (IS_GEN2(dev))
1043                 line_mask = DSL_LINEMASK_GEN2;
1044         else
1045                 line_mask = DSL_LINEMASK_GEN3;
1046
1047         line1 = I915_READ(reg) & line_mask;
1048         msleep(5);
1049         line2 = I915_READ(reg) & line_mask;
1050
1051         return line1 == line2;
1052 }
1053
1054 /*
1055  * intel_wait_for_pipe_off - wait for pipe to turn off
1056  * @crtc: crtc whose pipe to wait for
1057  *
1058  * After disabling a pipe, we can't wait for vblank in the usual way,
1059  * spinning on the vblank interrupt status bit, since we won't actually
1060  * see an interrupt when the pipe is disabled.
1061  *
1062  * On Gen4 and above:
1063  *   wait for the pipe register state bit to turn off
1064  *
1065  * Otherwise:
1066  *   wait for the display line value to settle (it usually
1067  *   ends up stopping at the start of the next frame).
1068  *
1069  */
1070 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1071 {
1072         struct drm_device *dev = crtc->base.dev;
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1075         enum pipe pipe = crtc->pipe;
1076
1077         if (INTEL_INFO(dev)->gen >= 4) {
1078                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1079
1080                 /* Wait for the Pipe State to go off */
1081                 if (intel_wait_for_register(dev_priv,
1082                                             reg, I965_PIPECONF_ACTIVE, 0,
1083                                             100))
1084                         WARN(1, "pipe_off wait timed out\n");
1085         } else {
1086                 /* Wait for the display line to settle */
1087                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1088                         WARN(1, "pipe_off wait timed out\n");
1089         }
1090 }
1091
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094                 enum pipe pipe, bool state)
1095 {
1096         u32 val;
1097         bool cur_state;
1098
1099         val = I915_READ(DPLL(pipe));
1100         cur_state = !!(val & DPLL_VCO_ENABLE);
1101         I915_STATE_WARN(cur_state != state,
1102              "PLL state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105
1106 /* XXX: the dsi pll is shared between MIPI DSI ports */
1107 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111
1112         mutex_lock(&dev_priv->sb_lock);
1113         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1114         mutex_unlock(&dev_priv->sb_lock);
1115
1116         cur_state = val & DSI_PLL_VCO_EN;
1117         I915_STATE_WARN(cur_state != state,
1118              "DSI PLL state assertion failure (expected %s, current %s)\n",
1119                         onoff(state), onoff(cur_state));
1120 }
1121
1122 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1123                           enum pipe pipe, bool state)
1124 {
1125         bool cur_state;
1126         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1127                                                                       pipe);
1128
1129         if (HAS_DDI(dev_priv)) {
1130                 /* DDI does not have a specific FDI_TX register */
1131                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1135                 cur_state = !!(val & FDI_TX_ENABLE);
1136         }
1137         I915_STATE_WARN(cur_state != state,
1138              "FDI TX state assertion failure (expected %s, current %s)\n",
1139                         onoff(state), onoff(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         u32 val;
1148         bool cur_state;
1149
1150         val = I915_READ(FDI_RX_CTL(pipe));
1151         cur_state = !!(val & FDI_RX_ENABLE);
1152         I915_STATE_WARN(cur_state != state,
1153              "FDI RX state assertion failure (expected %s, current %s)\n",
1154                         onoff(state), onoff(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160                                       enum pipe pipe)
1161 {
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (IS_GEN5(dev_priv))
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv))
1170                 return;
1171
1172         val = I915_READ(FDI_TX_CTL(pipe));
1173         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1174 }
1175
1176 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1177                        enum pipe pipe, bool state)
1178 {
1179         u32 val;
1180         bool cur_state;
1181
1182         val = I915_READ(FDI_RX_CTL(pipe));
1183         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184         I915_STATE_WARN(cur_state != state,
1185              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186                         onoff(state), onoff(cur_state));
1187 }
1188
1189 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190                            enum pipe pipe)
1191 {
1192         struct drm_device *dev = &dev_priv->drm;
1193         i915_reg_t pp_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (WARN_ON(HAS_DDI(dev)))
1199                 return;
1200
1201         if (HAS_PCH_SPLIT(dev)) {
1202                 u32 port_sel;
1203
1204                 pp_reg = PCH_PP_CONTROL;
1205                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1206
1207                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1208                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1209                         panel_pipe = PIPE_B;
1210                 /* XXX: else fix for eDP */
1211         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1212                 /* presumably write lock depends on pipe, not port select */
1213                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1214                 panel_pipe = pipe;
1215         } else {
1216                 pp_reg = PP_CONTROL;
1217                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1218                         panel_pipe = PIPE_B;
1219         }
1220
1221         val = I915_READ(pp_reg);
1222         if (!(val & PANEL_POWER_ON) ||
1223             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1224                 locked = false;
1225
1226         I915_STATE_WARN(panel_pipe == pipe && locked,
1227              "panel assertion failure, pipe %c regs locked\n",
1228              pipe_name(pipe));
1229 }
1230
1231 static void assert_cursor(struct drm_i915_private *dev_priv,
1232                           enum pipe pipe, bool state)
1233 {
1234         struct drm_device *dev = &dev_priv->drm;
1235         bool cur_state;
1236
1237         if (IS_845G(dev) || IS_I865G(dev))
1238                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1239         else
1240                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244                         pipe_name(pipe), onoff(state), onoff(cur_state));
1245 }
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1248
1249 void assert_pipe(struct drm_i915_private *dev_priv,
1250                  enum pipe pipe, bool state)
1251 {
1252         bool cur_state;
1253         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1254                                                                       pipe);
1255         enum intel_display_power_domain power_domain;
1256
1257         /* if we need the pipe quirk it must be always on */
1258         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1259             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1260                 state = true;
1261
1262         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1263         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1264                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1265                 cur_state = !!(val & PIPECONF_ENABLE);
1266
1267                 intel_display_power_put(dev_priv, power_domain);
1268         } else {
1269                 cur_state = false;
1270         }
1271
1272         I915_STATE_WARN(cur_state != state,
1273              "pipe %c assertion failure (expected %s, current %s)\n",
1274                         pipe_name(pipe), onoff(state), onoff(cur_state));
1275 }
1276
1277 static void assert_plane(struct drm_i915_private *dev_priv,
1278                          enum plane plane, bool state)
1279 {
1280         u32 val;
1281         bool cur_state;
1282
1283         val = I915_READ(DSPCNTR(plane));
1284         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1285         I915_STATE_WARN(cur_state != state,
1286              "plane %c assertion failure (expected %s, current %s)\n",
1287                         plane_name(plane), onoff(state), onoff(cur_state));
1288 }
1289
1290 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1291 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1292
1293 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1294                                    enum pipe pipe)
1295 {
1296         struct drm_device *dev = &dev_priv->drm;
1297         int i;
1298
1299         /* Primary planes are fixed to pipes on gen4+ */
1300         if (INTEL_INFO(dev)->gen >= 4) {
1301                 u32 val = I915_READ(DSPCNTR(pipe));
1302                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1303                      "plane %c assertion failure, should be disabled but not\n",
1304                      plane_name(pipe));
1305                 return;
1306         }
1307
1308         /* Need to check both planes against the pipe */
1309         for_each_pipe(dev_priv, i) {
1310                 u32 val = I915_READ(DSPCNTR(i));
1311                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1312                         DISPPLANE_SEL_PIPE_SHIFT;
1313                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1314                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1315                      plane_name(i), pipe_name(pipe));
1316         }
1317 }
1318
1319 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1320                                     enum pipe pipe)
1321 {
1322         struct drm_device *dev = &dev_priv->drm;
1323         int sprite;
1324
1325         if (INTEL_INFO(dev)->gen >= 9) {
1326                 for_each_sprite(dev_priv, pipe, sprite) {
1327                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1328                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1329                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1330                              sprite, pipe_name(pipe));
1331                 }
1332         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1333                 for_each_sprite(dev_priv, pipe, sprite) {
1334                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1335                         I915_STATE_WARN(val & SP_ENABLE,
1336                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337                              sprite_name(pipe, sprite), pipe_name(pipe));
1338                 }
1339         } else if (INTEL_INFO(dev)->gen >= 7) {
1340                 u32 val = I915_READ(SPRCTL(pipe));
1341                 I915_STATE_WARN(val & SPRITE_ENABLE,
1342                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343                      plane_name(pipe), pipe_name(pipe));
1344         } else if (INTEL_INFO(dev)->gen >= 5) {
1345                 u32 val = I915_READ(DVSCNTR(pipe));
1346                 I915_STATE_WARN(val & DVS_ENABLE,
1347                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348                      plane_name(pipe), pipe_name(pipe));
1349         }
1350 }
1351
1352 static void assert_vblank_disabled(struct drm_crtc *crtc)
1353 {
1354         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1355                 drm_crtc_vblank_put(crtc);
1356 }
1357
1358 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359                                     enum pipe pipe)
1360 {
1361         u32 val;
1362         bool enabled;
1363
1364         val = I915_READ(PCH_TRANSCONF(pipe));
1365         enabled = !!(val & TRANS_ENABLE);
1366         I915_STATE_WARN(enabled,
1367              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1368              pipe_name(pipe));
1369 }
1370
1371 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1372                             enum pipe pipe, u32 port_sel, u32 val)
1373 {
1374         if ((val & DP_PORT_EN) == 0)
1375                 return false;
1376
1377         if (HAS_PCH_CPT(dev_priv)) {
1378                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1379                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380                         return false;
1381         } else if (IS_CHERRYVIEW(dev_priv)) {
1382                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386                         return false;
1387         }
1388         return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & SDVO_ENABLE) == 0)
1395                 return false;
1396
1397         if (HAS_PCH_CPT(dev_priv)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399                         return false;
1400         } else if (IS_CHERRYVIEW(dev_priv)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402                         return false;
1403         } else {
1404                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405                         return false;
1406         }
1407         return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411                               enum pipe pipe, u32 val)
1412 {
1413         if ((val & LVDS_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv)) {
1417                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418                         return false;
1419         } else {
1420                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421                         return false;
1422         }
1423         return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427                               enum pipe pipe, u32 val)
1428 {
1429         if ((val & ADPA_DAC_ENABLE) == 0)
1430                 return false;
1431         if (HAS_PCH_CPT(dev_priv)) {
1432                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433                         return false;
1434         } else {
1435                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436                         return false;
1437         }
1438         return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442                                    enum pipe pipe, i915_reg_t reg,
1443                                    u32 port_sel)
1444 {
1445         u32 val = I915_READ(reg);
1446         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1447              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448              i915_mmio_reg_offset(reg), pipe_name(pipe));
1449
1450         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1451              && (val & DP_PIPEB_SELECT),
1452              "IBX PCH dp port still using transcoder B\n");
1453 }
1454
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1456                                      enum pipe pipe, i915_reg_t reg)
1457 {
1458         u32 val = I915_READ(reg);
1459         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1460              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461              i915_mmio_reg_offset(reg), pipe_name(pipe));
1462
1463         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1464              && (val & SDVO_PIPE_B_SELECT),
1465              "IBX PCH hdmi port still using transcoder B\n");
1466 }
1467
1468 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469                                       enum pipe pipe)
1470 {
1471         u32 val;
1472
1473         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477         val = I915_READ(PCH_ADPA);
1478         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479              "PCH VGA enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         val = I915_READ(PCH_LVDS);
1483         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1484              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485              pipe_name(pipe));
1486
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 }
1491
1492 static void _vlv_enable_pll(struct intel_crtc *crtc,
1493                             const struct intel_crtc_state *pipe_config)
1494 {
1495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1496         enum pipe pipe = crtc->pipe;
1497
1498         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1499         POSTING_READ(DPLL(pipe));
1500         udelay(150);
1501
1502         if (intel_wait_for_register(dev_priv,
1503                                     DPLL(pipe),
1504                                     DPLL_LOCK_VLV,
1505                                     DPLL_LOCK_VLV,
1506                                     1))
1507                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1514         enum pipe pipe = crtc->pipe;
1515
1516         assert_pipe_disabled(dev_priv, pipe);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         assert_panel_unlocked(dev_priv, pipe);
1520
1521         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1522                 _vlv_enable_pll(crtc, pipe_config);
1523
1524         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1525         POSTING_READ(DPLL_MD(pipe));
1526 }
1527
1528
1529 static void _chv_enable_pll(struct intel_crtc *crtc,
1530                             const struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533         enum pipe pipe = crtc->pipe;
1534         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1535         u32 tmp;
1536
1537         mutex_lock(&dev_priv->sb_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         mutex_unlock(&dev_priv->sb_lock);
1545
1546         /*
1547          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1548          */
1549         udelay(1);
1550
1551         /* Enable PLL */
1552         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1553
1554         /* Check PLL is locked */
1555         if (intel_wait_for_register(dev_priv,
1556                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1557                                     1))
1558                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1559 }
1560
1561 static void chv_enable_pll(struct intel_crtc *crtc,
1562                            const struct intel_crtc_state *pipe_config)
1563 {
1564         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1565         enum pipe pipe = crtc->pipe;
1566
1567         assert_pipe_disabled(dev_priv, pipe);
1568
1569         /* PLL is protected by panel, make sure we can write it */
1570         assert_panel_unlocked(dev_priv, pipe);
1571
1572         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1573                 _chv_enable_pll(crtc, pipe_config);
1574
1575         if (pipe != PIPE_A) {
1576                 /*
1577                  * WaPixelRepeatModeFixForC0:chv
1578                  *
1579                  * DPLLCMD is AWOL. Use chicken bits to propagate
1580                  * the value from DPLLBMD to either pipe B or C.
1581                  */
1582                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1583                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1584                 I915_WRITE(CBR4_VLV, 0);
1585                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1586
1587                 /*
1588                  * DPLLB VGA mode also seems to cause problems.
1589                  * We should always have it disabled.
1590                  */
1591                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1592         } else {
1593                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1594                 POSTING_READ(DPLL_MD(pipe));
1595         }
1596 }
1597
1598 static int intel_num_dvo_pipes(struct drm_device *dev)
1599 {
1600         struct intel_crtc *crtc;
1601         int count = 0;
1602
1603         for_each_intel_crtc(dev, crtc) {
1604                 count += crtc->base.state->active &&
1605                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1606         }
1607
1608         return count;
1609 }
1610
1611 static void i9xx_enable_pll(struct intel_crtc *crtc)
1612 {
1613         struct drm_device *dev = crtc->base.dev;
1614         struct drm_i915_private *dev_priv = to_i915(dev);
1615         i915_reg_t reg = DPLL(crtc->pipe);
1616         u32 dpll = crtc->config->dpll_hw_state.dpll;
1617
1618         assert_pipe_disabled(dev_priv, crtc->pipe);
1619
1620         /* PLL is protected by panel, make sure we can write it */
1621         if (IS_MOBILE(dev) && !IS_I830(dev))
1622                 assert_panel_unlocked(dev_priv, crtc->pipe);
1623
1624         /* Enable DVO 2x clock on both PLLs if necessary */
1625         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1626                 /*
1627                  * It appears to be important that we don't enable this
1628                  * for the current pipe before otherwise configuring the
1629                  * PLL. No idea how this should be handled if multiple
1630                  * DVO outputs are enabled simultaneosly.
1631                  */
1632                 dpll |= DPLL_DVO_2X_MODE;
1633                 I915_WRITE(DPLL(!crtc->pipe),
1634                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1635         }
1636
1637         /*
1638          * Apparently we need to have VGA mode enabled prior to changing
1639          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1640          * dividers, even though the register value does change.
1641          */
1642         I915_WRITE(reg, 0);
1643
1644         I915_WRITE(reg, dpll);
1645
1646         /* Wait for the clocks to stabilize. */
1647         POSTING_READ(reg);
1648         udelay(150);
1649
1650         if (INTEL_INFO(dev)->gen >= 4) {
1651                 I915_WRITE(DPLL_MD(crtc->pipe),
1652                            crtc->config->dpll_hw_state.dpll_md);
1653         } else {
1654                 /* The pixel multiplier can only be updated once the
1655                  * DPLL is enabled and the clocks are stable.
1656                  *
1657                  * So write it again.
1658                  */
1659                 I915_WRITE(reg, dpll);
1660         }
1661
1662         /* We do this three times for luck */
1663         I915_WRITE(reg, dpll);
1664         POSTING_READ(reg);
1665         udelay(150); /* wait for warmup */
1666         I915_WRITE(reg, dpll);
1667         POSTING_READ(reg);
1668         udelay(150); /* wait for warmup */
1669         I915_WRITE(reg, dpll);
1670         POSTING_READ(reg);
1671         udelay(150); /* wait for warmup */
1672 }
1673
1674 /**
1675  * i9xx_disable_pll - disable a PLL
1676  * @dev_priv: i915 private structure
1677  * @pipe: pipe PLL to disable
1678  *
1679  * Disable the PLL for @pipe, making sure the pipe is off first.
1680  *
1681  * Note!  This is for pre-ILK only.
1682  */
1683 static void i9xx_disable_pll(struct intel_crtc *crtc)
1684 {
1685         struct drm_device *dev = crtc->base.dev;
1686         struct drm_i915_private *dev_priv = to_i915(dev);
1687         enum pipe pipe = crtc->pipe;
1688
1689         /* Disable DVO 2x clock on both PLLs if necessary */
1690         if (IS_I830(dev) &&
1691             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1692             !intel_num_dvo_pipes(dev)) {
1693                 I915_WRITE(DPLL(PIPE_B),
1694                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1695                 I915_WRITE(DPLL(PIPE_A),
1696                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1697         }
1698
1699         /* Don't disable pipe or pipe PLLs if needed */
1700         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1701             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1702                 return;
1703
1704         /* Make sure the pipe isn't still relying on us */
1705         assert_pipe_disabled(dev_priv, pipe);
1706
1707         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1708         POSTING_READ(DPLL(pipe));
1709 }
1710
1711 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713         u32 val;
1714
1715         /* Make sure the pipe isn't still relying on us */
1716         assert_pipe_disabled(dev_priv, pipe);
1717
1718         val = DPLL_INTEGRATED_REF_CLK_VLV |
1719                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1720         if (pipe != PIPE_A)
1721                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1722
1723         I915_WRITE(DPLL(pipe), val);
1724         POSTING_READ(DPLL(pipe));
1725 }
1726
1727 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1728 {
1729         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1730         u32 val;
1731
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734
1735         val = DPLL_SSC_REF_CLK_CHV |
1736                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737         if (pipe != PIPE_A)
1738                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740         I915_WRITE(DPLL(pipe), val);
1741         POSTING_READ(DPLL(pipe));
1742
1743         mutex_lock(&dev_priv->sb_lock);
1744
1745         /* Disable 10bit clock to display controller */
1746         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1747         val &= ~DPIO_DCLKP_EN;
1748         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1749
1750         mutex_unlock(&dev_priv->sb_lock);
1751 }
1752
1753 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1754                          struct intel_digital_port *dport,
1755                          unsigned int expected_mask)
1756 {
1757         u32 port_mask;
1758         i915_reg_t dpll_reg;
1759
1760         switch (dport->port) {
1761         case PORT_B:
1762                 port_mask = DPLL_PORTB_READY_MASK;
1763                 dpll_reg = DPLL(0);
1764                 break;
1765         case PORT_C:
1766                 port_mask = DPLL_PORTC_READY_MASK;
1767                 dpll_reg = DPLL(0);
1768                 expected_mask <<= 4;
1769                 break;
1770         case PORT_D:
1771                 port_mask = DPLL_PORTD_READY_MASK;
1772                 dpll_reg = DPIO_PHY_STATUS;
1773                 break;
1774         default:
1775                 BUG();
1776         }
1777
1778         if (intel_wait_for_register(dev_priv,
1779                                     dpll_reg, port_mask, expected_mask,
1780                                     1000))
1781                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1782                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1783 }
1784
1785 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1786                                            enum pipe pipe)
1787 {
1788         struct drm_device *dev = &dev_priv->drm;
1789         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         i915_reg_t reg;
1792         uint32_t val, pipeconf_val;
1793
1794         /* Make sure PCH DPLL is enabled */
1795         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1796
1797         /* FDI must be feeding us bits for PCH ports */
1798         assert_fdi_tx_enabled(dev_priv, pipe);
1799         assert_fdi_rx_enabled(dev_priv, pipe);
1800
1801         if (HAS_PCH_CPT(dev)) {
1802                 /* Workaround: Set the timing override bit before enabling the
1803                  * pch transcoder. */
1804                 reg = TRANS_CHICKEN2(pipe);
1805                 val = I915_READ(reg);
1806                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1807                 I915_WRITE(reg, val);
1808         }
1809
1810         reg = PCH_TRANSCONF(pipe);
1811         val = I915_READ(reg);
1812         pipeconf_val = I915_READ(PIPECONF(pipe));
1813
1814         if (HAS_PCH_IBX(dev_priv)) {
1815                 /*
1816                  * Make the BPC in transcoder be consistent with
1817                  * that in pipeconf reg. For HDMI we must use 8bpc
1818                  * here for both 8bpc and 12bpc.
1819                  */
1820                 val &= ~PIPECONF_BPC_MASK;
1821                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1822                         val |= PIPECONF_8BPC;
1823                 else
1824                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1825         }
1826
1827         val &= ~TRANS_INTERLACE_MASK;
1828         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1829                 if (HAS_PCH_IBX(dev_priv) &&
1830                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1831                         val |= TRANS_LEGACY_INTERLACED_ILK;
1832                 else
1833                         val |= TRANS_INTERLACED;
1834         else
1835                 val |= TRANS_PROGRESSIVE;
1836
1837         I915_WRITE(reg, val | TRANS_ENABLE);
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1840                                     100))
1841                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1842 }
1843
1844 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1845                                       enum transcoder cpu_transcoder)
1846 {
1847         u32 val, pipeconf_val;
1848
1849         /* FDI must be feeding us bits for PCH ports */
1850         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1851         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1852
1853         /* Workaround: set timing override bit. */
1854         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1855         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1857
1858         val = TRANS_ENABLE;
1859         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1860
1861         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1862             PIPECONF_INTERLACED_ILK)
1863                 val |= TRANS_INTERLACED;
1864         else
1865                 val |= TRANS_PROGRESSIVE;
1866
1867         I915_WRITE(LPT_TRANSCONF, val);
1868         if (intel_wait_for_register(dev_priv,
1869                                     LPT_TRANSCONF,
1870                                     TRANS_STATE_ENABLE,
1871                                     TRANS_STATE_ENABLE,
1872                                     100))
1873                 DRM_ERROR("Failed to enable PCH transcoder\n");
1874 }
1875
1876 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1877                                             enum pipe pipe)
1878 {
1879         struct drm_device *dev = &dev_priv->drm;
1880         i915_reg_t reg;
1881         uint32_t val;
1882
1883         /* FDI relies on the transcoder */
1884         assert_fdi_tx_disabled(dev_priv, pipe);
1885         assert_fdi_rx_disabled(dev_priv, pipe);
1886
1887         /* Ports must be off as well */
1888         assert_pch_ports_disabled(dev_priv, pipe);
1889
1890         reg = PCH_TRANSCONF(pipe);
1891         val = I915_READ(reg);
1892         val &= ~TRANS_ENABLE;
1893         I915_WRITE(reg, val);
1894         /* wait for PCH transcoder off, transcoder state */
1895         if (intel_wait_for_register(dev_priv,
1896                                     reg, TRANS_STATE_ENABLE, 0,
1897                                     50))
1898                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1899
1900         if (HAS_PCH_CPT(dev)) {
1901                 /* Workaround: Clear the timing override chicken bit again. */
1902                 reg = TRANS_CHICKEN2(pipe);
1903                 val = I915_READ(reg);
1904                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1905                 I915_WRITE(reg, val);
1906         }
1907 }
1908
1909 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1910 {
1911         u32 val;
1912
1913         val = I915_READ(LPT_TRANSCONF);
1914         val &= ~TRANS_ENABLE;
1915         I915_WRITE(LPT_TRANSCONF, val);
1916         /* wait for PCH transcoder off, transcoder state */
1917         if (intel_wait_for_register(dev_priv,
1918                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1919                                     50))
1920                 DRM_ERROR("Failed to disable PCH transcoder\n");
1921
1922         /* Workaround: clear timing override bit. */
1923         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1924         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1925         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1926 }
1927
1928 /**
1929  * intel_enable_pipe - enable a pipe, asserting requirements
1930  * @crtc: crtc responsible for the pipe
1931  *
1932  * Enable @crtc's pipe, making sure that various hardware specific requirements
1933  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1934  */
1935 static void intel_enable_pipe(struct intel_crtc *crtc)
1936 {
1937         struct drm_device *dev = crtc->base.dev;
1938         struct drm_i915_private *dev_priv = to_i915(dev);
1939         enum pipe pipe = crtc->pipe;
1940         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1941         enum pipe pch_transcoder;
1942         i915_reg_t reg;
1943         u32 val;
1944
1945         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1946
1947         assert_planes_disabled(dev_priv, pipe);
1948         assert_cursor_disabled(dev_priv, pipe);
1949         assert_sprites_disabled(dev_priv, pipe);
1950
1951         if (HAS_PCH_LPT(dev_priv))
1952                 pch_transcoder = TRANSCODER_A;
1953         else
1954                 pch_transcoder = pipe;
1955
1956         /*
1957          * A pipe without a PLL won't actually be able to drive bits from
1958          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1959          * need the check.
1960          */
1961         if (HAS_GMCH_DISPLAY(dev_priv))
1962                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1963                         assert_dsi_pll_enabled(dev_priv);
1964                 else
1965                         assert_pll_enabled(dev_priv, pipe);
1966         else {
1967                 if (crtc->config->has_pch_encoder) {
1968                         /* if driving the PCH, we need FDI enabled */
1969                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1970                         assert_fdi_tx_pll_enabled(dev_priv,
1971                                                   (enum pipe) cpu_transcoder);
1972                 }
1973                 /* FIXME: assert CPU port conditions for SNB+ */
1974         }
1975
1976         reg = PIPECONF(cpu_transcoder);
1977         val = I915_READ(reg);
1978         if (val & PIPECONF_ENABLE) {
1979                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1980                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1981                 return;
1982         }
1983
1984         I915_WRITE(reg, val | PIPECONF_ENABLE);
1985         POSTING_READ(reg);
1986
1987         /*
1988          * Until the pipe starts DSL will read as 0, which would cause
1989          * an apparent vblank timestamp jump, which messes up also the
1990          * frame count when it's derived from the timestamps. So let's
1991          * wait for the pipe to start properly before we call
1992          * drm_crtc_vblank_on()
1993          */
1994         if (dev->max_vblank_count == 0 &&
1995             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1996                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1997 }
1998
1999 /**
2000  * intel_disable_pipe - disable a pipe, asserting requirements
2001  * @crtc: crtc whose pipes is to be disabled
2002  *
2003  * Disable the pipe of @crtc, making sure that various hardware
2004  * specific requirements are met, if applicable, e.g. plane
2005  * disabled, panel fitter off, etc.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2012         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2013         enum pipe pipe = crtc->pipe;
2014         i915_reg_t reg;
2015         u32 val;
2016
2017         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2018
2019         /*
2020          * Make sure planes won't keep trying to pump pixels to us,
2021          * or we might hang the display.
2022          */
2023         assert_planes_disabled(dev_priv, pipe);
2024         assert_cursor_disabled(dev_priv, pipe);
2025         assert_sprites_disabled(dev_priv, pipe);
2026
2027         reg = PIPECONF(cpu_transcoder);
2028         val = I915_READ(reg);
2029         if ((val & PIPECONF_ENABLE) == 0)
2030                 return;
2031
2032         /*
2033          * Double wide has implications for planes
2034          * so best keep it disabled when not needed.
2035          */
2036         if (crtc->config->double_wide)
2037                 val &= ~PIPECONF_DOUBLE_WIDE;
2038
2039         /* Don't disable pipe or pipe PLLs if needed */
2040         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2041             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2042                 val &= ~PIPECONF_ENABLE;
2043
2044         I915_WRITE(reg, val);
2045         if ((val & PIPECONF_ENABLE) == 0)
2046                 intel_wait_for_pipe_off(crtc);
2047 }
2048
2049 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2050 {
2051         return IS_GEN2(dev_priv) ? 2048 : 4096;
2052 }
2053
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2055                                            uint64_t fb_modifier, unsigned int cpp)
2056 {
2057         switch (fb_modifier) {
2058         case DRM_FORMAT_MOD_NONE:
2059                 return cpp;
2060         case I915_FORMAT_MOD_X_TILED:
2061                 if (IS_GEN2(dev_priv))
2062                         return 128;
2063                 else
2064                         return 512;
2065         case I915_FORMAT_MOD_Y_TILED:
2066                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2067                         return 128;
2068                 else
2069                         return 512;
2070         case I915_FORMAT_MOD_Yf_TILED:
2071                 switch (cpp) {
2072                 case 1:
2073                         return 64;
2074                 case 2:
2075                 case 4:
2076                         return 128;
2077                 case 8:
2078                 case 16:
2079                         return 256;
2080                 default:
2081                         MISSING_CASE(cpp);
2082                         return cpp;
2083                 }
2084                 break;
2085         default:
2086                 MISSING_CASE(fb_modifier);
2087                 return cpp;
2088         }
2089 }
2090
2091 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2092                                uint64_t fb_modifier, unsigned int cpp)
2093 {
2094         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2095                 return 1;
2096         else
2097                 return intel_tile_size(dev_priv) /
2098                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2099 }
2100
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2103                             unsigned int *tile_width,
2104                             unsigned int *tile_height,
2105                             uint64_t fb_modifier,
2106                             unsigned int cpp)
2107 {
2108         unsigned int tile_width_bytes =
2109                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2110
2111         *tile_width = tile_width_bytes / cpp;
2112         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2113 }
2114
2115 unsigned int
2116 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2117                       uint32_t pixel_format, uint64_t fb_modifier)
2118 {
2119         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2120         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2121
2122         return ALIGN(height, tile_height);
2123 }
2124
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2126 {
2127         unsigned int size = 0;
2128         int i;
2129
2130         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2131                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2132
2133         return size;
2134 }
2135
2136 static void
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2138                         const struct drm_framebuffer *fb,
2139                         unsigned int rotation)
2140 {
2141         if (intel_rotation_90_or_270(rotation)) {
2142                 *view = i915_ggtt_view_rotated;
2143                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2144         } else {
2145                 *view = i915_ggtt_view_normal;
2146         }
2147 }
2148
2149 static void
2150 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2151                    struct drm_framebuffer *fb)
2152 {
2153         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2154         unsigned int tile_size, tile_width, tile_height, cpp;
2155
2156         tile_size = intel_tile_size(dev_priv);
2157
2158         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2159         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2160                         fb->modifier[0], cpp);
2161
2162         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2163         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2164
2165         if (info->pixel_format == DRM_FORMAT_NV12) {
2166                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2167                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2168                                 fb->modifier[1], cpp);
2169
2170                 info->uv_offset = fb->offsets[1];
2171                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2172                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2173         }
2174 }
2175
2176 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2177 {
2178         if (INTEL_INFO(dev_priv)->gen >= 9)
2179                 return 256 * 1024;
2180         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2181                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2182                 return 128 * 1024;
2183         else if (INTEL_INFO(dev_priv)->gen >= 4)
2184                 return 4 * 1024;
2185         else
2186                 return 0;
2187 }
2188
2189 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2190                                          uint64_t fb_modifier)
2191 {
2192         switch (fb_modifier) {
2193         case DRM_FORMAT_MOD_NONE:
2194                 return intel_linear_alignment(dev_priv);
2195         case I915_FORMAT_MOD_X_TILED:
2196                 if (INTEL_INFO(dev_priv)->gen >= 9)
2197                         return 256 * 1024;
2198                 return 0;
2199         case I915_FORMAT_MOD_Y_TILED:
2200         case I915_FORMAT_MOD_Yf_TILED:
2201                 return 1 * 1024 * 1024;
2202         default:
2203                 MISSING_CASE(fb_modifier);
2204                 return 0;
2205         }
2206 }
2207
2208 int
2209 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2210                            unsigned int rotation)
2211 {
2212         struct drm_device *dev = fb->dev;
2213         struct drm_i915_private *dev_priv = to_i915(dev);
2214         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2215         struct i915_ggtt_view view;
2216         u32 alignment;
2217         int ret;
2218
2219         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2220
2221         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2222
2223         intel_fill_fb_ggtt_view(&view, fb, rotation);
2224
2225         /* Note that the w/a also requires 64 PTE of padding following the
2226          * bo. We currently fill all unused PTE with the shadow page and so
2227          * we should always have valid PTE following the scanout preventing
2228          * the VT-d warning.
2229          */
2230         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2231                 alignment = 256 * 1024;
2232
2233         /*
2234          * Global gtt pte registers are special registers which actually forward
2235          * writes to a chunk of system memory. Which means that there is no risk
2236          * that the register values disappear as soon as we call
2237          * intel_runtime_pm_put(), so it is correct to wrap only the
2238          * pin/unpin/fence and not more.
2239          */
2240         intel_runtime_pm_get(dev_priv);
2241
2242         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2243                                                    &view);
2244         if (ret)
2245                 goto err_pm;
2246
2247         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2248          * fence, whereas 965+ only requires a fence if using
2249          * framebuffer compression.  For simplicity, we always install
2250          * a fence as the cost is not that onerous.
2251          */
2252         if (view.type == I915_GGTT_VIEW_NORMAL) {
2253                 ret = i915_gem_object_get_fence(obj);
2254                 if (ret == -EDEADLK) {
2255                         /*
2256                          * -EDEADLK means there are no free fences
2257                          * no pending flips.
2258                          *
2259                          * This is propagated to atomic, but it uses
2260                          * -EDEADLK to force a locking recovery, so
2261                          * change the returned error to -EBUSY.
2262                          */
2263                         ret = -EBUSY;
2264                         goto err_unpin;
2265                 } else if (ret)
2266                         goto err_unpin;
2267
2268                 i915_gem_object_pin_fence(obj);
2269         }
2270
2271         intel_runtime_pm_put(dev_priv);
2272         return 0;
2273
2274 err_unpin:
2275         i915_gem_object_unpin_from_display_plane(obj, &view);
2276 err_pm:
2277         intel_runtime_pm_put(dev_priv);
2278         return ret;
2279 }
2280
2281 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2282 {
2283         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2284         struct i915_ggtt_view view;
2285
2286         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2287
2288         intel_fill_fb_ggtt_view(&view, fb, rotation);
2289
2290         if (view.type == I915_GGTT_VIEW_NORMAL)
2291                 i915_gem_object_unpin_fence(obj);
2292
2293         i915_gem_object_unpin_from_display_plane(obj, &view);
2294 }
2295
2296 /*
2297  * Adjust the tile offset by moving the difference into
2298  * the x/y offsets.
2299  *
2300  * Input tile dimensions and pitch must already be
2301  * rotated to match x and y, and in pixel units.
2302  */
2303 static u32 intel_adjust_tile_offset(int *x, int *y,
2304                                     unsigned int tile_width,
2305                                     unsigned int tile_height,
2306                                     unsigned int tile_size,
2307                                     unsigned int pitch_tiles,
2308                                     u32 old_offset,
2309                                     u32 new_offset)
2310 {
2311         unsigned int tiles;
2312
2313         WARN_ON(old_offset & (tile_size - 1));
2314         WARN_ON(new_offset & (tile_size - 1));
2315         WARN_ON(new_offset > old_offset);
2316
2317         tiles = (old_offset - new_offset) / tile_size;
2318
2319         *y += tiles / pitch_tiles * tile_height;
2320         *x += tiles % pitch_tiles * tile_width;
2321
2322         return new_offset;
2323 }
2324
2325 /*
2326  * Computes the linear offset to the base tile and adjusts
2327  * x, y. bytes per pixel is assumed to be a power-of-two.
2328  *
2329  * In the 90/270 rotated case, x and y are assumed
2330  * to be already rotated to match the rotated GTT view, and
2331  * pitch is the tile_height aligned framebuffer height.
2332  */
2333 u32 intel_compute_tile_offset(int *x, int *y,
2334                               const struct drm_framebuffer *fb, int plane,
2335                               unsigned int pitch,
2336                               unsigned int rotation)
2337 {
2338         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2339         uint64_t fb_modifier = fb->modifier[plane];
2340         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2341         u32 offset, offset_aligned, alignment;
2342
2343         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2344         if (alignment)
2345                 alignment--;
2346
2347         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2348                 unsigned int tile_size, tile_width, tile_height;
2349                 unsigned int tile_rows, tiles, pitch_tiles;
2350
2351                 tile_size = intel_tile_size(dev_priv);
2352                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2353                                 fb_modifier, cpp);
2354
2355                 if (intel_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                          tile_size, pitch_tiles,
2373                                          offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 static int i9xx_format_to_fourcc(int format)
2386 {
2387         switch (format) {
2388         case DISPPLANE_8BPP:
2389                 return DRM_FORMAT_C8;
2390         case DISPPLANE_BGRX555:
2391                 return DRM_FORMAT_XRGB1555;
2392         case DISPPLANE_BGRX565:
2393                 return DRM_FORMAT_RGB565;
2394         default:
2395         case DISPPLANE_BGRX888:
2396                 return DRM_FORMAT_XRGB8888;
2397         case DISPPLANE_RGBX888:
2398                 return DRM_FORMAT_XBGR8888;
2399         case DISPPLANE_BGRX101010:
2400                 return DRM_FORMAT_XRGB2101010;
2401         case DISPPLANE_RGBX101010:
2402                 return DRM_FORMAT_XBGR2101010;
2403         }
2404 }
2405
2406 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2407 {
2408         switch (format) {
2409         case PLANE_CTL_FORMAT_RGB_565:
2410                 return DRM_FORMAT_RGB565;
2411         default:
2412         case PLANE_CTL_FORMAT_XRGB_8888:
2413                 if (rgb_order) {
2414                         if (alpha)
2415                                 return DRM_FORMAT_ABGR8888;
2416                         else
2417                                 return DRM_FORMAT_XBGR8888;
2418                 } else {
2419                         if (alpha)
2420                                 return DRM_FORMAT_ARGB8888;
2421                         else
2422                                 return DRM_FORMAT_XRGB8888;
2423                 }
2424         case PLANE_CTL_FORMAT_XRGB_2101010:
2425                 if (rgb_order)
2426                         return DRM_FORMAT_XBGR2101010;
2427                 else
2428                         return DRM_FORMAT_XRGB2101010;
2429         }
2430 }
2431
2432 static bool
2433 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2434                               struct intel_initial_plane_config *plane_config)
2435 {
2436         struct drm_device *dev = crtc->base.dev;
2437         struct drm_i915_private *dev_priv = to_i915(dev);
2438         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2439         struct drm_i915_gem_object *obj = NULL;
2440         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2441         struct drm_framebuffer *fb = &plane_config->fb->base;
2442         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2443         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2444                                     PAGE_SIZE);
2445
2446         size_aligned -= base_aligned;
2447
2448         if (plane_config->size == 0)
2449                 return false;
2450
2451         /* If the FB is too big, just don't use it since fbdev is not very
2452          * important and we should probably use that space with FBC or other
2453          * features. */
2454         if (size_aligned * 2 > ggtt->stolen_usable_size)
2455                 return false;
2456
2457         mutex_lock(&dev->struct_mutex);
2458
2459         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2460                                                              base_aligned,
2461                                                              base_aligned,
2462                                                              size_aligned);
2463         if (!obj) {
2464                 mutex_unlock(&dev->struct_mutex);
2465                 return false;
2466         }
2467
2468         obj->tiling_mode = plane_config->tiling;
2469         if (obj->tiling_mode == I915_TILING_X)
2470                 obj->stride = fb->pitches[0];
2471
2472         mode_cmd.pixel_format = fb->pixel_format;
2473         mode_cmd.width = fb->width;
2474         mode_cmd.height = fb->height;
2475         mode_cmd.pitches[0] = fb->pitches[0];
2476         mode_cmd.modifier[0] = fb->modifier[0];
2477         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2478
2479         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2480                                    &mode_cmd, obj)) {
2481                 DRM_DEBUG_KMS("intel fb init failed\n");
2482                 goto out_unref_obj;
2483         }
2484
2485         mutex_unlock(&dev->struct_mutex);
2486
2487         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2488         return true;
2489
2490 out_unref_obj:
2491         drm_gem_object_unreference(&obj->base);
2492         mutex_unlock(&dev->struct_mutex);
2493         return false;
2494 }
2495
2496 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2497 static void
2498 update_state_fb(struct drm_plane *plane)
2499 {
2500         if (plane->fb == plane->state->fb)
2501                 return;
2502
2503         if (plane->state->fb)
2504                 drm_framebuffer_unreference(plane->state->fb);
2505         plane->state->fb = plane->fb;
2506         if (plane->state->fb)
2507                 drm_framebuffer_reference(plane->state->fb);
2508 }
2509
2510 static void
2511 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2512                              struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = intel_crtc->base.dev;
2515         struct drm_i915_private *dev_priv = to_i915(dev);
2516         struct drm_crtc *c;
2517         struct intel_crtc *i;
2518         struct drm_i915_gem_object *obj;
2519         struct drm_plane *primary = intel_crtc->base.primary;
2520         struct drm_plane_state *plane_state = primary->state;
2521         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2522         struct intel_plane *intel_plane = to_intel_plane(primary);
2523         struct intel_plane_state *intel_state =
2524                 to_intel_plane_state(plane_state);
2525         struct drm_framebuffer *fb;
2526
2527         if (!plane_config->fb)
2528                 return;
2529
2530         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2531                 fb = &plane_config->fb->base;
2532                 goto valid_fb;
2533         }
2534
2535         kfree(plane_config->fb);
2536
2537         /*
2538          * Failed to alloc the obj, check to see if we should share
2539          * an fb with another CRTC instead
2540          */
2541         for_each_crtc(dev, c) {
2542                 i = to_intel_crtc(c);
2543
2544                 if (c == &intel_crtc->base)
2545                         continue;
2546
2547                 if (!i->active)
2548                         continue;
2549
2550                 fb = c->primary->fb;
2551                 if (!fb)
2552                         continue;
2553
2554                 obj = intel_fb_obj(fb);
2555                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2556                         drm_framebuffer_reference(fb);
2557                         goto valid_fb;
2558                 }
2559         }
2560
2561         /*
2562          * We've failed to reconstruct the BIOS FB.  Current display state
2563          * indicates that the primary plane is visible, but has a NULL FB,
2564          * which will lead to problems later if we don't fix it up.  The
2565          * simplest solution is to just disable the primary plane now and
2566          * pretend the BIOS never had it enabled.
2567          */
2568         to_intel_plane_state(plane_state)->visible = false;
2569         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2570         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2571         intel_plane->disable_plane(primary, &intel_crtc->base);
2572
2573         return;
2574
2575 valid_fb:
2576         plane_state->src_x = 0;
2577         plane_state->src_y = 0;
2578         plane_state->src_w = fb->width << 16;
2579         plane_state->src_h = fb->height << 16;
2580
2581         plane_state->crtc_x = 0;
2582         plane_state->crtc_y = 0;
2583         plane_state->crtc_w = fb->width;
2584         plane_state->crtc_h = fb->height;
2585
2586         intel_state->src.x1 = plane_state->src_x;
2587         intel_state->src.y1 = plane_state->src_y;
2588         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2589         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2590         intel_state->dst.x1 = plane_state->crtc_x;
2591         intel_state->dst.y1 = plane_state->crtc_y;
2592         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2593         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2594
2595         obj = intel_fb_obj(fb);
2596         if (obj->tiling_mode != I915_TILING_NONE)
2597                 dev_priv->preserve_bios_swizzle = true;
2598
2599         drm_framebuffer_reference(fb);
2600         primary->fb = primary->state->fb = fb;
2601         primary->crtc = primary->state->crtc = &intel_crtc->base;
2602         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2603         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2604 }
2605
2606 static void i9xx_update_primary_plane(struct drm_plane *primary,
2607                                       const struct intel_crtc_state *crtc_state,
2608                                       const struct intel_plane_state *plane_state)
2609 {
2610         struct drm_device *dev = primary->dev;
2611         struct drm_i915_private *dev_priv = to_i915(dev);
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2613         struct drm_framebuffer *fb = plane_state->base.fb;
2614         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2615         int plane = intel_crtc->plane;
2616         u32 linear_offset;
2617         u32 dspcntr;
2618         i915_reg_t reg = DSPCNTR(plane);
2619         unsigned int rotation = plane_state->base.rotation;
2620         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2621         int x = plane_state->src.x1 >> 16;
2622         int y = plane_state->src.y1 >> 16;
2623
2624         dspcntr = DISPPLANE_GAMMA_ENABLE;
2625
2626         dspcntr |= DISPLAY_PLANE_ENABLE;
2627
2628         if (INTEL_INFO(dev)->gen < 4) {
2629                 if (intel_crtc->pipe == PIPE_B)
2630                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2631
2632                 /* pipesrc and dspsize control the size that is scaled from,
2633                  * which should always be the user's requested size.
2634                  */
2635                 I915_WRITE(DSPSIZE(plane),
2636                            ((crtc_state->pipe_src_h - 1) << 16) |
2637                            (crtc_state->pipe_src_w - 1));
2638                 I915_WRITE(DSPPOS(plane), 0);
2639         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2640                 I915_WRITE(PRIMSIZE(plane),
2641                            ((crtc_state->pipe_src_h - 1) << 16) |
2642                            (crtc_state->pipe_src_w - 1));
2643                 I915_WRITE(PRIMPOS(plane), 0);
2644                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2645         }
2646
2647         switch (fb->pixel_format) {
2648         case DRM_FORMAT_C8:
2649                 dspcntr |= DISPPLANE_8BPP;
2650                 break;
2651         case DRM_FORMAT_XRGB1555:
2652                 dspcntr |= DISPPLANE_BGRX555;
2653                 break;
2654         case DRM_FORMAT_RGB565:
2655                 dspcntr |= DISPPLANE_BGRX565;
2656                 break;
2657         case DRM_FORMAT_XRGB8888:
2658                 dspcntr |= DISPPLANE_BGRX888;
2659                 break;
2660         case DRM_FORMAT_XBGR8888:
2661                 dspcntr |= DISPPLANE_RGBX888;
2662                 break;
2663         case DRM_FORMAT_XRGB2101010:
2664                 dspcntr |= DISPPLANE_BGRX101010;
2665                 break;
2666         case DRM_FORMAT_XBGR2101010:
2667                 dspcntr |= DISPPLANE_RGBX101010;
2668                 break;
2669         default:
2670                 BUG();
2671         }
2672
2673         if (INTEL_INFO(dev)->gen >= 4 &&
2674             obj->tiling_mode != I915_TILING_NONE)
2675                 dspcntr |= DISPPLANE_TILED;
2676
2677         if (IS_G4X(dev))
2678                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2679
2680         linear_offset = y * fb->pitches[0] + x * cpp;
2681
2682         if (INTEL_INFO(dev)->gen >= 4) {
2683                 intel_crtc->dspaddr_offset =
2684                         intel_compute_tile_offset(&x, &y, fb, 0,
2685                                                   fb->pitches[0], rotation);
2686                 linear_offset -= intel_crtc->dspaddr_offset;
2687         } else {
2688                 intel_crtc->dspaddr_offset = linear_offset;
2689         }
2690
2691         if (rotation == BIT(DRM_ROTATE_180)) {
2692                 dspcntr |= DISPPLANE_ROTATE_180;
2693
2694                 x += (crtc_state->pipe_src_w - 1);
2695                 y += (crtc_state->pipe_src_h - 1);
2696
2697                 /* Finding the last pixel of the last line of the display
2698                 data and adding to linear_offset*/
2699                 linear_offset +=
2700                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2701                         (crtc_state->pipe_src_w - 1) * cpp;
2702         }
2703
2704         intel_crtc->adjusted_x = x;
2705         intel_crtc->adjusted_y = y;
2706
2707         I915_WRITE(reg, dspcntr);
2708
2709         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2710         if (INTEL_INFO(dev)->gen >= 4) {
2711                 I915_WRITE(DSPSURF(plane),
2712                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2713                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2714                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2715         } else
2716                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2717         POSTING_READ(reg);
2718 }
2719
2720 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2721                                        struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int plane = intel_crtc->plane;
2727
2728         I915_WRITE(DSPCNTR(plane), 0);
2729         if (INTEL_INFO(dev_priv)->gen >= 4)
2730                 I915_WRITE(DSPSURF(plane), 0);
2731         else
2732                 I915_WRITE(DSPADDR(plane), 0);
2733         POSTING_READ(DSPCNTR(plane));
2734 }
2735
2736 static void ironlake_update_primary_plane(struct drm_plane *primary,
2737                                           const struct intel_crtc_state *crtc_state,
2738                                           const struct intel_plane_state *plane_state)
2739 {
2740         struct drm_device *dev = primary->dev;
2741         struct drm_i915_private *dev_priv = to_i915(dev);
2742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2743         struct drm_framebuffer *fb = plane_state->base.fb;
2744         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2745         int plane = intel_crtc->plane;
2746         u32 linear_offset;
2747         u32 dspcntr;
2748         i915_reg_t reg = DSPCNTR(plane);
2749         unsigned int rotation = plane_state->base.rotation;
2750         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2751         int x = plane_state->src.x1 >> 16;
2752         int y = plane_state->src.y1 >> 16;
2753
2754         dspcntr = DISPPLANE_GAMMA_ENABLE;
2755         dspcntr |= DISPLAY_PLANE_ENABLE;
2756
2757         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2758                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2759
2760         switch (fb->pixel_format) {
2761         case DRM_FORMAT_C8:
2762                 dspcntr |= DISPPLANE_8BPP;
2763                 break;
2764         case DRM_FORMAT_RGB565:
2765                 dspcntr |= DISPPLANE_BGRX565;
2766                 break;
2767         case DRM_FORMAT_XRGB8888:
2768                 dspcntr |= DISPPLANE_BGRX888;
2769                 break;
2770         case DRM_FORMAT_XBGR8888:
2771                 dspcntr |= DISPPLANE_RGBX888;
2772                 break;
2773         case DRM_FORMAT_XRGB2101010:
2774                 dspcntr |= DISPPLANE_BGRX101010;
2775                 break;
2776         case DRM_FORMAT_XBGR2101010:
2777                 dspcntr |= DISPPLANE_RGBX101010;
2778                 break;
2779         default:
2780                 BUG();
2781         }
2782
2783         if (obj->tiling_mode != I915_TILING_NONE)
2784                 dspcntr |= DISPPLANE_TILED;
2785
2786         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2787                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2788
2789         linear_offset = y * fb->pitches[0] + x * cpp;
2790         intel_crtc->dspaddr_offset =
2791                 intel_compute_tile_offset(&x, &y, fb, 0,
2792                                           fb->pitches[0], rotation);
2793         linear_offset -= intel_crtc->dspaddr_offset;
2794         if (rotation == BIT(DRM_ROTATE_180)) {
2795                 dspcntr |= DISPPLANE_ROTATE_180;
2796
2797                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2798                         x += (crtc_state->pipe_src_w - 1);
2799                         y += (crtc_state->pipe_src_h - 1);
2800
2801                         /* Finding the last pixel of the last line of the display
2802                         data and adding to linear_offset*/
2803                         linear_offset +=
2804                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2805                                 (crtc_state->pipe_src_w - 1) * cpp;
2806                 }
2807         }
2808
2809         intel_crtc->adjusted_x = x;
2810         intel_crtc->adjusted_y = y;
2811
2812         I915_WRITE(reg, dspcntr);
2813
2814         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2815         I915_WRITE(DSPSURF(plane),
2816                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2817         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2818                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2819         } else {
2820                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2821                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2822         }
2823         POSTING_READ(reg);
2824 }
2825
2826 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2827                               uint64_t fb_modifier, uint32_t pixel_format)
2828 {
2829         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2830                 return 64;
2831         } else {
2832                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2833
2834                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2835         }
2836 }
2837
2838 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2839                            struct drm_i915_gem_object *obj,
2840                            unsigned int plane)
2841 {
2842         struct i915_ggtt_view view;
2843         struct i915_vma *vma;
2844         u64 offset;
2845
2846         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2847                                 intel_plane->base.state->rotation);
2848
2849         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2850         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2851                 view.type))
2852                 return -1;
2853
2854         offset = vma->node.start;
2855
2856         if (plane == 1) {
2857                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2858                           PAGE_SIZE;
2859         }
2860
2861         WARN_ON(upper_32_bits(offset));
2862
2863         return lower_32_bits(offset);
2864 }
2865
2866 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2867 {
2868         struct drm_device *dev = intel_crtc->base.dev;
2869         struct drm_i915_private *dev_priv = to_i915(dev);
2870
2871         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2872         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2873         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2874 }
2875
2876 /*
2877  * This function detaches (aka. unbinds) unused scalers in hardware
2878  */
2879 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2880 {
2881         struct intel_crtc_scaler_state *scaler_state;
2882         int i;
2883
2884         scaler_state = &intel_crtc->config->scaler_state;
2885
2886         /* loop through and disable scalers that aren't in use */
2887         for (i = 0; i < intel_crtc->num_scalers; i++) {
2888                 if (!scaler_state->scalers[i].in_use)
2889                         skl_detach_scaler(intel_crtc, i);
2890         }
2891 }
2892
2893 u32 skl_plane_ctl_format(uint32_t pixel_format)
2894 {
2895         switch (pixel_format) {
2896         case DRM_FORMAT_C8:
2897                 return PLANE_CTL_FORMAT_INDEXED;
2898         case DRM_FORMAT_RGB565:
2899                 return PLANE_CTL_FORMAT_RGB_565;
2900         case DRM_FORMAT_XBGR8888:
2901                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2902         case DRM_FORMAT_XRGB8888:
2903                 return PLANE_CTL_FORMAT_XRGB_8888;
2904         /*
2905          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2906          * to be already pre-multiplied. We need to add a knob (or a different
2907          * DRM_FORMAT) for user-space to configure that.
2908          */
2909         case DRM_FORMAT_ABGR8888:
2910                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2911                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2912         case DRM_FORMAT_ARGB8888:
2913                 return PLANE_CTL_FORMAT_XRGB_8888 |
2914                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2915         case DRM_FORMAT_XRGB2101010:
2916                 return PLANE_CTL_FORMAT_XRGB_2101010;
2917         case DRM_FORMAT_XBGR2101010:
2918                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2919         case DRM_FORMAT_YUYV:
2920                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2921         case DRM_FORMAT_YVYU:
2922                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2923         case DRM_FORMAT_UYVY:
2924                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2925         case DRM_FORMAT_VYUY:
2926                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2927         default:
2928                 MISSING_CASE(pixel_format);
2929         }
2930
2931         return 0;
2932 }
2933
2934 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2935 {
2936         switch (fb_modifier) {
2937         case DRM_FORMAT_MOD_NONE:
2938                 break;
2939         case I915_FORMAT_MOD_X_TILED:
2940                 return PLANE_CTL_TILED_X;
2941         case I915_FORMAT_MOD_Y_TILED:
2942                 return PLANE_CTL_TILED_Y;
2943         case I915_FORMAT_MOD_Yf_TILED:
2944                 return PLANE_CTL_TILED_YF;
2945         default:
2946                 MISSING_CASE(fb_modifier);
2947         }
2948
2949         return 0;
2950 }
2951
2952 u32 skl_plane_ctl_rotation(unsigned int rotation)
2953 {
2954         switch (rotation) {
2955         case BIT(DRM_ROTATE_0):
2956                 break;
2957         /*
2958          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2959          * while i915 HW rotation is clockwise, thats why this swapping.
2960          */
2961         case BIT(DRM_ROTATE_90):
2962                 return PLANE_CTL_ROTATE_270;
2963         case BIT(DRM_ROTATE_180):
2964                 return PLANE_CTL_ROTATE_180;
2965         case BIT(DRM_ROTATE_270):
2966                 return PLANE_CTL_ROTATE_90;
2967         default:
2968                 MISSING_CASE(rotation);
2969         }
2970
2971         return 0;
2972 }
2973
2974 static void skylake_update_primary_plane(struct drm_plane *plane,
2975                                          const struct intel_crtc_state *crtc_state,
2976                                          const struct intel_plane_state *plane_state)
2977 {
2978         struct drm_device *dev = plane->dev;
2979         struct drm_i915_private *dev_priv = to_i915(dev);
2980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2981         struct drm_framebuffer *fb = plane_state->base.fb;
2982         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2983         int pipe = intel_crtc->pipe;
2984         u32 plane_ctl, stride_div, stride;
2985         u32 tile_height, plane_offset, plane_size;
2986         unsigned int rotation = plane_state->base.rotation;
2987         int x_offset, y_offset;
2988         u32 surf_addr;
2989         int scaler_id = plane_state->scaler_id;
2990         int src_x = plane_state->src.x1 >> 16;
2991         int src_y = plane_state->src.y1 >> 16;
2992         int src_w = drm_rect_width(&plane_state->src) >> 16;
2993         int src_h = drm_rect_height(&plane_state->src) >> 16;
2994         int dst_x = plane_state->dst.x1;
2995         int dst_y = plane_state->dst.y1;
2996         int dst_w = drm_rect_width(&plane_state->dst);
2997         int dst_h = drm_rect_height(&plane_state->dst);
2998
2999         plane_ctl = PLANE_CTL_ENABLE |
3000                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3001                     PLANE_CTL_PIPE_CSC_ENABLE;
3002
3003         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3004         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3005         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3006         plane_ctl |= skl_plane_ctl_rotation(rotation);
3007
3008         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3009                                                fb->pixel_format);
3010         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3011
3012         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3013
3014         if (intel_rotation_90_or_270(rotation)) {
3015                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3016
3017                 /* stride = Surface height in tiles */
3018                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3019                 stride = DIV_ROUND_UP(fb->height, tile_height);
3020                 x_offset = stride * tile_height - src_y - src_h;
3021                 y_offset = src_x;
3022                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3023         } else {
3024                 stride = fb->pitches[0] / stride_div;
3025                 x_offset = src_x;
3026                 y_offset = src_y;
3027                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3028         }
3029         plane_offset = y_offset << 16 | x_offset;
3030
3031         intel_crtc->adjusted_x = x_offset;
3032         intel_crtc->adjusted_y = y_offset;
3033
3034         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3035         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3036         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3037         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3038
3039         if (scaler_id >= 0) {
3040                 uint32_t ps_ctrl = 0;
3041
3042                 WARN_ON(!dst_w || !dst_h);
3043                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3044                         crtc_state->scaler_state.scalers[scaler_id].mode;
3045                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3046                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3047                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3048                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3049                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3050         } else {
3051                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3052         }
3053
3054         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3055
3056         POSTING_READ(PLANE_SURF(pipe, 0));
3057 }
3058
3059 static void skylake_disable_primary_plane(struct drm_plane *primary,
3060                                           struct drm_crtc *crtc)
3061 {
3062         struct drm_device *dev = crtc->dev;
3063         struct drm_i915_private *dev_priv = to_i915(dev);
3064         int pipe = to_intel_crtc(crtc)->pipe;
3065
3066         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3067         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3068         POSTING_READ(PLANE_SURF(pipe, 0));
3069 }
3070
3071 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3072 static int
3073 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3074                            int x, int y, enum mode_set_atomic state)
3075 {
3076         /* Support for kgdboc is disabled, this needs a major rework. */
3077         DRM_ERROR("legacy panic handler not supported any more.\n");
3078
3079         return -ENODEV;
3080 }
3081
3082 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3083 {
3084         struct intel_crtc *crtc;
3085
3086         for_each_intel_crtc(&dev_priv->drm, crtc)
3087                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3088 }
3089
3090 static void intel_update_primary_planes(struct drm_device *dev)
3091 {
3092         struct drm_crtc *crtc;
3093
3094         for_each_crtc(dev, crtc) {
3095                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3096                 struct intel_plane_state *plane_state;
3097
3098                 drm_modeset_lock_crtc(crtc, &plane->base);
3099                 plane_state = to_intel_plane_state(plane->base.state);
3100
3101                 if (plane_state->visible)
3102                         plane->update_plane(&plane->base,
3103                                             to_intel_crtc_state(crtc->state),
3104                                             plane_state);
3105
3106                 drm_modeset_unlock_crtc(crtc);
3107         }
3108 }
3109
3110 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3111 {
3112         /* no reset support for gen2 */
3113         if (IS_GEN2(dev_priv))
3114                 return;
3115
3116         /* reset doesn't touch the display */
3117         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3118                 return;
3119
3120         drm_modeset_lock_all(&dev_priv->drm);
3121         /*
3122          * Disabling the crtcs gracefully seems nicer. Also the
3123          * g33 docs say we should at least disable all the planes.
3124          */
3125         intel_display_suspend(&dev_priv->drm);
3126 }
3127
3128 void intel_finish_reset(struct drm_i915_private *dev_priv)
3129 {
3130         /*
3131          * Flips in the rings will be nuked by the reset,
3132          * so complete all pending flips so that user space
3133          * will get its events and not get stuck.
3134          */
3135         intel_complete_page_flips(dev_priv);
3136
3137         /* no reset support for gen2 */
3138         if (IS_GEN2(dev_priv))
3139                 return;
3140
3141         /* reset doesn't touch the display */
3142         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3143                 /*
3144                  * Flips in the rings have been nuked by the reset,
3145                  * so update the base address of all primary
3146                  * planes to the the last fb to make sure we're
3147                  * showing the correct fb after a reset.
3148                  *
3149                  * FIXME: Atomic will make this obsolete since we won't schedule
3150                  * CS-based flips (which might get lost in gpu resets) any more.
3151                  */
3152                 intel_update_primary_planes(&dev_priv->drm);
3153                 return;
3154         }
3155
3156         /*
3157          * The display has been reset as well,
3158          * so need a full re-initialization.
3159          */
3160         intel_runtime_pm_disable_interrupts(dev_priv);
3161         intel_runtime_pm_enable_interrupts(dev_priv);
3162
3163         intel_modeset_init_hw(&dev_priv->drm);
3164
3165         spin_lock_irq(&dev_priv->irq_lock);
3166         if (dev_priv->display.hpd_irq_setup)
3167                 dev_priv->display.hpd_irq_setup(dev_priv);
3168         spin_unlock_irq(&dev_priv->irq_lock);
3169
3170         intel_display_resume(&dev_priv->drm);
3171
3172         intel_hpd_init(dev_priv);
3173
3174         drm_modeset_unlock_all(&dev_priv->drm);
3175 }
3176
3177 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3178 {
3179         struct drm_device *dev = crtc->dev;
3180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181         unsigned reset_counter;
3182         bool pending;
3183
3184         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3185         if (intel_crtc->reset_counter != reset_counter)
3186                 return false;
3187
3188         spin_lock_irq(&dev->event_lock);
3189         pending = to_intel_crtc(crtc)->flip_work != NULL;
3190         spin_unlock_irq(&dev->event_lock);
3191
3192         return pending;
3193 }
3194
3195 static void intel_update_pipe_config(struct intel_crtc *crtc,
3196                                      struct intel_crtc_state *old_crtc_state)
3197 {
3198         struct drm_device *dev = crtc->base.dev;
3199         struct drm_i915_private *dev_priv = to_i915(dev);
3200         struct intel_crtc_state *pipe_config =
3201                 to_intel_crtc_state(crtc->base.state);
3202
3203         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3204         crtc->base.mode = crtc->base.state->mode;
3205
3206         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3207                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3208                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3209
3210         /*
3211          * Update pipe size and adjust fitter if needed: the reason for this is
3212          * that in compute_mode_changes we check the native mode (not the pfit
3213          * mode) to see if we can flip rather than do a full mode set. In the
3214          * fastboot case, we'll flip, but if we don't update the pipesrc and
3215          * pfit state, we'll end up with a big fb scanned out into the wrong
3216          * sized surface.
3217          */
3218
3219         I915_WRITE(PIPESRC(crtc->pipe),
3220                    ((pipe_config->pipe_src_w - 1) << 16) |
3221                    (pipe_config->pipe_src_h - 1));
3222
3223         /* on skylake this is done by detaching scalers */
3224         if (INTEL_INFO(dev)->gen >= 9) {
3225                 skl_detach_scalers(crtc);
3226
3227                 if (pipe_config->pch_pfit.enabled)
3228                         skylake_pfit_enable(crtc);
3229         } else if (HAS_PCH_SPLIT(dev)) {
3230                 if (pipe_config->pch_pfit.enabled)
3231                         ironlake_pfit_enable(crtc);
3232                 else if (old_crtc_state->pch_pfit.enabled)
3233                         ironlake_pfit_disable(crtc, true);
3234         }
3235 }
3236
3237 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = to_i915(dev);
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         int pipe = intel_crtc->pipe;
3243         i915_reg_t reg;
3244         u32 temp;
3245
3246         /* enable normal train */
3247         reg = FDI_TX_CTL(pipe);
3248         temp = I915_READ(reg);
3249         if (IS_IVYBRIDGE(dev)) {
3250                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3251                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3252         } else {
3253                 temp &= ~FDI_LINK_TRAIN_NONE;
3254                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3255         }
3256         I915_WRITE(reg, temp);
3257
3258         reg = FDI_RX_CTL(pipe);
3259         temp = I915_READ(reg);
3260         if (HAS_PCH_CPT(dev)) {
3261                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3262                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3263         } else {
3264                 temp &= ~FDI_LINK_TRAIN_NONE;
3265                 temp |= FDI_LINK_TRAIN_NONE;
3266         }
3267         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3268
3269         /* wait one idle pattern time */
3270         POSTING_READ(reg);
3271         udelay(1000);
3272
3273         /* IVB wants error correction enabled */
3274         if (IS_IVYBRIDGE(dev))
3275                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3276                            FDI_FE_ERRC_ENABLE);
3277 }
3278
3279 /* The FDI link training functions for ILK/Ibexpeak. */
3280 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3281 {
3282         struct drm_device *dev = crtc->dev;
3283         struct drm_i915_private *dev_priv = to_i915(dev);
3284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285         int pipe = intel_crtc->pipe;
3286         i915_reg_t reg;
3287         u32 temp, tries;
3288
3289         /* FDI needs bits from pipe first */
3290         assert_pipe_enabled(dev_priv, pipe);
3291
3292         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3293            for train result */
3294         reg = FDI_RX_IMR(pipe);
3295         temp = I915_READ(reg);
3296         temp &= ~FDI_RX_SYMBOL_LOCK;
3297         temp &= ~FDI_RX_BIT_LOCK;
3298         I915_WRITE(reg, temp);
3299         I915_READ(reg);
3300         udelay(150);
3301
3302         /* enable CPU FDI TX and PCH FDI RX */
3303         reg = FDI_TX_CTL(pipe);
3304         temp = I915_READ(reg);
3305         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3306         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3307         temp &= ~FDI_LINK_TRAIN_NONE;
3308         temp |= FDI_LINK_TRAIN_PATTERN_1;
3309         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3310
3311         reg = FDI_RX_CTL(pipe);
3312         temp = I915_READ(reg);
3313         temp &= ~FDI_LINK_TRAIN_NONE;
3314         temp |= FDI_LINK_TRAIN_PATTERN_1;
3315         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3316
3317         POSTING_READ(reg);
3318         udelay(150);
3319
3320         /* Ironlake workaround, enable clock pointer after FDI enable*/
3321         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3322         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3323                    FDI_RX_PHASE_SYNC_POINTER_EN);
3324
3325         reg = FDI_RX_IIR(pipe);
3326         for (tries = 0; tries < 5; tries++) {
3327                 temp = I915_READ(reg);
3328                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330                 if ((temp & FDI_RX_BIT_LOCK)) {
3331                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3332                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333                         break;
3334                 }
3335         }
3336         if (tries == 5)
3337                 DRM_ERROR("FDI train 1 fail!\n");
3338
3339         /* Train 2 */
3340         reg = FDI_TX_CTL(pipe);
3341         temp = I915_READ(reg);
3342         temp &= ~FDI_LINK_TRAIN_NONE;
3343         temp |= FDI_LINK_TRAIN_PATTERN_2;
3344         I915_WRITE(reg, temp);
3345
3346         reg = FDI_RX_CTL(pipe);
3347         temp = I915_READ(reg);
3348         temp &= ~FDI_LINK_TRAIN_NONE;
3349         temp |= FDI_LINK_TRAIN_PATTERN_2;
3350         I915_WRITE(reg, temp);
3351
3352         POSTING_READ(reg);
3353         udelay(150);
3354
3355         reg = FDI_RX_IIR(pipe);
3356         for (tries = 0; tries < 5; tries++) {
3357                 temp = I915_READ(reg);
3358                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3359
3360                 if (temp & FDI_RX_SYMBOL_LOCK) {
3361                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3362                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3363                         break;
3364                 }
3365         }
3366         if (tries == 5)
3367                 DRM_ERROR("FDI train 2 fail!\n");
3368
3369         DRM_DEBUG_KMS("FDI train done\n");
3370
3371 }
3372
3373 static const int snb_b_fdi_train_param[] = {
3374         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3375         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3376         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3377         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3378 };
3379
3380 /* The FDI link training functions for SNB/Cougarpoint. */
3381 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         struct drm_i915_private *dev_priv = to_i915(dev);
3385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386         int pipe = intel_crtc->pipe;
3387         i915_reg_t reg;
3388         u32 temp, i, retry;
3389
3390         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3391            for train result */
3392         reg = FDI_RX_IMR(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~FDI_RX_SYMBOL_LOCK;
3395         temp &= ~FDI_RX_BIT_LOCK;
3396         I915_WRITE(reg, temp);
3397
3398         POSTING_READ(reg);
3399         udelay(150);
3400
3401         /* enable CPU FDI TX and PCH FDI RX */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3405         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3406         temp &= ~FDI_LINK_TRAIN_NONE;
3407         temp |= FDI_LINK_TRAIN_PATTERN_1;
3408         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3409         /* SNB-B */
3410         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3411         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3412
3413         I915_WRITE(FDI_RX_MISC(pipe),
3414                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3415
3416         reg = FDI_RX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         if (HAS_PCH_CPT(dev)) {
3419                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3420                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3421         } else {
3422                 temp &= ~FDI_LINK_TRAIN_NONE;
3423                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3424         }
3425         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427         POSTING_READ(reg);
3428         udelay(150);
3429
3430         for (i = 0; i < 4; i++) {
3431                 reg = FDI_TX_CTL(pipe);
3432                 temp = I915_READ(reg);
3433                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3434                 temp |= snb_b_fdi_train_param[i];
3435                 I915_WRITE(reg, temp);
3436
3437                 POSTING_READ(reg);
3438                 udelay(500);
3439
3440                 for (retry = 0; retry < 5; retry++) {
3441                         reg = FDI_RX_IIR(pipe);
3442                         temp = I915_READ(reg);
3443                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3444                         if (temp & FDI_RX_BIT_LOCK) {
3445                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3447                                 break;
3448                         }
3449                         udelay(50);
3450                 }
3451                 if (retry < 5)
3452                         break;
3453         }
3454         if (i == 4)
3455                 DRM_ERROR("FDI train 1 fail!\n");
3456
3457         /* Train 2 */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         temp &= ~FDI_LINK_TRAIN_NONE;
3461         temp |= FDI_LINK_TRAIN_PATTERN_2;
3462         if (IS_GEN6(dev)) {
3463                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3464                 /* SNB-B */
3465                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3466         }
3467         I915_WRITE(reg, temp);
3468
3469         reg = FDI_RX_CTL(pipe);
3470         temp = I915_READ(reg);
3471         if (HAS_PCH_CPT(dev)) {
3472                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3473                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3474         } else {
3475                 temp &= ~FDI_LINK_TRAIN_NONE;
3476                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3477         }
3478         I915_WRITE(reg, temp);
3479
3480         POSTING_READ(reg);
3481         udelay(150);
3482
3483         for (i = 0; i < 4; i++) {
3484                 reg = FDI_TX_CTL(pipe);
3485                 temp = I915_READ(reg);
3486                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3487                 temp |= snb_b_fdi_train_param[i];
3488                 I915_WRITE(reg, temp);
3489
3490                 POSTING_READ(reg);
3491                 udelay(500);
3492
3493                 for (retry = 0; retry < 5; retry++) {
3494                         reg = FDI_RX_IIR(pipe);
3495                         temp = I915_READ(reg);
3496                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497                         if (temp & FDI_RX_SYMBOL_LOCK) {
3498                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3499                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3500                                 break;
3501                         }
3502                         udelay(50);
3503                 }
3504                 if (retry < 5)
3505                         break;
3506         }
3507         if (i == 4)
3508                 DRM_ERROR("FDI train 2 fail!\n");
3509
3510         DRM_DEBUG_KMS("FDI train done.\n");
3511 }
3512
3513 /* Manual link training for Ivy Bridge A0 parts */
3514 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         struct drm_i915_private *dev_priv = to_i915(dev);
3518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3519         int pipe = intel_crtc->pipe;
3520         i915_reg_t reg;
3521         u32 temp, i, j;
3522
3523         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3524            for train result */
3525         reg = FDI_RX_IMR(pipe);
3526         temp = I915_READ(reg);
3527         temp &= ~FDI_RX_SYMBOL_LOCK;
3528         temp &= ~FDI_RX_BIT_LOCK;
3529         I915_WRITE(reg, temp);
3530
3531         POSTING_READ(reg);
3532         udelay(150);
3533
3534         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3535                       I915_READ(FDI_RX_IIR(pipe)));
3536
3537         /* Try each vswing and preemphasis setting twice before moving on */
3538         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3539                 /* disable first in case we need to retry */
3540                 reg = FDI_TX_CTL(pipe);
3541                 temp = I915_READ(reg);
3542                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3543                 temp &= ~FDI_TX_ENABLE;
3544                 I915_WRITE(reg, temp);
3545
3546                 reg = FDI_RX_CTL(pipe);
3547                 temp = I915_READ(reg);
3548                 temp &= ~FDI_LINK_TRAIN_AUTO;
3549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550                 temp &= ~FDI_RX_ENABLE;
3551                 I915_WRITE(reg, temp);
3552
3553                 /* enable CPU FDI TX and PCH FDI RX */
3554                 reg = FDI_TX_CTL(pipe);
3555                 temp = I915_READ(reg);
3556                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3557                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3558                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3559                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560                 temp |= snb_b_fdi_train_param[j/2];
3561                 temp |= FDI_COMPOSITE_SYNC;
3562                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3563
3564                 I915_WRITE(FDI_RX_MISC(pipe),
3565                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3566
3567                 reg = FDI_RX_CTL(pipe);
3568                 temp = I915_READ(reg);
3569                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3570                 temp |= FDI_COMPOSITE_SYNC;
3571                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3572
3573                 POSTING_READ(reg);
3574                 udelay(1); /* should be 0.5us */
3575
3576                 for (i = 0; i < 4; i++) {
3577                         reg = FDI_RX_IIR(pipe);
3578                         temp = I915_READ(reg);
3579                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3580
3581                         if (temp & FDI_RX_BIT_LOCK ||
3582                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3583                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3584                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3585                                               i);
3586                                 break;
3587                         }
3588                         udelay(1); /* should be 0.5us */
3589                 }
3590                 if (i == 4) {
3591                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3592                         continue;
3593                 }
3594
3595                 /* Train 2 */
3596                 reg = FDI_TX_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3599                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3600                 I915_WRITE(reg, temp);
3601
3602                 reg = FDI_RX_CTL(pipe);
3603                 temp = I915_READ(reg);
3604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3605                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3606                 I915_WRITE(reg, temp);
3607
3608                 POSTING_READ(reg);
3609                 udelay(2); /* should be 1.5us */
3610
3611                 for (i = 0; i < 4; i++) {
3612                         reg = FDI_RX_IIR(pipe);
3613                         temp = I915_READ(reg);
3614                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3615
3616                         if (temp & FDI_RX_SYMBOL_LOCK ||
3617                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3618                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3619                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3620                                               i);
3621                                 goto train_done;
3622                         }
3623                         udelay(2); /* should be 1.5us */
3624                 }
3625                 if (i == 4)
3626                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3627         }
3628
3629 train_done:
3630         DRM_DEBUG_KMS("FDI train done.\n");
3631 }
3632
3633 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3634 {
3635         struct drm_device *dev = intel_crtc->base.dev;
3636         struct drm_i915_private *dev_priv = to_i915(dev);
3637         int pipe = intel_crtc->pipe;
3638         i915_reg_t reg;
3639         u32 temp;
3640
3641         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3642         reg = FDI_RX_CTL(pipe);
3643         temp = I915_READ(reg);
3644         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3645         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3646         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3647         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3648
3649         POSTING_READ(reg);
3650         udelay(200);
3651
3652         /* Switch from Rawclk to PCDclk */
3653         temp = I915_READ(reg);
3654         I915_WRITE(reg, temp | FDI_PCDCLK);
3655
3656         POSTING_READ(reg);
3657         udelay(200);
3658
3659         /* Enable CPU FDI TX PLL, always on for Ironlake */
3660         reg = FDI_TX_CTL(pipe);
3661         temp = I915_READ(reg);
3662         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3663                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3664
3665                 POSTING_READ(reg);
3666                 udelay(100);
3667         }
3668 }
3669
3670 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3671 {
3672         struct drm_device *dev = intel_crtc->base.dev;
3673         struct drm_i915_private *dev_priv = to_i915(dev);
3674         int pipe = intel_crtc->pipe;
3675         i915_reg_t reg;
3676         u32 temp;
3677
3678         /* Switch from PCDclk to Rawclk */
3679         reg = FDI_RX_CTL(pipe);
3680         temp = I915_READ(reg);
3681         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3682
3683         /* Disable CPU FDI TX PLL */
3684         reg = FDI_TX_CTL(pipe);
3685         temp = I915_READ(reg);
3686         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3687
3688         POSTING_READ(reg);
3689         udelay(100);
3690
3691         reg = FDI_RX_CTL(pipe);
3692         temp = I915_READ(reg);
3693         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3694
3695         /* Wait for the clocks to turn off. */
3696         POSTING_READ(reg);
3697         udelay(100);
3698 }
3699
3700 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3701 {
3702         struct drm_device *dev = crtc->dev;
3703         struct drm_i915_private *dev_priv = to_i915(dev);
3704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705         int pipe = intel_crtc->pipe;
3706         i915_reg_t reg;
3707         u32 temp;
3708
3709         /* disable CPU FDI tx and PCH FDI rx */
3710         reg = FDI_TX_CTL(pipe);
3711         temp = I915_READ(reg);
3712         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3713         POSTING_READ(reg);
3714
3715         reg = FDI_RX_CTL(pipe);
3716         temp = I915_READ(reg);
3717         temp &= ~(0x7 << 16);
3718         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3719         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3720
3721         POSTING_READ(reg);
3722         udelay(100);
3723
3724         /* Ironlake workaround, disable clock pointer after downing FDI */
3725         if (HAS_PCH_IBX(dev))
3726                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3727
3728         /* still set train pattern 1 */
3729         reg = FDI_TX_CTL(pipe);
3730         temp = I915_READ(reg);
3731         temp &= ~FDI_LINK_TRAIN_NONE;
3732         temp |= FDI_LINK_TRAIN_PATTERN_1;
3733         I915_WRITE(reg, temp);
3734
3735         reg = FDI_RX_CTL(pipe);
3736         temp = I915_READ(reg);
3737         if (HAS_PCH_CPT(dev)) {
3738                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3739                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3740         } else {
3741                 temp &= ~FDI_LINK_TRAIN_NONE;
3742                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3743         }
3744         /* BPC in FDI rx is consistent with that in PIPECONF */
3745         temp &= ~(0x07 << 16);
3746         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3747         I915_WRITE(reg, temp);
3748
3749         POSTING_READ(reg);
3750         udelay(100);
3751 }
3752
3753 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3754 {
3755         struct intel_crtc *crtc;
3756
3757         /* Note that we don't need to be called with mode_config.lock here
3758          * as our list of CRTC objects is static for the lifetime of the
3759          * device and so cannot disappear as we iterate. Similarly, we can
3760          * happily treat the predicates as racy, atomic checks as userspace
3761          * cannot claim and pin a new fb without at least acquring the
3762          * struct_mutex and so serialising with us.
3763          */
3764         for_each_intel_crtc(dev, crtc) {
3765                 if (atomic_read(&crtc->unpin_work_count) == 0)
3766                         continue;
3767
3768                 if (crtc->flip_work)
3769                         intel_wait_for_vblank(dev, crtc->pipe);
3770
3771                 return true;
3772         }
3773
3774         return false;
3775 }
3776
3777 static void page_flip_completed(struct intel_crtc *intel_crtc)
3778 {
3779         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3780         struct intel_flip_work *work = intel_crtc->flip_work;
3781
3782         intel_crtc->flip_work = NULL;
3783
3784         if (work->event)
3785                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3786
3787         drm_crtc_vblank_put(&intel_crtc->base);
3788
3789         wake_up_all(&dev_priv->pending_flip_queue);
3790         queue_work(dev_priv->wq, &work->unpin_work);
3791
3792         trace_i915_flip_complete(intel_crtc->plane,
3793                                  work->pending_flip_obj);
3794 }
3795
3796 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3797 {
3798         struct drm_device *dev = crtc->dev;
3799         struct drm_i915_private *dev_priv = to_i915(dev);
3800         long ret;
3801
3802         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3803
3804         ret = wait_event_interruptible_timeout(
3805                                         dev_priv->pending_flip_queue,
3806                                         !intel_crtc_has_pending_flip(crtc),
3807                                         60*HZ);
3808
3809         if (ret < 0)
3810                 return ret;
3811
3812         if (ret == 0) {
3813                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814                 struct intel_flip_work *work;
3815
3816                 spin_lock_irq(&dev->event_lock);
3817                 work = intel_crtc->flip_work;
3818                 if (work && !is_mmio_work(work)) {
3819                         WARN_ONCE(1, "Removing stuck page flip\n");
3820                         page_flip_completed(intel_crtc);
3821                 }
3822                 spin_unlock_irq(&dev->event_lock);
3823         }
3824
3825         return 0;
3826 }
3827
3828 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3829 {
3830         u32 temp;
3831
3832         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833
3834         mutex_lock(&dev_priv->sb_lock);
3835
3836         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3837         temp |= SBI_SSCCTL_DISABLE;
3838         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3839
3840         mutex_unlock(&dev_priv->sb_lock);
3841 }
3842
3843 /* Program iCLKIP clock to the desired frequency */
3844 static void lpt_program_iclkip(struct drm_crtc *crtc)
3845 {
3846         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3847         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3848         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3849         u32 temp;
3850
3851         lpt_disable_iclkip(dev_priv);
3852
3853         /* The iCLK virtual clock root frequency is in MHz,
3854          * but the adjusted_mode->crtc_clock in in KHz. To get the
3855          * divisors, it is necessary to divide one by another, so we
3856          * convert the virtual clock precision to KHz here for higher
3857          * precision.
3858          */
3859         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3860                 u32 iclk_virtual_root_freq = 172800 * 1000;
3861                 u32 iclk_pi_range = 64;
3862                 u32 desired_divisor;
3863
3864                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3865                                                     clock << auxdiv);
3866                 divsel = (desired_divisor / iclk_pi_range) - 2;
3867                 phaseinc = desired_divisor % iclk_pi_range;
3868
3869                 /*
3870                  * Near 20MHz is a corner case which is
3871                  * out of range for the 7-bit divisor
3872                  */
3873                 if (divsel <= 0x7f)
3874                         break;
3875         }
3876
3877         /* This should not happen with any sane values */
3878         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3879                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3880         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3881                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3882
3883         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3884                         clock,
3885                         auxdiv,
3886                         divsel,
3887                         phasedir,
3888                         phaseinc);
3889
3890         mutex_lock(&dev_priv->sb_lock);
3891
3892         /* Program SSCDIVINTPHASE6 */
3893         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3894         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3895         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3896         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3897         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3898         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3899         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3900         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3901
3902         /* Program SSCAUXDIV */
3903         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3904         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3905         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3906         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3907
3908         /* Enable modulator and associated divider */
3909         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3910         temp &= ~SBI_SSCCTL_DISABLE;
3911         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3912
3913         mutex_unlock(&dev_priv->sb_lock);
3914
3915         /* Wait for initialization time */
3916         udelay(24);
3917
3918         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3919 }
3920
3921 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3922 {
3923         u32 divsel, phaseinc, auxdiv;
3924         u32 iclk_virtual_root_freq = 172800 * 1000;
3925         u32 iclk_pi_range = 64;
3926         u32 desired_divisor;
3927         u32 temp;
3928
3929         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3930                 return 0;
3931
3932         mutex_lock(&dev_priv->sb_lock);
3933
3934         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3935         if (temp & SBI_SSCCTL_DISABLE) {
3936                 mutex_unlock(&dev_priv->sb_lock);
3937                 return 0;
3938         }
3939
3940         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3941         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3942                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3943         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3944                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3945
3946         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3947         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3948                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3949
3950         mutex_unlock(&dev_priv->sb_lock);
3951
3952         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3953
3954         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3955                                  desired_divisor << auxdiv);
3956 }
3957
3958 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3959                                                 enum pipe pch_transcoder)
3960 {
3961         struct drm_device *dev = crtc->base.dev;
3962         struct drm_i915_private *dev_priv = to_i915(dev);
3963         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3964
3965         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3966                    I915_READ(HTOTAL(cpu_transcoder)));
3967         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3968                    I915_READ(HBLANK(cpu_transcoder)));
3969         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3970                    I915_READ(HSYNC(cpu_transcoder)));
3971
3972         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3973                    I915_READ(VTOTAL(cpu_transcoder)));
3974         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3975                    I915_READ(VBLANK(cpu_transcoder)));
3976         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3977                    I915_READ(VSYNC(cpu_transcoder)));
3978         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3979                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3980 }
3981
3982 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3983 {
3984         struct drm_i915_private *dev_priv = to_i915(dev);
3985         uint32_t temp;
3986
3987         temp = I915_READ(SOUTH_CHICKEN1);
3988         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3989                 return;
3990
3991         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3992         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3993
3994         temp &= ~FDI_BC_BIFURCATION_SELECT;
3995         if (enable)
3996                 temp |= FDI_BC_BIFURCATION_SELECT;
3997
3998         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3999         I915_WRITE(SOUTH_CHICKEN1, temp);
4000         POSTING_READ(SOUTH_CHICKEN1);
4001 }
4002
4003 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4004 {
4005         struct drm_device *dev = intel_crtc->base.dev;
4006
4007         switch (intel_crtc->pipe) {
4008         case PIPE_A:
4009                 break;
4010         case PIPE_B:
4011                 if (intel_crtc->config->fdi_lanes > 2)
4012                         cpt_set_fdi_bc_bifurcation(dev, false);
4013                 else
4014                         cpt_set_fdi_bc_bifurcation(dev, true);
4015
4016                 break;
4017         case PIPE_C:
4018                 cpt_set_fdi_bc_bifurcation(dev, true);
4019
4020                 break;
4021         default:
4022                 BUG();
4023         }
4024 }
4025
4026 /* Return which DP Port should be selected for Transcoder DP control */
4027 static enum port
4028 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4029 {
4030         struct drm_device *dev = crtc->dev;
4031         struct intel_encoder *encoder;
4032
4033         for_each_encoder_on_crtc(dev, crtc, encoder) {
4034                 if (encoder->type == INTEL_OUTPUT_DP ||
4035                     encoder->type == INTEL_OUTPUT_EDP)
4036                         return enc_to_dig_port(&encoder->base)->port;
4037         }
4038
4039         return -1;
4040 }
4041
4042 /*
4043  * Enable PCH resources required for PCH ports:
4044  *   - PCH PLLs
4045  *   - FDI training & RX/TX
4046  *   - update transcoder timings
4047  *   - DP transcoding bits
4048  *   - transcoder
4049  */
4050 static void ironlake_pch_enable(struct drm_crtc *crtc)
4051 {
4052         struct drm_device *dev = crtc->dev;
4053         struct drm_i915_private *dev_priv = to_i915(dev);
4054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4055         int pipe = intel_crtc->pipe;
4056         u32 temp;
4057
4058         assert_pch_transcoder_disabled(dev_priv, pipe);
4059
4060         if (IS_IVYBRIDGE(dev))
4061                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4062
4063         /* Write the TU size bits before fdi link training, so that error
4064          * detection works. */
4065         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4066                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4067
4068         /* For PCH output, training FDI link */
4069         dev_priv->display.fdi_link_train(crtc);
4070
4071         /* We need to program the right clock selection before writing the pixel
4072          * mutliplier into the DPLL. */
4073         if (HAS_PCH_CPT(dev)) {
4074                 u32 sel;
4075
4076                 temp = I915_READ(PCH_DPLL_SEL);
4077                 temp |= TRANS_DPLL_ENABLE(pipe);
4078                 sel = TRANS_DPLLB_SEL(pipe);
4079                 if (intel_crtc->config->shared_dpll ==
4080                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4081                         temp |= sel;
4082                 else
4083                         temp &= ~sel;
4084                 I915_WRITE(PCH_DPLL_SEL, temp);
4085         }
4086
4087         /* XXX: pch pll's can be enabled any time before we enable the PCH
4088          * transcoder, and we actually should do this to not upset any PCH
4089          * transcoder that already use the clock when we share it.
4090          *
4091          * Note that enable_shared_dpll tries to do the right thing, but
4092          * get_shared_dpll unconditionally resets the pll - we need that to have
4093          * the right LVDS enable sequence. */
4094         intel_enable_shared_dpll(intel_crtc);
4095
4096         /* set transcoder timing, panel must allow it */
4097         assert_panel_unlocked(dev_priv, pipe);
4098         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4099
4100         intel_fdi_normal_train(crtc);
4101
4102         /* For PCH DP, enable TRANS_DP_CTL */
4103         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4104                 const struct drm_display_mode *adjusted_mode =
4105                         &intel_crtc->config->base.adjusted_mode;
4106                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4107                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4108                 temp = I915_READ(reg);
4109                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4110                           TRANS_DP_SYNC_MASK |
4111                           TRANS_DP_BPC_MASK);
4112                 temp |= TRANS_DP_OUTPUT_ENABLE;
4113                 temp |= bpc << 9; /* same format but at 11:9 */
4114
4115                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4116                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4117                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4118                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4119
4120                 switch (intel_trans_dp_port_sel(crtc)) {
4121                 case PORT_B:
4122                         temp |= TRANS_DP_PORT_SEL_B;
4123                         break;
4124                 case PORT_C:
4125                         temp |= TRANS_DP_PORT_SEL_C;
4126                         break;
4127                 case PORT_D:
4128                         temp |= TRANS_DP_PORT_SEL_D;
4129                         break;
4130                 default:
4131                         BUG();
4132                 }
4133
4134                 I915_WRITE(reg, temp);
4135         }
4136
4137         ironlake_enable_pch_transcoder(dev_priv, pipe);
4138 }
4139
4140 static void lpt_pch_enable(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = to_i915(dev);
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4146
4147         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4148
4149         lpt_program_iclkip(crtc);
4150
4151         /* Set transcoder timing. */
4152         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4153
4154         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4155 }
4156
4157 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4158 {
4159         struct drm_i915_private *dev_priv = to_i915(dev);
4160         i915_reg_t dslreg = PIPEDSL(pipe);
4161         u32 temp;
4162
4163         temp = I915_READ(dslreg);
4164         udelay(500);
4165         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4166                 if (wait_for(I915_READ(dslreg) != temp, 5))
4167                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4168         }
4169 }
4170
4171 static int
4172 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4173                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4174                   int src_w, int src_h, int dst_w, int dst_h)
4175 {
4176         struct intel_crtc_scaler_state *scaler_state =
4177                 &crtc_state->scaler_state;
4178         struct intel_crtc *intel_crtc =
4179                 to_intel_crtc(crtc_state->base.crtc);
4180         int need_scaling;
4181
4182         need_scaling = intel_rotation_90_or_270(rotation) ?
4183                 (src_h != dst_w || src_w != dst_h):
4184                 (src_w != dst_w || src_h != dst_h);
4185
4186         /*
4187          * if plane is being disabled or scaler is no more required or force detach
4188          *  - free scaler binded to this plane/crtc
4189          *  - in order to do this, update crtc->scaler_usage
4190          *
4191          * Here scaler state in crtc_state is set free so that
4192          * scaler can be assigned to other user. Actual register
4193          * update to free the scaler is done in plane/panel-fit programming.
4194          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4195          */
4196         if (force_detach || !need_scaling) {
4197                 if (*scaler_id >= 0) {
4198                         scaler_state->scaler_users &= ~(1 << scaler_user);
4199                         scaler_state->scalers[*scaler_id].in_use = 0;
4200
4201                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4202                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4203                                 intel_crtc->pipe, scaler_user, *scaler_id,
4204                                 scaler_state->scaler_users);
4205                         *scaler_id = -1;
4206                 }
4207                 return 0;
4208         }
4209
4210         /* range checks */
4211         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4212                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4213
4214                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4215                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4216                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4217                         "size is out of scaler range\n",
4218                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4219                 return -EINVAL;
4220         }
4221
4222         /* mark this plane as a scaler user in crtc_state */
4223         scaler_state->scaler_users |= (1 << scaler_user);
4224         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4225                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4226                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4227                 scaler_state->scaler_users);
4228
4229         return 0;
4230 }
4231
4232 /**
4233  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4234  *
4235  * @state: crtc's scaler state
4236  *
4237  * Return
4238  *     0 - scaler_usage updated successfully
4239  *    error - requested scaling cannot be supported or other error condition
4240  */
4241 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4242 {
4243         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4244         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4245
4246         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4247                       intel_crtc->base.base.id, intel_crtc->base.name,
4248                       intel_crtc->pipe, SKL_CRTC_INDEX);
4249
4250         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4251                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4252                 state->pipe_src_w, state->pipe_src_h,
4253                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4254 }
4255
4256 /**
4257  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4258  *
4259  * @state: crtc's scaler state
4260  * @plane_state: atomic plane state to update
4261  *
4262  * Return
4263  *     0 - scaler_usage updated successfully
4264  *    error - requested scaling cannot be supported or other error condition
4265  */
4266 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4267                                    struct intel_plane_state *plane_state)
4268 {
4269
4270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4271         struct intel_plane *intel_plane =
4272                 to_intel_plane(plane_state->base.plane);
4273         struct drm_framebuffer *fb = plane_state->base.fb;
4274         int ret;
4275
4276         bool force_detach = !fb || !plane_state->visible;
4277
4278         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4279                       intel_plane->base.base.id, intel_plane->base.name,
4280                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4281
4282         ret = skl_update_scaler(crtc_state, force_detach,
4283                                 drm_plane_index(&intel_plane->base),
4284                                 &plane_state->scaler_id,
4285                                 plane_state->base.rotation,
4286                                 drm_rect_width(&plane_state->src) >> 16,
4287                                 drm_rect_height(&plane_state->src) >> 16,
4288                                 drm_rect_width(&plane_state->dst),
4289                                 drm_rect_height(&plane_state->dst));
4290
4291         if (ret || plane_state->scaler_id < 0)
4292                 return ret;
4293
4294         /* check colorkey */
4295         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4296                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4297                               intel_plane->base.base.id,
4298                               intel_plane->base.name);
4299                 return -EINVAL;
4300         }
4301
4302         /* Check src format */
4303         switch (fb->pixel_format) {
4304         case DRM_FORMAT_RGB565:
4305         case DRM_FORMAT_XBGR8888:
4306         case DRM_FORMAT_XRGB8888:
4307         case DRM_FORMAT_ABGR8888:
4308         case DRM_FORMAT_ARGB8888:
4309         case DRM_FORMAT_XRGB2101010:
4310         case DRM_FORMAT_XBGR2101010:
4311         case DRM_FORMAT_YUYV:
4312         case DRM_FORMAT_YVYU:
4313         case DRM_FORMAT_UYVY:
4314         case DRM_FORMAT_VYUY:
4315                 break;
4316         default:
4317                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4318                               intel_plane->base.base.id, intel_plane->base.name,
4319                               fb->base.id, fb->pixel_format);
4320                 return -EINVAL;
4321         }
4322
4323         return 0;
4324 }
4325
4326 static void skylake_scaler_disable(struct intel_crtc *crtc)
4327 {
4328         int i;
4329
4330         for (i = 0; i < crtc->num_scalers; i++)
4331                 skl_detach_scaler(crtc, i);
4332 }
4333
4334 static void skylake_pfit_enable(struct intel_crtc *crtc)
4335 {
4336         struct drm_device *dev = crtc->base.dev;
4337         struct drm_i915_private *dev_priv = to_i915(dev);
4338         int pipe = crtc->pipe;
4339         struct intel_crtc_scaler_state *scaler_state =
4340                 &crtc->config->scaler_state;
4341
4342         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4343
4344         if (crtc->config->pch_pfit.enabled) {
4345                 int id;
4346
4347                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4348                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4349                         return;
4350                 }
4351
4352                 id = scaler_state->scaler_id;
4353                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4354                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4355                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4356                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4357
4358                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4359         }
4360 }
4361
4362 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4363 {
4364         struct drm_device *dev = crtc->base.dev;
4365         struct drm_i915_private *dev_priv = to_i915(dev);
4366         int pipe = crtc->pipe;
4367
4368         if (crtc->config->pch_pfit.enabled) {
4369                 /* Force use of hard-coded filter coefficients
4370                  * as some pre-programmed values are broken,
4371                  * e.g. x201.
4372                  */
4373                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4374                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4375                                                  PF_PIPE_SEL_IVB(pipe));
4376                 else
4377                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4378                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4379                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4380         }
4381 }
4382
4383 void hsw_enable_ips(struct intel_crtc *crtc)
4384 {
4385         struct drm_device *dev = crtc->base.dev;
4386         struct drm_i915_private *dev_priv = to_i915(dev);
4387
4388         if (!crtc->config->ips_enabled)
4389                 return;
4390
4391         /*
4392          * We can only enable IPS after we enable a plane and wait for a vblank
4393          * This function is called from post_plane_update, which is run after
4394          * a vblank wait.
4395          */
4396
4397         assert_plane_enabled(dev_priv, crtc->plane);
4398         if (IS_BROADWELL(dev)) {
4399                 mutex_lock(&dev_priv->rps.hw_lock);
4400                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4401                 mutex_unlock(&dev_priv->rps.hw_lock);
4402                 /* Quoting Art Runyan: "its not safe to expect any particular
4403                  * value in IPS_CTL bit 31 after enabling IPS through the
4404                  * mailbox." Moreover, the mailbox may return a bogus state,
4405                  * so we need to just enable it and continue on.
4406                  */
4407         } else {
4408                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4409                 /* The bit only becomes 1 in the next vblank, so this wait here
4410                  * is essentially intel_wait_for_vblank. If we don't have this
4411                  * and don't wait for vblanks until the end of crtc_enable, then
4412                  * the HW state readout code will complain that the expected
4413                  * IPS_CTL value is not the one we read. */
4414                 if (intel_wait_for_register(dev_priv,
4415                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4416                                             50))
4417                         DRM_ERROR("Timed out waiting for IPS enable\n");
4418         }
4419 }
4420
4421 void hsw_disable_ips(struct intel_crtc *crtc)
4422 {
4423         struct drm_device *dev = crtc->base.dev;
4424         struct drm_i915_private *dev_priv = to_i915(dev);
4425
4426         if (!crtc->config->ips_enabled)
4427                 return;
4428
4429         assert_plane_enabled(dev_priv, crtc->plane);
4430         if (IS_BROADWELL(dev)) {
4431                 mutex_lock(&dev_priv->rps.hw_lock);
4432                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4433                 mutex_unlock(&dev_priv->rps.hw_lock);
4434                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4435                 if (intel_wait_for_register(dev_priv,
4436                                             IPS_CTL, IPS_ENABLE, 0,
4437                                             42))
4438                         DRM_ERROR("Timed out waiting for IPS disable\n");
4439         } else {
4440                 I915_WRITE(IPS_CTL, 0);
4441                 POSTING_READ(IPS_CTL);
4442         }
4443
4444         /* We need to wait for a vblank before we can disable the plane. */
4445         intel_wait_for_vblank(dev, crtc->pipe);
4446 }
4447
4448 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4449 {
4450         if (intel_crtc->overlay) {
4451                 struct drm_device *dev = intel_crtc->base.dev;
4452                 struct drm_i915_private *dev_priv = to_i915(dev);
4453
4454                 mutex_lock(&dev->struct_mutex);
4455                 dev_priv->mm.interruptible = false;
4456                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4457                 dev_priv->mm.interruptible = true;
4458                 mutex_unlock(&dev->struct_mutex);
4459         }
4460
4461         /* Let userspace switch the overlay on again. In most cases userspace
4462          * has to recompute where to put it anyway.
4463          */
4464 }
4465
4466 /**
4467  * intel_post_enable_primary - Perform operations after enabling primary plane
4468  * @crtc: the CRTC whose primary plane was just enabled
4469  *
4470  * Performs potentially sleeping operations that must be done after the primary
4471  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4472  * called due to an explicit primary plane update, or due to an implicit
4473  * re-enable that is caused when a sprite plane is updated to no longer
4474  * completely hide the primary plane.
4475  */
4476 static void
4477 intel_post_enable_primary(struct drm_crtc *crtc)
4478 {
4479         struct drm_device *dev = crtc->dev;
4480         struct drm_i915_private *dev_priv = to_i915(dev);
4481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4482         int pipe = intel_crtc->pipe;
4483
4484         /*
4485          * FIXME IPS should be fine as long as one plane is
4486          * enabled, but in practice it seems to have problems
4487          * when going from primary only to sprite only and vice
4488          * versa.
4489          */
4490         hsw_enable_ips(intel_crtc);
4491
4492         /*
4493          * Gen2 reports pipe underruns whenever all planes are disabled.
4494          * So don't enable underrun reporting before at least some planes
4495          * are enabled.
4496          * FIXME: Need to fix the logic to work when we turn off all planes
4497          * but leave the pipe running.
4498          */
4499         if (IS_GEN2(dev))
4500                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4501
4502         /* Underruns don't always raise interrupts, so check manually. */
4503         intel_check_cpu_fifo_underruns(dev_priv);
4504         intel_check_pch_fifo_underruns(dev_priv);
4505 }
4506
4507 /* FIXME move all this to pre_plane_update() with proper state tracking */
4508 static void
4509 intel_pre_disable_primary(struct drm_crtc *crtc)
4510 {
4511         struct drm_device *dev = crtc->dev;
4512         struct drm_i915_private *dev_priv = to_i915(dev);
4513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514         int pipe = intel_crtc->pipe;
4515
4516         /*
4517          * Gen2 reports pipe underruns whenever all planes are disabled.
4518          * So diasble underrun reporting before all the planes get disabled.
4519          * FIXME: Need to fix the logic to work when we turn off all planes
4520          * but leave the pipe running.
4521          */
4522         if (IS_GEN2(dev))
4523                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4524
4525         /*
4526          * FIXME IPS should be fine as long as one plane is
4527          * enabled, but in practice it seems to have problems
4528          * when going from primary only to sprite only and vice
4529          * versa.
4530          */
4531         hsw_disable_ips(intel_crtc);
4532 }
4533
4534 /* FIXME get rid of this and use pre_plane_update */
4535 static void
4536 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4537 {
4538         struct drm_device *dev = crtc->dev;
4539         struct drm_i915_private *dev_priv = to_i915(dev);
4540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541         int pipe = intel_crtc->pipe;
4542
4543         intel_pre_disable_primary(crtc);
4544
4545         /*
4546          * Vblank time updates from the shadow to live plane control register
4547          * are blocked if the memory self-refresh mode is active at that
4548          * moment. So to make sure the plane gets truly disabled, disable
4549          * first the self-refresh mode. The self-refresh enable bit in turn
4550          * will be checked/applied by the HW only at the next frame start
4551          * event which is after the vblank start event, so we need to have a
4552          * wait-for-vblank between disabling the plane and the pipe.
4553          */
4554         if (HAS_GMCH_DISPLAY(dev)) {
4555                 intel_set_memory_cxsr(dev_priv, false);
4556                 dev_priv->wm.vlv.cxsr = false;
4557                 intel_wait_for_vblank(dev, pipe);
4558         }
4559 }
4560
4561 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4562 {
4563         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4564         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4565         struct intel_crtc_state *pipe_config =
4566                 to_intel_crtc_state(crtc->base.state);
4567         struct drm_device *dev = crtc->base.dev;
4568         struct drm_plane *primary = crtc->base.primary;
4569         struct drm_plane_state *old_pri_state =
4570                 drm_atomic_get_existing_plane_state(old_state, primary);
4571
4572         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4573
4574         crtc->wm.cxsr_allowed = true;
4575
4576         if (pipe_config->update_wm_post && pipe_config->base.active)
4577                 intel_update_watermarks(&crtc->base);
4578
4579         if (old_pri_state) {
4580                 struct intel_plane_state *primary_state =
4581                         to_intel_plane_state(primary->state);
4582                 struct intel_plane_state *old_primary_state =
4583                         to_intel_plane_state(old_pri_state);
4584
4585                 intel_fbc_post_update(crtc);
4586
4587                 if (primary_state->visible &&
4588                     (needs_modeset(&pipe_config->base) ||
4589                      !old_primary_state->visible))
4590                         intel_post_enable_primary(&crtc->base);
4591         }
4592 }
4593
4594 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4595 {
4596         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4597         struct drm_device *dev = crtc->base.dev;
4598         struct drm_i915_private *dev_priv = to_i915(dev);
4599         struct intel_crtc_state *pipe_config =
4600                 to_intel_crtc_state(crtc->base.state);
4601         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4602         struct drm_plane *primary = crtc->base.primary;
4603         struct drm_plane_state *old_pri_state =
4604                 drm_atomic_get_existing_plane_state(old_state, primary);
4605         bool modeset = needs_modeset(&pipe_config->base);
4606
4607         if (old_pri_state) {
4608                 struct intel_plane_state *primary_state =
4609                         to_intel_plane_state(primary->state);
4610                 struct intel_plane_state *old_primary_state =
4611                         to_intel_plane_state(old_pri_state);
4612
4613                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4614
4615                 if (old_primary_state->visible &&
4616                     (modeset || !primary_state->visible))
4617                         intel_pre_disable_primary(&crtc->base);
4618         }
4619
4620         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4621                 crtc->wm.cxsr_allowed = false;
4622
4623                 /*
4624                  * Vblank time updates from the shadow to live plane control register
4625                  * are blocked if the memory self-refresh mode is active at that
4626                  * moment. So to make sure the plane gets truly disabled, disable
4627                  * first the self-refresh mode. The self-refresh enable bit in turn
4628                  * will be checked/applied by the HW only at the next frame start
4629                  * event which is after the vblank start event, so we need to have a
4630                  * wait-for-vblank between disabling the plane and the pipe.
4631                  */
4632                 if (old_crtc_state->base.active) {
4633                         intel_set_memory_cxsr(dev_priv, false);
4634                         dev_priv->wm.vlv.cxsr = false;
4635                         intel_wait_for_vblank(dev, crtc->pipe);
4636                 }
4637         }
4638
4639         /*
4640          * IVB workaround: must disable low power watermarks for at least
4641          * one frame before enabling scaling.  LP watermarks can be re-enabled
4642          * when scaling is disabled.
4643          *
4644          * WaCxSRDisabledForSpriteScaling:ivb
4645          */
4646         if (pipe_config->disable_lp_wm) {
4647                 ilk_disable_lp_wm(dev);
4648                 intel_wait_for_vblank(dev, crtc->pipe);
4649         }
4650
4651         /*
4652          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4653          * watermark programming here.
4654          */
4655         if (needs_modeset(&pipe_config->base))
4656                 return;
4657
4658         /*
4659          * For platforms that support atomic watermarks, program the
4660          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4661          * will be the intermediate values that are safe for both pre- and
4662          * post- vblank; when vblank happens, the 'active' values will be set
4663          * to the final 'target' values and we'll do this again to get the
4664          * optimal watermarks.  For gen9+ platforms, the values we program here
4665          * will be the final target values which will get automatically latched
4666          * at vblank time; no further programming will be necessary.
4667          *
4668          * If a platform hasn't been transitioned to atomic watermarks yet,
4669          * we'll continue to update watermarks the old way, if flags tell
4670          * us to.
4671          */
4672         if (dev_priv->display.initial_watermarks != NULL)
4673                 dev_priv->display.initial_watermarks(pipe_config);
4674         else if (pipe_config->update_wm_pre)
4675                 intel_update_watermarks(&crtc->base);
4676 }
4677
4678 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4679 {
4680         struct drm_device *dev = crtc->dev;
4681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4682         struct drm_plane *p;
4683         int pipe = intel_crtc->pipe;
4684
4685         intel_crtc_dpms_overlay_disable(intel_crtc);
4686
4687         drm_for_each_plane_mask(p, dev, plane_mask)
4688                 to_intel_plane(p)->disable_plane(p, crtc);
4689
4690         /*
4691          * FIXME: Once we grow proper nuclear flip support out of this we need
4692          * to compute the mask of flip planes precisely. For the time being
4693          * consider this a flip to a NULL plane.
4694          */
4695         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4696 }
4697
4698 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         struct drm_i915_private *dev_priv = to_i915(dev);
4702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703         struct intel_encoder *encoder;
4704         int pipe = intel_crtc->pipe;
4705         struct intel_crtc_state *pipe_config =
4706                 to_intel_crtc_state(crtc->state);
4707
4708         if (WARN_ON(intel_crtc->active))
4709                 return;
4710
4711         /*
4712          * Sometimes spurious CPU pipe underruns happen during FDI
4713          * training, at least with VGA+HDMI cloning. Suppress them.
4714          *
4715          * On ILK we get an occasional spurious CPU pipe underruns
4716          * between eDP port A enable and vdd enable. Also PCH port
4717          * enable seems to result in the occasional CPU pipe underrun.
4718          *
4719          * Spurious PCH underruns also occur during PCH enabling.
4720          */
4721         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4722                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4723         if (intel_crtc->config->has_pch_encoder)
4724                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4725
4726         if (intel_crtc->config->has_pch_encoder)
4727                 intel_prepare_shared_dpll(intel_crtc);
4728
4729         if (intel_crtc_has_dp_encoder(intel_crtc->config))
4730                 intel_dp_set_m_n(intel_crtc, M1_N1);
4731
4732         intel_set_pipe_timings(intel_crtc);
4733         intel_set_pipe_src_size(intel_crtc);
4734
4735         if (intel_crtc->config->has_pch_encoder) {
4736                 intel_cpu_transcoder_set_m_n(intel_crtc,
4737                                      &intel_crtc->config->fdi_m_n, NULL);
4738         }
4739
4740         ironlake_set_pipeconf(crtc);
4741
4742         intel_crtc->active = true;
4743
4744         for_each_encoder_on_crtc(dev, crtc, encoder)
4745                 if (encoder->pre_enable)
4746                         encoder->pre_enable(encoder);
4747
4748         if (intel_crtc->config->has_pch_encoder) {
4749                 /* Note: FDI PLL enabling _must_ be done before we enable the
4750                  * cpu pipes, hence this is separate from all the other fdi/pch
4751                  * enabling. */
4752                 ironlake_fdi_pll_enable(intel_crtc);
4753         } else {
4754                 assert_fdi_tx_disabled(dev_priv, pipe);
4755                 assert_fdi_rx_disabled(dev_priv, pipe);
4756         }
4757
4758         ironlake_pfit_enable(intel_crtc);
4759
4760         /*
4761          * On ILK+ LUT must be loaded before the pipe is running but with
4762          * clocks enabled
4763          */
4764         intel_color_load_luts(&pipe_config->base);
4765
4766         if (dev_priv->display.initial_watermarks != NULL)
4767                 dev_priv->display.initial_watermarks(intel_crtc->config);
4768         intel_enable_pipe(intel_crtc);
4769
4770         if (intel_crtc->config->has_pch_encoder)
4771                 ironlake_pch_enable(crtc);
4772
4773         assert_vblank_disabled(crtc);
4774         drm_crtc_vblank_on(crtc);
4775
4776         for_each_encoder_on_crtc(dev, crtc, encoder)
4777                 encoder->enable(encoder);
4778
4779         if (HAS_PCH_CPT(dev))
4780                 cpt_verify_modeset(dev, intel_crtc->pipe);
4781
4782         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4783         if (intel_crtc->config->has_pch_encoder)
4784                 intel_wait_for_vblank(dev, pipe);
4785         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4786         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4787 }
4788
4789 /* IPS only exists on ULT machines and is tied to pipe A. */
4790 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4791 {
4792         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4793 }
4794
4795 static void haswell_crtc_enable(struct drm_crtc *crtc)
4796 {
4797         struct drm_device *dev = crtc->dev;
4798         struct drm_i915_private *dev_priv = to_i915(dev);
4799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4800         struct intel_encoder *encoder;
4801         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4802         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4803         struct intel_crtc_state *pipe_config =
4804                 to_intel_crtc_state(crtc->state);
4805
4806         if (WARN_ON(intel_crtc->active))
4807                 return;
4808
4809         if (intel_crtc->config->has_pch_encoder)
4810                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4811                                                       false);
4812
4813         for_each_encoder_on_crtc(dev, crtc, encoder)
4814                 if (encoder->pre_pll_enable)
4815                         encoder->pre_pll_enable(encoder);
4816
4817         if (intel_crtc->config->shared_dpll)
4818                 intel_enable_shared_dpll(intel_crtc);
4819
4820         if (intel_crtc_has_dp_encoder(intel_crtc->config))
4821                 intel_dp_set_m_n(intel_crtc, M1_N1);
4822
4823         if (!transcoder_is_dsi(cpu_transcoder))
4824                 intel_set_pipe_timings(intel_crtc);
4825
4826         intel_set_pipe_src_size(intel_crtc);
4827
4828         if (cpu_transcoder != TRANSCODER_EDP &&
4829             !transcoder_is_dsi(cpu_transcoder)) {
4830                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4831                            intel_crtc->config->pixel_multiplier - 1);
4832         }
4833
4834         if (intel_crtc->config->has_pch_encoder) {
4835                 intel_cpu_transcoder_set_m_n(intel_crtc,
4836                                      &intel_crtc->config->fdi_m_n, NULL);
4837         }
4838
4839         if (!transcoder_is_dsi(cpu_transcoder))
4840                 haswell_set_pipeconf(crtc);
4841
4842         haswell_set_pipemisc(crtc);
4843
4844         intel_color_set_csc(&pipe_config->base);
4845
4846         intel_crtc->active = true;
4847
4848         if (intel_crtc->config->has_pch_encoder)
4849                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4850         else
4851                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4852
4853         for_each_encoder_on_crtc(dev, crtc, encoder) {
4854                 if (encoder->pre_enable)
4855                         encoder->pre_enable(encoder);
4856         }
4857
4858         if (intel_crtc->config->has_pch_encoder)
4859                 dev_priv->display.fdi_link_train(crtc);
4860
4861         if (!transcoder_is_dsi(cpu_transcoder))
4862                 intel_ddi_enable_pipe_clock(intel_crtc);
4863
4864         if (INTEL_INFO(dev)->gen >= 9)
4865                 skylake_pfit_enable(intel_crtc);
4866         else
4867                 ironlake_pfit_enable(intel_crtc);
4868
4869         /*
4870          * On ILK+ LUT must be loaded before the pipe is running but with
4871          * clocks enabled
4872          */
4873         intel_color_load_luts(&pipe_config->base);
4874
4875         intel_ddi_set_pipe_settings(crtc);
4876         if (!transcoder_is_dsi(cpu_transcoder))
4877                 intel_ddi_enable_transcoder_func(crtc);
4878
4879         if (dev_priv->display.initial_watermarks != NULL)
4880                 dev_priv->display.initial_watermarks(pipe_config);
4881         else
4882                 intel_update_watermarks(crtc);
4883
4884         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4885         if (!transcoder_is_dsi(cpu_transcoder))
4886                 intel_enable_pipe(intel_crtc);
4887
4888         if (intel_crtc->config->has_pch_encoder)
4889                 lpt_pch_enable(crtc);
4890
4891         if (intel_crtc->config->dp_encoder_is_mst)
4892                 intel_ddi_set_vc_payload_alloc(crtc, true);
4893
4894         assert_vblank_disabled(crtc);
4895         drm_crtc_vblank_on(crtc);
4896
4897         for_each_encoder_on_crtc(dev, crtc, encoder) {
4898                 encoder->enable(encoder);
4899                 intel_opregion_notify_encoder(encoder, true);
4900         }
4901
4902         if (intel_crtc->config->has_pch_encoder) {
4903                 intel_wait_for_vblank(dev, pipe);
4904                 intel_wait_for_vblank(dev, pipe);
4905                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4907                                                       true);
4908         }
4909
4910         /* If we change the relative order between pipe/planes enabling, we need
4911          * to change the workaround. */
4912         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4913         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4914                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4915                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4916         }
4917 }
4918
4919 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4920 {
4921         struct drm_device *dev = crtc->base.dev;
4922         struct drm_i915_private *dev_priv = to_i915(dev);
4923         int pipe = crtc->pipe;
4924
4925         /* To avoid upsetting the power well on haswell only disable the pfit if
4926          * it's in use. The hw state code will make sure we get this right. */
4927         if (force || crtc->config->pch_pfit.enabled) {
4928                 I915_WRITE(PF_CTL(pipe), 0);
4929                 I915_WRITE(PF_WIN_POS(pipe), 0);
4930                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4931         }
4932 }
4933
4934 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4935 {
4936         struct drm_device *dev = crtc->dev;
4937         struct drm_i915_private *dev_priv = to_i915(dev);
4938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4939         struct intel_encoder *encoder;
4940         int pipe = intel_crtc->pipe;
4941
4942         /*
4943          * Sometimes spurious CPU pipe underruns happen when the
4944          * pipe is already disabled, but FDI RX/TX is still enabled.
4945          * Happens at least with VGA+HDMI cloning. Suppress them.
4946          */
4947         if (intel_crtc->config->has_pch_encoder) {
4948                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4949                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4950         }
4951
4952         for_each_encoder_on_crtc(dev, crtc, encoder)
4953                 encoder->disable(encoder);
4954
4955         drm_crtc_vblank_off(crtc);
4956         assert_vblank_disabled(crtc);
4957
4958         intel_disable_pipe(intel_crtc);
4959
4960         ironlake_pfit_disable(intel_crtc, false);
4961
4962         if (intel_crtc->config->has_pch_encoder)
4963                 ironlake_fdi_disable(crtc);
4964
4965         for_each_encoder_on_crtc(dev, crtc, encoder)
4966                 if (encoder->post_disable)
4967                         encoder->post_disable(encoder);
4968
4969         if (intel_crtc->config->has_pch_encoder) {
4970                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4971
4972                 if (HAS_PCH_CPT(dev)) {
4973                         i915_reg_t reg;
4974                         u32 temp;
4975
4976                         /* disable TRANS_DP_CTL */
4977                         reg = TRANS_DP_CTL(pipe);
4978                         temp = I915_READ(reg);
4979                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4980                                   TRANS_DP_PORT_SEL_MASK);
4981                         temp |= TRANS_DP_PORT_SEL_NONE;
4982                         I915_WRITE(reg, temp);
4983
4984                         /* disable DPLL_SEL */
4985                         temp = I915_READ(PCH_DPLL_SEL);
4986                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4987                         I915_WRITE(PCH_DPLL_SEL, temp);
4988                 }
4989
4990                 ironlake_fdi_pll_disable(intel_crtc);
4991         }
4992
4993         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4994         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4995 }
4996
4997 static void haswell_crtc_disable(struct drm_crtc *crtc)
4998 {
4999         struct drm_device *dev = crtc->dev;
5000         struct drm_i915_private *dev_priv = to_i915(dev);
5001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002         struct intel_encoder *encoder;
5003         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5004
5005         if (intel_crtc->config->has_pch_encoder)
5006                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5007                                                       false);
5008
5009         for_each_encoder_on_crtc(dev, crtc, encoder) {
5010                 intel_opregion_notify_encoder(encoder, false);
5011                 encoder->disable(encoder);
5012         }
5013
5014         drm_crtc_vblank_off(crtc);
5015         assert_vblank_disabled(crtc);
5016
5017         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5018         if (!transcoder_is_dsi(cpu_transcoder))
5019                 intel_disable_pipe(intel_crtc);
5020
5021         if (intel_crtc->config->dp_encoder_is_mst)
5022                 intel_ddi_set_vc_payload_alloc(crtc, false);
5023
5024         if (!transcoder_is_dsi(cpu_transcoder))
5025                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5026
5027         if (INTEL_INFO(dev)->gen >= 9)
5028                 skylake_scaler_disable(intel_crtc);
5029         else
5030                 ironlake_pfit_disable(intel_crtc, false);
5031
5032         if (!transcoder_is_dsi(cpu_transcoder))
5033                 intel_ddi_disable_pipe_clock(intel_crtc);
5034
5035         for_each_encoder_on_crtc(dev, crtc, encoder)
5036                 if (encoder->post_disable)
5037                         encoder->post_disable(encoder);
5038
5039         if (intel_crtc->config->has_pch_encoder) {
5040                 lpt_disable_pch_transcoder(dev_priv);
5041                 lpt_disable_iclkip(dev_priv);
5042                 intel_ddi_fdi_disable(crtc);
5043
5044                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5045                                                       true);
5046         }
5047 }
5048
5049 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5050 {
5051         struct drm_device *dev = crtc->base.dev;
5052         struct drm_i915_private *dev_priv = to_i915(dev);
5053         struct intel_crtc_state *pipe_config = crtc->config;
5054
5055         if (!pipe_config->gmch_pfit.control)
5056                 return;
5057
5058         /*
5059          * The panel fitter should only be adjusted whilst the pipe is disabled,
5060          * according to register description and PRM.
5061          */
5062         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5063         assert_pipe_disabled(dev_priv, crtc->pipe);
5064
5065         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5066         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5067
5068         /* Border color in case we don't scale up to the full screen. Black by
5069          * default, change to something else for debugging. */
5070         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5071 }
5072
5073 static enum intel_display_power_domain port_to_power_domain(enum port port)
5074 {
5075         switch (port) {
5076         case PORT_A:
5077                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5078         case PORT_B:
5079                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5080         case PORT_C:
5081                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5082         case PORT_D:
5083                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5084         case PORT_E:
5085                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5086         default:
5087                 MISSING_CASE(port);
5088                 return POWER_DOMAIN_PORT_OTHER;
5089         }
5090 }
5091
5092 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5093 {
5094         switch (port) {
5095         case PORT_A:
5096                 return POWER_DOMAIN_AUX_A;
5097         case PORT_B:
5098                 return POWER_DOMAIN_AUX_B;
5099         case PORT_C:
5100                 return POWER_DOMAIN_AUX_C;
5101         case PORT_D:
5102                 return POWER_DOMAIN_AUX_D;
5103         case PORT_E:
5104                 /* FIXME: Check VBT for actual wiring of PORT E */
5105                 return POWER_DOMAIN_AUX_D;
5106         default:
5107                 MISSING_CASE(port);
5108                 return POWER_DOMAIN_AUX_A;
5109         }
5110 }
5111
5112 enum intel_display_power_domain
5113 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5114 {
5115         struct drm_device *dev = intel_encoder->base.dev;
5116         struct intel_digital_port *intel_dig_port;
5117
5118         switch (intel_encoder->type) {
5119         case INTEL_OUTPUT_UNKNOWN:
5120                 /* Only DDI platforms should ever use this output type */
5121                 WARN_ON_ONCE(!HAS_DDI(dev));
5122         case INTEL_OUTPUT_DP:
5123         case INTEL_OUTPUT_HDMI:
5124         case INTEL_OUTPUT_EDP:
5125                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5126                 return port_to_power_domain(intel_dig_port->port);
5127         case INTEL_OUTPUT_DP_MST:
5128                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5129                 return port_to_power_domain(intel_dig_port->port);
5130         case INTEL_OUTPUT_ANALOG:
5131                 return POWER_DOMAIN_PORT_CRT;
5132         case INTEL_OUTPUT_DSI:
5133                 return POWER_DOMAIN_PORT_DSI;
5134         default:
5135                 return POWER_DOMAIN_PORT_OTHER;
5136         }
5137 }
5138
5139 enum intel_display_power_domain
5140 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5141 {
5142         struct drm_device *dev = intel_encoder->base.dev;
5143         struct intel_digital_port *intel_dig_port;
5144
5145         switch (intel_encoder->type) {
5146         case INTEL_OUTPUT_UNKNOWN:
5147         case INTEL_OUTPUT_HDMI:
5148                 /*
5149                  * Only DDI platforms should ever use these output types.
5150                  * We can get here after the HDMI detect code has already set
5151                  * the type of the shared encoder. Since we can't be sure
5152                  * what's the status of the given connectors, play safe and
5153                  * run the DP detection too.
5154                  */
5155                 WARN_ON_ONCE(!HAS_DDI(dev));
5156         case INTEL_OUTPUT_DP:
5157         case INTEL_OUTPUT_EDP:
5158                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5159                 return port_to_aux_power_domain(intel_dig_port->port);
5160         case INTEL_OUTPUT_DP_MST:
5161                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5162                 return port_to_aux_power_domain(intel_dig_port->port);
5163         default:
5164                 MISSING_CASE(intel_encoder->type);
5165                 return POWER_DOMAIN_AUX_A;
5166         }
5167 }
5168
5169 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5170                                             struct intel_crtc_state *crtc_state)
5171 {
5172         struct drm_device *dev = crtc->dev;
5173         struct drm_encoder *encoder;
5174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175         enum pipe pipe = intel_crtc->pipe;
5176         unsigned long mask;
5177         enum transcoder transcoder = crtc_state->cpu_transcoder;
5178
5179         if (!crtc_state->base.active)
5180                 return 0;
5181
5182         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5183         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5184         if (crtc_state->pch_pfit.enabled ||
5185             crtc_state->pch_pfit.force_thru)
5186                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5187
5188         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5189                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5190
5191                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5192         }
5193
5194         if (crtc_state->shared_dpll)
5195                 mask |= BIT(POWER_DOMAIN_PLLS);
5196
5197         return mask;
5198 }
5199
5200 static unsigned long
5201 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5202                                struct intel_crtc_state *crtc_state)
5203 {
5204         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206         enum intel_display_power_domain domain;
5207         unsigned long domains, new_domains, old_domains;
5208
5209         old_domains = intel_crtc->enabled_power_domains;
5210         intel_crtc->enabled_power_domains = new_domains =
5211                 get_crtc_power_domains(crtc, crtc_state);
5212
5213         domains = new_domains & ~old_domains;
5214
5215         for_each_power_domain(domain, domains)
5216                 intel_display_power_get(dev_priv, domain);
5217
5218         return old_domains & ~new_domains;
5219 }
5220
5221 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5222                                       unsigned long domains)
5223 {
5224         enum intel_display_power_domain domain;
5225
5226         for_each_power_domain(domain, domains)
5227                 intel_display_power_put(dev_priv, domain);
5228 }
5229
5230 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5231 {
5232         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5233
5234         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5235             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5236                 return max_cdclk_freq;
5237         else if (IS_CHERRYVIEW(dev_priv))
5238                 return max_cdclk_freq*95/100;
5239         else if (INTEL_INFO(dev_priv)->gen < 4)
5240                 return 2*max_cdclk_freq*90/100;
5241         else
5242                 return max_cdclk_freq*90/100;
5243 }
5244
5245 static int skl_calc_cdclk(int max_pixclk, int vco);
5246
5247 static void intel_update_max_cdclk(struct drm_device *dev)
5248 {
5249         struct drm_i915_private *dev_priv = to_i915(dev);
5250
5251         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5252                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5253                 int max_cdclk, vco;
5254
5255                 vco = dev_priv->skl_preferred_vco_freq;
5256                 WARN_ON(vco != 8100000 && vco != 8640000);
5257
5258                 /*
5259                  * Use the lower (vco 8640) cdclk values as a
5260                  * first guess. skl_calc_cdclk() will correct it
5261                  * if the preferred vco is 8100 instead.
5262                  */
5263                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5264                         max_cdclk = 617143;
5265                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5266                         max_cdclk = 540000;
5267                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5268                         max_cdclk = 432000;
5269                 else
5270                         max_cdclk = 308571;
5271
5272                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5273         } else if (IS_BROXTON(dev)) {
5274                 dev_priv->max_cdclk_freq = 624000;
5275         } else if (IS_BROADWELL(dev))  {
5276                 /*
5277                  * FIXME with extra cooling we can allow
5278                  * 540 MHz for ULX and 675 Mhz for ULT.
5279                  * How can we know if extra cooling is
5280                  * available? PCI ID, VTB, something else?
5281                  */
5282                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5283                         dev_priv->max_cdclk_freq = 450000;
5284                 else if (IS_BDW_ULX(dev))
5285                         dev_priv->max_cdclk_freq = 450000;
5286                 else if (IS_BDW_ULT(dev))
5287                         dev_priv->max_cdclk_freq = 540000;
5288                 else
5289                         dev_priv->max_cdclk_freq = 675000;
5290         } else if (IS_CHERRYVIEW(dev)) {
5291                 dev_priv->max_cdclk_freq = 320000;
5292         } else if (IS_VALLEYVIEW(dev)) {
5293                 dev_priv->max_cdclk_freq = 400000;
5294         } else {
5295                 /* otherwise assume cdclk is fixed */
5296                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5297         }
5298
5299         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5300
5301         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302                          dev_priv->max_cdclk_freq);
5303
5304         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5305                          dev_priv->max_dotclk_freq);
5306 }
5307
5308 static void intel_update_cdclk(struct drm_device *dev)
5309 {
5310         struct drm_i915_private *dev_priv = to_i915(dev);
5311
5312         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5313
5314         if (INTEL_GEN(dev_priv) >= 9)
5315                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5316                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5317                                  dev_priv->cdclk_pll.ref);
5318         else
5319                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5320                                  dev_priv->cdclk_freq);
5321
5322         /*
5323          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5324          * Programmng [sic] note: bit[9:2] should be programmed to the number
5325          * of cdclk that generates 4MHz reference clock freq which is used to
5326          * generate GMBus clock. This will vary with the cdclk freq.
5327          */
5328         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5329                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5330 }
5331
5332 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5333 static int skl_cdclk_decimal(int cdclk)
5334 {
5335         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5336 }
5337
5338 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5339 {
5340         int ratio;
5341
5342         if (cdclk == dev_priv->cdclk_pll.ref)
5343                 return 0;
5344
5345         switch (cdclk) {
5346         default:
5347                 MISSING_CASE(cdclk);
5348         case 144000:
5349         case 288000:
5350         case 384000:
5351         case 576000:
5352                 ratio = 60;
5353                 break;
5354         case 624000:
5355                 ratio = 65;
5356                 break;
5357         }
5358
5359         return dev_priv->cdclk_pll.ref * ratio;
5360 }
5361
5362 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5363 {
5364         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5365
5366         /* Timeout 200us */
5367         if (intel_wait_for_register(dev_priv,
5368                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5369                                     1))
5370                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5371
5372         dev_priv->cdclk_pll.vco = 0;
5373 }
5374
5375 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5376 {
5377         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5378         u32 val;
5379
5380         val = I915_READ(BXT_DE_PLL_CTL);
5381         val &= ~BXT_DE_PLL_RATIO_MASK;
5382         val |= BXT_DE_PLL_RATIO(ratio);
5383         I915_WRITE(BXT_DE_PLL_CTL, val);
5384
5385         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5386
5387         /* Timeout 200us */
5388         if (intel_wait_for_register(dev_priv,
5389                                     BXT_DE_PLL_ENABLE,
5390                                     BXT_DE_PLL_LOCK,
5391                                     BXT_DE_PLL_LOCK,
5392                                     1))
5393                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5394
5395         dev_priv->cdclk_pll.vco = vco;
5396 }
5397
5398 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5399 {
5400         u32 val, divider;
5401         int vco, ret;
5402
5403         vco = bxt_de_pll_vco(dev_priv, cdclk);
5404
5405         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5406
5407         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5408         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5409         case 8:
5410                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5411                 break;
5412         case 4:
5413                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5414                 break;
5415         case 3:
5416                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5417                 break;
5418         case 2:
5419                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5420                 break;
5421         default:
5422                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5423                 WARN_ON(vco != 0);
5424
5425                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5426                 break;
5427         }
5428
5429         /* Inform power controller of upcoming frequency change */
5430         mutex_lock(&dev_priv->rps.hw_lock);
5431         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5432                                       0x80000000);
5433         mutex_unlock(&dev_priv->rps.hw_lock);
5434
5435         if (ret) {
5436                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5437                           ret, cdclk);
5438                 return;
5439         }
5440
5441         if (dev_priv->cdclk_pll.vco != 0 &&
5442             dev_priv->cdclk_pll.vco != vco)
5443                 bxt_de_pll_disable(dev_priv);
5444
5445         if (dev_priv->cdclk_pll.vco != vco)
5446                 bxt_de_pll_enable(dev_priv, vco);
5447
5448         val = divider | skl_cdclk_decimal(cdclk);
5449         /*
5450          * FIXME if only the cd2x divider needs changing, it could be done
5451          * without shutting off the pipe (if only one pipe is active).
5452          */
5453         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5454         /*
5455          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5456          * enable otherwise.
5457          */
5458         if (cdclk >= 500000)
5459                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5460         I915_WRITE(CDCLK_CTL, val);
5461
5462         mutex_lock(&dev_priv->rps.hw_lock);
5463         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5464                                       DIV_ROUND_UP(cdclk, 25000));
5465         mutex_unlock(&dev_priv->rps.hw_lock);
5466
5467         if (ret) {
5468                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5469                           ret, cdclk);
5470                 return;
5471         }
5472
5473         intel_update_cdclk(&dev_priv->drm);
5474 }
5475
5476 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5477 {
5478         u32 cdctl, expected;
5479
5480         intel_update_cdclk(&dev_priv->drm);
5481
5482         if (dev_priv->cdclk_pll.vco == 0 ||
5483             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5484                 goto sanitize;
5485
5486         /* DPLL okay; verify the cdclock
5487          *
5488          * Some BIOS versions leave an incorrect decimal frequency value and
5489          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5490          * so sanitize this register.
5491          */
5492         cdctl = I915_READ(CDCLK_CTL);
5493         /*
5494          * Let's ignore the pipe field, since BIOS could have configured the
5495          * dividers both synching to an active pipe, or asynchronously
5496          * (PIPE_NONE).
5497          */
5498         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5499
5500         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5501                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5502         /*
5503          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5504          * enable otherwise.
5505          */
5506         if (dev_priv->cdclk_freq >= 500000)
5507                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5508
5509         if (cdctl == expected)
5510                 /* All well; nothing to sanitize */
5511                 return;
5512
5513 sanitize:
5514         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5515
5516         /* force cdclk programming */
5517         dev_priv->cdclk_freq = 0;
5518
5519         /* force full PLL disable + enable */
5520         dev_priv->cdclk_pll.vco = -1;
5521 }
5522
5523 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5524 {
5525         bxt_sanitize_cdclk(dev_priv);
5526
5527         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5528                 return;
5529
5530         /*
5531          * FIXME:
5532          * - The initial CDCLK needs to be read from VBT.
5533          *   Need to make this change after VBT has changes for BXT.
5534          */
5535         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5536 }
5537
5538 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5539 {
5540         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5541 }
5542
5543 static int skl_calc_cdclk(int max_pixclk, int vco)
5544 {
5545         if (vco == 8640000) {
5546                 if (max_pixclk > 540000)
5547                         return 617143;
5548                 else if (max_pixclk > 432000)
5549                         return 540000;
5550                 else if (max_pixclk > 308571)
5551                         return 432000;
5552                 else
5553                         return 308571;
5554         } else {
5555                 if (max_pixclk > 540000)
5556                         return 675000;
5557                 else if (max_pixclk > 450000)
5558                         return 540000;
5559                 else if (max_pixclk > 337500)
5560                         return 450000;
5561                 else
5562                         return 337500;
5563         }
5564 }
5565
5566 static void
5567 skl_dpll0_update(struct drm_i915_private *dev_priv)
5568 {
5569         u32 val;
5570
5571         dev_priv->cdclk_pll.ref = 24000;
5572         dev_priv->cdclk_pll.vco = 0;
5573
5574         val = I915_READ(LCPLL1_CTL);
5575         if ((val & LCPLL_PLL_ENABLE) == 0)
5576                 return;
5577
5578         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5579                 return;
5580
5581         val = I915_READ(DPLL_CTRL1);
5582
5583         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5584                             DPLL_CTRL1_SSC(SKL_DPLL0) |
5585                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5586                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5587                 return;
5588
5589         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5590         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5591         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5592         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5593         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5594                 dev_priv->cdclk_pll.vco = 8100000;
5595                 break;
5596         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5597         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5598                 dev_priv->cdclk_pll.vco = 8640000;
5599                 break;
5600         default:
5601                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5602                 break;
5603         }
5604 }
5605
5606 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5607 {
5608         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5609
5610         dev_priv->skl_preferred_vco_freq = vco;
5611
5612         if (changed)
5613                 intel_update_max_cdclk(&dev_priv->drm);
5614 }
5615
5616 static void
5617 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5618 {
5619         int min_cdclk = skl_calc_cdclk(0, vco);
5620         u32 val;
5621
5622         WARN_ON(vco != 8100000 && vco != 8640000);
5623
5624         /* select the minimum CDCLK before enabling DPLL 0 */
5625         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5626         I915_WRITE(CDCLK_CTL, val);
5627         POSTING_READ(CDCLK_CTL);
5628
5629         /*
5630          * We always enable DPLL0 with the lowest link rate possible, but still
5631          * taking into account the VCO required to operate the eDP panel at the
5632          * desired frequency. The usual DP link rates operate with a VCO of
5633          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5634          * The modeset code is responsible for the selection of the exact link
5635          * rate later on, with the constraint of choosing a frequency that
5636          * works with vco.
5637          */
5638         val = I915_READ(DPLL_CTRL1);
5639
5640         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5641                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5642         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5643         if (vco == 8640000)
5644                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5645                                             SKL_DPLL0);
5646         else
5647                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5648                                             SKL_DPLL0);
5649
5650         I915_WRITE(DPLL_CTRL1, val);
5651         POSTING_READ(DPLL_CTRL1);
5652
5653         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5654
5655         if (intel_wait_for_register(dev_priv,
5656                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5657                                     5))
5658                 DRM_ERROR("DPLL0 not locked\n");
5659
5660         dev_priv->cdclk_pll.vco = vco;
5661
5662         /* We'll want to keep using the current vco from now on. */
5663         skl_set_preferred_cdclk_vco(dev_priv, vco);
5664 }
5665
5666 static void
5667 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5668 {
5669         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5670         if (intel_wait_for_register(dev_priv,
5671                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
5672                                    1))
5673                 DRM_ERROR("Couldn't disable DPLL0\n");
5674
5675         dev_priv->cdclk_pll.vco = 0;
5676 }
5677
5678 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5679 {
5680         int ret;
5681         u32 val;
5682
5683         /* inform PCU we want to change CDCLK */
5684         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5685         mutex_lock(&dev_priv->rps.hw_lock);
5686         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5687         mutex_unlock(&dev_priv->rps.hw_lock);
5688
5689         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5690 }
5691
5692 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5693 {
5694         unsigned int i;
5695
5696         for (i = 0; i < 15; i++) {
5697                 if (skl_cdclk_pcu_ready(dev_priv))
5698                         return true;
5699                 udelay(10);
5700         }
5701
5702         return false;
5703 }
5704
5705 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5706 {
5707         struct drm_device *dev = &dev_priv->drm;
5708         u32 freq_select, pcu_ack;
5709
5710         WARN_ON((cdclk == 24000) != (vco == 0));
5711
5712         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5713
5714         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5715                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5716                 return;
5717         }
5718
5719         /* set CDCLK_CTL */
5720         switch (cdclk) {
5721         case 450000:
5722         case 432000:
5723                 freq_select = CDCLK_FREQ_450_432;
5724                 pcu_ack = 1;
5725                 break;
5726         case 540000:
5727                 freq_select = CDCLK_FREQ_540;
5728                 pcu_ack = 2;
5729                 break;
5730         case 308571:
5731         case 337500:
5732         default:
5733                 freq_select = CDCLK_FREQ_337_308;
5734                 pcu_ack = 0;
5735                 break;
5736         case 617143:
5737         case 675000:
5738                 freq_select = CDCLK_FREQ_675_617;
5739                 pcu_ack = 3;
5740                 break;
5741         }
5742
5743         if (dev_priv->cdclk_pll.vco != 0 &&
5744             dev_priv->cdclk_pll.vco != vco)
5745                 skl_dpll0_disable(dev_priv);
5746
5747         if (dev_priv->cdclk_pll.vco != vco)
5748                 skl_dpll0_enable(dev_priv, vco);
5749
5750         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5751         POSTING_READ(CDCLK_CTL);
5752
5753         /* inform PCU of the change */
5754         mutex_lock(&dev_priv->rps.hw_lock);
5755         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5756         mutex_unlock(&dev_priv->rps.hw_lock);
5757
5758         intel_update_cdclk(dev);
5759 }
5760
5761 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5762
5763 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5764 {
5765         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5766 }
5767
5768 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5769 {
5770         int cdclk, vco;
5771
5772         skl_sanitize_cdclk(dev_priv);
5773
5774         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5775                 /*
5776                  * Use the current vco as our initial
5777                  * guess as to what the preferred vco is.
5778                  */
5779                 if (dev_priv->skl_preferred_vco_freq == 0)
5780                         skl_set_preferred_cdclk_vco(dev_priv,
5781                                                     dev_priv->cdclk_pll.vco);
5782                 return;
5783         }
5784
5785         vco = dev_priv->skl_preferred_vco_freq;
5786         if (vco == 0)
5787                 vco = 8100000;
5788         cdclk = skl_calc_cdclk(0, vco);
5789
5790         skl_set_cdclk(dev_priv, cdclk, vco);
5791 }
5792
5793 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5794 {
5795         uint32_t cdctl, expected;
5796
5797         /*
5798          * check if the pre-os intialized the display
5799          * There is SWF18 scratchpad register defined which is set by the
5800          * pre-os which can be used by the OS drivers to check the status
5801          */
5802         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5803                 goto sanitize;
5804
5805         intel_update_cdclk(&dev_priv->drm);
5806         /* Is PLL enabled and locked ? */
5807         if (dev_priv->cdclk_pll.vco == 0 ||
5808             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5809                 goto sanitize;
5810
5811         /* DPLL okay; verify the cdclock
5812          *
5813          * Noticed in some instances that the freq selection is correct but
5814          * decimal part is programmed wrong from BIOS where pre-os does not
5815          * enable display. Verify the same as well.
5816          */
5817         cdctl = I915_READ(CDCLK_CTL);
5818         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5819                 skl_cdclk_decimal(dev_priv->cdclk_freq);
5820         if (cdctl == expected)
5821                 /* All well; nothing to sanitize */
5822                 return;
5823
5824 sanitize:
5825         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5826
5827         /* force cdclk programming */
5828         dev_priv->cdclk_freq = 0;
5829         /* force full PLL disable + enable */
5830         dev_priv->cdclk_pll.vco = -1;
5831 }
5832
5833 /* Adjust CDclk dividers to allow high res or save power if possible */
5834 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5835 {
5836         struct drm_i915_private *dev_priv = to_i915(dev);
5837         u32 val, cmd;
5838
5839         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5840                                         != dev_priv->cdclk_freq);
5841
5842         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5843                 cmd = 2;
5844         else if (cdclk == 266667)
5845                 cmd = 1;
5846         else
5847                 cmd = 0;
5848
5849         mutex_lock(&dev_priv->rps.hw_lock);
5850         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5851         val &= ~DSPFREQGUAR_MASK;
5852         val |= (cmd << DSPFREQGUAR_SHIFT);
5853         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5854         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5855                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5856                      50)) {
5857                 DRM_ERROR("timed out waiting for CDclk change\n");
5858         }
5859         mutex_unlock(&dev_priv->rps.hw_lock);
5860
5861         mutex_lock(&dev_priv->sb_lock);
5862
5863         if (cdclk == 400000) {
5864                 u32 divider;
5865
5866                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5867
5868                 /* adjust cdclk divider */
5869                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5870                 val &= ~CCK_FREQUENCY_VALUES;
5871                 val |= divider;
5872                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5873
5874                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5875                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5876                              50))
5877                         DRM_ERROR("timed out waiting for CDclk change\n");
5878         }
5879
5880         /* adjust self-refresh exit latency value */
5881         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5882         val &= ~0x7f;
5883
5884         /*
5885          * For high bandwidth configs, we set a higher latency in the bunit
5886          * so that the core display fetch happens in time to avoid underruns.
5887          */
5888         if (cdclk == 400000)
5889                 val |= 4500 / 250; /* 4.5 usec */
5890         else
5891                 val |= 3000 / 250; /* 3.0 usec */
5892         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5893
5894         mutex_unlock(&dev_priv->sb_lock);
5895
5896         intel_update_cdclk(dev);
5897 }
5898
5899 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5900 {
5901         struct drm_i915_private *dev_priv = to_i915(dev);
5902         u32 val, cmd;
5903
5904         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5905                                                 != dev_priv->cdclk_freq);
5906
5907         switch (cdclk) {
5908         case 333333:
5909         case 320000:
5910         case 266667:
5911         case 200000:
5912                 break;
5913         default:
5914                 MISSING_CASE(cdclk);
5915                 return;
5916         }
5917
5918         /*
5919          * Specs are full of misinformation, but testing on actual
5920          * hardware has shown that we just need to write the desired
5921          * CCK divider into the Punit register.
5922          */
5923         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5924
5925         mutex_lock(&dev_priv->rps.hw_lock);
5926         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5927         val &= ~DSPFREQGUAR_MASK_CHV;
5928         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5929         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5930         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5931                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5932                      50)) {
5933                 DRM_ERROR("timed out waiting for CDclk change\n");
5934         }
5935         mutex_unlock(&dev_priv->rps.hw_lock);
5936
5937         intel_update_cdclk(dev);
5938 }
5939
5940 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5941                                  int max_pixclk)
5942 {
5943         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5944         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5945
5946         /*
5947          * Really only a few cases to deal with, as only 4 CDclks are supported:
5948          *   200MHz
5949          *   267MHz
5950          *   320/333MHz (depends on HPLL freq)
5951          *   400MHz (VLV only)
5952          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5953          * of the lower bin and adjust if needed.
5954          *
5955          * We seem to get an unstable or solid color picture at 200MHz.
5956          * Not sure what's wrong. For now use 200MHz only when all pipes
5957          * are off.
5958          */
5959         if (!IS_CHERRYVIEW(dev_priv) &&
5960             max_pixclk > freq_320*limit/100)
5961                 return 400000;
5962         else if (max_pixclk > 266667*limit/100)
5963                 return freq_320;
5964         else if (max_pixclk > 0)
5965                 return 266667;
5966         else
5967                 return 200000;
5968 }
5969
5970 static int bxt_calc_cdclk(int max_pixclk)
5971 {
5972         if (max_pixclk > 576000)
5973                 return 624000;
5974         else if (max_pixclk > 384000)
5975                 return 576000;
5976         else if (max_pixclk > 288000)
5977                 return 384000;
5978         else if (max_pixclk > 144000)
5979                 return 288000;
5980         else
5981                 return 144000;
5982 }
5983
5984 /* Compute the max pixel clock for new configuration. */
5985 static int intel_mode_max_pixclk(struct drm_device *dev,
5986                                  struct drm_atomic_state *state)
5987 {
5988         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5989         struct drm_i915_private *dev_priv = to_i915(dev);
5990         struct drm_crtc *crtc;
5991         struct drm_crtc_state *crtc_state;
5992         unsigned max_pixclk = 0, i;
5993         enum pipe pipe;
5994
5995         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5996                sizeof(intel_state->min_pixclk));
5997
5998         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5999                 int pixclk = 0;
6000
6001                 if (crtc_state->enable)
6002                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6003
6004                 intel_state->min_pixclk[i] = pixclk;
6005         }
6006
6007         for_each_pipe(dev_priv, pipe)
6008                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6009
6010         return max_pixclk;
6011 }
6012
6013 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6014 {
6015         struct drm_device *dev = state->dev;
6016         struct drm_i915_private *dev_priv = to_i915(dev);
6017         int max_pixclk = intel_mode_max_pixclk(dev, state);
6018         struct intel_atomic_state *intel_state =
6019                 to_intel_atomic_state(state);
6020
6021         intel_state->cdclk = intel_state->dev_cdclk =
6022                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6023
6024         if (!intel_state->active_crtcs)
6025                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6026
6027         return 0;
6028 }
6029
6030 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6031 {
6032         int max_pixclk = ilk_max_pixel_rate(state);
6033         struct intel_atomic_state *intel_state =
6034                 to_intel_atomic_state(state);
6035
6036         intel_state->cdclk = intel_state->dev_cdclk =
6037                 bxt_calc_cdclk(max_pixclk);
6038
6039         if (!intel_state->active_crtcs)
6040                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6041
6042         return 0;
6043 }
6044
6045 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6046 {
6047         unsigned int credits, default_credits;
6048
6049         if (IS_CHERRYVIEW(dev_priv))
6050                 default_credits = PFI_CREDIT(12);
6051         else
6052                 default_credits = PFI_CREDIT(8);
6053
6054         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6055                 /* CHV suggested value is 31 or 63 */
6056                 if (IS_CHERRYVIEW(dev_priv))
6057                         credits = PFI_CREDIT_63;
6058                 else
6059                         credits = PFI_CREDIT(15);
6060         } else {
6061                 credits = default_credits;
6062         }
6063
6064         /*
6065          * WA - write default credits before re-programming
6066          * FIXME: should we also set the resend bit here?
6067          */
6068         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6069                    default_credits);
6070
6071         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6072                    credits | PFI_CREDIT_RESEND);
6073
6074         /*
6075          * FIXME is this guaranteed to clear
6076          * immediately or should we poll for it?
6077          */
6078         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6079 }
6080
6081 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6082 {
6083         struct drm_device *dev = old_state->dev;
6084         struct drm_i915_private *dev_priv = to_i915(dev);
6085         struct intel_atomic_state *old_intel_state =
6086                 to_intel_atomic_state(old_state);
6087         unsigned req_cdclk = old_intel_state->dev_cdclk;
6088
6089         /*
6090          * FIXME: We can end up here with all power domains off, yet
6091          * with a CDCLK frequency other than the minimum. To account
6092          * for this take the PIPE-A power domain, which covers the HW
6093          * blocks needed for the following programming. This can be
6094          * removed once it's guaranteed that we get here either with
6095          * the minimum CDCLK set, or the required power domains
6096          * enabled.
6097          */
6098         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6099
6100         if (IS_CHERRYVIEW(dev))
6101                 cherryview_set_cdclk(dev, req_cdclk);
6102         else
6103                 valleyview_set_cdclk(dev, req_cdclk);
6104
6105         vlv_program_pfi_credits(dev_priv);
6106
6107         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6108 }
6109
6110 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6111 {
6112         struct drm_device *dev = crtc->dev;
6113         struct drm_i915_private *dev_priv = to_i915(dev);
6114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6115         struct intel_encoder *encoder;
6116         struct intel_crtc_state *pipe_config =
6117                 to_intel_crtc_state(crtc->state);
6118         int pipe = intel_crtc->pipe;
6119
6120         if (WARN_ON(intel_crtc->active))
6121                 return;
6122
6123         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6124                 intel_dp_set_m_n(intel_crtc, M1_N1);
6125
6126         intel_set_pipe_timings(intel_crtc);
6127         intel_set_pipe_src_size(intel_crtc);
6128
6129         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6130                 struct drm_i915_private *dev_priv = to_i915(dev);
6131
6132                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6133                 I915_WRITE(CHV_CANVAS(pipe), 0);
6134         }
6135
6136         i9xx_set_pipeconf(intel_crtc);
6137
6138         intel_crtc->active = true;
6139
6140         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6141
6142         for_each_encoder_on_crtc(dev, crtc, encoder)
6143                 if (encoder->pre_pll_enable)
6144                         encoder->pre_pll_enable(encoder);
6145
6146         if (IS_CHERRYVIEW(dev)) {
6147                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6148                 chv_enable_pll(intel_crtc, intel_crtc->config);
6149         } else {
6150                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6151                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6152         }
6153
6154         for_each_encoder_on_crtc(dev, crtc, encoder)
6155                 if (encoder->pre_enable)
6156                         encoder->pre_enable(encoder);
6157
6158         i9xx_pfit_enable(intel_crtc);
6159
6160         intel_color_load_luts(&pipe_config->base);
6161
6162         intel_update_watermarks(crtc);
6163         intel_enable_pipe(intel_crtc);
6164
6165         assert_vblank_disabled(crtc);
6166         drm_crtc_vblank_on(crtc);
6167
6168         for_each_encoder_on_crtc(dev, crtc, encoder)
6169                 encoder->enable(encoder);
6170 }
6171
6172 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6173 {
6174         struct drm_device *dev = crtc->base.dev;
6175         struct drm_i915_private *dev_priv = to_i915(dev);
6176
6177         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6178         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6179 }
6180
6181 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6182 {
6183         struct drm_device *dev = crtc->dev;
6184         struct drm_i915_private *dev_priv = to_i915(dev);
6185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6186         struct intel_encoder *encoder;
6187         struct intel_crtc_state *pipe_config =
6188                 to_intel_crtc_state(crtc->state);
6189         enum pipe pipe = intel_crtc->pipe;
6190
6191         if (WARN_ON(intel_crtc->active))
6192                 return;
6193
6194         i9xx_set_pll_dividers(intel_crtc);
6195
6196         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6197                 intel_dp_set_m_n(intel_crtc, M1_N1);
6198
6199         intel_set_pipe_timings(intel_crtc);
6200         intel_set_pipe_src_size(intel_crtc);
6201
6202         i9xx_set_pipeconf(intel_crtc);
6203
6204         intel_crtc->active = true;
6205
6206         if (!IS_GEN2(dev))
6207                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6208
6209         for_each_encoder_on_crtc(dev, crtc, encoder)
6210                 if (encoder->pre_enable)
6211                         encoder->pre_enable(encoder);
6212
6213         i9xx_enable_pll(intel_crtc);
6214
6215         i9xx_pfit_enable(intel_crtc);
6216
6217         intel_color_load_luts(&pipe_config->base);
6218
6219         intel_update_watermarks(crtc);
6220         intel_enable_pipe(intel_crtc);
6221
6222         assert_vblank_disabled(crtc);
6223         drm_crtc_vblank_on(crtc);
6224
6225         for_each_encoder_on_crtc(dev, crtc, encoder)
6226                 encoder->enable(encoder);
6227 }
6228
6229 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6230 {
6231         struct drm_device *dev = crtc->base.dev;
6232         struct drm_i915_private *dev_priv = to_i915(dev);
6233
6234         if (!crtc->config->gmch_pfit.control)
6235                 return;
6236
6237         assert_pipe_disabled(dev_priv, crtc->pipe);
6238
6239         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6240                          I915_READ(PFIT_CONTROL));
6241         I915_WRITE(PFIT_CONTROL, 0);
6242 }
6243
6244 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6245 {
6246         struct drm_device *dev = crtc->dev;
6247         struct drm_i915_private *dev_priv = to_i915(dev);
6248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249         struct intel_encoder *encoder;
6250         int pipe = intel_crtc->pipe;
6251
6252         /*
6253          * On gen2 planes are double buffered but the pipe isn't, so we must
6254          * wait for planes to fully turn off before disabling the pipe.
6255          */
6256         if (IS_GEN2(dev))
6257                 intel_wait_for_vblank(dev, pipe);
6258
6259         for_each_encoder_on_crtc(dev, crtc, encoder)
6260                 encoder->disable(encoder);
6261
6262         drm_crtc_vblank_off(crtc);
6263         assert_vblank_disabled(crtc);
6264
6265         intel_disable_pipe(intel_crtc);
6266
6267         i9xx_pfit_disable(intel_crtc);
6268
6269         for_each_encoder_on_crtc(dev, crtc, encoder)
6270                 if (encoder->post_disable)
6271                         encoder->post_disable(encoder);
6272
6273         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6274                 if (IS_CHERRYVIEW(dev))
6275                         chv_disable_pll(dev_priv, pipe);
6276                 else if (IS_VALLEYVIEW(dev))
6277                         vlv_disable_pll(dev_priv, pipe);
6278                 else
6279                         i9xx_disable_pll(intel_crtc);
6280         }
6281
6282         for_each_encoder_on_crtc(dev, crtc, encoder)
6283                 if (encoder->post_pll_disable)
6284                         encoder->post_pll_disable(encoder);
6285
6286         if (!IS_GEN2(dev))
6287                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6288 }
6289
6290 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6291 {
6292         struct intel_encoder *encoder;
6293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6294         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6295         enum intel_display_power_domain domain;
6296         unsigned long domains;
6297
6298         if (!intel_crtc->active)
6299                 return;
6300
6301         if (to_intel_plane_state(crtc->primary->state)->visible) {
6302                 WARN_ON(intel_crtc->flip_work);
6303
6304                 intel_pre_disable_primary_noatomic(crtc);
6305
6306                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6307                 to_intel_plane_state(crtc->primary->state)->visible = false;
6308         }
6309
6310         dev_priv->display.crtc_disable(crtc);
6311
6312         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6313                       crtc->base.id, crtc->name);
6314
6315         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6316         crtc->state->active = false;
6317         intel_crtc->active = false;
6318         crtc->enabled = false;
6319         crtc->state->connector_mask = 0;
6320         crtc->state->encoder_mask = 0;
6321
6322         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6323                 encoder->base.crtc = NULL;
6324
6325         intel_fbc_disable(intel_crtc);
6326         intel_update_watermarks(crtc);
6327         intel_disable_shared_dpll(intel_crtc);
6328
6329         domains = intel_crtc->enabled_power_domains;
6330         for_each_power_domain(domain, domains)
6331                 intel_display_power_put(dev_priv, domain);
6332         intel_crtc->enabled_power_domains = 0;
6333
6334         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6335         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6336 }
6337
6338 /*
6339  * turn all crtc's off, but do not adjust state
6340  * This has to be paired with a call to intel_modeset_setup_hw_state.
6341  */
6342 int intel_display_suspend(struct drm_device *dev)
6343 {
6344         struct drm_i915_private *dev_priv = to_i915(dev);
6345         struct drm_atomic_state *state;
6346         int ret;
6347
6348         state = drm_atomic_helper_suspend(dev);
6349         ret = PTR_ERR_OR_ZERO(state);
6350         if (ret)
6351                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6352         else
6353                 dev_priv->modeset_restore_state = state;
6354         return ret;
6355 }
6356
6357 void intel_encoder_destroy(struct drm_encoder *encoder)
6358 {
6359         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6360
6361         drm_encoder_cleanup(encoder);
6362         kfree(intel_encoder);
6363 }
6364
6365 /* Cross check the actual hw state with our own modeset state tracking (and it's
6366  * internal consistency). */
6367 static void intel_connector_verify_state(struct intel_connector *connector)
6368 {
6369         struct drm_crtc *crtc = connector->base.state->crtc;
6370
6371         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372                       connector->base.base.id,
6373                       connector->base.name);
6374
6375         if (connector->get_hw_state(connector)) {
6376                 struct intel_encoder *encoder = connector->encoder;
6377                 struct drm_connector_state *conn_state = connector->base.state;
6378
6379                 I915_STATE_WARN(!crtc,
6380                          "connector enabled without attached crtc\n");
6381
6382                 if (!crtc)
6383                         return;
6384
6385                 I915_STATE_WARN(!crtc->state->active,
6386                       "connector is active, but attached crtc isn't\n");
6387
6388                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6389                         return;
6390
6391                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6392                         "atomic encoder doesn't match attached encoder\n");
6393
6394                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6395                         "attached encoder crtc differs from connector crtc\n");
6396         } else {
6397                 I915_STATE_WARN(crtc && crtc->state->active,
6398                         "attached crtc is active, but connector isn't\n");
6399                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6400                         "best encoder set without crtc!\n");
6401         }
6402 }
6403
6404 int intel_connector_init(struct intel_connector *connector)
6405 {
6406         drm_atomic_helper_connector_reset(&connector->base);
6407
6408         if (!connector->base.state)
6409                 return -ENOMEM;
6410
6411         return 0;
6412 }
6413
6414 struct intel_connector *intel_connector_alloc(void)
6415 {
6416         struct intel_connector *connector;
6417
6418         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6419         if (!connector)
6420                 return NULL;
6421
6422         if (intel_connector_init(connector) < 0) {
6423                 kfree(connector);
6424                 return NULL;
6425         }
6426
6427         return connector;
6428 }
6429
6430 /* Simple connector->get_hw_state implementation for encoders that support only
6431  * one connector and no cloning and hence the encoder state determines the state
6432  * of the connector. */
6433 bool intel_connector_get_hw_state(struct intel_connector *connector)
6434 {
6435         enum pipe pipe = 0;
6436         struct intel_encoder *encoder = connector->encoder;
6437
6438         return encoder->get_hw_state(encoder, &pipe);
6439 }
6440
6441 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6442 {
6443         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6444                 return crtc_state->fdi_lanes;
6445
6446         return 0;
6447 }
6448
6449 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6450                                      struct intel_crtc_state *pipe_config)
6451 {
6452         struct drm_atomic_state *state = pipe_config->base.state;
6453         struct intel_crtc *other_crtc;
6454         struct intel_crtc_state *other_crtc_state;
6455
6456         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6457                       pipe_name(pipe), pipe_config->fdi_lanes);
6458         if (pipe_config->fdi_lanes > 4) {
6459                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6460                               pipe_name(pipe), pipe_config->fdi_lanes);
6461                 return -EINVAL;
6462         }
6463
6464         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6465                 if (pipe_config->fdi_lanes > 2) {
6466                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6467                                       pipe_config->fdi_lanes);
6468                         return -EINVAL;
6469                 } else {
6470                         return 0;
6471                 }
6472         }
6473
6474         if (INTEL_INFO(dev)->num_pipes == 2)
6475                 return 0;
6476
6477         /* Ivybridge 3 pipe is really complicated */
6478         switch (pipe) {
6479         case PIPE_A:
6480                 return 0;
6481         case PIPE_B:
6482                 if (pipe_config->fdi_lanes <= 2)
6483                         return 0;
6484
6485                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6486                 other_crtc_state =
6487                         intel_atomic_get_crtc_state(state, other_crtc);
6488                 if (IS_ERR(other_crtc_state))
6489                         return PTR_ERR(other_crtc_state);
6490
6491                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6492                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6493                                       pipe_name(pipe), pipe_config->fdi_lanes);
6494                         return -EINVAL;
6495                 }
6496                 return 0;
6497         case PIPE_C:
6498                 if (pipe_config->fdi_lanes > 2) {
6499                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6500                                       pipe_name(pipe), pipe_config->fdi_lanes);
6501                         return -EINVAL;
6502                 }
6503
6504                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6505                 other_crtc_state =
6506                         intel_atomic_get_crtc_state(state, other_crtc);
6507                 if (IS_ERR(other_crtc_state))
6508                         return PTR_ERR(other_crtc_state);
6509
6510                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6511                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6512                         return -EINVAL;
6513                 }
6514                 return 0;
6515         default:
6516                 BUG();
6517         }
6518 }
6519
6520 #define RETRY 1
6521 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6522                                        struct intel_crtc_state *pipe_config)
6523 {
6524         struct drm_device *dev = intel_crtc->base.dev;
6525         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6526         int lane, link_bw, fdi_dotclock, ret;
6527         bool needs_recompute = false;
6528
6529 retry:
6530         /* FDI is a binary signal running at ~2.7GHz, encoding
6531          * each output octet as 10 bits. The actual frequency
6532          * is stored as a divider into a 100MHz clock, and the
6533          * mode pixel clock is stored in units of 1KHz.
6534          * Hence the bw of each lane in terms of the mode signal
6535          * is:
6536          */
6537         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6538
6539         fdi_dotclock = adjusted_mode->crtc_clock;
6540
6541         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6542                                            pipe_config->pipe_bpp);
6543
6544         pipe_config->fdi_lanes = lane;
6545
6546         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6547                                link_bw, &pipe_config->fdi_m_n);
6548
6549         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6550         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6551                 pipe_config->pipe_bpp -= 2*3;
6552                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6553                               pipe_config->pipe_bpp);
6554                 needs_recompute = true;
6555                 pipe_config->bw_constrained = true;
6556
6557                 goto retry;
6558         }
6559
6560         if (needs_recompute)
6561                 return RETRY;
6562
6563         return ret;
6564 }
6565
6566 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6567                                      struct intel_crtc_state *pipe_config)
6568 {
6569         if (pipe_config->pipe_bpp > 24)
6570                 return false;
6571
6572         /* HSW can handle pixel rate up to cdclk? */
6573         if (IS_HASWELL(dev_priv))
6574                 return true;
6575
6576         /*
6577          * We compare against max which means we must take
6578          * the increased cdclk requirement into account when
6579          * calculating the new cdclk.
6580          *
6581          * Should measure whether using a lower cdclk w/o IPS
6582          */
6583         return ilk_pipe_pixel_rate(pipe_config) <=
6584                 dev_priv->max_cdclk_freq * 95 / 100;
6585 }
6586
6587 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6588                                    struct intel_crtc_state *pipe_config)
6589 {
6590         struct drm_device *dev = crtc->base.dev;
6591         struct drm_i915_private *dev_priv = to_i915(dev);
6592
6593         pipe_config->ips_enabled = i915.enable_ips &&
6594                 hsw_crtc_supports_ips(crtc) &&
6595                 pipe_config_supports_ips(dev_priv, pipe_config);
6596 }
6597
6598 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6599 {
6600         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6601
6602         /* GDG double wide on either pipe, otherwise pipe A only */
6603         return INTEL_INFO(dev_priv)->gen < 4 &&
6604                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6605 }
6606
6607 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6608                                      struct intel_crtc_state *pipe_config)
6609 {
6610         struct drm_device *dev = crtc->base.dev;
6611         struct drm_i915_private *dev_priv = to_i915(dev);
6612         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6613         int clock_limit = dev_priv->max_dotclk_freq;
6614
6615         if (INTEL_INFO(dev)->gen < 4) {
6616                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6617
6618                 /*
6619                  * Enable double wide mode when the dot clock
6620                  * is > 90% of the (display) core speed.
6621                  */
6622                 if (intel_crtc_supports_double_wide(crtc) &&
6623                     adjusted_mode->crtc_clock > clock_limit) {
6624                         clock_limit = dev_priv->max_dotclk_freq;
6625                         pipe_config->double_wide = true;
6626                 }
6627         }
6628
6629         if (adjusted_mode->crtc_clock > clock_limit) {
6630                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6631                               adjusted_mode->crtc_clock, clock_limit,
6632                               yesno(pipe_config->double_wide));
6633                 return -EINVAL;
6634         }
6635
6636         /*
6637          * Pipe horizontal size must be even in:
6638          * - DVO ganged mode
6639          * - LVDS dual channel mode
6640          * - Double wide pipe
6641          */
6642         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6643              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6644                 pipe_config->pipe_src_w &= ~1;
6645
6646         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6647          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6648          */
6649         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6650                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6651                 return -EINVAL;
6652
6653         if (HAS_IPS(dev))
6654                 hsw_compute_ips_config(crtc, pipe_config);
6655
6656         if (pipe_config->has_pch_encoder)
6657                 return ironlake_fdi_compute_config(crtc, pipe_config);
6658
6659         return 0;
6660 }
6661
6662 static int skylake_get_display_clock_speed(struct drm_device *dev)
6663 {
6664         struct drm_i915_private *dev_priv = to_i915(dev);
6665         uint32_t cdctl;
6666
6667         skl_dpll0_update(dev_priv);
6668
6669         if (dev_priv->cdclk_pll.vco == 0)
6670                 return dev_priv->cdclk_pll.ref;
6671
6672         cdctl = I915_READ(CDCLK_CTL);
6673
6674         if (dev_priv->cdclk_pll.vco == 8640000) {
6675                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6676                 case CDCLK_FREQ_450_432:
6677                         return 432000;
6678                 case CDCLK_FREQ_337_308:
6679                         return 308571;
6680                 case CDCLK_FREQ_540:
6681                         return 540000;
6682                 case CDCLK_FREQ_675_617:
6683                         return 617143;
6684                 default:
6685                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6686                 }
6687         } else {
6688                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6689                 case CDCLK_FREQ_450_432:
6690                         return 450000;
6691                 case CDCLK_FREQ_337_308:
6692                         return 337500;
6693                 case CDCLK_FREQ_540:
6694                         return 540000;
6695                 case CDCLK_FREQ_675_617:
6696                         return 675000;
6697                 default:
6698                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6699                 }
6700         }
6701
6702         return dev_priv->cdclk_pll.ref;
6703 }
6704
6705 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6706 {
6707         u32 val;
6708
6709         dev_priv->cdclk_pll.ref = 19200;
6710         dev_priv->cdclk_pll.vco = 0;
6711
6712         val = I915_READ(BXT_DE_PLL_ENABLE);
6713         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6714                 return;
6715
6716         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6717                 return;
6718
6719         val = I915_READ(BXT_DE_PLL_CTL);
6720         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6721                 dev_priv->cdclk_pll.ref;
6722 }
6723
6724 static int broxton_get_display_clock_speed(struct drm_device *dev)
6725 {
6726         struct drm_i915_private *dev_priv = to_i915(dev);
6727         u32 divider;
6728         int div, vco;
6729
6730         bxt_de_pll_update(dev_priv);
6731
6732         vco = dev_priv->cdclk_pll.vco;
6733         if (vco == 0)
6734                 return dev_priv->cdclk_pll.ref;
6735
6736         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6737
6738         switch (divider) {
6739         case BXT_CDCLK_CD2X_DIV_SEL_1:
6740                 div = 2;
6741                 break;
6742         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6743                 div = 3;
6744                 break;
6745         case BXT_CDCLK_CD2X_DIV_SEL_2:
6746                 div = 4;
6747                 break;
6748         case BXT_CDCLK_CD2X_DIV_SEL_4:
6749                 div = 8;
6750                 break;
6751         default:
6752                 MISSING_CASE(divider);
6753                 return dev_priv->cdclk_pll.ref;
6754         }
6755
6756         return DIV_ROUND_CLOSEST(vco, div);
6757 }
6758
6759 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6760 {
6761         struct drm_i915_private *dev_priv = to_i915(dev);
6762         uint32_t lcpll = I915_READ(LCPLL_CTL);
6763         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6764
6765         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6766                 return 800000;
6767         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6768                 return 450000;
6769         else if (freq == LCPLL_CLK_FREQ_450)
6770                 return 450000;
6771         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6772                 return 540000;
6773         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6774                 return 337500;
6775         else
6776                 return 675000;
6777 }
6778
6779 static int haswell_get_display_clock_speed(struct drm_device *dev)
6780 {
6781         struct drm_i915_private *dev_priv = to_i915(dev);
6782         uint32_t lcpll = I915_READ(LCPLL_CTL);
6783         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6784
6785         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6786                 return 800000;
6787         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6788                 return 450000;
6789         else if (freq == LCPLL_CLK_FREQ_450)
6790                 return 450000;
6791         else if (IS_HSW_ULT(dev))
6792                 return 337500;
6793         else
6794                 return 540000;
6795 }
6796
6797 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6798 {
6799         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6800                                       CCK_DISPLAY_CLOCK_CONTROL);
6801 }
6802
6803 static int ilk_get_display_clock_speed(struct drm_device *dev)
6804 {
6805         return 450000;
6806 }
6807
6808 static int i945_get_display_clock_speed(struct drm_device *dev)
6809 {
6810         return 400000;
6811 }
6812
6813 static int i915_get_display_clock_speed(struct drm_device *dev)
6814 {
6815         return 333333;
6816 }
6817
6818 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6819 {
6820         return 200000;
6821 }
6822
6823 static int pnv_get_display_clock_speed(struct drm_device *dev)
6824 {
6825         u16 gcfgc = 0;
6826
6827         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6828
6829         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6830         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6831                 return 266667;
6832         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6833                 return 333333;
6834         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6835                 return 444444;
6836         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6837                 return 200000;
6838         default:
6839                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6840         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6841                 return 133333;
6842         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6843                 return 166667;
6844         }
6845 }
6846
6847 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         u16 gcfgc = 0;
6850
6851         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6852
6853         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6854                 return 133333;
6855         else {
6856                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6857                 case GC_DISPLAY_CLOCK_333_MHZ:
6858                         return 333333;
6859                 default:
6860                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6861                         return 190000;
6862                 }
6863         }
6864 }
6865
6866 static int i865_get_display_clock_speed(struct drm_device *dev)
6867 {
6868         return 266667;
6869 }
6870
6871 static int i85x_get_display_clock_speed(struct drm_device *dev)
6872 {
6873         u16 hpllcc = 0;
6874
6875         /*
6876          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6877          * encoding is different :(
6878          * FIXME is this the right way to detect 852GM/852GMV?
6879          */
6880         if (dev->pdev->revision == 0x1)
6881                 return 133333;
6882
6883         pci_bus_read_config_word(dev->pdev->bus,
6884                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6885
6886         /* Assume that the hardware is in the high speed state.  This
6887          * should be the default.
6888          */
6889         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6890         case GC_CLOCK_133_200:
6891         case GC_CLOCK_133_200_2:
6892         case GC_CLOCK_100_200:
6893                 return 200000;
6894         case GC_CLOCK_166_250:
6895                 return 250000;
6896         case GC_CLOCK_100_133:
6897                 return 133333;
6898         case GC_CLOCK_133_266:
6899         case GC_CLOCK_133_266_2:
6900         case GC_CLOCK_166_266:
6901                 return 266667;
6902         }
6903
6904         /* Shouldn't happen */
6905         return 0;
6906 }
6907
6908 static int i830_get_display_clock_speed(struct drm_device *dev)
6909 {
6910         return 133333;
6911 }
6912
6913 static unsigned int intel_hpll_vco(struct drm_device *dev)
6914 {
6915         struct drm_i915_private *dev_priv = to_i915(dev);
6916         static const unsigned int blb_vco[8] = {
6917                 [0] = 3200000,
6918                 [1] = 4000000,
6919                 [2] = 5333333,
6920                 [3] = 4800000,
6921                 [4] = 6400000,
6922         };
6923         static const unsigned int pnv_vco[8] = {
6924                 [0] = 3200000,
6925                 [1] = 4000000,
6926                 [2] = 5333333,
6927                 [3] = 4800000,
6928                 [4] = 2666667,
6929         };
6930         static const unsigned int cl_vco[8] = {
6931                 [0] = 3200000,
6932                 [1] = 4000000,
6933                 [2] = 5333333,
6934                 [3] = 6400000,
6935                 [4] = 3333333,
6936                 [5] = 3566667,
6937                 [6] = 4266667,
6938         };
6939         static const unsigned int elk_vco[8] = {
6940                 [0] = 3200000,
6941                 [1] = 4000000,
6942                 [2] = 5333333,
6943                 [3] = 4800000,
6944         };
6945         static const unsigned int ctg_vco[8] = {
6946                 [0] = 3200000,
6947                 [1] = 4000000,
6948                 [2] = 5333333,
6949                 [3] = 6400000,
6950                 [4] = 2666667,
6951                 [5] = 4266667,
6952         };
6953         const unsigned int *vco_table;
6954         unsigned int vco;
6955         uint8_t tmp = 0;
6956
6957         /* FIXME other chipsets? */
6958         if (IS_GM45(dev))
6959                 vco_table = ctg_vco;
6960         else if (IS_G4X(dev))
6961                 vco_table = elk_vco;
6962         else if (IS_CRESTLINE(dev))
6963                 vco_table = cl_vco;
6964         else if (IS_PINEVIEW(dev))
6965                 vco_table = pnv_vco;
6966         else if (IS_G33(dev))
6967                 vco_table = blb_vco;
6968         else
6969                 return 0;
6970
6971         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6972
6973         vco = vco_table[tmp & 0x7];
6974         if (vco == 0)
6975                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6976         else
6977                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6978
6979         return vco;
6980 }
6981
6982 static int gm45_get_display_clock_speed(struct drm_device *dev)
6983 {
6984         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6985         uint16_t tmp = 0;
6986
6987         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6988
6989         cdclk_sel = (tmp >> 12) & 0x1;
6990
6991         switch (vco) {
6992         case 2666667:
6993         case 4000000:
6994         case 5333333:
6995                 return cdclk_sel ? 333333 : 222222;
6996         case 3200000:
6997                 return cdclk_sel ? 320000 : 228571;
6998         default:
6999                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7000                 return 222222;
7001         }
7002 }
7003
7004 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7005 {
7006         static const uint8_t div_3200[] = { 16, 10,  8 };
7007         static const uint8_t div_4000[] = { 20, 12, 10 };
7008         static const uint8_t div_5333[] = { 24, 16, 14 };
7009         const uint8_t *div_table;
7010         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7011         uint16_t tmp = 0;
7012
7013         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7014
7015         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7016
7017         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7018                 goto fail;
7019
7020         switch (vco) {
7021         case 3200000:
7022                 div_table = div_3200;
7023                 break;
7024         case 4000000:
7025                 div_table = div_4000;
7026                 break;
7027         case 5333333:
7028                 div_table = div_5333;
7029                 break;
7030         default:
7031                 goto fail;
7032         }
7033
7034         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7035
7036 fail:
7037         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7038         return 200000;
7039 }
7040
7041 static int g33_get_display_clock_speed(struct drm_device *dev)
7042 {
7043         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7044         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7045         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7046         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7047         const uint8_t *div_table;
7048         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7049         uint16_t tmp = 0;
7050
7051         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7052
7053         cdclk_sel = (tmp >> 4) & 0x7;
7054
7055         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7056                 goto fail;
7057
7058         switch (vco) {
7059         case 3200000:
7060                 div_table = div_3200;
7061                 break;
7062         case 4000000:
7063                 div_table = div_4000;
7064                 break;
7065         case 4800000:
7066                 div_table = div_4800;
7067                 break;
7068         case 5333333:
7069                 div_table = div_5333;
7070                 break;
7071         default:
7072                 goto fail;
7073         }
7074
7075         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7076
7077 fail:
7078         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7079         return 190476;
7080 }
7081
7082 static void
7083 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7084 {
7085         while (*num > DATA_LINK_M_N_MASK ||
7086                *den > DATA_LINK_M_N_MASK) {
7087                 *num >>= 1;
7088                 *den >>= 1;
7089         }
7090 }
7091
7092 static void compute_m_n(unsigned int m, unsigned int n,
7093                         uint32_t *ret_m, uint32_t *ret_n)
7094 {
7095         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7096         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7097         intel_reduce_m_n_ratio(ret_m, ret_n);
7098 }
7099
7100 void
7101 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7102                        int pixel_clock, int link_clock,
7103                        struct intel_link_m_n *m_n)
7104 {
7105         m_n->tu = 64;
7106
7107         compute_m_n(bits_per_pixel * pixel_clock,
7108                     link_clock * nlanes * 8,
7109                     &m_n->gmch_m, &m_n->gmch_n);
7110
7111         compute_m_n(pixel_clock, link_clock,
7112                     &m_n->link_m, &m_n->link_n);
7113 }
7114
7115 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7116 {
7117         if (i915.panel_use_ssc >= 0)
7118                 return i915.panel_use_ssc != 0;
7119         return dev_priv->vbt.lvds_use_ssc
7120                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7121 }
7122
7123 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7124 {
7125         return (1 << dpll->n) << 16 | dpll->m2;
7126 }
7127
7128 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7129 {
7130         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7131 }
7132
7133 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7134                                      struct intel_crtc_state *crtc_state,
7135                                      struct dpll *reduced_clock)
7136 {
7137         struct drm_device *dev = crtc->base.dev;
7138         u32 fp, fp2 = 0;
7139
7140         if (IS_PINEVIEW(dev)) {
7141                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7142                 if (reduced_clock)
7143                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7144         } else {
7145                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7146                 if (reduced_clock)
7147                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7148         }
7149
7150         crtc_state->dpll_hw_state.fp0 = fp;
7151
7152         crtc->lowfreq_avail = false;
7153         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7154             reduced_clock) {
7155                 crtc_state->dpll_hw_state.fp1 = fp2;
7156                 crtc->lowfreq_avail = true;
7157         } else {
7158                 crtc_state->dpll_hw_state.fp1 = fp;
7159         }
7160 }
7161
7162 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7163                 pipe)
7164 {
7165         u32 reg_val;
7166
7167         /*
7168          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7169          * and set it to a reasonable value instead.
7170          */
7171         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7172         reg_val &= 0xffffff00;
7173         reg_val |= 0x00000030;
7174         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7175
7176         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7177         reg_val &= 0x8cffffff;
7178         reg_val = 0x8c000000;
7179         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7180
7181         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7182         reg_val &= 0xffffff00;
7183         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7184
7185         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7186         reg_val &= 0x00ffffff;
7187         reg_val |= 0xb0000000;
7188         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7189 }
7190
7191 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7192                                          struct intel_link_m_n *m_n)
7193 {
7194         struct drm_device *dev = crtc->base.dev;
7195         struct drm_i915_private *dev_priv = to_i915(dev);
7196         int pipe = crtc->pipe;
7197
7198         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7199         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7200         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7201         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7202 }
7203
7204 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7205                                          struct intel_link_m_n *m_n,
7206                                          struct intel_link_m_n *m2_n2)
7207 {
7208         struct drm_device *dev = crtc->base.dev;
7209         struct drm_i915_private *dev_priv = to_i915(dev);
7210         int pipe = crtc->pipe;
7211         enum transcoder transcoder = crtc->config->cpu_transcoder;
7212
7213         if (INTEL_INFO(dev)->gen >= 5) {
7214                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7215                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7216                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7217                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7218                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7219                  * for gen < 8) and if DRRS is supported (to make sure the
7220                  * registers are not unnecessarily accessed).
7221                  */
7222                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7223                         crtc->config->has_drrs) {
7224                         I915_WRITE(PIPE_DATA_M2(transcoder),
7225                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7226                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7227                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7228                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7229                 }
7230         } else {
7231                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7232                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7233                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7234                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7235         }
7236 }
7237
7238 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7239 {
7240         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7241
7242         if (m_n == M1_N1) {
7243                 dp_m_n = &crtc->config->dp_m_n;
7244                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7245         } else if (m_n == M2_N2) {
7246
7247                 /*
7248                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7249                  * needs to be programmed into M1_N1.
7250                  */
7251                 dp_m_n = &crtc->config->dp_m2_n2;
7252         } else {
7253                 DRM_ERROR("Unsupported divider value\n");
7254                 return;
7255         }
7256
7257         if (crtc->config->has_pch_encoder)
7258                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7259         else
7260                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7261 }
7262
7263 static void vlv_compute_dpll(struct intel_crtc *crtc,
7264                              struct intel_crtc_state *pipe_config)
7265 {
7266         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7267                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7268         if (crtc->pipe != PIPE_A)
7269                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7270
7271         /* DPLL not used with DSI, but still need the rest set up */
7272         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7273                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7274                         DPLL_EXT_BUFFER_ENABLE_VLV;
7275
7276         pipe_config->dpll_hw_state.dpll_md =
7277                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7278 }
7279
7280 static void chv_compute_dpll(struct intel_crtc *crtc,
7281                              struct intel_crtc_state *pipe_config)
7282 {
7283         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7284                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7285         if (crtc->pipe != PIPE_A)
7286                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7287
7288         /* DPLL not used with DSI, but still need the rest set up */
7289         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7290                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7291
7292         pipe_config->dpll_hw_state.dpll_md =
7293                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7294 }
7295
7296 static void vlv_prepare_pll(struct intel_crtc *crtc,
7297                             const struct intel_crtc_state *pipe_config)
7298 {
7299         struct drm_device *dev = crtc->base.dev;
7300         struct drm_i915_private *dev_priv = to_i915(dev);
7301         enum pipe pipe = crtc->pipe;
7302         u32 mdiv;
7303         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7304         u32 coreclk, reg_val;
7305
7306         /* Enable Refclk */
7307         I915_WRITE(DPLL(pipe),
7308                    pipe_config->dpll_hw_state.dpll &
7309                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7310
7311         /* No need to actually set up the DPLL with DSI */
7312         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7313                 return;
7314
7315         mutex_lock(&dev_priv->sb_lock);
7316
7317         bestn = pipe_config->dpll.n;
7318         bestm1 = pipe_config->dpll.m1;
7319         bestm2 = pipe_config->dpll.m2;
7320         bestp1 = pipe_config->dpll.p1;
7321         bestp2 = pipe_config->dpll.p2;
7322
7323         /* See eDP HDMI DPIO driver vbios notes doc */
7324
7325         /* PLL B needs special handling */
7326         if (pipe == PIPE_B)
7327                 vlv_pllb_recal_opamp(dev_priv, pipe);
7328
7329         /* Set up Tx target for periodic Rcomp update */
7330         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7331
7332         /* Disable target IRef on PLL */
7333         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7334         reg_val &= 0x00ffffff;
7335         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7336
7337         /* Disable fast lock */
7338         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7339
7340         /* Set idtafcrecal before PLL is enabled */
7341         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7342         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7343         mdiv |= ((bestn << DPIO_N_SHIFT));
7344         mdiv |= (1 << DPIO_K_SHIFT);
7345
7346         /*
7347          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7348          * but we don't support that).
7349          * Note: don't use the DAC post divider as it seems unstable.
7350          */
7351         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7352         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7353
7354         mdiv |= DPIO_ENABLE_CALIBRATION;
7355         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7356
7357         /* Set HBR and RBR LPF coefficients */
7358         if (pipe_config->port_clock == 162000 ||
7359             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7360             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7361                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7362                                  0x009f0003);
7363         else
7364                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7365                                  0x00d0000f);
7366
7367         if (intel_crtc_has_dp_encoder(pipe_config)) {
7368                 /* Use SSC source */
7369                 if (pipe == PIPE_A)
7370                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7371                                          0x0df40000);
7372                 else
7373                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7374                                          0x0df70000);
7375         } else { /* HDMI or VGA */
7376                 /* Use bend source */
7377                 if (pipe == PIPE_A)
7378                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7379                                          0x0df70000);
7380                 else
7381                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7382                                          0x0df40000);
7383         }
7384
7385         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7386         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7387         if (intel_crtc_has_dp_encoder(crtc->config))
7388                 coreclk |= 0x01000000;
7389         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7390
7391         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7392         mutex_unlock(&dev_priv->sb_lock);
7393 }
7394
7395 static void chv_prepare_pll(struct intel_crtc *crtc,
7396                             const struct intel_crtc_state *pipe_config)
7397 {
7398         struct drm_device *dev = crtc->base.dev;
7399         struct drm_i915_private *dev_priv = to_i915(dev);
7400         enum pipe pipe = crtc->pipe;
7401         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7402         u32 loopfilter, tribuf_calcntr;
7403         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7404         u32 dpio_val;
7405         int vco;
7406
7407         /* Enable Refclk and SSC */
7408         I915_WRITE(DPLL(pipe),
7409                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7410
7411         /* No need to actually set up the DPLL with DSI */
7412         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7413                 return;
7414
7415         bestn = pipe_config->dpll.n;
7416         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7417         bestm1 = pipe_config->dpll.m1;
7418         bestm2 = pipe_config->dpll.m2 >> 22;
7419         bestp1 = pipe_config->dpll.p1;
7420         bestp2 = pipe_config->dpll.p2;
7421         vco = pipe_config->dpll.vco;
7422         dpio_val = 0;
7423         loopfilter = 0;
7424
7425         mutex_lock(&dev_priv->sb_lock);
7426
7427         /* p1 and p2 divider */
7428         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7429                         5 << DPIO_CHV_S1_DIV_SHIFT |
7430                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7431                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7432                         1 << DPIO_CHV_K_DIV_SHIFT);
7433
7434         /* Feedback post-divider - m2 */
7435         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7436
7437         /* Feedback refclk divider - n and m1 */
7438         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7439                         DPIO_CHV_M1_DIV_BY_2 |
7440                         1 << DPIO_CHV_N_DIV_SHIFT);
7441
7442         /* M2 fraction division */
7443         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7444
7445         /* M2 fraction division enable */
7446         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7447         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7448         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7449         if (bestm2_frac)
7450                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7451         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7452
7453         /* Program digital lock detect threshold */
7454         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7455         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7456                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7457         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7458         if (!bestm2_frac)
7459                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7460         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7461
7462         /* Loop filter */
7463         if (vco == 5400000) {
7464                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7465                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7466                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7467                 tribuf_calcntr = 0x9;
7468         } else if (vco <= 6200000) {
7469                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7470                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7471                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7472                 tribuf_calcntr = 0x9;
7473         } else if (vco <= 6480000) {
7474                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7475                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7476                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7477                 tribuf_calcntr = 0x8;
7478         } else {
7479                 /* Not supported. Apply the same limits as in the max case */
7480                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7481                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7482                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7483                 tribuf_calcntr = 0;
7484         }
7485         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7486
7487         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7488         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7489         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7490         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7491
7492         /* AFC Recal */
7493         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7494                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7495                         DPIO_AFC_RECAL);
7496
7497         mutex_unlock(&dev_priv->sb_lock);
7498 }
7499
7500 /**
7501  * vlv_force_pll_on - forcibly enable just the PLL
7502  * @dev_priv: i915 private structure
7503  * @pipe: pipe PLL to enable
7504  * @dpll: PLL configuration
7505  *
7506  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7507  * in cases where we need the PLL enabled even when @pipe is not going to
7508  * be enabled.
7509  */
7510 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7511                      const struct dpll *dpll)
7512 {
7513         struct intel_crtc *crtc =
7514                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7515         struct intel_crtc_state *pipe_config;
7516
7517         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7518         if (!pipe_config)
7519                 return -ENOMEM;
7520
7521         pipe_config->base.crtc = &crtc->base;
7522         pipe_config->pixel_multiplier = 1;
7523         pipe_config->dpll = *dpll;
7524
7525         if (IS_CHERRYVIEW(dev)) {
7526                 chv_compute_dpll(crtc, pipe_config);
7527                 chv_prepare_pll(crtc, pipe_config);
7528                 chv_enable_pll(crtc, pipe_config);
7529         } else {
7530                 vlv_compute_dpll(crtc, pipe_config);
7531                 vlv_prepare_pll(crtc, pipe_config);
7532                 vlv_enable_pll(crtc, pipe_config);
7533         }
7534
7535         kfree(pipe_config);
7536
7537         return 0;
7538 }
7539
7540 /**
7541  * vlv_force_pll_off - forcibly disable just the PLL
7542  * @dev_priv: i915 private structure
7543  * @pipe: pipe PLL to disable
7544  *
7545  * Disable the PLL for @pipe. To be used in cases where we need
7546  * the PLL enabled even when @pipe is not going to be enabled.
7547  */
7548 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7549 {
7550         if (IS_CHERRYVIEW(dev))
7551                 chv_disable_pll(to_i915(dev), pipe);
7552         else
7553                 vlv_disable_pll(to_i915(dev), pipe);
7554 }
7555
7556 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7557                               struct intel_crtc_state *crtc_state,
7558                               struct dpll *reduced_clock)
7559 {
7560         struct drm_device *dev = crtc->base.dev;
7561         struct drm_i915_private *dev_priv = to_i915(dev);
7562         u32 dpll;
7563         struct dpll *clock = &crtc_state->dpll;
7564
7565         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7566
7567         dpll = DPLL_VGA_MODE_DIS;
7568
7569         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7570                 dpll |= DPLLB_MODE_LVDS;
7571         else
7572                 dpll |= DPLLB_MODE_DAC_SERIAL;
7573
7574         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7575                 dpll |= (crtc_state->pixel_multiplier - 1)
7576                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7577         }
7578
7579         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7580             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7581                 dpll |= DPLL_SDVO_HIGH_SPEED;
7582
7583         if (intel_crtc_has_dp_encoder(crtc_state))
7584                 dpll |= DPLL_SDVO_HIGH_SPEED;
7585
7586         /* compute bitmask from p1 value */
7587         if (IS_PINEVIEW(dev))
7588                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7589         else {
7590                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7591                 if (IS_G4X(dev) && reduced_clock)
7592                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7593         }
7594         switch (clock->p2) {
7595         case 5:
7596                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7597                 break;
7598         case 7:
7599                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7600                 break;
7601         case 10:
7602                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7603                 break;
7604         case 14:
7605                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7606                 break;
7607         }
7608         if (INTEL_INFO(dev)->gen >= 4)
7609                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7610
7611         if (crtc_state->sdvo_tv_clock)
7612                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7613         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7614                  intel_panel_use_ssc(dev_priv))
7615                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7616         else
7617                 dpll |= PLL_REF_INPUT_DREFCLK;
7618
7619         dpll |= DPLL_VCO_ENABLE;
7620         crtc_state->dpll_hw_state.dpll = dpll;
7621
7622         if (INTEL_INFO(dev)->gen >= 4) {
7623                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7624                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7625                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7626         }
7627 }
7628
7629 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7630                               struct intel_crtc_state *crtc_state,
7631                               struct dpll *reduced_clock)
7632 {
7633         struct drm_device *dev = crtc->base.dev;
7634         struct drm_i915_private *dev_priv = to_i915(dev);
7635         u32 dpll;
7636         struct dpll *clock = &crtc_state->dpll;
7637
7638         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7639
7640         dpll = DPLL_VGA_MODE_DIS;
7641
7642         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7643                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7644         } else {
7645                 if (clock->p1 == 2)
7646                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7647                 else
7648                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7649                 if (clock->p2 == 4)
7650                         dpll |= PLL_P2_DIVIDE_BY_4;
7651         }
7652
7653         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7654                 dpll |= DPLL_DVO_2X_MODE;
7655
7656         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7657             intel_panel_use_ssc(dev_priv))
7658                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7659         else
7660                 dpll |= PLL_REF_INPUT_DREFCLK;
7661
7662         dpll |= DPLL_VCO_ENABLE;
7663         crtc_state->dpll_hw_state.dpll = dpll;
7664 }
7665
7666 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7667 {
7668         struct drm_device *dev = intel_crtc->base.dev;
7669         struct drm_i915_private *dev_priv = to_i915(dev);
7670         enum pipe pipe = intel_crtc->pipe;
7671         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7672         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7673         uint32_t crtc_vtotal, crtc_vblank_end;
7674         int vsyncshift = 0;
7675
7676         /* We need to be careful not to changed the adjusted mode, for otherwise
7677          * the hw state checker will get angry at the mismatch. */
7678         crtc_vtotal = adjusted_mode->crtc_vtotal;
7679         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7680
7681         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7682                 /* the chip adds 2 halflines automatically */
7683                 crtc_vtotal -= 1;
7684                 crtc_vblank_end -= 1;
7685
7686                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7687                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7688                 else
7689                         vsyncshift = adjusted_mode->crtc_hsync_start -
7690                                 adjusted_mode->crtc_htotal / 2;
7691                 if (vsyncshift < 0)
7692                         vsyncshift += adjusted_mode->crtc_htotal;
7693         }
7694
7695         if (INTEL_INFO(dev)->gen > 3)
7696                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7697
7698         I915_WRITE(HTOTAL(cpu_transcoder),
7699                    (adjusted_mode->crtc_hdisplay - 1) |
7700                    ((adjusted_mode->crtc_htotal - 1) << 16));
7701         I915_WRITE(HBLANK(cpu_transcoder),
7702                    (adjusted_mode->crtc_hblank_start - 1) |
7703                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7704         I915_WRITE(HSYNC(cpu_transcoder),
7705                    (adjusted_mode->crtc_hsync_start - 1) |
7706                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7707
7708         I915_WRITE(VTOTAL(cpu_transcoder),
7709                    (adjusted_mode->crtc_vdisplay - 1) |
7710                    ((crtc_vtotal - 1) << 16));
7711         I915_WRITE(VBLANK(cpu_transcoder),
7712                    (adjusted_mode->crtc_vblank_start - 1) |
7713                    ((crtc_vblank_end - 1) << 16));
7714         I915_WRITE(VSYNC(cpu_transcoder),
7715                    (adjusted_mode->crtc_vsync_start - 1) |
7716                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7717
7718         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7719          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7720          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7721          * bits. */
7722         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7723             (pipe == PIPE_B || pipe == PIPE_C))
7724                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7725
7726 }
7727
7728 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7729 {
7730         struct drm_device *dev = intel_crtc->base.dev;
7731         struct drm_i915_private *dev_priv = to_i915(dev);
7732         enum pipe pipe = intel_crtc->pipe;
7733
7734         /* pipesrc controls the size that is scaled from, which should
7735          * always be the user's requested size.
7736          */
7737         I915_WRITE(PIPESRC(pipe),
7738                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7739                    (intel_crtc->config->pipe_src_h - 1));
7740 }
7741
7742 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7743                                    struct intel_crtc_state *pipe_config)
7744 {
7745         struct drm_device *dev = crtc->base.dev;
7746         struct drm_i915_private *dev_priv = to_i915(dev);
7747         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7748         uint32_t tmp;
7749
7750         tmp = I915_READ(HTOTAL(cpu_transcoder));
7751         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7752         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7753         tmp = I915_READ(HBLANK(cpu_transcoder));
7754         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7755         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7756         tmp = I915_READ(HSYNC(cpu_transcoder));
7757         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7758         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7759
7760         tmp = I915_READ(VTOTAL(cpu_transcoder));
7761         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7762         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7763         tmp = I915_READ(VBLANK(cpu_transcoder));
7764         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7765         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7766         tmp = I915_READ(VSYNC(cpu_transcoder));
7767         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7768         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7769
7770         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7771                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7772                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7773                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7774         }
7775 }
7776
7777 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7778                                     struct intel_crtc_state *pipe_config)
7779 {
7780         struct drm_device *dev = crtc->base.dev;
7781         struct drm_i915_private *dev_priv = to_i915(dev);
7782         u32 tmp;
7783
7784         tmp = I915_READ(PIPESRC(crtc->pipe));
7785         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7786         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7787
7788         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7789         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7790 }
7791
7792 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7793                                  struct intel_crtc_state *pipe_config)
7794 {
7795         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7796         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7797         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7798         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7799
7800         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7801         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7802         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7803         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7804
7805         mode->flags = pipe_config->base.adjusted_mode.flags;
7806         mode->type = DRM_MODE_TYPE_DRIVER;
7807
7808         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7809         mode->flags |= pipe_config->base.adjusted_mode.flags;
7810
7811         mode->hsync = drm_mode_hsync(mode);
7812         mode->vrefresh = drm_mode_vrefresh(mode);
7813         drm_mode_set_name(mode);
7814 }
7815
7816 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7817 {
7818         struct drm_device *dev = intel_crtc->base.dev;
7819         struct drm_i915_private *dev_priv = to_i915(dev);
7820         uint32_t pipeconf;
7821
7822         pipeconf = 0;
7823
7824         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7825             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7826                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7827
7828         if (intel_crtc->config->double_wide)
7829                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7830
7831         /* only g4x and later have fancy bpc/dither controls */
7832         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7833                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7834                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7835                         pipeconf |= PIPECONF_DITHER_EN |
7836                                     PIPECONF_DITHER_TYPE_SP;
7837
7838                 switch (intel_crtc->config->pipe_bpp) {
7839                 case 18:
7840                         pipeconf |= PIPECONF_6BPC;
7841                         break;
7842                 case 24:
7843                         pipeconf |= PIPECONF_8BPC;
7844                         break;
7845                 case 30:
7846                         pipeconf |= PIPECONF_10BPC;
7847                         break;
7848                 default:
7849                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7850                         BUG();
7851                 }
7852         }
7853
7854         if (HAS_PIPE_CXSR(dev)) {
7855                 if (intel_crtc->lowfreq_avail) {
7856                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7857                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7858                 } else {
7859                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7860                 }
7861         }
7862
7863         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7864                 if (INTEL_INFO(dev)->gen < 4 ||
7865                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7866                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7867                 else
7868                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7869         } else
7870                 pipeconf |= PIPECONF_PROGRESSIVE;
7871
7872         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7873              intel_crtc->config->limited_color_range)
7874                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7875
7876         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7877         POSTING_READ(PIPECONF(intel_crtc->pipe));
7878 }
7879
7880 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7881                                    struct intel_crtc_state *crtc_state)
7882 {
7883         struct drm_device *dev = crtc->base.dev;
7884         struct drm_i915_private *dev_priv = to_i915(dev);
7885         const struct intel_limit *limit;
7886         int refclk = 48000;
7887
7888         memset(&crtc_state->dpll_hw_state, 0,
7889                sizeof(crtc_state->dpll_hw_state));
7890
7891         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7892                 if (intel_panel_use_ssc(dev_priv)) {
7893                         refclk = dev_priv->vbt.lvds_ssc_freq;
7894                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7895                 }
7896
7897                 limit = &intel_limits_i8xx_lvds;
7898         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7899                 limit = &intel_limits_i8xx_dvo;
7900         } else {
7901                 limit = &intel_limits_i8xx_dac;
7902         }
7903
7904         if (!crtc_state->clock_set &&
7905             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7906                                  refclk, NULL, &crtc_state->dpll)) {
7907                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7908                 return -EINVAL;
7909         }
7910
7911         i8xx_compute_dpll(crtc, crtc_state, NULL);
7912
7913         return 0;
7914 }
7915
7916 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7917                                   struct intel_crtc_state *crtc_state)
7918 {
7919         struct drm_device *dev = crtc->base.dev;
7920         struct drm_i915_private *dev_priv = to_i915(dev);
7921         const struct intel_limit *limit;
7922         int refclk = 96000;
7923
7924         memset(&crtc_state->dpll_hw_state, 0,
7925                sizeof(crtc_state->dpll_hw_state));
7926
7927         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7928                 if (intel_panel_use_ssc(dev_priv)) {
7929                         refclk = dev_priv->vbt.lvds_ssc_freq;
7930                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7931                 }
7932
7933                 if (intel_is_dual_link_lvds(dev))
7934                         limit = &intel_limits_g4x_dual_channel_lvds;
7935                 else
7936                         limit = &intel_limits_g4x_single_channel_lvds;
7937         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7938                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7939                 limit = &intel_limits_g4x_hdmi;
7940         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7941                 limit = &intel_limits_g4x_sdvo;
7942         } else {
7943                 /* The option is for other outputs */
7944                 limit = &intel_limits_i9xx_sdvo;
7945         }
7946
7947         if (!crtc_state->clock_set &&
7948             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7949                                 refclk, NULL, &crtc_state->dpll)) {
7950                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7951                 return -EINVAL;
7952         }
7953
7954         i9xx_compute_dpll(crtc, crtc_state, NULL);
7955
7956         return 0;
7957 }
7958
7959 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7960                                   struct intel_crtc_state *crtc_state)
7961 {
7962         struct drm_device *dev = crtc->base.dev;
7963         struct drm_i915_private *dev_priv = to_i915(dev);
7964         const struct intel_limit *limit;
7965         int refclk = 96000;
7966
7967         memset(&crtc_state->dpll_hw_state, 0,
7968                sizeof(crtc_state->dpll_hw_state));
7969
7970         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7971                 if (intel_panel_use_ssc(dev_priv)) {
7972                         refclk = dev_priv->vbt.lvds_ssc_freq;
7973                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7974                 }
7975
7976                 limit = &intel_limits_pineview_lvds;
7977         } else {
7978                 limit = &intel_limits_pineview_sdvo;
7979         }
7980
7981         if (!crtc_state->clock_set &&
7982             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7983                                 refclk, NULL, &crtc_state->dpll)) {
7984                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7985                 return -EINVAL;
7986         }
7987
7988         i9xx_compute_dpll(crtc, crtc_state, NULL);
7989
7990         return 0;
7991 }
7992
7993 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7994                                    struct intel_crtc_state *crtc_state)
7995 {
7996         struct drm_device *dev = crtc->base.dev;
7997         struct drm_i915_private *dev_priv = to_i915(dev);
7998         const struct intel_limit *limit;
7999         int refclk = 96000;
8000
8001         memset(&crtc_state->dpll_hw_state, 0,
8002                sizeof(crtc_state->dpll_hw_state));
8003
8004         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8005                 if (intel_panel_use_ssc(dev_priv)) {
8006                         refclk = dev_priv->vbt.lvds_ssc_freq;
8007                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8008                 }
8009
8010                 limit = &intel_limits_i9xx_lvds;
8011         } else {
8012                 limit = &intel_limits_i9xx_sdvo;
8013         }
8014
8015         if (!crtc_state->clock_set &&
8016             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8017                                  refclk, NULL, &crtc_state->dpll)) {
8018                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8019                 return -EINVAL;
8020         }
8021
8022         i9xx_compute_dpll(crtc, crtc_state, NULL);
8023
8024         return 0;
8025 }
8026
8027 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8028                                   struct intel_crtc_state *crtc_state)
8029 {
8030         int refclk = 100000;
8031         const struct intel_limit *limit = &intel_limits_chv;
8032
8033         memset(&crtc_state->dpll_hw_state, 0,
8034                sizeof(crtc_state->dpll_hw_state));
8035
8036         if (!crtc_state->clock_set &&
8037             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8038                                 refclk, NULL, &crtc_state->dpll)) {
8039                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8040                 return -EINVAL;
8041         }
8042
8043         chv_compute_dpll(crtc, crtc_state);
8044
8045         return 0;
8046 }
8047
8048 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8049                                   struct intel_crtc_state *crtc_state)
8050 {
8051         int refclk = 100000;
8052         const struct intel_limit *limit = &intel_limits_vlv;
8053
8054         memset(&crtc_state->dpll_hw_state, 0,
8055                sizeof(crtc_state->dpll_hw_state));
8056
8057         if (!crtc_state->clock_set &&
8058             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8059                                 refclk, NULL, &crtc_state->dpll)) {
8060                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8061                 return -EINVAL;
8062         }
8063
8064         vlv_compute_dpll(crtc, crtc_state);
8065
8066         return 0;
8067 }
8068
8069 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8070                                  struct intel_crtc_state *pipe_config)
8071 {
8072         struct drm_device *dev = crtc->base.dev;
8073         struct drm_i915_private *dev_priv = to_i915(dev);
8074         uint32_t tmp;
8075
8076         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8077                 return;
8078
8079         tmp = I915_READ(PFIT_CONTROL);
8080         if (!(tmp & PFIT_ENABLE))
8081                 return;
8082
8083         /* Check whether the pfit is attached to our pipe. */
8084         if (INTEL_INFO(dev)->gen < 4) {
8085                 if (crtc->pipe != PIPE_B)
8086                         return;
8087         } else {
8088                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8089                         return;
8090         }
8091
8092         pipe_config->gmch_pfit.control = tmp;
8093         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8094 }
8095
8096 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8097                                struct intel_crtc_state *pipe_config)
8098 {
8099         struct drm_device *dev = crtc->base.dev;
8100         struct drm_i915_private *dev_priv = to_i915(dev);
8101         int pipe = pipe_config->cpu_transcoder;
8102         struct dpll clock;
8103         u32 mdiv;
8104         int refclk = 100000;
8105
8106         /* In case of DSI, DPLL will not be used */
8107         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8108                 return;
8109
8110         mutex_lock(&dev_priv->sb_lock);
8111         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8112         mutex_unlock(&dev_priv->sb_lock);
8113
8114         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8115         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8116         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8117         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8118         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8119
8120         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8121 }
8122
8123 static void
8124 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8125                               struct intel_initial_plane_config *plane_config)
8126 {
8127         struct drm_device *dev = crtc->base.dev;
8128         struct drm_i915_private *dev_priv = to_i915(dev);
8129         u32 val, base, offset;
8130         int pipe = crtc->pipe, plane = crtc->plane;
8131         int fourcc, pixel_format;
8132         unsigned int aligned_height;
8133         struct drm_framebuffer *fb;
8134         struct intel_framebuffer *intel_fb;
8135
8136         val = I915_READ(DSPCNTR(plane));
8137         if (!(val & DISPLAY_PLANE_ENABLE))
8138                 return;
8139
8140         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8141         if (!intel_fb) {
8142                 DRM_DEBUG_KMS("failed to alloc fb\n");
8143                 return;
8144         }
8145
8146         fb = &intel_fb->base;
8147
8148         if (INTEL_INFO(dev)->gen >= 4) {
8149                 if (val & DISPPLANE_TILED) {
8150                         plane_config->tiling = I915_TILING_X;
8151                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8152                 }
8153         }
8154
8155         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8156         fourcc = i9xx_format_to_fourcc(pixel_format);
8157         fb->pixel_format = fourcc;
8158         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8159
8160         if (INTEL_INFO(dev)->gen >= 4) {
8161                 if (plane_config->tiling)
8162                         offset = I915_READ(DSPTILEOFF(plane));
8163                 else
8164                         offset = I915_READ(DSPLINOFF(plane));
8165                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8166         } else {
8167                 base = I915_READ(DSPADDR(plane));
8168         }
8169         plane_config->base = base;
8170
8171         val = I915_READ(PIPESRC(pipe));
8172         fb->width = ((val >> 16) & 0xfff) + 1;
8173         fb->height = ((val >> 0) & 0xfff) + 1;
8174
8175         val = I915_READ(DSPSTRIDE(pipe));
8176         fb->pitches[0] = val & 0xffffffc0;
8177
8178         aligned_height = intel_fb_align_height(dev, fb->height,
8179                                                fb->pixel_format,
8180                                                fb->modifier[0]);
8181
8182         plane_config->size = fb->pitches[0] * aligned_height;
8183
8184         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8185                       pipe_name(pipe), plane, fb->width, fb->height,
8186                       fb->bits_per_pixel, base, fb->pitches[0],
8187                       plane_config->size);
8188
8189         plane_config->fb = intel_fb;
8190 }
8191
8192 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8193                                struct intel_crtc_state *pipe_config)
8194 {
8195         struct drm_device *dev = crtc->base.dev;
8196         struct drm_i915_private *dev_priv = to_i915(dev);
8197         int pipe = pipe_config->cpu_transcoder;
8198         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8199         struct dpll clock;
8200         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8201         int refclk = 100000;
8202
8203         /* In case of DSI, DPLL will not be used */
8204         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8205                 return;
8206
8207         mutex_lock(&dev_priv->sb_lock);
8208         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8209         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8210         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8211         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8212         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8213         mutex_unlock(&dev_priv->sb_lock);
8214
8215         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8216         clock.m2 = (pll_dw0 & 0xff) << 22;
8217         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8218                 clock.m2 |= pll_dw2 & 0x3fffff;
8219         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8220         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8221         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8222
8223         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8224 }
8225
8226 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8227                                  struct intel_crtc_state *pipe_config)
8228 {
8229         struct drm_device *dev = crtc->base.dev;
8230         struct drm_i915_private *dev_priv = to_i915(dev);
8231         enum intel_display_power_domain power_domain;
8232         uint32_t tmp;
8233         bool ret;
8234
8235         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8236         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8237                 return false;
8238
8239         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8240         pipe_config->shared_dpll = NULL;
8241
8242         ret = false;
8243
8244         tmp = I915_READ(PIPECONF(crtc->pipe));
8245         if (!(tmp & PIPECONF_ENABLE))
8246                 goto out;
8247
8248         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8249                 switch (tmp & PIPECONF_BPC_MASK) {
8250                 case PIPECONF_6BPC:
8251                         pipe_config->pipe_bpp = 18;
8252                         break;
8253                 case PIPECONF_8BPC:
8254                         pipe_config->pipe_bpp = 24;
8255                         break;
8256                 case PIPECONF_10BPC:
8257                         pipe_config->pipe_bpp = 30;
8258                         break;
8259                 default:
8260                         break;
8261                 }
8262         }
8263
8264         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8265             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8266                 pipe_config->limited_color_range = true;
8267
8268         if (INTEL_INFO(dev)->gen < 4)
8269                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8270
8271         intel_get_pipe_timings(crtc, pipe_config);
8272         intel_get_pipe_src_size(crtc, pipe_config);
8273
8274         i9xx_get_pfit_config(crtc, pipe_config);
8275
8276         if (INTEL_INFO(dev)->gen >= 4) {
8277                 /* No way to read it out on pipes B and C */
8278                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8279                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8280                 else
8281                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8282                 pipe_config->pixel_multiplier =
8283                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8284                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8285                 pipe_config->dpll_hw_state.dpll_md = tmp;
8286         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8287                 tmp = I915_READ(DPLL(crtc->pipe));
8288                 pipe_config->pixel_multiplier =
8289                         ((tmp & SDVO_MULTIPLIER_MASK)
8290                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8291         } else {
8292                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8293                  * port and will be fixed up in the encoder->get_config
8294                  * function. */
8295                 pipe_config->pixel_multiplier = 1;
8296         }
8297         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8298         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8299                 /*
8300                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8301                  * on 830. Filter it out here so that we don't
8302                  * report errors due to that.
8303                  */
8304                 if (IS_I830(dev))
8305                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8306
8307                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8308                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8309         } else {
8310                 /* Mask out read-only status bits. */
8311                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8312                                                      DPLL_PORTC_READY_MASK |
8313                                                      DPLL_PORTB_READY_MASK);
8314         }
8315
8316         if (IS_CHERRYVIEW(dev))
8317                 chv_crtc_clock_get(crtc, pipe_config);
8318         else if (IS_VALLEYVIEW(dev))
8319                 vlv_crtc_clock_get(crtc, pipe_config);
8320         else
8321                 i9xx_crtc_clock_get(crtc, pipe_config);
8322
8323         /*
8324          * Normally the dotclock is filled in by the encoder .get_config()
8325          * but in case the pipe is enabled w/o any ports we need a sane
8326          * default.
8327          */
8328         pipe_config->base.adjusted_mode.crtc_clock =
8329                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8330
8331         ret = true;
8332
8333 out:
8334         intel_display_power_put(dev_priv, power_domain);
8335
8336         return ret;
8337 }
8338
8339 static void ironlake_init_pch_refclk(struct drm_device *dev)
8340 {
8341         struct drm_i915_private *dev_priv = to_i915(dev);
8342         struct intel_encoder *encoder;
8343         int i;
8344         u32 val, final;
8345         bool has_lvds = false;
8346         bool has_cpu_edp = false;
8347         bool has_panel = false;
8348         bool has_ck505 = false;
8349         bool can_ssc = false;
8350         bool using_ssc_source = false;
8351
8352         /* We need to take the global config into account */
8353         for_each_intel_encoder(dev, encoder) {
8354                 switch (encoder->type) {
8355                 case INTEL_OUTPUT_LVDS:
8356                         has_panel = true;
8357                         has_lvds = true;
8358                         break;
8359                 case INTEL_OUTPUT_EDP:
8360                         has_panel = true;
8361                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8362                                 has_cpu_edp = true;
8363                         break;
8364                 default:
8365                         break;
8366                 }
8367         }
8368
8369         if (HAS_PCH_IBX(dev)) {
8370                 has_ck505 = dev_priv->vbt.display_clock_mode;
8371                 can_ssc = has_ck505;
8372         } else {
8373                 has_ck505 = false;
8374                 can_ssc = true;
8375         }
8376
8377         /* Check if any DPLLs are using the SSC source */
8378         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8379                 u32 temp = I915_READ(PCH_DPLL(i));
8380
8381                 if (!(temp & DPLL_VCO_ENABLE))
8382                         continue;
8383
8384                 if ((temp & PLL_REF_INPUT_MASK) ==
8385                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8386                         using_ssc_source = true;
8387                         break;
8388                 }
8389         }
8390
8391         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8392                       has_panel, has_lvds, has_ck505, using_ssc_source);
8393
8394         /* Ironlake: try to setup display ref clock before DPLL
8395          * enabling. This is only under driver's control after
8396          * PCH B stepping, previous chipset stepping should be
8397          * ignoring this setting.
8398          */
8399         val = I915_READ(PCH_DREF_CONTROL);
8400
8401         /* As we must carefully and slowly disable/enable each source in turn,
8402          * compute the final state we want first and check if we need to
8403          * make any changes at all.
8404          */
8405         final = val;
8406         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8407         if (has_ck505)
8408                 final |= DREF_NONSPREAD_CK505_ENABLE;
8409         else
8410                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8411
8412         final &= ~DREF_SSC_SOURCE_MASK;
8413         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8414         final &= ~DREF_SSC1_ENABLE;
8415
8416         if (has_panel) {
8417                 final |= DREF_SSC_SOURCE_ENABLE;
8418
8419                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8420                         final |= DREF_SSC1_ENABLE;
8421
8422                 if (has_cpu_edp) {
8423                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8424                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8425                         else
8426                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8427                 } else
8428                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8429         } else if (using_ssc_source) {
8430                 final |= DREF_SSC_SOURCE_ENABLE;
8431                 final |= DREF_SSC1_ENABLE;
8432         }
8433
8434         if (final == val)
8435                 return;
8436
8437         /* Always enable nonspread source */
8438         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8439
8440         if (has_ck505)
8441                 val |= DREF_NONSPREAD_CK505_ENABLE;
8442         else
8443                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8444
8445         if (has_panel) {
8446                 val &= ~DREF_SSC_SOURCE_MASK;
8447                 val |= DREF_SSC_SOURCE_ENABLE;
8448
8449                 /* SSC must be turned on before enabling the CPU output  */
8450                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8451                         DRM_DEBUG_KMS("Using SSC on panel\n");
8452                         val |= DREF_SSC1_ENABLE;
8453                 } else
8454                         val &= ~DREF_SSC1_ENABLE;
8455
8456                 /* Get SSC going before enabling the outputs */
8457                 I915_WRITE(PCH_DREF_CONTROL, val);
8458                 POSTING_READ(PCH_DREF_CONTROL);
8459                 udelay(200);
8460
8461                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8462
8463                 /* Enable CPU source on CPU attached eDP */
8464                 if (has_cpu_edp) {
8465                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8466                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8467                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8468                         } else
8469                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8470                 } else
8471                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8472
8473                 I915_WRITE(PCH_DREF_CONTROL, val);
8474                 POSTING_READ(PCH_DREF_CONTROL);
8475                 udelay(200);
8476         } else {
8477                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8478
8479                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8480
8481                 /* Turn off CPU output */
8482                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8483
8484                 I915_WRITE(PCH_DREF_CONTROL, val);
8485                 POSTING_READ(PCH_DREF_CONTROL);
8486                 udelay(200);
8487
8488                 if (!using_ssc_source) {
8489                         DRM_DEBUG_KMS("Disabling SSC source\n");
8490
8491                         /* Turn off the SSC source */
8492                         val &= ~DREF_SSC_SOURCE_MASK;
8493                         val |= DREF_SSC_SOURCE_DISABLE;
8494
8495                         /* Turn off SSC1 */
8496                         val &= ~DREF_SSC1_ENABLE;
8497
8498                         I915_WRITE(PCH_DREF_CONTROL, val);
8499                         POSTING_READ(PCH_DREF_CONTROL);
8500                         udelay(200);
8501                 }
8502         }
8503
8504         BUG_ON(val != final);
8505 }
8506
8507 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8508 {
8509         uint32_t tmp;
8510
8511         tmp = I915_READ(SOUTH_CHICKEN2);
8512         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8513         I915_WRITE(SOUTH_CHICKEN2, tmp);
8514
8515         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8516                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8517                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8518
8519         tmp = I915_READ(SOUTH_CHICKEN2);
8520         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8521         I915_WRITE(SOUTH_CHICKEN2, tmp);
8522
8523         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8524                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8525                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8526 }
8527
8528 /* WaMPhyProgramming:hsw */
8529 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8530 {
8531         uint32_t tmp;
8532
8533         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8534         tmp &= ~(0xFF << 24);
8535         tmp |= (0x12 << 24);
8536         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8537
8538         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8539         tmp |= (1 << 11);
8540         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8541
8542         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8543         tmp |= (1 << 11);
8544         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8545
8546         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8547         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8548         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8549
8550         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8551         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8552         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8553
8554         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8555         tmp &= ~(7 << 13);
8556         tmp |= (5 << 13);
8557         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8558
8559         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8560         tmp &= ~(7 << 13);
8561         tmp |= (5 << 13);
8562         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8563
8564         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8565         tmp &= ~0xFF;
8566         tmp |= 0x1C;
8567         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8568
8569         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8570         tmp &= ~0xFF;
8571         tmp |= 0x1C;
8572         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8573
8574         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8575         tmp &= ~(0xFF << 16);
8576         tmp |= (0x1C << 16);
8577         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8578
8579         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8580         tmp &= ~(0xFF << 16);
8581         tmp |= (0x1C << 16);
8582         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8583
8584         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8585         tmp |= (1 << 27);
8586         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8587
8588         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8589         tmp |= (1 << 27);
8590         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8591
8592         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8593         tmp &= ~(0xF << 28);
8594         tmp |= (4 << 28);
8595         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8596
8597         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8598         tmp &= ~(0xF << 28);
8599         tmp |= (4 << 28);
8600         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8601 }
8602
8603 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8604  * Programming" based on the parameters passed:
8605  * - Sequence to enable CLKOUT_DP
8606  * - Sequence to enable CLKOUT_DP without spread
8607  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8608  */
8609 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8610                                  bool with_fdi)
8611 {
8612         struct drm_i915_private *dev_priv = to_i915(dev);
8613         uint32_t reg, tmp;
8614
8615         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8616                 with_spread = true;
8617         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8618                 with_fdi = false;
8619
8620         mutex_lock(&dev_priv->sb_lock);
8621
8622         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8623         tmp &= ~SBI_SSCCTL_DISABLE;
8624         tmp |= SBI_SSCCTL_PATHALT;
8625         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8626
8627         udelay(24);
8628
8629         if (with_spread) {
8630                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8631                 tmp &= ~SBI_SSCCTL_PATHALT;
8632                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8633
8634                 if (with_fdi) {
8635                         lpt_reset_fdi_mphy(dev_priv);
8636                         lpt_program_fdi_mphy(dev_priv);
8637                 }
8638         }
8639
8640         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8641         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8642         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8643         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8644
8645         mutex_unlock(&dev_priv->sb_lock);
8646 }
8647
8648 /* Sequence to disable CLKOUT_DP */
8649 static void lpt_disable_clkout_dp(struct drm_device *dev)
8650 {
8651         struct drm_i915_private *dev_priv = to_i915(dev);
8652         uint32_t reg, tmp;
8653
8654         mutex_lock(&dev_priv->sb_lock);
8655
8656         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8657         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8658         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8659         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8660
8661         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8662         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8663                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8664                         tmp |= SBI_SSCCTL_PATHALT;
8665                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8666                         udelay(32);
8667                 }
8668                 tmp |= SBI_SSCCTL_DISABLE;
8669                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8670         }
8671
8672         mutex_unlock(&dev_priv->sb_lock);
8673 }
8674
8675 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8676
8677 static const uint16_t sscdivintphase[] = {
8678         [BEND_IDX( 50)] = 0x3B23,
8679         [BEND_IDX( 45)] = 0x3B23,
8680         [BEND_IDX( 40)] = 0x3C23,
8681         [BEND_IDX( 35)] = 0x3C23,
8682         [BEND_IDX( 30)] = 0x3D23,
8683         [BEND_IDX( 25)] = 0x3D23,
8684         [BEND_IDX( 20)] = 0x3E23,
8685         [BEND_IDX( 15)] = 0x3E23,
8686         [BEND_IDX( 10)] = 0x3F23,
8687         [BEND_IDX(  5)] = 0x3F23,
8688         [BEND_IDX(  0)] = 0x0025,
8689         [BEND_IDX( -5)] = 0x0025,
8690         [BEND_IDX(-10)] = 0x0125,
8691         [BEND_IDX(-15)] = 0x0125,
8692         [BEND_IDX(-20)] = 0x0225,
8693         [BEND_IDX(-25)] = 0x0225,
8694         [BEND_IDX(-30)] = 0x0325,
8695         [BEND_IDX(-35)] = 0x0325,
8696         [BEND_IDX(-40)] = 0x0425,
8697         [BEND_IDX(-45)] = 0x0425,
8698         [BEND_IDX(-50)] = 0x0525,
8699 };
8700
8701 /*
8702  * Bend CLKOUT_DP
8703  * steps -50 to 50 inclusive, in steps of 5
8704  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8705  * change in clock period = -(steps / 10) * 5.787 ps
8706  */
8707 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8708 {
8709         uint32_t tmp;
8710         int idx = BEND_IDX(steps);
8711
8712         if (WARN_ON(steps % 5 != 0))
8713                 return;
8714
8715         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8716                 return;
8717
8718         mutex_lock(&dev_priv->sb_lock);
8719
8720         if (steps % 10 != 0)
8721                 tmp = 0xAAAAAAAB;
8722         else
8723                 tmp = 0x00000000;
8724         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8725
8726         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8727         tmp &= 0xffff0000;
8728         tmp |= sscdivintphase[idx];
8729         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8730
8731         mutex_unlock(&dev_priv->sb_lock);
8732 }
8733
8734 #undef BEND_IDX
8735
8736 static void lpt_init_pch_refclk(struct drm_device *dev)
8737 {
8738         struct intel_encoder *encoder;
8739         bool has_vga = false;
8740
8741         for_each_intel_encoder(dev, encoder) {
8742                 switch (encoder->type) {
8743                 case INTEL_OUTPUT_ANALOG:
8744                         has_vga = true;
8745                         break;
8746                 default:
8747                         break;
8748                 }
8749         }
8750
8751         if (has_vga) {
8752                 lpt_bend_clkout_dp(to_i915(dev), 0);
8753                 lpt_enable_clkout_dp(dev, true, true);
8754         } else {
8755                 lpt_disable_clkout_dp(dev);
8756         }
8757 }
8758
8759 /*
8760  * Initialize reference clocks when the driver loads
8761  */
8762 void intel_init_pch_refclk(struct drm_device *dev)
8763 {
8764         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8765                 ironlake_init_pch_refclk(dev);
8766         else if (HAS_PCH_LPT(dev))
8767                 lpt_init_pch_refclk(dev);
8768 }
8769
8770 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8771 {
8772         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8774         int pipe = intel_crtc->pipe;
8775         uint32_t val;
8776
8777         val = 0;
8778
8779         switch (intel_crtc->config->pipe_bpp) {
8780         case 18:
8781                 val |= PIPECONF_6BPC;
8782                 break;
8783         case 24:
8784                 val |= PIPECONF_8BPC;
8785                 break;
8786         case 30:
8787                 val |= PIPECONF_10BPC;
8788                 break;
8789         case 36:
8790                 val |= PIPECONF_12BPC;
8791                 break;
8792         default:
8793                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8794                 BUG();
8795         }
8796
8797         if (intel_crtc->config->dither)
8798                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8799
8800         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8801                 val |= PIPECONF_INTERLACED_ILK;
8802         else
8803                 val |= PIPECONF_PROGRESSIVE;
8804
8805         if (intel_crtc->config->limited_color_range)
8806                 val |= PIPECONF_COLOR_RANGE_SELECT;
8807
8808         I915_WRITE(PIPECONF(pipe), val);
8809         POSTING_READ(PIPECONF(pipe));
8810 }
8811
8812 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8813 {
8814         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8816         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8817         u32 val = 0;
8818
8819         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8820                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8821
8822         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8823                 val |= PIPECONF_INTERLACED_ILK;
8824         else
8825                 val |= PIPECONF_PROGRESSIVE;
8826
8827         I915_WRITE(PIPECONF(cpu_transcoder), val);
8828         POSTING_READ(PIPECONF(cpu_transcoder));
8829 }
8830
8831 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8832 {
8833         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8835
8836         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8837                 u32 val = 0;
8838
8839                 switch (intel_crtc->config->pipe_bpp) {
8840                 case 18:
8841                         val |= PIPEMISC_DITHER_6_BPC;
8842                         break;
8843                 case 24:
8844                         val |= PIPEMISC_DITHER_8_BPC;
8845                         break;
8846                 case 30:
8847                         val |= PIPEMISC_DITHER_10_BPC;
8848                         break;
8849                 case 36:
8850                         val |= PIPEMISC_DITHER_12_BPC;
8851                         break;
8852                 default:
8853                         /* Case prevented by pipe_config_set_bpp. */
8854                         BUG();
8855                 }
8856
8857                 if (intel_crtc->config->dither)
8858                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8859
8860                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8861         }
8862 }
8863
8864 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8865 {
8866         /*
8867          * Account for spread spectrum to avoid
8868          * oversubscribing the link. Max center spread
8869          * is 2.5%; use 5% for safety's sake.
8870          */
8871         u32 bps = target_clock * bpp * 21 / 20;
8872         return DIV_ROUND_UP(bps, link_bw * 8);
8873 }
8874
8875 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8876 {
8877         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8878 }
8879
8880 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8881                                   struct intel_crtc_state *crtc_state,
8882                                   struct dpll *reduced_clock)
8883 {
8884         struct drm_crtc *crtc = &intel_crtc->base;
8885         struct drm_device *dev = crtc->dev;
8886         struct drm_i915_private *dev_priv = to_i915(dev);
8887         u32 dpll, fp, fp2;
8888         int factor;
8889
8890         /* Enable autotuning of the PLL clock (if permissible) */
8891         factor = 21;
8892         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8893                 if ((intel_panel_use_ssc(dev_priv) &&
8894                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8895                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8896                         factor = 25;
8897         } else if (crtc_state->sdvo_tv_clock)
8898                 factor = 20;
8899
8900         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8901
8902         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8903                 fp |= FP_CB_TUNE;
8904
8905         if (reduced_clock) {
8906                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8907
8908                 if (reduced_clock->m < factor * reduced_clock->n)
8909                         fp2 |= FP_CB_TUNE;
8910         } else {
8911                 fp2 = fp;
8912         }
8913
8914         dpll = 0;
8915
8916         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8917                 dpll |= DPLLB_MODE_LVDS;
8918         else
8919                 dpll |= DPLLB_MODE_DAC_SERIAL;
8920
8921         dpll |= (crtc_state->pixel_multiplier - 1)
8922                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8923
8924         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8925             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8926                 dpll |= DPLL_SDVO_HIGH_SPEED;
8927
8928         if (intel_crtc_has_dp_encoder(crtc_state))
8929                 dpll |= DPLL_SDVO_HIGH_SPEED;
8930
8931         /* compute bitmask from p1 value */
8932         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8933         /* also FPA1 */
8934         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8935
8936         switch (crtc_state->dpll.p2) {
8937         case 5:
8938                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8939                 break;
8940         case 7:
8941                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8942                 break;
8943         case 10:
8944                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8945                 break;
8946         case 14:
8947                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8948                 break;
8949         }
8950
8951         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8952             intel_panel_use_ssc(dev_priv))
8953                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8954         else
8955                 dpll |= PLL_REF_INPUT_DREFCLK;
8956
8957         dpll |= DPLL_VCO_ENABLE;
8958
8959         crtc_state->dpll_hw_state.dpll = dpll;
8960         crtc_state->dpll_hw_state.fp0 = fp;
8961         crtc_state->dpll_hw_state.fp1 = fp2;
8962 }
8963
8964 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8965                                        struct intel_crtc_state *crtc_state)
8966 {
8967         struct drm_device *dev = crtc->base.dev;
8968         struct drm_i915_private *dev_priv = to_i915(dev);
8969         struct dpll reduced_clock;
8970         bool has_reduced_clock = false;
8971         struct intel_shared_dpll *pll;
8972         const struct intel_limit *limit;
8973         int refclk = 120000;
8974
8975         memset(&crtc_state->dpll_hw_state, 0,
8976                sizeof(crtc_state->dpll_hw_state));
8977
8978         crtc->lowfreq_avail = false;
8979
8980         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8981         if (!crtc_state->has_pch_encoder)
8982                 return 0;
8983
8984         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8985                 if (intel_panel_use_ssc(dev_priv)) {
8986                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8987                                       dev_priv->vbt.lvds_ssc_freq);
8988                         refclk = dev_priv->vbt.lvds_ssc_freq;
8989                 }
8990
8991                 if (intel_is_dual_link_lvds(dev)) {
8992                         if (refclk == 100000)
8993                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8994                         else
8995                                 limit = &intel_limits_ironlake_dual_lvds;
8996                 } else {
8997                         if (refclk == 100000)
8998                                 limit = &intel_limits_ironlake_single_lvds_100m;
8999                         else
9000                                 limit = &intel_limits_ironlake_single_lvds;
9001                 }
9002         } else {
9003                 limit = &intel_limits_ironlake_dac;
9004         }
9005
9006         if (!crtc_state->clock_set &&
9007             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9008                                 refclk, NULL, &crtc_state->dpll)) {
9009                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9010                 return -EINVAL;
9011         }
9012
9013         ironlake_compute_dpll(crtc, crtc_state,
9014                               has_reduced_clock ? &reduced_clock : NULL);
9015
9016         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9017         if (pll == NULL) {
9018                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9019                                  pipe_name(crtc->pipe));
9020                 return -EINVAL;
9021         }
9022
9023         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9024             has_reduced_clock)
9025                 crtc->lowfreq_avail = true;
9026
9027         return 0;
9028 }
9029
9030 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9031                                          struct intel_link_m_n *m_n)
9032 {
9033         struct drm_device *dev = crtc->base.dev;
9034         struct drm_i915_private *dev_priv = to_i915(dev);
9035         enum pipe pipe = crtc->pipe;
9036
9037         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9038         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9039         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9040                 & ~TU_SIZE_MASK;
9041         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9042         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9043                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9044 }
9045
9046 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9047                                          enum transcoder transcoder,
9048                                          struct intel_link_m_n *m_n,
9049                                          struct intel_link_m_n *m2_n2)
9050 {
9051         struct drm_device *dev = crtc->base.dev;
9052         struct drm_i915_private *dev_priv = to_i915(dev);
9053         enum pipe pipe = crtc->pipe;
9054
9055         if (INTEL_INFO(dev)->gen >= 5) {
9056                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9057                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9058                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9059                         & ~TU_SIZE_MASK;
9060                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9061                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9062                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9063                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9064                  * gen < 8) and if DRRS is supported (to make sure the
9065                  * registers are not unnecessarily read).
9066                  */
9067                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9068                         crtc->config->has_drrs) {
9069                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9070                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9071                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9072                                         & ~TU_SIZE_MASK;
9073                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9074                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9075                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9076                 }
9077         } else {
9078                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9079                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9080                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9081                         & ~TU_SIZE_MASK;
9082                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9083                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9084                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9085         }
9086 }
9087
9088 void intel_dp_get_m_n(struct intel_crtc *crtc,
9089                       struct intel_crtc_state *pipe_config)
9090 {
9091         if (pipe_config->has_pch_encoder)
9092                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9093         else
9094                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9095                                              &pipe_config->dp_m_n,
9096                                              &pipe_config->dp_m2_n2);
9097 }
9098
9099 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9100                                         struct intel_crtc_state *pipe_config)
9101 {
9102         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9103                                      &pipe_config->fdi_m_n, NULL);
9104 }
9105
9106 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9107                                     struct intel_crtc_state *pipe_config)
9108 {
9109         struct drm_device *dev = crtc->base.dev;
9110         struct drm_i915_private *dev_priv = to_i915(dev);
9111         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9112         uint32_t ps_ctrl = 0;
9113         int id = -1;
9114         int i;
9115
9116         /* find scaler attached to this pipe */
9117         for (i = 0; i < crtc->num_scalers; i++) {
9118                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9119                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9120                         id = i;
9121                         pipe_config->pch_pfit.enabled = true;
9122                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9123                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9124                         break;
9125                 }
9126         }
9127
9128         scaler_state->scaler_id = id;
9129         if (id >= 0) {
9130                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9131         } else {
9132                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9133         }
9134 }
9135
9136 static void
9137 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9138                                  struct intel_initial_plane_config *plane_config)
9139 {
9140         struct drm_device *dev = crtc->base.dev;
9141         struct drm_i915_private *dev_priv = to_i915(dev);
9142         u32 val, base, offset, stride_mult, tiling;
9143         int pipe = crtc->pipe;
9144         int fourcc, pixel_format;
9145         unsigned int aligned_height;
9146         struct drm_framebuffer *fb;
9147         struct intel_framebuffer *intel_fb;
9148
9149         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9150         if (!intel_fb) {
9151                 DRM_DEBUG_KMS("failed to alloc fb\n");
9152                 return;
9153         }
9154
9155         fb = &intel_fb->base;
9156
9157         val = I915_READ(PLANE_CTL(pipe, 0));
9158         if (!(val & PLANE_CTL_ENABLE))
9159                 goto error;
9160
9161         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9162         fourcc = skl_format_to_fourcc(pixel_format,
9163                                       val & PLANE_CTL_ORDER_RGBX,
9164                                       val & PLANE_CTL_ALPHA_MASK);
9165         fb->pixel_format = fourcc;
9166         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9167
9168         tiling = val & PLANE_CTL_TILED_MASK;
9169         switch (tiling) {
9170         case PLANE_CTL_TILED_LINEAR:
9171                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9172                 break;
9173         case PLANE_CTL_TILED_X:
9174                 plane_config->tiling = I915_TILING_X;
9175                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9176                 break;
9177         case PLANE_CTL_TILED_Y:
9178                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9179                 break;
9180         case PLANE_CTL_TILED_YF:
9181                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9182                 break;
9183         default:
9184                 MISSING_CASE(tiling);
9185                 goto error;
9186         }
9187
9188         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9189         plane_config->base = base;
9190
9191         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9192
9193         val = I915_READ(PLANE_SIZE(pipe, 0));
9194         fb->height = ((val >> 16) & 0xfff) + 1;
9195         fb->width = ((val >> 0) & 0x1fff) + 1;
9196
9197         val = I915_READ(PLANE_STRIDE(pipe, 0));
9198         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9199                                                 fb->pixel_format);
9200         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9201
9202         aligned_height = intel_fb_align_height(dev, fb->height,
9203                                                fb->pixel_format,
9204                                                fb->modifier[0]);
9205
9206         plane_config->size = fb->pitches[0] * aligned_height;
9207
9208         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9209                       pipe_name(pipe), fb->width, fb->height,
9210                       fb->bits_per_pixel, base, fb->pitches[0],
9211                       plane_config->size);
9212
9213         plane_config->fb = intel_fb;
9214         return;
9215
9216 error:
9217         kfree(fb);
9218 }
9219
9220 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9221                                      struct intel_crtc_state *pipe_config)
9222 {
9223         struct drm_device *dev = crtc->base.dev;
9224         struct drm_i915_private *dev_priv = to_i915(dev);
9225         uint32_t tmp;
9226
9227         tmp = I915_READ(PF_CTL(crtc->pipe));
9228
9229         if (tmp & PF_ENABLE) {
9230                 pipe_config->pch_pfit.enabled = true;
9231                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9232                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9233
9234                 /* We currently do not free assignements of panel fitters on
9235                  * ivb/hsw (since we don't use the higher upscaling modes which
9236                  * differentiates them) so just WARN about this case for now. */
9237                 if (IS_GEN7(dev)) {
9238                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9239                                 PF_PIPE_SEL_IVB(crtc->pipe));
9240                 }
9241         }
9242 }
9243
9244 static void
9245 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9246                                   struct intel_initial_plane_config *plane_config)
9247 {
9248         struct drm_device *dev = crtc->base.dev;
9249         struct drm_i915_private *dev_priv = to_i915(dev);
9250         u32 val, base, offset;
9251         int pipe = crtc->pipe;
9252         int fourcc, pixel_format;
9253         unsigned int aligned_height;
9254         struct drm_framebuffer *fb;
9255         struct intel_framebuffer *intel_fb;
9256
9257         val = I915_READ(DSPCNTR(pipe));
9258         if (!(val & DISPLAY_PLANE_ENABLE))
9259                 return;
9260
9261         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9262         if (!intel_fb) {
9263                 DRM_DEBUG_KMS("failed to alloc fb\n");
9264                 return;
9265         }
9266
9267         fb = &intel_fb->base;
9268
9269         if (INTEL_INFO(dev)->gen >= 4) {
9270                 if (val & DISPPLANE_TILED) {
9271                         plane_config->tiling = I915_TILING_X;
9272                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9273                 }
9274         }
9275
9276         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9277         fourcc = i9xx_format_to_fourcc(pixel_format);
9278         fb->pixel_format = fourcc;
9279         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9280
9281         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9282         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9283                 offset = I915_READ(DSPOFFSET(pipe));
9284         } else {
9285                 if (plane_config->tiling)
9286                         offset = I915_READ(DSPTILEOFF(pipe));
9287                 else
9288                         offset = I915_READ(DSPLINOFF(pipe));
9289         }
9290         plane_config->base = base;
9291
9292         val = I915_READ(PIPESRC(pipe));
9293         fb->width = ((val >> 16) & 0xfff) + 1;
9294         fb->height = ((val >> 0) & 0xfff) + 1;
9295
9296         val = I915_READ(DSPSTRIDE(pipe));
9297         fb->pitches[0] = val & 0xffffffc0;
9298
9299         aligned_height = intel_fb_align_height(dev, fb->height,
9300                                                fb->pixel_format,
9301                                                fb->modifier[0]);
9302
9303         plane_config->size = fb->pitches[0] * aligned_height;
9304
9305         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9306                       pipe_name(pipe), fb->width, fb->height,
9307                       fb->bits_per_pixel, base, fb->pitches[0],
9308                       plane_config->size);
9309
9310         plane_config->fb = intel_fb;
9311 }
9312
9313 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9314                                      struct intel_crtc_state *pipe_config)
9315 {
9316         struct drm_device *dev = crtc->base.dev;
9317         struct drm_i915_private *dev_priv = to_i915(dev);
9318         enum intel_display_power_domain power_domain;
9319         uint32_t tmp;
9320         bool ret;
9321
9322         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9323         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9324                 return false;
9325
9326         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9327         pipe_config->shared_dpll = NULL;
9328
9329         ret = false;
9330         tmp = I915_READ(PIPECONF(crtc->pipe));
9331         if (!(tmp & PIPECONF_ENABLE))
9332                 goto out;
9333
9334         switch (tmp & PIPECONF_BPC_MASK) {
9335         case PIPECONF_6BPC:
9336                 pipe_config->pipe_bpp = 18;
9337                 break;
9338         case PIPECONF_8BPC:
9339                 pipe_config->pipe_bpp = 24;
9340                 break;
9341         case PIPECONF_10BPC:
9342                 pipe_config->pipe_bpp = 30;
9343                 break;
9344         case PIPECONF_12BPC:
9345                 pipe_config->pipe_bpp = 36;
9346                 break;
9347         default:
9348                 break;
9349         }
9350
9351         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9352                 pipe_config->limited_color_range = true;
9353
9354         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9355                 struct intel_shared_dpll *pll;
9356                 enum intel_dpll_id pll_id;
9357
9358                 pipe_config->has_pch_encoder = true;
9359
9360                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9361                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9362                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9363
9364                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9365
9366                 if (HAS_PCH_IBX(dev_priv)) {
9367                         /*
9368                          * The pipe->pch transcoder and pch transcoder->pll
9369                          * mapping is fixed.
9370                          */
9371                         pll_id = (enum intel_dpll_id) crtc->pipe;
9372                 } else {
9373                         tmp = I915_READ(PCH_DPLL_SEL);
9374                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9375                                 pll_id = DPLL_ID_PCH_PLL_B;
9376                         else
9377                                 pll_id= DPLL_ID_PCH_PLL_A;
9378                 }
9379
9380                 pipe_config->shared_dpll =
9381                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9382                 pll = pipe_config->shared_dpll;
9383
9384                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9385                                                  &pipe_config->dpll_hw_state));
9386
9387                 tmp = pipe_config->dpll_hw_state.dpll;
9388                 pipe_config->pixel_multiplier =
9389                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9390                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9391
9392                 ironlake_pch_clock_get(crtc, pipe_config);
9393         } else {
9394                 pipe_config->pixel_multiplier = 1;
9395         }
9396
9397         intel_get_pipe_timings(crtc, pipe_config);
9398         intel_get_pipe_src_size(crtc, pipe_config);
9399
9400         ironlake_get_pfit_config(crtc, pipe_config);
9401
9402         ret = true;
9403
9404 out:
9405         intel_display_power_put(dev_priv, power_domain);
9406
9407         return ret;
9408 }
9409
9410 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9411 {
9412         struct drm_device *dev = &dev_priv->drm;
9413         struct intel_crtc *crtc;
9414
9415         for_each_intel_crtc(dev, crtc)
9416                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9417                      pipe_name(crtc->pipe));
9418
9419         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9420         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9421         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9422         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9423         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9424         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9425              "CPU PWM1 enabled\n");
9426         if (IS_HASWELL(dev))
9427                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9428                      "CPU PWM2 enabled\n");
9429         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9430              "PCH PWM1 enabled\n");
9431         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9432              "Utility pin enabled\n");
9433         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9434
9435         /*
9436          * In theory we can still leave IRQs enabled, as long as only the HPD
9437          * interrupts remain enabled. We used to check for that, but since it's
9438          * gen-specific and since we only disable LCPLL after we fully disable
9439          * the interrupts, the check below should be enough.
9440          */
9441         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9442 }
9443
9444 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9445 {
9446         struct drm_device *dev = &dev_priv->drm;
9447
9448         if (IS_HASWELL(dev))
9449                 return I915_READ(D_COMP_HSW);
9450         else
9451                 return I915_READ(D_COMP_BDW);
9452 }
9453
9454 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9455 {
9456         struct drm_device *dev = &dev_priv->drm;
9457
9458         if (IS_HASWELL(dev)) {
9459                 mutex_lock(&dev_priv->rps.hw_lock);
9460                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9461                                             val))
9462                         DRM_ERROR("Failed to write to D_COMP\n");
9463                 mutex_unlock(&dev_priv->rps.hw_lock);
9464         } else {
9465                 I915_WRITE(D_COMP_BDW, val);
9466                 POSTING_READ(D_COMP_BDW);
9467         }
9468 }
9469
9470 /*
9471  * This function implements pieces of two sequences from BSpec:
9472  * - Sequence for display software to disable LCPLL
9473  * - Sequence for display software to allow package C8+
9474  * The steps implemented here are just the steps that actually touch the LCPLL
9475  * register. Callers should take care of disabling all the display engine
9476  * functions, doing the mode unset, fixing interrupts, etc.
9477  */
9478 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9479                               bool switch_to_fclk, bool allow_power_down)
9480 {
9481         uint32_t val;
9482
9483         assert_can_disable_lcpll(dev_priv);
9484
9485         val = I915_READ(LCPLL_CTL);
9486
9487         if (switch_to_fclk) {
9488                 val |= LCPLL_CD_SOURCE_FCLK;
9489                 I915_WRITE(LCPLL_CTL, val);
9490
9491                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9492                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9493                         DRM_ERROR("Switching to FCLK failed\n");
9494
9495                 val = I915_READ(LCPLL_CTL);
9496         }
9497
9498         val |= LCPLL_PLL_DISABLE;
9499         I915_WRITE(LCPLL_CTL, val);
9500         POSTING_READ(LCPLL_CTL);
9501
9502         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9503                 DRM_ERROR("LCPLL still locked\n");
9504
9505         val = hsw_read_dcomp(dev_priv);
9506         val |= D_COMP_COMP_DISABLE;
9507         hsw_write_dcomp(dev_priv, val);
9508         ndelay(100);
9509
9510         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9511                      1))
9512                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9513
9514         if (allow_power_down) {
9515                 val = I915_READ(LCPLL_CTL);
9516                 val |= LCPLL_POWER_DOWN_ALLOW;
9517                 I915_WRITE(LCPLL_CTL, val);
9518                 POSTING_READ(LCPLL_CTL);
9519         }
9520 }
9521
9522 /*
9523  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9524  * source.
9525  */
9526 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9527 {
9528         uint32_t val;
9529
9530         val = I915_READ(LCPLL_CTL);
9531
9532         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9533                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9534                 return;
9535
9536         /*
9537          * Make sure we're not on PC8 state before disabling PC8, otherwise
9538          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9539          */
9540         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9541
9542         if (val & LCPLL_POWER_DOWN_ALLOW) {
9543                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9544                 I915_WRITE(LCPLL_CTL, val);
9545                 POSTING_READ(LCPLL_CTL);
9546         }
9547
9548         val = hsw_read_dcomp(dev_priv);
9549         val |= D_COMP_COMP_FORCE;
9550         val &= ~D_COMP_COMP_DISABLE;
9551         hsw_write_dcomp(dev_priv, val);
9552
9553         val = I915_READ(LCPLL_CTL);
9554         val &= ~LCPLL_PLL_DISABLE;
9555         I915_WRITE(LCPLL_CTL, val);
9556
9557         if (intel_wait_for_register(dev_priv,
9558                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9559                                     5))
9560                 DRM_ERROR("LCPLL not locked yet\n");
9561
9562         if (val & LCPLL_CD_SOURCE_FCLK) {
9563                 val = I915_READ(LCPLL_CTL);
9564                 val &= ~LCPLL_CD_SOURCE_FCLK;
9565                 I915_WRITE(LCPLL_CTL, val);
9566
9567                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9568                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9569                         DRM_ERROR("Switching back to LCPLL failed\n");
9570         }
9571
9572         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9573         intel_update_cdclk(&dev_priv->drm);
9574 }
9575
9576 /*
9577  * Package states C8 and deeper are really deep PC states that can only be
9578  * reached when all the devices on the system allow it, so even if the graphics
9579  * device allows PC8+, it doesn't mean the system will actually get to these
9580  * states. Our driver only allows PC8+ when going into runtime PM.
9581  *
9582  * The requirements for PC8+ are that all the outputs are disabled, the power
9583  * well is disabled and most interrupts are disabled, and these are also
9584  * requirements for runtime PM. When these conditions are met, we manually do
9585  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9586  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9587  * hang the machine.
9588  *
9589  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9590  * the state of some registers, so when we come back from PC8+ we need to
9591  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9592  * need to take care of the registers kept by RC6. Notice that this happens even
9593  * if we don't put the device in PCI D3 state (which is what currently happens
9594  * because of the runtime PM support).
9595  *
9596  * For more, read "Display Sequences for Package C8" on the hardware
9597  * documentation.
9598  */
9599 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9600 {
9601         struct drm_device *dev = &dev_priv->drm;
9602         uint32_t val;
9603
9604         DRM_DEBUG_KMS("Enabling package C8+\n");
9605
9606         if (HAS_PCH_LPT_LP(dev)) {
9607                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9608                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9609                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9610         }
9611
9612         lpt_disable_clkout_dp(dev);
9613         hsw_disable_lcpll(dev_priv, true, true);
9614 }
9615
9616 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9617 {
9618         struct drm_device *dev = &dev_priv->drm;
9619         uint32_t val;
9620
9621         DRM_DEBUG_KMS("Disabling package C8+\n");
9622
9623         hsw_restore_lcpll(dev_priv);
9624         lpt_init_pch_refclk(dev);
9625
9626         if (HAS_PCH_LPT_LP(dev)) {
9627                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9628                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9629                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9630         }
9631 }
9632
9633 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9634 {
9635         struct drm_device *dev = old_state->dev;
9636         struct intel_atomic_state *old_intel_state =
9637                 to_intel_atomic_state(old_state);
9638         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9639
9640         bxt_set_cdclk(to_i915(dev), req_cdclk);
9641 }
9642
9643 /* compute the max rate for new configuration */
9644 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9645 {
9646         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9647         struct drm_i915_private *dev_priv = to_i915(state->dev);
9648         struct drm_crtc *crtc;
9649         struct drm_crtc_state *cstate;
9650         struct intel_crtc_state *crtc_state;
9651         unsigned max_pixel_rate = 0, i;
9652         enum pipe pipe;
9653
9654         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9655                sizeof(intel_state->min_pixclk));
9656
9657         for_each_crtc_in_state(state, crtc, cstate, i) {
9658                 int pixel_rate;
9659
9660                 crtc_state = to_intel_crtc_state(cstate);
9661                 if (!crtc_state->base.enable) {
9662                         intel_state->min_pixclk[i] = 0;
9663                         continue;
9664                 }
9665
9666                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9667
9668                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9669                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9670                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9671
9672                 intel_state->min_pixclk[i] = pixel_rate;
9673         }
9674
9675         for_each_pipe(dev_priv, pipe)
9676                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9677
9678         return max_pixel_rate;
9679 }
9680
9681 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9682 {
9683         struct drm_i915_private *dev_priv = to_i915(dev);
9684         uint32_t val, data;
9685         int ret;
9686
9687         if (WARN((I915_READ(LCPLL_CTL) &
9688                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9689                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9690                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9691                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9692                  "trying to change cdclk frequency with cdclk not enabled\n"))
9693                 return;
9694
9695         mutex_lock(&dev_priv->rps.hw_lock);
9696         ret = sandybridge_pcode_write(dev_priv,
9697                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9698         mutex_unlock(&dev_priv->rps.hw_lock);
9699         if (ret) {
9700                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9701                 return;
9702         }
9703
9704         val = I915_READ(LCPLL_CTL);
9705         val |= LCPLL_CD_SOURCE_FCLK;
9706         I915_WRITE(LCPLL_CTL, val);
9707
9708         if (wait_for_us(I915_READ(LCPLL_CTL) &
9709                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9710                 DRM_ERROR("Switching to FCLK failed\n");
9711
9712         val = I915_READ(LCPLL_CTL);
9713         val &= ~LCPLL_CLK_FREQ_MASK;
9714
9715         switch (cdclk) {
9716         case 450000:
9717                 val |= LCPLL_CLK_FREQ_450;
9718                 data = 0;
9719                 break;
9720         case 540000:
9721                 val |= LCPLL_CLK_FREQ_54O_BDW;
9722                 data = 1;
9723                 break;
9724         case 337500:
9725                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9726                 data = 2;
9727                 break;
9728         case 675000:
9729                 val |= LCPLL_CLK_FREQ_675_BDW;
9730                 data = 3;
9731                 break;
9732         default:
9733                 WARN(1, "invalid cdclk frequency\n");
9734                 return;
9735         }
9736
9737         I915_WRITE(LCPLL_CTL, val);
9738
9739         val = I915_READ(LCPLL_CTL);
9740         val &= ~LCPLL_CD_SOURCE_FCLK;
9741         I915_WRITE(LCPLL_CTL, val);
9742
9743         if (wait_for_us((I915_READ(LCPLL_CTL) &
9744                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9745                 DRM_ERROR("Switching back to LCPLL failed\n");
9746
9747         mutex_lock(&dev_priv->rps.hw_lock);
9748         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9749         mutex_unlock(&dev_priv->rps.hw_lock);
9750
9751         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9752
9753         intel_update_cdclk(dev);
9754
9755         WARN(cdclk != dev_priv->cdclk_freq,
9756              "cdclk requested %d kHz but got %d kHz\n",
9757              cdclk, dev_priv->cdclk_freq);
9758 }
9759
9760 static int broadwell_calc_cdclk(int max_pixclk)
9761 {
9762         if (max_pixclk > 540000)
9763                 return 675000;
9764         else if (max_pixclk > 450000)
9765                 return 540000;
9766         else if (max_pixclk > 337500)
9767                 return 450000;
9768         else
9769                 return 337500;
9770 }
9771
9772 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9773 {
9774         struct drm_i915_private *dev_priv = to_i915(state->dev);
9775         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9776         int max_pixclk = ilk_max_pixel_rate(state);
9777         int cdclk;
9778
9779         /*
9780          * FIXME should also account for plane ratio
9781          * once 64bpp pixel formats are supported.
9782          */
9783         cdclk = broadwell_calc_cdclk(max_pixclk);
9784
9785         if (cdclk > dev_priv->max_cdclk_freq) {
9786                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9787                               cdclk, dev_priv->max_cdclk_freq);
9788                 return -EINVAL;
9789         }
9790
9791         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9792         if (!intel_state->active_crtcs)
9793                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9794
9795         return 0;
9796 }
9797
9798 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9799 {
9800         struct drm_device *dev = old_state->dev;
9801         struct intel_atomic_state *old_intel_state =
9802                 to_intel_atomic_state(old_state);
9803         unsigned req_cdclk = old_intel_state->dev_cdclk;
9804
9805         broadwell_set_cdclk(dev, req_cdclk);
9806 }
9807
9808 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9809 {
9810         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9811         struct drm_i915_private *dev_priv = to_i915(state->dev);
9812         const int max_pixclk = ilk_max_pixel_rate(state);
9813         int vco = intel_state->cdclk_pll_vco;
9814         int cdclk;
9815
9816         /*
9817          * FIXME should also account for plane ratio
9818          * once 64bpp pixel formats are supported.
9819          */
9820         cdclk = skl_calc_cdclk(max_pixclk, vco);
9821
9822         /*
9823          * FIXME move the cdclk caclulation to
9824          * compute_config() so we can fail gracegully.
9825          */
9826         if (cdclk > dev_priv->max_cdclk_freq) {
9827                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9828                           cdclk, dev_priv->max_cdclk_freq);
9829                 cdclk = dev_priv->max_cdclk_freq;
9830         }
9831
9832         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9833         if (!intel_state->active_crtcs)
9834                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9835
9836         return 0;
9837 }
9838
9839 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9840 {
9841         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9842         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9843         unsigned int req_cdclk = intel_state->dev_cdclk;
9844         unsigned int req_vco = intel_state->cdclk_pll_vco;
9845
9846         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9847 }
9848
9849 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9850                                       struct intel_crtc_state *crtc_state)
9851 {
9852         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9853                 if (!intel_ddi_pll_select(crtc, crtc_state))
9854                         return -EINVAL;
9855         }
9856
9857         crtc->lowfreq_avail = false;
9858
9859         return 0;
9860 }
9861
9862 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9863                                 enum port port,
9864                                 struct intel_crtc_state *pipe_config)
9865 {
9866         enum intel_dpll_id id;
9867
9868         switch (port) {
9869         case PORT_A:
9870                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9871                 id = DPLL_ID_SKL_DPLL0;
9872                 break;
9873         case PORT_B:
9874                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9875                 id = DPLL_ID_SKL_DPLL1;
9876                 break;
9877         case PORT_C:
9878                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9879                 id = DPLL_ID_SKL_DPLL2;
9880                 break;
9881         default:
9882                 DRM_ERROR("Incorrect port type\n");
9883                 return;
9884         }
9885
9886         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9887 }
9888
9889 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9890                                 enum port port,
9891                                 struct intel_crtc_state *pipe_config)
9892 {
9893         enum intel_dpll_id id;
9894         u32 temp;
9895
9896         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9897         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9898
9899         switch (pipe_config->ddi_pll_sel) {
9900         case SKL_DPLL0:
9901                 id = DPLL_ID_SKL_DPLL0;
9902                 break;
9903         case SKL_DPLL1:
9904                 id = DPLL_ID_SKL_DPLL1;
9905                 break;
9906         case SKL_DPLL2:
9907                 id = DPLL_ID_SKL_DPLL2;
9908                 break;
9909         case SKL_DPLL3:
9910                 id = DPLL_ID_SKL_DPLL3;
9911                 break;
9912         default:
9913                 MISSING_CASE(pipe_config->ddi_pll_sel);
9914                 return;
9915         }
9916
9917         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9918 }
9919
9920 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9921                                 enum port port,
9922                                 struct intel_crtc_state *pipe_config)
9923 {
9924         enum intel_dpll_id id;
9925
9926         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9927
9928         switch (pipe_config->ddi_pll_sel) {
9929         case PORT_CLK_SEL_WRPLL1:
9930                 id = DPLL_ID_WRPLL1;
9931                 break;
9932         case PORT_CLK_SEL_WRPLL2:
9933                 id = DPLL_ID_WRPLL2;
9934                 break;
9935         case PORT_CLK_SEL_SPLL:
9936                 id = DPLL_ID_SPLL;
9937                 break;
9938         case PORT_CLK_SEL_LCPLL_810:
9939                 id = DPLL_ID_LCPLL_810;
9940                 break;
9941         case PORT_CLK_SEL_LCPLL_1350:
9942                 id = DPLL_ID_LCPLL_1350;
9943                 break;
9944         case PORT_CLK_SEL_LCPLL_2700:
9945                 id = DPLL_ID_LCPLL_2700;
9946                 break;
9947         default:
9948                 MISSING_CASE(pipe_config->ddi_pll_sel);
9949                 /* fall through */
9950         case PORT_CLK_SEL_NONE:
9951                 return;
9952         }
9953
9954         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9955 }
9956
9957 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9958                                      struct intel_crtc_state *pipe_config,
9959                                      unsigned long *power_domain_mask)
9960 {
9961         struct drm_device *dev = crtc->base.dev;
9962         struct drm_i915_private *dev_priv = to_i915(dev);
9963         enum intel_display_power_domain power_domain;
9964         u32 tmp;
9965
9966         /*
9967          * The pipe->transcoder mapping is fixed with the exception of the eDP
9968          * transcoder handled below.
9969          */
9970         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9971
9972         /*
9973          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9974          * consistency and less surprising code; it's in always on power).
9975          */
9976         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9977         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9978                 enum pipe trans_edp_pipe;
9979                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9980                 default:
9981                         WARN(1, "unknown pipe linked to edp transcoder\n");
9982                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9983                 case TRANS_DDI_EDP_INPUT_A_ON:
9984                         trans_edp_pipe = PIPE_A;
9985                         break;
9986                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9987                         trans_edp_pipe = PIPE_B;
9988                         break;
9989                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9990                         trans_edp_pipe = PIPE_C;
9991                         break;
9992                 }
9993
9994                 if (trans_edp_pipe == crtc->pipe)
9995                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9996         }
9997
9998         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9999         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10000                 return false;
10001         *power_domain_mask |= BIT(power_domain);
10002
10003         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10004
10005         return tmp & PIPECONF_ENABLE;
10006 }
10007
10008 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10009                                          struct intel_crtc_state *pipe_config,
10010                                          unsigned long *power_domain_mask)
10011 {
10012         struct drm_device *dev = crtc->base.dev;
10013         struct drm_i915_private *dev_priv = to_i915(dev);
10014         enum intel_display_power_domain power_domain;
10015         enum port port;
10016         enum transcoder cpu_transcoder;
10017         u32 tmp;
10018
10019         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10020                 if (port == PORT_A)
10021                         cpu_transcoder = TRANSCODER_DSI_A;
10022                 else
10023                         cpu_transcoder = TRANSCODER_DSI_C;
10024
10025                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10026                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10027                         continue;
10028                 *power_domain_mask |= BIT(power_domain);
10029
10030                 /*
10031                  * The PLL needs to be enabled with a valid divider
10032                  * configuration, otherwise accessing DSI registers will hang
10033                  * the machine. See BSpec North Display Engine
10034                  * registers/MIPI[BXT]. We can break out here early, since we
10035                  * need the same DSI PLL to be enabled for both DSI ports.
10036                  */
10037                 if (!intel_dsi_pll_is_enabled(dev_priv))
10038                         break;
10039
10040                 /* XXX: this works for video mode only */
10041                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10042                 if (!(tmp & DPI_ENABLE))
10043                         continue;
10044
10045                 tmp = I915_READ(MIPI_CTRL(port));
10046                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10047                         continue;
10048
10049                 pipe_config->cpu_transcoder = cpu_transcoder;
10050                 break;
10051         }
10052
10053         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10054 }
10055
10056 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10057                                        struct intel_crtc_state *pipe_config)
10058 {
10059         struct drm_device *dev = crtc->base.dev;
10060         struct drm_i915_private *dev_priv = to_i915(dev);
10061         struct intel_shared_dpll *pll;
10062         enum port port;
10063         uint32_t tmp;
10064
10065         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10066
10067         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10068
10069         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10070                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10071         else if (IS_BROXTON(dev))
10072                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10073         else
10074                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10075
10076         pll = pipe_config->shared_dpll;
10077         if (pll) {
10078                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10079                                                  &pipe_config->dpll_hw_state));
10080         }
10081
10082         /*
10083          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10084          * DDI E. So just check whether this pipe is wired to DDI E and whether
10085          * the PCH transcoder is on.
10086          */
10087         if (INTEL_INFO(dev)->gen < 9 &&
10088             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10089                 pipe_config->has_pch_encoder = true;
10090
10091                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10092                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10093                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10094
10095                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10096         }
10097 }
10098
10099 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10100                                     struct intel_crtc_state *pipe_config)
10101 {
10102         struct drm_device *dev = crtc->base.dev;
10103         struct drm_i915_private *dev_priv = to_i915(dev);
10104         enum intel_display_power_domain power_domain;
10105         unsigned long power_domain_mask;
10106         bool active;
10107
10108         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10109         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10110                 return false;
10111         power_domain_mask = BIT(power_domain);
10112
10113         pipe_config->shared_dpll = NULL;
10114
10115         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10116
10117         if (IS_BROXTON(dev_priv) &&
10118             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10119                 WARN_ON(active);
10120                 active = true;
10121         }
10122
10123         if (!active)
10124                 goto out;
10125
10126         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10127                 haswell_get_ddi_port_state(crtc, pipe_config);
10128                 intel_get_pipe_timings(crtc, pipe_config);
10129         }
10130
10131         intel_get_pipe_src_size(crtc, pipe_config);
10132
10133         pipe_config->gamma_mode =
10134                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10135
10136         if (INTEL_INFO(dev)->gen >= 9) {
10137                 skl_init_scalers(dev, crtc, pipe_config);
10138         }
10139
10140         if (INTEL_INFO(dev)->gen >= 9) {
10141                 pipe_config->scaler_state.scaler_id = -1;
10142                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10143         }
10144
10145         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10146         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10147                 power_domain_mask |= BIT(power_domain);
10148                 if (INTEL_INFO(dev)->gen >= 9)
10149                         skylake_get_pfit_config(crtc, pipe_config);
10150                 else
10151                         ironlake_get_pfit_config(crtc, pipe_config);
10152         }
10153
10154         if (IS_HASWELL(dev))
10155                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10156                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10157
10158         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10159             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10160                 pipe_config->pixel_multiplier =
10161                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10162         } else {
10163                 pipe_config->pixel_multiplier = 1;
10164         }
10165
10166 out:
10167         for_each_power_domain(power_domain, power_domain_mask)
10168                 intel_display_power_put(dev_priv, power_domain);
10169
10170         return active;
10171 }
10172
10173 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10174                                const struct intel_plane_state *plane_state)
10175 {
10176         struct drm_device *dev = crtc->dev;
10177         struct drm_i915_private *dev_priv = to_i915(dev);
10178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10179         uint32_t cntl = 0, size = 0;
10180
10181         if (plane_state && plane_state->visible) {
10182                 unsigned int width = plane_state->base.crtc_w;
10183                 unsigned int height = plane_state->base.crtc_h;
10184                 unsigned int stride = roundup_pow_of_two(width) * 4;
10185
10186                 switch (stride) {
10187                 default:
10188                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10189                                   width, stride);
10190                         stride = 256;
10191                         /* fallthrough */
10192                 case 256:
10193                 case 512:
10194                 case 1024:
10195                 case 2048:
10196                         break;
10197                 }
10198
10199                 cntl |= CURSOR_ENABLE |
10200                         CURSOR_GAMMA_ENABLE |
10201                         CURSOR_FORMAT_ARGB |
10202                         CURSOR_STRIDE(stride);
10203
10204                 size = (height << 12) | width;
10205         }
10206
10207         if (intel_crtc->cursor_cntl != 0 &&
10208             (intel_crtc->cursor_base != base ||
10209              intel_crtc->cursor_size != size ||
10210              intel_crtc->cursor_cntl != cntl)) {
10211                 /* On these chipsets we can only modify the base/size/stride
10212                  * whilst the cursor is disabled.
10213                  */
10214                 I915_WRITE(CURCNTR(PIPE_A), 0);
10215                 POSTING_READ(CURCNTR(PIPE_A));
10216                 intel_crtc->cursor_cntl = 0;
10217         }
10218
10219         if (intel_crtc->cursor_base != base) {
10220                 I915_WRITE(CURBASE(PIPE_A), base);
10221                 intel_crtc->cursor_base = base;
10222         }
10223
10224         if (intel_crtc->cursor_size != size) {
10225                 I915_WRITE(CURSIZE, size);
10226                 intel_crtc->cursor_size = size;
10227         }
10228
10229         if (intel_crtc->cursor_cntl != cntl) {
10230                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10231                 POSTING_READ(CURCNTR(PIPE_A));
10232                 intel_crtc->cursor_cntl = cntl;
10233         }
10234 }
10235
10236 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10237                                const struct intel_plane_state *plane_state)
10238 {
10239         struct drm_device *dev = crtc->dev;
10240         struct drm_i915_private *dev_priv = to_i915(dev);
10241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10242         int pipe = intel_crtc->pipe;
10243         uint32_t cntl = 0;
10244
10245         if (plane_state && plane_state->visible) {
10246                 cntl = MCURSOR_GAMMA_ENABLE;
10247                 switch (plane_state->base.crtc_w) {
10248                         case 64:
10249                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10250                                 break;
10251                         case 128:
10252                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10253                                 break;
10254                         case 256:
10255                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10256                                 break;
10257                         default:
10258                                 MISSING_CASE(plane_state->base.crtc_w);
10259                                 return;
10260                 }
10261                 cntl |= pipe << 28; /* Connect to correct pipe */
10262
10263                 if (HAS_DDI(dev))
10264                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10265
10266                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10267                         cntl |= CURSOR_ROTATE_180;
10268         }
10269
10270         if (intel_crtc->cursor_cntl != cntl) {
10271                 I915_WRITE(CURCNTR(pipe), cntl);
10272                 POSTING_READ(CURCNTR(pipe));
10273                 intel_crtc->cursor_cntl = cntl;
10274         }
10275
10276         /* and commit changes on next vblank */
10277         I915_WRITE(CURBASE(pipe), base);
10278         POSTING_READ(CURBASE(pipe));
10279
10280         intel_crtc->cursor_base = base;
10281 }
10282
10283 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10284 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10285                                      const struct intel_plane_state *plane_state)
10286 {
10287         struct drm_device *dev = crtc->dev;
10288         struct drm_i915_private *dev_priv = to_i915(dev);
10289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10290         int pipe = intel_crtc->pipe;
10291         u32 base = intel_crtc->cursor_addr;
10292         u32 pos = 0;
10293
10294         if (plane_state) {
10295                 int x = plane_state->base.crtc_x;
10296                 int y = plane_state->base.crtc_y;
10297
10298                 if (x < 0) {
10299                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10300                         x = -x;
10301                 }
10302                 pos |= x << CURSOR_X_SHIFT;
10303
10304                 if (y < 0) {
10305                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10306                         y = -y;
10307                 }
10308                 pos |= y << CURSOR_Y_SHIFT;
10309
10310                 /* ILK+ do this automagically */
10311                 if (HAS_GMCH_DISPLAY(dev) &&
10312                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10313                         base += (plane_state->base.crtc_h *
10314                                  plane_state->base.crtc_w - 1) * 4;
10315                 }
10316         }
10317
10318         I915_WRITE(CURPOS(pipe), pos);
10319
10320         if (IS_845G(dev) || IS_I865G(dev))
10321                 i845_update_cursor(crtc, base, plane_state);
10322         else
10323                 i9xx_update_cursor(crtc, base, plane_state);
10324 }
10325
10326 static bool cursor_size_ok(struct drm_device *dev,
10327                            uint32_t width, uint32_t height)
10328 {
10329         if (width == 0 || height == 0)
10330                 return false;
10331
10332         /*
10333          * 845g/865g are special in that they are only limited by
10334          * the width of their cursors, the height is arbitrary up to
10335          * the precision of the register. Everything else requires
10336          * square cursors, limited to a few power-of-two sizes.
10337          */
10338         if (IS_845G(dev) || IS_I865G(dev)) {
10339                 if ((width & 63) != 0)
10340                         return false;
10341
10342                 if (width > (IS_845G(dev) ? 64 : 512))
10343                         return false;
10344
10345                 if (height > 1023)
10346                         return false;
10347         } else {
10348                 switch (width | height) {
10349                 case 256:
10350                 case 128:
10351                         if (IS_GEN2(dev))
10352                                 return false;
10353                 case 64:
10354                         break;
10355                 default:
10356                         return false;
10357                 }
10358         }
10359
10360         return true;
10361 }
10362
10363 /* VESA 640x480x72Hz mode to set on the pipe */
10364 static struct drm_display_mode load_detect_mode = {
10365         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10366                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10367 };
10368
10369 struct drm_framebuffer *
10370 __intel_framebuffer_create(struct drm_device *dev,
10371                            struct drm_mode_fb_cmd2 *mode_cmd,
10372                            struct drm_i915_gem_object *obj)
10373 {
10374         struct intel_framebuffer *intel_fb;
10375         int ret;
10376
10377         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10378         if (!intel_fb)
10379                 return ERR_PTR(-ENOMEM);
10380
10381         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10382         if (ret)
10383                 goto err;
10384
10385         return &intel_fb->base;
10386
10387 err:
10388         kfree(intel_fb);
10389         return ERR_PTR(ret);
10390 }
10391
10392 static struct drm_framebuffer *
10393 intel_framebuffer_create(struct drm_device *dev,
10394                          struct drm_mode_fb_cmd2 *mode_cmd,
10395                          struct drm_i915_gem_object *obj)
10396 {
10397         struct drm_framebuffer *fb;
10398         int ret;
10399
10400         ret = i915_mutex_lock_interruptible(dev);
10401         if (ret)
10402                 return ERR_PTR(ret);
10403         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10404         mutex_unlock(&dev->struct_mutex);
10405
10406         return fb;
10407 }
10408
10409 static u32
10410 intel_framebuffer_pitch_for_width(int width, int bpp)
10411 {
10412         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10413         return ALIGN(pitch, 64);
10414 }
10415
10416 static u32
10417 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10418 {
10419         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10420         return PAGE_ALIGN(pitch * mode->vdisplay);
10421 }
10422
10423 static struct drm_framebuffer *
10424 intel_framebuffer_create_for_mode(struct drm_device *dev,
10425                                   struct drm_display_mode *mode,
10426                                   int depth, int bpp)
10427 {
10428         struct drm_framebuffer *fb;
10429         struct drm_i915_gem_object *obj;
10430         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10431
10432         obj = i915_gem_object_create(dev,
10433                                     intel_framebuffer_size_for_mode(mode, bpp));
10434         if (IS_ERR(obj))
10435                 return ERR_CAST(obj);
10436
10437         mode_cmd.width = mode->hdisplay;
10438         mode_cmd.height = mode->vdisplay;
10439         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10440                                                                 bpp);
10441         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10442
10443         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10444         if (IS_ERR(fb))
10445                 drm_gem_object_unreference_unlocked(&obj->base);
10446
10447         return fb;
10448 }
10449
10450 static struct drm_framebuffer *
10451 mode_fits_in_fbdev(struct drm_device *dev,
10452                    struct drm_display_mode *mode)
10453 {
10454 #ifdef CONFIG_DRM_FBDEV_EMULATION
10455         struct drm_i915_private *dev_priv = to_i915(dev);
10456         struct drm_i915_gem_object *obj;
10457         struct drm_framebuffer *fb;
10458
10459         if (!dev_priv->fbdev)
10460                 return NULL;
10461
10462         if (!dev_priv->fbdev->fb)
10463                 return NULL;
10464
10465         obj = dev_priv->fbdev->fb->obj;
10466         BUG_ON(!obj);
10467
10468         fb = &dev_priv->fbdev->fb->base;
10469         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10470                                                                fb->bits_per_pixel))
10471                 return NULL;
10472
10473         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10474                 return NULL;
10475
10476         drm_framebuffer_reference(fb);
10477         return fb;
10478 #else
10479         return NULL;
10480 #endif
10481 }
10482
10483 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10484                                            struct drm_crtc *crtc,
10485                                            struct drm_display_mode *mode,
10486                                            struct drm_framebuffer *fb,
10487                                            int x, int y)
10488 {
10489         struct drm_plane_state *plane_state;
10490         int hdisplay, vdisplay;
10491         int ret;
10492
10493         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10494         if (IS_ERR(plane_state))
10495                 return PTR_ERR(plane_state);
10496
10497         if (mode)
10498                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10499         else
10500                 hdisplay = vdisplay = 0;
10501
10502         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10503         if (ret)
10504                 return ret;
10505         drm_atomic_set_fb_for_plane(plane_state, fb);
10506         plane_state->crtc_x = 0;
10507         plane_state->crtc_y = 0;
10508         plane_state->crtc_w = hdisplay;
10509         plane_state->crtc_h = vdisplay;
10510         plane_state->src_x = x << 16;
10511         plane_state->src_y = y << 16;
10512         plane_state->src_w = hdisplay << 16;
10513         plane_state->src_h = vdisplay << 16;
10514
10515         return 0;
10516 }
10517
10518 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10519                                 struct drm_display_mode *mode,
10520                                 struct intel_load_detect_pipe *old,
10521                                 struct drm_modeset_acquire_ctx *ctx)
10522 {
10523         struct intel_crtc *intel_crtc;
10524         struct intel_encoder *intel_encoder =
10525                 intel_attached_encoder(connector);
10526         struct drm_crtc *possible_crtc;
10527         struct drm_encoder *encoder = &intel_encoder->base;
10528         struct drm_crtc *crtc = NULL;
10529         struct drm_device *dev = encoder->dev;
10530         struct drm_framebuffer *fb;
10531         struct drm_mode_config *config = &dev->mode_config;
10532         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10533         struct drm_connector_state *connector_state;
10534         struct intel_crtc_state *crtc_state;
10535         int ret, i = -1;
10536
10537         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10538                       connector->base.id, connector->name,
10539                       encoder->base.id, encoder->name);
10540
10541         old->restore_state = NULL;
10542
10543 retry:
10544         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10545         if (ret)
10546                 goto fail;
10547
10548         /*
10549          * Algorithm gets a little messy:
10550          *
10551          *   - if the connector already has an assigned crtc, use it (but make
10552          *     sure it's on first)
10553          *
10554          *   - try to find the first unused crtc that can drive this connector,
10555          *     and use that if we find one
10556          */
10557
10558         /* See if we already have a CRTC for this connector */
10559         if (connector->state->crtc) {
10560                 crtc = connector->state->crtc;
10561
10562                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10563                 if (ret)
10564                         goto fail;
10565
10566                 /* Make sure the crtc and connector are running */
10567                 goto found;
10568         }
10569
10570         /* Find an unused one (if possible) */
10571         for_each_crtc(dev, possible_crtc) {
10572                 i++;
10573                 if (!(encoder->possible_crtcs & (1 << i)))
10574                         continue;
10575
10576                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10577                 if (ret)
10578                         goto fail;
10579
10580                 if (possible_crtc->state->enable) {
10581                         drm_modeset_unlock(&possible_crtc->mutex);
10582                         continue;
10583                 }
10584
10585                 crtc = possible_crtc;
10586                 break;
10587         }
10588
10589         /*
10590          * If we didn't find an unused CRTC, don't use any.
10591          */
10592         if (!crtc) {
10593                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10594                 goto fail;
10595         }
10596
10597 found:
10598         intel_crtc = to_intel_crtc(crtc);
10599
10600         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10601         if (ret)
10602                 goto fail;
10603
10604         state = drm_atomic_state_alloc(dev);
10605         restore_state = drm_atomic_state_alloc(dev);
10606         if (!state || !restore_state) {
10607                 ret = -ENOMEM;
10608                 goto fail;
10609         }
10610
10611         state->acquire_ctx = ctx;
10612         restore_state->acquire_ctx = ctx;
10613
10614         connector_state = drm_atomic_get_connector_state(state, connector);
10615         if (IS_ERR(connector_state)) {
10616                 ret = PTR_ERR(connector_state);
10617                 goto fail;
10618         }
10619
10620         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10621         if (ret)
10622                 goto fail;
10623
10624         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10625         if (IS_ERR(crtc_state)) {
10626                 ret = PTR_ERR(crtc_state);
10627                 goto fail;
10628         }
10629
10630         crtc_state->base.active = crtc_state->base.enable = true;
10631
10632         if (!mode)
10633                 mode = &load_detect_mode;
10634
10635         /* We need a framebuffer large enough to accommodate all accesses
10636          * that the plane may generate whilst we perform load detection.
10637          * We can not rely on the fbcon either being present (we get called
10638          * during its initialisation to detect all boot displays, or it may
10639          * not even exist) or that it is large enough to satisfy the
10640          * requested mode.
10641          */
10642         fb = mode_fits_in_fbdev(dev, mode);
10643         if (fb == NULL) {
10644                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10645                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10646         } else
10647                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10648         if (IS_ERR(fb)) {
10649                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10650                 goto fail;
10651         }
10652
10653         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10654         if (ret)
10655                 goto fail;
10656
10657         drm_framebuffer_unreference(fb);
10658
10659         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10660         if (ret)
10661                 goto fail;
10662
10663         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10664         if (!ret)
10665                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10666         if (!ret)
10667                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10668         if (ret) {
10669                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10670                 goto fail;
10671         }
10672
10673         ret = drm_atomic_commit(state);
10674         if (ret) {
10675                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10676                 goto fail;
10677         }
10678
10679         old->restore_state = restore_state;
10680
10681         /* let the connector get through one full cycle before testing */
10682         intel_wait_for_vblank(dev, intel_crtc->pipe);
10683         return true;
10684
10685 fail:
10686         drm_atomic_state_free(state);
10687         drm_atomic_state_free(restore_state);
10688         restore_state = state = NULL;
10689
10690         if (ret == -EDEADLK) {
10691                 drm_modeset_backoff(ctx);
10692                 goto retry;
10693         }
10694
10695         return false;
10696 }
10697
10698 void intel_release_load_detect_pipe(struct drm_connector *connector,
10699                                     struct intel_load_detect_pipe *old,
10700                                     struct drm_modeset_acquire_ctx *ctx)
10701 {
10702         struct intel_encoder *intel_encoder =
10703                 intel_attached_encoder(connector);
10704         struct drm_encoder *encoder = &intel_encoder->base;
10705         struct drm_atomic_state *state = old->restore_state;
10706         int ret;
10707
10708         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10709                       connector->base.id, connector->name,
10710                       encoder->base.id, encoder->name);
10711
10712         if (!state)
10713                 return;
10714
10715         ret = drm_atomic_commit(state);
10716         if (ret) {
10717                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10718                 drm_atomic_state_free(state);
10719         }
10720 }
10721
10722 static int i9xx_pll_refclk(struct drm_device *dev,
10723                            const struct intel_crtc_state *pipe_config)
10724 {
10725         struct drm_i915_private *dev_priv = to_i915(dev);
10726         u32 dpll = pipe_config->dpll_hw_state.dpll;
10727
10728         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10729                 return dev_priv->vbt.lvds_ssc_freq;
10730         else if (HAS_PCH_SPLIT(dev))
10731                 return 120000;
10732         else if (!IS_GEN2(dev))
10733                 return 96000;
10734         else
10735                 return 48000;
10736 }
10737
10738 /* Returns the clock of the currently programmed mode of the given pipe. */
10739 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10740                                 struct intel_crtc_state *pipe_config)
10741 {
10742         struct drm_device *dev = crtc->base.dev;
10743         struct drm_i915_private *dev_priv = to_i915(dev);
10744         int pipe = pipe_config->cpu_transcoder;
10745         u32 dpll = pipe_config->dpll_hw_state.dpll;
10746         u32 fp;
10747         struct dpll clock;
10748         int port_clock;
10749         int refclk = i9xx_pll_refclk(dev, pipe_config);
10750
10751         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10752                 fp = pipe_config->dpll_hw_state.fp0;
10753         else
10754                 fp = pipe_config->dpll_hw_state.fp1;
10755
10756         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10757         if (IS_PINEVIEW(dev)) {
10758                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10759                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10760         } else {
10761                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10762                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10763         }
10764
10765         if (!IS_GEN2(dev)) {
10766                 if (IS_PINEVIEW(dev))
10767                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10768                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10769                 else
10770                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10771                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10772
10773                 switch (dpll & DPLL_MODE_MASK) {
10774                 case DPLLB_MODE_DAC_SERIAL:
10775                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10776                                 5 : 10;
10777                         break;
10778                 case DPLLB_MODE_LVDS:
10779                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10780                                 7 : 14;
10781                         break;
10782                 default:
10783                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10784                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10785                         return;
10786                 }
10787
10788                 if (IS_PINEVIEW(dev))
10789                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10790                 else
10791                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10792         } else {
10793                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10794                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10795
10796                 if (is_lvds) {
10797                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10798                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10799
10800                         if (lvds & LVDS_CLKB_POWER_UP)
10801                                 clock.p2 = 7;
10802                         else
10803                                 clock.p2 = 14;
10804                 } else {
10805                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10806                                 clock.p1 = 2;
10807                         else {
10808                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10809                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10810                         }
10811                         if (dpll & PLL_P2_DIVIDE_BY_4)
10812                                 clock.p2 = 4;
10813                         else
10814                                 clock.p2 = 2;
10815                 }
10816
10817                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10818         }
10819
10820         /*
10821          * This value includes pixel_multiplier. We will use
10822          * port_clock to compute adjusted_mode.crtc_clock in the
10823          * encoder's get_config() function.
10824          */
10825         pipe_config->port_clock = port_clock;
10826 }
10827
10828 int intel_dotclock_calculate(int link_freq,
10829                              const struct intel_link_m_n *m_n)
10830 {
10831         /*
10832          * The calculation for the data clock is:
10833          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10834          * But we want to avoid losing precison if possible, so:
10835          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10836          *
10837          * and the link clock is simpler:
10838          * link_clock = (m * link_clock) / n
10839          */
10840
10841         if (!m_n->link_n)
10842                 return 0;
10843
10844         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10845 }
10846
10847 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10848                                    struct intel_crtc_state *pipe_config)
10849 {
10850         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10851
10852         /* read out port_clock from the DPLL */
10853         i9xx_crtc_clock_get(crtc, pipe_config);
10854
10855         /*
10856          * In case there is an active pipe without active ports,
10857          * we may need some idea for the dotclock anyway.
10858          * Calculate one based on the FDI configuration.
10859          */
10860         pipe_config->base.adjusted_mode.crtc_clock =
10861                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10862                                          &pipe_config->fdi_m_n);
10863 }
10864
10865 /** Returns the currently programmed mode of the given pipe. */
10866 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10867                                              struct drm_crtc *crtc)
10868 {
10869         struct drm_i915_private *dev_priv = to_i915(dev);
10870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10871         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10872         struct drm_display_mode *mode;
10873         struct intel_crtc_state *pipe_config;
10874         int htot = I915_READ(HTOTAL(cpu_transcoder));
10875         int hsync = I915_READ(HSYNC(cpu_transcoder));
10876         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10877         int vsync = I915_READ(VSYNC(cpu_transcoder));
10878         enum pipe pipe = intel_crtc->pipe;
10879
10880         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10881         if (!mode)
10882                 return NULL;
10883
10884         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10885         if (!pipe_config) {
10886                 kfree(mode);
10887                 return NULL;
10888         }
10889
10890         /*
10891          * Construct a pipe_config sufficient for getting the clock info
10892          * back out of crtc_clock_get.
10893          *
10894          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10895          * to use a real value here instead.
10896          */
10897         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10898         pipe_config->pixel_multiplier = 1;
10899         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10900         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10901         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10902         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10903
10904         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10905         mode->hdisplay = (htot & 0xffff) + 1;
10906         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10907         mode->hsync_start = (hsync & 0xffff) + 1;
10908         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10909         mode->vdisplay = (vtot & 0xffff) + 1;
10910         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10911         mode->vsync_start = (vsync & 0xffff) + 1;
10912         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10913
10914         drm_mode_set_name(mode);
10915
10916         kfree(pipe_config);
10917
10918         return mode;
10919 }
10920
10921 static void intel_crtc_destroy(struct drm_crtc *crtc)
10922 {
10923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10924         struct drm_device *dev = crtc->dev;
10925         struct intel_flip_work *work;
10926
10927         spin_lock_irq(&dev->event_lock);
10928         work = intel_crtc->flip_work;
10929         intel_crtc->flip_work = NULL;
10930         spin_unlock_irq(&dev->event_lock);
10931
10932         if (work) {
10933                 cancel_work_sync(&work->mmio_work);
10934                 cancel_work_sync(&work->unpin_work);
10935                 kfree(work);
10936         }
10937
10938         drm_crtc_cleanup(crtc);
10939
10940         kfree(intel_crtc);
10941 }
10942
10943 static void intel_unpin_work_fn(struct work_struct *__work)
10944 {
10945         struct intel_flip_work *work =
10946                 container_of(__work, struct intel_flip_work, unpin_work);
10947         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10948         struct drm_device *dev = crtc->base.dev;
10949         struct drm_plane *primary = crtc->base.primary;
10950
10951         if (is_mmio_work(work))
10952                 flush_work(&work->mmio_work);
10953
10954         mutex_lock(&dev->struct_mutex);
10955         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10956         drm_gem_object_unreference(&work->pending_flip_obj->base);
10957
10958         if (work->flip_queued_req)
10959                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10960         mutex_unlock(&dev->struct_mutex);
10961
10962         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10963         intel_fbc_post_update(crtc);
10964         drm_framebuffer_unreference(work->old_fb);
10965
10966         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10967         atomic_dec(&crtc->unpin_work_count);
10968
10969         kfree(work);
10970 }
10971
10972 /* Is 'a' after or equal to 'b'? */
10973 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10974 {
10975         return !((a - b) & 0x80000000);
10976 }
10977
10978 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10979                                    struct intel_flip_work *work)
10980 {
10981         struct drm_device *dev = crtc->base.dev;
10982         struct drm_i915_private *dev_priv = to_i915(dev);
10983         unsigned reset_counter;
10984
10985         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10986         if (crtc->reset_counter != reset_counter)
10987                 return true;
10988
10989         /*
10990          * The relevant registers doen't exist on pre-ctg.
10991          * As the flip done interrupt doesn't trigger for mmio
10992          * flips on gmch platforms, a flip count check isn't
10993          * really needed there. But since ctg has the registers,
10994          * include it in the check anyway.
10995          */
10996         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10997                 return true;
10998
10999         /*
11000          * BDW signals flip done immediately if the plane
11001          * is disabled, even if the plane enable is already
11002          * armed to occur at the next vblank :(
11003          */
11004
11005         /*
11006          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11007          * used the same base address. In that case the mmio flip might
11008          * have completed, but the CS hasn't even executed the flip yet.
11009          *
11010          * A flip count check isn't enough as the CS might have updated
11011          * the base address just after start of vblank, but before we
11012          * managed to process the interrupt. This means we'd complete the
11013          * CS flip too soon.
11014          *
11015          * Combining both checks should get us a good enough result. It may
11016          * still happen that the CS flip has been executed, but has not
11017          * yet actually completed. But in case the base address is the same
11018          * anyway, we don't really care.
11019          */
11020         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11021                 crtc->flip_work->gtt_offset &&
11022                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11023                                     crtc->flip_work->flip_count);
11024 }
11025
11026 static bool
11027 __pageflip_finished_mmio(struct intel_crtc *crtc,
11028                                struct intel_flip_work *work)
11029 {
11030         /*
11031          * MMIO work completes when vblank is different from
11032          * flip_queued_vblank.
11033          *
11034          * Reset counter value doesn't matter, this is handled by
11035          * i915_wait_request finishing early, so no need to handle
11036          * reset here.
11037          */
11038         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11039 }
11040
11041
11042 static bool pageflip_finished(struct intel_crtc *crtc,
11043                               struct intel_flip_work *work)
11044 {
11045         if (!atomic_read(&work->pending))
11046                 return false;
11047
11048         smp_rmb();
11049
11050         if (is_mmio_work(work))
11051                 return __pageflip_finished_mmio(crtc, work);
11052         else
11053                 return __pageflip_finished_cs(crtc, work);
11054 }
11055
11056 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11057 {
11058         struct drm_device *dev = &dev_priv->drm;
11059         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11061         struct intel_flip_work *work;
11062         unsigned long flags;
11063
11064         /* Ignore early vblank irqs */
11065         if (!crtc)
11066                 return;
11067
11068         /*
11069          * This is called both by irq handlers and the reset code (to complete
11070          * lost pageflips) so needs the full irqsave spinlocks.
11071          */
11072         spin_lock_irqsave(&dev->event_lock, flags);
11073         work = intel_crtc->flip_work;
11074
11075         if (work != NULL &&
11076             !is_mmio_work(work) &&
11077             pageflip_finished(intel_crtc, work))
11078                 page_flip_completed(intel_crtc);
11079
11080         spin_unlock_irqrestore(&dev->event_lock, flags);
11081 }
11082
11083 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11084 {
11085         struct drm_device *dev = &dev_priv->drm;
11086         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11088         struct intel_flip_work *work;
11089         unsigned long flags;
11090
11091         /* Ignore early vblank irqs */
11092         if (!crtc)
11093                 return;
11094
11095         /*
11096          * This is called both by irq handlers and the reset code (to complete
11097          * lost pageflips) so needs the full irqsave spinlocks.
11098          */
11099         spin_lock_irqsave(&dev->event_lock, flags);
11100         work = intel_crtc->flip_work;
11101
11102         if (work != NULL &&
11103             is_mmio_work(work) &&
11104             pageflip_finished(intel_crtc, work))
11105                 page_flip_completed(intel_crtc);
11106
11107         spin_unlock_irqrestore(&dev->event_lock, flags);
11108 }
11109
11110 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11111                                                struct intel_flip_work *work)
11112 {
11113         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11114
11115         /* Ensure that the work item is consistent when activating it ... */
11116         smp_mb__before_atomic();
11117         atomic_set(&work->pending, 1);
11118 }
11119
11120 static int intel_gen2_queue_flip(struct drm_device *dev,
11121                                  struct drm_crtc *crtc,
11122                                  struct drm_framebuffer *fb,
11123                                  struct drm_i915_gem_object *obj,
11124                                  struct drm_i915_gem_request *req,
11125                                  uint32_t flags)
11126 {
11127         struct intel_engine_cs *engine = req->engine;
11128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11129         u32 flip_mask;
11130         int ret;
11131
11132         ret = intel_ring_begin(req, 6);
11133         if (ret)
11134                 return ret;
11135
11136         /* Can't queue multiple flips, so wait for the previous
11137          * one to finish before executing the next.
11138          */
11139         if (intel_crtc->plane)
11140                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11141         else
11142                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11143         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11144         intel_ring_emit(engine, MI_NOOP);
11145         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11146                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11147         intel_ring_emit(engine, fb->pitches[0]);
11148         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11149         intel_ring_emit(engine, 0); /* aux display base address, unused */
11150
11151         return 0;
11152 }
11153
11154 static int intel_gen3_queue_flip(struct drm_device *dev,
11155                                  struct drm_crtc *crtc,
11156                                  struct drm_framebuffer *fb,
11157                                  struct drm_i915_gem_object *obj,
11158                                  struct drm_i915_gem_request *req,
11159                                  uint32_t flags)
11160 {
11161         struct intel_engine_cs *engine = req->engine;
11162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11163         u32 flip_mask;
11164         int ret;
11165
11166         ret = intel_ring_begin(req, 6);
11167         if (ret)
11168                 return ret;
11169
11170         if (intel_crtc->plane)
11171                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11172         else
11173                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11174         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11175         intel_ring_emit(engine, MI_NOOP);
11176         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11177                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11178         intel_ring_emit(engine, fb->pitches[0]);
11179         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11180         intel_ring_emit(engine, MI_NOOP);
11181
11182         return 0;
11183 }
11184
11185 static int intel_gen4_queue_flip(struct drm_device *dev,
11186                                  struct drm_crtc *crtc,
11187                                  struct drm_framebuffer *fb,
11188                                  struct drm_i915_gem_object *obj,
11189                                  struct drm_i915_gem_request *req,
11190                                  uint32_t flags)
11191 {
11192         struct intel_engine_cs *engine = req->engine;
11193         struct drm_i915_private *dev_priv = to_i915(dev);
11194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11195         uint32_t pf, pipesrc;
11196         int ret;
11197
11198         ret = intel_ring_begin(req, 4);
11199         if (ret)
11200                 return ret;
11201
11202         /* i965+ uses the linear or tiled offsets from the
11203          * Display Registers (which do not change across a page-flip)
11204          * so we need only reprogram the base address.
11205          */
11206         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11207                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11208         intel_ring_emit(engine, fb->pitches[0]);
11209         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11210                         obj->tiling_mode);
11211
11212         /* XXX Enabling the panel-fitter across page-flip is so far
11213          * untested on non-native modes, so ignore it for now.
11214          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11215          */
11216         pf = 0;
11217         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11218         intel_ring_emit(engine, pf | pipesrc);
11219
11220         return 0;
11221 }
11222
11223 static int intel_gen6_queue_flip(struct drm_device *dev,
11224                                  struct drm_crtc *crtc,
11225                                  struct drm_framebuffer *fb,
11226                                  struct drm_i915_gem_object *obj,
11227                                  struct drm_i915_gem_request *req,
11228                                  uint32_t flags)
11229 {
11230         struct intel_engine_cs *engine = req->engine;
11231         struct drm_i915_private *dev_priv = to_i915(dev);
11232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11233         uint32_t pf, pipesrc;
11234         int ret;
11235
11236         ret = intel_ring_begin(req, 4);
11237         if (ret)
11238                 return ret;
11239
11240         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11241                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11242         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11243         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11244
11245         /* Contrary to the suggestions in the documentation,
11246          * "Enable Panel Fitter" does not seem to be required when page
11247          * flipping with a non-native mode, and worse causes a normal
11248          * modeset to fail.
11249          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11250          */
11251         pf = 0;
11252         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11253         intel_ring_emit(engine, pf | pipesrc);
11254
11255         return 0;
11256 }
11257
11258 static int intel_gen7_queue_flip(struct drm_device *dev,
11259                                  struct drm_crtc *crtc,
11260                                  struct drm_framebuffer *fb,
11261                                  struct drm_i915_gem_object *obj,
11262                                  struct drm_i915_gem_request *req,
11263                                  uint32_t flags)
11264 {
11265         struct intel_engine_cs *engine = req->engine;
11266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11267         uint32_t plane_bit = 0;
11268         int len, ret;
11269
11270         switch (intel_crtc->plane) {
11271         case PLANE_A:
11272                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11273                 break;
11274         case PLANE_B:
11275                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11276                 break;
11277         case PLANE_C:
11278                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11279                 break;
11280         default:
11281                 WARN_ONCE(1, "unknown plane in flip command\n");
11282                 return -ENODEV;
11283         }
11284
11285         len = 4;
11286         if (engine->id == RCS) {
11287                 len += 6;
11288                 /*
11289                  * On Gen 8, SRM is now taking an extra dword to accommodate
11290                  * 48bits addresses, and we need a NOOP for the batch size to
11291                  * stay even.
11292                  */
11293                 if (IS_GEN8(dev))
11294                         len += 2;
11295         }
11296
11297         /*
11298          * BSpec MI_DISPLAY_FLIP for IVB:
11299          * "The full packet must be contained within the same cache line."
11300          *
11301          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11302          * cacheline, if we ever start emitting more commands before
11303          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11304          * then do the cacheline alignment, and finally emit the
11305          * MI_DISPLAY_FLIP.
11306          */
11307         ret = intel_ring_cacheline_align(req);
11308         if (ret)
11309                 return ret;
11310
11311         ret = intel_ring_begin(req, len);
11312         if (ret)
11313                 return ret;
11314
11315         /* Unmask the flip-done completion message. Note that the bspec says that
11316          * we should do this for both the BCS and RCS, and that we must not unmask
11317          * more than one flip event at any time (or ensure that one flip message
11318          * can be sent by waiting for flip-done prior to queueing new flips).
11319          * Experimentation says that BCS works despite DERRMR masking all
11320          * flip-done completion events and that unmasking all planes at once
11321          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11322          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11323          */
11324         if (engine->id == RCS) {
11325                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11326                 intel_ring_emit_reg(engine, DERRMR);
11327                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11328                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11329                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11330                 if (IS_GEN8(dev))
11331                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11332                                               MI_SRM_LRM_GLOBAL_GTT);
11333                 else
11334                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11335                                               MI_SRM_LRM_GLOBAL_GTT);
11336                 intel_ring_emit_reg(engine, DERRMR);
11337                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11338                 if (IS_GEN8(dev)) {
11339                         intel_ring_emit(engine, 0);
11340                         intel_ring_emit(engine, MI_NOOP);
11341                 }
11342         }
11343
11344         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11345         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11346         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11347         intel_ring_emit(engine, (MI_NOOP));
11348
11349         return 0;
11350 }
11351
11352 static bool use_mmio_flip(struct intel_engine_cs *engine,
11353                           struct drm_i915_gem_object *obj)
11354 {
11355         struct reservation_object *resv;
11356
11357         /*
11358          * This is not being used for older platforms, because
11359          * non-availability of flip done interrupt forces us to use
11360          * CS flips. Older platforms derive flip done using some clever
11361          * tricks involving the flip_pending status bits and vblank irqs.
11362          * So using MMIO flips there would disrupt this mechanism.
11363          */
11364
11365         if (engine == NULL)
11366                 return true;
11367
11368         if (INTEL_GEN(engine->i915) < 5)
11369                 return false;
11370
11371         if (i915.use_mmio_flip < 0)
11372                 return false;
11373         else if (i915.use_mmio_flip > 0)
11374                 return true;
11375         else if (i915.enable_execlists)
11376                 return true;
11377
11378         resv = i915_gem_object_get_dmabuf_resv(obj);
11379         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11380                 return true;
11381
11382         return engine != i915_gem_request_get_engine(obj->last_write_req);
11383 }
11384
11385 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11386                              unsigned int rotation,
11387                              struct intel_flip_work *work)
11388 {
11389         struct drm_device *dev = intel_crtc->base.dev;
11390         struct drm_i915_private *dev_priv = to_i915(dev);
11391         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11392         const enum pipe pipe = intel_crtc->pipe;
11393         u32 ctl, stride, tile_height;
11394
11395         ctl = I915_READ(PLANE_CTL(pipe, 0));
11396         ctl &= ~PLANE_CTL_TILED_MASK;
11397         switch (fb->modifier[0]) {
11398         case DRM_FORMAT_MOD_NONE:
11399                 break;
11400         case I915_FORMAT_MOD_X_TILED:
11401                 ctl |= PLANE_CTL_TILED_X;
11402                 break;
11403         case I915_FORMAT_MOD_Y_TILED:
11404                 ctl |= PLANE_CTL_TILED_Y;
11405                 break;
11406         case I915_FORMAT_MOD_Yf_TILED:
11407                 ctl |= PLANE_CTL_TILED_YF;
11408                 break;
11409         default:
11410                 MISSING_CASE(fb->modifier[0]);
11411         }
11412
11413         /*
11414          * The stride is either expressed as a multiple of 64 bytes chunks for
11415          * linear buffers or in number of tiles for tiled buffers.
11416          */
11417         if (intel_rotation_90_or_270(rotation)) {
11418                 /* stride = Surface height in tiles */
11419                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11420                 stride = DIV_ROUND_UP(fb->height, tile_height);
11421         } else {
11422                 stride = fb->pitches[0] /
11423                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11424                                                   fb->pixel_format);
11425         }
11426
11427         /*
11428          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11429          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11430          */
11431         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11432         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11433
11434         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11435         POSTING_READ(PLANE_SURF(pipe, 0));
11436 }
11437
11438 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11439                              struct intel_flip_work *work)
11440 {
11441         struct drm_device *dev = intel_crtc->base.dev;
11442         struct drm_i915_private *dev_priv = to_i915(dev);
11443         struct intel_framebuffer *intel_fb =
11444                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11445         struct drm_i915_gem_object *obj = intel_fb->obj;
11446         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11447         u32 dspcntr;
11448
11449         dspcntr = I915_READ(reg);
11450
11451         if (obj->tiling_mode != I915_TILING_NONE)
11452                 dspcntr |= DISPPLANE_TILED;
11453         else
11454                 dspcntr &= ~DISPPLANE_TILED;
11455
11456         I915_WRITE(reg, dspcntr);
11457
11458         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11459         POSTING_READ(DSPSURF(intel_crtc->plane));
11460 }
11461
11462 static void intel_mmio_flip_work_func(struct work_struct *w)
11463 {
11464         struct intel_flip_work *work =
11465                 container_of(w, struct intel_flip_work, mmio_work);
11466         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11467         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11468         struct intel_framebuffer *intel_fb =
11469                 to_intel_framebuffer(crtc->base.primary->fb);
11470         struct drm_i915_gem_object *obj = intel_fb->obj;
11471         struct reservation_object *resv;
11472
11473         if (work->flip_queued_req)
11474                 WARN_ON(__i915_wait_request(work->flip_queued_req,
11475                                             false, NULL,
11476                                             &dev_priv->rps.mmioflips));
11477
11478         /* For framebuffer backed by dmabuf, wait for fence */
11479         resv = i915_gem_object_get_dmabuf_resv(obj);
11480         if (resv)
11481                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11482                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11483
11484         intel_pipe_update_start(crtc);
11485
11486         if (INTEL_GEN(dev_priv) >= 9)
11487                 skl_do_mmio_flip(crtc, work->rotation, work);
11488         else
11489                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11490                 ilk_do_mmio_flip(crtc, work);
11491
11492         intel_pipe_update_end(crtc, work);
11493 }
11494
11495 static int intel_default_queue_flip(struct drm_device *dev,
11496                                     struct drm_crtc *crtc,
11497                                     struct drm_framebuffer *fb,
11498                                     struct drm_i915_gem_object *obj,
11499                                     struct drm_i915_gem_request *req,
11500                                     uint32_t flags)
11501 {
11502         return -ENODEV;
11503 }
11504
11505 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11506                                       struct intel_crtc *intel_crtc,
11507                                       struct intel_flip_work *work)
11508 {
11509         u32 addr, vblank;
11510
11511         if (!atomic_read(&work->pending))
11512                 return false;
11513
11514         smp_rmb();
11515
11516         vblank = intel_crtc_get_vblank_counter(intel_crtc);
11517         if (work->flip_ready_vblank == 0) {
11518                 if (work->flip_queued_req &&
11519                     !i915_gem_request_completed(work->flip_queued_req))
11520                         return false;
11521
11522                 work->flip_ready_vblank = vblank;
11523         }
11524
11525         if (vblank - work->flip_ready_vblank < 3)
11526                 return false;
11527
11528         /* Potential stall - if we see that the flip has happened,
11529          * assume a missed interrupt. */
11530         if (INTEL_GEN(dev_priv) >= 4)
11531                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11532         else
11533                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11534
11535         /* There is a potential issue here with a false positive after a flip
11536          * to the same address. We could address this by checking for a
11537          * non-incrementing frame counter.
11538          */
11539         return addr == work->gtt_offset;
11540 }
11541
11542 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11543 {
11544         struct drm_device *dev = &dev_priv->drm;
11545         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11547         struct intel_flip_work *work;
11548
11549         WARN_ON(!in_interrupt());
11550
11551         if (crtc == NULL)
11552                 return;
11553
11554         spin_lock(&dev->event_lock);
11555         work = intel_crtc->flip_work;
11556
11557         if (work != NULL && !is_mmio_work(work) &&
11558             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11559                 WARN_ONCE(1,
11560                           "Kicking stuck page flip: queued at %d, now %d\n",
11561                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11562                 page_flip_completed(intel_crtc);
11563                 work = NULL;
11564         }
11565
11566         if (work != NULL && !is_mmio_work(work) &&
11567             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11568                 intel_queue_rps_boost_for_request(work->flip_queued_req);
11569         spin_unlock(&dev->event_lock);
11570 }
11571
11572 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11573                                 struct drm_framebuffer *fb,
11574                                 struct drm_pending_vblank_event *event,
11575                                 uint32_t page_flip_flags)
11576 {
11577         struct drm_device *dev = crtc->dev;
11578         struct drm_i915_private *dev_priv = to_i915(dev);
11579         struct drm_framebuffer *old_fb = crtc->primary->fb;
11580         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11582         struct drm_plane *primary = crtc->primary;
11583         enum pipe pipe = intel_crtc->pipe;
11584         struct intel_flip_work *work;
11585         struct intel_engine_cs *engine;
11586         bool mmio_flip;
11587         struct drm_i915_gem_request *request = NULL;
11588         int ret;
11589
11590         /*
11591          * drm_mode_page_flip_ioctl() should already catch this, but double
11592          * check to be safe.  In the future we may enable pageflipping from
11593          * a disabled primary plane.
11594          */
11595         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11596                 return -EBUSY;
11597
11598         /* Can't change pixel format via MI display flips. */
11599         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11600                 return -EINVAL;
11601
11602         /*
11603          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11604          * Note that pitch changes could also affect these register.
11605          */
11606         if (INTEL_INFO(dev)->gen > 3 &&
11607             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11608              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11609                 return -EINVAL;
11610
11611         if (i915_terminally_wedged(&dev_priv->gpu_error))
11612                 goto out_hang;
11613
11614         work = kzalloc(sizeof(*work), GFP_KERNEL);
11615         if (work == NULL)
11616                 return -ENOMEM;
11617
11618         work->event = event;
11619         work->crtc = crtc;
11620         work->old_fb = old_fb;
11621         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11622
11623         ret = drm_crtc_vblank_get(crtc);
11624         if (ret)
11625                 goto free_work;
11626
11627         /* We borrow the event spin lock for protecting flip_work */
11628         spin_lock_irq(&dev->event_lock);
11629         if (intel_crtc->flip_work) {
11630                 /* Before declaring the flip queue wedged, check if
11631                  * the hardware completed the operation behind our backs.
11632                  */
11633                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11634                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11635                         page_flip_completed(intel_crtc);
11636                 } else {
11637                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11638                         spin_unlock_irq(&dev->event_lock);
11639
11640                         drm_crtc_vblank_put(crtc);
11641                         kfree(work);
11642                         return -EBUSY;
11643                 }
11644         }
11645         intel_crtc->flip_work = work;
11646         spin_unlock_irq(&dev->event_lock);
11647
11648         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11649                 flush_workqueue(dev_priv->wq);
11650
11651         /* Reference the objects for the scheduled work. */
11652         drm_framebuffer_reference(work->old_fb);
11653         drm_gem_object_reference(&obj->base);
11654
11655         crtc->primary->fb = fb;
11656         update_state_fb(crtc->primary);
11657
11658         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11659                              to_intel_plane_state(primary->state));
11660
11661         work->pending_flip_obj = obj;
11662
11663         ret = i915_mutex_lock_interruptible(dev);
11664         if (ret)
11665                 goto cleanup;
11666
11667         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11668         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11669                 ret = -EIO;
11670                 goto cleanup;
11671         }
11672
11673         atomic_inc(&intel_crtc->unpin_work_count);
11674
11675         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11676                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11677
11678         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11679                 engine = &dev_priv->engine[BCS];
11680                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11681                         /* vlv: DISPLAY_FLIP fails to change tiling */
11682                         engine = NULL;
11683         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11684                 engine = &dev_priv->engine[BCS];
11685         } else if (INTEL_INFO(dev)->gen >= 7) {
11686                 engine = i915_gem_request_get_engine(obj->last_write_req);
11687                 if (engine == NULL || engine->id != RCS)
11688                         engine = &dev_priv->engine[BCS];
11689         } else {
11690                 engine = &dev_priv->engine[RCS];
11691         }
11692
11693         mmio_flip = use_mmio_flip(engine, obj);
11694
11695         /* When using CS flips, we want to emit semaphores between rings.
11696          * However, when using mmio flips we will create a task to do the
11697          * synchronisation, so all we want here is to pin the framebuffer
11698          * into the display plane and skip any waits.
11699          */
11700         if (!mmio_flip) {
11701                 ret = i915_gem_object_sync(obj, engine, &request);
11702                 if (!ret && !request) {
11703                         request = i915_gem_request_alloc(engine, NULL);
11704                         ret = PTR_ERR_OR_ZERO(request);
11705                 }
11706
11707                 if (ret)
11708                         goto cleanup_pending;
11709         }
11710
11711         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11712         if (ret)
11713                 goto cleanup_pending;
11714
11715         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11716                                                   obj, 0);
11717         work->gtt_offset += intel_crtc->dspaddr_offset;
11718         work->rotation = crtc->primary->state->rotation;
11719
11720         if (mmio_flip) {
11721                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11722
11723                 i915_gem_request_assign(&work->flip_queued_req,
11724                                         obj->last_write_req);
11725
11726                 schedule_work(&work->mmio_work);
11727         } else {
11728                 i915_gem_request_assign(&work->flip_queued_req, request);
11729                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11730                                                    page_flip_flags);
11731                 if (ret)
11732                         goto cleanup_unpin;
11733
11734                 intel_mark_page_flip_active(intel_crtc, work);
11735
11736                 i915_add_request_no_flush(request);
11737         }
11738
11739         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11740                           to_intel_plane(primary)->frontbuffer_bit);
11741         mutex_unlock(&dev->struct_mutex);
11742
11743         intel_frontbuffer_flip_prepare(dev,
11744                                        to_intel_plane(primary)->frontbuffer_bit);
11745
11746         trace_i915_flip_request(intel_crtc->plane, obj);
11747
11748         return 0;
11749
11750 cleanup_unpin:
11751         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11752 cleanup_pending:
11753         if (!IS_ERR_OR_NULL(request))
11754                 i915_add_request_no_flush(request);
11755         atomic_dec(&intel_crtc->unpin_work_count);
11756         mutex_unlock(&dev->struct_mutex);
11757 cleanup:
11758         crtc->primary->fb = old_fb;
11759         update_state_fb(crtc->primary);
11760
11761         drm_gem_object_unreference_unlocked(&obj->base);
11762         drm_framebuffer_unreference(work->old_fb);
11763
11764         spin_lock_irq(&dev->event_lock);
11765         intel_crtc->flip_work = NULL;
11766         spin_unlock_irq(&dev->event_lock);
11767
11768         drm_crtc_vblank_put(crtc);
11769 free_work:
11770         kfree(work);
11771
11772         if (ret == -EIO) {
11773                 struct drm_atomic_state *state;
11774                 struct drm_plane_state *plane_state;
11775
11776 out_hang:
11777                 state = drm_atomic_state_alloc(dev);
11778                 if (!state)
11779                         return -ENOMEM;
11780                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11781
11782 retry:
11783                 plane_state = drm_atomic_get_plane_state(state, primary);
11784                 ret = PTR_ERR_OR_ZERO(plane_state);
11785                 if (!ret) {
11786                         drm_atomic_set_fb_for_plane(plane_state, fb);
11787
11788                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11789                         if (!ret)
11790                                 ret = drm_atomic_commit(state);
11791                 }
11792
11793                 if (ret == -EDEADLK) {
11794                         drm_modeset_backoff(state->acquire_ctx);
11795                         drm_atomic_state_clear(state);
11796                         goto retry;
11797                 }
11798
11799                 if (ret)
11800                         drm_atomic_state_free(state);
11801
11802                 if (ret == 0 && event) {
11803                         spin_lock_irq(&dev->event_lock);
11804                         drm_crtc_send_vblank_event(crtc, event);
11805                         spin_unlock_irq(&dev->event_lock);
11806                 }
11807         }
11808         return ret;
11809 }
11810
11811
11812 /**
11813  * intel_wm_need_update - Check whether watermarks need updating
11814  * @plane: drm plane
11815  * @state: new plane state
11816  *
11817  * Check current plane state versus the new one to determine whether
11818  * watermarks need to be recalculated.
11819  *
11820  * Returns true or false.
11821  */
11822 static bool intel_wm_need_update(struct drm_plane *plane,
11823                                  struct drm_plane_state *state)
11824 {
11825         struct intel_plane_state *new = to_intel_plane_state(state);
11826         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11827
11828         /* Update watermarks on tiling or size changes. */
11829         if (new->visible != cur->visible)
11830                 return true;
11831
11832         if (!cur->base.fb || !new->base.fb)
11833                 return false;
11834
11835         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11836             cur->base.rotation != new->base.rotation ||
11837             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11838             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11839             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11840             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11841                 return true;
11842
11843         return false;
11844 }
11845
11846 static bool needs_scaling(struct intel_plane_state *state)
11847 {
11848         int src_w = drm_rect_width(&state->src) >> 16;
11849         int src_h = drm_rect_height(&state->src) >> 16;
11850         int dst_w = drm_rect_width(&state->dst);
11851         int dst_h = drm_rect_height(&state->dst);
11852
11853         return (src_w != dst_w || src_h != dst_h);
11854 }
11855
11856 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11857                                     struct drm_plane_state *plane_state)
11858 {
11859         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11860         struct drm_crtc *crtc = crtc_state->crtc;
11861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11862         struct drm_plane *plane = plane_state->plane;
11863         struct drm_device *dev = crtc->dev;
11864         struct drm_i915_private *dev_priv = to_i915(dev);
11865         struct intel_plane_state *old_plane_state =
11866                 to_intel_plane_state(plane->state);
11867         bool mode_changed = needs_modeset(crtc_state);
11868         bool was_crtc_enabled = crtc->state->active;
11869         bool is_crtc_enabled = crtc_state->active;
11870         bool turn_off, turn_on, visible, was_visible;
11871         struct drm_framebuffer *fb = plane_state->fb;
11872         int ret;
11873
11874         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
11875                 ret = skl_update_scaler_plane(
11876                         to_intel_crtc_state(crtc_state),
11877                         to_intel_plane_state(plane_state));
11878                 if (ret)
11879                         return ret;
11880         }
11881
11882         was_visible = old_plane_state->visible;
11883         visible = to_intel_plane_state(plane_state)->visible;
11884
11885         if (!was_crtc_enabled && WARN_ON(was_visible))
11886                 was_visible = false;
11887
11888         /*
11889          * Visibility is calculated as if the crtc was on, but
11890          * after scaler setup everything depends on it being off
11891          * when the crtc isn't active.
11892          *
11893          * FIXME this is wrong for watermarks. Watermarks should also
11894          * be computed as if the pipe would be active. Perhaps move
11895          * per-plane wm computation to the .check_plane() hook, and
11896          * only combine the results from all planes in the current place?
11897          */
11898         if (!is_crtc_enabled)
11899                 to_intel_plane_state(plane_state)->visible = visible = false;
11900
11901         if (!was_visible && !visible)
11902                 return 0;
11903
11904         if (fb != old_plane_state->base.fb)
11905                 pipe_config->fb_changed = true;
11906
11907         turn_off = was_visible && (!visible || mode_changed);
11908         turn_on = visible && (!was_visible || mode_changed);
11909
11910         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11911                          intel_crtc->base.base.id,
11912                          intel_crtc->base.name,
11913                          plane->base.id, plane->name,
11914                          fb ? fb->base.id : -1);
11915
11916         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11917                          plane->base.id, plane->name,
11918                          was_visible, visible,
11919                          turn_off, turn_on, mode_changed);
11920
11921         if (turn_on) {
11922                 pipe_config->update_wm_pre = true;
11923
11924                 /* must disable cxsr around plane enable/disable */
11925                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11926                         pipe_config->disable_cxsr = true;
11927         } else if (turn_off) {
11928                 pipe_config->update_wm_post = true;
11929
11930                 /* must disable cxsr around plane enable/disable */
11931                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11932                         pipe_config->disable_cxsr = true;
11933         } else if (intel_wm_need_update(plane, plane_state)) {
11934                 /* FIXME bollocks */
11935                 pipe_config->update_wm_pre = true;
11936                 pipe_config->update_wm_post = true;
11937         }
11938
11939         /* Pre-gen9 platforms need two-step watermark updates */
11940         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11941             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11942                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11943
11944         if (visible || was_visible)
11945                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11946
11947         /*
11948          * WaCxSRDisabledForSpriteScaling:ivb
11949          *
11950          * cstate->update_wm was already set above, so this flag will
11951          * take effect when we commit and program watermarks.
11952          */
11953         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11954             needs_scaling(to_intel_plane_state(plane_state)) &&
11955             !needs_scaling(old_plane_state))
11956                 pipe_config->disable_lp_wm = true;
11957
11958         return 0;
11959 }
11960
11961 static bool encoders_cloneable(const struct intel_encoder *a,
11962                                const struct intel_encoder *b)
11963 {
11964         /* masks could be asymmetric, so check both ways */
11965         return a == b || (a->cloneable & (1 << b->type) &&
11966                           b->cloneable & (1 << a->type));
11967 }
11968
11969 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11970                                          struct intel_crtc *crtc,
11971                                          struct intel_encoder *encoder)
11972 {
11973         struct intel_encoder *source_encoder;
11974         struct drm_connector *connector;
11975         struct drm_connector_state *connector_state;
11976         int i;
11977
11978         for_each_connector_in_state(state, connector, connector_state, i) {
11979                 if (connector_state->crtc != &crtc->base)
11980                         continue;
11981
11982                 source_encoder =
11983                         to_intel_encoder(connector_state->best_encoder);
11984                 if (!encoders_cloneable(encoder, source_encoder))
11985                         return false;
11986         }
11987
11988         return true;
11989 }
11990
11991 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11992                                    struct drm_crtc_state *crtc_state)
11993 {
11994         struct drm_device *dev = crtc->dev;
11995         struct drm_i915_private *dev_priv = to_i915(dev);
11996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11997         struct intel_crtc_state *pipe_config =
11998                 to_intel_crtc_state(crtc_state);
11999         struct drm_atomic_state *state = crtc_state->state;
12000         int ret;
12001         bool mode_changed = needs_modeset(crtc_state);
12002
12003         if (mode_changed && !crtc_state->active)
12004                 pipe_config->update_wm_post = true;
12005
12006         if (mode_changed && crtc_state->enable &&
12007             dev_priv->display.crtc_compute_clock &&
12008             !WARN_ON(pipe_config->shared_dpll)) {
12009                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12010                                                            pipe_config);
12011                 if (ret)
12012                         return ret;
12013         }
12014
12015         if (crtc_state->color_mgmt_changed) {
12016                 ret = intel_color_check(crtc, crtc_state);
12017                 if (ret)
12018                         return ret;
12019
12020                 /*
12021                  * Changing color management on Intel hardware is
12022                  * handled as part of planes update.
12023                  */
12024                 crtc_state->planes_changed = true;
12025         }
12026
12027         ret = 0;
12028         if (dev_priv->display.compute_pipe_wm) {
12029                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12030                 if (ret) {
12031                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12032                         return ret;
12033                 }
12034         }
12035
12036         if (dev_priv->display.compute_intermediate_wm &&
12037             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12038                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12039                         return 0;
12040
12041                 /*
12042                  * Calculate 'intermediate' watermarks that satisfy both the
12043                  * old state and the new state.  We can program these
12044                  * immediately.
12045                  */
12046                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12047                                                                 intel_crtc,
12048                                                                 pipe_config);
12049                 if (ret) {
12050                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12051                         return ret;
12052                 }
12053         } else if (dev_priv->display.compute_intermediate_wm) {
12054                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12055                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12056         }
12057
12058         if (INTEL_INFO(dev)->gen >= 9) {
12059                 if (mode_changed)
12060                         ret = skl_update_scaler_crtc(pipe_config);
12061
12062                 if (!ret)
12063                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12064                                                          pipe_config);
12065         }
12066
12067         return ret;
12068 }
12069
12070 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12071         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12072         .atomic_begin = intel_begin_crtc_commit,
12073         .atomic_flush = intel_finish_crtc_commit,
12074         .atomic_check = intel_crtc_atomic_check,
12075 };
12076
12077 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12078 {
12079         struct intel_connector *connector;
12080
12081         for_each_intel_connector(dev, connector) {
12082                 if (connector->base.state->crtc)
12083                         drm_connector_unreference(&connector->base);
12084
12085                 if (connector->base.encoder) {
12086                         connector->base.state->best_encoder =
12087                                 connector->base.encoder;
12088                         connector->base.state->crtc =
12089                                 connector->base.encoder->crtc;
12090
12091                         drm_connector_reference(&connector->base);
12092                 } else {
12093                         connector->base.state->best_encoder = NULL;
12094                         connector->base.state->crtc = NULL;
12095                 }
12096         }
12097 }
12098
12099 static void
12100 connected_sink_compute_bpp(struct intel_connector *connector,
12101                            struct intel_crtc_state *pipe_config)
12102 {
12103         int bpp = pipe_config->pipe_bpp;
12104
12105         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12106                 connector->base.base.id,
12107                 connector->base.name);
12108
12109         /* Don't use an invalid EDID bpc value */
12110         if (connector->base.display_info.bpc &&
12111             connector->base.display_info.bpc * 3 < bpp) {
12112                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12113                               bpp, connector->base.display_info.bpc*3);
12114                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12115         }
12116
12117         /* Clamp bpp to default limit on screens without EDID 1.4 */
12118         if (connector->base.display_info.bpc == 0) {
12119                 int type = connector->base.connector_type;
12120                 int clamp_bpp = 24;
12121
12122                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12123                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12124                     type == DRM_MODE_CONNECTOR_eDP)
12125                         clamp_bpp = 18;
12126
12127                 if (bpp > clamp_bpp) {
12128                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12129                                       bpp, clamp_bpp);
12130                         pipe_config->pipe_bpp = clamp_bpp;
12131                 }
12132         }
12133 }
12134
12135 static int
12136 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12137                           struct intel_crtc_state *pipe_config)
12138 {
12139         struct drm_device *dev = crtc->base.dev;
12140         struct drm_atomic_state *state;
12141         struct drm_connector *connector;
12142         struct drm_connector_state *connector_state;
12143         int bpp, i;
12144
12145         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12146                 bpp = 10*3;
12147         else if (INTEL_INFO(dev)->gen >= 5)
12148                 bpp = 12*3;
12149         else
12150                 bpp = 8*3;
12151
12152
12153         pipe_config->pipe_bpp = bpp;
12154
12155         state = pipe_config->base.state;
12156
12157         /* Clamp display bpp to EDID value */
12158         for_each_connector_in_state(state, connector, connector_state, i) {
12159                 if (connector_state->crtc != &crtc->base)
12160                         continue;
12161
12162                 connected_sink_compute_bpp(to_intel_connector(connector),
12163                                            pipe_config);
12164         }
12165
12166         return bpp;
12167 }
12168
12169 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12170 {
12171         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12172                         "type: 0x%x flags: 0x%x\n",
12173                 mode->crtc_clock,
12174                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12175                 mode->crtc_hsync_end, mode->crtc_htotal,
12176                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12177                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12178 }
12179
12180 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12181                                    struct intel_crtc_state *pipe_config,
12182                                    const char *context)
12183 {
12184         struct drm_device *dev = crtc->base.dev;
12185         struct drm_plane *plane;
12186         struct intel_plane *intel_plane;
12187         struct intel_plane_state *state;
12188         struct drm_framebuffer *fb;
12189
12190         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12191                       crtc->base.base.id, crtc->base.name,
12192                       context, pipe_config, pipe_name(crtc->pipe));
12193
12194         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12195         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12196                       pipe_config->pipe_bpp, pipe_config->dither);
12197         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12198                       pipe_config->has_pch_encoder,
12199                       pipe_config->fdi_lanes,
12200                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12201                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12202                       pipe_config->fdi_m_n.tu);
12203         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12204                       intel_crtc_has_dp_encoder(pipe_config),
12205                       pipe_config->lane_count,
12206                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12207                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12208                       pipe_config->dp_m_n.tu);
12209
12210         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12211                       intel_crtc_has_dp_encoder(pipe_config),
12212                       pipe_config->lane_count,
12213                       pipe_config->dp_m2_n2.gmch_m,
12214                       pipe_config->dp_m2_n2.gmch_n,
12215                       pipe_config->dp_m2_n2.link_m,
12216                       pipe_config->dp_m2_n2.link_n,
12217                       pipe_config->dp_m2_n2.tu);
12218
12219         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12220                       pipe_config->has_audio,
12221                       pipe_config->has_infoframe);
12222
12223         DRM_DEBUG_KMS("requested mode:\n");
12224         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12225         DRM_DEBUG_KMS("adjusted mode:\n");
12226         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12227         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12228         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12229         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12230                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12231         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12232                       crtc->num_scalers,
12233                       pipe_config->scaler_state.scaler_users,
12234                       pipe_config->scaler_state.scaler_id);
12235         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12236                       pipe_config->gmch_pfit.control,
12237                       pipe_config->gmch_pfit.pgm_ratios,
12238                       pipe_config->gmch_pfit.lvds_border_bits);
12239         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12240                       pipe_config->pch_pfit.pos,
12241                       pipe_config->pch_pfit.size,
12242                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12243         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12244         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12245
12246         if (IS_BROXTON(dev)) {
12247                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12248                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12249                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12250                               pipe_config->ddi_pll_sel,
12251                               pipe_config->dpll_hw_state.ebb0,
12252                               pipe_config->dpll_hw_state.ebb4,
12253                               pipe_config->dpll_hw_state.pll0,
12254                               pipe_config->dpll_hw_state.pll1,
12255                               pipe_config->dpll_hw_state.pll2,
12256                               pipe_config->dpll_hw_state.pll3,
12257                               pipe_config->dpll_hw_state.pll6,
12258                               pipe_config->dpll_hw_state.pll8,
12259                               pipe_config->dpll_hw_state.pll9,
12260                               pipe_config->dpll_hw_state.pll10,
12261                               pipe_config->dpll_hw_state.pcsdw12);
12262         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12263                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12264                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12265                               pipe_config->ddi_pll_sel,
12266                               pipe_config->dpll_hw_state.ctrl1,
12267                               pipe_config->dpll_hw_state.cfgcr1,
12268                               pipe_config->dpll_hw_state.cfgcr2);
12269         } else if (HAS_DDI(dev)) {
12270                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12271                               pipe_config->ddi_pll_sel,
12272                               pipe_config->dpll_hw_state.wrpll,
12273                               pipe_config->dpll_hw_state.spll);
12274         } else {
12275                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12276                               "fp0: 0x%x, fp1: 0x%x\n",
12277                               pipe_config->dpll_hw_state.dpll,
12278                               pipe_config->dpll_hw_state.dpll_md,
12279                               pipe_config->dpll_hw_state.fp0,
12280                               pipe_config->dpll_hw_state.fp1);
12281         }
12282
12283         DRM_DEBUG_KMS("planes on this crtc\n");
12284         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12285                 intel_plane = to_intel_plane(plane);
12286                 if (intel_plane->pipe != crtc->pipe)
12287                         continue;
12288
12289                 state = to_intel_plane_state(plane->state);
12290                 fb = state->base.fb;
12291                 if (!fb) {
12292                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12293                                       plane->base.id, plane->name, state->scaler_id);
12294                         continue;
12295                 }
12296
12297                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12298                               plane->base.id, plane->name);
12299                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12300                               fb->base.id, fb->width, fb->height,
12301                               drm_get_format_name(fb->pixel_format));
12302                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12303                               state->scaler_id,
12304                               state->src.x1 >> 16, state->src.y1 >> 16,
12305                               drm_rect_width(&state->src) >> 16,
12306                               drm_rect_height(&state->src) >> 16,
12307                               state->dst.x1, state->dst.y1,
12308                               drm_rect_width(&state->dst),
12309                               drm_rect_height(&state->dst));
12310         }
12311 }
12312
12313 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12314 {
12315         struct drm_device *dev = state->dev;
12316         struct drm_connector *connector;
12317         unsigned int used_ports = 0;
12318
12319         /*
12320          * Walk the connector list instead of the encoder
12321          * list to detect the problem on ddi platforms
12322          * where there's just one encoder per digital port.
12323          */
12324         drm_for_each_connector(connector, dev) {
12325                 struct drm_connector_state *connector_state;
12326                 struct intel_encoder *encoder;
12327
12328                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12329                 if (!connector_state)
12330                         connector_state = connector->state;
12331
12332                 if (!connector_state->best_encoder)
12333                         continue;
12334
12335                 encoder = to_intel_encoder(connector_state->best_encoder);
12336
12337                 WARN_ON(!connector_state->crtc);
12338
12339                 switch (encoder->type) {
12340                         unsigned int port_mask;
12341                 case INTEL_OUTPUT_UNKNOWN:
12342                         if (WARN_ON(!HAS_DDI(dev)))
12343                                 break;
12344                 case INTEL_OUTPUT_DP:
12345                 case INTEL_OUTPUT_HDMI:
12346                 case INTEL_OUTPUT_EDP:
12347                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12348
12349                         /* the same port mustn't appear more than once */
12350                         if (used_ports & port_mask)
12351                                 return false;
12352
12353                         used_ports |= port_mask;
12354                 default:
12355                         break;
12356                 }
12357         }
12358
12359         return true;
12360 }
12361
12362 static void
12363 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12364 {
12365         struct drm_crtc_state tmp_state;
12366         struct intel_crtc_scaler_state scaler_state;
12367         struct intel_dpll_hw_state dpll_hw_state;
12368         struct intel_shared_dpll *shared_dpll;
12369         uint32_t ddi_pll_sel;
12370         bool force_thru;
12371
12372         /* FIXME: before the switch to atomic started, a new pipe_config was
12373          * kzalloc'd. Code that depends on any field being zero should be
12374          * fixed, so that the crtc_state can be safely duplicated. For now,
12375          * only fields that are know to not cause problems are preserved. */
12376
12377         tmp_state = crtc_state->base;
12378         scaler_state = crtc_state->scaler_state;
12379         shared_dpll = crtc_state->shared_dpll;
12380         dpll_hw_state = crtc_state->dpll_hw_state;
12381         ddi_pll_sel = crtc_state->ddi_pll_sel;
12382         force_thru = crtc_state->pch_pfit.force_thru;
12383
12384         memset(crtc_state, 0, sizeof *crtc_state);
12385
12386         crtc_state->base = tmp_state;
12387         crtc_state->scaler_state = scaler_state;
12388         crtc_state->shared_dpll = shared_dpll;
12389         crtc_state->dpll_hw_state = dpll_hw_state;
12390         crtc_state->ddi_pll_sel = ddi_pll_sel;
12391         crtc_state->pch_pfit.force_thru = force_thru;
12392 }
12393
12394 static int
12395 intel_modeset_pipe_config(struct drm_crtc *crtc,
12396                           struct intel_crtc_state *pipe_config)
12397 {
12398         struct drm_atomic_state *state = pipe_config->base.state;
12399         struct intel_encoder *encoder;
12400         struct drm_connector *connector;
12401         struct drm_connector_state *connector_state;
12402         int base_bpp, ret = -EINVAL;
12403         int i;
12404         bool retry = true;
12405
12406         clear_intel_crtc_state(pipe_config);
12407
12408         pipe_config->cpu_transcoder =
12409                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12410
12411         /*
12412          * Sanitize sync polarity flags based on requested ones. If neither
12413          * positive or negative polarity is requested, treat this as meaning
12414          * negative polarity.
12415          */
12416         if (!(pipe_config->base.adjusted_mode.flags &
12417               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12418                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12419
12420         if (!(pipe_config->base.adjusted_mode.flags &
12421               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12422                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12423
12424         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12425                                              pipe_config);
12426         if (base_bpp < 0)
12427                 goto fail;
12428
12429         /*
12430          * Determine the real pipe dimensions. Note that stereo modes can
12431          * increase the actual pipe size due to the frame doubling and
12432          * insertion of additional space for blanks between the frame. This
12433          * is stored in the crtc timings. We use the requested mode to do this
12434          * computation to clearly distinguish it from the adjusted mode, which
12435          * can be changed by the connectors in the below retry loop.
12436          */
12437         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12438                                &pipe_config->pipe_src_w,
12439                                &pipe_config->pipe_src_h);
12440
12441         for_each_connector_in_state(state, connector, connector_state, i) {
12442                 if (connector_state->crtc != crtc)
12443                         continue;
12444
12445                 encoder = to_intel_encoder(connector_state->best_encoder);
12446
12447                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12448                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12449                         goto fail;
12450                 }
12451
12452                 /*
12453                  * Determine output_types before calling the .compute_config()
12454                  * hooks so that the hooks can use this information safely.
12455                  */
12456                 pipe_config->output_types |= 1 << encoder->type;
12457         }
12458
12459 encoder_retry:
12460         /* Ensure the port clock defaults are reset when retrying. */
12461         pipe_config->port_clock = 0;
12462         pipe_config->pixel_multiplier = 1;
12463
12464         /* Fill in default crtc timings, allow encoders to overwrite them. */
12465         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12466                               CRTC_STEREO_DOUBLE);
12467
12468         /* Pass our mode to the connectors and the CRTC to give them a chance to
12469          * adjust it according to limitations or connector properties, and also
12470          * a chance to reject the mode entirely.
12471          */
12472         for_each_connector_in_state(state, connector, connector_state, i) {
12473                 if (connector_state->crtc != crtc)
12474                         continue;
12475
12476                 encoder = to_intel_encoder(connector_state->best_encoder);
12477
12478                 if (!(encoder->compute_config(encoder, pipe_config))) {
12479                         DRM_DEBUG_KMS("Encoder config failure\n");
12480                         goto fail;
12481                 }
12482         }
12483
12484         /* Set default port clock if not overwritten by the encoder. Needs to be
12485          * done afterwards in case the encoder adjusts the mode. */
12486         if (!pipe_config->port_clock)
12487                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12488                         * pipe_config->pixel_multiplier;
12489
12490         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12491         if (ret < 0) {
12492                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12493                 goto fail;
12494         }
12495
12496         if (ret == RETRY) {
12497                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12498                         ret = -EINVAL;
12499                         goto fail;
12500                 }
12501
12502                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12503                 retry = false;
12504                 goto encoder_retry;
12505         }
12506
12507         /* Dithering seems to not pass-through bits correctly when it should, so
12508          * only enable it on 6bpc panels. */
12509         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12510         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12511                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12512
12513 fail:
12514         return ret;
12515 }
12516
12517 static void
12518 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12519 {
12520         struct drm_crtc *crtc;
12521         struct drm_crtc_state *crtc_state;
12522         int i;
12523
12524         /* Double check state. */
12525         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12526                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12527
12528                 /* Update hwmode for vblank functions */
12529                 if (crtc->state->active)
12530                         crtc->hwmode = crtc->state->adjusted_mode;
12531                 else
12532                         crtc->hwmode.crtc_clock = 0;
12533
12534                 /*
12535                  * Update legacy state to satisfy fbc code. This can
12536                  * be removed when fbc uses the atomic state.
12537                  */
12538                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12539                         struct drm_plane_state *plane_state = crtc->primary->state;
12540
12541                         crtc->primary->fb = plane_state->fb;
12542                         crtc->x = plane_state->src_x >> 16;
12543                         crtc->y = plane_state->src_y >> 16;
12544                 }
12545         }
12546 }
12547
12548 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12549 {
12550         int diff;
12551
12552         if (clock1 == clock2)
12553                 return true;
12554
12555         if (!clock1 || !clock2)
12556                 return false;
12557
12558         diff = abs(clock1 - clock2);
12559
12560         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12561                 return true;
12562
12563         return false;
12564 }
12565
12566 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12567         list_for_each_entry((intel_crtc), \
12568                             &(dev)->mode_config.crtc_list, \
12569                             base.head) \
12570                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12571
12572 static bool
12573 intel_compare_m_n(unsigned int m, unsigned int n,
12574                   unsigned int m2, unsigned int n2,
12575                   bool exact)
12576 {
12577         if (m == m2 && n == n2)
12578                 return true;
12579
12580         if (exact || !m || !n || !m2 || !n2)
12581                 return false;
12582
12583         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12584
12585         if (n > n2) {
12586                 while (n > n2) {
12587                         m2 <<= 1;
12588                         n2 <<= 1;
12589                 }
12590         } else if (n < n2) {
12591                 while (n < n2) {
12592                         m <<= 1;
12593                         n <<= 1;
12594                 }
12595         }
12596
12597         if (n != n2)
12598                 return false;
12599
12600         return intel_fuzzy_clock_check(m, m2);
12601 }
12602
12603 static bool
12604 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12605                        struct intel_link_m_n *m2_n2,
12606                        bool adjust)
12607 {
12608         if (m_n->tu == m2_n2->tu &&
12609             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12610                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12611             intel_compare_m_n(m_n->link_m, m_n->link_n,
12612                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12613                 if (adjust)
12614                         *m2_n2 = *m_n;
12615
12616                 return true;
12617         }
12618
12619         return false;
12620 }
12621
12622 static bool
12623 intel_pipe_config_compare(struct drm_device *dev,
12624                           struct intel_crtc_state *current_config,
12625                           struct intel_crtc_state *pipe_config,
12626                           bool adjust)
12627 {
12628         bool ret = true;
12629
12630 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12631         do { \
12632                 if (!adjust) \
12633                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12634                 else \
12635                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12636         } while (0)
12637
12638 #define PIPE_CONF_CHECK_X(name) \
12639         if (current_config->name != pipe_config->name) { \
12640                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12641                           "(expected 0x%08x, found 0x%08x)\n", \
12642                           current_config->name, \
12643                           pipe_config->name); \
12644                 ret = false; \
12645         }
12646
12647 #define PIPE_CONF_CHECK_I(name) \
12648         if (current_config->name != pipe_config->name) { \
12649                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12650                           "(expected %i, found %i)\n", \
12651                           current_config->name, \
12652                           pipe_config->name); \
12653                 ret = false; \
12654         }
12655
12656 #define PIPE_CONF_CHECK_P(name) \
12657         if (current_config->name != pipe_config->name) { \
12658                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12659                           "(expected %p, found %p)\n", \
12660                           current_config->name, \
12661                           pipe_config->name); \
12662                 ret = false; \
12663         }
12664
12665 #define PIPE_CONF_CHECK_M_N(name) \
12666         if (!intel_compare_link_m_n(&current_config->name, \
12667                                     &pipe_config->name,\
12668                                     adjust)) { \
12669                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12670                           "(expected tu %i gmch %i/%i link %i/%i, " \
12671                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12672                           current_config->name.tu, \
12673                           current_config->name.gmch_m, \
12674                           current_config->name.gmch_n, \
12675                           current_config->name.link_m, \
12676                           current_config->name.link_n, \
12677                           pipe_config->name.tu, \
12678                           pipe_config->name.gmch_m, \
12679                           pipe_config->name.gmch_n, \
12680                           pipe_config->name.link_m, \
12681                           pipe_config->name.link_n); \
12682                 ret = false; \
12683         }
12684
12685 /* This is required for BDW+ where there is only one set of registers for
12686  * switching between high and low RR.
12687  * This macro can be used whenever a comparison has to be made between one
12688  * hw state and multiple sw state variables.
12689  */
12690 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12691         if (!intel_compare_link_m_n(&current_config->name, \
12692                                     &pipe_config->name, adjust) && \
12693             !intel_compare_link_m_n(&current_config->alt_name, \
12694                                     &pipe_config->name, adjust)) { \
12695                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12696                           "(expected tu %i gmch %i/%i link %i/%i, " \
12697                           "or tu %i gmch %i/%i link %i/%i, " \
12698                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12699                           current_config->name.tu, \
12700                           current_config->name.gmch_m, \
12701                           current_config->name.gmch_n, \
12702                           current_config->name.link_m, \
12703                           current_config->name.link_n, \
12704                           current_config->alt_name.tu, \
12705                           current_config->alt_name.gmch_m, \
12706                           current_config->alt_name.gmch_n, \
12707                           current_config->alt_name.link_m, \
12708                           current_config->alt_name.link_n, \
12709                           pipe_config->name.tu, \
12710                           pipe_config->name.gmch_m, \
12711                           pipe_config->name.gmch_n, \
12712                           pipe_config->name.link_m, \
12713                           pipe_config->name.link_n); \
12714                 ret = false; \
12715         }
12716
12717 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12718         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12719                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12720                           "(expected %i, found %i)\n", \
12721                           current_config->name & (mask), \
12722                           pipe_config->name & (mask)); \
12723                 ret = false; \
12724         }
12725
12726 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12727         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12728                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12729                           "(expected %i, found %i)\n", \
12730                           current_config->name, \
12731                           pipe_config->name); \
12732                 ret = false; \
12733         }
12734
12735 #define PIPE_CONF_QUIRK(quirk)  \
12736         ((current_config->quirks | pipe_config->quirks) & (quirk))
12737
12738         PIPE_CONF_CHECK_I(cpu_transcoder);
12739
12740         PIPE_CONF_CHECK_I(has_pch_encoder);
12741         PIPE_CONF_CHECK_I(fdi_lanes);
12742         PIPE_CONF_CHECK_M_N(fdi_m_n);
12743
12744         PIPE_CONF_CHECK_I(lane_count);
12745         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12746
12747         if (INTEL_INFO(dev)->gen < 8) {
12748                 PIPE_CONF_CHECK_M_N(dp_m_n);
12749
12750                 if (current_config->has_drrs)
12751                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12752         } else
12753                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12754
12755         PIPE_CONF_CHECK_X(output_types);
12756
12757         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12758         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12759         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12760         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12761         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12762         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12763
12764         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12765         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12766         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12767         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12768         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12769         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12770
12771         PIPE_CONF_CHECK_I(pixel_multiplier);
12772         PIPE_CONF_CHECK_I(has_hdmi_sink);
12773         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12774             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12775                 PIPE_CONF_CHECK_I(limited_color_range);
12776         PIPE_CONF_CHECK_I(has_infoframe);
12777
12778         PIPE_CONF_CHECK_I(has_audio);
12779
12780         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12781                               DRM_MODE_FLAG_INTERLACE);
12782
12783         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12784                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12785                                       DRM_MODE_FLAG_PHSYNC);
12786                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12787                                       DRM_MODE_FLAG_NHSYNC);
12788                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12789                                       DRM_MODE_FLAG_PVSYNC);
12790                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12791                                       DRM_MODE_FLAG_NVSYNC);
12792         }
12793
12794         PIPE_CONF_CHECK_X(gmch_pfit.control);
12795         /* pfit ratios are autocomputed by the hw on gen4+ */
12796         if (INTEL_INFO(dev)->gen < 4)
12797                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12798         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12799
12800         if (!adjust) {
12801                 PIPE_CONF_CHECK_I(pipe_src_w);
12802                 PIPE_CONF_CHECK_I(pipe_src_h);
12803
12804                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12805                 if (current_config->pch_pfit.enabled) {
12806                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12807                         PIPE_CONF_CHECK_X(pch_pfit.size);
12808                 }
12809
12810                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12811         }
12812
12813         /* BDW+ don't expose a synchronous way to read the state */
12814         if (IS_HASWELL(dev))
12815                 PIPE_CONF_CHECK_I(ips_enabled);
12816
12817         PIPE_CONF_CHECK_I(double_wide);
12818
12819         PIPE_CONF_CHECK_X(ddi_pll_sel);
12820
12821         PIPE_CONF_CHECK_P(shared_dpll);
12822         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12823         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12824         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12825         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12826         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12827         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12828         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12829         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12830         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12831
12832         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12833         PIPE_CONF_CHECK_X(dsi_pll.div);
12834
12835         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12836                 PIPE_CONF_CHECK_I(pipe_bpp);
12837
12838         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12839         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12840
12841 #undef PIPE_CONF_CHECK_X
12842 #undef PIPE_CONF_CHECK_I
12843 #undef PIPE_CONF_CHECK_P
12844 #undef PIPE_CONF_CHECK_FLAGS
12845 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12846 #undef PIPE_CONF_QUIRK
12847 #undef INTEL_ERR_OR_DBG_KMS
12848
12849         return ret;
12850 }
12851
12852 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12853                                            const struct intel_crtc_state *pipe_config)
12854 {
12855         if (pipe_config->has_pch_encoder) {
12856                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12857                                                             &pipe_config->fdi_m_n);
12858                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12859
12860                 /*
12861                  * FDI already provided one idea for the dotclock.
12862                  * Yell if the encoder disagrees.
12863                  */
12864                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12865                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12866                      fdi_dotclock, dotclock);
12867         }
12868 }
12869
12870 static void verify_wm_state(struct drm_crtc *crtc,
12871                             struct drm_crtc_state *new_state)
12872 {
12873         struct drm_device *dev = crtc->dev;
12874         struct drm_i915_private *dev_priv = to_i915(dev);
12875         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12876         struct skl_ddb_entry *hw_entry, *sw_entry;
12877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12878         const enum pipe pipe = intel_crtc->pipe;
12879         int plane;
12880
12881         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12882                 return;
12883
12884         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12885         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12886
12887         /* planes */
12888         for_each_plane(dev_priv, pipe, plane) {
12889                 hw_entry = &hw_ddb.plane[pipe][plane];
12890                 sw_entry = &sw_ddb->plane[pipe][plane];
12891
12892                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12893                         continue;
12894
12895                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12896                           "(expected (%u,%u), found (%u,%u))\n",
12897                           pipe_name(pipe), plane + 1,
12898                           sw_entry->start, sw_entry->end,
12899                           hw_entry->start, hw_entry->end);
12900         }
12901
12902         /* cursor */
12903         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12904         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12905
12906         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12907                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12908                           "(expected (%u,%u), found (%u,%u))\n",
12909                           pipe_name(pipe),
12910                           sw_entry->start, sw_entry->end,
12911                           hw_entry->start, hw_entry->end);
12912         }
12913 }
12914
12915 static void
12916 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12917 {
12918         struct drm_connector *connector;
12919
12920         drm_for_each_connector(connector, dev) {
12921                 struct drm_encoder *encoder = connector->encoder;
12922                 struct drm_connector_state *state = connector->state;
12923
12924                 if (state->crtc != crtc)
12925                         continue;
12926
12927                 intel_connector_verify_state(to_intel_connector(connector));
12928
12929                 I915_STATE_WARN(state->best_encoder != encoder,
12930                      "connector's atomic encoder doesn't match legacy encoder\n");
12931         }
12932 }
12933
12934 static void
12935 verify_encoder_state(struct drm_device *dev)
12936 {
12937         struct intel_encoder *encoder;
12938         struct intel_connector *connector;
12939
12940         for_each_intel_encoder(dev, encoder) {
12941                 bool enabled = false;
12942                 enum pipe pipe;
12943
12944                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12945                               encoder->base.base.id,
12946                               encoder->base.name);
12947
12948                 for_each_intel_connector(dev, connector) {
12949                         if (connector->base.state->best_encoder != &encoder->base)
12950                                 continue;
12951                         enabled = true;
12952
12953                         I915_STATE_WARN(connector->base.state->crtc !=
12954                                         encoder->base.crtc,
12955                              "connector's crtc doesn't match encoder crtc\n");
12956                 }
12957
12958                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12959                      "encoder's enabled state mismatch "
12960                      "(expected %i, found %i)\n",
12961                      !!encoder->base.crtc, enabled);
12962
12963                 if (!encoder->base.crtc) {
12964                         bool active;
12965
12966                         active = encoder->get_hw_state(encoder, &pipe);
12967                         I915_STATE_WARN(active,
12968                              "encoder detached but still enabled on pipe %c.\n",
12969                              pipe_name(pipe));
12970                 }
12971         }
12972 }
12973
12974 static void
12975 verify_crtc_state(struct drm_crtc *crtc,
12976                   struct drm_crtc_state *old_crtc_state,
12977                   struct drm_crtc_state *new_crtc_state)
12978 {
12979         struct drm_device *dev = crtc->dev;
12980         struct drm_i915_private *dev_priv = to_i915(dev);
12981         struct intel_encoder *encoder;
12982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12983         struct intel_crtc_state *pipe_config, *sw_config;
12984         struct drm_atomic_state *old_state;
12985         bool active;
12986
12987         old_state = old_crtc_state->state;
12988         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12989         pipe_config = to_intel_crtc_state(old_crtc_state);
12990         memset(pipe_config, 0, sizeof(*pipe_config));
12991         pipe_config->base.crtc = crtc;
12992         pipe_config->base.state = old_state;
12993
12994         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12995
12996         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12997
12998         /* hw state is inconsistent with the pipe quirk */
12999         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13000             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13001                 active = new_crtc_state->active;
13002
13003         I915_STATE_WARN(new_crtc_state->active != active,
13004              "crtc active state doesn't match with hw state "
13005              "(expected %i, found %i)\n", new_crtc_state->active, active);
13006
13007         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13008              "transitional active state does not match atomic hw state "
13009              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13010
13011         for_each_encoder_on_crtc(dev, crtc, encoder) {
13012                 enum pipe pipe;
13013
13014                 active = encoder->get_hw_state(encoder, &pipe);
13015                 I915_STATE_WARN(active != new_crtc_state->active,
13016                         "[ENCODER:%i] active %i with crtc active %i\n",
13017                         encoder->base.base.id, active, new_crtc_state->active);
13018
13019                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13020                                 "Encoder connected to wrong pipe %c\n",
13021                                 pipe_name(pipe));
13022
13023                 if (active) {
13024                         pipe_config->output_types |= 1 << encoder->type;
13025                         encoder->get_config(encoder, pipe_config);
13026                 }
13027         }
13028
13029         if (!new_crtc_state->active)
13030                 return;
13031
13032         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13033
13034         sw_config = to_intel_crtc_state(crtc->state);
13035         if (!intel_pipe_config_compare(dev, sw_config,
13036                                        pipe_config, false)) {
13037                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13038                 intel_dump_pipe_config(intel_crtc, pipe_config,
13039                                        "[hw state]");
13040                 intel_dump_pipe_config(intel_crtc, sw_config,
13041                                        "[sw state]");
13042         }
13043 }
13044
13045 static void
13046 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13047                          struct intel_shared_dpll *pll,
13048                          struct drm_crtc *crtc,
13049                          struct drm_crtc_state *new_state)
13050 {
13051         struct intel_dpll_hw_state dpll_hw_state;
13052         unsigned crtc_mask;
13053         bool active;
13054
13055         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13056
13057         DRM_DEBUG_KMS("%s\n", pll->name);
13058
13059         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13060
13061         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13062                 I915_STATE_WARN(!pll->on && pll->active_mask,
13063                      "pll in active use but not on in sw tracking\n");
13064                 I915_STATE_WARN(pll->on && !pll->active_mask,
13065                      "pll is on but not used by any active crtc\n");
13066                 I915_STATE_WARN(pll->on != active,
13067                      "pll on state mismatch (expected %i, found %i)\n",
13068                      pll->on, active);
13069         }
13070
13071         if (!crtc) {
13072                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13073                                 "more active pll users than references: %x vs %x\n",
13074                                 pll->active_mask, pll->config.crtc_mask);
13075
13076                 return;
13077         }
13078
13079         crtc_mask = 1 << drm_crtc_index(crtc);
13080
13081         if (new_state->active)
13082                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13083                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13084                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13085         else
13086                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13087                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13088                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13089
13090         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13091                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13092                         crtc_mask, pll->config.crtc_mask);
13093
13094         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13095                                           &dpll_hw_state,
13096                                           sizeof(dpll_hw_state)),
13097                         "pll hw state mismatch\n");
13098 }
13099
13100 static void
13101 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13102                          struct drm_crtc_state *old_crtc_state,
13103                          struct drm_crtc_state *new_crtc_state)
13104 {
13105         struct drm_i915_private *dev_priv = to_i915(dev);
13106         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13107         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13108
13109         if (new_state->shared_dpll)
13110                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13111
13112         if (old_state->shared_dpll &&
13113             old_state->shared_dpll != new_state->shared_dpll) {
13114                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13115                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13116
13117                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13118                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13119                                 pipe_name(drm_crtc_index(crtc)));
13120                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13121                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13122                                 pipe_name(drm_crtc_index(crtc)));
13123         }
13124 }
13125
13126 static void
13127 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13128                          struct drm_crtc_state *old_state,
13129                          struct drm_crtc_state *new_state)
13130 {
13131         if (!needs_modeset(new_state) &&
13132             !to_intel_crtc_state(new_state)->update_pipe)
13133                 return;
13134
13135         verify_wm_state(crtc, new_state);
13136         verify_connector_state(crtc->dev, crtc);
13137         verify_crtc_state(crtc, old_state, new_state);
13138         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13139 }
13140
13141 static void
13142 verify_disabled_dpll_state(struct drm_device *dev)
13143 {
13144         struct drm_i915_private *dev_priv = to_i915(dev);
13145         int i;
13146
13147         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13148                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13149 }
13150
13151 static void
13152 intel_modeset_verify_disabled(struct drm_device *dev)
13153 {
13154         verify_encoder_state(dev);
13155         verify_connector_state(dev, NULL);
13156         verify_disabled_dpll_state(dev);
13157 }
13158
13159 static void update_scanline_offset(struct intel_crtc *crtc)
13160 {
13161         struct drm_device *dev = crtc->base.dev;
13162
13163         /*
13164          * The scanline counter increments at the leading edge of hsync.
13165          *
13166          * On most platforms it starts counting from vtotal-1 on the
13167          * first active line. That means the scanline counter value is
13168          * always one less than what we would expect. Ie. just after
13169          * start of vblank, which also occurs at start of hsync (on the
13170          * last active line), the scanline counter will read vblank_start-1.
13171          *
13172          * On gen2 the scanline counter starts counting from 1 instead
13173          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13174          * to keep the value positive), instead of adding one.
13175          *
13176          * On HSW+ the behaviour of the scanline counter depends on the output
13177          * type. For DP ports it behaves like most other platforms, but on HDMI
13178          * there's an extra 1 line difference. So we need to add two instead of
13179          * one to the value.
13180          */
13181         if (IS_GEN2(dev)) {
13182                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13183                 int vtotal;
13184
13185                 vtotal = adjusted_mode->crtc_vtotal;
13186                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13187                         vtotal /= 2;
13188
13189                 crtc->scanline_offset = vtotal - 1;
13190         } else if (HAS_DDI(dev) &&
13191                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13192                 crtc->scanline_offset = 2;
13193         } else
13194                 crtc->scanline_offset = 1;
13195 }
13196
13197 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13198 {
13199         struct drm_device *dev = state->dev;
13200         struct drm_i915_private *dev_priv = to_i915(dev);
13201         struct intel_shared_dpll_config *shared_dpll = NULL;
13202         struct drm_crtc *crtc;
13203         struct drm_crtc_state *crtc_state;
13204         int i;
13205
13206         if (!dev_priv->display.crtc_compute_clock)
13207                 return;
13208
13209         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13210                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13211                 struct intel_shared_dpll *old_dpll =
13212                         to_intel_crtc_state(crtc->state)->shared_dpll;
13213
13214                 if (!needs_modeset(crtc_state))
13215                         continue;
13216
13217                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13218
13219                 if (!old_dpll)
13220                         continue;
13221
13222                 if (!shared_dpll)
13223                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13224
13225                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13226         }
13227 }
13228
13229 /*
13230  * This implements the workaround described in the "notes" section of the mode
13231  * set sequence documentation. When going from no pipes or single pipe to
13232  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13233  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13234  */
13235 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13236 {
13237         struct drm_crtc_state *crtc_state;
13238         struct intel_crtc *intel_crtc;
13239         struct drm_crtc *crtc;
13240         struct intel_crtc_state *first_crtc_state = NULL;
13241         struct intel_crtc_state *other_crtc_state = NULL;
13242         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13243         int i;
13244
13245         /* look at all crtc's that are going to be enabled in during modeset */
13246         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13247                 intel_crtc = to_intel_crtc(crtc);
13248
13249                 if (!crtc_state->active || !needs_modeset(crtc_state))
13250                         continue;
13251
13252                 if (first_crtc_state) {
13253                         other_crtc_state = to_intel_crtc_state(crtc_state);
13254                         break;
13255                 } else {
13256                         first_crtc_state = to_intel_crtc_state(crtc_state);
13257                         first_pipe = intel_crtc->pipe;
13258                 }
13259         }
13260
13261         /* No workaround needed? */
13262         if (!first_crtc_state)
13263                 return 0;
13264
13265         /* w/a possibly needed, check how many crtc's are already enabled. */
13266         for_each_intel_crtc(state->dev, intel_crtc) {
13267                 struct intel_crtc_state *pipe_config;
13268
13269                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13270                 if (IS_ERR(pipe_config))
13271                         return PTR_ERR(pipe_config);
13272
13273                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13274
13275                 if (!pipe_config->base.active ||
13276                     needs_modeset(&pipe_config->base))
13277                         continue;
13278
13279                 /* 2 or more enabled crtcs means no need for w/a */
13280                 if (enabled_pipe != INVALID_PIPE)
13281                         return 0;
13282
13283                 enabled_pipe = intel_crtc->pipe;
13284         }
13285
13286         if (enabled_pipe != INVALID_PIPE)
13287                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13288         else if (other_crtc_state)
13289                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13290
13291         return 0;
13292 }
13293
13294 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13295 {
13296         struct drm_crtc *crtc;
13297         struct drm_crtc_state *crtc_state;
13298         int ret = 0;
13299
13300         /* add all active pipes to the state */
13301         for_each_crtc(state->dev, crtc) {
13302                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13303                 if (IS_ERR(crtc_state))
13304                         return PTR_ERR(crtc_state);
13305
13306                 if (!crtc_state->active || needs_modeset(crtc_state))
13307                         continue;
13308
13309                 crtc_state->mode_changed = true;
13310
13311                 ret = drm_atomic_add_affected_connectors(state, crtc);
13312                 if (ret)
13313                         break;
13314
13315                 ret = drm_atomic_add_affected_planes(state, crtc);
13316                 if (ret)
13317                         break;
13318         }
13319
13320         return ret;
13321 }
13322
13323 static int intel_modeset_checks(struct drm_atomic_state *state)
13324 {
13325         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13326         struct drm_i915_private *dev_priv = to_i915(state->dev);
13327         struct drm_crtc *crtc;
13328         struct drm_crtc_state *crtc_state;
13329         int ret = 0, i;
13330
13331         if (!check_digital_port_conflicts(state)) {
13332                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13333                 return -EINVAL;
13334         }
13335
13336         intel_state->modeset = true;
13337         intel_state->active_crtcs = dev_priv->active_crtcs;
13338
13339         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13340                 if (crtc_state->active)
13341                         intel_state->active_crtcs |= 1 << i;
13342                 else
13343                         intel_state->active_crtcs &= ~(1 << i);
13344
13345                 if (crtc_state->active != crtc->state->active)
13346                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13347         }
13348
13349         /*
13350          * See if the config requires any additional preparation, e.g.
13351          * to adjust global state with pipes off.  We need to do this
13352          * here so we can get the modeset_pipe updated config for the new
13353          * mode set on this crtc.  For other crtcs we need to use the
13354          * adjusted_mode bits in the crtc directly.
13355          */
13356         if (dev_priv->display.modeset_calc_cdclk) {
13357                 if (!intel_state->cdclk_pll_vco)
13358                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13359                 if (!intel_state->cdclk_pll_vco)
13360                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13361
13362                 ret = dev_priv->display.modeset_calc_cdclk(state);
13363                 if (ret < 0)
13364                         return ret;
13365
13366                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13367                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13368                         ret = intel_modeset_all_pipes(state);
13369
13370                 if (ret < 0)
13371                         return ret;
13372
13373                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13374                               intel_state->cdclk, intel_state->dev_cdclk);
13375         } else
13376                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13377
13378         intel_modeset_clear_plls(state);
13379
13380         if (IS_HASWELL(dev_priv))
13381                 return haswell_mode_set_planes_workaround(state);
13382
13383         return 0;
13384 }
13385
13386 /*
13387  * Handle calculation of various watermark data at the end of the atomic check
13388  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13389  * handlers to ensure that all derived state has been updated.
13390  */
13391 static int calc_watermark_data(struct drm_atomic_state *state)
13392 {
13393         struct drm_device *dev = state->dev;
13394         struct drm_i915_private *dev_priv = to_i915(dev);
13395
13396         /* Is there platform-specific watermark information to calculate? */
13397         if (dev_priv->display.compute_global_watermarks)
13398                 return dev_priv->display.compute_global_watermarks(state);
13399
13400         return 0;
13401 }
13402
13403 /**
13404  * intel_atomic_check - validate state object
13405  * @dev: drm device
13406  * @state: state to validate
13407  */
13408 static int intel_atomic_check(struct drm_device *dev,
13409                               struct drm_atomic_state *state)
13410 {
13411         struct drm_i915_private *dev_priv = to_i915(dev);
13412         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13413         struct drm_crtc *crtc;
13414         struct drm_crtc_state *crtc_state;
13415         int ret, i;
13416         bool any_ms = false;
13417
13418         ret = drm_atomic_helper_check_modeset(dev, state);
13419         if (ret)
13420                 return ret;
13421
13422         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13423                 struct intel_crtc_state *pipe_config =
13424                         to_intel_crtc_state(crtc_state);
13425
13426                 /* Catch I915_MODE_FLAG_INHERITED */
13427                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13428                         crtc_state->mode_changed = true;
13429
13430                 if (!needs_modeset(crtc_state))
13431                         continue;
13432
13433                 if (!crtc_state->enable) {
13434                         any_ms = true;
13435                         continue;
13436                 }
13437
13438                 /* FIXME: For only active_changed we shouldn't need to do any
13439                  * state recomputation at all. */
13440
13441                 ret = drm_atomic_add_affected_connectors(state, crtc);
13442                 if (ret)
13443                         return ret;
13444
13445                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13446                 if (ret) {
13447                         intel_dump_pipe_config(to_intel_crtc(crtc),
13448                                                pipe_config, "[failed]");
13449                         return ret;
13450                 }
13451
13452                 if (i915.fastboot &&
13453                     intel_pipe_config_compare(dev,
13454                                         to_intel_crtc_state(crtc->state),
13455                                         pipe_config, true)) {
13456                         crtc_state->mode_changed = false;
13457                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13458                 }
13459
13460                 if (needs_modeset(crtc_state))
13461                         any_ms = true;
13462
13463                 ret = drm_atomic_add_affected_planes(state, crtc);
13464                 if (ret)
13465                         return ret;
13466
13467                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13468                                        needs_modeset(crtc_state) ?
13469                                        "[modeset]" : "[fastset]");
13470         }
13471
13472         if (any_ms) {
13473                 ret = intel_modeset_checks(state);
13474
13475                 if (ret)
13476                         return ret;
13477         } else
13478                 intel_state->cdclk = dev_priv->cdclk_freq;
13479
13480         ret = drm_atomic_helper_check_planes(dev, state);
13481         if (ret)
13482                 return ret;
13483
13484         intel_fbc_choose_crtc(dev_priv, state);
13485         return calc_watermark_data(state);
13486 }
13487
13488 static int intel_atomic_prepare_commit(struct drm_device *dev,
13489                                        struct drm_atomic_state *state,
13490                                        bool nonblock)
13491 {
13492         struct drm_i915_private *dev_priv = to_i915(dev);
13493         struct drm_plane_state *plane_state;
13494         struct drm_crtc_state *crtc_state;
13495         struct drm_plane *plane;
13496         struct drm_crtc *crtc;
13497         int i, ret;
13498
13499         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13500                 if (state->legacy_cursor_update)
13501                         continue;
13502
13503                 ret = intel_crtc_wait_for_pending_flips(crtc);
13504                 if (ret)
13505                         return ret;
13506
13507                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13508                         flush_workqueue(dev_priv->wq);
13509         }
13510
13511         ret = mutex_lock_interruptible(&dev->struct_mutex);
13512         if (ret)
13513                 return ret;
13514
13515         ret = drm_atomic_helper_prepare_planes(dev, state);
13516         mutex_unlock(&dev->struct_mutex);
13517
13518         if (!ret && !nonblock) {
13519                 for_each_plane_in_state(state, plane, plane_state, i) {
13520                         struct intel_plane_state *intel_plane_state =
13521                                 to_intel_plane_state(plane_state);
13522
13523                         if (!intel_plane_state->wait_req)
13524                                 continue;
13525
13526                         ret = __i915_wait_request(intel_plane_state->wait_req,
13527                                                   true, NULL, NULL);
13528                         if (ret) {
13529                                 /* Any hang should be swallowed by the wait */
13530                                 WARN_ON(ret == -EIO);
13531                                 mutex_lock(&dev->struct_mutex);
13532                                 drm_atomic_helper_cleanup_planes(dev, state);
13533                                 mutex_unlock(&dev->struct_mutex);
13534                                 break;
13535                         }
13536                 }
13537         }
13538
13539         return ret;
13540 }
13541
13542 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13543 {
13544         struct drm_device *dev = crtc->base.dev;
13545
13546         if (!dev->max_vblank_count)
13547                 return drm_accurate_vblank_count(&crtc->base);
13548
13549         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13550 }
13551
13552 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13553                                           struct drm_i915_private *dev_priv,
13554                                           unsigned crtc_mask)
13555 {
13556         unsigned last_vblank_count[I915_MAX_PIPES];
13557         enum pipe pipe;
13558         int ret;
13559
13560         if (!crtc_mask)
13561                 return;
13562
13563         for_each_pipe(dev_priv, pipe) {
13564                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13565
13566                 if (!((1 << pipe) & crtc_mask))
13567                         continue;
13568
13569                 ret = drm_crtc_vblank_get(crtc);
13570                 if (WARN_ON(ret != 0)) {
13571                         crtc_mask &= ~(1 << pipe);
13572                         continue;
13573                 }
13574
13575                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13576         }
13577
13578         for_each_pipe(dev_priv, pipe) {
13579                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13580                 long lret;
13581
13582                 if (!((1 << pipe) & crtc_mask))
13583                         continue;
13584
13585                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13586                                 last_vblank_count[pipe] !=
13587                                         drm_crtc_vblank_count(crtc),
13588                                 msecs_to_jiffies(50));
13589
13590                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13591
13592                 drm_crtc_vblank_put(crtc);
13593         }
13594 }
13595
13596 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13597 {
13598         /* fb updated, need to unpin old fb */
13599         if (crtc_state->fb_changed)
13600                 return true;
13601
13602         /* wm changes, need vblank before final wm's */
13603         if (crtc_state->update_wm_post)
13604                 return true;
13605
13606         /*
13607          * cxsr is re-enabled after vblank.
13608          * This is already handled by crtc_state->update_wm_post,
13609          * but added for clarity.
13610          */
13611         if (crtc_state->disable_cxsr)
13612                 return true;
13613
13614         return false;
13615 }
13616
13617 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13618 {
13619         struct drm_device *dev = state->dev;
13620         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13621         struct drm_i915_private *dev_priv = to_i915(dev);
13622         struct drm_crtc_state *old_crtc_state;
13623         struct drm_crtc *crtc;
13624         struct intel_crtc_state *intel_cstate;
13625         struct drm_plane *plane;
13626         struct drm_plane_state *plane_state;
13627         bool hw_check = intel_state->modeset;
13628         unsigned long put_domains[I915_MAX_PIPES] = {};
13629         unsigned crtc_vblank_mask = 0;
13630         int i, ret;
13631
13632         for_each_plane_in_state(state, plane, plane_state, i) {
13633                 struct intel_plane_state *intel_plane_state =
13634                         to_intel_plane_state(plane_state);
13635
13636                 if (!intel_plane_state->wait_req)
13637                         continue;
13638
13639                 ret = __i915_wait_request(intel_plane_state->wait_req,
13640                                           true, NULL, NULL);
13641                 /* EIO should be eaten, and we can't get interrupted in the
13642                  * worker, and blocking commits have waited already. */
13643                 WARN_ON(ret);
13644         }
13645
13646         drm_atomic_helper_wait_for_dependencies(state);
13647
13648         if (intel_state->modeset) {
13649                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13650                        sizeof(intel_state->min_pixclk));
13651                 dev_priv->active_crtcs = intel_state->active_crtcs;
13652                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13653
13654                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13655         }
13656
13657         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13658                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13659
13660                 if (needs_modeset(crtc->state) ||
13661                     to_intel_crtc_state(crtc->state)->update_pipe) {
13662                         hw_check = true;
13663
13664                         put_domains[to_intel_crtc(crtc)->pipe] =
13665                                 modeset_get_crtc_power_domains(crtc,
13666                                         to_intel_crtc_state(crtc->state));
13667                 }
13668
13669                 if (!needs_modeset(crtc->state))
13670                         continue;
13671
13672                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13673
13674                 if (old_crtc_state->active) {
13675                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13676                         dev_priv->display.crtc_disable(crtc);
13677                         intel_crtc->active = false;
13678                         intel_fbc_disable(intel_crtc);
13679                         intel_disable_shared_dpll(intel_crtc);
13680
13681                         /*
13682                          * Underruns don't always raise
13683                          * interrupts, so check manually.
13684                          */
13685                         intel_check_cpu_fifo_underruns(dev_priv);
13686                         intel_check_pch_fifo_underruns(dev_priv);
13687
13688                         if (!crtc->state->active)
13689                                 intel_update_watermarks(crtc);
13690                 }
13691         }
13692
13693         /* Only after disabling all output pipelines that will be changed can we
13694          * update the the output configuration. */
13695         intel_modeset_update_crtc_state(state);
13696
13697         if (intel_state->modeset) {
13698                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13699
13700                 if (dev_priv->display.modeset_commit_cdclk &&
13701                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13702                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13703                         dev_priv->display.modeset_commit_cdclk(state);
13704
13705                 intel_modeset_verify_disabled(dev);
13706         }
13707
13708         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13709         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13710                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13711                 bool modeset = needs_modeset(crtc->state);
13712                 struct intel_crtc_state *pipe_config =
13713                         to_intel_crtc_state(crtc->state);
13714
13715                 if (modeset && crtc->state->active) {
13716                         update_scanline_offset(to_intel_crtc(crtc));
13717                         dev_priv->display.crtc_enable(crtc);
13718                 }
13719
13720                 /* Complete events for now disable pipes here. */
13721                 if (modeset && !crtc->state->active && crtc->state->event) {
13722                         spin_lock_irq(&dev->event_lock);
13723                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
13724                         spin_unlock_irq(&dev->event_lock);
13725
13726                         crtc->state->event = NULL;
13727                 }
13728
13729                 if (!modeset)
13730                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13731
13732                 if (crtc->state->active &&
13733                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13734                         intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13735
13736                 if (crtc->state->active)
13737                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13738
13739                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13740                         crtc_vblank_mask |= 1 << i;
13741         }
13742
13743         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13744          * already, but still need the state for the delayed optimization. To
13745          * fix this:
13746          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13747          * - schedule that vblank worker _before_ calling hw_done
13748          * - at the start of commit_tail, cancel it _synchrously
13749          * - switch over to the vblank wait helper in the core after that since
13750          *   we don't need out special handling any more.
13751          */
13752         if (!state->legacy_cursor_update)
13753                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13754
13755         /*
13756          * Now that the vblank has passed, we can go ahead and program the
13757          * optimal watermarks on platforms that need two-step watermark
13758          * programming.
13759          *
13760          * TODO: Move this (and other cleanup) to an async worker eventually.
13761          */
13762         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13763                 intel_cstate = to_intel_crtc_state(crtc->state);
13764
13765                 if (dev_priv->display.optimize_watermarks)
13766                         dev_priv->display.optimize_watermarks(intel_cstate);
13767         }
13768
13769         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13770                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13771
13772                 if (put_domains[i])
13773                         modeset_put_power_domains(dev_priv, put_domains[i]);
13774
13775                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13776         }
13777
13778         drm_atomic_helper_commit_hw_done(state);
13779
13780         if (intel_state->modeset)
13781                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13782
13783         mutex_lock(&dev->struct_mutex);
13784         drm_atomic_helper_cleanup_planes(dev, state);
13785         mutex_unlock(&dev->struct_mutex);
13786
13787         drm_atomic_helper_commit_cleanup_done(state);
13788
13789         drm_atomic_state_free(state);
13790
13791         /* As one of the primary mmio accessors, KMS has a high likelihood
13792          * of triggering bugs in unclaimed access. After we finish
13793          * modesetting, see if an error has been flagged, and if so
13794          * enable debugging for the next modeset - and hope we catch
13795          * the culprit.
13796          *
13797          * XXX note that we assume display power is on at this point.
13798          * This might hold true now but we need to add pm helper to check
13799          * unclaimed only when the hardware is on, as atomic commits
13800          * can happen also when the device is completely off.
13801          */
13802         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13803 }
13804
13805 static void intel_atomic_commit_work(struct work_struct *work)
13806 {
13807         struct drm_atomic_state *state = container_of(work,
13808                                                       struct drm_atomic_state,
13809                                                       commit_work);
13810         intel_atomic_commit_tail(state);
13811 }
13812
13813 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13814 {
13815         struct drm_plane_state *old_plane_state;
13816         struct drm_plane *plane;
13817         struct drm_i915_gem_object *obj, *old_obj;
13818         struct intel_plane *intel_plane;
13819         int i;
13820
13821         mutex_lock(&state->dev->struct_mutex);
13822         for_each_plane_in_state(state, plane, old_plane_state, i) {
13823                 obj = intel_fb_obj(plane->state->fb);
13824                 old_obj = intel_fb_obj(old_plane_state->fb);
13825                 intel_plane = to_intel_plane(plane);
13826
13827                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13828         }
13829         mutex_unlock(&state->dev->struct_mutex);
13830 }
13831
13832 /**
13833  * intel_atomic_commit - commit validated state object
13834  * @dev: DRM device
13835  * @state: the top-level driver state object
13836  * @nonblock: nonblocking commit
13837  *
13838  * This function commits a top-level state object that has been validated
13839  * with drm_atomic_helper_check().
13840  *
13841  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13842  * nonblocking commits are only safe for pure plane updates. Everything else
13843  * should work though.
13844  *
13845  * RETURNS
13846  * Zero for success or -errno.
13847  */
13848 static int intel_atomic_commit(struct drm_device *dev,
13849                                struct drm_atomic_state *state,
13850                                bool nonblock)
13851 {
13852         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13853         struct drm_i915_private *dev_priv = to_i915(dev);
13854         int ret = 0;
13855
13856         if (intel_state->modeset && nonblock) {
13857                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13858                 return -EINVAL;
13859         }
13860
13861         ret = drm_atomic_helper_setup_commit(state, nonblock);
13862         if (ret)
13863                 return ret;
13864
13865         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13866
13867         ret = intel_atomic_prepare_commit(dev, state, nonblock);
13868         if (ret) {
13869                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13870                 return ret;
13871         }
13872
13873         drm_atomic_helper_swap_state(state, true);
13874         dev_priv->wm.distrust_bios_wm = false;
13875         dev_priv->wm.skl_results = intel_state->wm_results;
13876         intel_shared_dpll_commit(state);
13877         intel_atomic_track_fbs(state);
13878
13879         if (nonblock)
13880                 queue_work(system_unbound_wq, &state->commit_work);
13881         else
13882                 intel_atomic_commit_tail(state);
13883
13884         return 0;
13885 }
13886
13887 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13888 {
13889         struct drm_device *dev = crtc->dev;
13890         struct drm_atomic_state *state;
13891         struct drm_crtc_state *crtc_state;
13892         int ret;
13893
13894         state = drm_atomic_state_alloc(dev);
13895         if (!state) {
13896                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13897                               crtc->base.id, crtc->name);
13898                 return;
13899         }
13900
13901         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13902
13903 retry:
13904         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13905         ret = PTR_ERR_OR_ZERO(crtc_state);
13906         if (!ret) {
13907                 if (!crtc_state->active)
13908                         goto out;
13909
13910                 crtc_state->mode_changed = true;
13911                 ret = drm_atomic_commit(state);
13912         }
13913
13914         if (ret == -EDEADLK) {
13915                 drm_atomic_state_clear(state);
13916                 drm_modeset_backoff(state->acquire_ctx);
13917                 goto retry;
13918         }
13919
13920         if (ret)
13921 out:
13922                 drm_atomic_state_free(state);
13923 }
13924
13925 #undef for_each_intel_crtc_masked
13926
13927 /*
13928  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13929  *        drm_atomic_helper_legacy_gamma_set() directly.
13930  */
13931 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13932                                          u16 *red, u16 *green, u16 *blue,
13933                                          uint32_t size)
13934 {
13935         struct drm_device *dev = crtc->dev;
13936         struct drm_mode_config *config = &dev->mode_config;
13937         struct drm_crtc_state *state;
13938         int ret;
13939
13940         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13941         if (ret)
13942                 return ret;
13943
13944         /*
13945          * Make sure we update the legacy properties so this works when
13946          * atomic is not enabled.
13947          */
13948
13949         state = crtc->state;
13950
13951         drm_object_property_set_value(&crtc->base,
13952                                       config->degamma_lut_property,
13953                                       (state->degamma_lut) ?
13954                                       state->degamma_lut->base.id : 0);
13955
13956         drm_object_property_set_value(&crtc->base,
13957                                       config->ctm_property,
13958                                       (state->ctm) ?
13959                                       state->ctm->base.id : 0);
13960
13961         drm_object_property_set_value(&crtc->base,
13962                                       config->gamma_lut_property,
13963                                       (state->gamma_lut) ?
13964                                       state->gamma_lut->base.id : 0);
13965
13966         return 0;
13967 }
13968
13969 static const struct drm_crtc_funcs intel_crtc_funcs = {
13970         .gamma_set = intel_atomic_legacy_gamma_set,
13971         .set_config = drm_atomic_helper_set_config,
13972         .set_property = drm_atomic_helper_crtc_set_property,
13973         .destroy = intel_crtc_destroy,
13974         .page_flip = intel_crtc_page_flip,
13975         .atomic_duplicate_state = intel_crtc_duplicate_state,
13976         .atomic_destroy_state = intel_crtc_destroy_state,
13977 };
13978
13979 /**
13980  * intel_prepare_plane_fb - Prepare fb for usage on plane
13981  * @plane: drm plane to prepare for
13982  * @fb: framebuffer to prepare for presentation
13983  *
13984  * Prepares a framebuffer for usage on a display plane.  Generally this
13985  * involves pinning the underlying object and updating the frontbuffer tracking
13986  * bits.  Some older platforms need special physical address handling for
13987  * cursor planes.
13988  *
13989  * Must be called with struct_mutex held.
13990  *
13991  * Returns 0 on success, negative error code on failure.
13992  */
13993 int
13994 intel_prepare_plane_fb(struct drm_plane *plane,
13995                        const struct drm_plane_state *new_state)
13996 {
13997         struct drm_device *dev = plane->dev;
13998         struct drm_framebuffer *fb = new_state->fb;
13999         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14000         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14001         struct reservation_object *resv;
14002         int ret = 0;
14003
14004         if (!obj && !old_obj)
14005                 return 0;
14006
14007         if (old_obj) {
14008                 struct drm_crtc_state *crtc_state =
14009                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14010
14011                 /* Big Hammer, we also need to ensure that any pending
14012                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14013                  * current scanout is retired before unpinning the old
14014                  * framebuffer. Note that we rely on userspace rendering
14015                  * into the buffer attached to the pipe they are waiting
14016                  * on. If not, userspace generates a GPU hang with IPEHR
14017                  * point to the MI_WAIT_FOR_EVENT.
14018                  *
14019                  * This should only fail upon a hung GPU, in which case we
14020                  * can safely continue.
14021                  */
14022                 if (needs_modeset(crtc_state))
14023                         ret = i915_gem_object_wait_rendering(old_obj, true);
14024                 if (ret) {
14025                         /* GPU hangs should have been swallowed by the wait */
14026                         WARN_ON(ret == -EIO);
14027                         return ret;
14028                 }
14029         }
14030
14031         if (!obj)
14032                 return 0;
14033
14034         /* For framebuffer backed by dmabuf, wait for fence */
14035         resv = i915_gem_object_get_dmabuf_resv(obj);
14036         if (resv) {
14037                 long lret;
14038
14039                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14040                                                            MAX_SCHEDULE_TIMEOUT);
14041                 if (lret == -ERESTARTSYS)
14042                         return lret;
14043
14044                 WARN(lret < 0, "waiting returns %li\n", lret);
14045         }
14046
14047         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14048             INTEL_INFO(dev)->cursor_needs_physical) {
14049                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14050                 ret = i915_gem_object_attach_phys(obj, align);
14051                 if (ret)
14052                         DRM_DEBUG_KMS("failed to attach phys object\n");
14053         } else {
14054                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14055         }
14056
14057         if (ret == 0) {
14058                 struct intel_plane_state *plane_state =
14059                         to_intel_plane_state(new_state);
14060
14061                 i915_gem_request_assign(&plane_state->wait_req,
14062                                         obj->last_write_req);
14063         }
14064
14065         return ret;
14066 }
14067
14068 /**
14069  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14070  * @plane: drm plane to clean up for
14071  * @fb: old framebuffer that was on plane
14072  *
14073  * Cleans up a framebuffer that has just been removed from a plane.
14074  *
14075  * Must be called with struct_mutex held.
14076  */
14077 void
14078 intel_cleanup_plane_fb(struct drm_plane *plane,
14079                        const struct drm_plane_state *old_state)
14080 {
14081         struct drm_device *dev = plane->dev;
14082         struct intel_plane_state *old_intel_state;
14083         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14084         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14085
14086         old_intel_state = to_intel_plane_state(old_state);
14087
14088         if (!obj && !old_obj)
14089                 return;
14090
14091         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14092             !INTEL_INFO(dev)->cursor_needs_physical))
14093                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14094
14095         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14096 }
14097
14098 int
14099 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14100 {
14101         int max_scale;
14102         int crtc_clock, cdclk;
14103
14104         if (!intel_crtc || !crtc_state->base.enable)
14105                 return DRM_PLANE_HELPER_NO_SCALING;
14106
14107         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14108         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14109
14110         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14111                 return DRM_PLANE_HELPER_NO_SCALING;
14112
14113         /*
14114          * skl max scale is lower of:
14115          *    close to 3 but not 3, -1 is for that purpose
14116          *            or
14117          *    cdclk/crtc_clock
14118          */
14119         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14120
14121         return max_scale;
14122 }
14123
14124 static int
14125 intel_check_primary_plane(struct drm_plane *plane,
14126                           struct intel_crtc_state *crtc_state,
14127                           struct intel_plane_state *state)
14128 {
14129         struct drm_crtc *crtc = state->base.crtc;
14130         struct drm_framebuffer *fb = state->base.fb;
14131         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14132         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14133         bool can_position = false;
14134
14135         if (INTEL_INFO(plane->dev)->gen >= 9) {
14136                 /* use scaler when colorkey is not required */
14137                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14138                         min_scale = 1;
14139                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14140                 }
14141                 can_position = true;
14142         }
14143
14144         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14145                                              &state->dst, &state->clip,
14146                                              state->base.rotation,
14147                                              min_scale, max_scale,
14148                                              can_position, true,
14149                                              &state->visible);
14150 }
14151
14152 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14153                                     struct drm_crtc_state *old_crtc_state)
14154 {
14155         struct drm_device *dev = crtc->dev;
14156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14157         struct intel_crtc_state *old_intel_state =
14158                 to_intel_crtc_state(old_crtc_state);
14159         bool modeset = needs_modeset(crtc->state);
14160
14161         /* Perform vblank evasion around commit operation */
14162         intel_pipe_update_start(intel_crtc);
14163
14164         if (modeset)
14165                 return;
14166
14167         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14168                 intel_color_set_csc(crtc->state);
14169                 intel_color_load_luts(crtc->state);
14170         }
14171
14172         if (to_intel_crtc_state(crtc->state)->update_pipe)
14173                 intel_update_pipe_config(intel_crtc, old_intel_state);
14174         else if (INTEL_INFO(dev)->gen >= 9)
14175                 skl_detach_scalers(intel_crtc);
14176 }
14177
14178 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14179                                      struct drm_crtc_state *old_crtc_state)
14180 {
14181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14182
14183         intel_pipe_update_end(intel_crtc, NULL);
14184 }
14185
14186 /**
14187  * intel_plane_destroy - destroy a plane
14188  * @plane: plane to destroy
14189  *
14190  * Common destruction function for all types of planes (primary, cursor,
14191  * sprite).
14192  */
14193 void intel_plane_destroy(struct drm_plane *plane)
14194 {
14195         if (!plane)
14196                 return;
14197
14198         drm_plane_cleanup(plane);
14199         kfree(to_intel_plane(plane));
14200 }
14201
14202 const struct drm_plane_funcs intel_plane_funcs = {
14203         .update_plane = drm_atomic_helper_update_plane,
14204         .disable_plane = drm_atomic_helper_disable_plane,
14205         .destroy = intel_plane_destroy,
14206         .set_property = drm_atomic_helper_plane_set_property,
14207         .atomic_get_property = intel_plane_atomic_get_property,
14208         .atomic_set_property = intel_plane_atomic_set_property,
14209         .atomic_duplicate_state = intel_plane_duplicate_state,
14210         .atomic_destroy_state = intel_plane_destroy_state,
14211
14212 };
14213
14214 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14215                                                     int pipe)
14216 {
14217         struct intel_plane *primary = NULL;
14218         struct intel_plane_state *state = NULL;
14219         const uint32_t *intel_primary_formats;
14220         unsigned int num_formats;
14221         int ret;
14222
14223         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14224         if (!primary)
14225                 goto fail;
14226
14227         state = intel_create_plane_state(&primary->base);
14228         if (!state)
14229                 goto fail;
14230         primary->base.state = &state->base;
14231
14232         primary->can_scale = false;
14233         primary->max_downscale = 1;
14234         if (INTEL_INFO(dev)->gen >= 9) {
14235                 primary->can_scale = true;
14236                 state->scaler_id = -1;
14237         }
14238         primary->pipe = pipe;
14239         primary->plane = pipe;
14240         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14241         primary->check_plane = intel_check_primary_plane;
14242         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14243                 primary->plane = !pipe;
14244
14245         if (INTEL_INFO(dev)->gen >= 9) {
14246                 intel_primary_formats = skl_primary_formats;
14247                 num_formats = ARRAY_SIZE(skl_primary_formats);
14248
14249                 primary->update_plane = skylake_update_primary_plane;
14250                 primary->disable_plane = skylake_disable_primary_plane;
14251         } else if (HAS_PCH_SPLIT(dev)) {
14252                 intel_primary_formats = i965_primary_formats;
14253                 num_formats = ARRAY_SIZE(i965_primary_formats);
14254
14255                 primary->update_plane = ironlake_update_primary_plane;
14256                 primary->disable_plane = i9xx_disable_primary_plane;
14257         } else if (INTEL_INFO(dev)->gen >= 4) {
14258                 intel_primary_formats = i965_primary_formats;
14259                 num_formats = ARRAY_SIZE(i965_primary_formats);
14260
14261                 primary->update_plane = i9xx_update_primary_plane;
14262                 primary->disable_plane = i9xx_disable_primary_plane;
14263         } else {
14264                 intel_primary_formats = i8xx_primary_formats;
14265                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14266
14267                 primary->update_plane = i9xx_update_primary_plane;
14268                 primary->disable_plane = i9xx_disable_primary_plane;
14269         }
14270
14271         if (INTEL_INFO(dev)->gen >= 9)
14272                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14273                                                &intel_plane_funcs,
14274                                                intel_primary_formats, num_formats,
14275                                                DRM_PLANE_TYPE_PRIMARY,
14276                                                "plane 1%c", pipe_name(pipe));
14277         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14278                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14279                                                &intel_plane_funcs,
14280                                                intel_primary_formats, num_formats,
14281                                                DRM_PLANE_TYPE_PRIMARY,
14282                                                "primary %c", pipe_name(pipe));
14283         else
14284                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14285                                                &intel_plane_funcs,
14286                                                intel_primary_formats, num_formats,
14287                                                DRM_PLANE_TYPE_PRIMARY,
14288                                                "plane %c", plane_name(primary->plane));
14289         if (ret)
14290                 goto fail;
14291
14292         if (INTEL_INFO(dev)->gen >= 4)
14293                 intel_create_rotation_property(dev, primary);
14294
14295         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14296
14297         return &primary->base;
14298
14299 fail:
14300         kfree(state);
14301         kfree(primary);
14302
14303         return NULL;
14304 }
14305
14306 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14307 {
14308         if (!dev->mode_config.rotation_property) {
14309                 unsigned long flags = BIT(DRM_ROTATE_0) |
14310                         BIT(DRM_ROTATE_180);
14311
14312                 if (INTEL_INFO(dev)->gen >= 9)
14313                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14314
14315                 dev->mode_config.rotation_property =
14316                         drm_mode_create_rotation_property(dev, flags);
14317         }
14318         if (dev->mode_config.rotation_property)
14319                 drm_object_attach_property(&plane->base.base,
14320                                 dev->mode_config.rotation_property,
14321                                 plane->base.state->rotation);
14322 }
14323
14324 static int
14325 intel_check_cursor_plane(struct drm_plane *plane,
14326                          struct intel_crtc_state *crtc_state,
14327                          struct intel_plane_state *state)
14328 {
14329         struct drm_crtc *crtc = crtc_state->base.crtc;
14330         struct drm_framebuffer *fb = state->base.fb;
14331         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14332         enum pipe pipe = to_intel_plane(plane)->pipe;
14333         unsigned stride;
14334         int ret;
14335
14336         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14337                                             &state->dst, &state->clip,
14338                                             state->base.rotation,
14339                                             DRM_PLANE_HELPER_NO_SCALING,
14340                                             DRM_PLANE_HELPER_NO_SCALING,
14341                                             true, true, &state->visible);
14342         if (ret)
14343                 return ret;
14344
14345         /* if we want to turn off the cursor ignore width and height */
14346         if (!obj)
14347                 return 0;
14348
14349         /* Check for which cursor types we support */
14350         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14351                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14352                           state->base.crtc_w, state->base.crtc_h);
14353                 return -EINVAL;
14354         }
14355
14356         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14357         if (obj->base.size < stride * state->base.crtc_h) {
14358                 DRM_DEBUG_KMS("buffer is too small\n");
14359                 return -ENOMEM;
14360         }
14361
14362         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14363                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14364                 return -EINVAL;
14365         }
14366
14367         /*
14368          * There's something wrong with the cursor on CHV pipe C.
14369          * If it straddles the left edge of the screen then
14370          * moving it away from the edge or disabling it often
14371          * results in a pipe underrun, and often that can lead to
14372          * dead pipe (constant underrun reported, and it scans
14373          * out just a solid color). To recover from that, the
14374          * display power well must be turned off and on again.
14375          * Refuse the put the cursor into that compromised position.
14376          */
14377         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14378             state->visible && state->base.crtc_x < 0) {
14379                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14380                 return -EINVAL;
14381         }
14382
14383         return 0;
14384 }
14385
14386 static void
14387 intel_disable_cursor_plane(struct drm_plane *plane,
14388                            struct drm_crtc *crtc)
14389 {
14390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14391
14392         intel_crtc->cursor_addr = 0;
14393         intel_crtc_update_cursor(crtc, NULL);
14394 }
14395
14396 static void
14397 intel_update_cursor_plane(struct drm_plane *plane,
14398                           const struct intel_crtc_state *crtc_state,
14399                           const struct intel_plane_state *state)
14400 {
14401         struct drm_crtc *crtc = crtc_state->base.crtc;
14402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14403         struct drm_device *dev = plane->dev;
14404         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14405         uint32_t addr;
14406
14407         if (!obj)
14408                 addr = 0;
14409         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14410                 addr = i915_gem_obj_ggtt_offset(obj);
14411         else
14412                 addr = obj->phys_handle->busaddr;
14413
14414         intel_crtc->cursor_addr = addr;
14415         intel_crtc_update_cursor(crtc, state);
14416 }
14417
14418 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14419                                                    int pipe)
14420 {
14421         struct intel_plane *cursor = NULL;
14422         struct intel_plane_state *state = NULL;
14423         int ret;
14424
14425         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14426         if (!cursor)
14427                 goto fail;
14428
14429         state = intel_create_plane_state(&cursor->base);
14430         if (!state)
14431                 goto fail;
14432         cursor->base.state = &state->base;
14433
14434         cursor->can_scale = false;
14435         cursor->max_downscale = 1;
14436         cursor->pipe = pipe;
14437         cursor->plane = pipe;
14438         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14439         cursor->check_plane = intel_check_cursor_plane;
14440         cursor->update_plane = intel_update_cursor_plane;
14441         cursor->disable_plane = intel_disable_cursor_plane;
14442
14443         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14444                                        &intel_plane_funcs,
14445                                        intel_cursor_formats,
14446                                        ARRAY_SIZE(intel_cursor_formats),
14447                                        DRM_PLANE_TYPE_CURSOR,
14448                                        "cursor %c", pipe_name(pipe));
14449         if (ret)
14450                 goto fail;
14451
14452         if (INTEL_INFO(dev)->gen >= 4) {
14453                 if (!dev->mode_config.rotation_property)
14454                         dev->mode_config.rotation_property =
14455                                 drm_mode_create_rotation_property(dev,
14456                                                         BIT(DRM_ROTATE_0) |
14457                                                         BIT(DRM_ROTATE_180));
14458                 if (dev->mode_config.rotation_property)
14459                         drm_object_attach_property(&cursor->base.base,
14460                                 dev->mode_config.rotation_property,
14461                                 state->base.rotation);
14462         }
14463
14464         if (INTEL_INFO(dev)->gen >=9)
14465                 state->scaler_id = -1;
14466
14467         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14468
14469         return &cursor->base;
14470
14471 fail:
14472         kfree(state);
14473         kfree(cursor);
14474
14475         return NULL;
14476 }
14477
14478 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14479         struct intel_crtc_state *crtc_state)
14480 {
14481         int i;
14482         struct intel_scaler *intel_scaler;
14483         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14484
14485         for (i = 0; i < intel_crtc->num_scalers; i++) {
14486                 intel_scaler = &scaler_state->scalers[i];
14487                 intel_scaler->in_use = 0;
14488                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14489         }
14490
14491         scaler_state->scaler_id = -1;
14492 }
14493
14494 static void intel_crtc_init(struct drm_device *dev, int pipe)
14495 {
14496         struct drm_i915_private *dev_priv = to_i915(dev);
14497         struct intel_crtc *intel_crtc;
14498         struct intel_crtc_state *crtc_state = NULL;
14499         struct drm_plane *primary = NULL;
14500         struct drm_plane *cursor = NULL;
14501         int ret;
14502
14503         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14504         if (intel_crtc == NULL)
14505                 return;
14506
14507         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14508         if (!crtc_state)
14509                 goto fail;
14510         intel_crtc->config = crtc_state;
14511         intel_crtc->base.state = &crtc_state->base;
14512         crtc_state->base.crtc = &intel_crtc->base;
14513
14514         /* initialize shared scalers */
14515         if (INTEL_INFO(dev)->gen >= 9) {
14516                 if (pipe == PIPE_C)
14517                         intel_crtc->num_scalers = 1;
14518                 else
14519                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14520
14521                 skl_init_scalers(dev, intel_crtc, crtc_state);
14522         }
14523
14524         primary = intel_primary_plane_create(dev, pipe);
14525         if (!primary)
14526                 goto fail;
14527
14528         cursor = intel_cursor_plane_create(dev, pipe);
14529         if (!cursor)
14530                 goto fail;
14531
14532         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14533                                         cursor, &intel_crtc_funcs,
14534                                         "pipe %c", pipe_name(pipe));
14535         if (ret)
14536                 goto fail;
14537
14538         /*
14539          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14540          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14541          */
14542         intel_crtc->pipe = pipe;
14543         intel_crtc->plane = pipe;
14544         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14545                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14546                 intel_crtc->plane = !pipe;
14547         }
14548
14549         intel_crtc->cursor_base = ~0;
14550         intel_crtc->cursor_cntl = ~0;
14551         intel_crtc->cursor_size = ~0;
14552
14553         intel_crtc->wm.cxsr_allowed = true;
14554
14555         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14556                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14557         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14558         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14559
14560         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14561
14562         intel_color_init(&intel_crtc->base);
14563
14564         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14565         return;
14566
14567 fail:
14568         intel_plane_destroy(primary);
14569         intel_plane_destroy(cursor);
14570         kfree(crtc_state);
14571         kfree(intel_crtc);
14572 }
14573
14574 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14575 {
14576         struct drm_encoder *encoder = connector->base.encoder;
14577         struct drm_device *dev = connector->base.dev;
14578
14579         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14580
14581         if (!encoder || WARN_ON(!encoder->crtc))
14582                 return INVALID_PIPE;
14583
14584         return to_intel_crtc(encoder->crtc)->pipe;
14585 }
14586
14587 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14588                                 struct drm_file *file)
14589 {
14590         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14591         struct drm_crtc *drmmode_crtc;
14592         struct intel_crtc *crtc;
14593
14594         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14595         if (!drmmode_crtc)
14596                 return -ENOENT;
14597
14598         crtc = to_intel_crtc(drmmode_crtc);
14599         pipe_from_crtc_id->pipe = crtc->pipe;
14600
14601         return 0;
14602 }
14603
14604 static int intel_encoder_clones(struct intel_encoder *encoder)
14605 {
14606         struct drm_device *dev = encoder->base.dev;
14607         struct intel_encoder *source_encoder;
14608         int index_mask = 0;
14609         int entry = 0;
14610
14611         for_each_intel_encoder(dev, source_encoder) {
14612                 if (encoders_cloneable(encoder, source_encoder))
14613                         index_mask |= (1 << entry);
14614
14615                 entry++;
14616         }
14617
14618         return index_mask;
14619 }
14620
14621 static bool has_edp_a(struct drm_device *dev)
14622 {
14623         struct drm_i915_private *dev_priv = to_i915(dev);
14624
14625         if (!IS_MOBILE(dev))
14626                 return false;
14627
14628         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14629                 return false;
14630
14631         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14632                 return false;
14633
14634         return true;
14635 }
14636
14637 static bool intel_crt_present(struct drm_device *dev)
14638 {
14639         struct drm_i915_private *dev_priv = to_i915(dev);
14640
14641         if (INTEL_INFO(dev)->gen >= 9)
14642                 return false;
14643
14644         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14645                 return false;
14646
14647         if (IS_CHERRYVIEW(dev))
14648                 return false;
14649
14650         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14651                 return false;
14652
14653         /* DDI E can't be used if DDI A requires 4 lanes */
14654         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14655                 return false;
14656
14657         if (!dev_priv->vbt.int_crt_support)
14658                 return false;
14659
14660         return true;
14661 }
14662
14663 static void intel_setup_outputs(struct drm_device *dev)
14664 {
14665         struct drm_i915_private *dev_priv = to_i915(dev);
14666         struct intel_encoder *encoder;
14667         bool dpd_is_edp = false;
14668
14669         /*
14670          * intel_edp_init_connector() depends on this completing first, to
14671          * prevent the registeration of both eDP and LVDS and the incorrect
14672          * sharing of the PPS.
14673          */
14674         intel_lvds_init(dev);
14675
14676         if (intel_crt_present(dev))
14677                 intel_crt_init(dev);
14678
14679         if (IS_BROXTON(dev)) {
14680                 /*
14681                  * FIXME: Broxton doesn't support port detection via the
14682                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14683                  * detect the ports.
14684                  */
14685                 intel_ddi_init(dev, PORT_A);
14686                 intel_ddi_init(dev, PORT_B);
14687                 intel_ddi_init(dev, PORT_C);
14688
14689                 intel_dsi_init(dev);
14690         } else if (HAS_DDI(dev)) {
14691                 int found;
14692
14693                 /*
14694                  * Haswell uses DDI functions to detect digital outputs.
14695                  * On SKL pre-D0 the strap isn't connected, so we assume
14696                  * it's there.
14697                  */
14698                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14699                 /* WaIgnoreDDIAStrap: skl */
14700                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14701                         intel_ddi_init(dev, PORT_A);
14702
14703                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14704                  * register */
14705                 found = I915_READ(SFUSE_STRAP);
14706
14707                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14708                         intel_ddi_init(dev, PORT_B);
14709                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14710                         intel_ddi_init(dev, PORT_C);
14711                 if (found & SFUSE_STRAP_DDID_DETECTED)
14712                         intel_ddi_init(dev, PORT_D);
14713                 /*
14714                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14715                  */
14716                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14717                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14718                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14719                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14720                         intel_ddi_init(dev, PORT_E);
14721
14722         } else if (HAS_PCH_SPLIT(dev)) {
14723                 int found;
14724                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14725
14726                 if (has_edp_a(dev))
14727                         intel_dp_init(dev, DP_A, PORT_A);
14728
14729                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14730                         /* PCH SDVOB multiplex with HDMIB */
14731                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14732                         if (!found)
14733                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14734                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14735                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14736                 }
14737
14738                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14739                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14740
14741                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14742                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14743
14744                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14745                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14746
14747                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14748                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14749         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14750                 bool has_edp, has_port;
14751
14752                 /*
14753                  * The DP_DETECTED bit is the latched state of the DDC
14754                  * SDA pin at boot. However since eDP doesn't require DDC
14755                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14756                  * eDP ports may have been muxed to an alternate function.
14757                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14758                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14759                  * detect eDP ports.
14760                  *
14761                  * Sadly the straps seem to be missing sometimes even for HDMI
14762                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14763                  * and VBT for the presence of the port. Additionally we can't
14764                  * trust the port type the VBT declares as we've seen at least
14765                  * HDMI ports that the VBT claim are DP or eDP.
14766                  */
14767                 has_edp = intel_dp_is_edp(dev, PORT_B);
14768                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14769                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14770                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14771                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14772                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14773
14774                 has_edp = intel_dp_is_edp(dev, PORT_C);
14775                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14776                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14777                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14778                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14779                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14780
14781                 if (IS_CHERRYVIEW(dev)) {
14782                         /*
14783                          * eDP not supported on port D,
14784                          * so no need to worry about it
14785                          */
14786                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14787                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14788                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14789                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14790                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14791                 }
14792
14793                 intel_dsi_init(dev);
14794         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14795                 bool found = false;
14796
14797                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14798                         DRM_DEBUG_KMS("probing SDVOB\n");
14799                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14800                         if (!found && IS_G4X(dev)) {
14801                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14802                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14803                         }
14804
14805                         if (!found && IS_G4X(dev))
14806                                 intel_dp_init(dev, DP_B, PORT_B);
14807                 }
14808
14809                 /* Before G4X SDVOC doesn't have its own detect register */
14810
14811                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14812                         DRM_DEBUG_KMS("probing SDVOC\n");
14813                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14814                 }
14815
14816                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14817
14818                         if (IS_G4X(dev)) {
14819                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14820                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14821                         }
14822                         if (IS_G4X(dev))
14823                                 intel_dp_init(dev, DP_C, PORT_C);
14824                 }
14825
14826                 if (IS_G4X(dev) &&
14827                     (I915_READ(DP_D) & DP_DETECTED))
14828                         intel_dp_init(dev, DP_D, PORT_D);
14829         } else if (IS_GEN2(dev))
14830                 intel_dvo_init(dev);
14831
14832         if (SUPPORTS_TV(dev))
14833                 intel_tv_init(dev);
14834
14835         intel_psr_init(dev);
14836
14837         for_each_intel_encoder(dev, encoder) {
14838                 encoder->base.possible_crtcs = encoder->crtc_mask;
14839                 encoder->base.possible_clones =
14840                         intel_encoder_clones(encoder);
14841         }
14842
14843         intel_init_pch_refclk(dev);
14844
14845         drm_helper_move_panel_connectors_to_head(dev);
14846 }
14847
14848 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14849 {
14850         struct drm_device *dev = fb->dev;
14851         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14852
14853         drm_framebuffer_cleanup(fb);
14854         mutex_lock(&dev->struct_mutex);
14855         WARN_ON(!intel_fb->obj->framebuffer_references--);
14856         drm_gem_object_unreference(&intel_fb->obj->base);
14857         mutex_unlock(&dev->struct_mutex);
14858         kfree(intel_fb);
14859 }
14860
14861 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14862                                                 struct drm_file *file,
14863                                                 unsigned int *handle)
14864 {
14865         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14866         struct drm_i915_gem_object *obj = intel_fb->obj;
14867
14868         if (obj->userptr.mm) {
14869                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14870                 return -EINVAL;
14871         }
14872
14873         return drm_gem_handle_create(file, &obj->base, handle);
14874 }
14875
14876 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14877                                         struct drm_file *file,
14878                                         unsigned flags, unsigned color,
14879                                         struct drm_clip_rect *clips,
14880                                         unsigned num_clips)
14881 {
14882         struct drm_device *dev = fb->dev;
14883         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14884         struct drm_i915_gem_object *obj = intel_fb->obj;
14885
14886         mutex_lock(&dev->struct_mutex);
14887         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14888         mutex_unlock(&dev->struct_mutex);
14889
14890         return 0;
14891 }
14892
14893 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14894         .destroy = intel_user_framebuffer_destroy,
14895         .create_handle = intel_user_framebuffer_create_handle,
14896         .dirty = intel_user_framebuffer_dirty,
14897 };
14898
14899 static
14900 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14901                          uint32_t pixel_format)
14902 {
14903         u32 gen = INTEL_INFO(dev)->gen;
14904
14905         if (gen >= 9) {
14906                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14907
14908                 /* "The stride in bytes must not exceed the of the size of 8K
14909                  *  pixels and 32K bytes."
14910                  */
14911                 return min(8192 * cpp, 32768);
14912         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14913                 return 32*1024;
14914         } else if (gen >= 4) {
14915                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14916                         return 16*1024;
14917                 else
14918                         return 32*1024;
14919         } else if (gen >= 3) {
14920                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14921                         return 8*1024;
14922                 else
14923                         return 16*1024;
14924         } else {
14925                 /* XXX DSPC is limited to 4k tiled */
14926                 return 8*1024;
14927         }
14928 }
14929
14930 static int intel_framebuffer_init(struct drm_device *dev,
14931                                   struct intel_framebuffer *intel_fb,
14932                                   struct drm_mode_fb_cmd2 *mode_cmd,
14933                                   struct drm_i915_gem_object *obj)
14934 {
14935         struct drm_i915_private *dev_priv = to_i915(dev);
14936         unsigned int aligned_height;
14937         int ret;
14938         u32 pitch_limit, stride_alignment;
14939
14940         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14941
14942         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14943                 /* Enforce that fb modifier and tiling mode match, but only for
14944                  * X-tiled. This is needed for FBC. */
14945                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14946                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14947                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14948                         return -EINVAL;
14949                 }
14950         } else {
14951                 if (obj->tiling_mode == I915_TILING_X)
14952                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14953                 else if (obj->tiling_mode == I915_TILING_Y) {
14954                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14955                         return -EINVAL;
14956                 }
14957         }
14958
14959         /* Passed in modifier sanity checking. */
14960         switch (mode_cmd->modifier[0]) {
14961         case I915_FORMAT_MOD_Y_TILED:
14962         case I915_FORMAT_MOD_Yf_TILED:
14963                 if (INTEL_INFO(dev)->gen < 9) {
14964                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14965                                   mode_cmd->modifier[0]);
14966                         return -EINVAL;
14967                 }
14968         case DRM_FORMAT_MOD_NONE:
14969         case I915_FORMAT_MOD_X_TILED:
14970                 break;
14971         default:
14972                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14973                           mode_cmd->modifier[0]);
14974                 return -EINVAL;
14975         }
14976
14977         stride_alignment = intel_fb_stride_alignment(dev_priv,
14978                                                      mode_cmd->modifier[0],
14979                                                      mode_cmd->pixel_format);
14980         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14981                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14982                           mode_cmd->pitches[0], stride_alignment);
14983                 return -EINVAL;
14984         }
14985
14986         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14987                                            mode_cmd->pixel_format);
14988         if (mode_cmd->pitches[0] > pitch_limit) {
14989                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14990                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14991                           "tiled" : "linear",
14992                           mode_cmd->pitches[0], pitch_limit);
14993                 return -EINVAL;
14994         }
14995
14996         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14997             mode_cmd->pitches[0] != obj->stride) {
14998                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14999                           mode_cmd->pitches[0], obj->stride);
15000                 return -EINVAL;
15001         }
15002
15003         /* Reject formats not supported by any plane early. */
15004         switch (mode_cmd->pixel_format) {
15005         case DRM_FORMAT_C8:
15006         case DRM_FORMAT_RGB565:
15007         case DRM_FORMAT_XRGB8888:
15008         case DRM_FORMAT_ARGB8888:
15009                 break;
15010         case DRM_FORMAT_XRGB1555:
15011                 if (INTEL_INFO(dev)->gen > 3) {
15012                         DRM_DEBUG("unsupported pixel format: %s\n",
15013                                   drm_get_format_name(mode_cmd->pixel_format));
15014                         return -EINVAL;
15015                 }
15016                 break;
15017         case DRM_FORMAT_ABGR8888:
15018                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15019                     INTEL_INFO(dev)->gen < 9) {
15020                         DRM_DEBUG("unsupported pixel format: %s\n",
15021                                   drm_get_format_name(mode_cmd->pixel_format));
15022                         return -EINVAL;
15023                 }
15024                 break;
15025         case DRM_FORMAT_XBGR8888:
15026         case DRM_FORMAT_XRGB2101010:
15027         case DRM_FORMAT_XBGR2101010:
15028                 if (INTEL_INFO(dev)->gen < 4) {
15029                         DRM_DEBUG("unsupported pixel format: %s\n",
15030                                   drm_get_format_name(mode_cmd->pixel_format));
15031                         return -EINVAL;
15032                 }
15033                 break;
15034         case DRM_FORMAT_ABGR2101010:
15035                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15036                         DRM_DEBUG("unsupported pixel format: %s\n",
15037                                   drm_get_format_name(mode_cmd->pixel_format));
15038                         return -EINVAL;
15039                 }
15040                 break;
15041         case DRM_FORMAT_YUYV:
15042         case DRM_FORMAT_UYVY:
15043         case DRM_FORMAT_YVYU:
15044         case DRM_FORMAT_VYUY:
15045                 if (INTEL_INFO(dev)->gen < 5) {
15046                         DRM_DEBUG("unsupported pixel format: %s\n",
15047                                   drm_get_format_name(mode_cmd->pixel_format));
15048                         return -EINVAL;
15049                 }
15050                 break;
15051         default:
15052                 DRM_DEBUG("unsupported pixel format: %s\n",
15053                           drm_get_format_name(mode_cmd->pixel_format));
15054                 return -EINVAL;
15055         }
15056
15057         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15058         if (mode_cmd->offsets[0] != 0)
15059                 return -EINVAL;
15060
15061         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15062                                                mode_cmd->pixel_format,
15063                                                mode_cmd->modifier[0]);
15064         /* FIXME drm helper for size checks (especially planar formats)? */
15065         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15066                 return -EINVAL;
15067
15068         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15069         intel_fb->obj = obj;
15070
15071         intel_fill_fb_info(dev_priv, &intel_fb->base);
15072
15073         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15074         if (ret) {
15075                 DRM_ERROR("framebuffer init failed %d\n", ret);
15076                 return ret;
15077         }
15078
15079         intel_fb->obj->framebuffer_references++;
15080
15081         return 0;
15082 }
15083
15084 static struct drm_framebuffer *
15085 intel_user_framebuffer_create(struct drm_device *dev,
15086                               struct drm_file *filp,
15087                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15088 {
15089         struct drm_framebuffer *fb;
15090         struct drm_i915_gem_object *obj;
15091         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15092
15093         obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15094         if (&obj->base == NULL)
15095                 return ERR_PTR(-ENOENT);
15096
15097         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15098         if (IS_ERR(fb))
15099                 drm_gem_object_unreference_unlocked(&obj->base);
15100
15101         return fb;
15102 }
15103
15104 #ifndef CONFIG_DRM_FBDEV_EMULATION
15105 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15106 {
15107 }
15108 #endif
15109
15110 static const struct drm_mode_config_funcs intel_mode_funcs = {
15111         .fb_create = intel_user_framebuffer_create,
15112         .output_poll_changed = intel_fbdev_output_poll_changed,
15113         .atomic_check = intel_atomic_check,
15114         .atomic_commit = intel_atomic_commit,
15115         .atomic_state_alloc = intel_atomic_state_alloc,
15116         .atomic_state_clear = intel_atomic_state_clear,
15117 };
15118
15119 /**
15120  * intel_init_display_hooks - initialize the display modesetting hooks
15121  * @dev_priv: device private
15122  */
15123 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15124 {
15125         if (INTEL_INFO(dev_priv)->gen >= 9) {
15126                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15127                 dev_priv->display.get_initial_plane_config =
15128                         skylake_get_initial_plane_config;
15129                 dev_priv->display.crtc_compute_clock =
15130                         haswell_crtc_compute_clock;
15131                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15132                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15133         } else if (HAS_DDI(dev_priv)) {
15134                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15135                 dev_priv->display.get_initial_plane_config =
15136                         ironlake_get_initial_plane_config;
15137                 dev_priv->display.crtc_compute_clock =
15138                         haswell_crtc_compute_clock;
15139                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15140                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15141         } else if (HAS_PCH_SPLIT(dev_priv)) {
15142                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15143                 dev_priv->display.get_initial_plane_config =
15144                         ironlake_get_initial_plane_config;
15145                 dev_priv->display.crtc_compute_clock =
15146                         ironlake_crtc_compute_clock;
15147                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15148                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15149         } else if (IS_CHERRYVIEW(dev_priv)) {
15150                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15151                 dev_priv->display.get_initial_plane_config =
15152                         i9xx_get_initial_plane_config;
15153                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15154                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15155                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15156         } else if (IS_VALLEYVIEW(dev_priv)) {
15157                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15158                 dev_priv->display.get_initial_plane_config =
15159                         i9xx_get_initial_plane_config;
15160                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15161                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15162                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15163         } else if (IS_G4X(dev_priv)) {
15164                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15165                 dev_priv->display.get_initial_plane_config =
15166                         i9xx_get_initial_plane_config;
15167                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15168                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15169                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15170         } else if (IS_PINEVIEW(dev_priv)) {
15171                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15172                 dev_priv->display.get_initial_plane_config =
15173                         i9xx_get_initial_plane_config;
15174                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15175                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15176                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15177         } else if (!IS_GEN2(dev_priv)) {
15178                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15179                 dev_priv->display.get_initial_plane_config =
15180                         i9xx_get_initial_plane_config;
15181                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15182                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15183                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15184         } else {
15185                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15186                 dev_priv->display.get_initial_plane_config =
15187                         i9xx_get_initial_plane_config;
15188                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15189                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15190                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15191         }
15192
15193         /* Returns the core display clock speed */
15194         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15195                 dev_priv->display.get_display_clock_speed =
15196                         skylake_get_display_clock_speed;
15197         else if (IS_BROXTON(dev_priv))
15198                 dev_priv->display.get_display_clock_speed =
15199                         broxton_get_display_clock_speed;
15200         else if (IS_BROADWELL(dev_priv))
15201                 dev_priv->display.get_display_clock_speed =
15202                         broadwell_get_display_clock_speed;
15203         else if (IS_HASWELL(dev_priv))
15204                 dev_priv->display.get_display_clock_speed =
15205                         haswell_get_display_clock_speed;
15206         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15207                 dev_priv->display.get_display_clock_speed =
15208                         valleyview_get_display_clock_speed;
15209         else if (IS_GEN5(dev_priv))
15210                 dev_priv->display.get_display_clock_speed =
15211                         ilk_get_display_clock_speed;
15212         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15213                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15214                 dev_priv->display.get_display_clock_speed =
15215                         i945_get_display_clock_speed;
15216         else if (IS_GM45(dev_priv))
15217                 dev_priv->display.get_display_clock_speed =
15218                         gm45_get_display_clock_speed;
15219         else if (IS_CRESTLINE(dev_priv))
15220                 dev_priv->display.get_display_clock_speed =
15221                         i965gm_get_display_clock_speed;
15222         else if (IS_PINEVIEW(dev_priv))
15223                 dev_priv->display.get_display_clock_speed =
15224                         pnv_get_display_clock_speed;
15225         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15226                 dev_priv->display.get_display_clock_speed =
15227                         g33_get_display_clock_speed;
15228         else if (IS_I915G(dev_priv))
15229                 dev_priv->display.get_display_clock_speed =
15230                         i915_get_display_clock_speed;
15231         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15232                 dev_priv->display.get_display_clock_speed =
15233                         i9xx_misc_get_display_clock_speed;
15234         else if (IS_I915GM(dev_priv))
15235                 dev_priv->display.get_display_clock_speed =
15236                         i915gm_get_display_clock_speed;
15237         else if (IS_I865G(dev_priv))
15238                 dev_priv->display.get_display_clock_speed =
15239                         i865_get_display_clock_speed;
15240         else if (IS_I85X(dev_priv))
15241                 dev_priv->display.get_display_clock_speed =
15242                         i85x_get_display_clock_speed;
15243         else { /* 830 */
15244                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15245                 dev_priv->display.get_display_clock_speed =
15246                         i830_get_display_clock_speed;
15247         }
15248
15249         if (IS_GEN5(dev_priv)) {
15250                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15251         } else if (IS_GEN6(dev_priv)) {
15252                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15253         } else if (IS_IVYBRIDGE(dev_priv)) {
15254                 /* FIXME: detect B0+ stepping and use auto training */
15255                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15256         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15257                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15258         }
15259
15260         if (IS_BROADWELL(dev_priv)) {
15261                 dev_priv->display.modeset_commit_cdclk =
15262                         broadwell_modeset_commit_cdclk;
15263                 dev_priv->display.modeset_calc_cdclk =
15264                         broadwell_modeset_calc_cdclk;
15265         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15266                 dev_priv->display.modeset_commit_cdclk =
15267                         valleyview_modeset_commit_cdclk;
15268                 dev_priv->display.modeset_calc_cdclk =
15269                         valleyview_modeset_calc_cdclk;
15270         } else if (IS_BROXTON(dev_priv)) {
15271                 dev_priv->display.modeset_commit_cdclk =
15272                         bxt_modeset_commit_cdclk;
15273                 dev_priv->display.modeset_calc_cdclk =
15274                         bxt_modeset_calc_cdclk;
15275         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15276                 dev_priv->display.modeset_commit_cdclk =
15277                         skl_modeset_commit_cdclk;
15278                 dev_priv->display.modeset_calc_cdclk =
15279                         skl_modeset_calc_cdclk;
15280         }
15281
15282         switch (INTEL_INFO(dev_priv)->gen) {
15283         case 2:
15284                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15285                 break;
15286
15287         case 3:
15288                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15289                 break;
15290
15291         case 4:
15292         case 5:
15293                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15294                 break;
15295
15296         case 6:
15297                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15298                 break;
15299         case 7:
15300         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15301                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15302                 break;
15303         case 9:
15304                 /* Drop through - unsupported since execlist only. */
15305         default:
15306                 /* Default just returns -ENODEV to indicate unsupported */
15307                 dev_priv->display.queue_flip = intel_default_queue_flip;
15308         }
15309 }
15310
15311 /*
15312  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15313  * resume, or other times.  This quirk makes sure that's the case for
15314  * affected systems.
15315  */
15316 static void quirk_pipea_force(struct drm_device *dev)
15317 {
15318         struct drm_i915_private *dev_priv = to_i915(dev);
15319
15320         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15321         DRM_INFO("applying pipe a force quirk\n");
15322 }
15323
15324 static void quirk_pipeb_force(struct drm_device *dev)
15325 {
15326         struct drm_i915_private *dev_priv = to_i915(dev);
15327
15328         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15329         DRM_INFO("applying pipe b force quirk\n");
15330 }
15331
15332 /*
15333  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15334  */
15335 static void quirk_ssc_force_disable(struct drm_device *dev)
15336 {
15337         struct drm_i915_private *dev_priv = to_i915(dev);
15338         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15339         DRM_INFO("applying lvds SSC disable quirk\n");
15340 }
15341
15342 /*
15343  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15344  * brightness value
15345  */
15346 static void quirk_invert_brightness(struct drm_device *dev)
15347 {
15348         struct drm_i915_private *dev_priv = to_i915(dev);
15349         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15350         DRM_INFO("applying inverted panel brightness quirk\n");
15351 }
15352
15353 /* Some VBT's incorrectly indicate no backlight is present */
15354 static void quirk_backlight_present(struct drm_device *dev)
15355 {
15356         struct drm_i915_private *dev_priv = to_i915(dev);
15357         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15358         DRM_INFO("applying backlight present quirk\n");
15359 }
15360
15361 struct intel_quirk {
15362         int device;
15363         int subsystem_vendor;
15364         int subsystem_device;
15365         void (*hook)(struct drm_device *dev);
15366 };
15367
15368 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15369 struct intel_dmi_quirk {
15370         void (*hook)(struct drm_device *dev);
15371         const struct dmi_system_id (*dmi_id_list)[];
15372 };
15373
15374 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15375 {
15376         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15377         return 1;
15378 }
15379
15380 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15381         {
15382                 .dmi_id_list = &(const struct dmi_system_id[]) {
15383                         {
15384                                 .callback = intel_dmi_reverse_brightness,
15385                                 .ident = "NCR Corporation",
15386                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15387                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15388                                 },
15389                         },
15390                         { }  /* terminating entry */
15391                 },
15392                 .hook = quirk_invert_brightness,
15393         },
15394 };
15395
15396 static struct intel_quirk intel_quirks[] = {
15397         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15398         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15399
15400         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15401         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15402
15403         /* 830 needs to leave pipe A & dpll A up */
15404         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15405
15406         /* 830 needs to leave pipe B & dpll B up */
15407         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15408
15409         /* Lenovo U160 cannot use SSC on LVDS */
15410         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15411
15412         /* Sony Vaio Y cannot use SSC on LVDS */
15413         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15414
15415         /* Acer Aspire 5734Z must invert backlight brightness */
15416         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15417
15418         /* Acer/eMachines G725 */
15419         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15420
15421         /* Acer/eMachines e725 */
15422         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15423
15424         /* Acer/Packard Bell NCL20 */
15425         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15426
15427         /* Acer Aspire 4736Z */
15428         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15429
15430         /* Acer Aspire 5336 */
15431         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15432
15433         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15434         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15435
15436         /* Acer C720 Chromebook (Core i3 4005U) */
15437         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15438
15439         /* Apple Macbook 2,1 (Core 2 T7400) */
15440         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15441
15442         /* Apple Macbook 4,1 */
15443         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15444
15445         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15446         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15447
15448         /* HP Chromebook 14 (Celeron 2955U) */
15449         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15450
15451         /* Dell Chromebook 11 */
15452         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15453
15454         /* Dell Chromebook 11 (2015 version) */
15455         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15456 };
15457
15458 static void intel_init_quirks(struct drm_device *dev)
15459 {
15460         struct pci_dev *d = dev->pdev;
15461         int i;
15462
15463         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15464                 struct intel_quirk *q = &intel_quirks[i];
15465
15466                 if (d->device == q->device &&
15467                     (d->subsystem_vendor == q->subsystem_vendor ||
15468                      q->subsystem_vendor == PCI_ANY_ID) &&
15469                     (d->subsystem_device == q->subsystem_device ||
15470                      q->subsystem_device == PCI_ANY_ID))
15471                         q->hook(dev);
15472         }
15473         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15474                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15475                         intel_dmi_quirks[i].hook(dev);
15476         }
15477 }
15478
15479 /* Disable the VGA plane that we never use */
15480 static void i915_disable_vga(struct drm_device *dev)
15481 {
15482         struct drm_i915_private *dev_priv = to_i915(dev);
15483         u8 sr1;
15484         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15485
15486         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15487         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15488         outb(SR01, VGA_SR_INDEX);
15489         sr1 = inb(VGA_SR_DATA);
15490         outb(sr1 | 1<<5, VGA_SR_DATA);
15491         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15492         udelay(300);
15493
15494         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15495         POSTING_READ(vga_reg);
15496 }
15497
15498 void intel_modeset_init_hw(struct drm_device *dev)
15499 {
15500         struct drm_i915_private *dev_priv = to_i915(dev);
15501
15502         intel_update_cdclk(dev);
15503
15504         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15505
15506         intel_init_clock_gating(dev);
15507         intel_enable_gt_powersave(dev_priv);
15508 }
15509
15510 /*
15511  * Calculate what we think the watermarks should be for the state we've read
15512  * out of the hardware and then immediately program those watermarks so that
15513  * we ensure the hardware settings match our internal state.
15514  *
15515  * We can calculate what we think WM's should be by creating a duplicate of the
15516  * current state (which was constructed during hardware readout) and running it
15517  * through the atomic check code to calculate new watermark values in the
15518  * state object.
15519  */
15520 static void sanitize_watermarks(struct drm_device *dev)
15521 {
15522         struct drm_i915_private *dev_priv = to_i915(dev);
15523         struct drm_atomic_state *state;
15524         struct drm_crtc *crtc;
15525         struct drm_crtc_state *cstate;
15526         struct drm_modeset_acquire_ctx ctx;
15527         int ret;
15528         int i;
15529
15530         /* Only supported on platforms that use atomic watermark design */
15531         if (!dev_priv->display.optimize_watermarks)
15532                 return;
15533
15534         /*
15535          * We need to hold connection_mutex before calling duplicate_state so
15536          * that the connector loop is protected.
15537          */
15538         drm_modeset_acquire_init(&ctx, 0);
15539 retry:
15540         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15541         if (ret == -EDEADLK) {
15542                 drm_modeset_backoff(&ctx);
15543                 goto retry;
15544         } else if (WARN_ON(ret)) {
15545                 goto fail;
15546         }
15547
15548         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15549         if (WARN_ON(IS_ERR(state)))
15550                 goto fail;
15551
15552         /*
15553          * Hardware readout is the only time we don't want to calculate
15554          * intermediate watermarks (since we don't trust the current
15555          * watermarks).
15556          */
15557         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15558
15559         ret = intel_atomic_check(dev, state);
15560         if (ret) {
15561                 /*
15562                  * If we fail here, it means that the hardware appears to be
15563                  * programmed in a way that shouldn't be possible, given our
15564                  * understanding of watermark requirements.  This might mean a
15565                  * mistake in the hardware readout code or a mistake in the
15566                  * watermark calculations for a given platform.  Raise a WARN
15567                  * so that this is noticeable.
15568                  *
15569                  * If this actually happens, we'll have to just leave the
15570                  * BIOS-programmed watermarks untouched and hope for the best.
15571                  */
15572                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15573                 goto fail;
15574         }
15575
15576         /* Write calculated watermark values back */
15577         for_each_crtc_in_state(state, crtc, cstate, i) {
15578                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15579
15580                 cs->wm.need_postvbl_update = true;
15581                 dev_priv->display.optimize_watermarks(cs);
15582         }
15583
15584         drm_atomic_state_free(state);
15585 fail:
15586         drm_modeset_drop_locks(&ctx);
15587         drm_modeset_acquire_fini(&ctx);
15588 }
15589
15590 void intel_modeset_init(struct drm_device *dev)
15591 {
15592         struct drm_i915_private *dev_priv = to_i915(dev);
15593         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15594         int sprite, ret;
15595         enum pipe pipe;
15596         struct intel_crtc *crtc;
15597
15598         drm_mode_config_init(dev);
15599
15600         dev->mode_config.min_width = 0;
15601         dev->mode_config.min_height = 0;
15602
15603         dev->mode_config.preferred_depth = 24;
15604         dev->mode_config.prefer_shadow = 1;
15605
15606         dev->mode_config.allow_fb_modifiers = true;
15607
15608         dev->mode_config.funcs = &intel_mode_funcs;
15609
15610         intel_init_quirks(dev);
15611
15612         intel_init_pm(dev);
15613
15614         if (INTEL_INFO(dev)->num_pipes == 0)
15615                 return;
15616
15617         /*
15618          * There may be no VBT; and if the BIOS enabled SSC we can
15619          * just keep using it to avoid unnecessary flicker.  Whereas if the
15620          * BIOS isn't using it, don't assume it will work even if the VBT
15621          * indicates as much.
15622          */
15623         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15624                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15625                                             DREF_SSC1_ENABLE);
15626
15627                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15628                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15629                                      bios_lvds_use_ssc ? "en" : "dis",
15630                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15631                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15632                 }
15633         }
15634
15635         if (IS_GEN2(dev)) {
15636                 dev->mode_config.max_width = 2048;
15637                 dev->mode_config.max_height = 2048;
15638         } else if (IS_GEN3(dev)) {
15639                 dev->mode_config.max_width = 4096;
15640                 dev->mode_config.max_height = 4096;
15641         } else {
15642                 dev->mode_config.max_width = 8192;
15643                 dev->mode_config.max_height = 8192;
15644         }
15645
15646         if (IS_845G(dev) || IS_I865G(dev)) {
15647                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15648                 dev->mode_config.cursor_height = 1023;
15649         } else if (IS_GEN2(dev)) {
15650                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15651                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15652         } else {
15653                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15654                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15655         }
15656
15657         dev->mode_config.fb_base = ggtt->mappable_base;
15658
15659         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15660                       INTEL_INFO(dev)->num_pipes,
15661                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15662
15663         for_each_pipe(dev_priv, pipe) {
15664                 intel_crtc_init(dev, pipe);
15665                 for_each_sprite(dev_priv, pipe, sprite) {
15666                         ret = intel_plane_init(dev, pipe, sprite);
15667                         if (ret)
15668                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15669                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15670                 }
15671         }
15672
15673         intel_update_czclk(dev_priv);
15674         intel_update_cdclk(dev);
15675
15676         intel_shared_dpll_init(dev);
15677
15678         if (dev_priv->max_cdclk_freq == 0)
15679                 intel_update_max_cdclk(dev);
15680
15681         /* Just disable it once at startup */
15682         i915_disable_vga(dev);
15683         intel_setup_outputs(dev);
15684
15685         drm_modeset_lock_all(dev);
15686         intel_modeset_setup_hw_state(dev);
15687         drm_modeset_unlock_all(dev);
15688
15689         for_each_intel_crtc(dev, crtc) {
15690                 struct intel_initial_plane_config plane_config = {};
15691
15692                 if (!crtc->active)
15693                         continue;
15694
15695                 /*
15696                  * Note that reserving the BIOS fb up front prevents us
15697                  * from stuffing other stolen allocations like the ring
15698                  * on top.  This prevents some ugliness at boot time, and
15699                  * can even allow for smooth boot transitions if the BIOS
15700                  * fb is large enough for the active pipe configuration.
15701                  */
15702                 dev_priv->display.get_initial_plane_config(crtc,
15703                                                            &plane_config);
15704
15705                 /*
15706                  * If the fb is shared between multiple heads, we'll
15707                  * just get the first one.
15708                  */
15709                 intel_find_initial_plane_obj(crtc, &plane_config);
15710         }
15711
15712         /*
15713          * Make sure hardware watermarks really match the state we read out.
15714          * Note that we need to do this after reconstructing the BIOS fb's
15715          * since the watermark calculation done here will use pstate->fb.
15716          */
15717         sanitize_watermarks(dev);
15718 }
15719
15720 static void intel_enable_pipe_a(struct drm_device *dev)
15721 {
15722         struct intel_connector *connector;
15723         struct drm_connector *crt = NULL;
15724         struct intel_load_detect_pipe load_detect_temp;
15725         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15726
15727         /* We can't just switch on the pipe A, we need to set things up with a
15728          * proper mode and output configuration. As a gross hack, enable pipe A
15729          * by enabling the load detect pipe once. */
15730         for_each_intel_connector(dev, connector) {
15731                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15732                         crt = &connector->base;
15733                         break;
15734                 }
15735         }
15736
15737         if (!crt)
15738                 return;
15739
15740         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15741                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15742 }
15743
15744 static bool
15745 intel_check_plane_mapping(struct intel_crtc *crtc)
15746 {
15747         struct drm_device *dev = crtc->base.dev;
15748         struct drm_i915_private *dev_priv = to_i915(dev);
15749         u32 val;
15750
15751         if (INTEL_INFO(dev)->num_pipes == 1)
15752                 return true;
15753
15754         val = I915_READ(DSPCNTR(!crtc->plane));
15755
15756         if ((val & DISPLAY_PLANE_ENABLE) &&
15757             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15758                 return false;
15759
15760         return true;
15761 }
15762
15763 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15764 {
15765         struct drm_device *dev = crtc->base.dev;
15766         struct intel_encoder *encoder;
15767
15768         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15769                 return true;
15770
15771         return false;
15772 }
15773
15774 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15775 {
15776         struct drm_device *dev = encoder->base.dev;
15777         struct intel_connector *connector;
15778
15779         for_each_connector_on_encoder(dev, &encoder->base, connector)
15780                 return true;
15781
15782         return false;
15783 }
15784
15785 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15786 {
15787         struct drm_device *dev = crtc->base.dev;
15788         struct drm_i915_private *dev_priv = to_i915(dev);
15789         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15790
15791         /* Clear any frame start delays used for debugging left by the BIOS */
15792         if (!transcoder_is_dsi(cpu_transcoder)) {
15793                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15794
15795                 I915_WRITE(reg,
15796                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15797         }
15798
15799         /* restore vblank interrupts to correct state */
15800         drm_crtc_vblank_reset(&crtc->base);
15801         if (crtc->active) {
15802                 struct intel_plane *plane;
15803
15804                 drm_crtc_vblank_on(&crtc->base);
15805
15806                 /* Disable everything but the primary plane */
15807                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15808                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15809                                 continue;
15810
15811                         plane->disable_plane(&plane->base, &crtc->base);
15812                 }
15813         }
15814
15815         /* We need to sanitize the plane -> pipe mapping first because this will
15816          * disable the crtc (and hence change the state) if it is wrong. Note
15817          * that gen4+ has a fixed plane -> pipe mapping.  */
15818         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15819                 bool plane;
15820
15821                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15822                               crtc->base.base.id, crtc->base.name);
15823
15824                 /* Pipe has the wrong plane attached and the plane is active.
15825                  * Temporarily change the plane mapping and disable everything
15826                  * ...  */
15827                 plane = crtc->plane;
15828                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15829                 crtc->plane = !plane;
15830                 intel_crtc_disable_noatomic(&crtc->base);
15831                 crtc->plane = plane;
15832         }
15833
15834         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15835             crtc->pipe == PIPE_A && !crtc->active) {
15836                 /* BIOS forgot to enable pipe A, this mostly happens after
15837                  * resume. Force-enable the pipe to fix this, the update_dpms
15838                  * call below we restore the pipe to the right state, but leave
15839                  * the required bits on. */
15840                 intel_enable_pipe_a(dev);
15841         }
15842
15843         /* Adjust the state of the output pipe according to whether we
15844          * have active connectors/encoders. */
15845         if (crtc->active && !intel_crtc_has_encoders(crtc))
15846                 intel_crtc_disable_noatomic(&crtc->base);
15847
15848         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15849                 /*
15850                  * We start out with underrun reporting disabled to avoid races.
15851                  * For correct bookkeeping mark this on active crtcs.
15852                  *
15853                  * Also on gmch platforms we dont have any hardware bits to
15854                  * disable the underrun reporting. Which means we need to start
15855                  * out with underrun reporting disabled also on inactive pipes,
15856                  * since otherwise we'll complain about the garbage we read when
15857                  * e.g. coming up after runtime pm.
15858                  *
15859                  * No protection against concurrent access is required - at
15860                  * worst a fifo underrun happens which also sets this to false.
15861                  */
15862                 crtc->cpu_fifo_underrun_disabled = true;
15863                 crtc->pch_fifo_underrun_disabled = true;
15864         }
15865 }
15866
15867 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15868 {
15869         struct intel_connector *connector;
15870         struct drm_device *dev = encoder->base.dev;
15871
15872         /* We need to check both for a crtc link (meaning that the
15873          * encoder is active and trying to read from a pipe) and the
15874          * pipe itself being active. */
15875         bool has_active_crtc = encoder->base.crtc &&
15876                 to_intel_crtc(encoder->base.crtc)->active;
15877
15878         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15879                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15880                               encoder->base.base.id,
15881                               encoder->base.name);
15882
15883                 /* Connector is active, but has no active pipe. This is
15884                  * fallout from our resume register restoring. Disable
15885                  * the encoder manually again. */
15886                 if (encoder->base.crtc) {
15887                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15888                                       encoder->base.base.id,
15889                                       encoder->base.name);
15890                         encoder->disable(encoder);
15891                         if (encoder->post_disable)
15892                                 encoder->post_disable(encoder);
15893                 }
15894                 encoder->base.crtc = NULL;
15895
15896                 /* Inconsistent output/port/pipe state happens presumably due to
15897                  * a bug in one of the get_hw_state functions. Or someplace else
15898                  * in our code, like the register restore mess on resume. Clamp
15899                  * things to off as a safer default. */
15900                 for_each_intel_connector(dev, connector) {
15901                         if (connector->encoder != encoder)
15902                                 continue;
15903                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15904                         connector->base.encoder = NULL;
15905                 }
15906         }
15907         /* Enabled encoders without active connectors will be fixed in
15908          * the crtc fixup. */
15909 }
15910
15911 void i915_redisable_vga_power_on(struct drm_device *dev)
15912 {
15913         struct drm_i915_private *dev_priv = to_i915(dev);
15914         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15915
15916         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15917                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15918                 i915_disable_vga(dev);
15919         }
15920 }
15921
15922 void i915_redisable_vga(struct drm_device *dev)
15923 {
15924         struct drm_i915_private *dev_priv = to_i915(dev);
15925
15926         /* This function can be called both from intel_modeset_setup_hw_state or
15927          * at a very early point in our resume sequence, where the power well
15928          * structures are not yet restored. Since this function is at a very
15929          * paranoid "someone might have enabled VGA while we were not looking"
15930          * level, just check if the power well is enabled instead of trying to
15931          * follow the "don't touch the power well if we don't need it" policy
15932          * the rest of the driver uses. */
15933         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15934                 return;
15935
15936         i915_redisable_vga_power_on(dev);
15937
15938         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15939 }
15940
15941 static bool primary_get_hw_state(struct intel_plane *plane)
15942 {
15943         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15944
15945         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15946 }
15947
15948 /* FIXME read out full plane state for all planes */
15949 static void readout_plane_state(struct intel_crtc *crtc)
15950 {
15951         struct drm_plane *primary = crtc->base.primary;
15952         struct intel_plane_state *plane_state =
15953                 to_intel_plane_state(primary->state);
15954
15955         plane_state->visible = crtc->active &&
15956                 primary_get_hw_state(to_intel_plane(primary));
15957
15958         if (plane_state->visible)
15959                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15960 }
15961
15962 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15963 {
15964         struct drm_i915_private *dev_priv = to_i915(dev);
15965         enum pipe pipe;
15966         struct intel_crtc *crtc;
15967         struct intel_encoder *encoder;
15968         struct intel_connector *connector;
15969         int i;
15970
15971         dev_priv->active_crtcs = 0;
15972
15973         for_each_intel_crtc(dev, crtc) {
15974                 struct intel_crtc_state *crtc_state = crtc->config;
15975                 int pixclk = 0;
15976
15977                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15978                 memset(crtc_state, 0, sizeof(*crtc_state));
15979                 crtc_state->base.crtc = &crtc->base;
15980
15981                 crtc_state->base.active = crtc_state->base.enable =
15982                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15983
15984                 crtc->base.enabled = crtc_state->base.enable;
15985                 crtc->active = crtc_state->base.active;
15986
15987                 if (crtc_state->base.active) {
15988                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15989
15990                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15991                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15992                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15993                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15994                         else
15995                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15996
15997                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15998                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15999                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16000                 }
16001
16002                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16003
16004                 readout_plane_state(crtc);
16005
16006                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16007                               crtc->base.base.id, crtc->base.name,
16008                               crtc->active ? "enabled" : "disabled");
16009         }
16010
16011         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16012                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16013
16014                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16015                                                   &pll->config.hw_state);
16016                 pll->config.crtc_mask = 0;
16017                 for_each_intel_crtc(dev, crtc) {
16018                         if (crtc->active && crtc->config->shared_dpll == pll)
16019                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16020                 }
16021                 pll->active_mask = pll->config.crtc_mask;
16022
16023                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16024                               pll->name, pll->config.crtc_mask, pll->on);
16025         }
16026
16027         for_each_intel_encoder(dev, encoder) {
16028                 pipe = 0;
16029
16030                 if (encoder->get_hw_state(encoder, &pipe)) {
16031                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16032                         encoder->base.crtc = &crtc->base;
16033                         crtc->config->output_types |= 1 << encoder->type;
16034                         encoder->get_config(encoder, crtc->config);
16035                 } else {
16036                         encoder->base.crtc = NULL;
16037                 }
16038
16039                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16040                               encoder->base.base.id,
16041                               encoder->base.name,
16042                               encoder->base.crtc ? "enabled" : "disabled",
16043                               pipe_name(pipe));
16044         }
16045
16046         for_each_intel_connector(dev, connector) {
16047                 if (connector->get_hw_state(connector)) {
16048                         connector->base.dpms = DRM_MODE_DPMS_ON;
16049
16050                         encoder = connector->encoder;
16051                         connector->base.encoder = &encoder->base;
16052
16053                         if (encoder->base.crtc &&
16054                             encoder->base.crtc->state->active) {
16055                                 /*
16056                                  * This has to be done during hardware readout
16057                                  * because anything calling .crtc_disable may
16058                                  * rely on the connector_mask being accurate.
16059                                  */
16060                                 encoder->base.crtc->state->connector_mask |=
16061                                         1 << drm_connector_index(&connector->base);
16062                                 encoder->base.crtc->state->encoder_mask |=
16063                                         1 << drm_encoder_index(&encoder->base);
16064                         }
16065
16066                 } else {
16067                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16068                         connector->base.encoder = NULL;
16069                 }
16070                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16071                               connector->base.base.id,
16072                               connector->base.name,
16073                               connector->base.encoder ? "enabled" : "disabled");
16074         }
16075
16076         for_each_intel_crtc(dev, crtc) {
16077                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16078
16079                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16080                 if (crtc->base.state->active) {
16081                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16082                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16083                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16084
16085                         /*
16086                          * The initial mode needs to be set in order to keep
16087                          * the atomic core happy. It wants a valid mode if the
16088                          * crtc's enabled, so we do the above call.
16089                          *
16090                          * At this point some state updated by the connectors
16091                          * in their ->detect() callback has not run yet, so
16092                          * no recalculation can be done yet.
16093                          *
16094                          * Even if we could do a recalculation and modeset
16095                          * right now it would cause a double modeset if
16096                          * fbdev or userspace chooses a different initial mode.
16097                          *
16098                          * If that happens, someone indicated they wanted a
16099                          * mode change, which means it's safe to do a full
16100                          * recalculation.
16101                          */
16102                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16103
16104                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16105                         update_scanline_offset(crtc);
16106                 }
16107
16108                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16109         }
16110 }
16111
16112 /* Scan out the current hw modeset state,
16113  * and sanitizes it to the current state
16114  */
16115 static void
16116 intel_modeset_setup_hw_state(struct drm_device *dev)
16117 {
16118         struct drm_i915_private *dev_priv = to_i915(dev);
16119         enum pipe pipe;
16120         struct intel_crtc *crtc;
16121         struct intel_encoder *encoder;
16122         int i;
16123
16124         intel_modeset_readout_hw_state(dev);
16125
16126         /* HW state is read out, now we need to sanitize this mess. */
16127         for_each_intel_encoder(dev, encoder) {
16128                 intel_sanitize_encoder(encoder);
16129         }
16130
16131         for_each_pipe(dev_priv, pipe) {
16132                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16133                 intel_sanitize_crtc(crtc);
16134                 intel_dump_pipe_config(crtc, crtc->config,
16135                                        "[setup_hw_state]");
16136         }
16137
16138         intel_modeset_update_connector_atomic_state(dev);
16139
16140         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16141                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16142
16143                 if (!pll->on || pll->active_mask)
16144                         continue;
16145
16146                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16147
16148                 pll->funcs.disable(dev_priv, pll);
16149                 pll->on = false;
16150         }
16151
16152         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16153                 vlv_wm_get_hw_state(dev);
16154         else if (IS_GEN9(dev))
16155                 skl_wm_get_hw_state(dev);
16156         else if (HAS_PCH_SPLIT(dev))
16157                 ilk_wm_get_hw_state(dev);
16158
16159         for_each_intel_crtc(dev, crtc) {
16160                 unsigned long put_domains;
16161
16162                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16163                 if (WARN_ON(put_domains))
16164                         modeset_put_power_domains(dev_priv, put_domains);
16165         }
16166         intel_display_set_init_power(dev_priv, false);
16167
16168         intel_fbc_init_pipe_state(dev_priv);
16169 }
16170
16171 void intel_display_resume(struct drm_device *dev)
16172 {
16173         struct drm_i915_private *dev_priv = to_i915(dev);
16174         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16175         struct drm_modeset_acquire_ctx ctx;
16176         int ret;
16177         bool setup = false;
16178
16179         dev_priv->modeset_restore_state = NULL;
16180
16181         /*
16182          * This is a cludge because with real atomic modeset mode_config.mutex
16183          * won't be taken. Unfortunately some probed state like
16184          * audio_codec_enable is still protected by mode_config.mutex, so lock
16185          * it here for now.
16186          */
16187         mutex_lock(&dev->mode_config.mutex);
16188         drm_modeset_acquire_init(&ctx, 0);
16189
16190 retry:
16191         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16192
16193         if (ret == 0 && !setup) {
16194                 setup = true;
16195
16196                 intel_modeset_setup_hw_state(dev);
16197                 i915_redisable_vga(dev);
16198         }
16199
16200         if (ret == 0 && state) {
16201                 struct drm_crtc_state *crtc_state;
16202                 struct drm_crtc *crtc;
16203                 int i;
16204
16205                 state->acquire_ctx = &ctx;
16206
16207                 /* ignore any reset values/BIOS leftovers in the WM registers */
16208                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16209
16210                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16211                         /*
16212                          * Force recalculation even if we restore
16213                          * current state. With fast modeset this may not result
16214                          * in a modeset when the state is compatible.
16215                          */
16216                         crtc_state->mode_changed = true;
16217                 }
16218
16219                 ret = drm_atomic_commit(state);
16220         }
16221
16222         if (ret == -EDEADLK) {
16223                 drm_modeset_backoff(&ctx);
16224                 goto retry;
16225         }
16226
16227         drm_modeset_drop_locks(&ctx);
16228         drm_modeset_acquire_fini(&ctx);
16229         mutex_unlock(&dev->mode_config.mutex);
16230
16231         if (ret) {
16232                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16233                 drm_atomic_state_free(state);
16234         }
16235 }
16236
16237 void intel_modeset_gem_init(struct drm_device *dev)
16238 {
16239         struct drm_i915_private *dev_priv = to_i915(dev);
16240         struct drm_crtc *c;
16241         struct drm_i915_gem_object *obj;
16242         int ret;
16243
16244         intel_init_gt_powersave(dev_priv);
16245
16246         intel_modeset_init_hw(dev);
16247
16248         intel_setup_overlay(dev_priv);
16249
16250         /*
16251          * Make sure any fbs we allocated at startup are properly
16252          * pinned & fenced.  When we do the allocation it's too early
16253          * for this.
16254          */
16255         for_each_crtc(dev, c) {
16256                 obj = intel_fb_obj(c->primary->fb);
16257                 if (obj == NULL)
16258                         continue;
16259
16260                 mutex_lock(&dev->struct_mutex);
16261                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16262                                                  c->primary->state->rotation);
16263                 mutex_unlock(&dev->struct_mutex);
16264                 if (ret) {
16265                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16266                                   to_intel_crtc(c)->pipe);
16267                         drm_framebuffer_unreference(c->primary->fb);
16268                         c->primary->fb = NULL;
16269                         c->primary->crtc = c->primary->state->crtc = NULL;
16270                         update_state_fb(c->primary);
16271                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16272                 }
16273         }
16274 }
16275
16276 int intel_connector_register(struct drm_connector *connector)
16277 {
16278         struct intel_connector *intel_connector = to_intel_connector(connector);
16279         int ret;
16280
16281         ret = intel_backlight_device_register(intel_connector);
16282         if (ret)
16283                 goto err;
16284
16285         return 0;
16286
16287 err:
16288         return ret;
16289 }
16290
16291 void intel_connector_unregister(struct drm_connector *connector)
16292 {
16293         struct intel_connector *intel_connector = to_intel_connector(connector);
16294
16295         intel_backlight_device_unregister(intel_connector);
16296         intel_panel_destroy_backlight(connector);
16297 }
16298
16299 void intel_modeset_cleanup(struct drm_device *dev)
16300 {
16301         struct drm_i915_private *dev_priv = to_i915(dev);
16302
16303         intel_disable_gt_powersave(dev_priv);
16304
16305         /*
16306          * Interrupts and polling as the first thing to avoid creating havoc.
16307          * Too much stuff here (turning of connectors, ...) would
16308          * experience fancy races otherwise.
16309          */
16310         intel_irq_uninstall(dev_priv);
16311
16312         /*
16313          * Due to the hpd irq storm handling the hotplug work can re-arm the
16314          * poll handlers. Hence disable polling after hpd handling is shut down.
16315          */
16316         drm_kms_helper_poll_fini(dev);
16317
16318         intel_unregister_dsm_handler();
16319
16320         intel_fbc_global_disable(dev_priv);
16321
16322         /* flush any delayed tasks or pending work */
16323         flush_scheduled_work();
16324
16325         drm_mode_config_cleanup(dev);
16326
16327         intel_cleanup_overlay(dev_priv);
16328
16329         intel_cleanup_gt_powersave(dev_priv);
16330
16331         intel_teardown_gmbus(dev);
16332 }
16333
16334 void intel_connector_attach_encoder(struct intel_connector *connector,
16335                                     struct intel_encoder *encoder)
16336 {
16337         connector->encoder = encoder;
16338         drm_mode_connector_attach_encoder(&connector->base,
16339                                           &encoder->base);
16340 }
16341
16342 /*
16343  * set vga decode state - true == enable VGA decode
16344  */
16345 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16346 {
16347         struct drm_i915_private *dev_priv = to_i915(dev);
16348         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16349         u16 gmch_ctrl;
16350
16351         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16352                 DRM_ERROR("failed to read control word\n");
16353                 return -EIO;
16354         }
16355
16356         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16357                 return 0;
16358
16359         if (state)
16360                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16361         else
16362                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16363
16364         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16365                 DRM_ERROR("failed to write control word\n");
16366                 return -EIO;
16367         }
16368
16369         return 0;
16370 }
16371
16372 struct intel_display_error_state {
16373
16374         u32 power_well_driver;
16375
16376         int num_transcoders;
16377
16378         struct intel_cursor_error_state {
16379                 u32 control;
16380                 u32 position;
16381                 u32 base;
16382                 u32 size;
16383         } cursor[I915_MAX_PIPES];
16384
16385         struct intel_pipe_error_state {
16386                 bool power_domain_on;
16387                 u32 source;
16388                 u32 stat;
16389         } pipe[I915_MAX_PIPES];
16390
16391         struct intel_plane_error_state {
16392                 u32 control;
16393                 u32 stride;
16394                 u32 size;
16395                 u32 pos;
16396                 u32 addr;
16397                 u32 surface;
16398                 u32 tile_offset;
16399         } plane[I915_MAX_PIPES];
16400
16401         struct intel_transcoder_error_state {
16402                 bool power_domain_on;
16403                 enum transcoder cpu_transcoder;
16404
16405                 u32 conf;
16406
16407                 u32 htotal;
16408                 u32 hblank;
16409                 u32 hsync;
16410                 u32 vtotal;
16411                 u32 vblank;
16412                 u32 vsync;
16413         } transcoder[4];
16414 };
16415
16416 struct intel_display_error_state *
16417 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16418 {
16419         struct intel_display_error_state *error;
16420         int transcoders[] = {
16421                 TRANSCODER_A,
16422                 TRANSCODER_B,
16423                 TRANSCODER_C,
16424                 TRANSCODER_EDP,
16425         };
16426         int i;
16427
16428         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16429                 return NULL;
16430
16431         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16432         if (error == NULL)
16433                 return NULL;
16434
16435         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16436                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16437
16438         for_each_pipe(dev_priv, i) {
16439                 error->pipe[i].power_domain_on =
16440                         __intel_display_power_is_enabled(dev_priv,
16441                                                          POWER_DOMAIN_PIPE(i));
16442                 if (!error->pipe[i].power_domain_on)
16443                         continue;
16444
16445                 error->cursor[i].control = I915_READ(CURCNTR(i));
16446                 error->cursor[i].position = I915_READ(CURPOS(i));
16447                 error->cursor[i].base = I915_READ(CURBASE(i));
16448
16449                 error->plane[i].control = I915_READ(DSPCNTR(i));
16450                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16451                 if (INTEL_GEN(dev_priv) <= 3) {
16452                         error->plane[i].size = I915_READ(DSPSIZE(i));
16453                         error->plane[i].pos = I915_READ(DSPPOS(i));
16454                 }
16455                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16456                         error->plane[i].addr = I915_READ(DSPADDR(i));
16457                 if (INTEL_GEN(dev_priv) >= 4) {
16458                         error->plane[i].surface = I915_READ(DSPSURF(i));
16459                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16460                 }
16461
16462                 error->pipe[i].source = I915_READ(PIPESRC(i));
16463
16464                 if (HAS_GMCH_DISPLAY(dev_priv))
16465                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16466         }
16467
16468         /* Note: this does not include DSI transcoders. */
16469         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16470         if (HAS_DDI(dev_priv))
16471                 error->num_transcoders++; /* Account for eDP. */
16472
16473         for (i = 0; i < error->num_transcoders; i++) {
16474                 enum transcoder cpu_transcoder = transcoders[i];
16475
16476                 error->transcoder[i].power_domain_on =
16477                         __intel_display_power_is_enabled(dev_priv,
16478                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16479                 if (!error->transcoder[i].power_domain_on)
16480                         continue;
16481
16482                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16483
16484                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16485                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16486                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16487                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16488                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16489                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16490                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16491         }
16492
16493         return error;
16494 }
16495
16496 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16497
16498 void
16499 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16500                                 struct drm_device *dev,
16501                                 struct intel_display_error_state *error)
16502 {
16503         struct drm_i915_private *dev_priv = to_i915(dev);
16504         int i;
16505
16506         if (!error)
16507                 return;
16508
16509         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16510         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16511                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16512                            error->power_well_driver);
16513         for_each_pipe(dev_priv, i) {
16514                 err_printf(m, "Pipe [%d]:\n", i);
16515                 err_printf(m, "  Power: %s\n",
16516                            onoff(error->pipe[i].power_domain_on));
16517                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16518                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16519
16520                 err_printf(m, "Plane [%d]:\n", i);
16521                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16522                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16523                 if (INTEL_INFO(dev)->gen <= 3) {
16524                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16525                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16526                 }
16527                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16528                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16529                 if (INTEL_INFO(dev)->gen >= 4) {
16530                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16531                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16532                 }
16533
16534                 err_printf(m, "Cursor [%d]:\n", i);
16535                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16536                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16537                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16538         }
16539
16540         for (i = 0; i < error->num_transcoders; i++) {
16541                 err_printf(m, "CPU transcoder: %s\n",
16542                            transcoder_name(error->transcoder[i].cpu_transcoder));
16543                 err_printf(m, "  Power: %s\n",
16544                            onoff(error->transcoder[i].power_domain_on));
16545                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16546                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16547                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16548                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16549                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16550                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16551                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16552         }
16553 }