drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_dp_helper.h>
  42 #include <drm/drm_crtc_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <linux/dma_remapping.h>
  46
  47 /* Primary plane formats supported by all gen */
  48 #define COMMON_PRIMARY_FORMATS \
  49         DRM_FORMAT_C8, \
  50         DRM_FORMAT_RGB565, \
  51         DRM_FORMAT_XRGB8888, \
  52         DRM_FORMAT_ARGB8888
  53
  54 /* Primary plane formats for gen <= 3 */
  55 static const uint32_t intel_primary_formats_gen2[] = {
  56         COMMON_PRIMARY_FORMATS,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_ARGB1555,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t intel_primary_formats_gen4[] = {
  63         COMMON_PRIMARY_FORMATS, \
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_ARGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_ABGR2101010,
  70 };
  71
  72 /* Cursor formats */
  73 static const uint32_t intel_cursor_formats[] = {
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  78
  79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  80                                 struct intel_crtc_state *pipe_config);
  81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  82                                    struct intel_crtc_state *pipe_config);
  83
  84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  85                           int x, int y, struct drm_framebuffer *old_fb);
  86 static int intel_framebuffer_init(struct drm_device *dev,
  87                                   struct intel_framebuffer *ifb,
  88                                   struct drm_mode_fb_cmd2 *mode_cmd,
  89                                   struct drm_i915_gem_object *obj);
  90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  93                                          struct intel_link_m_n *m_n,
  94                                          struct intel_link_m_n *m2_n2);
  95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  98 static void vlv_prepare_pll(struct intel_crtc *crtc,
  99                             const struct intel_crtc_state *pipe_config);
 100 static void chv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4860000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 415 {
 416         struct drm_device *dev = crtc->base.dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 /**
 427  * Returns whether any output on the specified pipe will have the specified
 428  * type after a staged modeset is complete, i.e., the same as
 429  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 430  * encoder->crtc.
 431  */
 432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 433 {
 434         struct drm_device *dev = crtc->base.dev;
 435         struct intel_encoder *encoder;
 436
 437         for_each_intel_encoder(dev, encoder)
 438                 if (encoder->new_crtc == crtc && encoder->type == type)
 439                         return true;
 440
 441         return false;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev)) {
 452                         if (refclk == 100000)
 453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 454                         else
 455                                 limit = &intel_limits_ironlake_dual_lvds;
 456                 } else {
 457                         if (refclk == 100000)
 458                                 limit = &intel_limits_ironlake_single_lvds_100m;
 459                         else
 460                                 limit = &intel_limits_ironlake_single_lvds;
 461                 }
 462         } else
 463                 limit = &intel_limits_ironlake_dac;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (intel_is_dual_link_lvds(dev))
 475                         limit = &intel_limits_g4x_dual_channel_lvds;
 476                 else
 477                         limit = &intel_limits_g4x_single_channel_lvds;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 479                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 480                 limit = &intel_limits_g4x_hdmi;
 481         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 482                 limit = &intel_limits_g4x_sdvo;
 483         } else /* The option is for other outputs */
 484                 limit = &intel_limits_i9xx_sdvo;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 490 {
 491         struct drm_device *dev = crtc->base.dev;
 492         const intel_limit_t *limit;
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 limit = intel_ironlake_limit(crtc, refclk);
 496         else if (IS_G4X(dev)) {
 497                 limit = intel_g4x_limit(crtc);
 498         } else if (IS_PINEVIEW(dev)) {
 499                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 500                         limit = &intel_limits_pineview_lvds;
 501                 else
 502                         limit = &intel_limits_pineview_sdvo;
 503         } else if (IS_CHERRYVIEW(dev)) {
 504                 limit = &intel_limits_chv;
 505         } else if (IS_VALLEYVIEW(dev)) {
 506                 limit = &intel_limits_vlv;
 507         } else if (!IS_GEN2(dev)) {
 508                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 509                         limit = &intel_limits_i9xx_lvds;
 510                 else
 511                         limit = &intel_limits_i9xx_sdvo;
 512         } else {
 513                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 514                         limit = &intel_limits_i8xx_lvds;
 515                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 516                         limit = &intel_limits_i8xx_dvo;
 517                 else
 518                         limit = &intel_limits_i8xx_dac;
 519         }
 520         return limit;
 521 }
 522
 523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 524 static void pineview_clock(int refclk, intel_clock_t *clock)
 525 {
 526         clock->m = clock->m2 + 2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return;
 530         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 531         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 532 }
 533
 534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 535 {
 536         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 537 }
 538
 539 static void i9xx_clock(int refclk, intel_clock_t *clock)
 540 {
 541         clock->m = i9xx_dpll_compute_m(clock);
 542         clock->p = clock->p1 * clock->p2;
 543         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 544                 return;
 545         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 546         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 547 }
 548
 549 static void chv_clock(int refclk, intel_clock_t *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_device *dev,
 567                                const intel_limit_t *limit,
 568                                const intel_clock_t *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 580                 if (clock->m1 <= clock->m2)
 581                         INTELPllInvalid("m1 <= m2\n");
 582
 583         if (!IS_VALLEYVIEW(dev)) {
 584                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 585                         INTELPllInvalid("p out of range\n");
 586                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 587                         INTELPllInvalid("m out of range\n");
 588         }
 589
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->base.dev;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         clock.p2 = limit->p2.p2_fast;
 618                 else
 619                         clock.p2 = limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         clock.p2 = limit->p2.p2_slow;
 623                 else
 624                         clock.p2 = limit->p2.p2_fast;
 625         }
 626
 627         memset(best_clock, 0, sizeof(*best_clock));
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_clock(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645                                         if (match_clock &&
 646                                             clock.p != match_clock->p)
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err) {
 651                                                 *best_clock = clock;
 652                                                 err = this_err;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658
 659         return (err != target);
 660 }
 661
 662 static bool
 663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 664                    int target, int refclk, intel_clock_t *match_clock,
 665                    intel_clock_t *best_clock)
 666 {
 667         struct drm_device *dev = crtc->base.dev;
 668         intel_clock_t clock;
 669         int err = target;
 670
 671         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 672                 /*
 673                  * For LVDS just rely on its current settings for dual-channel.
 674                  * We haven't figured out how to reliably set up different
 675                  * single/dual channel state, if we even can.
 676                  */
 677                 if (intel_is_dual_link_lvds(dev))
 678                         clock.p2 = limit->p2.p2_fast;
 679                 else
 680                         clock.p2 = limit->p2.p2_slow;
 681         } else {
 682                 if (target < limit->p2.dot_limit)
 683                         clock.p2 = limit->p2.p2_slow;
 684                 else
 685                         clock.p2 = limit->p2.p2_fast;
 686         }
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         pineview_clock(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 static bool
 722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 723                    int target, int refclk, intel_clock_t *match_clock,
 724                    intel_clock_t *best_clock)
 725 {
 726         struct drm_device *dev = crtc->base.dev;
 727         intel_clock_t clock;
 728         int max_n;
 729         bool found;
 730         /* approximately equals target * 0.00585 */
 731         int err_most = (target >> 8) + (target >> 9);
 732         found = false;
 733
 734         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 735                 if (intel_is_dual_link_lvds(dev))
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_clock(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(dev, limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 static bool
 779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->base.dev;
 784         intel_clock_t clock;
 785         unsigned int bestppm = 1000000;
 786         /* min update 19.2 MHz */
 787         int max_n = min(limit->n.max, refclk / 19200);
 788         bool found = false;
 789
 790         target *= 5; /* fast clock */
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 797                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 798                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799                                 clock.p = clock.p1 * clock.p2;
 800                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 801                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 802                                         unsigned int ppm, diff;
 803
 804                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 805                                                                      refclk * clock.m1);
 806
 807                                         vlv_clock(refclk, &clock);
 808
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812
 813                                         diff = abs(clock.dot - target);
 814                                         ppm = div_u64(1000000ULL * diff, target);
 815
 816                                         if (ppm < 100 && clock.p > best_clock->p) {
 817                                                 bestppm = 0;
 818                                                 *best_clock = clock;
 819                                                 found = true;
 820                                         }
 821
 822                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 823                                                 bestppm = ppm;
 824                                                 *best_clock = clock;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831
 832         return found;
 833 }
 834
 835 static bool
 836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 837                    int target, int refclk, intel_clock_t *match_clock,
 838                    intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->base.dev;
 841         intel_clock_t clock;
 842         uint64_t m2;
 843         int found = false;
 844
 845         memset(best_clock, 0, sizeof(*best_clock));
 846
 847         /*
 848          * Based on hardware doc, the n always set to 1, and m1 always
 849          * set to 2.  If requires to support 200Mhz refclk, we need to
 850          * revisit this because n may not 1 anymore.
 851          */
 852         clock.n = 1, clock.m1 = 2;
 853         target *= 5;    /* fast clock */
 854
 855         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 856                 for (clock.p2 = limit->p2.p2_fast;
 857                                 clock.p2 >= limit->p2.p2_slow;
 858                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859
 860                         clock.p = clock.p1 * clock.p2;
 861
 862                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 863                                         clock.n) << 22, refclk * clock.m1);
 864
 865                         if (m2 > INT_MAX/clock.m1)
 866                                 continue;
 867
 868                         clock.m2 = m2;
 869
 870                         chv_clock(refclk, &clock);
 871
 872                         if (!intel_PLL_is_valid(dev, limit, &clock))
 873                                 continue;
 874
 875                         /* based on hardware requirement, prefer bigger p
 876                          */
 877                         if (clock.p > best_clock->p) {
 878                                 *best_clock = clock;
 879                                 found = true;
 880                         }
 881                 }
 882         }
 883
 884         return found;
 885 }
 886
 887 bool intel_crtc_active(struct drm_crtc *crtc)
 888 {
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         /* Be paranoid as we can arrive here with only partial
 892          * state retrieved from the hardware during setup.
 893          *
 894          * We can ditch the adjusted_mode.crtc_clock check as soon
 895          * as Haswell has gained clock readout/fastboot support.
 896          *
 897          * We can ditch the crtc->primary->fb check as soon as we can
 898          * properly reconstruct framebuffers.
 899          */
 900         return intel_crtc->active && crtc->primary->fb &&
 901                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 902 }
 903
 904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 905                                              enum pipe pipe)
 906 {
 907         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 909
 910         return intel_crtc->config->cpu_transcoder;
 911 }
 912
 913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         u32 reg = PIPEDSL(pipe);
 917         u32 line1, line2;
 918         u32 line_mask;
 919
 920         if (IS_GEN2(dev))
 921                 line_mask = DSL_LINEMASK_GEN2;
 922         else
 923                 line_mask = DSL_LINEMASK_GEN3;
 924
 925         line1 = I915_READ(reg) & line_mask;
 926         mdelay(5);
 927         line2 = I915_READ(reg) & line_mask;
 928
 929         return line1 == line2;
 930 }
 931
 932 /*
 933  * intel_wait_for_pipe_off - wait for pipe to turn off
 934  * @crtc: crtc whose pipe to wait for
 935  *
 936  * After disabling a pipe, we can't wait for vblank in the usual way,
 937  * spinning on the vblank interrupt status bit, since we won't actually
 938  * see an interrupt when the pipe is disabled.
 939  *
 940  * On Gen4 and above:
 941  *   wait for the pipe register state bit to turn off
 942  *
 943  * Otherwise:
 944  *   wait for the display line value to settle (it usually
 945  *   ends up stopping at the start of the next frame).
 946  *
 947  */
 948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 949 {
 950         struct drm_device *dev = crtc->base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 953         enum pipe pipe = crtc->pipe;
 954
 955         if (INTEL_INFO(dev)->gen >= 4) {
 956                 int reg = PIPECONF(cpu_transcoder);
 957
 958                 /* Wait for the Pipe State to go off */
 959                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 960                              100))
 961                         WARN(1, "pipe_off wait timed out\n");
 962         } else {
 963                 /* Wait for the display line to settle */
 964                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 965                         WARN(1, "pipe_off wait timed out\n");
 966         }
 967 }
 968
 969 /*
 970  * ibx_digital_port_connected - is the specified port connected?
 971  * @dev_priv: i915 private structure
 972  * @port: the port to test
 973  *
 974  * Returns true if @port is connected, false otherwise.
 975  */
 976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 977                                 struct intel_digital_port *port)
 978 {
 979         u32 bit;
 980
 981         if (HAS_PCH_IBX(dev_priv->dev)) {
 982                 switch (port->port) {
 983                 case PORT_B:
 984                         bit = SDE_PORTB_HOTPLUG;
 985                         break;
 986                 case PORT_C:
 987                         bit = SDE_PORTC_HOTPLUG;
 988                         break;
 989                 case PORT_D:
 990                         bit = SDE_PORTD_HOTPLUG;
 991                         break;
 992                 default:
 993                         return true;
 994                 }
 995         } else {
 996                 switch (port->port) {
 997                 case PORT_B:
 998                         bit = SDE_PORTB_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_C:
1001                         bit = SDE_PORTC_HOTPLUG_CPT;
1002                         break;
1003                 case PORT_D:
1004                         bit = SDE_PORTD_HOTPLUG_CPT;
1005                         break;
1006                 default:
1007                         return true;
1008                 }
1009         }
1010
1011         return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016         return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021                 enum pipe pipe, bool state)
1022 {
1023         int reg;
1024         u32 val;
1025         bool cur_state;
1026
1027         reg = DPLL(pipe);
1028         val = I915_READ(reg);
1029         cur_state = !!(val & DPLL_VCO_ENABLE);
1030         I915_STATE_WARN(cur_state != state,
1031              "PLL state assertion failure (expected %s, current %s)\n",
1032              state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038         u32 val;
1039         bool cur_state;
1040
1041         mutex_lock(&dev_priv->dpio_lock);
1042         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043         mutex_unlock(&dev_priv->dpio_lock);
1044
1045         cur_state = val & DSI_PLL_VCO_EN;
1046         I915_STATE_WARN(cur_state != state,
1047              "DSI PLL state assertion failure (expected %s, current %s)\n",
1048              state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058         if (crtc->config->shared_dpll < 0)
1059                 return NULL;
1060
1061         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066                         struct intel_shared_dpll *pll,
1067                         bool state)
1068 {
1069         bool cur_state;
1070         struct intel_dpll_hw_state hw_state;
1071
1072         if (WARN (!pll,
1073                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1074                 return;
1075
1076         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077         I915_STATE_WARN(cur_state != state,
1078              "%s assertion failure (expected %s, current %s)\n",
1079              pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083                           enum pipe pipe, bool state)
1084 {
1085         int reg;
1086         u32 val;
1087         bool cur_state;
1088         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089                                                                       pipe);
1090
1091         if (HAS_DDI(dev_priv->dev)) {
1092                 /* DDI does not have a specific FDI_TX register */
1093                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094                 val = I915_READ(reg);
1095                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096         } else {
1097                 reg = FDI_TX_CTL(pipe);
1098                 val = I915_READ(reg);
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103              state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         int reg;
1112         u32 val;
1113         bool cur_state;
1114
1115         reg = FDI_RX_CTL(pipe);
1116         val = I915_READ(reg);
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120              state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         int reg;
1129         u32 val;
1130
1131         /* ILK FDI PLL is always enabled */
1132         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133                 return;
1134
1135         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136         if (HAS_DDI(dev_priv->dev))
1137                 return;
1138
1139         reg = FDI_TX_CTL(pipe);
1140         val = I915_READ(reg);
1141         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145                        enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160                            enum pipe pipe)
1161 {
1162         struct drm_device *dev = dev_priv->dev;
1163         int pp_reg;
1164         u32 val;
1165         enum pipe panel_pipe = PIPE_A;
1166         bool locked = true;
1167
1168         if (WARN_ON(HAS_DDI(dev)))
1169                 return;
1170
1171         if (HAS_PCH_SPLIT(dev)) {
1172                 u32 port_sel;
1173
1174                 pp_reg = PCH_PP_CONTROL;
1175                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179                         panel_pipe = PIPE_B;
1180                 /* XXX: else fix for eDP */
1181         } else if (IS_VALLEYVIEW(dev)) {
1182                 /* presumably write lock depends on pipe, not port select */
1183                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184                 panel_pipe = pipe;
1185         } else {
1186                 pp_reg = PP_CONTROL;
1187                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188                         panel_pipe = PIPE_B;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         I915_STATE_WARN(panel_pipe == pipe && locked,
1197              "panel assertion failure, pipe %c regs locked\n",
1198              pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202                           enum pipe pipe, bool state)
1203 {
1204         struct drm_device *dev = dev_priv->dev;
1205         bool cur_state;
1206
1207         if (IS_845G(dev) || IS_I865G(dev))
1208                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209         else
1210                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212         I915_STATE_WARN(cur_state != state,
1213              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214              pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         /* if we need the pipe quirk it must be always on */
1229         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231                 state = true;
1232
1233         if (!intel_display_power_is_enabled(dev_priv,
1234                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235                 cur_state = false;
1236         } else {
1237                 reg = PIPECONF(cpu_transcoder);
1238                 val = I915_READ(reg);
1239                 cur_state = !!(val & PIPECONF_ENABLE);
1240         }
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         struct drm_device *dev = dev_priv->dev;
1269         int reg, i;
1270         u32 val;
1271         int cur_pipe;
1272
1273         /* Primary planes are fixed to pipes on gen4+ */
1274         if (INTEL_INFO(dev)->gen >= 4) {
1275                 reg = DSPCNTR(pipe);
1276                 val = I915_READ(reg);
1277                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278                      "plane %c assertion failure, should be disabled but not\n",
1279                      plane_name(pipe));
1280                 return;
1281         }
1282
1283         /* Need to check both planes against the pipe */
1284         for_each_pipe(dev_priv, i) {
1285                 reg = DSPCNTR(i);
1286                 val = I915_READ(reg);
1287                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288                         DISPPLANE_SEL_PIPE_SHIFT;
1289                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(i), pipe_name(pipe));
1292         }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296                                     enum pipe pipe)
1297 {
1298         struct drm_device *dev = dev_priv->dev;
1299         int reg, sprite;
1300         u32 val;
1301
1302         if (INTEL_INFO(dev)->gen >= 9) {
1303                 for_each_sprite(pipe, sprite) {
1304                         val = I915_READ(PLANE_CTL(pipe, sprite));
1305                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307                              sprite, pipe_name(pipe));
1308                 }
1309         } else if (IS_VALLEYVIEW(dev)) {
1310                 for_each_sprite(pipe, sprite) {
1311                         reg = SPCNTR(pipe, sprite);
1312                         val = I915_READ(reg);
1313                         I915_STATE_WARN(val & SP_ENABLE,
1314                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315                              sprite_name(pipe, sprite), pipe_name(pipe));
1316                 }
1317         } else if (INTEL_INFO(dev)->gen >= 7) {
1318                 reg = SPRCTL(pipe);
1319                 val = I915_READ(reg);
1320                 I915_STATE_WARN(val & SPRITE_ENABLE,
1321                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322                      plane_name(pipe), pipe_name(pipe));
1323         } else if (INTEL_INFO(dev)->gen >= 5) {
1324                 reg = DVSCNTR(pipe);
1325                 val = I915_READ(reg);
1326                 I915_STATE_WARN(val & DVS_ENABLE,
1327                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328                      plane_name(pipe), pipe_name(pipe));
1329         }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335                 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340         u32 val;
1341         bool enabled;
1342
1343         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345         val = I915_READ(PCH_DREF_CONTROL);
1346         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347                             DREF_SUPERSPREAD_SOURCE_MASK));
1348         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352                                            enum pipe pipe)
1353 {
1354         int reg;
1355         u32 val;
1356         bool enabled;
1357
1358         reg = PCH_TRANSCONF(pipe);
1359         val = I915_READ(reg);
1360         enabled = !!(val & TRANS_ENABLE);
1361         I915_STATE_WARN(enabled,
1362              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363              pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367                             enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369         if ((val & DP_PORT_EN) == 0)
1370                 return false;
1371
1372         if (HAS_PCH_CPT(dev_priv->dev)) {
1373                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv->dev)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv->dev)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, int reg, u32 port_sel)
1439 {
1440         u32 val = I915_READ(reg);
1441         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443              reg, pipe_name(pipe));
1444
1445         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446              && (val & DP_PIPEB_SELECT),
1447              "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451                                      enum pipe pipe, int reg)
1452 {
1453         u32 val = I915_READ(reg);
1454         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456              reg, pipe_name(pipe));
1457
1458         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459              && (val & SDVO_PIPE_B_SELECT),
1460              "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464                                       enum pipe pipe)
1465 {
1466         int reg;
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         reg = PCH_ADPA;
1474         val = I915_READ(reg);
1475         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476              "PCH VGA enabled on transcoder %c, should be disabled\n",
1477              pipe_name(pipe));
1478
1479         reg = PCH_LVDS;
1480         val = I915_READ(reg);
1481         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494         if (!IS_VALLEYVIEW(dev))
1495                 return;
1496
1497         /*
1498          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499          * CHV x1 PHY (DP/HDMI D)
1500          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501          */
1502         if (IS_CHERRYVIEW(dev)) {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505         } else {
1506                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507         }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_device *dev = crtc->base.dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515         int reg = DPLL(crtc->pipe);
1516         u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518         assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520         /* No really, not for ILK+ */
1521         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523         /* PLL is protected by panel, make sure we can write it */
1524         if (IS_MOBILE(dev_priv->dev))
1525                 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527         I915_WRITE(reg, dpll);
1528         POSTING_READ(reg);
1529         udelay(150);
1530
1531         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535         POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537         /* We do this three times for luck */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544         I915_WRITE(reg, dpll);
1545         POSTING_READ(reg);
1546         udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550                            const struct intel_crtc_state *pipe_config)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int pipe = crtc->pipe;
1555         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556         u32 tmp;
1557
1558         assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562         mutex_lock(&dev_priv->dpio_lock);
1563
1564         /* Enable back the 10bit clock to display controller */
1565         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566         tmp |= DPIO_DCLKP_EN;
1567         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569         /*
1570          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571          */
1572         udelay(1);
1573
1574         /* Enable PLL */
1575         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577         /* Check PLL is locked */
1578         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581         /* not sure when this should be written */
1582         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583         POSTING_READ(DPLL_MD(pipe));
1584
1585         mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590         struct intel_crtc *crtc;
1591         int count = 0;
1592
1593         for_each_intel_crtc(dev, crtc)
1594                 count += crtc->active &&
1595                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597         return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         int reg = DPLL(crtc->pipe);
1605         u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev) && !IS_I830(dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         /* Enable DVO 2x clock on both PLLs if necessary */
1617         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618                 /*
1619                  * It appears to be important that we don't enable this
1620                  * for the current pipe before otherwise configuring the
1621                  * PLL. No idea how this should be handled if multiple
1622                  * DVO outputs are enabled simultaneosly.
1623                  */
1624                 dpll |= DPLL_DVO_2X_MODE;
1625                 I915_WRITE(DPLL(!crtc->pipe),
1626                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627         }
1628
1629         /* Wait for the clocks to stabilize. */
1630         POSTING_READ(reg);
1631         udelay(150);
1632
1633         if (INTEL_INFO(dev)->gen >= 4) {
1634                 I915_WRITE(DPLL_MD(crtc->pipe),
1635                            crtc->config->dpll_hw_state.dpll_md);
1636         } else {
1637                 /* The pixel multiplier can only be updated once the
1638                  * DPLL is enabled and the clocks are stable.
1639                  *
1640                  * So write it again.
1641                  */
1642                 I915_WRITE(reg, dpll);
1643         }
1644
1645         /* We do this three times for luck */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652         I915_WRITE(reg, dpll);
1653         POSTING_READ(reg);
1654         udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658  * i9xx_disable_pll - disable a PLL
1659  * @dev_priv: i915 private structure
1660  * @pipe: pipe PLL to disable
1661  *
1662  * Disable the PLL for @pipe, making sure the pipe is off first.
1663  *
1664  * Note!  This is for pre-ILK only.
1665  */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668         struct drm_device *dev = crtc->base.dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         enum pipe pipe = crtc->pipe;
1671
1672         /* Disable DVO 2x clock on both PLLs if necessary */
1673         if (IS_I830(dev) &&
1674             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675             intel_num_dvo_pipes(dev) == 1) {
1676                 I915_WRITE(DPLL(PIPE_B),
1677                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678                 I915_WRITE(DPLL(PIPE_A),
1679                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680         }
1681
1682         /* Don't disable pipe or pipe PLLs if needed */
1683         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685                 return;
1686
1687         /* Make sure the pipe isn't still relying on us */
1688         assert_pipe_disabled(dev_priv, pipe);
1689
1690         I915_WRITE(DPLL(pipe), 0);
1691         POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696         u32 val = 0;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /*
1702          * Leave integrated clock source and reference clock enabled for pipe B.
1703          * The latter is needed for VGA hotplug / manual detection.
1704          */
1705         if (pipe == PIPE_B)
1706                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707         I915_WRITE(DPLL(pipe), val);
1708         POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715         u32 val;
1716
1717         /* Make sure the pipe isn't still relying on us */
1718         assert_pipe_disabled(dev_priv, pipe);
1719
1720         /* Set PLL en = 0 */
1721         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722         if (pipe != PIPE_A)
1723                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726
1727         mutex_lock(&dev_priv->dpio_lock);
1728
1729         /* Disable 10bit clock to display controller */
1730         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731         val &= ~DPIO_DCLKP_EN;
1732         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734         /* disable left/right clock distribution */
1735         if (pipe != PIPE_B) {
1736                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739         } else {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743         }
1744
1745         mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                 struct intel_digital_port *dport)
1750 {
1751         u32 port_mask;
1752         int dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_D:
1764                 port_mask = DPLL_PORTD_READY_MASK;
1765                 dpll_reg = DPIO_PHY_STATUS;
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770
1771         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773                      port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782         if (WARN_ON(pll == NULL))
1783                 return;
1784
1785         WARN_ON(!pll->config.crtc_mask);
1786         if (pll->active == 0) {
1787                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788                 WARN_ON(pll->on);
1789                 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791                 pll->mode_set(dev_priv, pll);
1792         }
1793 }
1794
1795 /**
1796  * intel_enable_shared_dpll - enable PCH PLL
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe PLL to enable
1799  *
1800  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801  * drives the transcoder clock.
1802  */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805         struct drm_device *dev = crtc->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809         if (WARN_ON(pll == NULL))
1810                 return;
1811
1812         if (WARN_ON(pll->config.crtc_mask == 0))
1813                 return;
1814
1815         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816                       pll->name, pll->active, pll->on,
1817                       crtc->base.base.id);
1818
1819         if (pll->active++) {
1820                 WARN_ON(!pll->on);
1821                 assert_shared_dpll_enabled(dev_priv, pll);
1822                 return;
1823         }
1824         WARN_ON(pll->on);
1825
1826         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829         pll->enable(dev_priv, pll);
1830         pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835         struct drm_device *dev = crtc->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841         if (WARN_ON(pll == NULL))
1842                return;
1843
1844         if (WARN_ON(pll->config.crtc_mask == 0))
1845                 return;
1846
1847         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848                       pll->name, pll->active, pll->on,
1849                       crtc->base.base.id);
1850
1851         if (WARN_ON(pll->active == 0)) {
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853                 return;
1854         }
1855
1856         assert_shared_dpll_enabled(dev_priv, pll);
1857         WARN_ON(!pll->on);
1858         if (--pll->active)
1859                 return;
1860
1861         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862         pll->disable(dev_priv, pll);
1863         pll->on = false;
1864
1865         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869                                            enum pipe pipe)
1870 {
1871         struct drm_device *dev = dev_priv->dev;
1872         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874         uint32_t reg, val, pipeconf_val;
1875
1876         /* PCH only available on ILK+ */
1877         BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879         /* Make sure PCH DPLL is enabled */
1880         assert_shared_dpll_enabled(dev_priv,
1881                                    intel_crtc_to_shared_dpll(intel_crtc));
1882
1883         /* FDI must be feeding us bits for PCH ports */
1884         assert_fdi_tx_enabled(dev_priv, pipe);
1885         assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887         if (HAS_PCH_CPT(dev)) {
1888                 /* Workaround: Set the timing override bit before enabling the
1889                  * pch transcoder. */
1890                 reg = TRANS_CHICKEN2(pipe);
1891                 val = I915_READ(reg);
1892                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893                 I915_WRITE(reg, val);
1894         }
1895
1896         reg = PCH_TRANSCONF(pipe);
1897         val = I915_READ(reg);
1898         pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900         if (HAS_PCH_IBX(dev_priv->dev)) {
1901                 /*
1902                  * make the BPC in transcoder be consistent with
1903                  * that in pipeconf reg.
1904                  */
1905                 val &= ~PIPECONF_BPC_MASK;
1906                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907         }
1908
1909         val &= ~TRANS_INTERLACE_MASK;
1910         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911                 if (HAS_PCH_IBX(dev_priv->dev) &&
1912                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913                         val |= TRANS_LEGACY_INTERLACED_ILK;
1914                 else
1915                         val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(reg, val | TRANS_ENABLE);
1920         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                       enum transcoder cpu_transcoder)
1926 {
1927         u32 val, pipeconf_val;
1928
1929         /* PCH only available on ILK+ */
1930         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932         /* FDI must be feeding us bits for PCH ports */
1933         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936         /* Workaround: set timing override bit. */
1937         val = I915_READ(_TRANSA_CHICKEN2);
1938         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939         I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941         val = TRANS_ENABLE;
1942         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945             PIPECONF_INTERLACED_ILK)
1946                 val |= TRANS_INTERLACED;
1947         else
1948                 val |= TRANS_PROGRESSIVE;
1949
1950         I915_WRITE(LPT_TRANSCONF, val);
1951         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952                 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956                                             enum pipe pipe)
1957 {
1958         struct drm_device *dev = dev_priv->dev;
1959         uint32_t reg, val;
1960
1961         /* FDI relies on the transcoder */
1962         assert_fdi_tx_disabled(dev_priv, pipe);
1963         assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965         /* Ports must be off as well */
1966         assert_pch_ports_disabled(dev_priv, pipe);
1967
1968         reg = PCH_TRANSCONF(pipe);
1969         val = I915_READ(reg);
1970         val &= ~TRANS_ENABLE;
1971         I915_WRITE(reg, val);
1972         /* wait for PCH transcoder off, transcoder state */
1973         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976         if (!HAS_PCH_IBX(dev)) {
1977                 /* Workaround: Clear the timing override chicken bit again. */
1978                 reg = TRANS_CHICKEN2(pipe);
1979                 val = I915_READ(reg);
1980                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981                 I915_WRITE(reg, val);
1982         }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987         u32 val;
1988
1989         val = I915_READ(LPT_TRANSCONF);
1990         val &= ~TRANS_ENABLE;
1991         I915_WRITE(LPT_TRANSCONF, val);
1992         /* wait for PCH transcoder off, transcoder state */
1993         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994                 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996         /* Workaround: clear timing override bit. */
1997         val = I915_READ(_TRANSA_CHICKEN2);
1998         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999         I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003  * intel_enable_pipe - enable a pipe, asserting requirements
2004  * @crtc: crtc responsible for the pipe
2005  *
2006  * Enable @crtc's pipe, making sure that various hardware specific requirements
2007  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008  */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_device *dev = crtc->base.dev;
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         enum pipe pipe = crtc->pipe;
2014         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015                                                                       pipe);
2016         enum pipe pch_transcoder;
2017         int reg;
2018         u32 val;
2019
2020         assert_planes_disabled(dev_priv, pipe);
2021         assert_cursor_disabled(dev_priv, pipe);
2022         assert_sprites_disabled(dev_priv, pipe);
2023
2024         if (HAS_PCH_LPT(dev_priv->dev))
2025                 pch_transcoder = TRANSCODER_A;
2026         else
2027                 pch_transcoder = pipe;
2028
2029         /*
2030          * A pipe without a PLL won't actually be able to drive bits from
2031          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2032          * need the check.
2033          */
2034         if (!HAS_PCH_SPLIT(dev_priv->dev))
2035                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036                         assert_dsi_pll_enabled(dev_priv);
2037                 else
2038                         assert_pll_enabled(dev_priv, pipe);
2039         else {
2040                 if (crtc->config->has_pch_encoder) {
2041                         /* if driving the PCH, we need FDI enabled */
2042                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043                         assert_fdi_tx_pll_enabled(dev_priv,
2044                                                   (enum pipe) cpu_transcoder);
2045                 }
2046                 /* FIXME: assert CPU port conditions for SNB+ */
2047         }
2048
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if (val & PIPECONF_ENABLE) {
2052                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054                 return;
2055         }
2056
2057         I915_WRITE(reg, val | PIPECONF_ENABLE);
2058         POSTING_READ(reg);
2059 }
2060
2061 /**
2062  * intel_disable_pipe - disable a pipe, asserting requirements
2063  * @crtc: crtc whose pipes is to be disabled
2064  *
2065  * Disable the pipe of @crtc, making sure that various hardware
2066  * specific requirements are met, if applicable, e.g. plane
2067  * disabled, panel fitter off, etc.
2068  *
2069  * Will wait until the pipe has shut down before returning.
2070  */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075         enum pipe pipe = crtc->pipe;
2076         int reg;
2077         u32 val;
2078
2079         /*
2080          * Make sure planes won't keep trying to pump pixels to us,
2081          * or we might hang the display.
2082          */
2083         assert_planes_disabled(dev_priv, pipe);
2084         assert_cursor_disabled(dev_priv, pipe);
2085         assert_sprites_disabled(dev_priv, pipe);
2086
2087         reg = PIPECONF(cpu_transcoder);
2088         val = I915_READ(reg);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 return;
2091
2092         /*
2093          * Double wide has implications for planes
2094          * so best keep it disabled when not needed.
2095          */
2096         if (crtc->config->double_wide)
2097                 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099         /* Don't disable pipe or pipe PLLs if needed */
2100         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102                 val &= ~PIPECONF_ENABLE;
2103
2104         I915_WRITE(reg, val);
2105         if ((val & PIPECONF_ENABLE) == 0)
2106                 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110  * Plane regs are double buffered, going from enabled->disabled needs a
2111  * trigger in order to latch.  The display address reg provides this.
2112  */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114                                enum plane plane)
2115 {
2116         struct drm_device *dev = dev_priv->dev;
2117         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119         I915_WRITE(reg, I915_READ(reg));
2120         POSTING_READ(reg);
2121 }
2122
2123 /**
2124  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125  * @plane:  plane to be enabled
2126  * @crtc: crtc for the plane
2127  *
2128  * Enable @plane on @crtc, making sure that the pipe is running first.
2129  */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131                                           struct drm_crtc *crtc)
2132 {
2133         struct drm_device *dev = plane->dev;
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140         if (intel_crtc->primary_enabled)
2141                 return;
2142
2143         intel_crtc->primary_enabled = true;
2144
2145         dev_priv->display.update_primary_plane(crtc, plane->fb,
2146                                                crtc->x, crtc->y);
2147
2148         /*
2149          * BDW signals flip done immediately if the plane
2150          * is disabled, even if the plane enable is already
2151          * armed to occur at the next vblank :(
2152          */
2153         if (IS_BROADWELL(dev))
2154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158  * intel_disable_primary_hw_plane - disable the primary hardware plane
2159  * @plane: plane to be disabled
2160  * @crtc: crtc for the plane
2161  *
2162  * Disable @plane on @crtc, making sure that the pipe is running first.
2163  */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165                                            struct drm_crtc *crtc)
2166 {
2167         struct drm_device *dev = plane->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171         if (WARN_ON(!intel_crtc->active))
2172                 return;
2173
2174         if (!intel_crtc->primary_enabled)
2175                 return;
2176
2177         intel_crtc->primary_enabled = false;
2178
2179         dev_priv->display.update_primary_plane(crtc, plane->fb,
2180                                                crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187                 return true;
2188 #endif
2189         return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194                       uint32_t pixel_format,
2195                       uint64_t fb_format_modifier)
2196 {
2197         int tile_height;
2198
2199         tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
2200                 (IS_GEN2(dev) ? 16 : 8) : 1;
2201
2202         return ALIGN(height, tile_height);
2203 }
2204
2205 int
2206 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2207                            struct drm_framebuffer *fb,
2208                            struct intel_engine_cs *pipelined)
2209 {
2210         struct drm_device *dev = fb->dev;
2211         struct drm_i915_private *dev_priv = dev->dev_private;
2212         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2213         u32 alignment;
2214         int ret;
2215
2216         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2217
2218         switch (fb->modifier[0]) {
2219         case DRM_FORMAT_MOD_NONE:
2220                 if (INTEL_INFO(dev)->gen >= 9)
2221                         alignment = 256 * 1024;
2222                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2223                         alignment = 128 * 1024;
2224                 else if (INTEL_INFO(dev)->gen >= 4)
2225                         alignment = 4 * 1024;
2226                 else
2227                         alignment = 64 * 1024;
2228                 break;
2229         case I915_FORMAT_MOD_X_TILED:
2230                 if (INTEL_INFO(dev)->gen >= 9)
2231                         alignment = 256 * 1024;
2232                 else {
2233                         /* pin() will align the object as required by fence */
2234                         alignment = 0;
2235                 }
2236                 break;
2237         case I915_FORMAT_MOD_Y_TILED:
2238                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2239                 return -EINVAL;
2240         default:
2241                 MISSING_CASE(fb->modifier[0]);
2242                 return -EINVAL;
2243         }
2244
2245         /* Note that the w/a also requires 64 PTE of padding following the
2246          * bo. We currently fill all unused PTE with the shadow page and so
2247          * we should always have valid PTE following the scanout preventing
2248          * the VT-d warning.
2249          */
2250         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2251                 alignment = 256 * 1024;
2252
2253         /*
2254          * Global gtt pte registers are special registers which actually forward
2255          * writes to a chunk of system memory. Which means that there is no risk
2256          * that the register values disappear as soon as we call
2257          * intel_runtime_pm_put(), so it is correct to wrap only the
2258          * pin/unpin/fence and not more.
2259          */
2260         intel_runtime_pm_get(dev_priv);
2261
2262         dev_priv->mm.interruptible = false;
2263         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2264         if (ret)
2265                 goto err_interruptible;
2266
2267         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2268          * fence, whereas 965+ only requires a fence if using
2269          * framebuffer compression.  For simplicity, we always install
2270          * a fence as the cost is not that onerous.
2271          */
2272         ret = i915_gem_object_get_fence(obj);
2273         if (ret)
2274                 goto err_unpin;
2275
2276         i915_gem_object_pin_fence(obj);
2277
2278         dev_priv->mm.interruptible = true;
2279         intel_runtime_pm_put(dev_priv);
2280         return 0;
2281
2282 err_unpin:
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 err_interruptible:
2285         dev_priv->mm.interruptible = true;
2286         intel_runtime_pm_put(dev_priv);
2287         return ret;
2288 }
2289
2290 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2291 {
2292         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2293
2294         i915_gem_object_unpin_fence(obj);
2295         i915_gem_object_unpin_from_display_plane(obj);
2296 }
2297
2298 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2299  * is assumed to be a power-of-two. */
2300 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2301                                              unsigned int tiling_mode,
2302                                              unsigned int cpp,
2303                                              unsigned int pitch)
2304 {
2305         if (tiling_mode != I915_TILING_NONE) {
2306                 unsigned int tile_rows, tiles;
2307
2308                 tile_rows = *y / 8;
2309                 *y %= 8;
2310
2311                 tiles = *x / (512/cpp);
2312                 *x %= 512/cpp;
2313
2314                 return tile_rows * pitch * 8 + tiles * 4096;
2315         } else {
2316                 unsigned int offset;
2317
2318                 offset = *y * pitch + *x * cpp;
2319                 *y = 0;
2320                 *x = (offset & 4095) / cpp;
2321                 return offset & -4096;
2322         }
2323 }
2324
2325 static int i9xx_format_to_fourcc(int format)
2326 {
2327         switch (format) {
2328         case DISPPLANE_8BPP:
2329                 return DRM_FORMAT_C8;
2330         case DISPPLANE_BGRX555:
2331                 return DRM_FORMAT_XRGB1555;
2332         case DISPPLANE_BGRX565:
2333                 return DRM_FORMAT_RGB565;
2334         default:
2335         case DISPPLANE_BGRX888:
2336                 return DRM_FORMAT_XRGB8888;
2337         case DISPPLANE_RGBX888:
2338                 return DRM_FORMAT_XBGR8888;
2339         case DISPPLANE_BGRX101010:
2340                 return DRM_FORMAT_XRGB2101010;
2341         case DISPPLANE_RGBX101010:
2342                 return DRM_FORMAT_XBGR2101010;
2343         }
2344 }
2345
2346 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2347 {
2348         switch (format) {
2349         case PLANE_CTL_FORMAT_RGB_565:
2350                 return DRM_FORMAT_RGB565;
2351         default:
2352         case PLANE_CTL_FORMAT_XRGB_8888:
2353                 if (rgb_order) {
2354                         if (alpha)
2355                                 return DRM_FORMAT_ABGR8888;
2356                         else
2357                                 return DRM_FORMAT_XBGR8888;
2358                 } else {
2359                         if (alpha)
2360                                 return DRM_FORMAT_ARGB8888;
2361                         else
2362                                 return DRM_FORMAT_XRGB8888;
2363                 }
2364         case PLANE_CTL_FORMAT_XRGB_2101010:
2365                 if (rgb_order)
2366                         return DRM_FORMAT_XBGR2101010;
2367                 else
2368                         return DRM_FORMAT_XRGB2101010;
2369         }
2370 }
2371
2372 static bool
2373 intel_alloc_plane_obj(struct intel_crtc *crtc,
2374                       struct intel_initial_plane_config *plane_config)
2375 {
2376         struct drm_device *dev = crtc->base.dev;
2377         struct drm_i915_gem_object *obj = NULL;
2378         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2379         struct drm_framebuffer *fb = &plane_config->fb->base;
2380         u32 base = plane_config->base;
2381
2382         if (plane_config->size == 0)
2383                 return false;
2384
2385         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2386                                                              plane_config->size);
2387         if (!obj)
2388                 return false;
2389
2390         obj->tiling_mode = plane_config->tiling;
2391         if (obj->tiling_mode == I915_TILING_X)
2392                 obj->stride = fb->pitches[0];
2393
2394         mode_cmd.pixel_format = fb->pixel_format;
2395         mode_cmd.width = fb->width;
2396         mode_cmd.height = fb->height;
2397         mode_cmd.pitches[0] = fb->pitches[0];
2398         mode_cmd.modifier[0] = fb->modifier[0];
2399         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2400
2401         mutex_lock(&dev->struct_mutex);
2402
2403         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2404                                    &mode_cmd, obj)) {
2405                 DRM_DEBUG_KMS("intel fb init failed\n");
2406                 goto out_unref_obj;
2407         }
2408
2409         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2410         mutex_unlock(&dev->struct_mutex);
2411
2412         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2413         return true;
2414
2415 out_unref_obj:
2416         drm_gem_object_unreference(&obj->base);
2417         mutex_unlock(&dev->struct_mutex);
2418         return false;
2419 }
2420
2421 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2422 static void
2423 update_state_fb(struct drm_plane *plane)
2424 {
2425         if (plane->fb == plane->state->fb)
2426                 return;
2427
2428         if (plane->state->fb)
2429                 drm_framebuffer_unreference(plane->state->fb);
2430         plane->state->fb = plane->fb;
2431         if (plane->state->fb)
2432                 drm_framebuffer_reference(plane->state->fb);
2433 }
2434
2435 static void
2436 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2437                      struct intel_initial_plane_config *plane_config)
2438 {
2439         struct drm_device *dev = intel_crtc->base.dev;
2440         struct drm_i915_private *dev_priv = dev->dev_private;
2441         struct drm_crtc *c;
2442         struct intel_crtc *i;
2443         struct drm_i915_gem_object *obj;
2444
2445         if (!plane_config->fb)
2446                 return;
2447
2448         if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2449                 struct drm_plane *primary = intel_crtc->base.primary;
2450
2451                 primary->fb = &plane_config->fb->base;
2452                 primary->state->crtc = &intel_crtc->base;
2453                 update_state_fb(primary);
2454
2455                 return;
2456         }
2457
2458         kfree(plane_config->fb);
2459
2460         /*
2461          * Failed to alloc the obj, check to see if we should share
2462          * an fb with another CRTC instead
2463          */
2464         for_each_crtc(dev, c) {
2465                 i = to_intel_crtc(c);
2466
2467                 if (c == &intel_crtc->base)
2468                         continue;
2469
2470                 if (!i->active)
2471                         continue;
2472
2473                 obj = intel_fb_obj(c->primary->fb);
2474                 if (obj == NULL)
2475                         continue;
2476
2477                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2478                         struct drm_plane *primary = intel_crtc->base.primary;
2479
2480                         if (obj->tiling_mode != I915_TILING_NONE)
2481                                 dev_priv->preserve_bios_swizzle = true;
2482
2483                         drm_framebuffer_reference(c->primary->fb);
2484                         primary->fb = c->primary->fb;
2485                         primary->state->crtc = &intel_crtc->base;
2486                         update_state_fb(intel_crtc->base.primary);
2487                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2488                         break;
2489                 }
2490         }
2491
2492 }
2493
2494 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2495                                       struct drm_framebuffer *fb,
2496                                       int x, int y)
2497 {
2498         struct drm_device *dev = crtc->dev;
2499         struct drm_i915_private *dev_priv = dev->dev_private;
2500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2501         struct drm_i915_gem_object *obj;
2502         int plane = intel_crtc->plane;
2503         unsigned long linear_offset;
2504         u32 dspcntr;
2505         u32 reg = DSPCNTR(plane);
2506         int pixel_size;
2507
2508         if (!intel_crtc->primary_enabled) {
2509                 I915_WRITE(reg, 0);
2510                 if (INTEL_INFO(dev)->gen >= 4)
2511                         I915_WRITE(DSPSURF(plane), 0);
2512                 else
2513                         I915_WRITE(DSPADDR(plane), 0);
2514                 POSTING_READ(reg);
2515                 return;
2516         }
2517
2518         obj = intel_fb_obj(fb);
2519         if (WARN_ON(obj == NULL))
2520                 return;
2521
2522         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2523
2524         dspcntr = DISPPLANE_GAMMA_ENABLE;
2525
2526         dspcntr |= DISPLAY_PLANE_ENABLE;
2527
2528         if (INTEL_INFO(dev)->gen < 4) {
2529                 if (intel_crtc->pipe == PIPE_B)
2530                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2531
2532                 /* pipesrc and dspsize control the size that is scaled from,
2533                  * which should always be the user's requested size.
2534                  */
2535                 I915_WRITE(DSPSIZE(plane),
2536                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2537                            (intel_crtc->config->pipe_src_w - 1));
2538                 I915_WRITE(DSPPOS(plane), 0);
2539         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2540                 I915_WRITE(PRIMSIZE(plane),
2541                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2542                            (intel_crtc->config->pipe_src_w - 1));
2543                 I915_WRITE(PRIMPOS(plane), 0);
2544                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2545         }
2546
2547         switch (fb->pixel_format) {
2548         case DRM_FORMAT_C8:
2549                 dspcntr |= DISPPLANE_8BPP;
2550                 break;
2551         case DRM_FORMAT_XRGB1555:
2552         case DRM_FORMAT_ARGB1555:
2553                 dspcntr |= DISPPLANE_BGRX555;
2554                 break;
2555         case DRM_FORMAT_RGB565:
2556                 dspcntr |= DISPPLANE_BGRX565;
2557                 break;
2558         case DRM_FORMAT_XRGB8888:
2559         case DRM_FORMAT_ARGB8888:
2560                 dspcntr |= DISPPLANE_BGRX888;
2561                 break;
2562         case DRM_FORMAT_XBGR8888:
2563         case DRM_FORMAT_ABGR8888:
2564                 dspcntr |= DISPPLANE_RGBX888;
2565                 break;
2566         case DRM_FORMAT_XRGB2101010:
2567         case DRM_FORMAT_ARGB2101010:
2568                 dspcntr |= DISPPLANE_BGRX101010;
2569                 break;
2570         case DRM_FORMAT_XBGR2101010:
2571         case DRM_FORMAT_ABGR2101010:
2572                 dspcntr |= DISPPLANE_RGBX101010;
2573                 break;
2574         default:
2575                 BUG();
2576         }
2577
2578         if (INTEL_INFO(dev)->gen >= 4 &&
2579             obj->tiling_mode != I915_TILING_NONE)
2580                 dspcntr |= DISPPLANE_TILED;
2581
2582         if (IS_G4X(dev))
2583                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2584
2585         linear_offset = y * fb->pitches[0] + x * pixel_size;
2586
2587         if (INTEL_INFO(dev)->gen >= 4) {
2588                 intel_crtc->dspaddr_offset =
2589                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2590                                                        pixel_size,
2591                                                        fb->pitches[0]);
2592                 linear_offset -= intel_crtc->dspaddr_offset;
2593         } else {
2594                 intel_crtc->dspaddr_offset = linear_offset;
2595         }
2596
2597         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2598                 dspcntr |= DISPPLANE_ROTATE_180;
2599
2600                 x += (intel_crtc->config->pipe_src_w - 1);
2601                 y += (intel_crtc->config->pipe_src_h - 1);
2602
2603                 /* Finding the last pixel of the last line of the display
2604                 data and adding to linear_offset*/
2605                 linear_offset +=
2606                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2607                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2608         }
2609
2610         I915_WRITE(reg, dspcntr);
2611
2612         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2613                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2614                       fb->pitches[0]);
2615         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2616         if (INTEL_INFO(dev)->gen >= 4) {
2617                 I915_WRITE(DSPSURF(plane),
2618                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2619                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2620                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2621         } else
2622                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2623         POSTING_READ(reg);
2624 }
2625
2626 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2627                                           struct drm_framebuffer *fb,
2628                                           int x, int y)
2629 {
2630         struct drm_device *dev = crtc->dev;
2631         struct drm_i915_private *dev_priv = dev->dev_private;
2632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2633         struct drm_i915_gem_object *obj;
2634         int plane = intel_crtc->plane;
2635         unsigned long linear_offset;
2636         u32 dspcntr;
2637         u32 reg = DSPCNTR(plane);
2638         int pixel_size;
2639
2640         if (!intel_crtc->primary_enabled) {
2641                 I915_WRITE(reg, 0);
2642                 I915_WRITE(DSPSURF(plane), 0);
2643                 POSTING_READ(reg);
2644                 return;
2645         }
2646
2647         obj = intel_fb_obj(fb);
2648         if (WARN_ON(obj == NULL))
2649                 return;
2650
2651         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2652
2653         dspcntr = DISPPLANE_GAMMA_ENABLE;
2654
2655         dspcntr |= DISPLAY_PLANE_ENABLE;
2656
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2658                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2659
2660         switch (fb->pixel_format) {
2661         case DRM_FORMAT_C8:
2662                 dspcntr |= DISPPLANE_8BPP;
2663                 break;
2664         case DRM_FORMAT_RGB565:
2665                 dspcntr |= DISPPLANE_BGRX565;
2666                 break;
2667         case DRM_FORMAT_XRGB8888:
2668         case DRM_FORMAT_ARGB8888:
2669                 dspcntr |= DISPPLANE_BGRX888;
2670                 break;
2671         case DRM_FORMAT_XBGR8888:
2672         case DRM_FORMAT_ABGR8888:
2673                 dspcntr |= DISPPLANE_RGBX888;
2674                 break;
2675         case DRM_FORMAT_XRGB2101010:
2676         case DRM_FORMAT_ARGB2101010:
2677                 dspcntr |= DISPPLANE_BGRX101010;
2678                 break;
2679         case DRM_FORMAT_XBGR2101010:
2680         case DRM_FORMAT_ABGR2101010:
2681                 dspcntr |= DISPPLANE_RGBX101010;
2682                 break;
2683         default:
2684                 BUG();
2685         }
2686
2687         if (obj->tiling_mode != I915_TILING_NONE)
2688                 dspcntr |= DISPPLANE_TILED;
2689
2690         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2691                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2692
2693         linear_offset = y * fb->pitches[0] + x * pixel_size;
2694         intel_crtc->dspaddr_offset =
2695                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2696                                                pixel_size,
2697                                                fb->pitches[0]);
2698         linear_offset -= intel_crtc->dspaddr_offset;
2699         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2700                 dspcntr |= DISPPLANE_ROTATE_180;
2701
2702                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2703                         x += (intel_crtc->config->pipe_src_w - 1);
2704                         y += (intel_crtc->config->pipe_src_h - 1);
2705
2706                         /* Finding the last pixel of the last line of the display
2707                         data and adding to linear_offset*/
2708                         linear_offset +=
2709                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2710                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2711                 }
2712         }
2713
2714         I915_WRITE(reg, dspcntr);
2715
2716         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2717                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2718                       fb->pitches[0]);
2719         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2720         I915_WRITE(DSPSURF(plane),
2721                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2722         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2723                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2724         } else {
2725                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2726                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2727         }
2728         POSTING_READ(reg);
2729 }
2730
2731 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2732                                          struct drm_framebuffer *fb,
2733                                          int x, int y)
2734 {
2735         struct drm_device *dev = crtc->dev;
2736         struct drm_i915_private *dev_priv = dev->dev_private;
2737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2738         struct intel_framebuffer *intel_fb;
2739         struct drm_i915_gem_object *obj;
2740         int pipe = intel_crtc->pipe;
2741         u32 plane_ctl, stride;
2742
2743         if (!intel_crtc->primary_enabled) {
2744                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2745                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2746                 POSTING_READ(PLANE_CTL(pipe, 0));
2747                 return;
2748         }
2749
2750         plane_ctl = PLANE_CTL_ENABLE |
2751                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2752                     PLANE_CTL_PIPE_CSC_ENABLE;
2753
2754         switch (fb->pixel_format) {
2755         case DRM_FORMAT_RGB565:
2756                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2757                 break;
2758         case DRM_FORMAT_XRGB8888:
2759                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2760                 break;
2761         case DRM_FORMAT_XBGR8888:
2762                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2763                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2764                 break;
2765         case DRM_FORMAT_XRGB2101010:
2766                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2767                 break;
2768         case DRM_FORMAT_XBGR2101010:
2769                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2770                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2771                 break;
2772         default:
2773                 BUG();
2774         }
2775
2776         intel_fb = to_intel_framebuffer(fb);
2777         obj = intel_fb->obj;
2778
2779         /*
2780          * The stride is either expressed as a multiple of 64 bytes chunks for
2781          * linear buffers or in number of tiles for tiled buffers.
2782          */
2783         switch (fb->modifier[0]) {
2784         case DRM_FORMAT_MOD_NONE:
2785                 stride = fb->pitches[0] >> 6;
2786                 break;
2787         case I915_FORMAT_MOD_X_TILED:
2788                 plane_ctl |= PLANE_CTL_TILED_X;
2789                 stride = fb->pitches[0] >> 9;
2790                 break;
2791         default:
2792                 BUG();
2793         }
2794
2795         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2796         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2797                 plane_ctl |= PLANE_CTL_ROTATE_180;
2798
2799         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2800
2801         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2802                       i915_gem_obj_ggtt_offset(obj),
2803                       x, y, fb->width, fb->height,
2804                       fb->pitches[0]);
2805
2806         I915_WRITE(PLANE_POS(pipe, 0), 0);
2807         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2808         I915_WRITE(PLANE_SIZE(pipe, 0),
2809                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2810                    (intel_crtc->config->pipe_src_w - 1));
2811         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2812         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2813
2814         POSTING_READ(PLANE_SURF(pipe, 0));
2815 }
2816
2817 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2818 static int
2819 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2820                            int x, int y, enum mode_set_atomic state)
2821 {
2822         struct drm_device *dev = crtc->dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824
2825         if (dev_priv->display.disable_fbc)
2826                 dev_priv->display.disable_fbc(dev);
2827
2828         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2829
2830         return 0;
2831 }
2832
2833 static void intel_complete_page_flips(struct drm_device *dev)
2834 {
2835         struct drm_crtc *crtc;
2836
2837         for_each_crtc(dev, crtc) {
2838                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839                 enum plane plane = intel_crtc->plane;
2840
2841                 intel_prepare_page_flip(dev, plane);
2842                 intel_finish_page_flip_plane(dev, plane);
2843         }
2844 }
2845
2846 static void intel_update_primary_planes(struct drm_device *dev)
2847 {
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct drm_crtc *crtc;
2850
2851         for_each_crtc(dev, crtc) {
2852                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2853
2854                 drm_modeset_lock(&crtc->mutex, NULL);
2855                 /*
2856                  * FIXME: Once we have proper support for primary planes (and
2857                  * disabling them without disabling the entire crtc) allow again
2858                  * a NULL crtc->primary->fb.
2859                  */
2860                 if (intel_crtc->active && crtc->primary->fb)
2861                         dev_priv->display.update_primary_plane(crtc,
2862                                                                crtc->primary->fb,
2863                                                                crtc->x,
2864                                                                crtc->y);
2865                 drm_modeset_unlock(&crtc->mutex);
2866         }
2867 }
2868
2869 void intel_prepare_reset(struct drm_device *dev)
2870 {
2871         struct drm_i915_private *dev_priv = to_i915(dev);
2872         struct intel_crtc *crtc;
2873
2874         /* no reset support for gen2 */
2875         if (IS_GEN2(dev))
2876                 return;
2877
2878         /* reset doesn't touch the display */
2879         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2880                 return;
2881
2882         drm_modeset_lock_all(dev);
2883
2884         /*
2885          * Disabling the crtcs gracefully seems nicer. Also the
2886          * g33 docs say we should at least disable all the planes.
2887          */
2888         for_each_intel_crtc(dev, crtc) {
2889                 if (crtc->active)
2890                         dev_priv->display.crtc_disable(&crtc->base);
2891         }
2892 }
2893
2894 void intel_finish_reset(struct drm_device *dev)
2895 {
2896         struct drm_i915_private *dev_priv = to_i915(dev);
2897
2898         /*
2899          * Flips in the rings will be nuked by the reset,
2900          * so complete all pending flips so that user space
2901          * will get its events and not get stuck.
2902          */
2903         intel_complete_page_flips(dev);
2904
2905         /* no reset support for gen2 */
2906         if (IS_GEN2(dev))
2907                 return;
2908
2909         /* reset doesn't touch the display */
2910         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2911                 /*
2912                  * Flips in the rings have been nuked by the reset,
2913                  * so update the base address of all primary
2914                  * planes to the the last fb to make sure we're
2915                  * showing the correct fb after a reset.
2916                  */
2917                 intel_update_primary_planes(dev);
2918                 return;
2919         }
2920
2921         /*
2922          * The display has been reset as well,
2923          * so need a full re-initialization.
2924          */
2925         intel_runtime_pm_disable_interrupts(dev_priv);
2926         intel_runtime_pm_enable_interrupts(dev_priv);
2927
2928         intel_modeset_init_hw(dev);
2929
2930         spin_lock_irq(&dev_priv->irq_lock);
2931         if (dev_priv->display.hpd_irq_setup)
2932                 dev_priv->display.hpd_irq_setup(dev);
2933         spin_unlock_irq(&dev_priv->irq_lock);
2934
2935         intel_modeset_setup_hw_state(dev, true);
2936
2937         intel_hpd_init(dev_priv);
2938
2939         drm_modeset_unlock_all(dev);
2940 }
2941
2942 static int
2943 intel_finish_fb(struct drm_framebuffer *old_fb)
2944 {
2945         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2946         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2947         bool was_interruptible = dev_priv->mm.interruptible;
2948         int ret;
2949
2950         /* Big Hammer, we also need to ensure that any pending
2951          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2952          * current scanout is retired before unpinning the old
2953          * framebuffer.
2954          *
2955          * This should only fail upon a hung GPU, in which case we
2956          * can safely continue.
2957          */
2958         dev_priv->mm.interruptible = false;
2959         ret = i915_gem_object_finish_gpu(obj);
2960         dev_priv->mm.interruptible = was_interruptible;
2961
2962         return ret;
2963 }
2964
2965 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2970         bool pending;
2971
2972         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2973             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2974                 return false;
2975
2976         spin_lock_irq(&dev->event_lock);
2977         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2978         spin_unlock_irq(&dev->event_lock);
2979
2980         return pending;
2981 }
2982
2983 static void intel_update_pipe_size(struct intel_crtc *crtc)
2984 {
2985         struct drm_device *dev = crtc->base.dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         const struct drm_display_mode *adjusted_mode;
2988
2989         if (!i915.fastboot)
2990                 return;
2991
2992         /*
2993          * Update pipe size and adjust fitter if needed: the reason for this is
2994          * that in compute_mode_changes we check the native mode (not the pfit
2995          * mode) to see if we can flip rather than do a full mode set. In the
2996          * fastboot case, we'll flip, but if we don't update the pipesrc and
2997          * pfit state, we'll end up with a big fb scanned out into the wrong
2998          * sized surface.
2999          *
3000          * To fix this properly, we need to hoist the checks up into
3001          * compute_mode_changes (or above), check the actual pfit state and
3002          * whether the platform allows pfit disable with pipe active, and only
3003          * then update the pipesrc and pfit state, even on the flip path.
3004          */
3005
3006         adjusted_mode = &crtc->config->base.adjusted_mode;
3007
3008         I915_WRITE(PIPESRC(crtc->pipe),
3009                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3010                    (adjusted_mode->crtc_vdisplay - 1));
3011         if (!crtc->config->pch_pfit.enabled &&
3012             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3013              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3014                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3015                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3016                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3017         }
3018         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3019         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3020 }
3021
3022 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3023 {
3024         struct drm_device *dev = crtc->dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027         int pipe = intel_crtc->pipe;
3028         u32 reg, temp;
3029
3030         /* enable normal train */
3031         reg = FDI_TX_CTL(pipe);
3032         temp = I915_READ(reg);
3033         if (IS_IVYBRIDGE(dev)) {
3034                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3035                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3036         } else {
3037                 temp &= ~FDI_LINK_TRAIN_NONE;
3038                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3039         }
3040         I915_WRITE(reg, temp);
3041
3042         reg = FDI_RX_CTL(pipe);
3043         temp = I915_READ(reg);
3044         if (HAS_PCH_CPT(dev)) {
3045                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3047         } else {
3048                 temp &= ~FDI_LINK_TRAIN_NONE;
3049                 temp |= FDI_LINK_TRAIN_NONE;
3050         }
3051         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3052
3053         /* wait one idle pattern time */
3054         POSTING_READ(reg);
3055         udelay(1000);
3056
3057         /* IVB wants error correction enabled */
3058         if (IS_IVYBRIDGE(dev))
3059                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3060                            FDI_FE_ERRC_ENABLE);
3061 }
3062
3063 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3064 {
3065         return crtc->base.state->enable && crtc->active &&
3066                 crtc->config->has_pch_encoder;
3067 }
3068
3069 static void ivb_modeset_global_resources(struct drm_device *dev)
3070 {
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *pipe_B_crtc =
3073                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3074         struct intel_crtc *pipe_C_crtc =
3075                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3076         uint32_t temp;
3077
3078         /*
3079          * When everything is off disable fdi C so that we could enable fdi B
3080          * with all lanes. Note that we don't care about enabled pipes without
3081          * an enabled pch encoder.
3082          */
3083         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3084             !pipe_has_enabled_pch(pipe_C_crtc)) {
3085                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3086                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3087
3088                 temp = I915_READ(SOUTH_CHICKEN1);
3089                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3090                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091                 I915_WRITE(SOUTH_CHICKEN1, temp);
3092         }
3093 }
3094
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3097 {
3098         struct drm_device *dev = crtc->dev;
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101         int pipe = intel_crtc->pipe;
3102         u32 reg, temp, tries;
3103
3104         /* FDI needs bits from pipe first */
3105         assert_pipe_enabled(dev_priv, pipe);
3106
3107         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108            for train result */
3109         reg = FDI_RX_IMR(pipe);
3110         temp = I915_READ(reg);
3111         temp &= ~FDI_RX_SYMBOL_LOCK;
3112         temp &= ~FDI_RX_BIT_LOCK;
3113         I915_WRITE(reg, temp);
3114         I915_READ(reg);
3115         udelay(150);
3116
3117         /* enable CPU FDI TX and PCH FDI RX */
3118         reg = FDI_TX_CTL(pipe);
3119         temp = I915_READ(reg);
3120         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3121         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3122         temp &= ~FDI_LINK_TRAIN_NONE;
3123         temp |= FDI_LINK_TRAIN_PATTERN_1;
3124         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3125
3126         reg = FDI_RX_CTL(pipe);
3127         temp = I915_READ(reg);
3128         temp &= ~FDI_LINK_TRAIN_NONE;
3129         temp |= FDI_LINK_TRAIN_PATTERN_1;
3130         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3131
3132         POSTING_READ(reg);
3133         udelay(150);
3134
3135         /* Ironlake workaround, enable clock pointer after FDI enable*/
3136         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3137         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3138                    FDI_RX_PHASE_SYNC_POINTER_EN);
3139
3140         reg = FDI_RX_IIR(pipe);
3141         for (tries = 0; tries < 5; tries++) {
3142                 temp = I915_READ(reg);
3143                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3144
3145                 if ((temp & FDI_RX_BIT_LOCK)) {
3146                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3147                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3148                         break;
3149                 }
3150         }
3151         if (tries == 5)
3152                 DRM_ERROR("FDI train 1 fail!\n");
3153
3154         /* Train 2 */
3155         reg = FDI_TX_CTL(pipe);
3156         temp = I915_READ(reg);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_2;
3159         I915_WRITE(reg, temp);
3160
3161         reg = FDI_RX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         temp &= ~FDI_LINK_TRAIN_NONE;
3164         temp |= FDI_LINK_TRAIN_PATTERN_2;
3165         I915_WRITE(reg, temp);
3166
3167         POSTING_READ(reg);
3168         udelay(150);
3169
3170         reg = FDI_RX_IIR(pipe);
3171         for (tries = 0; tries < 5; tries++) {
3172                 temp = I915_READ(reg);
3173                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3174
3175                 if (temp & FDI_RX_SYMBOL_LOCK) {
3176                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3177                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3178                         break;
3179                 }
3180         }
3181         if (tries == 5)
3182                 DRM_ERROR("FDI train 2 fail!\n");
3183
3184         DRM_DEBUG_KMS("FDI train done\n");
3185
3186 }
3187
3188 static const int snb_b_fdi_train_param[] = {
3189         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3190         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3191         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3192         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3193 };
3194
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201         int pipe = intel_crtc->pipe;
3202         u32 reg, temp, i, retry;
3203
3204         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3205            for train result */
3206         reg = FDI_RX_IMR(pipe);
3207         temp = I915_READ(reg);
3208         temp &= ~FDI_RX_SYMBOL_LOCK;
3209         temp &= ~FDI_RX_BIT_LOCK;
3210         I915_WRITE(reg, temp);
3211
3212         POSTING_READ(reg);
3213         udelay(150);
3214
3215         /* enable CPU FDI TX and PCH FDI RX */
3216         reg = FDI_TX_CTL(pipe);
3217         temp = I915_READ(reg);
3218         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3219         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3220         temp &= ~FDI_LINK_TRAIN_NONE;
3221         temp |= FDI_LINK_TRAIN_PATTERN_1;
3222         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3223         /* SNB-B */
3224         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3225         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3226
3227         I915_WRITE(FDI_RX_MISC(pipe),
3228                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3229
3230         reg = FDI_RX_CTL(pipe);
3231         temp = I915_READ(reg);
3232         if (HAS_PCH_CPT(dev)) {
3233                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3234                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3235         } else {
3236                 temp &= ~FDI_LINK_TRAIN_NONE;
3237                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3238         }
3239         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3240
3241         POSTING_READ(reg);
3242         udelay(150);
3243
3244         for (i = 0; i < 4; i++) {
3245                 reg = FDI_TX_CTL(pipe);
3246                 temp = I915_READ(reg);
3247                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3248                 temp |= snb_b_fdi_train_param[i];
3249                 I915_WRITE(reg, temp);
3250
3251                 POSTING_READ(reg);
3252                 udelay(500);
3253
3254                 for (retry = 0; retry < 5; retry++) {
3255                         reg = FDI_RX_IIR(pipe);
3256                         temp = I915_READ(reg);
3257                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3258                         if (temp & FDI_RX_BIT_LOCK) {
3259                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3260                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3261                                 break;
3262                         }
3263                         udelay(50);
3264                 }
3265                 if (retry < 5)
3266                         break;
3267         }
3268         if (i == 4)
3269                 DRM_ERROR("FDI train 1 fail!\n");
3270
3271         /* Train 2 */
3272         reg = FDI_TX_CTL(pipe);
3273         temp = I915_READ(reg);
3274         temp &= ~FDI_LINK_TRAIN_NONE;
3275         temp |= FDI_LINK_TRAIN_PATTERN_2;
3276         if (IS_GEN6(dev)) {
3277                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278                 /* SNB-B */
3279                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3280         }
3281         I915_WRITE(reg, temp);
3282
3283         reg = FDI_RX_CTL(pipe);
3284         temp = I915_READ(reg);
3285         if (HAS_PCH_CPT(dev)) {
3286                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3287                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3288         } else {
3289                 temp &= ~FDI_LINK_TRAIN_NONE;
3290                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3291         }
3292         I915_WRITE(reg, temp);
3293
3294         POSTING_READ(reg);
3295         udelay(150);
3296
3297         for (i = 0; i < 4; i++) {
3298                 reg = FDI_TX_CTL(pipe);
3299                 temp = I915_READ(reg);
3300                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3301                 temp |= snb_b_fdi_train_param[i];
3302                 I915_WRITE(reg, temp);
3303
3304                 POSTING_READ(reg);
3305                 udelay(500);
3306
3307                 for (retry = 0; retry < 5; retry++) {
3308                         reg = FDI_RX_IIR(pipe);
3309                         temp = I915_READ(reg);
3310                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3311                         if (temp & FDI_RX_SYMBOL_LOCK) {
3312                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3313                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3314                                 break;
3315                         }
3316                         udelay(50);
3317                 }
3318                 if (retry < 5)
3319                         break;
3320         }
3321         if (i == 4)
3322                 DRM_ERROR("FDI train 2 fail!\n");
3323
3324         DRM_DEBUG_KMS("FDI train done.\n");
3325 }
3326
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3329 {
3330         struct drm_device *dev = crtc->dev;
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333         int pipe = intel_crtc->pipe;
3334         u32 reg, temp, i, j;
3335
3336         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3337            for train result */
3338         reg = FDI_RX_IMR(pipe);
3339         temp = I915_READ(reg);
3340         temp &= ~FDI_RX_SYMBOL_LOCK;
3341         temp &= ~FDI_RX_BIT_LOCK;
3342         I915_WRITE(reg, temp);
3343
3344         POSTING_READ(reg);
3345         udelay(150);
3346
3347         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348                       I915_READ(FDI_RX_IIR(pipe)));
3349
3350         /* Try each vswing and preemphasis setting twice before moving on */
3351         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3352                 /* disable first in case we need to retry */
3353                 reg = FDI_TX_CTL(pipe);
3354                 temp = I915_READ(reg);
3355                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3356                 temp &= ~FDI_TX_ENABLE;
3357                 I915_WRITE(reg, temp);
3358
3359                 reg = FDI_RX_CTL(pipe);
3360                 temp = I915_READ(reg);
3361                 temp &= ~FDI_LINK_TRAIN_AUTO;
3362                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363                 temp &= ~FDI_RX_ENABLE;
3364                 I915_WRITE(reg, temp);
3365
3366                 /* enable CPU FDI TX and PCH FDI RX */
3367                 reg = FDI_TX_CTL(pipe);
3368                 temp = I915_READ(reg);
3369                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3370                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3371                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3372                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3373                 temp |= snb_b_fdi_train_param[j/2];
3374                 temp |= FDI_COMPOSITE_SYNC;
3375                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3376
3377                 I915_WRITE(FDI_RX_MISC(pipe),
3378                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3379
3380                 reg = FDI_RX_CTL(pipe);
3381                 temp = I915_READ(reg);
3382                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3383                 temp |= FDI_COMPOSITE_SYNC;
3384                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3385
3386                 POSTING_READ(reg);
3387                 udelay(1); /* should be 0.5us */
3388
3389                 for (i = 0; i < 4; i++) {
3390                         reg = FDI_RX_IIR(pipe);
3391                         temp = I915_READ(reg);
3392                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393
3394                         if (temp & FDI_RX_BIT_LOCK ||
3395                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3396                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3397                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3398                                               i);
3399                                 break;
3400                         }
3401                         udelay(1); /* should be 0.5us */
3402                 }
3403                 if (i == 4) {
3404                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3405                         continue;
3406                 }
3407
3408                 /* Train 2 */
3409                 reg = FDI_TX_CTL(pipe);
3410                 temp = I915_READ(reg);
3411                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3413                 I915_WRITE(reg, temp);
3414
3415                 reg = FDI_RX_CTL(pipe);
3416                 temp = I915_READ(reg);
3417                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3419                 I915_WRITE(reg, temp);
3420
3421                 POSTING_READ(reg);
3422                 udelay(2); /* should be 1.5us */
3423
3424                 for (i = 0; i < 4; i++) {
3425                         reg = FDI_RX_IIR(pipe);
3426                         temp = I915_READ(reg);
3427                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429                         if (temp & FDI_RX_SYMBOL_LOCK ||
3430                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3431                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3433                                               i);
3434                                 goto train_done;
3435                         }
3436                         udelay(2); /* should be 1.5us */
3437                 }
3438                 if (i == 4)
3439                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3440         }
3441
3442 train_done:
3443         DRM_DEBUG_KMS("FDI train done.\n");
3444 }
3445
3446 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3447 {
3448         struct drm_device *dev = intel_crtc->base.dev;
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450         int pipe = intel_crtc->pipe;
3451         u32 reg, temp;
3452
3453
3454         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3458         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3460         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3461
3462         POSTING_READ(reg);
3463         udelay(200);
3464
3465         /* Switch from Rawclk to PCDclk */
3466         temp = I915_READ(reg);
3467         I915_WRITE(reg, temp | FDI_PCDCLK);
3468
3469         POSTING_READ(reg);
3470         udelay(200);
3471
3472         /* Enable CPU FDI TX PLL, always on for Ironlake */
3473         reg = FDI_TX_CTL(pipe);
3474         temp = I915_READ(reg);
3475         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3476                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3477
3478                 POSTING_READ(reg);
3479                 udelay(100);
3480         }
3481 }
3482
3483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3484 {
3485         struct drm_device *dev = intel_crtc->base.dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         int pipe = intel_crtc->pipe;
3488         u32 reg, temp;
3489
3490         /* Switch from PCDclk to Rawclk */
3491         reg = FDI_RX_CTL(pipe);
3492         temp = I915_READ(reg);
3493         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3494
3495         /* Disable CPU FDI TX PLL */
3496         reg = FDI_TX_CTL(pipe);
3497         temp = I915_READ(reg);
3498         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3499
3500         POSTING_READ(reg);
3501         udelay(100);
3502
3503         reg = FDI_RX_CTL(pipe);
3504         temp = I915_READ(reg);
3505         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3506
3507         /* Wait for the clocks to turn off. */
3508         POSTING_READ(reg);
3509         udelay(100);
3510 }
3511
3512 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3513 {
3514         struct drm_device *dev = crtc->dev;
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517         int pipe = intel_crtc->pipe;
3518         u32 reg, temp;
3519
3520         /* disable CPU FDI tx and PCH FDI rx */
3521         reg = FDI_TX_CTL(pipe);
3522         temp = I915_READ(reg);
3523         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3524         POSTING_READ(reg);
3525
3526         reg = FDI_RX_CTL(pipe);
3527         temp = I915_READ(reg);
3528         temp &= ~(0x7 << 16);
3529         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3530         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3531
3532         POSTING_READ(reg);
3533         udelay(100);
3534
3535         /* Ironlake workaround, disable clock pointer after downing FDI */
3536         if (HAS_PCH_IBX(dev))
3537                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3538
3539         /* still set train pattern 1 */
3540         reg = FDI_TX_CTL(pipe);
3541         temp = I915_READ(reg);
3542         temp &= ~FDI_LINK_TRAIN_NONE;
3543         temp |= FDI_LINK_TRAIN_PATTERN_1;
3544         I915_WRITE(reg, temp);
3545
3546         reg = FDI_RX_CTL(pipe);
3547         temp = I915_READ(reg);
3548         if (HAS_PCH_CPT(dev)) {
3549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3551         } else {
3552                 temp &= ~FDI_LINK_TRAIN_NONE;
3553                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3554         }
3555         /* BPC in FDI rx is consistent with that in PIPECONF */
3556         temp &= ~(0x07 << 16);
3557         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3558         I915_WRITE(reg, temp);
3559
3560         POSTING_READ(reg);
3561         udelay(100);
3562 }
3563
3564 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3565 {
3566         struct intel_crtc *crtc;
3567
3568         /* Note that we don't need to be called with mode_config.lock here
3569          * as our list of CRTC objects is static for the lifetime of the
3570          * device and so cannot disappear as we iterate. Similarly, we can
3571          * happily treat the predicates as racy, atomic checks as userspace
3572          * cannot claim and pin a new fb without at least acquring the
3573          * struct_mutex and so serialising with us.
3574          */
3575         for_each_intel_crtc(dev, crtc) {
3576                 if (atomic_read(&crtc->unpin_work_count) == 0)
3577                         continue;
3578
3579                 if (crtc->unpin_work)
3580                         intel_wait_for_vblank(dev, crtc->pipe);
3581
3582                 return true;
3583         }
3584
3585         return false;
3586 }
3587
3588 static void page_flip_completed(struct intel_crtc *intel_crtc)
3589 {
3590         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3591         struct intel_unpin_work *work = intel_crtc->unpin_work;
3592
3593         /* ensure that the unpin work is consistent wrt ->pending. */
3594         smp_rmb();
3595         intel_crtc->unpin_work = NULL;
3596
3597         if (work->event)
3598                 drm_send_vblank_event(intel_crtc->base.dev,
3599                                       intel_crtc->pipe,
3600                                       work->event);
3601
3602         drm_crtc_vblank_put(&intel_crtc->base);
3603
3604         wake_up_all(&dev_priv->pending_flip_queue);
3605         queue_work(dev_priv->wq, &work->work);
3606
3607         trace_i915_flip_complete(intel_crtc->plane,
3608                                  work->pending_flip_obj);
3609 }
3610
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3612 {
3613         struct drm_device *dev = crtc->dev;
3614         struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3617         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3618                                        !intel_crtc_has_pending_flip(crtc),
3619                                        60*HZ) == 0)) {
3620                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622                 spin_lock_irq(&dev->event_lock);
3623                 if (intel_crtc->unpin_work) {
3624                         WARN_ONCE(1, "Removing stuck page flip\n");
3625                         page_flip_completed(intel_crtc);
3626                 }
3627                 spin_unlock_irq(&dev->event_lock);
3628         }
3629
3630         if (crtc->primary->fb) {
3631                 mutex_lock(&dev->struct_mutex);
3632                 intel_finish_fb(crtc->primary->fb);
3633                 mutex_unlock(&dev->struct_mutex);
3634         }
3635 }
3636
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3643         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3644         u32 temp;
3645
3646         mutex_lock(&dev_priv->dpio_lock);
3647
3648         /* It is necessary to ungate the pixclk gate prior to programming
3649          * the divisors, and gate it back when it is done.
3650          */
3651         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3652
3653         /* Disable SSCCTL */
3654         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3655                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3656                                 SBI_SSCCTL_DISABLE,
3657                         SBI_ICLK);
3658
3659         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660         if (clock == 20000) {
3661                 auxdiv = 1;
3662                 divsel = 0x41;
3663                 phaseinc = 0x20;
3664         } else {
3665                 /* The iCLK virtual clock root frequency is in MHz,
3666                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3667                  * divisors, it is necessary to divide one by another, so we
3668                  * convert the virtual clock precision to KHz here for higher
3669                  * precision.
3670                  */
3671                 u32 iclk_virtual_root_freq = 172800 * 1000;
3672                 u32 iclk_pi_range = 64;
3673                 u32 desired_divisor, msb_divisor_value, pi_value;
3674
3675                 desired_divisor = (iclk_virtual_root_freq / clock);
3676                 msb_divisor_value = desired_divisor / iclk_pi_range;
3677                 pi_value = desired_divisor % iclk_pi_range;
3678
3679                 auxdiv = 0;
3680                 divsel = msb_divisor_value - 2;
3681                 phaseinc = pi_value;
3682         }
3683
3684         /* This should not happen with any sane values */
3685         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3686                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3687         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3688                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3689
3690         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3691                         clock,
3692                         auxdiv,
3693                         divsel,
3694                         phasedir,
3695                         phaseinc);
3696
3697         /* Program SSCDIVINTPHASE6 */
3698         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3699         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3700         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3701         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3702         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3703         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3704         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3705         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3706
3707         /* Program SSCAUXDIV */
3708         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3709         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3711         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3712
3713         /* Enable modulator and associated divider */
3714         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3715         temp &= ~SBI_SSCCTL_DISABLE;
3716         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3717
3718         /* Wait for initialization time */
3719         udelay(24);
3720
3721         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3722
3723         mutex_unlock(&dev_priv->dpio_lock);
3724 }
3725
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3727                                                 enum pipe pch_transcoder)
3728 {
3729         struct drm_device *dev = crtc->base.dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3732
3733         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3734                    I915_READ(HTOTAL(cpu_transcoder)));
3735         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3736                    I915_READ(HBLANK(cpu_transcoder)));
3737         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3738                    I915_READ(HSYNC(cpu_transcoder)));
3739
3740         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3741                    I915_READ(VTOTAL(cpu_transcoder)));
3742         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3743                    I915_READ(VBLANK(cpu_transcoder)));
3744         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3745                    I915_READ(VSYNC(cpu_transcoder)));
3746         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3747                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3748 }
3749
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3751 {
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         uint32_t temp;
3754
3755         temp = I915_READ(SOUTH_CHICKEN1);
3756         if (temp & FDI_BC_BIFURCATION_SELECT)
3757                 return;
3758
3759         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3760         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3761
3762         temp |= FDI_BC_BIFURCATION_SELECT;
3763         DRM_DEBUG_KMS("enabling fdi C rx\n");
3764         I915_WRITE(SOUTH_CHICKEN1, temp);
3765         POSTING_READ(SOUTH_CHICKEN1);
3766 }
3767
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3769 {
3770         struct drm_device *dev = intel_crtc->base.dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772
3773         switch (intel_crtc->pipe) {
3774         case PIPE_A:
3775                 break;
3776         case PIPE_B:
3777                 if (intel_crtc->config->fdi_lanes > 2)
3778                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3779                 else
3780                         cpt_enable_fdi_bc_bifurcation(dev);
3781
3782                 break;
3783         case PIPE_C:
3784                 cpt_enable_fdi_bc_bifurcation(dev);
3785
3786                 break;
3787         default:
3788                 BUG();
3789         }
3790 }
3791
3792 /*
3793  * Enable PCH resources required for PCH ports:
3794  *   - PCH PLLs
3795  *   - FDI training & RX/TX
3796  *   - update transcoder timings
3797  *   - DP transcoding bits
3798  *   - transcoder
3799  */
3800 static void ironlake_pch_enable(struct drm_crtc *crtc)
3801 {
3802         struct drm_device *dev = crtc->dev;
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805         int pipe = intel_crtc->pipe;
3806         u32 reg, temp;
3807
3808         assert_pch_transcoder_disabled(dev_priv, pipe);
3809
3810         if (IS_IVYBRIDGE(dev))
3811                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3812
3813         /* Write the TU size bits before fdi link training, so that error
3814          * detection works. */
3815         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3816                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3817
3818         /* For PCH output, training FDI link */
3819         dev_priv->display.fdi_link_train(crtc);
3820
3821         /* We need to program the right clock selection before writing the pixel
3822          * mutliplier into the DPLL. */
3823         if (HAS_PCH_CPT(dev)) {
3824                 u32 sel;
3825
3826                 temp = I915_READ(PCH_DPLL_SEL);
3827                 temp |= TRANS_DPLL_ENABLE(pipe);
3828                 sel = TRANS_DPLLB_SEL(pipe);
3829                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3830                         temp |= sel;
3831                 else
3832                         temp &= ~sel;
3833                 I915_WRITE(PCH_DPLL_SEL, temp);
3834         }
3835
3836         /* XXX: pch pll's can be enabled any time before we enable the PCH
3837          * transcoder, and we actually should do this to not upset any PCH
3838          * transcoder that already use the clock when we share it.
3839          *
3840          * Note that enable_shared_dpll tries to do the right thing, but
3841          * get_shared_dpll unconditionally resets the pll - we need that to have
3842          * the right LVDS enable sequence. */
3843         intel_enable_shared_dpll(intel_crtc);
3844
3845         /* set transcoder timing, panel must allow it */
3846         assert_panel_unlocked(dev_priv, pipe);
3847         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3848
3849         intel_fdi_normal_train(crtc);
3850
3851         /* For PCH DP, enable TRANS_DP_CTL */
3852         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3853                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3854                 reg = TRANS_DP_CTL(pipe);
3855                 temp = I915_READ(reg);
3856                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3857                           TRANS_DP_SYNC_MASK |
3858                           TRANS_DP_BPC_MASK);
3859                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3860                          TRANS_DP_ENH_FRAMING);
3861                 temp |= bpc << 9; /* same format but at 11:9 */
3862
3863                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3864                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3865                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3866                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3867
3868                 switch (intel_trans_dp_port_sel(crtc)) {
3869                 case PCH_DP_B:
3870                         temp |= TRANS_DP_PORT_SEL_B;
3871                         break;
3872                 case PCH_DP_C:
3873                         temp |= TRANS_DP_PORT_SEL_C;
3874                         break;
3875                 case PCH_DP_D:
3876                         temp |= TRANS_DP_PORT_SEL_D;
3877                         break;
3878                 default:
3879                         BUG();
3880                 }
3881
3882                 I915_WRITE(reg, temp);
3883         }
3884
3885         ironlake_enable_pch_transcoder(dev_priv, pipe);
3886 }
3887
3888 static void lpt_pch_enable(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3894
3895         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3896
3897         lpt_program_iclkip(crtc);
3898
3899         /* Set transcoder timing. */
3900         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3901
3902         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3903 }
3904
3905 void intel_put_shared_dpll(struct intel_crtc *crtc)
3906 {
3907         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3908
3909         if (pll == NULL)
3910                 return;
3911
3912         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3913                 WARN(1, "bad %s crtc mask\n", pll->name);
3914                 return;
3915         }
3916
3917         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3918         if (pll->config.crtc_mask == 0) {
3919                 WARN_ON(pll->on);
3920                 WARN_ON(pll->active);
3921         }
3922
3923         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3924 }
3925
3926 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3927                                                 struct intel_crtc_state *crtc_state)
3928 {
3929         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3930         struct intel_shared_dpll *pll;
3931         enum intel_dpll_id i;
3932
3933         if (HAS_PCH_IBX(dev_priv->dev)) {
3934                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3935                 i = (enum intel_dpll_id) crtc->pipe;
3936                 pll = &dev_priv->shared_dplls[i];
3937
3938                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3939                               crtc->base.base.id, pll->name);
3940
3941                 WARN_ON(pll->new_config->crtc_mask);
3942
3943                 goto found;
3944         }
3945
3946         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3947                 pll = &dev_priv->shared_dplls[i];
3948
3949                 /* Only want to check enabled timings first */
3950                 if (pll->new_config->crtc_mask == 0)
3951                         continue;
3952
3953                 if (memcmp(&crtc_state->dpll_hw_state,
3954                            &pll->new_config->hw_state,
3955                            sizeof(pll->new_config->hw_state)) == 0) {
3956                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3957                                       crtc->base.base.id, pll->name,
3958                                       pll->new_config->crtc_mask,
3959                                       pll->active);
3960                         goto found;
3961                 }
3962         }
3963
3964         /* Ok no matching timings, maybe there's a free one? */
3965         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3966                 pll = &dev_priv->shared_dplls[i];
3967                 if (pll->new_config->crtc_mask == 0) {
3968                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3969                                       crtc->base.base.id, pll->name);
3970                         goto found;
3971                 }
3972         }
3973
3974         return NULL;
3975
3976 found:
3977         if (pll->new_config->crtc_mask == 0)
3978                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3979
3980         crtc_state->shared_dpll = i;
3981         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3982                          pipe_name(crtc->pipe));
3983
3984         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3985
3986         return pll;
3987 }
3988
3989 /**
3990  * intel_shared_dpll_start_config - start a new PLL staged config
3991  * @dev_priv: DRM device
3992  * @clear_pipes: mask of pipes that will have their PLLs freed
3993  *
3994  * Starts a new PLL staged config, copying the current config but
3995  * releasing the references of pipes specified in clear_pipes.
3996  */
3997 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3998                                           unsigned clear_pipes)
3999 {
4000         struct intel_shared_dpll *pll;
4001         enum intel_dpll_id i;
4002
4003         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4004                 pll = &dev_priv->shared_dplls[i];
4005
4006                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4007                                           GFP_KERNEL);
4008                 if (!pll->new_config)
4009                         goto cleanup;
4010
4011                 pll->new_config->crtc_mask &= ~clear_pipes;
4012         }
4013
4014         return 0;
4015
4016 cleanup:
4017         while (--i >= 0) {
4018                 pll = &dev_priv->shared_dplls[i];
4019                 kfree(pll->new_config);
4020                 pll->new_config = NULL;
4021         }
4022
4023         return -ENOMEM;
4024 }
4025
4026 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4027 {
4028         struct intel_shared_dpll *pll;
4029         enum intel_dpll_id i;
4030
4031         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4032                 pll = &dev_priv->shared_dplls[i];
4033
4034                 WARN_ON(pll->new_config == &pll->config);
4035
4036                 pll->config = *pll->new_config;
4037                 kfree(pll->new_config);
4038                 pll->new_config = NULL;
4039         }
4040 }
4041
4042 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4043 {
4044         struct intel_shared_dpll *pll;
4045         enum intel_dpll_id i;
4046
4047         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4048                 pll = &dev_priv->shared_dplls[i];
4049
4050                 WARN_ON(pll->new_config == &pll->config);
4051
4052                 kfree(pll->new_config);
4053                 pll->new_config = NULL;
4054         }
4055 }
4056
4057 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4058 {
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         int dslreg = PIPEDSL(pipe);
4061         u32 temp;
4062
4063         temp = I915_READ(dslreg);
4064         udelay(500);
4065         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4066                 if (wait_for(I915_READ(dslreg) != temp, 5))
4067                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4068         }
4069 }
4070
4071 static void skylake_pfit_enable(struct intel_crtc *crtc)
4072 {
4073         struct drm_device *dev = crtc->base.dev;
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         int pipe = crtc->pipe;
4076
4077         if (crtc->config->pch_pfit.enabled) {
4078                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4079                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4080                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4081         }
4082 }
4083
4084 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4085 {
4086         struct drm_device *dev = crtc->base.dev;
4087         struct drm_i915_private *dev_priv = dev->dev_private;
4088         int pipe = crtc->pipe;
4089
4090         if (crtc->config->pch_pfit.enabled) {
4091                 /* Force use of hard-coded filter coefficients
4092                  * as some pre-programmed values are broken,
4093                  * e.g. x201.
4094                  */
4095                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4096                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4097                                                  PF_PIPE_SEL_IVB(pipe));
4098                 else
4099                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4100                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4101                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4102         }
4103 }
4104
4105 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4109         struct drm_plane *plane;
4110         struct intel_plane *intel_plane;
4111
4112         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4113                 intel_plane = to_intel_plane(plane);
4114                 if (intel_plane->pipe == pipe)
4115                         intel_plane_restore(&intel_plane->base);
4116         }
4117 }
4118
4119 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4120 {
4121         struct drm_device *dev = crtc->dev;
4122         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4123         struct drm_plane *plane;
4124         struct intel_plane *intel_plane;
4125
4126         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4127                 intel_plane = to_intel_plane(plane);
4128                 if (intel_plane->pipe == pipe)
4129                         plane->funcs->disable_plane(plane);
4130         }
4131 }
4132
4133 void hsw_enable_ips(struct intel_crtc *crtc)
4134 {
4135         struct drm_device *dev = crtc->base.dev;
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137
4138         if (!crtc->config->ips_enabled)
4139                 return;
4140
4141         /* We can only enable IPS after we enable a plane and wait for a vblank */
4142         intel_wait_for_vblank(dev, crtc->pipe);
4143
4144         assert_plane_enabled(dev_priv, crtc->plane);
4145         if (IS_BROADWELL(dev)) {
4146                 mutex_lock(&dev_priv->rps.hw_lock);
4147                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4148                 mutex_unlock(&dev_priv->rps.hw_lock);
4149                 /* Quoting Art Runyan: "its not safe to expect any particular
4150                  * value in IPS_CTL bit 31 after enabling IPS through the
4151                  * mailbox." Moreover, the mailbox may return a bogus state,
4152                  * so we need to just enable it and continue on.
4153                  */
4154         } else {
4155                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4156                 /* The bit only becomes 1 in the next vblank, so this wait here
4157                  * is essentially intel_wait_for_vblank. If we don't have this
4158                  * and don't wait for vblanks until the end of crtc_enable, then
4159                  * the HW state readout code will complain that the expected
4160                  * IPS_CTL value is not the one we read. */
4161                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4162                         DRM_ERROR("Timed out waiting for IPS enable\n");
4163         }
4164 }
4165
4166 void hsw_disable_ips(struct intel_crtc *crtc)
4167 {
4168         struct drm_device *dev = crtc->base.dev;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170
4171         if (!crtc->config->ips_enabled)
4172                 return;
4173
4174         assert_plane_enabled(dev_priv, crtc->plane);
4175         if (IS_BROADWELL(dev)) {
4176                 mutex_lock(&dev_priv->rps.hw_lock);
4177                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4178                 mutex_unlock(&dev_priv->rps.hw_lock);
4179                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4180                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4181                         DRM_ERROR("Timed out waiting for IPS disable\n");
4182         } else {
4183                 I915_WRITE(IPS_CTL, 0);
4184                 POSTING_READ(IPS_CTL);
4185         }
4186
4187         /* We need to wait for a vblank before we can disable the plane. */
4188         intel_wait_for_vblank(dev, crtc->pipe);
4189 }
4190
4191 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4192 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4193 {
4194         struct drm_device *dev = crtc->dev;
4195         struct drm_i915_private *dev_priv = dev->dev_private;
4196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197         enum pipe pipe = intel_crtc->pipe;
4198         int palreg = PALETTE(pipe);
4199         int i;
4200         bool reenable_ips = false;
4201
4202         /* The clocks have to be on to load the palette. */
4203         if (!crtc->state->enable || !intel_crtc->active)
4204                 return;
4205
4206         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4207                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4208                         assert_dsi_pll_enabled(dev_priv);
4209                 else
4210                         assert_pll_enabled(dev_priv, pipe);
4211         }
4212
4213         /* use legacy palette for Ironlake */
4214         if (!HAS_GMCH_DISPLAY(dev))
4215                 palreg = LGC_PALETTE(pipe);
4216
4217         /* Workaround : Do not read or write the pipe palette/gamma data while
4218          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4219          */
4220         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4221             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4222              GAMMA_MODE_MODE_SPLIT)) {
4223                 hsw_disable_ips(intel_crtc);
4224                 reenable_ips = true;
4225         }
4226
4227         for (i = 0; i < 256; i++) {
4228                 I915_WRITE(palreg + 4 * i,
4229                            (intel_crtc->lut_r[i] << 16) |
4230                            (intel_crtc->lut_g[i] << 8) |
4231                            intel_crtc->lut_b[i]);
4232         }
4233
4234         if (reenable_ips)
4235                 hsw_enable_ips(intel_crtc);
4236 }
4237
4238 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4239 {
4240         if (!enable && intel_crtc->overlay) {
4241                 struct drm_device *dev = intel_crtc->base.dev;
4242                 struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244                 mutex_lock(&dev->struct_mutex);
4245                 dev_priv->mm.interruptible = false;
4246                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4247                 dev_priv->mm.interruptible = true;
4248                 mutex_unlock(&dev->struct_mutex);
4249         }
4250
4251         /* Let userspace switch the overlay on again. In most cases userspace
4252          * has to recompute where to put it anyway.
4253          */
4254 }
4255
4256 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260         int pipe = intel_crtc->pipe;
4261
4262         intel_enable_primary_hw_plane(crtc->primary, crtc);
4263         intel_enable_sprite_planes(crtc);
4264         intel_crtc_update_cursor(crtc, true);
4265         intel_crtc_dpms_overlay(intel_crtc, true);
4266
4267         hsw_enable_ips(intel_crtc);
4268
4269         mutex_lock(&dev->struct_mutex);
4270         intel_fbc_update(dev);
4271         mutex_unlock(&dev->struct_mutex);
4272
4273         /*
4274          * FIXME: Once we grow proper nuclear flip support out of this we need
4275          * to compute the mask of flip planes precisely. For the time being
4276          * consider this a flip from a NULL plane.
4277          */
4278         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4279 }
4280
4281 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4282 {
4283         struct drm_device *dev = crtc->dev;
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286         int pipe = intel_crtc->pipe;
4287
4288         intel_crtc_wait_for_pending_flips(crtc);
4289
4290         if (dev_priv->fbc.crtc == intel_crtc)
4291                 intel_fbc_disable(dev);
4292
4293         hsw_disable_ips(intel_crtc);
4294
4295         intel_crtc_dpms_overlay(intel_crtc, false);
4296         intel_crtc_update_cursor(crtc, false);
4297         intel_disable_sprite_planes(crtc);
4298         intel_disable_primary_hw_plane(crtc->primary, crtc);
4299
4300         /*
4301          * FIXME: Once we grow proper nuclear flip support out of this we need
4302          * to compute the mask of flip planes precisely. For the time being
4303          * consider this a flip to a NULL plane.
4304          */
4305         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4306 }
4307
4308 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4309 {
4310         struct drm_device *dev = crtc->dev;
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313         struct intel_encoder *encoder;
4314         int pipe = intel_crtc->pipe;
4315
4316         WARN_ON(!crtc->state->enable);
4317
4318         if (intel_crtc->active)
4319                 return;
4320
4321         if (intel_crtc->config->has_pch_encoder)
4322                 intel_prepare_shared_dpll(intel_crtc);
4323
4324         if (intel_crtc->config->has_dp_encoder)
4325                 intel_dp_set_m_n(intel_crtc, M1_N1);
4326
4327         intel_set_pipe_timings(intel_crtc);
4328
4329         if (intel_crtc->config->has_pch_encoder) {
4330                 intel_cpu_transcoder_set_m_n(intel_crtc,
4331                                      &intel_crtc->config->fdi_m_n, NULL);
4332         }
4333
4334         ironlake_set_pipeconf(crtc);
4335
4336         intel_crtc->active = true;
4337
4338         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4339         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4340
4341         for_each_encoder_on_crtc(dev, crtc, encoder)
4342                 if (encoder->pre_enable)
4343                         encoder->pre_enable(encoder);
4344
4345         if (intel_crtc->config->has_pch_encoder) {
4346                 /* Note: FDI PLL enabling _must_ be done before we enable the
4347                  * cpu pipes, hence this is separate from all the other fdi/pch
4348                  * enabling. */
4349                 ironlake_fdi_pll_enable(intel_crtc);
4350         } else {
4351                 assert_fdi_tx_disabled(dev_priv, pipe);
4352                 assert_fdi_rx_disabled(dev_priv, pipe);
4353         }
4354
4355         ironlake_pfit_enable(intel_crtc);
4356
4357         /*
4358          * On ILK+ LUT must be loaded before the pipe is running but with
4359          * clocks enabled
4360          */
4361         intel_crtc_load_lut(crtc);
4362
4363         intel_update_watermarks(crtc);
4364         intel_enable_pipe(intel_crtc);
4365
4366         if (intel_crtc->config->has_pch_encoder)
4367                 ironlake_pch_enable(crtc);
4368
4369         assert_vblank_disabled(crtc);
4370         drm_crtc_vblank_on(crtc);
4371
4372         for_each_encoder_on_crtc(dev, crtc, encoder)
4373                 encoder->enable(encoder);
4374
4375         if (HAS_PCH_CPT(dev))
4376                 cpt_verify_modeset(dev, intel_crtc->pipe);
4377
4378         intel_crtc_enable_planes(crtc);
4379 }
4380
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4383 {
4384         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4385 }
4386
4387 /*
4388  * This implements the workaround described in the "notes" section of the mode
4389  * set sequence documentation. When going from no pipes or single pipe to
4390  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4392  */
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4394 {
4395         struct drm_device *dev = crtc->base.dev;
4396         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4397
4398         /* We want to get the other_active_crtc only if there's only 1 other
4399          * active crtc. */
4400         for_each_intel_crtc(dev, crtc_it) {
4401                 if (!crtc_it->active || crtc_it == crtc)
4402                         continue;
4403
4404                 if (other_active_crtc)
4405                         return;
4406
4407                 other_active_crtc = crtc_it;
4408         }
4409         if (!other_active_crtc)
4410                 return;
4411
4412         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4414 }
4415
4416 static void haswell_crtc_enable(struct drm_crtc *crtc)
4417 {
4418         struct drm_device *dev = crtc->dev;
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421         struct intel_encoder *encoder;
4422         int pipe = intel_crtc->pipe;
4423
4424         WARN_ON(!crtc->state->enable);
4425
4426         if (intel_crtc->active)
4427                 return;
4428
4429         if (intel_crtc_to_shared_dpll(intel_crtc))
4430                 intel_enable_shared_dpll(intel_crtc);
4431
4432         if (intel_crtc->config->has_dp_encoder)
4433                 intel_dp_set_m_n(intel_crtc, M1_N1);
4434
4435         intel_set_pipe_timings(intel_crtc);
4436
4437         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4438                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4439                            intel_crtc->config->pixel_multiplier - 1);
4440         }
4441
4442         if (intel_crtc->config->has_pch_encoder) {
4443                 intel_cpu_transcoder_set_m_n(intel_crtc,
4444                                      &intel_crtc->config->fdi_m_n, NULL);
4445         }
4446
4447         haswell_set_pipeconf(crtc);
4448
4449         intel_set_pipe_csc(crtc);
4450
4451         intel_crtc->active = true;
4452
4453         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4454         for_each_encoder_on_crtc(dev, crtc, encoder)
4455                 if (encoder->pre_enable)
4456                         encoder->pre_enable(encoder);
4457
4458         if (intel_crtc->config->has_pch_encoder) {
4459                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4460                                                       true);
4461                 dev_priv->display.fdi_link_train(crtc);
4462         }
4463
4464         intel_ddi_enable_pipe_clock(intel_crtc);
4465
4466         if (IS_SKYLAKE(dev))
4467                 skylake_pfit_enable(intel_crtc);
4468         else
4469                 ironlake_pfit_enable(intel_crtc);
4470
4471         /*
4472          * On ILK+ LUT must be loaded before the pipe is running but with
4473          * clocks enabled
4474          */
4475         intel_crtc_load_lut(crtc);
4476
4477         intel_ddi_set_pipe_settings(crtc);
4478         intel_ddi_enable_transcoder_func(crtc);
4479
4480         intel_update_watermarks(crtc);
4481         intel_enable_pipe(intel_crtc);
4482
4483         if (intel_crtc->config->has_pch_encoder)
4484                 lpt_pch_enable(crtc);
4485
4486         if (intel_crtc->config->dp_encoder_is_mst)
4487                 intel_ddi_set_vc_payload_alloc(crtc, true);
4488
4489         assert_vblank_disabled(crtc);
4490         drm_crtc_vblank_on(crtc);
4491
4492         for_each_encoder_on_crtc(dev, crtc, encoder) {
4493                 encoder->enable(encoder);
4494                 intel_opregion_notify_encoder(encoder, true);
4495         }
4496
4497         /* If we change the relative order between pipe/planes enabling, we need
4498          * to change the workaround. */
4499         haswell_mode_set_planes_workaround(intel_crtc);
4500         intel_crtc_enable_planes(crtc);
4501 }
4502
4503 static void skylake_pfit_disable(struct intel_crtc *crtc)
4504 {
4505         struct drm_device *dev = crtc->base.dev;
4506         struct drm_i915_private *dev_priv = dev->dev_private;
4507         int pipe = crtc->pipe;
4508
4509         /* To avoid upsetting the power well on haswell only disable the pfit if
4510          * it's in use. The hw state code will make sure we get this right. */
4511         if (crtc->config->pch_pfit.enabled) {
4512                 I915_WRITE(PS_CTL(pipe), 0);
4513                 I915_WRITE(PS_WIN_POS(pipe), 0);
4514                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4515         }
4516 }
4517
4518 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4519 {
4520         struct drm_device *dev = crtc->base.dev;
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522         int pipe = crtc->pipe;
4523
4524         /* To avoid upsetting the power well on haswell only disable the pfit if
4525          * it's in use. The hw state code will make sure we get this right. */
4526         if (crtc->config->pch_pfit.enabled) {
4527                 I915_WRITE(PF_CTL(pipe), 0);
4528                 I915_WRITE(PF_WIN_POS(pipe), 0);
4529                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4530         }
4531 }
4532
4533 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4534 {
4535         struct drm_device *dev = crtc->dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538         struct intel_encoder *encoder;
4539         int pipe = intel_crtc->pipe;
4540         u32 reg, temp;
4541
4542         if (!intel_crtc->active)
4543                 return;
4544
4545         intel_crtc_disable_planes(crtc);
4546
4547         for_each_encoder_on_crtc(dev, crtc, encoder)
4548                 encoder->disable(encoder);
4549
4550         drm_crtc_vblank_off(crtc);
4551         assert_vblank_disabled(crtc);
4552
4553         if (intel_crtc->config->has_pch_encoder)
4554                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556         intel_disable_pipe(intel_crtc);
4557
4558         ironlake_pfit_disable(intel_crtc);
4559
4560         for_each_encoder_on_crtc(dev, crtc, encoder)
4561                 if (encoder->post_disable)
4562                         encoder->post_disable(encoder);
4563
4564         if (intel_crtc->config->has_pch_encoder) {
4565                 ironlake_fdi_disable(crtc);
4566
4567                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4568
4569                 if (HAS_PCH_CPT(dev)) {
4570                         /* disable TRANS_DP_CTL */
4571                         reg = TRANS_DP_CTL(pipe);
4572                         temp = I915_READ(reg);
4573                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4574                                   TRANS_DP_PORT_SEL_MASK);
4575                         temp |= TRANS_DP_PORT_SEL_NONE;
4576                         I915_WRITE(reg, temp);
4577
4578                         /* disable DPLL_SEL */
4579                         temp = I915_READ(PCH_DPLL_SEL);
4580                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4581                         I915_WRITE(PCH_DPLL_SEL, temp);
4582                 }
4583
4584                 /* disable PCH DPLL */
4585                 intel_disable_shared_dpll(intel_crtc);
4586
4587                 ironlake_fdi_pll_disable(intel_crtc);
4588         }
4589
4590         intel_crtc->active = false;
4591         intel_update_watermarks(crtc);
4592
4593         mutex_lock(&dev->struct_mutex);
4594         intel_fbc_update(dev);
4595         mutex_unlock(&dev->struct_mutex);
4596 }
4597
4598 static void haswell_crtc_disable(struct drm_crtc *crtc)
4599 {
4600         struct drm_device *dev = crtc->dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4603         struct intel_encoder *encoder;
4604         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4605
4606         if (!intel_crtc->active)
4607                 return;
4608
4609         intel_crtc_disable_planes(crtc);
4610
4611         for_each_encoder_on_crtc(dev, crtc, encoder) {
4612                 intel_opregion_notify_encoder(encoder, false);
4613                 encoder->disable(encoder);
4614         }
4615
4616         drm_crtc_vblank_off(crtc);
4617         assert_vblank_disabled(crtc);
4618
4619         if (intel_crtc->config->has_pch_encoder)
4620                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4621                                                       false);
4622         intel_disable_pipe(intel_crtc);
4623
4624         if (intel_crtc->config->dp_encoder_is_mst)
4625                 intel_ddi_set_vc_payload_alloc(crtc, false);
4626
4627         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4628
4629         if (IS_SKYLAKE(dev))
4630                 skylake_pfit_disable(intel_crtc);
4631         else
4632                 ironlake_pfit_disable(intel_crtc);
4633
4634         intel_ddi_disable_pipe_clock(intel_crtc);
4635
4636         if (intel_crtc->config->has_pch_encoder) {
4637                 lpt_disable_pch_transcoder(dev_priv);
4638                 intel_ddi_fdi_disable(crtc);
4639         }
4640
4641         for_each_encoder_on_crtc(dev, crtc, encoder)
4642                 if (encoder->post_disable)
4643                         encoder->post_disable(encoder);
4644
4645         intel_crtc->active = false;
4646         intel_update_watermarks(crtc);
4647
4648         mutex_lock(&dev->struct_mutex);
4649         intel_fbc_update(dev);
4650         mutex_unlock(&dev->struct_mutex);
4651
4652         if (intel_crtc_to_shared_dpll(intel_crtc))
4653                 intel_disable_shared_dpll(intel_crtc);
4654 }
4655
4656 static void ironlake_crtc_off(struct drm_crtc *crtc)
4657 {
4658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659         intel_put_shared_dpll(intel_crtc);
4660 }
4661
4662
4663 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4664 {
4665         struct drm_device *dev = crtc->base.dev;
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         struct intel_crtc_state *pipe_config = crtc->config;
4668
4669         if (!pipe_config->gmch_pfit.control)
4670                 return;
4671
4672         /*
4673          * The panel fitter should only be adjusted whilst the pipe is disabled,
4674          * according to register description and PRM.
4675          */
4676         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4677         assert_pipe_disabled(dev_priv, crtc->pipe);
4678
4679         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4680         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4681
4682         /* Border color in case we don't scale up to the full screen. Black by
4683          * default, change to something else for debugging. */
4684         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4685 }
4686
4687 static enum intel_display_power_domain port_to_power_domain(enum port port)
4688 {
4689         switch (port) {
4690         case PORT_A:
4691                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4692         case PORT_B:
4693                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4694         case PORT_C:
4695                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4696         case PORT_D:
4697                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4698         default:
4699                 WARN_ON_ONCE(1);
4700                 return POWER_DOMAIN_PORT_OTHER;
4701         }
4702 }
4703
4704 #define for_each_power_domain(domain, mask)                             \
4705         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4706                 if ((1 << (domain)) & (mask))
4707
4708 enum intel_display_power_domain
4709 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4710 {
4711         struct drm_device *dev = intel_encoder->base.dev;
4712         struct intel_digital_port *intel_dig_port;
4713
4714         switch (intel_encoder->type) {
4715         case INTEL_OUTPUT_UNKNOWN:
4716                 /* Only DDI platforms should ever use this output type */
4717                 WARN_ON_ONCE(!HAS_DDI(dev));
4718         case INTEL_OUTPUT_DISPLAYPORT:
4719         case INTEL_OUTPUT_HDMI:
4720         case INTEL_OUTPUT_EDP:
4721                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4722                 return port_to_power_domain(intel_dig_port->port);
4723         case INTEL_OUTPUT_DP_MST:
4724                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4725                 return port_to_power_domain(intel_dig_port->port);
4726         case INTEL_OUTPUT_ANALOG:
4727                 return POWER_DOMAIN_PORT_CRT;
4728         case INTEL_OUTPUT_DSI:
4729                 return POWER_DOMAIN_PORT_DSI;
4730         default:
4731                 return POWER_DOMAIN_PORT_OTHER;
4732         }
4733 }
4734
4735 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4736 {
4737         struct drm_device *dev = crtc->dev;
4738         struct intel_encoder *intel_encoder;
4739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740         enum pipe pipe = intel_crtc->pipe;
4741         unsigned long mask;
4742         enum transcoder transcoder;
4743
4744         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4745
4746         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4747         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4748         if (intel_crtc->config->pch_pfit.enabled ||
4749             intel_crtc->config->pch_pfit.force_thru)
4750                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4751
4752         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4753                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4754
4755         return mask;
4756 }
4757
4758 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4759 {
4760         struct drm_i915_private *dev_priv = dev->dev_private;
4761         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4762         struct intel_crtc *crtc;
4763
4764         /*
4765          * First get all needed power domains, then put all unneeded, to avoid
4766          * any unnecessary toggling of the power wells.
4767          */
4768         for_each_intel_crtc(dev, crtc) {
4769                 enum intel_display_power_domain domain;
4770
4771                 if (!crtc->base.state->enable)
4772                         continue;
4773
4774                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4775
4776                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4777                         intel_display_power_get(dev_priv, domain);
4778         }
4779
4780         if (dev_priv->display.modeset_global_resources)
4781                 dev_priv->display.modeset_global_resources(dev);
4782
4783         for_each_intel_crtc(dev, crtc) {
4784                 enum intel_display_power_domain domain;
4785
4786                 for_each_power_domain(domain, crtc->enabled_power_domains)
4787                         intel_display_power_put(dev_priv, domain);
4788
4789                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4790         }
4791
4792         intel_display_set_init_power(dev_priv, false);
4793 }
4794
4795 /* returns HPLL frequency in kHz */
4796 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4797 {
4798         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4799
4800         /* Obtain SKU information */
4801         mutex_lock(&dev_priv->dpio_lock);
4802         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4803                 CCK_FUSE_HPLL_FREQ_MASK;
4804         mutex_unlock(&dev_priv->dpio_lock);
4805
4806         return vco_freq[hpll_freq] * 1000;
4807 }
4808
4809 static void vlv_update_cdclk(struct drm_device *dev)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812
4813         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4814         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4815                          dev_priv->vlv_cdclk_freq);
4816
4817         /*
4818          * Program the gmbus_freq based on the cdclk frequency.
4819          * BSpec erroneously claims we should aim for 4MHz, but
4820          * in fact 1MHz is the correct frequency.
4821          */
4822         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4823 }
4824
4825 /* Adjust CDclk dividers to allow high res or save power if possible */
4826 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4827 {
4828         struct drm_i915_private *dev_priv = dev->dev_private;
4829         u32 val, cmd;
4830
4831         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4832
4833         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4834                 cmd = 2;
4835         else if (cdclk == 266667)
4836                 cmd = 1;
4837         else
4838                 cmd = 0;
4839
4840         mutex_lock(&dev_priv->rps.hw_lock);
4841         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4842         val &= ~DSPFREQGUAR_MASK;
4843         val |= (cmd << DSPFREQGUAR_SHIFT);
4844         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4845         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4846                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4847                      50)) {
4848                 DRM_ERROR("timed out waiting for CDclk change\n");
4849         }
4850         mutex_unlock(&dev_priv->rps.hw_lock);
4851
4852         if (cdclk == 400000) {
4853                 u32 divider;
4854
4855                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4856
4857                 mutex_lock(&dev_priv->dpio_lock);
4858                 /* adjust cdclk divider */
4859                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4860                 val &= ~DISPLAY_FREQUENCY_VALUES;
4861                 val |= divider;
4862                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4863
4864                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4865                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4866                              50))
4867                         DRM_ERROR("timed out waiting for CDclk change\n");
4868                 mutex_unlock(&dev_priv->dpio_lock);
4869         }
4870
4871         mutex_lock(&dev_priv->dpio_lock);
4872         /* adjust self-refresh exit latency value */
4873         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4874         val &= ~0x7f;
4875
4876         /*
4877          * For high bandwidth configs, we set a higher latency in the bunit
4878          * so that the core display fetch happens in time to avoid underruns.
4879          */
4880         if (cdclk == 400000)
4881                 val |= 4500 / 250; /* 4.5 usec */
4882         else
4883                 val |= 3000 / 250; /* 3.0 usec */
4884         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4885         mutex_unlock(&dev_priv->dpio_lock);
4886
4887         vlv_update_cdclk(dev);
4888 }
4889
4890 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4891 {
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893         u32 val, cmd;
4894
4895         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4896
4897         switch (cdclk) {
4898         case 400000:
4899                 cmd = 3;
4900                 break;
4901         case 333333:
4902         case 320000:
4903                 cmd = 2;
4904                 break;
4905         case 266667:
4906                 cmd = 1;
4907                 break;
4908         case 200000:
4909                 cmd = 0;
4910                 break;
4911         default:
4912                 MISSING_CASE(cdclk);
4913                 return;
4914         }
4915
4916         mutex_lock(&dev_priv->rps.hw_lock);
4917         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4918         val &= ~DSPFREQGUAR_MASK_CHV;
4919         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4920         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4921         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4922                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4923                      50)) {
4924                 DRM_ERROR("timed out waiting for CDclk change\n");
4925         }
4926         mutex_unlock(&dev_priv->rps.hw_lock);
4927
4928         vlv_update_cdclk(dev);
4929 }
4930
4931 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4932                                  int max_pixclk)
4933 {
4934         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4935
4936         /* FIXME: Punit isn't quite ready yet */
4937         if (IS_CHERRYVIEW(dev_priv->dev))
4938                 return 400000;
4939
4940         /*
4941          * Really only a few cases to deal with, as only 4 CDclks are supported:
4942          *   200MHz
4943          *   267MHz
4944          *   320/333MHz (depends on HPLL freq)
4945          *   400MHz
4946          * So we check to see whether we're above 90% of the lower bin and
4947          * adjust if needed.
4948          *
4949          * We seem to get an unstable or solid color picture at 200MHz.
4950          * Not sure what's wrong. For now use 200MHz only when all pipes
4951          * are off.
4952          */
4953         if (max_pixclk > freq_320*9/10)
4954                 return 400000;
4955         else if (max_pixclk > 266667*9/10)
4956                 return freq_320;
4957         else if (max_pixclk > 0)
4958                 return 266667;
4959         else
4960                 return 200000;
4961 }
4962
4963 /* compute the max pixel clock for new configuration */
4964 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4965 {
4966         struct drm_device *dev = dev_priv->dev;
4967         struct intel_crtc *intel_crtc;
4968         int max_pixclk = 0;
4969
4970         for_each_intel_crtc(dev, intel_crtc) {
4971                 if (intel_crtc->new_enabled)
4972                         max_pixclk = max(max_pixclk,
4973                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4974         }
4975
4976         return max_pixclk;
4977 }
4978
4979 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4980                                             unsigned *prepare_pipes)
4981 {
4982         struct drm_i915_private *dev_priv = dev->dev_private;
4983         struct intel_crtc *intel_crtc;
4984         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4985
4986         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4987             dev_priv->vlv_cdclk_freq)
4988                 return;
4989
4990         /* disable/enable all currently active pipes while we change cdclk */
4991         for_each_intel_crtc(dev, intel_crtc)
4992                 if (intel_crtc->base.state->enable)
4993                         *prepare_pipes |= (1 << intel_crtc->pipe);
4994 }
4995
4996 static void valleyview_modeset_global_resources(struct drm_device *dev)
4997 {
4998         struct drm_i915_private *dev_priv = dev->dev_private;
4999         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5000         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5001
5002         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5003                 /*
5004                  * FIXME: We can end up here with all power domains off, yet
5005                  * with a CDCLK frequency other than the minimum. To account
5006                  * for this take the PIPE-A power domain, which covers the HW
5007                  * blocks needed for the following programming. This can be
5008                  * removed once it's guaranteed that we get here either with
5009                  * the minimum CDCLK set, or the required power domains
5010                  * enabled.
5011                  */
5012                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5013
5014                 if (IS_CHERRYVIEW(dev))
5015                         cherryview_set_cdclk(dev, req_cdclk);
5016                 else
5017                         valleyview_set_cdclk(dev, req_cdclk);
5018
5019                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5020         }
5021 }
5022
5023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = to_i915(dev);
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         struct intel_encoder *encoder;
5029         int pipe = intel_crtc->pipe;
5030         bool is_dsi;
5031
5032         WARN_ON(!crtc->state->enable);
5033
5034         if (intel_crtc->active)
5035                 return;
5036
5037         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5038
5039         if (!is_dsi) {
5040                 if (IS_CHERRYVIEW(dev))
5041                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5042                 else
5043                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5044         }
5045
5046         if (intel_crtc->config->has_dp_encoder)
5047                 intel_dp_set_m_n(intel_crtc, M1_N1);
5048
5049         intel_set_pipe_timings(intel_crtc);
5050
5051         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5052                 struct drm_i915_private *dev_priv = dev->dev_private;
5053
5054                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5055                 I915_WRITE(CHV_CANVAS(pipe), 0);
5056         }
5057
5058         i9xx_set_pipeconf(intel_crtc);
5059
5060         intel_crtc->active = true;
5061
5062         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5063
5064         for_each_encoder_on_crtc(dev, crtc, encoder)
5065                 if (encoder->pre_pll_enable)
5066                         encoder->pre_pll_enable(encoder);
5067
5068         if (!is_dsi) {
5069                 if (IS_CHERRYVIEW(dev))
5070                         chv_enable_pll(intel_crtc, intel_crtc->config);
5071                 else
5072                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5073         }
5074
5075         for_each_encoder_on_crtc(dev, crtc, encoder)
5076                 if (encoder->pre_enable)
5077                         encoder->pre_enable(encoder);
5078
5079         i9xx_pfit_enable(intel_crtc);
5080
5081         intel_crtc_load_lut(crtc);
5082
5083         intel_update_watermarks(crtc);
5084         intel_enable_pipe(intel_crtc);
5085
5086         assert_vblank_disabled(crtc);
5087         drm_crtc_vblank_on(crtc);
5088
5089         for_each_encoder_on_crtc(dev, crtc, encoder)
5090                 encoder->enable(encoder);
5091
5092         intel_crtc_enable_planes(crtc);
5093
5094         /* Underruns don't raise interrupts, so check manually. */
5095         i9xx_check_fifo_underruns(dev_priv);
5096 }
5097
5098 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5099 {
5100         struct drm_device *dev = crtc->base.dev;
5101         struct drm_i915_private *dev_priv = dev->dev_private;
5102
5103         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5104         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5105 }
5106
5107 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5108 {
5109         struct drm_device *dev = crtc->dev;
5110         struct drm_i915_private *dev_priv = to_i915(dev);
5111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112         struct intel_encoder *encoder;
5113         int pipe = intel_crtc->pipe;
5114
5115         WARN_ON(!crtc->state->enable);
5116
5117         if (intel_crtc->active)
5118                 return;
5119
5120         i9xx_set_pll_dividers(intel_crtc);
5121
5122         if (intel_crtc->config->has_dp_encoder)
5123                 intel_dp_set_m_n(intel_crtc, M1_N1);
5124
5125         intel_set_pipe_timings(intel_crtc);
5126
5127         i9xx_set_pipeconf(intel_crtc);
5128
5129         intel_crtc->active = true;
5130
5131         if (!IS_GEN2(dev))
5132                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5133
5134         for_each_encoder_on_crtc(dev, crtc, encoder)
5135                 if (encoder->pre_enable)
5136                         encoder->pre_enable(encoder);
5137
5138         i9xx_enable_pll(intel_crtc);
5139
5140         i9xx_pfit_enable(intel_crtc);
5141
5142         intel_crtc_load_lut(crtc);
5143
5144         intel_update_watermarks(crtc);
5145         intel_enable_pipe(intel_crtc);
5146
5147         assert_vblank_disabled(crtc);
5148         drm_crtc_vblank_on(crtc);
5149
5150         for_each_encoder_on_crtc(dev, crtc, encoder)
5151                 encoder->enable(encoder);
5152
5153         intel_crtc_enable_planes(crtc);
5154
5155         /*
5156          * Gen2 reports pipe underruns whenever all planes are disabled.
5157          * So don't enable underrun reporting before at least some planes
5158          * are enabled.
5159          * FIXME: Need to fix the logic to work when we turn off all planes
5160          * but leave the pipe running.
5161          */
5162         if (IS_GEN2(dev))
5163                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5164
5165         /* Underruns don't raise interrupts, so check manually. */
5166         i9xx_check_fifo_underruns(dev_priv);
5167 }
5168
5169 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5170 {
5171         struct drm_device *dev = crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173
5174         if (!crtc->config->gmch_pfit.control)
5175                 return;
5176
5177         assert_pipe_disabled(dev_priv, crtc->pipe);
5178
5179         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5180                          I915_READ(PFIT_CONTROL));
5181         I915_WRITE(PFIT_CONTROL, 0);
5182 }
5183
5184 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5185 {
5186         struct drm_device *dev = crtc->dev;
5187         struct drm_i915_private *dev_priv = dev->dev_private;
5188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189         struct intel_encoder *encoder;
5190         int pipe = intel_crtc->pipe;
5191
5192         if (!intel_crtc->active)
5193                 return;
5194
5195         /*
5196          * Gen2 reports pipe underruns whenever all planes are disabled.
5197          * So diasble underrun reporting before all the planes get disabled.
5198          * FIXME: Need to fix the logic to work when we turn off all planes
5199          * but leave the pipe running.
5200          */
5201         if (IS_GEN2(dev))
5202                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5203
5204         /*
5205          * Vblank time updates from the shadow to live plane control register
5206          * are blocked if the memory self-refresh mode is active at that
5207          * moment. So to make sure the plane gets truly disabled, disable
5208          * first the self-refresh mode. The self-refresh enable bit in turn
5209          * will be checked/applied by the HW only at the next frame start
5210          * event which is after the vblank start event, so we need to have a
5211          * wait-for-vblank between disabling the plane and the pipe.
5212          */
5213         intel_set_memory_cxsr(dev_priv, false);
5214         intel_crtc_disable_planes(crtc);
5215
5216         /*
5217          * On gen2 planes are double buffered but the pipe isn't, so we must
5218          * wait for planes to fully turn off before disabling the pipe.
5219          * We also need to wait on all gmch platforms because of the
5220          * self-refresh mode constraint explained above.
5221          */
5222         intel_wait_for_vblank(dev, pipe);
5223
5224         for_each_encoder_on_crtc(dev, crtc, encoder)
5225                 encoder->disable(encoder);
5226
5227         drm_crtc_vblank_off(crtc);
5228         assert_vblank_disabled(crtc);
5229
5230         intel_disable_pipe(intel_crtc);
5231
5232         i9xx_pfit_disable(intel_crtc);
5233
5234         for_each_encoder_on_crtc(dev, crtc, encoder)
5235                 if (encoder->post_disable)
5236                         encoder->post_disable(encoder);
5237
5238         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5239                 if (IS_CHERRYVIEW(dev))
5240                         chv_disable_pll(dev_priv, pipe);
5241                 else if (IS_VALLEYVIEW(dev))
5242                         vlv_disable_pll(dev_priv, pipe);
5243                 else
5244                         i9xx_disable_pll(intel_crtc);
5245         }
5246
5247         if (!IS_GEN2(dev))
5248                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5249
5250         intel_crtc->active = false;
5251         intel_update_watermarks(crtc);
5252
5253         mutex_lock(&dev->struct_mutex);
5254         intel_fbc_update(dev);
5255         mutex_unlock(&dev->struct_mutex);
5256 }
5257
5258 static void i9xx_crtc_off(struct drm_crtc *crtc)
5259 {
5260 }
5261
5262 /* Master function to enable/disable CRTC and corresponding power wells */
5263 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5264 {
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268         enum intel_display_power_domain domain;
5269         unsigned long domains;
5270
5271         if (enable) {
5272                 if (!intel_crtc->active) {
5273                         domains = get_crtc_power_domains(crtc);
5274                         for_each_power_domain(domain, domains)
5275                                 intel_display_power_get(dev_priv, domain);
5276                         intel_crtc->enabled_power_domains = domains;
5277
5278                         dev_priv->display.crtc_enable(crtc);
5279                 }
5280         } else {
5281                 if (intel_crtc->active) {
5282                         dev_priv->display.crtc_disable(crtc);
5283
5284                         domains = intel_crtc->enabled_power_domains;
5285                         for_each_power_domain(domain, domains)
5286                                 intel_display_power_put(dev_priv, domain);
5287                         intel_crtc->enabled_power_domains = 0;
5288                 }
5289         }
5290 }
5291
5292 /**
5293  * Sets the power management mode of the pipe and plane.
5294  */
5295 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5296 {
5297         struct drm_device *dev = crtc->dev;
5298         struct intel_encoder *intel_encoder;
5299         bool enable = false;
5300
5301         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5302                 enable |= intel_encoder->connectors_active;
5303
5304         intel_crtc_control(crtc, enable);
5305 }
5306
5307 static void intel_crtc_disable(struct drm_crtc *crtc)
5308 {
5309         struct drm_device *dev = crtc->dev;
5310         struct drm_connector *connector;
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313         /* crtc should still be enabled when we disable it. */
5314         WARN_ON(!crtc->state->enable);
5315
5316         dev_priv->display.crtc_disable(crtc);
5317         dev_priv->display.off(crtc);
5318
5319         crtc->primary->funcs->disable_plane(crtc->primary);
5320
5321         /* Update computed state. */
5322         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5323                 if (!connector->encoder || !connector->encoder->crtc)
5324                         continue;
5325
5326                 if (connector->encoder->crtc != crtc)
5327                         continue;
5328
5329                 connector->dpms = DRM_MODE_DPMS_OFF;
5330                 to_intel_encoder(connector->encoder)->connectors_active = false;
5331         }
5332 }
5333
5334 void intel_encoder_destroy(struct drm_encoder *encoder)
5335 {
5336         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5337
5338         drm_encoder_cleanup(encoder);
5339         kfree(intel_encoder);
5340 }
5341
5342 /* Simple dpms helper for encoders with just one connector, no cloning and only
5343  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5344  * state of the entire output pipe. */
5345 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5346 {
5347         if (mode == DRM_MODE_DPMS_ON) {
5348                 encoder->connectors_active = true;
5349
5350                 intel_crtc_update_dpms(encoder->base.crtc);
5351         } else {
5352                 encoder->connectors_active = false;
5353
5354                 intel_crtc_update_dpms(encoder->base.crtc);
5355         }
5356 }
5357
5358 /* Cross check the actual hw state with our own modeset state tracking (and it's
5359  * internal consistency). */
5360 static void intel_connector_check_state(struct intel_connector *connector)
5361 {
5362         if (connector->get_hw_state(connector)) {
5363                 struct intel_encoder *encoder = connector->encoder;
5364                 struct drm_crtc *crtc;
5365                 bool encoder_enabled;
5366                 enum pipe pipe;
5367
5368                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5369                               connector->base.base.id,
5370                               connector->base.name);
5371
5372                 /* there is no real hw state for MST connectors */
5373                 if (connector->mst_port)
5374                         return;
5375
5376                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5377                      "wrong connector dpms state\n");
5378                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5379                      "active connector not linked to encoder\n");
5380
5381                 if (encoder) {
5382                         I915_STATE_WARN(!encoder->connectors_active,
5383                              "encoder->connectors_active not set\n");
5384
5385                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5386                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5387                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5388                                 return;
5389
5390                         crtc = encoder->base.crtc;
5391
5392                         I915_STATE_WARN(!crtc->state->enable,
5393                                         "crtc not enabled\n");
5394                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5395                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5396                              "encoder active on the wrong pipe\n");
5397                 }
5398         }
5399 }
5400
5401 /* Even simpler default implementation, if there's really no special case to
5402  * consider. */
5403 void intel_connector_dpms(struct drm_connector *connector, int mode)
5404 {
5405         /* All the simple cases only support two dpms states. */
5406         if (mode != DRM_MODE_DPMS_ON)
5407                 mode = DRM_MODE_DPMS_OFF;
5408
5409         if (mode == connector->dpms)
5410                 return;
5411
5412         connector->dpms = mode;
5413
5414         /* Only need to change hw state when actually enabled */
5415         if (connector->encoder)
5416                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5417
5418         intel_modeset_check_state(connector->dev);
5419 }
5420
5421 /* Simple connector->get_hw_state implementation for encoders that support only
5422  * one connector and no cloning and hence the encoder state determines the state
5423  * of the connector. */
5424 bool intel_connector_get_hw_state(struct intel_connector *connector)
5425 {
5426         enum pipe pipe = 0;
5427         struct intel_encoder *encoder = connector->encoder;
5428
5429         return encoder->get_hw_state(encoder, &pipe);
5430 }
5431
5432 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5433                                      struct intel_crtc_state *pipe_config)
5434 {
5435         struct drm_i915_private *dev_priv = dev->dev_private;
5436         struct intel_crtc *pipe_B_crtc =
5437                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5438
5439         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5440                       pipe_name(pipe), pipe_config->fdi_lanes);
5441         if (pipe_config->fdi_lanes > 4) {
5442                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5443                               pipe_name(pipe), pipe_config->fdi_lanes);
5444                 return false;
5445         }
5446
5447         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5448                 if (pipe_config->fdi_lanes > 2) {
5449                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5450                                       pipe_config->fdi_lanes);
5451                         return false;
5452                 } else {
5453                         return true;
5454                 }
5455         }
5456
5457         if (INTEL_INFO(dev)->num_pipes == 2)
5458                 return true;
5459
5460         /* Ivybridge 3 pipe is really complicated */
5461         switch (pipe) {
5462         case PIPE_A:
5463                 return true;
5464         case PIPE_B:
5465                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5466                     pipe_config->fdi_lanes > 2) {
5467                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5468                                       pipe_name(pipe), pipe_config->fdi_lanes);
5469                         return false;
5470                 }
5471                 return true;
5472         case PIPE_C:
5473                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5474                     pipe_B_crtc->config->fdi_lanes <= 2) {
5475                         if (pipe_config->fdi_lanes > 2) {
5476                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5477                                               pipe_name(pipe), pipe_config->fdi_lanes);
5478                                 return false;
5479                         }
5480                 } else {
5481                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5482                         return false;
5483                 }
5484                 return true;
5485         default:
5486                 BUG();
5487         }
5488 }
5489
5490 #define RETRY 1
5491 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5492                                        struct intel_crtc_state *pipe_config)
5493 {
5494         struct drm_device *dev = intel_crtc->base.dev;
5495         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5496         int lane, link_bw, fdi_dotclock;
5497         bool setup_ok, needs_recompute = false;
5498
5499 retry:
5500         /* FDI is a binary signal running at ~2.7GHz, encoding
5501          * each output octet as 10 bits. The actual frequency
5502          * is stored as a divider into a 100MHz clock, and the
5503          * mode pixel clock is stored in units of 1KHz.
5504          * Hence the bw of each lane in terms of the mode signal
5505          * is:
5506          */
5507         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5508
5509         fdi_dotclock = adjusted_mode->crtc_clock;
5510
5511         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5512                                            pipe_config->pipe_bpp);
5513
5514         pipe_config->fdi_lanes = lane;
5515
5516         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5517                                link_bw, &pipe_config->fdi_m_n);
5518
5519         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5520                                             intel_crtc->pipe, pipe_config);
5521         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5522                 pipe_config->pipe_bpp -= 2*3;
5523                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5524                               pipe_config->pipe_bpp);
5525                 needs_recompute = true;
5526                 pipe_config->bw_constrained = true;
5527
5528                 goto retry;
5529         }
5530
5531         if (needs_recompute)
5532                 return RETRY;
5533
5534         return setup_ok ? 0 : -EINVAL;
5535 }
5536
5537 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5538                                    struct intel_crtc_state *pipe_config)
5539 {
5540         pipe_config->ips_enabled = i915.enable_ips &&
5541                                    hsw_crtc_supports_ips(crtc) &&
5542                                    pipe_config->pipe_bpp <= 24;
5543 }
5544
5545 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5546                                      struct intel_crtc_state *pipe_config)
5547 {
5548         struct drm_device *dev = crtc->base.dev;
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5551
5552         /* FIXME should check pixel clock limits on all platforms */
5553         if (INTEL_INFO(dev)->gen < 4) {
5554                 int clock_limit =
5555                         dev_priv->display.get_display_clock_speed(dev);
5556
5557                 /*
5558                  * Enable pixel doubling when the dot clock
5559                  * is > 90% of the (display) core speed.
5560                  *
5561                  * GDG double wide on either pipe,
5562                  * otherwise pipe A only.
5563                  */
5564                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5565                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5566                         clock_limit *= 2;
5567                         pipe_config->double_wide = true;
5568                 }
5569
5570                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5571                         return -EINVAL;
5572         }
5573
5574         /*
5575          * Pipe horizontal size must be even in:
5576          * - DVO ganged mode
5577          * - LVDS dual channel mode
5578          * - Double wide pipe
5579          */
5580         if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5581              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5582                 pipe_config->pipe_src_w &= ~1;
5583
5584         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5585          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5586          */
5587         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5588                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5589                 return -EINVAL;
5590
5591         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5592                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5593         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5594                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5595                  * for lvds. */
5596                 pipe_config->pipe_bpp = 8*3;
5597         }
5598
5599         if (HAS_IPS(dev))
5600                 hsw_compute_ips_config(crtc, pipe_config);
5601
5602         if (pipe_config->has_pch_encoder)
5603                 return ironlake_fdi_compute_config(crtc, pipe_config);
5604
5605         return 0;
5606 }
5607
5608 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5609 {
5610         struct drm_i915_private *dev_priv = dev->dev_private;
5611         u32 val;
5612         int divider;
5613
5614         /* FIXME: Punit isn't quite ready yet */
5615         if (IS_CHERRYVIEW(dev))
5616                 return 400000;
5617
5618         if (dev_priv->hpll_freq == 0)
5619                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5620
5621         mutex_lock(&dev_priv->dpio_lock);
5622         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5623         mutex_unlock(&dev_priv->dpio_lock);
5624
5625         divider = val & DISPLAY_FREQUENCY_VALUES;
5626
5627         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5628              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5629              "cdclk change in progress\n");
5630
5631         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5632 }
5633
5634 static int i945_get_display_clock_speed(struct drm_device *dev)
5635 {
5636         return 400000;
5637 }
5638
5639 static int i915_get_display_clock_speed(struct drm_device *dev)
5640 {
5641         return 333000;
5642 }
5643
5644 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5645 {
5646         return 200000;
5647 }
5648
5649 static int pnv_get_display_clock_speed(struct drm_device *dev)
5650 {
5651         u16 gcfgc = 0;
5652
5653         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5654
5655         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5656         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5657                 return 267000;
5658         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5659                 return 333000;
5660         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5661                 return 444000;
5662         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5663                 return 200000;
5664         default:
5665                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5666         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5667                 return 133000;
5668         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5669                 return 167000;
5670         }
5671 }
5672
5673 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5674 {
5675         u16 gcfgc = 0;
5676
5677         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5678
5679         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5680                 return 133000;
5681         else {
5682                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5683                 case GC_DISPLAY_CLOCK_333_MHZ:
5684                         return 333000;
5685                 default:
5686                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5687                         return 190000;
5688                 }
5689         }
5690 }
5691
5692 static int i865_get_display_clock_speed(struct drm_device *dev)
5693 {
5694         return 266000;
5695 }
5696
5697 static int i855_get_display_clock_speed(struct drm_device *dev)
5698 {
5699         u16 hpllcc = 0;
5700         /* Assume that the hardware is in the high speed state.  This
5701          * should be the default.
5702          */
5703         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5704         case GC_CLOCK_133_200:
5705         case GC_CLOCK_100_200:
5706                 return 200000;
5707         case GC_CLOCK_166_250:
5708                 return 250000;
5709         case GC_CLOCK_100_133:
5710                 return 133000;
5711         }
5712
5713         /* Shouldn't happen */
5714         return 0;
5715 }
5716
5717 static int i830_get_display_clock_speed(struct drm_device *dev)
5718 {
5719         return 133000;
5720 }
5721
5722 static void
5723 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5724 {
5725         while (*num > DATA_LINK_M_N_MASK ||
5726                *den > DATA_LINK_M_N_MASK) {
5727                 *num >>= 1;
5728                 *den >>= 1;
5729         }
5730 }
5731
5732 static void compute_m_n(unsigned int m, unsigned int n,
5733                         uint32_t *ret_m, uint32_t *ret_n)
5734 {
5735         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5736         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5737         intel_reduce_m_n_ratio(ret_m, ret_n);
5738 }
5739
5740 void
5741 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5742                        int pixel_clock, int link_clock,
5743                        struct intel_link_m_n *m_n)
5744 {
5745         m_n->tu = 64;
5746
5747         compute_m_n(bits_per_pixel * pixel_clock,
5748                     link_clock * nlanes * 8,
5749                     &m_n->gmch_m, &m_n->gmch_n);
5750
5751         compute_m_n(pixel_clock, link_clock,
5752                     &m_n->link_m, &m_n->link_n);
5753 }
5754
5755 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5756 {
5757         if (i915.panel_use_ssc >= 0)
5758                 return i915.panel_use_ssc != 0;
5759         return dev_priv->vbt.lvds_use_ssc
5760                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5761 }
5762
5763 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5764 {
5765         struct drm_device *dev = crtc->base.dev;
5766         struct drm_i915_private *dev_priv = dev->dev_private;
5767         int refclk;
5768
5769         if (IS_VALLEYVIEW(dev)) {
5770                 refclk = 100000;
5771         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5772             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5773                 refclk = dev_priv->vbt.lvds_ssc_freq;
5774                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5775         } else if (!IS_GEN2(dev)) {
5776                 refclk = 96000;
5777         } else {
5778                 refclk = 48000;
5779         }
5780
5781         return refclk;
5782 }
5783
5784 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5785 {
5786         return (1 << dpll->n) << 16 | dpll->m2;
5787 }
5788
5789 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5790 {
5791         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5792 }
5793
5794 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5795                                      struct intel_crtc_state *crtc_state,
5796                                      intel_clock_t *reduced_clock)
5797 {
5798         struct drm_device *dev = crtc->base.dev;
5799         u32 fp, fp2 = 0;
5800
5801         if (IS_PINEVIEW(dev)) {
5802                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5803                 if (reduced_clock)
5804                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5805         } else {
5806                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5807                 if (reduced_clock)
5808                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5809         }
5810
5811         crtc_state->dpll_hw_state.fp0 = fp;
5812
5813         crtc->lowfreq_avail = false;
5814         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5815             reduced_clock && i915.powersave) {
5816                 crtc_state->dpll_hw_state.fp1 = fp2;
5817                 crtc->lowfreq_avail = true;
5818         } else {
5819                 crtc_state->dpll_hw_state.fp1 = fp;
5820         }
5821 }
5822
5823 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5824                 pipe)
5825 {
5826         u32 reg_val;
5827
5828         /*
5829          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5830          * and set it to a reasonable value instead.
5831          */
5832         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5833         reg_val &= 0xffffff00;
5834         reg_val |= 0x00000030;
5835         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5836
5837         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5838         reg_val &= 0x8cffffff;
5839         reg_val = 0x8c000000;
5840         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5841
5842         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5843         reg_val &= 0xffffff00;
5844         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5845
5846         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5847         reg_val &= 0x00ffffff;
5848         reg_val |= 0xb0000000;
5849         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5850 }
5851
5852 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5853                                          struct intel_link_m_n *m_n)
5854 {
5855         struct drm_device *dev = crtc->base.dev;
5856         struct drm_i915_private *dev_priv = dev->dev_private;
5857         int pipe = crtc->pipe;
5858
5859         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5860         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5861         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5862         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5863 }
5864
5865 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5866                                          struct intel_link_m_n *m_n,
5867                                          struct intel_link_m_n *m2_n2)
5868 {
5869         struct drm_device *dev = crtc->base.dev;
5870         struct drm_i915_private *dev_priv = dev->dev_private;
5871         int pipe = crtc->pipe;
5872         enum transcoder transcoder = crtc->config->cpu_transcoder;
5873
5874         if (INTEL_INFO(dev)->gen >= 5) {
5875                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5876                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5877                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5878                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5879                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5880                  * for gen < 8) and if DRRS is supported (to make sure the
5881                  * registers are not unnecessarily accessed).
5882                  */
5883                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5884                         crtc->config->has_drrs) {
5885                         I915_WRITE(PIPE_DATA_M2(transcoder),
5886                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5887                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5888                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5889                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5890                 }
5891         } else {
5892                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5893                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5894                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5895                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5896         }
5897 }
5898
5899 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
5900 {
5901         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
5902
5903         if (m_n == M1_N1) {
5904                 dp_m_n = &crtc->config->dp_m_n;
5905                 dp_m2_n2 = &crtc->config->dp_m2_n2;
5906         } else if (m_n == M2_N2) {
5907
5908                 /*
5909                  * M2_N2 registers are not supported. Hence m2_n2 divider value
5910                  * needs to be programmed into M1_N1.
5911                  */
5912                 dp_m_n = &crtc->config->dp_m2_n2;
5913         } else {
5914                 DRM_ERROR("Unsupported divider value\n");
5915                 return;
5916         }
5917
5918         if (crtc->config->has_pch_encoder)
5919                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5920         else
5921                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
5922 }
5923
5924 static void vlv_update_pll(struct intel_crtc *crtc,
5925                            struct intel_crtc_state *pipe_config)
5926 {
5927         u32 dpll, dpll_md;
5928
5929         /*
5930          * Enable DPIO clock input. We should never disable the reference
5931          * clock for pipe B, since VGA hotplug / manual detection depends
5932          * on it.
5933          */
5934         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5935                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5936         /* We should never disable this, set it here for state tracking */
5937         if (crtc->pipe == PIPE_B)
5938                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5939         dpll |= DPLL_VCO_ENABLE;
5940         pipe_config->dpll_hw_state.dpll = dpll;
5941
5942         dpll_md = (pipe_config->pixel_multiplier - 1)
5943                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5944         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5945 }
5946
5947 static void vlv_prepare_pll(struct intel_crtc *crtc,
5948                             const struct intel_crtc_state *pipe_config)
5949 {
5950         struct drm_device *dev = crtc->base.dev;
5951         struct drm_i915_private *dev_priv = dev->dev_private;
5952         int pipe = crtc->pipe;
5953         u32 mdiv;
5954         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5955         u32 coreclk, reg_val;
5956
5957         mutex_lock(&dev_priv->dpio_lock);
5958
5959         bestn = pipe_config->dpll.n;
5960         bestm1 = pipe_config->dpll.m1;
5961         bestm2 = pipe_config->dpll.m2;
5962         bestp1 = pipe_config->dpll.p1;
5963         bestp2 = pipe_config->dpll.p2;
5964
5965         /* See eDP HDMI DPIO driver vbios notes doc */
5966
5967         /* PLL B needs special handling */
5968         if (pipe == PIPE_B)
5969                 vlv_pllb_recal_opamp(dev_priv, pipe);
5970
5971         /* Set up Tx target for periodic Rcomp update */
5972         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5973
5974         /* Disable target IRef on PLL */
5975         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5976         reg_val &= 0x00ffffff;
5977         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5978
5979         /* Disable fast lock */
5980         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5981
5982         /* Set idtafcrecal before PLL is enabled */
5983         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5984         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5985         mdiv |= ((bestn << DPIO_N_SHIFT));
5986         mdiv |= (1 << DPIO_K_SHIFT);
5987
5988         /*
5989          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5990          * but we don't support that).
5991          * Note: don't use the DAC post divider as it seems unstable.
5992          */
5993         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5994         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5995
5996         mdiv |= DPIO_ENABLE_CALIBRATION;
5997         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5998
5999         /* Set HBR and RBR LPF coefficients */
6000         if (pipe_config->port_clock == 162000 ||
6001             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6002             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6003                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6004                                  0x009f0003);
6005         else
6006                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6007                                  0x00d0000f);
6008
6009         if (pipe_config->has_dp_encoder) {
6010                 /* Use SSC source */
6011                 if (pipe == PIPE_A)
6012                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6013                                          0x0df40000);
6014                 else
6015                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6016                                          0x0df70000);
6017         } else { /* HDMI or VGA */
6018                 /* Use bend source */
6019                 if (pipe == PIPE_A)
6020                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6021                                          0x0df70000);
6022                 else
6023                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6024                                          0x0df40000);
6025         }
6026
6027         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6028         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6029         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6030             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6031                 coreclk |= 0x01000000;
6032         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6033
6034         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6035         mutex_unlock(&dev_priv->dpio_lock);
6036 }
6037
6038 static void chv_update_pll(struct intel_crtc *crtc,
6039                            struct intel_crtc_state *pipe_config)
6040 {
6041         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6042                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6043                 DPLL_VCO_ENABLE;
6044         if (crtc->pipe != PIPE_A)
6045                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6046
6047         pipe_config->dpll_hw_state.dpll_md =
6048                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6049 }
6050
6051 static void chv_prepare_pll(struct intel_crtc *crtc,
6052                             const struct intel_crtc_state *pipe_config)
6053 {
6054         struct drm_device *dev = crtc->base.dev;
6055         struct drm_i915_private *dev_priv = dev->dev_private;
6056         int pipe = crtc->pipe;
6057         int dpll_reg = DPLL(crtc->pipe);
6058         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6059         u32 loopfilter, intcoeff;
6060         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6061         int refclk;
6062
6063         bestn = pipe_config->dpll.n;
6064         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6065         bestm1 = pipe_config->dpll.m1;
6066         bestm2 = pipe_config->dpll.m2 >> 22;
6067         bestp1 = pipe_config->dpll.p1;
6068         bestp2 = pipe_config->dpll.p2;
6069
6070         /*
6071          * Enable Refclk and SSC
6072          */
6073         I915_WRITE(dpll_reg,
6074                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6075
6076         mutex_lock(&dev_priv->dpio_lock);
6077
6078         /* p1 and p2 divider */
6079         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6080                         5 << DPIO_CHV_S1_DIV_SHIFT |
6081                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6082                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6083                         1 << DPIO_CHV_K_DIV_SHIFT);
6084
6085         /* Feedback post-divider - m2 */
6086         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6087
6088         /* Feedback refclk divider - n and m1 */
6089         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6090                         DPIO_CHV_M1_DIV_BY_2 |
6091                         1 << DPIO_CHV_N_DIV_SHIFT);
6092
6093         /* M2 fraction division */
6094         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6095
6096         /* M2 fraction division enable */
6097         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6098                        DPIO_CHV_FRAC_DIV_EN |
6099                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6100
6101         /* Loop filter */
6102         refclk = i9xx_get_refclk(crtc, 0);
6103         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6104                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6105         if (refclk == 100000)
6106                 intcoeff = 11;
6107         else if (refclk == 38400)
6108                 intcoeff = 10;
6109         else
6110                 intcoeff = 9;
6111         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6112         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6113
6114         /* AFC Recal */
6115         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6116                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6117                         DPIO_AFC_RECAL);
6118
6119         mutex_unlock(&dev_priv->dpio_lock);
6120 }
6121
6122 /**
6123  * vlv_force_pll_on - forcibly enable just the PLL
6124  * @dev_priv: i915 private structure
6125  * @pipe: pipe PLL to enable
6126  * @dpll: PLL configuration
6127  *
6128  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6129  * in cases where we need the PLL enabled even when @pipe is not going to
6130  * be enabled.
6131  */
6132 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6133                       const struct dpll *dpll)
6134 {
6135         struct intel_crtc *crtc =
6136                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6137         struct intel_crtc_state pipe_config = {
6138                 .pixel_multiplier = 1,
6139                 .dpll = *dpll,
6140         };
6141
6142         if (IS_CHERRYVIEW(dev)) {
6143                 chv_update_pll(crtc, &pipe_config);
6144                 chv_prepare_pll(crtc, &pipe_config);
6145                 chv_enable_pll(crtc, &pipe_config);
6146         } else {
6147                 vlv_update_pll(crtc, &pipe_config);
6148                 vlv_prepare_pll(crtc, &pipe_config);
6149                 vlv_enable_pll(crtc, &pipe_config);
6150         }
6151 }
6152
6153 /**
6154  * vlv_force_pll_off - forcibly disable just the PLL
6155  * @dev_priv: i915 private structure
6156  * @pipe: pipe PLL to disable
6157  *
6158  * Disable the PLL for @pipe. To be used in cases where we need
6159  * the PLL enabled even when @pipe is not going to be enabled.
6160  */
6161 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6162 {
6163         if (IS_CHERRYVIEW(dev))
6164                 chv_disable_pll(to_i915(dev), pipe);
6165         else
6166                 vlv_disable_pll(to_i915(dev), pipe);
6167 }
6168
6169 static void i9xx_update_pll(struct intel_crtc *crtc,
6170                             struct intel_crtc_state *crtc_state,
6171                             intel_clock_t *reduced_clock,
6172                             int num_connectors)
6173 {
6174         struct drm_device *dev = crtc->base.dev;
6175         struct drm_i915_private *dev_priv = dev->dev_private;
6176         u32 dpll;
6177         bool is_sdvo;
6178         struct dpll *clock = &crtc_state->dpll;
6179
6180         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6181
6182         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6183                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6184
6185         dpll = DPLL_VGA_MODE_DIS;
6186
6187         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6188                 dpll |= DPLLB_MODE_LVDS;
6189         else
6190                 dpll |= DPLLB_MODE_DAC_SERIAL;
6191
6192         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6193                 dpll |= (crtc_state->pixel_multiplier - 1)
6194                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6195         }
6196
6197         if (is_sdvo)
6198                 dpll |= DPLL_SDVO_HIGH_SPEED;
6199
6200         if (crtc_state->has_dp_encoder)
6201                 dpll |= DPLL_SDVO_HIGH_SPEED;
6202
6203         /* compute bitmask from p1 value */
6204         if (IS_PINEVIEW(dev))
6205                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6206         else {
6207                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6208                 if (IS_G4X(dev) && reduced_clock)
6209                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6210         }
6211         switch (clock->p2) {
6212         case 5:
6213                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6214                 break;
6215         case 7:
6216                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6217                 break;
6218         case 10:
6219                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6220                 break;
6221         case 14:
6222                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6223                 break;
6224         }
6225         if (INTEL_INFO(dev)->gen >= 4)
6226                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6227
6228         if (crtc_state->sdvo_tv_clock)
6229                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6230         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6231                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6232                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6233         else
6234                 dpll |= PLL_REF_INPUT_DREFCLK;
6235
6236         dpll |= DPLL_VCO_ENABLE;
6237         crtc_state->dpll_hw_state.dpll = dpll;
6238
6239         if (INTEL_INFO(dev)->gen >= 4) {
6240                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6241                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6242                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6243         }
6244 }
6245
6246 static void i8xx_update_pll(struct intel_crtc *crtc,
6247                             struct intel_crtc_state *crtc_state,
6248                             intel_clock_t *reduced_clock,
6249                             int num_connectors)
6250 {
6251         struct drm_device *dev = crtc->base.dev;
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         u32 dpll;
6254         struct dpll *clock = &crtc_state->dpll;
6255
6256         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6257
6258         dpll = DPLL_VGA_MODE_DIS;
6259
6260         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6261                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6262         } else {
6263                 if (clock->p1 == 2)
6264                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6265                 else
6266                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6267                 if (clock->p2 == 4)
6268                         dpll |= PLL_P2_DIVIDE_BY_4;
6269         }
6270
6271         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6272                 dpll |= DPLL_DVO_2X_MODE;
6273
6274         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6275                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6276                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6277         else
6278                 dpll |= PLL_REF_INPUT_DREFCLK;
6279
6280         dpll |= DPLL_VCO_ENABLE;
6281         crtc_state->dpll_hw_state.dpll = dpll;
6282 }
6283
6284 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6285 {
6286         struct drm_device *dev = intel_crtc->base.dev;
6287         struct drm_i915_private *dev_priv = dev->dev_private;
6288         enum pipe pipe = intel_crtc->pipe;
6289         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6290         struct drm_display_mode *adjusted_mode =
6291                 &intel_crtc->config->base.adjusted_mode;
6292         uint32_t crtc_vtotal, crtc_vblank_end;
6293         int vsyncshift = 0;
6294
6295         /* We need to be careful not to changed the adjusted mode, for otherwise
6296          * the hw state checker will get angry at the mismatch. */
6297         crtc_vtotal = adjusted_mode->crtc_vtotal;
6298         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6299
6300         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6301                 /* the chip adds 2 halflines automatically */
6302                 crtc_vtotal -= 1;
6303                 crtc_vblank_end -= 1;
6304
6305                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6306                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6307                 else
6308                         vsyncshift = adjusted_mode->crtc_hsync_start -
6309                                 adjusted_mode->crtc_htotal / 2;
6310                 if (vsyncshift < 0)
6311                         vsyncshift += adjusted_mode->crtc_htotal;
6312         }
6313
6314         if (INTEL_INFO(dev)->gen > 3)
6315                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6316
6317         I915_WRITE(HTOTAL(cpu_transcoder),
6318                    (adjusted_mode->crtc_hdisplay - 1) |
6319                    ((adjusted_mode->crtc_htotal - 1) << 16));
6320         I915_WRITE(HBLANK(cpu_transcoder),
6321                    (adjusted_mode->crtc_hblank_start - 1) |
6322                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6323         I915_WRITE(HSYNC(cpu_transcoder),
6324                    (adjusted_mode->crtc_hsync_start - 1) |
6325                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6326
6327         I915_WRITE(VTOTAL(cpu_transcoder),
6328                    (adjusted_mode->crtc_vdisplay - 1) |
6329                    ((crtc_vtotal - 1) << 16));
6330         I915_WRITE(VBLANK(cpu_transcoder),
6331                    (adjusted_mode->crtc_vblank_start - 1) |
6332                    ((crtc_vblank_end - 1) << 16));
6333         I915_WRITE(VSYNC(cpu_transcoder),
6334                    (adjusted_mode->crtc_vsync_start - 1) |
6335                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6336
6337         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6338          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6339          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6340          * bits. */
6341         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6342             (pipe == PIPE_B || pipe == PIPE_C))
6343                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6344
6345         /* pipesrc controls the size that is scaled from, which should
6346          * always be the user's requested size.
6347          */
6348         I915_WRITE(PIPESRC(pipe),
6349                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6350                    (intel_crtc->config->pipe_src_h - 1));
6351 }
6352
6353 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6354                                    struct intel_crtc_state *pipe_config)
6355 {
6356         struct drm_device *dev = crtc->base.dev;
6357         struct drm_i915_private *dev_priv = dev->dev_private;
6358         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6359         uint32_t tmp;
6360
6361         tmp = I915_READ(HTOTAL(cpu_transcoder));
6362         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6363         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6364         tmp = I915_READ(HBLANK(cpu_transcoder));
6365         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6366         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6367         tmp = I915_READ(HSYNC(cpu_transcoder));
6368         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6369         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6370
6371         tmp = I915_READ(VTOTAL(cpu_transcoder));
6372         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6373         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6374         tmp = I915_READ(VBLANK(cpu_transcoder));
6375         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6376         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6377         tmp = I915_READ(VSYNC(cpu_transcoder));
6378         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6379         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6380
6381         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6382                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6383                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6384                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6385         }
6386
6387         tmp = I915_READ(PIPESRC(crtc->pipe));
6388         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6389         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6390
6391         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6392         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6393 }
6394
6395 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6396                                  struct intel_crtc_state *pipe_config)
6397 {
6398         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6399         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6400         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6401         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6402
6403         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6404         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6405         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6406         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6407
6408         mode->flags = pipe_config->base.adjusted_mode.flags;
6409
6410         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6411         mode->flags |= pipe_config->base.adjusted_mode.flags;
6412 }
6413
6414 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6415 {
6416         struct drm_device *dev = intel_crtc->base.dev;
6417         struct drm_i915_private *dev_priv = dev->dev_private;
6418         uint32_t pipeconf;
6419
6420         pipeconf = 0;
6421
6422         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6423             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6424                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6425
6426         if (intel_crtc->config->double_wide)
6427                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6428
6429         /* only g4x and later have fancy bpc/dither controls */
6430         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6431                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6432                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6433                         pipeconf |= PIPECONF_DITHER_EN |
6434                                     PIPECONF_DITHER_TYPE_SP;
6435
6436                 switch (intel_crtc->config->pipe_bpp) {
6437                 case 18:
6438                         pipeconf |= PIPECONF_6BPC;
6439                         break;
6440                 case 24:
6441                         pipeconf |= PIPECONF_8BPC;
6442                         break;
6443                 case 30:
6444                         pipeconf |= PIPECONF_10BPC;
6445                         break;
6446                 default:
6447                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6448                         BUG();
6449                 }
6450         }
6451
6452         if (HAS_PIPE_CXSR(dev)) {
6453                 if (intel_crtc->lowfreq_avail) {
6454                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6455                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6456                 } else {
6457                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6458                 }
6459         }
6460
6461         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6462                 if (INTEL_INFO(dev)->gen < 4 ||
6463                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6464                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6465                 else
6466                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6467         } else
6468                 pipeconf |= PIPECONF_PROGRESSIVE;
6469
6470         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6471                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6472
6473         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6474         POSTING_READ(PIPECONF(intel_crtc->pipe));
6475 }
6476
6477 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6478                                    struct intel_crtc_state *crtc_state)
6479 {
6480         struct drm_device *dev = crtc->base.dev;
6481         struct drm_i915_private *dev_priv = dev->dev_private;
6482         int refclk, num_connectors = 0;
6483         intel_clock_t clock, reduced_clock;
6484         bool ok, has_reduced_clock = false;
6485         bool is_lvds = false, is_dsi = false;
6486         struct intel_encoder *encoder;
6487         const intel_limit_t *limit;
6488
6489         for_each_intel_encoder(dev, encoder) {
6490                 if (encoder->new_crtc != crtc)
6491                         continue;
6492
6493                 switch (encoder->type) {
6494                 case INTEL_OUTPUT_LVDS:
6495                         is_lvds = true;
6496                         break;
6497                 case INTEL_OUTPUT_DSI:
6498                         is_dsi = true;
6499                         break;
6500                 default:
6501                         break;
6502                 }
6503
6504                 num_connectors++;
6505         }
6506
6507         if (is_dsi)
6508                 return 0;
6509
6510         if (!crtc_state->clock_set) {
6511                 refclk = i9xx_get_refclk(crtc, num_connectors);
6512
6513                 /*
6514                  * Returns a set of divisors for the desired target clock with
6515                  * the given refclk, or FALSE.  The returned values represent
6516                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6517                  * 2) / p1 / p2.
6518                  */
6519                 limit = intel_limit(crtc, refclk);
6520                 ok = dev_priv->display.find_dpll(limit, crtc,
6521                                                  crtc_state->port_clock,
6522                                                  refclk, NULL, &clock);
6523                 if (!ok) {
6524                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6525                         return -EINVAL;
6526                 }
6527
6528                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6529                         /*
6530                          * Ensure we match the reduced clock's P to the target
6531                          * clock.  If the clocks don't match, we can't switch
6532                          * the display clock by using the FP0/FP1. In such case
6533                          * we will disable the LVDS downclock feature.
6534                          */
6535                         has_reduced_clock =
6536                                 dev_priv->display.find_dpll(limit, crtc,
6537                                                             dev_priv->lvds_downclock,
6538                                                             refclk, &clock,
6539                                                             &reduced_clock);
6540                 }
6541                 /* Compat-code for transition, will disappear. */
6542                 crtc_state->dpll.n = clock.n;
6543                 crtc_state->dpll.m1 = clock.m1;
6544                 crtc_state->dpll.m2 = clock.m2;
6545                 crtc_state->dpll.p1 = clock.p1;
6546                 crtc_state->dpll.p2 = clock.p2;
6547         }
6548
6549         if (IS_GEN2(dev)) {
6550                 i8xx_update_pll(crtc, crtc_state,
6551                                 has_reduced_clock ? &reduced_clock : NULL,
6552                                 num_connectors);
6553         } else if (IS_CHERRYVIEW(dev)) {
6554                 chv_update_pll(crtc, crtc_state);
6555         } else if (IS_VALLEYVIEW(dev)) {
6556                 vlv_update_pll(crtc, crtc_state);
6557         } else {
6558                 i9xx_update_pll(crtc, crtc_state,
6559                                 has_reduced_clock ? &reduced_clock : NULL,
6560                                 num_connectors);
6561         }
6562
6563         return 0;
6564 }
6565
6566 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6567                                  struct intel_crtc_state *pipe_config)
6568 {
6569         struct drm_device *dev = crtc->base.dev;
6570         struct drm_i915_private *dev_priv = dev->dev_private;
6571         uint32_t tmp;
6572
6573         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6574                 return;
6575
6576         tmp = I915_READ(PFIT_CONTROL);
6577         if (!(tmp & PFIT_ENABLE))
6578                 return;
6579
6580         /* Check whether the pfit is attached to our pipe. */
6581         if (INTEL_INFO(dev)->gen < 4) {
6582                 if (crtc->pipe != PIPE_B)
6583                         return;
6584         } else {
6585                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6586                         return;
6587         }
6588
6589         pipe_config->gmch_pfit.control = tmp;
6590         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6591         if (INTEL_INFO(dev)->gen < 5)
6592                 pipe_config->gmch_pfit.lvds_border_bits =
6593                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6594 }
6595
6596 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6597                                struct intel_crtc_state *pipe_config)
6598 {
6599         struct drm_device *dev = crtc->base.dev;
6600         struct drm_i915_private *dev_priv = dev->dev_private;
6601         int pipe = pipe_config->cpu_transcoder;
6602         intel_clock_t clock;
6603         u32 mdiv;
6604         int refclk = 100000;
6605
6606         /* In case of MIPI DPLL will not even be used */
6607         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6608                 return;
6609
6610         mutex_lock(&dev_priv->dpio_lock);
6611         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6612         mutex_unlock(&dev_priv->dpio_lock);
6613
6614         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6615         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6616         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6617         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6618         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6619
6620         vlv_clock(refclk, &clock);
6621
6622         /* clock.dot is the fast clock */
6623         pipe_config->port_clock = clock.dot / 5;
6624 }
6625
6626 static void
6627 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6628                               struct intel_initial_plane_config *plane_config)
6629 {
6630         struct drm_device *dev = crtc->base.dev;
6631         struct drm_i915_private *dev_priv = dev->dev_private;
6632         u32 val, base, offset;
6633         int pipe = crtc->pipe, plane = crtc->plane;
6634         int fourcc, pixel_format;
6635         int aligned_height;
6636         struct drm_framebuffer *fb;
6637         struct intel_framebuffer *intel_fb;
6638
6639         val = I915_READ(DSPCNTR(plane));
6640         if (!(val & DISPLAY_PLANE_ENABLE))
6641                 return;
6642
6643         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6644         if (!intel_fb) {
6645                 DRM_DEBUG_KMS("failed to alloc fb\n");
6646                 return;
6647         }
6648
6649         fb = &intel_fb->base;
6650
6651         if (INTEL_INFO(dev)->gen >= 4) {
6652                 if (val & DISPPLANE_TILED) {
6653                         plane_config->tiling = I915_TILING_X;
6654                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6655                 }
6656         }
6657
6658         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6659         fourcc = i9xx_format_to_fourcc(pixel_format);
6660         fb->pixel_format = fourcc;
6661         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6662
6663         if (INTEL_INFO(dev)->gen >= 4) {
6664                 if (plane_config->tiling)
6665                         offset = I915_READ(DSPTILEOFF(plane));
6666                 else
6667                         offset = I915_READ(DSPLINOFF(plane));
6668                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6669         } else {
6670                 base = I915_READ(DSPADDR(plane));
6671         }
6672         plane_config->base = base;
6673
6674         val = I915_READ(PIPESRC(pipe));
6675         fb->width = ((val >> 16) & 0xfff) + 1;
6676         fb->height = ((val >> 0) & 0xfff) + 1;
6677
6678         val = I915_READ(DSPSTRIDE(pipe));
6679         fb->pitches[0] = val & 0xffffffc0;
6680
6681         aligned_height = intel_fb_align_height(dev, fb->height,
6682                                                fb->pixel_format,
6683                                                fb->modifier[0]);
6684
6685         plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6686
6687         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6688                       pipe_name(pipe), plane, fb->width, fb->height,
6689                       fb->bits_per_pixel, base, fb->pitches[0],
6690                       plane_config->size);
6691
6692         plane_config->fb = intel_fb;
6693 }
6694
6695 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6696                                struct intel_crtc_state *pipe_config)
6697 {
6698         struct drm_device *dev = crtc->base.dev;
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         int pipe = pipe_config->cpu_transcoder;
6701         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6702         intel_clock_t clock;
6703         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6704         int refclk = 100000;
6705
6706         mutex_lock(&dev_priv->dpio_lock);
6707         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6708         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6709         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6710         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6711         mutex_unlock(&dev_priv->dpio_lock);
6712
6713         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6714         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6715         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6716         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6717         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6718
6719         chv_clock(refclk, &clock);
6720
6721         /* clock.dot is the fast clock */
6722         pipe_config->port_clock = clock.dot / 5;
6723 }
6724
6725 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6726                                  struct intel_crtc_state *pipe_config)
6727 {
6728         struct drm_device *dev = crtc->base.dev;
6729         struct drm_i915_private *dev_priv = dev->dev_private;
6730         uint32_t tmp;
6731
6732         if (!intel_display_power_is_enabled(dev_priv,
6733                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6734                 return false;
6735
6736         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6737         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6738
6739         tmp = I915_READ(PIPECONF(crtc->pipe));
6740         if (!(tmp & PIPECONF_ENABLE))
6741                 return false;
6742
6743         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6744                 switch (tmp & PIPECONF_BPC_MASK) {
6745                 case PIPECONF_6BPC:
6746                         pipe_config->pipe_bpp = 18;
6747                         break;
6748                 case PIPECONF_8BPC:
6749                         pipe_config->pipe_bpp = 24;
6750                         break;
6751                 case PIPECONF_10BPC:
6752                         pipe_config->pipe_bpp = 30;
6753                         break;
6754                 default:
6755                         break;
6756                 }
6757         }
6758
6759         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6760                 pipe_config->limited_color_range = true;
6761
6762         if (INTEL_INFO(dev)->gen < 4)
6763                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6764
6765         intel_get_pipe_timings(crtc, pipe_config);
6766
6767         i9xx_get_pfit_config(crtc, pipe_config);
6768
6769         if (INTEL_INFO(dev)->gen >= 4) {
6770                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6771                 pipe_config->pixel_multiplier =
6772                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6773                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6774                 pipe_config->dpll_hw_state.dpll_md = tmp;
6775         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6776                 tmp = I915_READ(DPLL(crtc->pipe));
6777                 pipe_config->pixel_multiplier =
6778                         ((tmp & SDVO_MULTIPLIER_MASK)
6779                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6780         } else {
6781                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6782                  * port and will be fixed up in the encoder->get_config
6783                  * function. */
6784                 pipe_config->pixel_multiplier = 1;
6785         }
6786         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6787         if (!IS_VALLEYVIEW(dev)) {
6788                 /*
6789                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6790                  * on 830. Filter it out here so that we don't
6791                  * report errors due to that.
6792                  */
6793                 if (IS_I830(dev))
6794                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6795
6796                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6797                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6798         } else {
6799                 /* Mask out read-only status bits. */
6800                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6801                                                      DPLL_PORTC_READY_MASK |
6802                                                      DPLL_PORTB_READY_MASK);
6803         }
6804
6805         if (IS_CHERRYVIEW(dev))
6806                 chv_crtc_clock_get(crtc, pipe_config);
6807         else if (IS_VALLEYVIEW(dev))
6808                 vlv_crtc_clock_get(crtc, pipe_config);
6809         else
6810                 i9xx_crtc_clock_get(crtc, pipe_config);
6811
6812         return true;
6813 }
6814
6815 static void ironlake_init_pch_refclk(struct drm_device *dev)
6816 {
6817         struct drm_i915_private *dev_priv = dev->dev_private;
6818         struct intel_encoder *encoder;
6819         u32 val, final;
6820         bool has_lvds = false;
6821         bool has_cpu_edp = false;
6822         bool has_panel = false;
6823         bool has_ck505 = false;
6824         bool can_ssc = false;
6825
6826         /* We need to take the global config into account */
6827         for_each_intel_encoder(dev, encoder) {
6828                 switch (encoder->type) {
6829                 case INTEL_OUTPUT_LVDS:
6830                         has_panel = true;
6831                         has_lvds = true;
6832                         break;
6833                 case INTEL_OUTPUT_EDP:
6834                         has_panel = true;
6835                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6836                                 has_cpu_edp = true;
6837                         break;
6838                 default:
6839                         break;
6840                 }
6841         }
6842
6843         if (HAS_PCH_IBX(dev)) {
6844                 has_ck505 = dev_priv->vbt.display_clock_mode;
6845                 can_ssc = has_ck505;
6846         } else {
6847                 has_ck505 = false;
6848                 can_ssc = true;
6849         }
6850
6851         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6852                       has_panel, has_lvds, has_ck505);
6853
6854         /* Ironlake: try to setup display ref clock before DPLL
6855          * enabling. This is only under driver's control after
6856          * PCH B stepping, previous chipset stepping should be
6857          * ignoring this setting.
6858          */
6859         val = I915_READ(PCH_DREF_CONTROL);
6860
6861         /* As we must carefully and slowly disable/enable each source in turn,
6862          * compute the final state we want first and check if we need to
6863          * make any changes at all.
6864          */
6865         final = val;
6866         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6867         if (has_ck505)
6868                 final |= DREF_NONSPREAD_CK505_ENABLE;
6869         else
6870                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6871
6872         final &= ~DREF_SSC_SOURCE_MASK;
6873         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6874         final &= ~DREF_SSC1_ENABLE;
6875
6876         if (has_panel) {
6877                 final |= DREF_SSC_SOURCE_ENABLE;
6878
6879                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6880                         final |= DREF_SSC1_ENABLE;
6881
6882                 if (has_cpu_edp) {
6883                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6884                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6885                         else
6886                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6887                 } else
6888                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6889         } else {
6890                 final |= DREF_SSC_SOURCE_DISABLE;
6891                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6892         }
6893
6894         if (final == val)
6895                 return;
6896
6897         /* Always enable nonspread source */
6898         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6899
6900         if (has_ck505)
6901                 val |= DREF_NONSPREAD_CK505_ENABLE;
6902         else
6903                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6904
6905         if (has_panel) {
6906                 val &= ~DREF_SSC_SOURCE_MASK;
6907                 val |= DREF_SSC_SOURCE_ENABLE;
6908
6909                 /* SSC must be turned on before enabling the CPU output  */
6910                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6911                         DRM_DEBUG_KMS("Using SSC on panel\n");
6912                         val |= DREF_SSC1_ENABLE;
6913                 } else
6914                         val &= ~DREF_SSC1_ENABLE;
6915
6916                 /* Get SSC going before enabling the outputs */
6917                 I915_WRITE(PCH_DREF_CONTROL, val);
6918                 POSTING_READ(PCH_DREF_CONTROL);
6919                 udelay(200);
6920
6921                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6922
6923                 /* Enable CPU source on CPU attached eDP */
6924                 if (has_cpu_edp) {
6925                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6926                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6927                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6928                         } else
6929                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6930                 } else
6931                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6932
6933                 I915_WRITE(PCH_DREF_CONTROL, val);
6934                 POSTING_READ(PCH_DREF_CONTROL);
6935                 udelay(200);
6936         } else {
6937                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6938
6939                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6940
6941                 /* Turn off CPU output */
6942                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6943
6944                 I915_WRITE(PCH_DREF_CONTROL, val);
6945                 POSTING_READ(PCH_DREF_CONTROL);
6946                 udelay(200);
6947
6948                 /* Turn off the SSC source */
6949                 val &= ~DREF_SSC_SOURCE_MASK;
6950                 val |= DREF_SSC_SOURCE_DISABLE;
6951
6952                 /* Turn off SSC1 */
6953                 val &= ~DREF_SSC1_ENABLE;
6954
6955                 I915_WRITE(PCH_DREF_CONTROL, val);
6956                 POSTING_READ(PCH_DREF_CONTROL);
6957                 udelay(200);
6958         }
6959
6960         BUG_ON(val != final);
6961 }
6962
6963 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6964 {
6965         uint32_t tmp;
6966
6967         tmp = I915_READ(SOUTH_CHICKEN2);
6968         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6969         I915_WRITE(SOUTH_CHICKEN2, tmp);
6970
6971         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6972                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6973                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6974
6975         tmp = I915_READ(SOUTH_CHICKEN2);
6976         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6977         I915_WRITE(SOUTH_CHICKEN2, tmp);
6978
6979         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6980                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6981                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6982 }
6983
6984 /* WaMPhyProgramming:hsw */
6985 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6986 {
6987         uint32_t tmp;
6988
6989         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6990         tmp &= ~(0xFF << 24);
6991         tmp |= (0x12 << 24);
6992         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6993
6994         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6995         tmp |= (1 << 11);
6996         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6997
6998         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6999         tmp |= (1 << 11);
7000         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7001
7002         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7003         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7004         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7005
7006         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7007         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7008         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7009
7010         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7011         tmp &= ~(7 << 13);
7012         tmp |= (5 << 13);
7013         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7014
7015         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7016         tmp &= ~(7 << 13);
7017         tmp |= (5 << 13);
7018         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7019
7020         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7021         tmp &= ~0xFF;
7022         tmp |= 0x1C;
7023         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7024
7025         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7026         tmp &= ~0xFF;
7027         tmp |= 0x1C;
7028         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7029
7030         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7031         tmp &= ~(0xFF << 16);
7032         tmp |= (0x1C << 16);
7033         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7034
7035         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7036         tmp &= ~(0xFF << 16);
7037         tmp |= (0x1C << 16);
7038         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7039
7040         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7041         tmp |= (1 << 27);
7042         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7043
7044         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7045         tmp |= (1 << 27);
7046         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7047
7048         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7049         tmp &= ~(0xF << 28);
7050         tmp |= (4 << 28);
7051         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7052
7053         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7054         tmp &= ~(0xF << 28);
7055         tmp |= (4 << 28);
7056         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7057 }
7058
7059 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7060  * Programming" based on the parameters passed:
7061  * - Sequence to enable CLKOUT_DP
7062  * - Sequence to enable CLKOUT_DP without spread
7063  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7064  */
7065 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7066                                  bool with_fdi)
7067 {
7068         struct drm_i915_private *dev_priv = dev->dev_private;
7069         uint32_t reg, tmp;
7070
7071         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7072                 with_spread = true;
7073         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7074                  with_fdi, "LP PCH doesn't have FDI\n"))
7075                 with_fdi = false;
7076
7077         mutex_lock(&dev_priv->dpio_lock);
7078
7079         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7080         tmp &= ~SBI_SSCCTL_DISABLE;
7081         tmp |= SBI_SSCCTL_PATHALT;
7082         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7083
7084         udelay(24);
7085
7086         if (with_spread) {
7087                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7088                 tmp &= ~SBI_SSCCTL_PATHALT;
7089                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7090
7091                 if (with_fdi) {
7092                         lpt_reset_fdi_mphy(dev_priv);
7093                         lpt_program_fdi_mphy(dev_priv);
7094                 }
7095         }
7096
7097         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7098                SBI_GEN0 : SBI_DBUFF0;
7099         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7100         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7101         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7102
7103         mutex_unlock(&dev_priv->dpio_lock);
7104 }
7105
7106 /* Sequence to disable CLKOUT_DP */
7107 static void lpt_disable_clkout_dp(struct drm_device *dev)
7108 {
7109         struct drm_i915_private *dev_priv = dev->dev_private;
7110         uint32_t reg, tmp;
7111
7112         mutex_lock(&dev_priv->dpio_lock);
7113
7114         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7115                SBI_GEN0 : SBI_DBUFF0;
7116         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7117         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7118         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7119
7120         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7121         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7122                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7123                         tmp |= SBI_SSCCTL_PATHALT;
7124                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7125                         udelay(32);
7126                 }
7127                 tmp |= SBI_SSCCTL_DISABLE;
7128                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7129         }
7130
7131         mutex_unlock(&dev_priv->dpio_lock);
7132 }
7133
7134 static void lpt_init_pch_refclk(struct drm_device *dev)
7135 {
7136         struct intel_encoder *encoder;
7137         bool has_vga = false;
7138
7139         for_each_intel_encoder(dev, encoder) {
7140                 switch (encoder->type) {
7141                 case INTEL_OUTPUT_ANALOG:
7142                         has_vga = true;
7143                         break;
7144                 default:
7145                         break;
7146                 }
7147         }
7148
7149         if (has_vga)
7150                 lpt_enable_clkout_dp(dev, true, true);
7151         else
7152                 lpt_disable_clkout_dp(dev);
7153 }
7154
7155 /*
7156  * Initialize reference clocks when the driver loads
7157  */
7158 void intel_init_pch_refclk(struct drm_device *dev)
7159 {
7160         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7161                 ironlake_init_pch_refclk(dev);
7162         else if (HAS_PCH_LPT(dev))
7163                 lpt_init_pch_refclk(dev);
7164 }
7165
7166 static int ironlake_get_refclk(struct drm_crtc *crtc)
7167 {
7168         struct drm_device *dev = crtc->dev;
7169         struct drm_i915_private *dev_priv = dev->dev_private;
7170         struct intel_encoder *encoder;
7171         int num_connectors = 0;
7172         bool is_lvds = false;
7173
7174         for_each_intel_encoder(dev, encoder) {
7175                 if (encoder->new_crtc != to_intel_crtc(crtc))
7176                         continue;
7177
7178                 switch (encoder->type) {
7179                 case INTEL_OUTPUT_LVDS:
7180                         is_lvds = true;
7181                         break;
7182                 default:
7183                         break;
7184                 }
7185                 num_connectors++;
7186         }
7187
7188         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7189                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7190                               dev_priv->vbt.lvds_ssc_freq);
7191                 return dev_priv->vbt.lvds_ssc_freq;
7192         }
7193
7194         return 120000;
7195 }
7196
7197 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7198 {
7199         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7201         int pipe = intel_crtc->pipe;
7202         uint32_t val;
7203
7204         val = 0;
7205
7206         switch (intel_crtc->config->pipe_bpp) {
7207         case 18:
7208                 val |= PIPECONF_6BPC;
7209                 break;
7210         case 24:
7211                 val |= PIPECONF_8BPC;
7212                 break;
7213         case 30:
7214                 val |= PIPECONF_10BPC;
7215                 break;
7216         case 36:
7217                 val |= PIPECONF_12BPC;
7218                 break;
7219         default:
7220                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7221                 BUG();
7222         }
7223
7224         if (intel_crtc->config->dither)
7225                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7226
7227         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7228                 val |= PIPECONF_INTERLACED_ILK;
7229         else
7230                 val |= PIPECONF_PROGRESSIVE;
7231
7232         if (intel_crtc->config->limited_color_range)
7233                 val |= PIPECONF_COLOR_RANGE_SELECT;
7234
7235         I915_WRITE(PIPECONF(pipe), val);
7236         POSTING_READ(PIPECONF(pipe));
7237 }
7238
7239 /*
7240  * Set up the pipe CSC unit.
7241  *
7242  * Currently only full range RGB to limited range RGB conversion
7243  * is supported, but eventually this should handle various
7244  * RGB<->YCbCr scenarios as well.
7245  */
7246 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7247 {
7248         struct drm_device *dev = crtc->dev;
7249         struct drm_i915_private *dev_priv = dev->dev_private;
7250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7251         int pipe = intel_crtc->pipe;
7252         uint16_t coeff = 0x7800; /* 1.0 */
7253
7254         /*
7255          * TODO: Check what kind of values actually come out of the pipe
7256          * with these coeff/postoff values and adjust to get the best
7257          * accuracy. Perhaps we even need to take the bpc value into
7258          * consideration.
7259          */
7260
7261         if (intel_crtc->config->limited_color_range)
7262                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7263
7264         /*
7265          * GY/GU and RY/RU should be the other way around according
7266          * to BSpec, but reality doesn't agree. Just set them up in
7267          * a way that results in the correct picture.
7268          */
7269         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7270         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7271
7272         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7273         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7274
7275         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7276         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7277
7278         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7279         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7280         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7281
7282         if (INTEL_INFO(dev)->gen > 6) {
7283                 uint16_t postoff = 0;
7284
7285                 if (intel_crtc->config->limited_color_range)
7286                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7287
7288                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7289                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7290                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7291
7292                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7293         } else {
7294                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7295
7296                 if (intel_crtc->config->limited_color_range)
7297                         mode |= CSC_BLACK_SCREEN_OFFSET;
7298
7299                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7300         }
7301 }
7302
7303 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7304 {
7305         struct drm_device *dev = crtc->dev;
7306         struct drm_i915_private *dev_priv = dev->dev_private;
7307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7308         enum pipe pipe = intel_crtc->pipe;
7309         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7310         uint32_t val;
7311
7312         val = 0;
7313
7314         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7315                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7316
7317         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7318                 val |= PIPECONF_INTERLACED_ILK;
7319         else
7320                 val |= PIPECONF_PROGRESSIVE;
7321
7322         I915_WRITE(PIPECONF(cpu_transcoder), val);
7323         POSTING_READ(PIPECONF(cpu_transcoder));
7324
7325         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7326         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7327
7328         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7329                 val = 0;
7330
7331                 switch (intel_crtc->config->pipe_bpp) {
7332                 case 18:
7333                         val |= PIPEMISC_DITHER_6_BPC;
7334                         break;
7335                 case 24:
7336                         val |= PIPEMISC_DITHER_8_BPC;
7337                         break;
7338                 case 30:
7339                         val |= PIPEMISC_DITHER_10_BPC;
7340                         break;
7341                 case 36:
7342                         val |= PIPEMISC_DITHER_12_BPC;
7343                         break;
7344                 default:
7345                         /* Case prevented by pipe_config_set_bpp. */
7346                         BUG();
7347                 }
7348
7349                 if (intel_crtc->config->dither)
7350                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7351
7352                 I915_WRITE(PIPEMISC(pipe), val);
7353         }
7354 }
7355
7356 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7357                                     struct intel_crtc_state *crtc_state,
7358                                     intel_clock_t *clock,
7359                                     bool *has_reduced_clock,
7360                                     intel_clock_t *reduced_clock)
7361 {
7362         struct drm_device *dev = crtc->dev;
7363         struct drm_i915_private *dev_priv = dev->dev_private;
7364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7365         int refclk;
7366         const intel_limit_t *limit;
7367         bool ret, is_lvds = false;
7368
7369         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7370
7371         refclk = ironlake_get_refclk(crtc);
7372
7373         /*
7374          * Returns a set of divisors for the desired target clock with the given
7375          * refclk, or FALSE.  The returned values represent the clock equation:
7376          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7377          */
7378         limit = intel_limit(intel_crtc, refclk);
7379         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7380                                           crtc_state->port_clock,
7381                                           refclk, NULL, clock);
7382         if (!ret)
7383                 return false;
7384
7385         if (is_lvds && dev_priv->lvds_downclock_avail) {
7386                 /*
7387                  * Ensure we match the reduced clock's P to the target clock.
7388                  * If the clocks don't match, we can't switch the display clock
7389                  * by using the FP0/FP1. In such case we will disable the LVDS
7390                  * downclock feature.
7391                 */
7392                 *has_reduced_clock =
7393                         dev_priv->display.find_dpll(limit, intel_crtc,
7394                                                     dev_priv->lvds_downclock,
7395                                                     refclk, clock,
7396                                                     reduced_clock);
7397         }
7398
7399         return true;
7400 }
7401
7402 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7403 {
7404         /*
7405          * Account for spread spectrum to avoid
7406          * oversubscribing the link. Max center spread
7407          * is 2.5%; use 5% for safety's sake.
7408          */
7409         u32 bps = target_clock * bpp * 21 / 20;
7410         return DIV_ROUND_UP(bps, link_bw * 8);
7411 }
7412
7413 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7414 {
7415         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7416 }
7417
7418 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7419                                       struct intel_crtc_state *crtc_state,
7420                                       u32 *fp,
7421                                       intel_clock_t *reduced_clock, u32 *fp2)
7422 {
7423         struct drm_crtc *crtc = &intel_crtc->base;
7424         struct drm_device *dev = crtc->dev;
7425         struct drm_i915_private *dev_priv = dev->dev_private;
7426         struct intel_encoder *intel_encoder;
7427         uint32_t dpll;
7428         int factor, num_connectors = 0;
7429         bool is_lvds = false, is_sdvo = false;
7430
7431         for_each_intel_encoder(dev, intel_encoder) {
7432                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7433                         continue;
7434
7435                 switch (intel_encoder->type) {
7436                 case INTEL_OUTPUT_LVDS:
7437                         is_lvds = true;
7438                         break;
7439                 case INTEL_OUTPUT_SDVO:
7440                 case INTEL_OUTPUT_HDMI:
7441                         is_sdvo = true;
7442                         break;
7443                 default:
7444                         break;
7445                 }
7446
7447                 num_connectors++;
7448         }
7449
7450         /* Enable autotuning of the PLL clock (if permissible) */
7451         factor = 21;
7452         if (is_lvds) {
7453                 if ((intel_panel_use_ssc(dev_priv) &&
7454                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7455                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7456                         factor = 25;
7457         } else if (crtc_state->sdvo_tv_clock)
7458                 factor = 20;
7459
7460         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7461                 *fp |= FP_CB_TUNE;
7462
7463         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7464                 *fp2 |= FP_CB_TUNE;
7465
7466         dpll = 0;
7467
7468         if (is_lvds)
7469                 dpll |= DPLLB_MODE_LVDS;
7470         else
7471                 dpll |= DPLLB_MODE_DAC_SERIAL;
7472
7473         dpll |= (crtc_state->pixel_multiplier - 1)
7474                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7475
7476         if (is_sdvo)
7477                 dpll |= DPLL_SDVO_HIGH_SPEED;
7478         if (crtc_state->has_dp_encoder)
7479                 dpll |= DPLL_SDVO_HIGH_SPEED;
7480
7481         /* compute bitmask from p1 value */
7482         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7483         /* also FPA1 */
7484         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7485
7486         switch (crtc_state->dpll.p2) {
7487         case 5:
7488                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7489                 break;
7490         case 7:
7491                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7492                 break;
7493         case 10:
7494                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7495                 break;
7496         case 14:
7497                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7498                 break;
7499         }
7500
7501         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7502                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7503         else
7504                 dpll |= PLL_REF_INPUT_DREFCLK;
7505
7506         return dpll | DPLL_VCO_ENABLE;
7507 }
7508
7509 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7510                                        struct intel_crtc_state *crtc_state)
7511 {
7512         struct drm_device *dev = crtc->base.dev;
7513         intel_clock_t clock, reduced_clock;
7514         u32 dpll = 0, fp = 0, fp2 = 0;
7515         bool ok, has_reduced_clock = false;
7516         bool is_lvds = false;
7517         struct intel_shared_dpll *pll;
7518
7519         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7520
7521         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7522              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7523
7524         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7525                                      &has_reduced_clock, &reduced_clock);
7526         if (!ok && !crtc_state->clock_set) {
7527                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7528                 return -EINVAL;
7529         }
7530         /* Compat-code for transition, will disappear. */
7531         if (!crtc_state->clock_set) {
7532                 crtc_state->dpll.n = clock.n;
7533                 crtc_state->dpll.m1 = clock.m1;
7534                 crtc_state->dpll.m2 = clock.m2;
7535                 crtc_state->dpll.p1 = clock.p1;
7536                 crtc_state->dpll.p2 = clock.p2;
7537         }
7538
7539         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7540         if (crtc_state->has_pch_encoder) {
7541                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7542                 if (has_reduced_clock)
7543                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7544
7545                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7546                                              &fp, &reduced_clock,
7547                                              has_reduced_clock ? &fp2 : NULL);
7548
7549                 crtc_state->dpll_hw_state.dpll = dpll;
7550                 crtc_state->dpll_hw_state.fp0 = fp;
7551                 if (has_reduced_clock)
7552                         crtc_state->dpll_hw_state.fp1 = fp2;
7553                 else
7554                         crtc_state->dpll_hw_state.fp1 = fp;
7555
7556                 pll = intel_get_shared_dpll(crtc, crtc_state);
7557                 if (pll == NULL) {
7558                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7559                                          pipe_name(crtc->pipe));
7560                         return -EINVAL;
7561                 }
7562         }
7563
7564         if (is_lvds && has_reduced_clock && i915.powersave)
7565                 crtc->lowfreq_avail = true;
7566         else
7567                 crtc->lowfreq_avail = false;
7568
7569         return 0;
7570 }
7571
7572 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7573                                          struct intel_link_m_n *m_n)
7574 {
7575         struct drm_device *dev = crtc->base.dev;
7576         struct drm_i915_private *dev_priv = dev->dev_private;
7577         enum pipe pipe = crtc->pipe;
7578
7579         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7580         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7581         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7582                 & ~TU_SIZE_MASK;
7583         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7584         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7585                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7586 }
7587
7588 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7589                                          enum transcoder transcoder,
7590                                          struct intel_link_m_n *m_n,
7591                                          struct intel_link_m_n *m2_n2)
7592 {
7593         struct drm_device *dev = crtc->base.dev;
7594         struct drm_i915_private *dev_priv = dev->dev_private;
7595         enum pipe pipe = crtc->pipe;
7596
7597         if (INTEL_INFO(dev)->gen >= 5) {
7598                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7599                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7600                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7601                         & ~TU_SIZE_MASK;
7602                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7603                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7604                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7605                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7606                  * gen < 8) and if DRRS is supported (to make sure the
7607                  * registers are not unnecessarily read).
7608                  */
7609                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7610                         crtc->config->has_drrs) {
7611                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7612                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7613                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7614                                         & ~TU_SIZE_MASK;
7615                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7616                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7617                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7618                 }
7619         } else {
7620                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7621                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7622                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7623                         & ~TU_SIZE_MASK;
7624                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7625                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7626                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7627         }
7628 }
7629
7630 void intel_dp_get_m_n(struct intel_crtc *crtc,
7631                       struct intel_crtc_state *pipe_config)
7632 {
7633         if (pipe_config->has_pch_encoder)
7634                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7635         else
7636                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7637                                              &pipe_config->dp_m_n,
7638                                              &pipe_config->dp_m2_n2);
7639 }
7640
7641 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7642                                         struct intel_crtc_state *pipe_config)
7643 {
7644         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7645                                      &pipe_config->fdi_m_n, NULL);
7646 }
7647
7648 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7649                                     struct intel_crtc_state *pipe_config)
7650 {
7651         struct drm_device *dev = crtc->base.dev;
7652         struct drm_i915_private *dev_priv = dev->dev_private;
7653         uint32_t tmp;
7654
7655         tmp = I915_READ(PS_CTL(crtc->pipe));
7656
7657         if (tmp & PS_ENABLE) {
7658                 pipe_config->pch_pfit.enabled = true;
7659                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7660                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7661         }
7662 }
7663
7664 static void
7665 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7666                                  struct intel_initial_plane_config *plane_config)
7667 {
7668         struct drm_device *dev = crtc->base.dev;
7669         struct drm_i915_private *dev_priv = dev->dev_private;
7670         u32 val, base, offset, stride_mult;
7671         int pipe = crtc->pipe;
7672         int fourcc, pixel_format;
7673         int aligned_height;
7674         struct drm_framebuffer *fb;
7675         struct intel_framebuffer *intel_fb;
7676
7677         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7678         if (!intel_fb) {
7679                 DRM_DEBUG_KMS("failed to alloc fb\n");
7680                 return;
7681         }
7682
7683         fb = &intel_fb->base;
7684
7685         val = I915_READ(PLANE_CTL(pipe, 0));
7686         if (!(val & PLANE_CTL_ENABLE))
7687                 goto error;
7688
7689         if (val & PLANE_CTL_TILED_MASK) {
7690                 plane_config->tiling = I915_TILING_X;
7691                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7692         }
7693
7694         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7695         fourcc = skl_format_to_fourcc(pixel_format,
7696                                       val & PLANE_CTL_ORDER_RGBX,
7697                                       val & PLANE_CTL_ALPHA_MASK);
7698         fb->pixel_format = fourcc;
7699         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7700
7701         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7702         plane_config->base = base;
7703
7704         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7705
7706         val = I915_READ(PLANE_SIZE(pipe, 0));
7707         fb->height = ((val >> 16) & 0xfff) + 1;
7708         fb->width = ((val >> 0) & 0x1fff) + 1;
7709
7710         val = I915_READ(PLANE_STRIDE(pipe, 0));
7711         switch (plane_config->tiling) {
7712         case I915_TILING_NONE:
7713                 stride_mult = 64;
7714                 break;
7715         case I915_TILING_X:
7716                 stride_mult = 512;
7717                 break;
7718         default:
7719                 MISSING_CASE(plane_config->tiling);
7720                 goto error;
7721         }
7722         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7723
7724         aligned_height = intel_fb_align_height(dev, fb->height,
7725                                                fb->pixel_format,
7726                                                fb->modifier[0]);
7727
7728         plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7729
7730         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7731                       pipe_name(pipe), fb->width, fb->height,
7732                       fb->bits_per_pixel, base, fb->pitches[0],
7733                       plane_config->size);
7734
7735         plane_config->fb = intel_fb;
7736         return;
7737
7738 error:
7739         kfree(fb);
7740 }
7741
7742 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7743                                      struct intel_crtc_state *pipe_config)
7744 {
7745         struct drm_device *dev = crtc->base.dev;
7746         struct drm_i915_private *dev_priv = dev->dev_private;
7747         uint32_t tmp;
7748
7749         tmp = I915_READ(PF_CTL(crtc->pipe));
7750
7751         if (tmp & PF_ENABLE) {
7752                 pipe_config->pch_pfit.enabled = true;
7753                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7754                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7755
7756                 /* We currently do not free assignements of panel fitters on
7757                  * ivb/hsw (since we don't use the higher upscaling modes which
7758                  * differentiates them) so just WARN about this case for now. */
7759                 if (IS_GEN7(dev)) {
7760                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7761                                 PF_PIPE_SEL_IVB(crtc->pipe));
7762                 }
7763         }
7764 }
7765
7766 static void
7767 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7768                                   struct intel_initial_plane_config *plane_config)
7769 {
7770         struct drm_device *dev = crtc->base.dev;
7771         struct drm_i915_private *dev_priv = dev->dev_private;
7772         u32 val, base, offset;
7773         int pipe = crtc->pipe;
7774         int fourcc, pixel_format;
7775         int aligned_height;
7776         struct drm_framebuffer *fb;
7777         struct intel_framebuffer *intel_fb;
7778
7779         val = I915_READ(DSPCNTR(pipe));
7780         if (!(val & DISPLAY_PLANE_ENABLE))
7781                 return;
7782
7783         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7784         if (!intel_fb) {
7785                 DRM_DEBUG_KMS("failed to alloc fb\n");
7786                 return;
7787         }
7788
7789         fb = &intel_fb->base;
7790
7791         if (INTEL_INFO(dev)->gen >= 4) {
7792                 if (val & DISPPLANE_TILED) {
7793                         plane_config->tiling = I915_TILING_X;
7794                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7795                 }
7796         }
7797
7798         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7799         fourcc = i9xx_format_to_fourcc(pixel_format);
7800         fb->pixel_format = fourcc;
7801         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7802
7803         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7804         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7805                 offset = I915_READ(DSPOFFSET(pipe));
7806         } else {
7807                 if (plane_config->tiling)
7808                         offset = I915_READ(DSPTILEOFF(pipe));
7809                 else
7810                         offset = I915_READ(DSPLINOFF(pipe));
7811         }
7812         plane_config->base = base;
7813
7814         val = I915_READ(PIPESRC(pipe));
7815         fb->width = ((val >> 16) & 0xfff) + 1;
7816         fb->height = ((val >> 0) & 0xfff) + 1;
7817
7818         val = I915_READ(DSPSTRIDE(pipe));
7819         fb->pitches[0] = val & 0xffffffc0;
7820
7821         aligned_height = intel_fb_align_height(dev, fb->height,
7822                                                fb->pixel_format,
7823                                                fb->modifier[0]);
7824
7825         plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7826
7827         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7828                       pipe_name(pipe), fb->width, fb->height,
7829                       fb->bits_per_pixel, base, fb->pitches[0],
7830                       plane_config->size);
7831
7832         plane_config->fb = intel_fb;
7833 }
7834
7835 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7836                                      struct intel_crtc_state *pipe_config)
7837 {
7838         struct drm_device *dev = crtc->base.dev;
7839         struct drm_i915_private *dev_priv = dev->dev_private;
7840         uint32_t tmp;
7841
7842         if (!intel_display_power_is_enabled(dev_priv,
7843                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7844                 return false;
7845
7846         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7847         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7848
7849         tmp = I915_READ(PIPECONF(crtc->pipe));
7850         if (!(tmp & PIPECONF_ENABLE))
7851                 return false;
7852
7853         switch (tmp & PIPECONF_BPC_MASK) {
7854         case PIPECONF_6BPC:
7855                 pipe_config->pipe_bpp = 18;
7856                 break;
7857         case PIPECONF_8BPC:
7858                 pipe_config->pipe_bpp = 24;
7859                 break;
7860         case PIPECONF_10BPC:
7861                 pipe_config->pipe_bpp = 30;
7862                 break;
7863         case PIPECONF_12BPC:
7864                 pipe_config->pipe_bpp = 36;
7865                 break;
7866         default:
7867                 break;
7868         }
7869
7870         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7871                 pipe_config->limited_color_range = true;
7872
7873         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7874                 struct intel_shared_dpll *pll;
7875
7876                 pipe_config->has_pch_encoder = true;
7877
7878                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7879                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7880                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7881
7882                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7883
7884                 if (HAS_PCH_IBX(dev_priv->dev)) {
7885                         pipe_config->shared_dpll =
7886                                 (enum intel_dpll_id) crtc->pipe;
7887                 } else {
7888                         tmp = I915_READ(PCH_DPLL_SEL);
7889                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7890                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7891                         else
7892                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7893                 }
7894
7895                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7896
7897                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7898                                            &pipe_config->dpll_hw_state));
7899
7900                 tmp = pipe_config->dpll_hw_state.dpll;
7901                 pipe_config->pixel_multiplier =
7902                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7903                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7904
7905                 ironlake_pch_clock_get(crtc, pipe_config);
7906         } else {
7907                 pipe_config->pixel_multiplier = 1;
7908         }
7909
7910         intel_get_pipe_timings(crtc, pipe_config);
7911
7912         ironlake_get_pfit_config(crtc, pipe_config);
7913
7914         return true;
7915 }
7916
7917 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7918 {
7919         struct drm_device *dev = dev_priv->dev;
7920         struct intel_crtc *crtc;
7921
7922         for_each_intel_crtc(dev, crtc)
7923                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7924                      pipe_name(crtc->pipe));
7925
7926         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7927         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7928         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7929         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7930         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7931         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7932              "CPU PWM1 enabled\n");
7933         if (IS_HASWELL(dev))
7934                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7935                      "CPU PWM2 enabled\n");
7936         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7937              "PCH PWM1 enabled\n");
7938         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7939              "Utility pin enabled\n");
7940         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7941
7942         /*
7943          * In theory we can still leave IRQs enabled, as long as only the HPD
7944          * interrupts remain enabled. We used to check for that, but since it's
7945          * gen-specific and since we only disable LCPLL after we fully disable
7946          * the interrupts, the check below should be enough.
7947          */
7948         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7949 }
7950
7951 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7952 {
7953         struct drm_device *dev = dev_priv->dev;
7954
7955         if (IS_HASWELL(dev))
7956                 return I915_READ(D_COMP_HSW);
7957         else
7958                 return I915_READ(D_COMP_BDW);
7959 }
7960
7961 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7962 {
7963         struct drm_device *dev = dev_priv->dev;
7964
7965         if (IS_HASWELL(dev)) {
7966                 mutex_lock(&dev_priv->rps.hw_lock);
7967                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7968                                             val))
7969                         DRM_ERROR("Failed to write to D_COMP\n");
7970                 mutex_unlock(&dev_priv->rps.hw_lock);
7971         } else {
7972                 I915_WRITE(D_COMP_BDW, val);
7973                 POSTING_READ(D_COMP_BDW);
7974         }
7975 }
7976
7977 /*
7978  * This function implements pieces of two sequences from BSpec:
7979  * - Sequence for display software to disable LCPLL
7980  * - Sequence for display software to allow package C8+
7981  * The steps implemented here are just the steps that actually touch the LCPLL
7982  * register. Callers should take care of disabling all the display engine
7983  * functions, doing the mode unset, fixing interrupts, etc.
7984  */
7985 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7986                               bool switch_to_fclk, bool allow_power_down)
7987 {
7988         uint32_t val;
7989
7990         assert_can_disable_lcpll(dev_priv);
7991
7992         val = I915_READ(LCPLL_CTL);
7993
7994         if (switch_to_fclk) {
7995                 val |= LCPLL_CD_SOURCE_FCLK;
7996                 I915_WRITE(LCPLL_CTL, val);
7997
7998                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7999                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
8000                         DRM_ERROR("Switching to FCLK failed\n");
8001
8002                 val = I915_READ(LCPLL_CTL);
8003         }
8004
8005         val |= LCPLL_PLL_DISABLE;
8006         I915_WRITE(LCPLL_CTL, val);
8007         POSTING_READ(LCPLL_CTL);
8008
8009         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8010                 DRM_ERROR("LCPLL still locked\n");
8011
8012         val = hsw_read_dcomp(dev_priv);
8013         val |= D_COMP_COMP_DISABLE;
8014         hsw_write_dcomp(dev_priv, val);
8015         ndelay(100);
8016
8017         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8018                      1))
8019                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8020
8021         if (allow_power_down) {
8022                 val = I915_READ(LCPLL_CTL);
8023                 val |= LCPLL_POWER_DOWN_ALLOW;
8024                 I915_WRITE(LCPLL_CTL, val);
8025                 POSTING_READ(LCPLL_CTL);
8026         }
8027 }
8028
8029 /*
8030  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8031  * source.
8032  */
8033 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8034 {
8035         uint32_t val;
8036
8037         val = I915_READ(LCPLL_CTL);
8038
8039         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8040                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8041                 return;
8042
8043         /*
8044          * Make sure we're not on PC8 state before disabling PC8, otherwise
8045          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8046          */
8047         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8048
8049         if (val & LCPLL_POWER_DOWN_ALLOW) {
8050                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8051                 I915_WRITE(LCPLL_CTL, val);
8052                 POSTING_READ(LCPLL_CTL);
8053         }
8054
8055         val = hsw_read_dcomp(dev_priv);
8056         val |= D_COMP_COMP_FORCE;
8057         val &= ~D_COMP_COMP_DISABLE;
8058         hsw_write_dcomp(dev_priv, val);
8059
8060         val = I915_READ(LCPLL_CTL);
8061         val &= ~LCPLL_PLL_DISABLE;
8062         I915_WRITE(LCPLL_CTL, val);
8063
8064         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8065                 DRM_ERROR("LCPLL not locked yet\n");
8066
8067         if (val & LCPLL_CD_SOURCE_FCLK) {
8068                 val = I915_READ(LCPLL_CTL);
8069                 val &= ~LCPLL_CD_SOURCE_FCLK;
8070                 I915_WRITE(LCPLL_CTL, val);
8071
8072                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8073                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8074                         DRM_ERROR("Switching back to LCPLL failed\n");
8075         }
8076
8077         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8078 }
8079
8080 /*
8081  * Package states C8 and deeper are really deep PC states that can only be
8082  * reached when all the devices on the system allow it, so even if the graphics
8083  * device allows PC8+, it doesn't mean the system will actually get to these
8084  * states. Our driver only allows PC8+ when going into runtime PM.
8085  *
8086  * The requirements for PC8+ are that all the outputs are disabled, the power
8087  * well is disabled and most interrupts are disabled, and these are also
8088  * requirements for runtime PM. When these conditions are met, we manually do
8089  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8090  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8091  * hang the machine.
8092  *
8093  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8094  * the state of some registers, so when we come back from PC8+ we need to
8095  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8096  * need to take care of the registers kept by RC6. Notice that this happens even
8097  * if we don't put the device in PCI D3 state (which is what currently happens
8098  * because of the runtime PM support).
8099  *
8100  * For more, read "Display Sequences for Package C8" on the hardware
8101  * documentation.
8102  */
8103 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8104 {
8105         struct drm_device *dev = dev_priv->dev;
8106         uint32_t val;
8107
8108         DRM_DEBUG_KMS("Enabling package C8+\n");
8109
8110         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8111                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8112                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8113                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8114         }
8115
8116         lpt_disable_clkout_dp(dev);
8117         hsw_disable_lcpll(dev_priv, true, true);
8118 }
8119
8120 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8121 {
8122         struct drm_device *dev = dev_priv->dev;
8123         uint32_t val;
8124
8125         DRM_DEBUG_KMS("Disabling package C8+\n");
8126
8127         hsw_restore_lcpll(dev_priv);
8128         lpt_init_pch_refclk(dev);
8129
8130         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8131                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8132                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8133                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8134         }
8135
8136         intel_prepare_ddi(dev);
8137 }
8138
8139 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8140                                       struct intel_crtc_state *crtc_state)
8141 {
8142         if (!intel_ddi_pll_select(crtc, crtc_state))
8143                 return -EINVAL;
8144
8145         crtc->lowfreq_avail = false;
8146
8147         return 0;
8148 }
8149
8150 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8151                                 enum port port,
8152                                 struct intel_crtc_state *pipe_config)
8153 {
8154         u32 temp, dpll_ctl1;
8155
8156         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8157         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8158
8159         switch (pipe_config->ddi_pll_sel) {
8160         case SKL_DPLL0:
8161                 /*
8162                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8163                  * of the shared DPLL framework and thus needs to be read out
8164                  * separately
8165                  */
8166                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8167                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8168                 break;
8169         case SKL_DPLL1:
8170                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8171                 break;
8172         case SKL_DPLL2:
8173                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8174                 break;
8175         case SKL_DPLL3:
8176                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8177                 break;
8178         }
8179 }
8180
8181 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8182                                 enum port port,
8183                                 struct intel_crtc_state *pipe_config)
8184 {
8185         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8186
8187         switch (pipe_config->ddi_pll_sel) {
8188         case PORT_CLK_SEL_WRPLL1:
8189                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8190                 break;
8191         case PORT_CLK_SEL_WRPLL2:
8192                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8193                 break;
8194         }
8195 }
8196
8197 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8198                                        struct intel_crtc_state *pipe_config)
8199 {
8200         struct drm_device *dev = crtc->base.dev;
8201         struct drm_i915_private *dev_priv = dev->dev_private;
8202         struct intel_shared_dpll *pll;
8203         enum port port;
8204         uint32_t tmp;
8205
8206         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8207
8208         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8209
8210         if (IS_SKYLAKE(dev))
8211                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8212         else
8213                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8214
8215         if (pipe_config->shared_dpll >= 0) {
8216                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8217
8218                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8219                                            &pipe_config->dpll_hw_state));
8220         }
8221
8222         /*
8223          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8224          * DDI E. So just check whether this pipe is wired to DDI E and whether
8225          * the PCH transcoder is on.
8226          */
8227         if (INTEL_INFO(dev)->gen < 9 &&
8228             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8229                 pipe_config->has_pch_encoder = true;
8230
8231                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8232                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8233                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8234
8235                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8236         }
8237 }
8238
8239 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8240                                     struct intel_crtc_state *pipe_config)
8241 {
8242         struct drm_device *dev = crtc->base.dev;
8243         struct drm_i915_private *dev_priv = dev->dev_private;
8244         enum intel_display_power_domain pfit_domain;
8245         uint32_t tmp;
8246
8247         if (!intel_display_power_is_enabled(dev_priv,
8248                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8249                 return false;
8250
8251         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8252         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8253
8254         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8255         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8256                 enum pipe trans_edp_pipe;
8257                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8258                 default:
8259                         WARN(1, "unknown pipe linked to edp transcoder\n");
8260                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8261                 case TRANS_DDI_EDP_INPUT_A_ON:
8262                         trans_edp_pipe = PIPE_A;
8263                         break;
8264                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8265                         trans_edp_pipe = PIPE_B;
8266                         break;
8267                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8268                         trans_edp_pipe = PIPE_C;
8269                         break;
8270                 }
8271
8272                 if (trans_edp_pipe == crtc->pipe)
8273                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8274         }
8275
8276         if (!intel_display_power_is_enabled(dev_priv,
8277                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8278                 return false;
8279
8280         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8281         if (!(tmp & PIPECONF_ENABLE))
8282                 return false;
8283
8284         haswell_get_ddi_port_state(crtc, pipe_config);
8285
8286         intel_get_pipe_timings(crtc, pipe_config);
8287
8288         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8289         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8290                 if (IS_SKYLAKE(dev))
8291                         skylake_get_pfit_config(crtc, pipe_config);
8292                 else
8293                         ironlake_get_pfit_config(crtc, pipe_config);
8294         }
8295
8296         if (IS_HASWELL(dev))
8297                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8298                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8299
8300         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8301                 pipe_config->pixel_multiplier =
8302                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8303         } else {
8304                 pipe_config->pixel_multiplier = 1;
8305         }
8306
8307         return true;
8308 }
8309
8310 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8311 {
8312         struct drm_device *dev = crtc->dev;
8313         struct drm_i915_private *dev_priv = dev->dev_private;
8314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8315         uint32_t cntl = 0, size = 0;
8316
8317         if (base) {
8318                 unsigned int width = intel_crtc->cursor_width;
8319                 unsigned int height = intel_crtc->cursor_height;
8320                 unsigned int stride = roundup_pow_of_two(width) * 4;
8321
8322                 switch (stride) {
8323                 default:
8324                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8325                                   width, stride);
8326                         stride = 256;
8327                         /* fallthrough */
8328                 case 256:
8329                 case 512:
8330                 case 1024:
8331                 case 2048:
8332                         break;
8333                 }
8334
8335                 cntl |= CURSOR_ENABLE |
8336                         CURSOR_GAMMA_ENABLE |
8337                         CURSOR_FORMAT_ARGB |
8338                         CURSOR_STRIDE(stride);
8339
8340                 size = (height << 12) | width;
8341         }
8342
8343         if (intel_crtc->cursor_cntl != 0 &&
8344             (intel_crtc->cursor_base != base ||
8345              intel_crtc->cursor_size != size ||
8346              intel_crtc->cursor_cntl != cntl)) {
8347                 /* On these chipsets we can only modify the base/size/stride
8348                  * whilst the cursor is disabled.
8349                  */
8350                 I915_WRITE(_CURACNTR, 0);
8351                 POSTING_READ(_CURACNTR);
8352                 intel_crtc->cursor_cntl = 0;
8353         }
8354
8355         if (intel_crtc->cursor_base != base) {
8356                 I915_WRITE(_CURABASE, base);
8357                 intel_crtc->cursor_base = base;
8358         }
8359
8360         if (intel_crtc->cursor_size != size) {
8361                 I915_WRITE(CURSIZE, size);
8362                 intel_crtc->cursor_size = size;
8363         }
8364
8365         if (intel_crtc->cursor_cntl != cntl) {
8366                 I915_WRITE(_CURACNTR, cntl);
8367                 POSTING_READ(_CURACNTR);
8368                 intel_crtc->cursor_cntl = cntl;
8369         }
8370 }
8371
8372 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8373 {
8374         struct drm_device *dev = crtc->dev;
8375         struct drm_i915_private *dev_priv = dev->dev_private;
8376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8377         int pipe = intel_crtc->pipe;
8378         uint32_t cntl;
8379
8380         cntl = 0;
8381         if (base) {
8382                 cntl = MCURSOR_GAMMA_ENABLE;
8383                 switch (intel_crtc->cursor_width) {
8384                         case 64:
8385                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8386                                 break;
8387                         case 128:
8388                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8389                                 break;
8390                         case 256:
8391                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8392                                 break;
8393                         default:
8394                                 MISSING_CASE(intel_crtc->cursor_width);
8395                                 return;
8396                 }
8397                 cntl |= pipe << 28; /* Connect to correct pipe */
8398
8399                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8400                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8401         }
8402
8403         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8404                 cntl |= CURSOR_ROTATE_180;
8405
8406         if (intel_crtc->cursor_cntl != cntl) {
8407                 I915_WRITE(CURCNTR(pipe), cntl);
8408                 POSTING_READ(CURCNTR(pipe));
8409                 intel_crtc->cursor_cntl = cntl;
8410         }
8411
8412         /* and commit changes on next vblank */
8413         I915_WRITE(CURBASE(pipe), base);
8414         POSTING_READ(CURBASE(pipe));
8415
8416         intel_crtc->cursor_base = base;
8417 }
8418
8419 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8420 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8421                                      bool on)
8422 {
8423         struct drm_device *dev = crtc->dev;
8424         struct drm_i915_private *dev_priv = dev->dev_private;
8425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8426         int pipe = intel_crtc->pipe;
8427         int x = crtc->cursor_x;
8428         int y = crtc->cursor_y;
8429         u32 base = 0, pos = 0;
8430
8431         if (on)
8432                 base = intel_crtc->cursor_addr;
8433
8434         if (x >= intel_crtc->config->pipe_src_w)
8435                 base = 0;
8436
8437         if (y >= intel_crtc->config->pipe_src_h)
8438                 base = 0;
8439
8440         if (x < 0) {
8441                 if (x + intel_crtc->cursor_width <= 0)
8442                         base = 0;
8443
8444                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8445                 x = -x;
8446         }
8447         pos |= x << CURSOR_X_SHIFT;
8448
8449         if (y < 0) {
8450                 if (y + intel_crtc->cursor_height <= 0)
8451                         base = 0;
8452
8453                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8454                 y = -y;
8455         }
8456         pos |= y << CURSOR_Y_SHIFT;
8457
8458         if (base == 0 && intel_crtc->cursor_base == 0)
8459                 return;
8460
8461         I915_WRITE(CURPOS(pipe), pos);
8462
8463         /* ILK+ do this automagically */
8464         if (HAS_GMCH_DISPLAY(dev) &&
8465             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8466                 base += (intel_crtc->cursor_height *
8467                         intel_crtc->cursor_width - 1) * 4;
8468         }
8469
8470         if (IS_845G(dev) || IS_I865G(dev))
8471                 i845_update_cursor(crtc, base);
8472         else
8473                 i9xx_update_cursor(crtc, base);
8474 }
8475
8476 static bool cursor_size_ok(struct drm_device *dev,
8477                            uint32_t width, uint32_t height)
8478 {
8479         if (width == 0 || height == 0)
8480                 return false;
8481
8482         /*
8483          * 845g/865g are special in that they are only limited by
8484          * the width of their cursors, the height is arbitrary up to
8485          * the precision of the register. Everything else requires
8486          * square cursors, limited to a few power-of-two sizes.
8487          */
8488         if (IS_845G(dev) || IS_I865G(dev)) {
8489                 if ((width & 63) != 0)
8490                         return false;
8491
8492                 if (width > (IS_845G(dev) ? 64 : 512))
8493                         return false;
8494
8495                 if (height > 1023)
8496                         return false;
8497         } else {
8498                 switch (width | height) {
8499                 case 256:
8500                 case 128:
8501                         if (IS_GEN2(dev))
8502                                 return false;
8503                 case 64:
8504                         break;
8505                 default:
8506                         return false;
8507                 }
8508         }
8509
8510         return true;
8511 }
8512
8513 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8514                                  u16 *blue, uint32_t start, uint32_t size)
8515 {
8516         int end = (start + size > 256) ? 256 : start + size, i;
8517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8518
8519         for (i = start; i < end; i++) {
8520                 intel_crtc->lut_r[i] = red[i] >> 8;
8521                 intel_crtc->lut_g[i] = green[i] >> 8;
8522                 intel_crtc->lut_b[i] = blue[i] >> 8;
8523         }
8524
8525         intel_crtc_load_lut(crtc);
8526 }
8527
8528 /* VESA 640x480x72Hz mode to set on the pipe */
8529 static struct drm_display_mode load_detect_mode = {
8530         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8531                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8532 };
8533
8534 struct drm_framebuffer *
8535 __intel_framebuffer_create(struct drm_device *dev,
8536                            struct drm_mode_fb_cmd2 *mode_cmd,
8537                            struct drm_i915_gem_object *obj)
8538 {
8539         struct intel_framebuffer *intel_fb;
8540         int ret;
8541
8542         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8543         if (!intel_fb) {
8544                 drm_gem_object_unreference(&obj->base);
8545                 return ERR_PTR(-ENOMEM);
8546         }
8547
8548         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8549         if (ret)
8550                 goto err;
8551
8552         return &intel_fb->base;
8553 err:
8554         drm_gem_object_unreference(&obj->base);
8555         kfree(intel_fb);
8556
8557         return ERR_PTR(ret);
8558 }
8559
8560 static struct drm_framebuffer *
8561 intel_framebuffer_create(struct drm_device *dev,
8562                          struct drm_mode_fb_cmd2 *mode_cmd,
8563                          struct drm_i915_gem_object *obj)
8564 {
8565         struct drm_framebuffer *fb;
8566         int ret;
8567
8568         ret = i915_mutex_lock_interruptible(dev);
8569         if (ret)
8570                 return ERR_PTR(ret);
8571         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8572         mutex_unlock(&dev->struct_mutex);
8573
8574         return fb;
8575 }
8576
8577 static u32
8578 intel_framebuffer_pitch_for_width(int width, int bpp)
8579 {
8580         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8581         return ALIGN(pitch, 64);
8582 }
8583
8584 static u32
8585 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8586 {
8587         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8588         return PAGE_ALIGN(pitch * mode->vdisplay);
8589 }
8590
8591 static struct drm_framebuffer *
8592 intel_framebuffer_create_for_mode(struct drm_device *dev,
8593                                   struct drm_display_mode *mode,
8594                                   int depth, int bpp)
8595 {
8596         struct drm_i915_gem_object *obj;
8597         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8598
8599         obj = i915_gem_alloc_object(dev,
8600                                     intel_framebuffer_size_for_mode(mode, bpp));
8601         if (obj == NULL)
8602                 return ERR_PTR(-ENOMEM);
8603
8604         mode_cmd.width = mode->hdisplay;
8605         mode_cmd.height = mode->vdisplay;
8606         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8607                                                                 bpp);
8608         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8609
8610         return intel_framebuffer_create(dev, &mode_cmd, obj);
8611 }
8612
8613 static struct drm_framebuffer *
8614 mode_fits_in_fbdev(struct drm_device *dev,
8615                    struct drm_display_mode *mode)
8616 {
8617 #ifdef CONFIG_DRM_I915_FBDEV
8618         struct drm_i915_private *dev_priv = dev->dev_private;
8619         struct drm_i915_gem_object *obj;
8620         struct drm_framebuffer *fb;
8621
8622         if (!dev_priv->fbdev)
8623                 return NULL;
8624
8625         if (!dev_priv->fbdev->fb)
8626                 return NULL;
8627
8628         obj = dev_priv->fbdev->fb->obj;
8629         BUG_ON(!obj);
8630
8631         fb = &dev_priv->fbdev->fb->base;
8632         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8633                                                                fb->bits_per_pixel))
8634                 return NULL;
8635
8636         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8637                 return NULL;
8638
8639         return fb;
8640 #else
8641         return NULL;
8642 #endif
8643 }
8644
8645 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8646                                 struct drm_display_mode *mode,
8647                                 struct intel_load_detect_pipe *old,
8648                                 struct drm_modeset_acquire_ctx *ctx)
8649 {
8650         struct intel_crtc *intel_crtc;
8651         struct intel_encoder *intel_encoder =
8652                 intel_attached_encoder(connector);
8653         struct drm_crtc *possible_crtc;
8654         struct drm_encoder *encoder = &intel_encoder->base;
8655         struct drm_crtc *crtc = NULL;
8656         struct drm_device *dev = encoder->dev;
8657         struct drm_framebuffer *fb;
8658         struct drm_mode_config *config = &dev->mode_config;
8659         int ret, i = -1;
8660
8661         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8662                       connector->base.id, connector->name,
8663                       encoder->base.id, encoder->name);
8664
8665 retry:
8666         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8667         if (ret)
8668                 goto fail_unlock;
8669
8670         /*
8671          * Algorithm gets a little messy:
8672          *
8673          *   - if the connector already has an assigned crtc, use it (but make
8674          *     sure it's on first)
8675          *
8676          *   - try to find the first unused crtc that can drive this connector,
8677          *     and use that if we find one
8678          */
8679
8680         /* See if we already have a CRTC for this connector */
8681         if (encoder->crtc) {
8682                 crtc = encoder->crtc;
8683
8684                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8685                 if (ret)
8686                         goto fail_unlock;
8687                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8688                 if (ret)
8689                         goto fail_unlock;
8690
8691                 old->dpms_mode = connector->dpms;
8692                 old->load_detect_temp = false;
8693
8694                 /* Make sure the crtc and connector are running */
8695                 if (connector->dpms != DRM_MODE_DPMS_ON)
8696                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8697
8698                 return true;
8699         }
8700
8701         /* Find an unused one (if possible) */
8702         for_each_crtc(dev, possible_crtc) {
8703                 i++;
8704                 if (!(encoder->possible_crtcs & (1 << i)))
8705                         continue;
8706                 if (possible_crtc->state->enable)
8707                         continue;
8708                 /* This can occur when applying the pipe A quirk on resume. */
8709                 if (to_intel_crtc(possible_crtc)->new_enabled)
8710                         continue;
8711
8712                 crtc = possible_crtc;
8713                 break;
8714         }
8715
8716         /*
8717          * If we didn't find an unused CRTC, don't use any.
8718          */
8719         if (!crtc) {
8720                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8721                 goto fail_unlock;
8722         }
8723
8724         ret = drm_modeset_lock(&crtc->mutex, ctx);
8725         if (ret)
8726                 goto fail_unlock;
8727         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8728         if (ret)
8729                 goto fail_unlock;
8730         intel_encoder->new_crtc = to_intel_crtc(crtc);
8731         to_intel_connector(connector)->new_encoder = intel_encoder;
8732
8733         intel_crtc = to_intel_crtc(crtc);
8734         intel_crtc->new_enabled = true;
8735         intel_crtc->new_config = intel_crtc->config;
8736         old->dpms_mode = connector->dpms;
8737         old->load_detect_temp = true;
8738         old->release_fb = NULL;
8739
8740         if (!mode)
8741                 mode = &load_detect_mode;
8742
8743         /* We need a framebuffer large enough to accommodate all accesses
8744          * that the plane may generate whilst we perform load detection.
8745          * We can not rely on the fbcon either being present (we get called
8746          * during its initialisation to detect all boot displays, or it may
8747          * not even exist) or that it is large enough to satisfy the
8748          * requested mode.
8749          */
8750         fb = mode_fits_in_fbdev(dev, mode);
8751         if (fb == NULL) {
8752                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8753                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8754                 old->release_fb = fb;
8755         } else
8756                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8757         if (IS_ERR(fb)) {
8758                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8759                 goto fail;
8760         }
8761
8762         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8763                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8764                 if (old->release_fb)
8765                         old->release_fb->funcs->destroy(old->release_fb);
8766                 goto fail;
8767         }
8768
8769         /* let the connector get through one full cycle before testing */
8770         intel_wait_for_vblank(dev, intel_crtc->pipe);
8771         return true;
8772
8773  fail:
8774         intel_crtc->new_enabled = crtc->state->enable;
8775         if (intel_crtc->new_enabled)
8776                 intel_crtc->new_config = intel_crtc->config;
8777         else
8778                 intel_crtc->new_config = NULL;
8779 fail_unlock:
8780         if (ret == -EDEADLK) {
8781                 drm_modeset_backoff(ctx);
8782                 goto retry;
8783         }
8784
8785         return false;
8786 }
8787
8788 void intel_release_load_detect_pipe(struct drm_connector *connector,
8789                                     struct intel_load_detect_pipe *old)
8790 {
8791         struct intel_encoder *intel_encoder =
8792                 intel_attached_encoder(connector);
8793         struct drm_encoder *encoder = &intel_encoder->base;
8794         struct drm_crtc *crtc = encoder->crtc;
8795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8796
8797         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8798                       connector->base.id, connector->name,
8799                       encoder->base.id, encoder->name);
8800
8801         if (old->load_detect_temp) {
8802                 to_intel_connector(connector)->new_encoder = NULL;
8803                 intel_encoder->new_crtc = NULL;
8804                 intel_crtc->new_enabled = false;
8805                 intel_crtc->new_config = NULL;
8806                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8807
8808                 if (old->release_fb) {
8809                         drm_framebuffer_unregister_private(old->release_fb);
8810                         drm_framebuffer_unreference(old->release_fb);
8811                 }
8812
8813                 return;
8814         }
8815
8816         /* Switch crtc and encoder back off if necessary */
8817         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8818                 connector->funcs->dpms(connector, old->dpms_mode);
8819 }
8820
8821 static int i9xx_pll_refclk(struct drm_device *dev,
8822                            const struct intel_crtc_state *pipe_config)
8823 {
8824         struct drm_i915_private *dev_priv = dev->dev_private;
8825         u32 dpll = pipe_config->dpll_hw_state.dpll;
8826
8827         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8828                 return dev_priv->vbt.lvds_ssc_freq;
8829         else if (HAS_PCH_SPLIT(dev))
8830                 return 120000;
8831         else if (!IS_GEN2(dev))
8832                 return 96000;
8833         else
8834                 return 48000;
8835 }
8836
8837 /* Returns the clock of the currently programmed mode of the given pipe. */
8838 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8839                                 struct intel_crtc_state *pipe_config)
8840 {
8841         struct drm_device *dev = crtc->base.dev;
8842         struct drm_i915_private *dev_priv = dev->dev_private;
8843         int pipe = pipe_config->cpu_transcoder;
8844         u32 dpll = pipe_config->dpll_hw_state.dpll;
8845         u32 fp;
8846         intel_clock_t clock;
8847         int refclk = i9xx_pll_refclk(dev, pipe_config);
8848
8849         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8850                 fp = pipe_config->dpll_hw_state.fp0;
8851         else
8852                 fp = pipe_config->dpll_hw_state.fp1;
8853
8854         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8855         if (IS_PINEVIEW(dev)) {
8856                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8857                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8858         } else {
8859                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8860                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8861         }
8862
8863         if (!IS_GEN2(dev)) {
8864                 if (IS_PINEVIEW(dev))
8865                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8866                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8867                 else
8868                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8869                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8870
8871                 switch (dpll & DPLL_MODE_MASK) {
8872                 case DPLLB_MODE_DAC_SERIAL:
8873                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8874                                 5 : 10;
8875                         break;
8876                 case DPLLB_MODE_LVDS:
8877                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8878                                 7 : 14;
8879                         break;
8880                 default:
8881                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8882                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8883                         return;
8884                 }
8885
8886                 if (IS_PINEVIEW(dev))
8887                         pineview_clock(refclk, &clock);
8888                 else
8889                         i9xx_clock(refclk, &clock);
8890         } else {
8891                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8892                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8893
8894                 if (is_lvds) {
8895                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8896                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8897
8898                         if (lvds & LVDS_CLKB_POWER_UP)
8899                                 clock.p2 = 7;
8900                         else
8901                                 clock.p2 = 14;
8902                 } else {
8903                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8904                                 clock.p1 = 2;
8905                         else {
8906                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8907                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8908                         }
8909                         if (dpll & PLL_P2_DIVIDE_BY_4)
8910                                 clock.p2 = 4;
8911                         else
8912                                 clock.p2 = 2;
8913                 }
8914
8915                 i9xx_clock(refclk, &clock);
8916         }
8917
8918         /*
8919          * This value includes pixel_multiplier. We will use
8920          * port_clock to compute adjusted_mode.crtc_clock in the
8921          * encoder's get_config() function.
8922          */
8923         pipe_config->port_clock = clock.dot;
8924 }
8925
8926 int intel_dotclock_calculate(int link_freq,
8927                              const struct intel_link_m_n *m_n)
8928 {
8929         /*
8930          * The calculation for the data clock is:
8931          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8932          * But we want to avoid losing precison if possible, so:
8933          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8934          *
8935          * and the link clock is simpler:
8936          * link_clock = (m * link_clock) / n
8937          */
8938
8939         if (!m_n->link_n)
8940                 return 0;
8941
8942         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8943 }
8944
8945 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8946                                    struct intel_crtc_state *pipe_config)
8947 {
8948         struct drm_device *dev = crtc->base.dev;
8949
8950         /* read out port_clock from the DPLL */
8951         i9xx_crtc_clock_get(crtc, pipe_config);
8952
8953         /*
8954          * This value does not include pixel_multiplier.
8955          * We will check that port_clock and adjusted_mode.crtc_clock
8956          * agree once we know their relationship in the encoder's
8957          * get_config() function.
8958          */
8959         pipe_config->base.adjusted_mode.crtc_clock =
8960                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8961                                          &pipe_config->fdi_m_n);
8962 }
8963
8964 /** Returns the currently programmed mode of the given pipe. */
8965 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8966                                              struct drm_crtc *crtc)
8967 {
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8970         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8971         struct drm_display_mode *mode;
8972         struct intel_crtc_state pipe_config;
8973         int htot = I915_READ(HTOTAL(cpu_transcoder));
8974         int hsync = I915_READ(HSYNC(cpu_transcoder));
8975         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8976         int vsync = I915_READ(VSYNC(cpu_transcoder));
8977         enum pipe pipe = intel_crtc->pipe;
8978
8979         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8980         if (!mode)
8981                 return NULL;
8982
8983         /*
8984          * Construct a pipe_config sufficient for getting the clock info
8985          * back out of crtc_clock_get.
8986          *
8987          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8988          * to use a real value here instead.
8989          */
8990         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8991         pipe_config.pixel_multiplier = 1;
8992         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8993         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8994         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8995         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8996
8997         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8998         mode->hdisplay = (htot & 0xffff) + 1;
8999         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9000         mode->hsync_start = (hsync & 0xffff) + 1;
9001         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9002         mode->vdisplay = (vtot & 0xffff) + 1;
9003         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9004         mode->vsync_start = (vsync & 0xffff) + 1;
9005         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9006
9007         drm_mode_set_name(mode);
9008
9009         return mode;
9010 }
9011
9012 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9013 {
9014         struct drm_device *dev = crtc->dev;
9015         struct drm_i915_private *dev_priv = dev->dev_private;
9016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9017
9018         if (!HAS_GMCH_DISPLAY(dev))
9019                 return;
9020
9021         if (!dev_priv->lvds_downclock_avail)
9022                 return;
9023
9024         /*
9025          * Since this is called by a timer, we should never get here in
9026          * the manual case.
9027          */
9028         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9029                 int pipe = intel_crtc->pipe;
9030                 int dpll_reg = DPLL(pipe);
9031                 int dpll;
9032
9033                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9034
9035                 assert_panel_unlocked(dev_priv, pipe);
9036
9037                 dpll = I915_READ(dpll_reg);
9038                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9039                 I915_WRITE(dpll_reg, dpll);
9040                 intel_wait_for_vblank(dev, pipe);
9041                 dpll = I915_READ(dpll_reg);
9042                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9043                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9044         }
9045
9046 }
9047
9048 void intel_mark_busy(struct drm_device *dev)
9049 {
9050         struct drm_i915_private *dev_priv = dev->dev_private;
9051
9052         if (dev_priv->mm.busy)
9053                 return;
9054
9055         intel_runtime_pm_get(dev_priv);
9056         i915_update_gfx_val(dev_priv);
9057         dev_priv->mm.busy = true;
9058 }
9059
9060 void intel_mark_idle(struct drm_device *dev)
9061 {
9062         struct drm_i915_private *dev_priv = dev->dev_private;
9063         struct drm_crtc *crtc;
9064
9065         if (!dev_priv->mm.busy)
9066                 return;
9067
9068         dev_priv->mm.busy = false;
9069
9070         if (!i915.powersave)
9071                 goto out;
9072
9073         for_each_crtc(dev, crtc) {
9074                 if (!crtc->primary->fb)
9075                         continue;
9076
9077                 intel_decrease_pllclock(crtc);
9078         }
9079
9080         if (INTEL_INFO(dev)->gen >= 6)
9081                 gen6_rps_idle(dev->dev_private);
9082
9083 out:
9084         intel_runtime_pm_put(dev_priv);
9085 }
9086
9087 static void intel_crtc_set_state(struct intel_crtc *crtc,
9088                                  struct intel_crtc_state *crtc_state)
9089 {
9090         kfree(crtc->config);
9091         crtc->config = crtc_state;
9092         crtc->base.state = &crtc_state->base;
9093 }
9094
9095 static void intel_crtc_destroy(struct drm_crtc *crtc)
9096 {
9097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9098         struct drm_device *dev = crtc->dev;
9099         struct intel_unpin_work *work;
9100
9101         spin_lock_irq(&dev->event_lock);
9102         work = intel_crtc->unpin_work;
9103         intel_crtc->unpin_work = NULL;
9104         spin_unlock_irq(&dev->event_lock);
9105
9106         if (work) {
9107                 cancel_work_sync(&work->work);
9108                 kfree(work);
9109         }
9110
9111         intel_crtc_set_state(intel_crtc, NULL);
9112         drm_crtc_cleanup(crtc);
9113
9114         kfree(intel_crtc);
9115 }
9116
9117 static void intel_unpin_work_fn(struct work_struct *__work)
9118 {
9119         struct intel_unpin_work *work =
9120                 container_of(__work, struct intel_unpin_work, work);
9121         struct drm_device *dev = work->crtc->dev;
9122         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9123
9124         mutex_lock(&dev->struct_mutex);
9125         intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9126         drm_gem_object_unreference(&work->pending_flip_obj->base);
9127         drm_framebuffer_unreference(work->old_fb);
9128
9129         intel_fbc_update(dev);
9130
9131         if (work->flip_queued_req)
9132                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9133         mutex_unlock(&dev->struct_mutex);
9134
9135         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9136
9137         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9138         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9139
9140         kfree(work);
9141 }
9142
9143 static void do_intel_finish_page_flip(struct drm_device *dev,
9144                                       struct drm_crtc *crtc)
9145 {
9146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9147         struct intel_unpin_work *work;
9148         unsigned long flags;
9149
9150         /* Ignore early vblank irqs */
9151         if (intel_crtc == NULL)
9152                 return;
9153
9154         /*
9155          * This is called both by irq handlers and the reset code (to complete
9156          * lost pageflips) so needs the full irqsave spinlocks.
9157          */
9158         spin_lock_irqsave(&dev->event_lock, flags);
9159         work = intel_crtc->unpin_work;
9160
9161         /* Ensure we don't miss a work->pending update ... */
9162         smp_rmb();
9163
9164         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9165                 spin_unlock_irqrestore(&dev->event_lock, flags);
9166                 return;
9167         }
9168
9169         page_flip_completed(intel_crtc);
9170
9171         spin_unlock_irqrestore(&dev->event_lock, flags);
9172 }
9173
9174 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9175 {
9176         struct drm_i915_private *dev_priv = dev->dev_private;
9177         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9178
9179         do_intel_finish_page_flip(dev, crtc);
9180 }
9181
9182 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9183 {
9184         struct drm_i915_private *dev_priv = dev->dev_private;
9185         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9186
9187         do_intel_finish_page_flip(dev, crtc);
9188 }
9189
9190 /* Is 'a' after or equal to 'b'? */
9191 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9192 {
9193         return !((a - b) & 0x80000000);
9194 }
9195
9196 static bool page_flip_finished(struct intel_crtc *crtc)
9197 {
9198         struct drm_device *dev = crtc->base.dev;
9199         struct drm_i915_private *dev_priv = dev->dev_private;
9200
9201         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9202             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9203                 return true;
9204
9205         /*
9206          * The relevant registers doen't exist on pre-ctg.
9207          * As the flip done interrupt doesn't trigger for mmio
9208          * flips on gmch platforms, a flip count check isn't
9209          * really needed there. But since ctg has the registers,
9210          * include it in the check anyway.
9211          */
9212         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9213                 return true;
9214
9215         /*
9216          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9217          * used the same base address. In that case the mmio flip might
9218          * have completed, but the CS hasn't even executed the flip yet.
9219          *
9220          * A flip count check isn't enough as the CS might have updated
9221          * the base address just after start of vblank, but before we
9222          * managed to process the interrupt. This means we'd complete the
9223          * CS flip too soon.
9224          *
9225          * Combining both checks should get us a good enough result. It may
9226          * still happen that the CS flip has been executed, but has not
9227          * yet actually completed. But in case the base address is the same
9228          * anyway, we don't really care.
9229          */
9230         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9231                 crtc->unpin_work->gtt_offset &&
9232                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9233                                     crtc->unpin_work->flip_count);
9234 }
9235
9236 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9237 {
9238         struct drm_i915_private *dev_priv = dev->dev_private;
9239         struct intel_crtc *intel_crtc =
9240                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9241         unsigned long flags;
9242
9243
9244         /*
9245          * This is called both by irq handlers and the reset code (to complete
9246          * lost pageflips) so needs the full irqsave spinlocks.
9247          *
9248          * NB: An MMIO update of the plane base pointer will also
9249          * generate a page-flip completion irq, i.e. every modeset
9250          * is also accompanied by a spurious intel_prepare_page_flip().
9251          */
9252         spin_lock_irqsave(&dev->event_lock, flags);
9253         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9254                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9255         spin_unlock_irqrestore(&dev->event_lock, flags);
9256 }
9257
9258 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9259 {
9260         /* Ensure that the work item is consistent when activating it ... */
9261         smp_wmb();
9262         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9263         /* and that it is marked active as soon as the irq could fire. */
9264         smp_wmb();
9265 }
9266
9267 static int intel_gen2_queue_flip(struct drm_device *dev,
9268                                  struct drm_crtc *crtc,
9269                                  struct drm_framebuffer *fb,
9270                                  struct drm_i915_gem_object *obj,
9271                                  struct intel_engine_cs *ring,
9272                                  uint32_t flags)
9273 {
9274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9275         u32 flip_mask;
9276         int ret;
9277
9278         ret = intel_ring_begin(ring, 6);
9279         if (ret)
9280                 return ret;
9281
9282         /* Can't queue multiple flips, so wait for the previous
9283          * one to finish before executing the next.
9284          */
9285         if (intel_crtc->plane)
9286                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9287         else
9288                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9289         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9290         intel_ring_emit(ring, MI_NOOP);
9291         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9292                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9293         intel_ring_emit(ring, fb->pitches[0]);
9294         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9295         intel_ring_emit(ring, 0); /* aux display base address, unused */
9296
9297         intel_mark_page_flip_active(intel_crtc);
9298         __intel_ring_advance(ring);
9299         return 0;
9300 }
9301
9302 static int intel_gen3_queue_flip(struct drm_device *dev,
9303                                  struct drm_crtc *crtc,
9304                                  struct drm_framebuffer *fb,
9305                                  struct drm_i915_gem_object *obj,
9306                                  struct intel_engine_cs *ring,
9307                                  uint32_t flags)
9308 {
9309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9310         u32 flip_mask;
9311         int ret;
9312
9313         ret = intel_ring_begin(ring, 6);
9314         if (ret)
9315                 return ret;
9316
9317         if (intel_crtc->plane)
9318                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9319         else
9320                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9321         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9322         intel_ring_emit(ring, MI_NOOP);
9323         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9324                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9325         intel_ring_emit(ring, fb->pitches[0]);
9326         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9327         intel_ring_emit(ring, MI_NOOP);
9328
9329         intel_mark_page_flip_active(intel_crtc);
9330         __intel_ring_advance(ring);
9331         return 0;
9332 }
9333
9334 static int intel_gen4_queue_flip(struct drm_device *dev,
9335                                  struct drm_crtc *crtc,
9336                                  struct drm_framebuffer *fb,
9337                                  struct drm_i915_gem_object *obj,
9338                                  struct intel_engine_cs *ring,
9339                                  uint32_t flags)
9340 {
9341         struct drm_i915_private *dev_priv = dev->dev_private;
9342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9343         uint32_t pf, pipesrc;
9344         int ret;
9345
9346         ret = intel_ring_begin(ring, 4);
9347         if (ret)
9348                 return ret;
9349
9350         /* i965+ uses the linear or tiled offsets from the
9351          * Display Registers (which do not change across a page-flip)
9352          * so we need only reprogram the base address.
9353          */
9354         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9355                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9356         intel_ring_emit(ring, fb->pitches[0]);
9357         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9358                         obj->tiling_mode);
9359
9360         /* XXX Enabling the panel-fitter across page-flip is so far
9361          * untested on non-native modes, so ignore it for now.
9362          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9363          */
9364         pf = 0;
9365         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9366         intel_ring_emit(ring, pf | pipesrc);
9367
9368         intel_mark_page_flip_active(intel_crtc);
9369         __intel_ring_advance(ring);
9370         return 0;
9371 }
9372
9373 static int intel_gen6_queue_flip(struct drm_device *dev,
9374                                  struct drm_crtc *crtc,
9375                                  struct drm_framebuffer *fb,
9376                                  struct drm_i915_gem_object *obj,
9377                                  struct intel_engine_cs *ring,
9378                                  uint32_t flags)
9379 {
9380         struct drm_i915_private *dev_priv = dev->dev_private;
9381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9382         uint32_t pf, pipesrc;
9383         int ret;
9384
9385         ret = intel_ring_begin(ring, 4);
9386         if (ret)
9387                 return ret;
9388
9389         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9390                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9391         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9392         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9393
9394         /* Contrary to the suggestions in the documentation,
9395          * "Enable Panel Fitter" does not seem to be required when page
9396          * flipping with a non-native mode, and worse causes a normal
9397          * modeset to fail.
9398          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9399          */
9400         pf = 0;
9401         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9402         intel_ring_emit(ring, pf | pipesrc);
9403
9404         intel_mark_page_flip_active(intel_crtc);
9405         __intel_ring_advance(ring);
9406         return 0;
9407 }
9408
9409 static int intel_gen7_queue_flip(struct drm_device *dev,
9410                                  struct drm_crtc *crtc,
9411                                  struct drm_framebuffer *fb,
9412                                  struct drm_i915_gem_object *obj,
9413                                  struct intel_engine_cs *ring,
9414                                  uint32_t flags)
9415 {
9416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9417         uint32_t plane_bit = 0;
9418         int len, ret;
9419
9420         switch (intel_crtc->plane) {
9421         case PLANE_A:
9422                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9423                 break;
9424         case PLANE_B:
9425                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9426                 break;
9427         case PLANE_C:
9428                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9429                 break;
9430         default:
9431                 WARN_ONCE(1, "unknown plane in flip command\n");
9432                 return -ENODEV;
9433         }
9434
9435         len = 4;
9436         if (ring->id == RCS) {
9437                 len += 6;
9438                 /*
9439                  * On Gen 8, SRM is now taking an extra dword to accommodate
9440                  * 48bits addresses, and we need a NOOP for the batch size to
9441                  * stay even.
9442                  */
9443                 if (IS_GEN8(dev))
9444                         len += 2;
9445         }
9446
9447         /*
9448          * BSpec MI_DISPLAY_FLIP for IVB:
9449          * "The full packet must be contained within the same cache line."
9450          *
9451          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9452          * cacheline, if we ever start emitting more commands before
9453          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9454          * then do the cacheline alignment, and finally emit the
9455          * MI_DISPLAY_FLIP.
9456          */
9457         ret = intel_ring_cacheline_align(ring);
9458         if (ret)
9459                 return ret;
9460
9461         ret = intel_ring_begin(ring, len);
9462         if (ret)
9463                 return ret;
9464
9465         /* Unmask the flip-done completion message. Note that the bspec says that
9466          * we should do this for both the BCS and RCS, and that we must not unmask
9467          * more than one flip event at any time (or ensure that one flip message
9468          * can be sent by waiting for flip-done prior to queueing new flips).
9469          * Experimentation says that BCS works despite DERRMR masking all
9470          * flip-done completion events and that unmasking all planes at once
9471          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9472          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9473          */
9474         if (ring->id == RCS) {
9475                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9476                 intel_ring_emit(ring, DERRMR);
9477                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9478                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9479                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9480                 if (IS_GEN8(dev))
9481                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9482                                               MI_SRM_LRM_GLOBAL_GTT);
9483                 else
9484                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9485                                               MI_SRM_LRM_GLOBAL_GTT);
9486                 intel_ring_emit(ring, DERRMR);
9487                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9488                 if (IS_GEN8(dev)) {
9489                         intel_ring_emit(ring, 0);
9490                         intel_ring_emit(ring, MI_NOOP);
9491                 }
9492         }
9493
9494         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9495         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9496         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9497         intel_ring_emit(ring, (MI_NOOP));
9498
9499         intel_mark_page_flip_active(intel_crtc);
9500         __intel_ring_advance(ring);
9501         return 0;
9502 }
9503
9504 static bool use_mmio_flip(struct intel_engine_cs *ring,
9505                           struct drm_i915_gem_object *obj)
9506 {
9507         /*
9508          * This is not being used for older platforms, because
9509          * non-availability of flip done interrupt forces us to use
9510          * CS flips. Older platforms derive flip done using some clever
9511          * tricks involving the flip_pending status bits and vblank irqs.
9512          * So using MMIO flips there would disrupt this mechanism.
9513          */
9514
9515         if (ring == NULL)
9516                 return true;
9517
9518         if (INTEL_INFO(ring->dev)->gen < 5)
9519                 return false;
9520
9521         if (i915.use_mmio_flip < 0)
9522                 return false;
9523         else if (i915.use_mmio_flip > 0)
9524                 return true;
9525         else if (i915.enable_execlists)
9526                 return true;
9527         else
9528                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9529 }
9530
9531 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9532 {
9533         struct drm_device *dev = intel_crtc->base.dev;
9534         struct drm_i915_private *dev_priv = dev->dev_private;
9535         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9536         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9537         struct drm_i915_gem_object *obj = intel_fb->obj;
9538         const enum pipe pipe = intel_crtc->pipe;
9539         u32 ctl, stride;
9540
9541         ctl = I915_READ(PLANE_CTL(pipe, 0));
9542         ctl &= ~PLANE_CTL_TILED_MASK;
9543         if (obj->tiling_mode == I915_TILING_X)
9544                 ctl |= PLANE_CTL_TILED_X;
9545
9546         /*
9547          * The stride is either expressed as a multiple of 64 bytes chunks for
9548          * linear buffers or in number of tiles for tiled buffers.
9549          */
9550         stride = fb->pitches[0] >> 6;
9551         if (obj->tiling_mode == I915_TILING_X)
9552                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9553
9554         /*
9555          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9556          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9557          */
9558         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9559         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9560
9561         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9562         POSTING_READ(PLANE_SURF(pipe, 0));
9563 }
9564
9565 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9566 {
9567         struct drm_device *dev = intel_crtc->base.dev;
9568         struct drm_i915_private *dev_priv = dev->dev_private;
9569         struct intel_framebuffer *intel_fb =
9570                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9571         struct drm_i915_gem_object *obj = intel_fb->obj;
9572         u32 dspcntr;
9573         u32 reg;
9574
9575         reg = DSPCNTR(intel_crtc->plane);
9576         dspcntr = I915_READ(reg);
9577
9578         if (obj->tiling_mode != I915_TILING_NONE)
9579                 dspcntr |= DISPPLANE_TILED;
9580         else
9581                 dspcntr &= ~DISPPLANE_TILED;
9582
9583         I915_WRITE(reg, dspcntr);
9584
9585         I915_WRITE(DSPSURF(intel_crtc->plane),
9586                    intel_crtc->unpin_work->gtt_offset);
9587         POSTING_READ(DSPSURF(intel_crtc->plane));
9588
9589 }
9590
9591 /*
9592  * XXX: This is the temporary way to update the plane registers until we get
9593  * around to using the usual plane update functions for MMIO flips
9594  */
9595 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9596 {
9597         struct drm_device *dev = intel_crtc->base.dev;
9598         bool atomic_update;
9599         u32 start_vbl_count;
9600
9601         intel_mark_page_flip_active(intel_crtc);
9602
9603         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9604
9605         if (INTEL_INFO(dev)->gen >= 9)
9606                 skl_do_mmio_flip(intel_crtc);
9607         else
9608                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9609                 ilk_do_mmio_flip(intel_crtc);
9610
9611         if (atomic_update)
9612                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9613 }
9614
9615 static void intel_mmio_flip_work_func(struct work_struct *work)
9616 {
9617         struct intel_crtc *crtc =
9618                 container_of(work, struct intel_crtc, mmio_flip.work);
9619         struct intel_mmio_flip *mmio_flip;
9620
9621         mmio_flip = &crtc->mmio_flip;
9622         if (mmio_flip->req)
9623                 WARN_ON(__i915_wait_request(mmio_flip->req,
9624                                             crtc->reset_counter,
9625                                             false, NULL, NULL) != 0);
9626
9627         intel_do_mmio_flip(crtc);
9628         if (mmio_flip->req) {
9629                 mutex_lock(&crtc->base.dev->struct_mutex);
9630                 i915_gem_request_assign(&mmio_flip->req, NULL);
9631                 mutex_unlock(&crtc->base.dev->struct_mutex);
9632         }
9633 }
9634
9635 static int intel_queue_mmio_flip(struct drm_device *dev,
9636                                  struct drm_crtc *crtc,
9637                                  struct drm_framebuffer *fb,
9638                                  struct drm_i915_gem_object *obj,
9639                                  struct intel_engine_cs *ring,
9640                                  uint32_t flags)
9641 {
9642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9643
9644         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9645                                 obj->last_write_req);
9646
9647         schedule_work(&intel_crtc->mmio_flip.work);
9648
9649         return 0;
9650 }
9651
9652 static int intel_default_queue_flip(struct drm_device *dev,
9653                                     struct drm_crtc *crtc,
9654                                     struct drm_framebuffer *fb,
9655                                     struct drm_i915_gem_object *obj,
9656                                     struct intel_engine_cs *ring,
9657                                     uint32_t flags)
9658 {
9659         return -ENODEV;
9660 }
9661
9662 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9663                                          struct drm_crtc *crtc)
9664 {
9665         struct drm_i915_private *dev_priv = dev->dev_private;
9666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9667         struct intel_unpin_work *work = intel_crtc->unpin_work;
9668         u32 addr;
9669
9670         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9671                 return true;
9672
9673         if (!work->enable_stall_check)
9674                 return false;
9675
9676         if (work->flip_ready_vblank == 0) {
9677                 if (work->flip_queued_req &&
9678                     !i915_gem_request_completed(work->flip_queued_req, true))
9679                         return false;
9680
9681                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9682         }
9683
9684         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9685                 return false;
9686
9687         /* Potential stall - if we see that the flip has happened,
9688          * assume a missed interrupt. */
9689         if (INTEL_INFO(dev)->gen >= 4)
9690                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9691         else
9692                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9693
9694         /* There is a potential issue here with a false positive after a flip
9695          * to the same address. We could address this by checking for a
9696          * non-incrementing frame counter.
9697          */
9698         return addr == work->gtt_offset;
9699 }
9700
9701 void intel_check_page_flip(struct drm_device *dev, int pipe)
9702 {
9703         struct drm_i915_private *dev_priv = dev->dev_private;
9704         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9706
9707         WARN_ON(!in_irq());
9708
9709         if (crtc == NULL)
9710                 return;
9711
9712         spin_lock(&dev->event_lock);
9713         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9714                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9715                          intel_crtc->unpin_work->flip_queued_vblank,
9716                          drm_vblank_count(dev, pipe));
9717                 page_flip_completed(intel_crtc);
9718         }
9719         spin_unlock(&dev->event_lock);
9720 }
9721
9722 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9723                                 struct drm_framebuffer *fb,
9724                                 struct drm_pending_vblank_event *event,
9725                                 uint32_t page_flip_flags)
9726 {
9727         struct drm_device *dev = crtc->dev;
9728         struct drm_i915_private *dev_priv = dev->dev_private;
9729         struct drm_framebuffer *old_fb = crtc->primary->fb;
9730         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9732         struct drm_plane *primary = crtc->primary;
9733         enum pipe pipe = intel_crtc->pipe;
9734         struct intel_unpin_work *work;
9735         struct intel_engine_cs *ring;
9736         int ret;
9737
9738         /*
9739          * drm_mode_page_flip_ioctl() should already catch this, but double
9740          * check to be safe.  In the future we may enable pageflipping from
9741          * a disabled primary plane.
9742          */
9743         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9744                 return -EBUSY;
9745
9746         /* Can't change pixel format via MI display flips. */
9747         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9748                 return -EINVAL;
9749
9750         /*
9751          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9752          * Note that pitch changes could also affect these register.
9753          */
9754         if (INTEL_INFO(dev)->gen > 3 &&
9755             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9756              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9757                 return -EINVAL;
9758
9759         if (i915_terminally_wedged(&dev_priv->gpu_error))
9760                 goto out_hang;
9761
9762         work = kzalloc(sizeof(*work), GFP_KERNEL);
9763         if (work == NULL)
9764                 return -ENOMEM;
9765
9766         work->event = event;
9767         work->crtc = crtc;
9768         work->old_fb = old_fb;
9769         INIT_WORK(&work->work, intel_unpin_work_fn);
9770
9771         ret = drm_crtc_vblank_get(crtc);
9772         if (ret)
9773                 goto free_work;
9774
9775         /* We borrow the event spin lock for protecting unpin_work */
9776         spin_lock_irq(&dev->event_lock);
9777         if (intel_crtc->unpin_work) {
9778                 /* Before declaring the flip queue wedged, check if
9779                  * the hardware completed the operation behind our backs.
9780                  */
9781                 if (__intel_pageflip_stall_check(dev, crtc)) {
9782                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9783                         page_flip_completed(intel_crtc);
9784                 } else {
9785                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9786                         spin_unlock_irq(&dev->event_lock);
9787
9788                         drm_crtc_vblank_put(crtc);
9789                         kfree(work);
9790                         return -EBUSY;
9791                 }
9792         }
9793         intel_crtc->unpin_work = work;
9794         spin_unlock_irq(&dev->event_lock);
9795
9796         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9797                 flush_workqueue(dev_priv->wq);
9798
9799         ret = i915_mutex_lock_interruptible(dev);
9800         if (ret)
9801                 goto cleanup;
9802
9803         /* Reference the objects for the scheduled work. */
9804         drm_framebuffer_reference(work->old_fb);
9805         drm_gem_object_reference(&obj->base);
9806
9807         crtc->primary->fb = fb;
9808         update_state_fb(crtc->primary);
9809
9810         work->pending_flip_obj = obj;
9811
9812         atomic_inc(&intel_crtc->unpin_work_count);
9813         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9814
9815         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9816                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9817
9818         if (IS_VALLEYVIEW(dev)) {
9819                 ring = &dev_priv->ring[BCS];
9820                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9821                         /* vlv: DISPLAY_FLIP fails to change tiling */
9822                         ring = NULL;
9823         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9824                 ring = &dev_priv->ring[BCS];
9825         } else if (INTEL_INFO(dev)->gen >= 7) {
9826                 ring = i915_gem_request_get_ring(obj->last_read_req);
9827                 if (ring == NULL || ring->id != RCS)
9828                         ring = &dev_priv->ring[BCS];
9829         } else {
9830                 ring = &dev_priv->ring[RCS];
9831         }
9832
9833         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9834         if (ret)
9835                 goto cleanup_pending;
9836
9837         work->gtt_offset =
9838                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9839
9840         if (use_mmio_flip(ring, obj)) {
9841                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9842                                             page_flip_flags);
9843                 if (ret)
9844                         goto cleanup_unpin;
9845
9846                 i915_gem_request_assign(&work->flip_queued_req,
9847                                         obj->last_write_req);
9848         } else {
9849                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9850                                                    page_flip_flags);
9851                 if (ret)
9852                         goto cleanup_unpin;
9853
9854                 i915_gem_request_assign(&work->flip_queued_req,
9855                                         intel_ring_get_request(ring));
9856         }
9857
9858         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9859         work->enable_stall_check = true;
9860
9861         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9862                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9863
9864         intel_fbc_disable(dev);
9865         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9866         mutex_unlock(&dev->struct_mutex);
9867
9868         trace_i915_flip_request(intel_crtc->plane, obj);
9869
9870         return 0;
9871
9872 cleanup_unpin:
9873         intel_unpin_fb_obj(obj);
9874 cleanup_pending:
9875         atomic_dec(&intel_crtc->unpin_work_count);
9876         crtc->primary->fb = old_fb;
9877         update_state_fb(crtc->primary);
9878         drm_framebuffer_unreference(work->old_fb);
9879         drm_gem_object_unreference(&obj->base);
9880         mutex_unlock(&dev->struct_mutex);
9881
9882 cleanup:
9883         spin_lock_irq(&dev->event_lock);
9884         intel_crtc->unpin_work = NULL;
9885         spin_unlock_irq(&dev->event_lock);
9886
9887         drm_crtc_vblank_put(crtc);
9888 free_work:
9889         kfree(work);
9890
9891         if (ret == -EIO) {
9892 out_hang:
9893                 ret = intel_plane_restore(primary);
9894                 if (ret == 0 && event) {
9895                         spin_lock_irq(&dev->event_lock);
9896                         drm_send_vblank_event(dev, pipe, event);
9897                         spin_unlock_irq(&dev->event_lock);
9898                 }
9899         }
9900         return ret;
9901 }
9902
9903 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9904         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9905         .load_lut = intel_crtc_load_lut,
9906         .atomic_begin = intel_begin_crtc_commit,
9907         .atomic_flush = intel_finish_crtc_commit,
9908 };
9909
9910 /**
9911  * intel_modeset_update_staged_output_state
9912  *
9913  * Updates the staged output configuration state, e.g. after we've read out the
9914  * current hw state.
9915  */
9916 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9917 {
9918         struct intel_crtc *crtc;
9919         struct intel_encoder *encoder;
9920         struct intel_connector *connector;
9921
9922         list_for_each_entry(connector, &dev->mode_config.connector_list,
9923                             base.head) {
9924                 connector->new_encoder =
9925                         to_intel_encoder(connector->base.encoder);
9926         }
9927
9928         for_each_intel_encoder(dev, encoder) {
9929                 encoder->new_crtc =
9930                         to_intel_crtc(encoder->base.crtc);
9931         }
9932
9933         for_each_intel_crtc(dev, crtc) {
9934                 crtc->new_enabled = crtc->base.state->enable;
9935
9936                 if (crtc->new_enabled)
9937                         crtc->new_config = crtc->config;
9938                 else
9939                         crtc->new_config = NULL;
9940         }
9941 }
9942
9943 /**
9944  * intel_modeset_commit_output_state
9945  *
9946  * This function copies the stage display pipe configuration to the real one.
9947  */
9948 static void intel_modeset_commit_output_state(struct drm_device *dev)
9949 {
9950         struct intel_crtc *crtc;
9951         struct intel_encoder *encoder;
9952         struct intel_connector *connector;
9953
9954         list_for_each_entry(connector, &dev->mode_config.connector_list,
9955                             base.head) {
9956                 connector->base.encoder = &connector->new_encoder->base;
9957         }
9958
9959         for_each_intel_encoder(dev, encoder) {
9960                 encoder->base.crtc = &encoder->new_crtc->base;
9961         }
9962
9963         for_each_intel_crtc(dev, crtc) {
9964                 crtc->base.state->enable = crtc->new_enabled;
9965                 crtc->base.enabled = crtc->new_enabled;
9966         }
9967 }
9968
9969 static void
9970 connected_sink_compute_bpp(struct intel_connector *connector,
9971                            struct intel_crtc_state *pipe_config)
9972 {
9973         int bpp = pipe_config->pipe_bpp;
9974
9975         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9976                 connector->base.base.id,
9977                 connector->base.name);
9978
9979         /* Don't use an invalid EDID bpc value */
9980         if (connector->base.display_info.bpc &&
9981             connector->base.display_info.bpc * 3 < bpp) {
9982                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9983                               bpp, connector->base.display_info.bpc*3);
9984                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9985         }
9986
9987         /* Clamp bpp to 8 on screens without EDID 1.4 */
9988         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9989                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9990                               bpp);
9991                 pipe_config->pipe_bpp = 24;
9992         }
9993 }
9994
9995 static int
9996 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9997                           struct drm_framebuffer *fb,
9998                           struct intel_crtc_state *pipe_config)
9999 {
10000         struct drm_device *dev = crtc->base.dev;
10001         struct intel_connector *connector;
10002         int bpp;
10003
10004         switch (fb->pixel_format) {
10005         case DRM_FORMAT_C8:
10006                 bpp = 8*3; /* since we go through a colormap */
10007                 break;
10008         case DRM_FORMAT_XRGB1555:
10009         case DRM_FORMAT_ARGB1555:
10010                 /* checked in intel_framebuffer_init already */
10011                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10012                         return -EINVAL;
10013         case DRM_FORMAT_RGB565:
10014                 bpp = 6*3; /* min is 18bpp */
10015                 break;
10016         case DRM_FORMAT_XBGR8888:
10017         case DRM_FORMAT_ABGR8888:
10018                 /* checked in intel_framebuffer_init already */
10019                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10020                         return -EINVAL;
10021         case DRM_FORMAT_XRGB8888:
10022         case DRM_FORMAT_ARGB8888:
10023                 bpp = 8*3;
10024                 break;
10025         case DRM_FORMAT_XRGB2101010:
10026         case DRM_FORMAT_ARGB2101010:
10027         case DRM_FORMAT_XBGR2101010:
10028         case DRM_FORMAT_ABGR2101010:
10029                 /* checked in intel_framebuffer_init already */
10030                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10031                         return -EINVAL;
10032                 bpp = 10*3;
10033                 break;
10034         /* TODO: gen4+ supports 16 bpc floating point, too. */
10035         default:
10036                 DRM_DEBUG_KMS("unsupported depth\n");
10037                 return -EINVAL;
10038         }
10039
10040         pipe_config->pipe_bpp = bpp;
10041
10042         /* Clamp display bpp to EDID value */
10043         list_for_each_entry(connector, &dev->mode_config.connector_list,
10044                             base.head) {
10045                 if (!connector->new_encoder ||
10046                     connector->new_encoder->new_crtc != crtc)
10047                         continue;
10048
10049                 connected_sink_compute_bpp(connector, pipe_config);
10050         }
10051
10052         return bpp;
10053 }
10054
10055 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10056 {
10057         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10058                         "type: 0x%x flags: 0x%x\n",
10059                 mode->crtc_clock,
10060                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10061                 mode->crtc_hsync_end, mode->crtc_htotal,
10062                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10063                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10064 }
10065
10066 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10067                                    struct intel_crtc_state *pipe_config,
10068                                    const char *context)
10069 {
10070         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10071                       context, pipe_name(crtc->pipe));
10072
10073         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10074         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10075                       pipe_config->pipe_bpp, pipe_config->dither);
10076         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10077                       pipe_config->has_pch_encoder,
10078                       pipe_config->fdi_lanes,
10079                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10080                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10081                       pipe_config->fdi_m_n.tu);
10082         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10083                       pipe_config->has_dp_encoder,
10084                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10085                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10086                       pipe_config->dp_m_n.tu);
10087
10088         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10089                       pipe_config->has_dp_encoder,
10090                       pipe_config->dp_m2_n2.gmch_m,
10091                       pipe_config->dp_m2_n2.gmch_n,
10092                       pipe_config->dp_m2_n2.link_m,
10093                       pipe_config->dp_m2_n2.link_n,
10094                       pipe_config->dp_m2_n2.tu);
10095
10096         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10097                       pipe_config->has_audio,
10098                       pipe_config->has_infoframe);
10099
10100         DRM_DEBUG_KMS("requested mode:\n");
10101         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10102         DRM_DEBUG_KMS("adjusted mode:\n");
10103         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10104         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10105         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10106         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10107                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10108         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10109                       pipe_config->gmch_pfit.control,
10110                       pipe_config->gmch_pfit.pgm_ratios,
10111                       pipe_config->gmch_pfit.lvds_border_bits);
10112         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10113                       pipe_config->pch_pfit.pos,
10114                       pipe_config->pch_pfit.size,
10115                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10116         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10117         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10118 }
10119
10120 static bool encoders_cloneable(const struct intel_encoder *a,
10121                                const struct intel_encoder *b)
10122 {
10123         /* masks could be asymmetric, so check both ways */
10124         return a == b || (a->cloneable & (1 << b->type) &&
10125                           b->cloneable & (1 << a->type));
10126 }
10127
10128 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10129                                          struct intel_encoder *encoder)
10130 {
10131         struct drm_device *dev = crtc->base.dev;
10132         struct intel_encoder *source_encoder;
10133
10134         for_each_intel_encoder(dev, source_encoder) {
10135                 if (source_encoder->new_crtc != crtc)
10136                         continue;
10137
10138                 if (!encoders_cloneable(encoder, source_encoder))
10139                         return false;
10140         }
10141
10142         return true;
10143 }
10144
10145 static bool check_encoder_cloning(struct intel_crtc *crtc)
10146 {
10147         struct drm_device *dev = crtc->base.dev;
10148         struct intel_encoder *encoder;
10149
10150         for_each_intel_encoder(dev, encoder) {
10151                 if (encoder->new_crtc != crtc)
10152                         continue;
10153
10154                 if (!check_single_encoder_cloning(crtc, encoder))
10155                         return false;
10156         }
10157
10158         return true;
10159 }
10160
10161 static bool check_digital_port_conflicts(struct drm_device *dev)
10162 {
10163         struct intel_connector *connector;
10164         unsigned int used_ports = 0;
10165
10166         /*
10167          * Walk the connector list instead of the encoder
10168          * list to detect the problem on ddi platforms
10169          * where there's just one encoder per digital port.
10170          */
10171         list_for_each_entry(connector,
10172                             &dev->mode_config.connector_list, base.head) {
10173                 struct intel_encoder *encoder = connector->new_encoder;
10174
10175                 if (!encoder)
10176                         continue;
10177
10178                 WARN_ON(!encoder->new_crtc);
10179
10180                 switch (encoder->type) {
10181                         unsigned int port_mask;
10182                 case INTEL_OUTPUT_UNKNOWN:
10183                         if (WARN_ON(!HAS_DDI(dev)))
10184                                 break;
10185                 case INTEL_OUTPUT_DISPLAYPORT:
10186                 case INTEL_OUTPUT_HDMI:
10187                 case INTEL_OUTPUT_EDP:
10188                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10189
10190                         /* the same port mustn't appear more than once */
10191                         if (used_ports & port_mask)
10192                                 return false;
10193
10194                         used_ports |= port_mask;
10195                 default:
10196                         break;
10197                 }
10198         }
10199
10200         return true;
10201 }
10202
10203 static struct intel_crtc_state *
10204 intel_modeset_pipe_config(struct drm_crtc *crtc,
10205                           struct drm_framebuffer *fb,
10206                           struct drm_display_mode *mode)
10207 {
10208         struct drm_device *dev = crtc->dev;
10209         struct intel_encoder *encoder;
10210         struct intel_crtc_state *pipe_config;
10211         int plane_bpp, ret = -EINVAL;
10212         bool retry = true;
10213
10214         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10215                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10216                 return ERR_PTR(-EINVAL);
10217         }
10218
10219         if (!check_digital_port_conflicts(dev)) {
10220                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10221                 return ERR_PTR(-EINVAL);
10222         }
10223
10224         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10225         if (!pipe_config)
10226                 return ERR_PTR(-ENOMEM);
10227
10228         pipe_config->base.crtc = crtc;
10229         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10230         drm_mode_copy(&pipe_config->base.mode, mode);
10231
10232         pipe_config->cpu_transcoder =
10233                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10234         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10235
10236         /*
10237          * Sanitize sync polarity flags based on requested ones. If neither
10238          * positive or negative polarity is requested, treat this as meaning
10239          * negative polarity.
10240          */
10241         if (!(pipe_config->base.adjusted_mode.flags &
10242               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10243                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10244
10245         if (!(pipe_config->base.adjusted_mode.flags &
10246               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10247                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10248
10249         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10250          * plane pixel format and any sink constraints into account. Returns the
10251          * source plane bpp so that dithering can be selected on mismatches
10252          * after encoders and crtc also have had their say. */
10253         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10254                                               fb, pipe_config);
10255         if (plane_bpp < 0)
10256                 goto fail;
10257
10258         /*
10259          * Determine the real pipe dimensions. Note that stereo modes can
10260          * increase the actual pipe size due to the frame doubling and
10261          * insertion of additional space for blanks between the frame. This
10262          * is stored in the crtc timings. We use the requested mode to do this
10263          * computation to clearly distinguish it from the adjusted mode, which
10264          * can be changed by the connectors in the below retry loop.
10265          */
10266         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10267                                &pipe_config->pipe_src_w,
10268                                &pipe_config->pipe_src_h);
10269
10270 encoder_retry:
10271         /* Ensure the port clock defaults are reset when retrying. */
10272         pipe_config->port_clock = 0;
10273         pipe_config->pixel_multiplier = 1;
10274
10275         /* Fill in default crtc timings, allow encoders to overwrite them. */
10276         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10277                               CRTC_STEREO_DOUBLE);
10278
10279         /* Pass our mode to the connectors and the CRTC to give them a chance to
10280          * adjust it according to limitations or connector properties, and also
10281          * a chance to reject the mode entirely.
10282          */
10283         for_each_intel_encoder(dev, encoder) {
10284
10285                 if (&encoder->new_crtc->base != crtc)
10286                         continue;
10287
10288                 if (!(encoder->compute_config(encoder, pipe_config))) {
10289                         DRM_DEBUG_KMS("Encoder config failure\n");
10290                         goto fail;
10291                 }
10292         }
10293
10294         /* Set default port clock if not overwritten by the encoder. Needs to be
10295          * done afterwards in case the encoder adjusts the mode. */
10296         if (!pipe_config->port_clock)
10297                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10298                         * pipe_config->pixel_multiplier;
10299
10300         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10301         if (ret < 0) {
10302                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10303                 goto fail;
10304         }
10305
10306         if (ret == RETRY) {
10307                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10308                         ret = -EINVAL;
10309                         goto fail;
10310                 }
10311
10312                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10313                 retry = false;
10314                 goto encoder_retry;
10315         }
10316
10317         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10318         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10319                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10320
10321         return pipe_config;
10322 fail:
10323         kfree(pipe_config);
10324         return ERR_PTR(ret);
10325 }
10326
10327 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10328  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10329 static void
10330 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10331                              unsigned *prepare_pipes, unsigned *disable_pipes)
10332 {
10333         struct intel_crtc *intel_crtc;
10334         struct drm_device *dev = crtc->dev;
10335         struct intel_encoder *encoder;
10336         struct intel_connector *connector;
10337         struct drm_crtc *tmp_crtc;
10338
10339         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10340
10341         /* Check which crtcs have changed outputs connected to them, these need
10342          * to be part of the prepare_pipes mask. We don't (yet) support global
10343          * modeset across multiple crtcs, so modeset_pipes will only have one
10344          * bit set at most. */
10345         list_for_each_entry(connector, &dev->mode_config.connector_list,
10346                             base.head) {
10347                 if (connector->base.encoder == &connector->new_encoder->base)
10348                         continue;
10349
10350                 if (connector->base.encoder) {
10351                         tmp_crtc = connector->base.encoder->crtc;
10352
10353                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10354                 }
10355
10356                 if (connector->new_encoder)
10357                         *prepare_pipes |=
10358                                 1 << connector->new_encoder->new_crtc->pipe;
10359         }
10360
10361         for_each_intel_encoder(dev, encoder) {
10362                 if (encoder->base.crtc == &encoder->new_crtc->base)
10363                         continue;
10364
10365                 if (encoder->base.crtc) {
10366                         tmp_crtc = encoder->base.crtc;
10367
10368                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10369                 }
10370
10371                 if (encoder->new_crtc)
10372                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10373         }
10374
10375         /* Check for pipes that will be enabled/disabled ... */
10376         for_each_intel_crtc(dev, intel_crtc) {
10377                 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10378                         continue;
10379
10380                 if (!intel_crtc->new_enabled)
10381                         *disable_pipes |= 1 << intel_crtc->pipe;
10382                 else
10383                         *prepare_pipes |= 1 << intel_crtc->pipe;
10384         }
10385
10386
10387         /* set_mode is also used to update properties on life display pipes. */
10388         intel_crtc = to_intel_crtc(crtc);
10389         if (intel_crtc->new_enabled)
10390                 *prepare_pipes |= 1 << intel_crtc->pipe;
10391
10392         /*
10393          * For simplicity do a full modeset on any pipe where the output routing
10394          * changed. We could be more clever, but that would require us to be
10395          * more careful with calling the relevant encoder->mode_set functions.
10396          */
10397         if (*prepare_pipes)
10398                 *modeset_pipes = *prepare_pipes;
10399
10400         /* ... and mask these out. */
10401         *modeset_pipes &= ~(*disable_pipes);
10402         *prepare_pipes &= ~(*disable_pipes);
10403
10404         /*
10405          * HACK: We don't (yet) fully support global modesets. intel_set_config
10406          * obies this rule, but the modeset restore mode of
10407          * intel_modeset_setup_hw_state does not.
10408          */
10409         *modeset_pipes &= 1 << intel_crtc->pipe;
10410         *prepare_pipes &= 1 << intel_crtc->pipe;
10411
10412         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10413                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10414 }
10415
10416 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10417 {
10418         struct drm_encoder *encoder;
10419         struct drm_device *dev = crtc->dev;
10420
10421         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10422                 if (encoder->crtc == crtc)
10423                         return true;
10424
10425         return false;
10426 }
10427
10428 static void
10429 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10430 {
10431         struct drm_i915_private *dev_priv = dev->dev_private;
10432         struct intel_encoder *intel_encoder;
10433         struct intel_crtc *intel_crtc;
10434         struct drm_connector *connector;
10435
10436         intel_shared_dpll_commit(dev_priv);
10437
10438         for_each_intel_encoder(dev, intel_encoder) {
10439                 if (!intel_encoder->base.crtc)
10440                         continue;
10441
10442                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10443
10444                 if (prepare_pipes & (1 << intel_crtc->pipe))
10445                         intel_encoder->connectors_active = false;
10446         }
10447
10448         intel_modeset_commit_output_state(dev);
10449
10450         /* Double check state. */
10451         for_each_intel_crtc(dev, intel_crtc) {
10452                 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10453                 WARN_ON(intel_crtc->new_config &&
10454                         intel_crtc->new_config != intel_crtc->config);
10455                 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10456         }
10457
10458         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10459                 if (!connector->encoder || !connector->encoder->crtc)
10460                         continue;
10461
10462                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10463
10464                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10465                         struct drm_property *dpms_property =
10466                                 dev->mode_config.dpms_property;
10467
10468                         connector->dpms = DRM_MODE_DPMS_ON;
10469                         drm_object_property_set_value(&connector->base,
10470                                                          dpms_property,
10471                                                          DRM_MODE_DPMS_ON);
10472
10473                         intel_encoder = to_intel_encoder(connector->encoder);
10474                         intel_encoder->connectors_active = true;
10475                 }
10476         }
10477
10478 }
10479
10480 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10481 {
10482         int diff;
10483
10484         if (clock1 == clock2)
10485                 return true;
10486
10487         if (!clock1 || !clock2)
10488                 return false;
10489
10490         diff = abs(clock1 - clock2);
10491
10492         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10493                 return true;
10494
10495         return false;
10496 }
10497
10498 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10499         list_for_each_entry((intel_crtc), \
10500                             &(dev)->mode_config.crtc_list, \
10501                             base.head) \
10502                 if (mask & (1 <<(intel_crtc)->pipe))
10503
10504 static bool
10505 intel_pipe_config_compare(struct drm_device *dev,
10506                           struct intel_crtc_state *current_config,
10507                           struct intel_crtc_state *pipe_config)
10508 {
10509 #define PIPE_CONF_CHECK_X(name) \
10510         if (current_config->name != pipe_config->name) { \
10511                 DRM_ERROR("mismatch in " #name " " \
10512                           "(expected 0x%08x, found 0x%08x)\n", \
10513                           current_config->name, \
10514                           pipe_config->name); \
10515                 return false; \
10516         }
10517
10518 #define PIPE_CONF_CHECK_I(name) \
10519         if (current_config->name != pipe_config->name) { \
10520                 DRM_ERROR("mismatch in " #name " " \
10521                           "(expected %i, found %i)\n", \
10522                           current_config->name, \
10523                           pipe_config->name); \
10524                 return false; \
10525         }
10526
10527 /* This is required for BDW+ where there is only one set of registers for
10528  * switching between high and low RR.
10529  * This macro can be used whenever a comparison has to be made between one
10530  * hw state and multiple sw state variables.
10531  */
10532 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10533         if ((current_config->name != pipe_config->name) && \
10534                 (current_config->alt_name != pipe_config->name)) { \
10535                         DRM_ERROR("mismatch in " #name " " \
10536                                   "(expected %i or %i, found %i)\n", \
10537                                   current_config->name, \
10538                                   current_config->alt_name, \
10539                                   pipe_config->name); \
10540                         return false; \
10541         }
10542
10543 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10544         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10545                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10546                           "(expected %i, found %i)\n", \
10547                           current_config->name & (mask), \
10548                           pipe_config->name & (mask)); \
10549                 return false; \
10550         }
10551
10552 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10553         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10554                 DRM_ERROR("mismatch in " #name " " \
10555                           "(expected %i, found %i)\n", \
10556                           current_config->name, \
10557                           pipe_config->name); \
10558                 return false; \
10559         }
10560
10561 #define PIPE_CONF_QUIRK(quirk)  \
10562         ((current_config->quirks | pipe_config->quirks) & (quirk))
10563
10564         PIPE_CONF_CHECK_I(cpu_transcoder);
10565
10566         PIPE_CONF_CHECK_I(has_pch_encoder);
10567         PIPE_CONF_CHECK_I(fdi_lanes);
10568         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10569         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10570         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10571         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10572         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10573
10574         PIPE_CONF_CHECK_I(has_dp_encoder);
10575
10576         if (INTEL_INFO(dev)->gen < 8) {
10577                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10578                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10579                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10580                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10581                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10582
10583                 if (current_config->has_drrs) {
10584                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10585                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10586                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10587                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10588                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10589                 }
10590         } else {
10591                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10592                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10593                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10594                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10595                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10596         }
10597
10598         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10599         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10600         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10601         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10602         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10603         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10604
10605         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10606         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10607         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10608         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10609         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10610         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10611
10612         PIPE_CONF_CHECK_I(pixel_multiplier);
10613         PIPE_CONF_CHECK_I(has_hdmi_sink);
10614         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10615             IS_VALLEYVIEW(dev))
10616                 PIPE_CONF_CHECK_I(limited_color_range);
10617         PIPE_CONF_CHECK_I(has_infoframe);
10618
10619         PIPE_CONF_CHECK_I(has_audio);
10620
10621         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10622                               DRM_MODE_FLAG_INTERLACE);
10623
10624         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10625                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10626                                       DRM_MODE_FLAG_PHSYNC);
10627                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10628                                       DRM_MODE_FLAG_NHSYNC);
10629                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10630                                       DRM_MODE_FLAG_PVSYNC);
10631                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10632                                       DRM_MODE_FLAG_NVSYNC);
10633         }
10634
10635         PIPE_CONF_CHECK_I(pipe_src_w);
10636         PIPE_CONF_CHECK_I(pipe_src_h);
10637
10638         /*
10639          * FIXME: BIOS likes to set up a cloned config with lvds+external
10640          * screen. Since we don't yet re-compute the pipe config when moving
10641          * just the lvds port away to another pipe the sw tracking won't match.
10642          *
10643          * Proper atomic modesets with recomputed global state will fix this.
10644          * Until then just don't check gmch state for inherited modes.
10645          */
10646         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10647                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10648                 /* pfit ratios are autocomputed by the hw on gen4+ */
10649                 if (INTEL_INFO(dev)->gen < 4)
10650                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10651                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10652         }
10653
10654         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10655         if (current_config->pch_pfit.enabled) {
10656                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10657                 PIPE_CONF_CHECK_I(pch_pfit.size);
10658         }
10659
10660         /* BDW+ don't expose a synchronous way to read the state */
10661         if (IS_HASWELL(dev))
10662                 PIPE_CONF_CHECK_I(ips_enabled);
10663
10664         PIPE_CONF_CHECK_I(double_wide);
10665
10666         PIPE_CONF_CHECK_X(ddi_pll_sel);
10667
10668         PIPE_CONF_CHECK_I(shared_dpll);
10669         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10670         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10671         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10672         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10673         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10674         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10675         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10676         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10677
10678         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10679                 PIPE_CONF_CHECK_I(pipe_bpp);
10680
10681         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10682         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10683
10684 #undef PIPE_CONF_CHECK_X
10685 #undef PIPE_CONF_CHECK_I
10686 #undef PIPE_CONF_CHECK_I_ALT
10687 #undef PIPE_CONF_CHECK_FLAGS
10688 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10689 #undef PIPE_CONF_QUIRK
10690
10691         return true;
10692 }
10693
10694 static void check_wm_state(struct drm_device *dev)
10695 {
10696         struct drm_i915_private *dev_priv = dev->dev_private;
10697         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10698         struct intel_crtc *intel_crtc;
10699         int plane;
10700
10701         if (INTEL_INFO(dev)->gen < 9)
10702                 return;
10703
10704         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10705         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10706
10707         for_each_intel_crtc(dev, intel_crtc) {
10708                 struct skl_ddb_entry *hw_entry, *sw_entry;
10709                 const enum pipe pipe = intel_crtc->pipe;
10710
10711                 if (!intel_crtc->active)
10712                         continue;
10713
10714                 /* planes */
10715                 for_each_plane(pipe, plane) {
10716                         hw_entry = &hw_ddb.plane[pipe][plane];
10717                         sw_entry = &sw_ddb->plane[pipe][plane];
10718
10719                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10720                                 continue;
10721
10722                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10723                                   "(expected (%u,%u), found (%u,%u))\n",
10724                                   pipe_name(pipe), plane + 1,
10725                                   sw_entry->start, sw_entry->end,
10726                                   hw_entry->start, hw_entry->end);
10727                 }
10728
10729                 /* cursor */
10730                 hw_entry = &hw_ddb.cursor[pipe];
10731                 sw_entry = &sw_ddb->cursor[pipe];
10732
10733                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10734                         continue;
10735
10736                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10737                           "(expected (%u,%u), found (%u,%u))\n",
10738                           pipe_name(pipe),
10739                           sw_entry->start, sw_entry->end,
10740                           hw_entry->start, hw_entry->end);
10741         }
10742 }
10743
10744 static void
10745 check_connector_state(struct drm_device *dev)
10746 {
10747         struct intel_connector *connector;
10748
10749         list_for_each_entry(connector, &dev->mode_config.connector_list,
10750                             base.head) {
10751                 /* This also checks the encoder/connector hw state with the
10752                  * ->get_hw_state callbacks. */
10753                 intel_connector_check_state(connector);
10754
10755                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10756                      "connector's staged encoder doesn't match current encoder\n");
10757         }
10758 }
10759
10760 static void
10761 check_encoder_state(struct drm_device *dev)
10762 {
10763         struct intel_encoder *encoder;
10764         struct intel_connector *connector;
10765
10766         for_each_intel_encoder(dev, encoder) {
10767                 bool enabled = false;
10768                 bool active = false;
10769                 enum pipe pipe, tracked_pipe;
10770
10771                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10772                               encoder->base.base.id,
10773                               encoder->base.name);
10774
10775                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10776                      "encoder's stage crtc doesn't match current crtc\n");
10777                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10778                      "encoder's active_connectors set, but no crtc\n");
10779
10780                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10781                                     base.head) {
10782                         if (connector->base.encoder != &encoder->base)
10783                                 continue;
10784                         enabled = true;
10785                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10786                                 active = true;
10787                 }
10788                 /*
10789                  * for MST connectors if we unplug the connector is gone
10790                  * away but the encoder is still connected to a crtc
10791                  * until a modeset happens in response to the hotplug.
10792                  */
10793                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10794                         continue;
10795
10796                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10797                      "encoder's enabled state mismatch "
10798                      "(expected %i, found %i)\n",
10799                      !!encoder->base.crtc, enabled);
10800                 I915_STATE_WARN(active && !encoder->base.crtc,
10801                      "active encoder with no crtc\n");
10802
10803                 I915_STATE_WARN(encoder->connectors_active != active,
10804                      "encoder's computed active state doesn't match tracked active state "
10805                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10806
10807                 active = encoder->get_hw_state(encoder, &pipe);
10808                 I915_STATE_WARN(active != encoder->connectors_active,
10809                      "encoder's hw state doesn't match sw tracking "
10810                      "(expected %i, found %i)\n",
10811                      encoder->connectors_active, active);
10812
10813                 if (!encoder->base.crtc)
10814                         continue;
10815
10816                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10817                 I915_STATE_WARN(active && pipe != tracked_pipe,
10818                      "active encoder's pipe doesn't match"
10819                      "(expected %i, found %i)\n",
10820                      tracked_pipe, pipe);
10821
10822         }
10823 }
10824
10825 static void
10826 check_crtc_state(struct drm_device *dev)
10827 {
10828         struct drm_i915_private *dev_priv = dev->dev_private;
10829         struct intel_crtc *crtc;
10830         struct intel_encoder *encoder;
10831         struct intel_crtc_state pipe_config;
10832
10833         for_each_intel_crtc(dev, crtc) {
10834                 bool enabled = false;
10835                 bool active = false;
10836
10837                 memset(&pipe_config, 0, sizeof(pipe_config));
10838
10839                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10840                               crtc->base.base.id);
10841
10842                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10843                      "active crtc, but not enabled in sw tracking\n");
10844
10845                 for_each_intel_encoder(dev, encoder) {
10846                         if (encoder->base.crtc != &crtc->base)
10847                                 continue;
10848                         enabled = true;
10849                         if (encoder->connectors_active)
10850                                 active = true;
10851                 }
10852
10853                 I915_STATE_WARN(active != crtc->active,
10854                      "crtc's computed active state doesn't match tracked active state "
10855                      "(expected %i, found %i)\n", active, crtc->active);
10856                 I915_STATE_WARN(enabled != crtc->base.state->enable,
10857                      "crtc's computed enabled state doesn't match tracked enabled state "
10858                      "(expected %i, found %i)\n", enabled,
10859                                 crtc->base.state->enable);
10860
10861                 active = dev_priv->display.get_pipe_config(crtc,
10862                                                            &pipe_config);
10863
10864                 /* hw state is inconsistent with the pipe quirk */
10865                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10866                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10867                         active = crtc->active;
10868
10869                 for_each_intel_encoder(dev, encoder) {
10870                         enum pipe pipe;
10871                         if (encoder->base.crtc != &crtc->base)
10872                                 continue;
10873                         if (encoder->get_hw_state(encoder, &pipe))
10874                                 encoder->get_config(encoder, &pipe_config);
10875                 }
10876
10877                 I915_STATE_WARN(crtc->active != active,
10878                      "crtc active state doesn't match with hw state "
10879                      "(expected %i, found %i)\n", crtc->active, active);
10880
10881                 if (active &&
10882                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10883                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
10884                         intel_dump_pipe_config(crtc, &pipe_config,
10885                                                "[hw state]");
10886                         intel_dump_pipe_config(crtc, crtc->config,
10887                                                "[sw state]");
10888                 }
10889         }
10890 }
10891
10892 static void
10893 check_shared_dpll_state(struct drm_device *dev)
10894 {
10895         struct drm_i915_private *dev_priv = dev->dev_private;
10896         struct intel_crtc *crtc;
10897         struct intel_dpll_hw_state dpll_hw_state;
10898         int i;
10899
10900         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10901                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10902                 int enabled_crtcs = 0, active_crtcs = 0;
10903                 bool active;
10904
10905                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10906
10907                 DRM_DEBUG_KMS("%s\n", pll->name);
10908
10909                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10910
10911                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10912                      "more active pll users than references: %i vs %i\n",
10913                      pll->active, hweight32(pll->config.crtc_mask));
10914                 I915_STATE_WARN(pll->active && !pll->on,
10915                      "pll in active use but not on in sw tracking\n");
10916                 I915_STATE_WARN(pll->on && !pll->active,
10917                      "pll in on but not on in use in sw tracking\n");
10918                 I915_STATE_WARN(pll->on != active,
10919                      "pll on state mismatch (expected %i, found %i)\n",
10920                      pll->on, active);
10921
10922                 for_each_intel_crtc(dev, crtc) {
10923                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
10924                                 enabled_crtcs++;
10925                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10926                                 active_crtcs++;
10927                 }
10928                 I915_STATE_WARN(pll->active != active_crtcs,
10929                      "pll active crtcs mismatch (expected %i, found %i)\n",
10930                      pll->active, active_crtcs);
10931                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10932                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10933                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10934
10935                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10936                                        sizeof(dpll_hw_state)),
10937                      "pll hw state mismatch\n");
10938         }
10939 }
10940
10941 void
10942 intel_modeset_check_state(struct drm_device *dev)
10943 {
10944         check_wm_state(dev);
10945         check_connector_state(dev);
10946         check_encoder_state(dev);
10947         check_crtc_state(dev);
10948         check_shared_dpll_state(dev);
10949 }
10950
10951 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10952                                      int dotclock)
10953 {
10954         /*
10955          * FDI already provided one idea for the dotclock.
10956          * Yell if the encoder disagrees.
10957          */
10958         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10959              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10960              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10961 }
10962
10963 static void update_scanline_offset(struct intel_crtc *crtc)
10964 {
10965         struct drm_device *dev = crtc->base.dev;
10966
10967         /*
10968          * The scanline counter increments at the leading edge of hsync.
10969          *
10970          * On most platforms it starts counting from vtotal-1 on the
10971          * first active line. That means the scanline counter value is
10972          * always one less than what we would expect. Ie. just after
10973          * start of vblank, which also occurs at start of hsync (on the
10974          * last active line), the scanline counter will read vblank_start-1.
10975          *
10976          * On gen2 the scanline counter starts counting from 1 instead
10977          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10978          * to keep the value positive), instead of adding one.
10979          *
10980          * On HSW+ the behaviour of the scanline counter depends on the output
10981          * type. For DP ports it behaves like most other platforms, but on HDMI
10982          * there's an extra 1 line difference. So we need to add two instead of
10983          * one to the value.
10984          */
10985         if (IS_GEN2(dev)) {
10986                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10987                 int vtotal;
10988
10989                 vtotal = mode->crtc_vtotal;
10990                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10991                         vtotal /= 2;
10992
10993                 crtc->scanline_offset = vtotal - 1;
10994         } else if (HAS_DDI(dev) &&
10995                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10996                 crtc->scanline_offset = 2;
10997         } else
10998                 crtc->scanline_offset = 1;
10999 }
11000
11001 static struct intel_crtc_state *
11002 intel_modeset_compute_config(struct drm_crtc *crtc,
11003                              struct drm_display_mode *mode,
11004                              struct drm_framebuffer *fb,
11005                              unsigned *modeset_pipes,
11006                              unsigned *prepare_pipes,
11007                              unsigned *disable_pipes)
11008 {
11009         struct intel_crtc_state *pipe_config = NULL;
11010
11011         intel_modeset_affected_pipes(crtc, modeset_pipes,
11012                                      prepare_pipes, disable_pipes);
11013
11014         if ((*modeset_pipes) == 0)
11015                 goto out;
11016
11017         /*
11018          * Note this needs changes when we start tracking multiple modes
11019          * and crtcs.  At that point we'll need to compute the whole config
11020          * (i.e. one pipe_config for each crtc) rather than just the one
11021          * for this crtc.
11022          */
11023         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11024         if (IS_ERR(pipe_config)) {
11025                 goto out;
11026         }
11027         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11028                                "[modeset]");
11029
11030 out:
11031         return pipe_config;
11032 }
11033
11034 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11035                                        unsigned modeset_pipes,
11036                                        unsigned disable_pipes)
11037 {
11038         struct drm_i915_private *dev_priv = to_i915(dev);
11039         unsigned clear_pipes = modeset_pipes | disable_pipes;
11040         struct intel_crtc *intel_crtc;
11041         int ret = 0;
11042
11043         if (!dev_priv->display.crtc_compute_clock)
11044                 return 0;
11045
11046         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11047         if (ret)
11048                 goto done;
11049
11050         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11051                 struct intel_crtc_state *state = intel_crtc->new_config;
11052                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11053                                                            state);
11054                 if (ret) {
11055                         intel_shared_dpll_abort_config(dev_priv);
11056                         goto done;
11057                 }
11058         }
11059
11060 done:
11061         return ret;
11062 }
11063
11064 static int __intel_set_mode(struct drm_crtc *crtc,
11065                             struct drm_display_mode *mode,
11066                             int x, int y, struct drm_framebuffer *fb,
11067                             struct intel_crtc_state *pipe_config,
11068                             unsigned modeset_pipes,
11069                             unsigned prepare_pipes,
11070                             unsigned disable_pipes)
11071 {
11072         struct drm_device *dev = crtc->dev;
11073         struct drm_i915_private *dev_priv = dev->dev_private;
11074         struct drm_display_mode *saved_mode;
11075         struct intel_crtc *intel_crtc;
11076         int ret = 0;
11077
11078         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11079         if (!saved_mode)
11080                 return -ENOMEM;
11081
11082         *saved_mode = crtc->mode;
11083
11084         if (modeset_pipes)
11085                 to_intel_crtc(crtc)->new_config = pipe_config;
11086
11087         /*
11088          * See if the config requires any additional preparation, e.g.
11089          * to adjust global state with pipes off.  We need to do this
11090          * here so we can get the modeset_pipe updated config for the new
11091          * mode set on this crtc.  For other crtcs we need to use the
11092          * adjusted_mode bits in the crtc directly.
11093          */
11094         if (IS_VALLEYVIEW(dev)) {
11095                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11096
11097                 /* may have added more to prepare_pipes than we should */
11098                 prepare_pipes &= ~disable_pipes;
11099         }
11100
11101         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11102         if (ret)
11103                 goto done;
11104
11105         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11106                 intel_crtc_disable(&intel_crtc->base);
11107
11108         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11109                 if (intel_crtc->base.state->enable)
11110                         dev_priv->display.crtc_disable(&intel_crtc->base);
11111         }
11112
11113         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11114          * to set it here already despite that we pass it down the callchain.
11115          *
11116          * Note we'll need to fix this up when we start tracking multiple
11117          * pipes; here we assume a single modeset_pipe and only track the
11118          * single crtc and mode.
11119          */
11120         if (modeset_pipes) {
11121                 crtc->mode = *mode;
11122                 /* mode_set/enable/disable functions rely on a correct pipe
11123                  * config. */
11124                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11125
11126                 /*
11127                  * Calculate and store various constants which
11128                  * are later needed by vblank and swap-completion
11129                  * timestamping. They are derived from true hwmode.
11130                  */
11131                 drm_calc_timestamping_constants(crtc,
11132                                                 &pipe_config->base.adjusted_mode);
11133         }
11134
11135         /* Only after disabling all output pipelines that will be changed can we
11136          * update the the output configuration. */
11137         intel_modeset_update_state(dev, prepare_pipes);
11138
11139         modeset_update_crtc_power_domains(dev);
11140
11141         /* Set up the DPLL and any encoders state that needs to adjust or depend
11142          * on the DPLL.
11143          */
11144         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11145                 struct drm_plane *primary = intel_crtc->base.primary;
11146                 int vdisplay, hdisplay;
11147
11148                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11149                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11150                                                    fb, 0, 0,
11151                                                    hdisplay, vdisplay,
11152                                                    x << 16, y << 16,
11153                                                    hdisplay << 16, vdisplay << 16);
11154         }
11155
11156         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11157         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11158                 update_scanline_offset(intel_crtc);
11159
11160                 dev_priv->display.crtc_enable(&intel_crtc->base);
11161         }
11162
11163         /* FIXME: add subpixel order */
11164 done:
11165         if (ret && crtc->state->enable)
11166                 crtc->mode = *saved_mode;
11167
11168         kfree(saved_mode);
11169         return ret;
11170 }
11171
11172 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11173                                 struct drm_display_mode *mode,
11174                                 int x, int y, struct drm_framebuffer *fb,
11175                                 struct intel_crtc_state *pipe_config,
11176                                 unsigned modeset_pipes,
11177                                 unsigned prepare_pipes,
11178                                 unsigned disable_pipes)
11179 {
11180         int ret;
11181
11182         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11183                                prepare_pipes, disable_pipes);
11184
11185         if (ret == 0)
11186                 intel_modeset_check_state(crtc->dev);
11187
11188         return ret;
11189 }
11190
11191 static int intel_set_mode(struct drm_crtc *crtc,
11192                           struct drm_display_mode *mode,
11193                           int x, int y, struct drm_framebuffer *fb)
11194 {
11195         struct intel_crtc_state *pipe_config;
11196         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11197
11198         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11199                                                    &modeset_pipes,
11200                                                    &prepare_pipes,
11201                                                    &disable_pipes);
11202
11203         if (IS_ERR(pipe_config))
11204                 return PTR_ERR(pipe_config);
11205
11206         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11207                                     modeset_pipes, prepare_pipes,
11208                                     disable_pipes);
11209 }
11210
11211 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11212 {
11213         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11214 }
11215
11216 #undef for_each_intel_crtc_masked
11217
11218 static void intel_set_config_free(struct intel_set_config *config)
11219 {
11220         if (!config)
11221                 return;
11222
11223         kfree(config->save_connector_encoders);
11224         kfree(config->save_encoder_crtcs);
11225         kfree(config->save_crtc_enabled);
11226         kfree(config);
11227 }
11228
11229 static int intel_set_config_save_state(struct drm_device *dev,
11230                                        struct intel_set_config *config)
11231 {
11232         struct drm_crtc *crtc;
11233         struct drm_encoder *encoder;
11234         struct drm_connector *connector;
11235         int count;
11236
11237         config->save_crtc_enabled =
11238                 kcalloc(dev->mode_config.num_crtc,
11239                         sizeof(bool), GFP_KERNEL);
11240         if (!config->save_crtc_enabled)
11241                 return -ENOMEM;
11242
11243         config->save_encoder_crtcs =
11244                 kcalloc(dev->mode_config.num_encoder,
11245                         sizeof(struct drm_crtc *), GFP_KERNEL);
11246         if (!config->save_encoder_crtcs)
11247                 return -ENOMEM;
11248
11249         config->save_connector_encoders =
11250                 kcalloc(dev->mode_config.num_connector,
11251                         sizeof(struct drm_encoder *), GFP_KERNEL);
11252         if (!config->save_connector_encoders)
11253                 return -ENOMEM;
11254
11255         /* Copy data. Note that driver private data is not affected.
11256          * Should anything bad happen only the expected state is
11257          * restored, not the drivers personal bookkeeping.
11258          */
11259         count = 0;
11260         for_each_crtc(dev, crtc) {
11261                 config->save_crtc_enabled[count++] = crtc->state->enable;
11262         }
11263
11264         count = 0;
11265         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11266                 config->save_encoder_crtcs[count++] = encoder->crtc;
11267         }
11268
11269         count = 0;
11270         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11271                 config->save_connector_encoders[count++] = connector->encoder;
11272         }
11273
11274         return 0;
11275 }
11276
11277 static void intel_set_config_restore_state(struct drm_device *dev,
11278                                            struct intel_set_config *config)
11279 {
11280         struct intel_crtc *crtc;
11281         struct intel_encoder *encoder;
11282         struct intel_connector *connector;
11283         int count;
11284
11285         count = 0;
11286         for_each_intel_crtc(dev, crtc) {
11287                 crtc->new_enabled = config->save_crtc_enabled[count++];
11288
11289                 if (crtc->new_enabled)
11290                         crtc->new_config = crtc->config;
11291                 else
11292                         crtc->new_config = NULL;
11293         }
11294
11295         count = 0;
11296         for_each_intel_encoder(dev, encoder) {
11297                 encoder->new_crtc =
11298                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11299         }
11300
11301         count = 0;
11302         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11303                 connector->new_encoder =
11304                         to_intel_encoder(config->save_connector_encoders[count++]);
11305         }
11306 }
11307
11308 static bool
11309 is_crtc_connector_off(struct drm_mode_set *set)
11310 {
11311         int i;
11312
11313         if (set->num_connectors == 0)
11314                 return false;
11315
11316         if (WARN_ON(set->connectors == NULL))
11317                 return false;
11318
11319         for (i = 0; i < set->num_connectors; i++)
11320                 if (set->connectors[i]->encoder &&
11321                     set->connectors[i]->encoder->crtc == set->crtc &&
11322                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11323                         return true;
11324
11325         return false;
11326 }
11327
11328 static void
11329 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11330                                       struct intel_set_config *config)
11331 {
11332
11333         /* We should be able to check here if the fb has the same properties
11334          * and then just flip_or_move it */
11335         if (is_crtc_connector_off(set)) {
11336                 config->mode_changed = true;
11337         } else if (set->crtc->primary->fb != set->fb) {
11338                 /*
11339                  * If we have no fb, we can only flip as long as the crtc is
11340                  * active, otherwise we need a full mode set.  The crtc may
11341                  * be active if we've only disabled the primary plane, or
11342                  * in fastboot situations.
11343                  */
11344                 if (set->crtc->primary->fb == NULL) {
11345                         struct intel_crtc *intel_crtc =
11346                                 to_intel_crtc(set->crtc);
11347
11348                         if (intel_crtc->active) {
11349                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11350                                 config->fb_changed = true;
11351                         } else {
11352                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11353                                 config->mode_changed = true;
11354                         }
11355                 } else if (set->fb == NULL) {
11356                         config->mode_changed = true;
11357                 } else if (set->fb->pixel_format !=
11358                            set->crtc->primary->fb->pixel_format) {
11359                         config->mode_changed = true;
11360                 } else {
11361                         config->fb_changed = true;
11362                 }
11363         }
11364
11365         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11366                 config->fb_changed = true;
11367
11368         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11369                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11370                 drm_mode_debug_printmodeline(&set->crtc->mode);
11371                 drm_mode_debug_printmodeline(set->mode);
11372                 config->mode_changed = true;
11373         }
11374
11375         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11376                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11377 }
11378
11379 static int
11380 intel_modeset_stage_output_state(struct drm_device *dev,
11381                                  struct drm_mode_set *set,
11382                                  struct intel_set_config *config)
11383 {
11384         struct intel_connector *connector;
11385         struct intel_encoder *encoder;
11386         struct intel_crtc *crtc;
11387         int ro;
11388
11389         /* The upper layers ensure that we either disable a crtc or have a list
11390          * of connectors. For paranoia, double-check this. */
11391         WARN_ON(!set->fb && (set->num_connectors != 0));
11392         WARN_ON(set->fb && (set->num_connectors == 0));
11393
11394         list_for_each_entry(connector, &dev->mode_config.connector_list,
11395                             base.head) {
11396                 /* Otherwise traverse passed in connector list and get encoders
11397                  * for them. */
11398                 for (ro = 0; ro < set->num_connectors; ro++) {
11399                         if (set->connectors[ro] == &connector->base) {
11400                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11401                                 break;
11402                         }
11403                 }
11404
11405                 /* If we disable the crtc, disable all its connectors. Also, if
11406                  * the connector is on the changing crtc but not on the new
11407                  * connector list, disable it. */
11408                 if ((!set->fb || ro == set->num_connectors) &&
11409                     connector->base.encoder &&
11410                     connector->base.encoder->crtc == set->crtc) {
11411                         connector->new_encoder = NULL;
11412
11413                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11414                                 connector->base.base.id,
11415                                 connector->base.name);
11416                 }
11417
11418
11419                 if (&connector->new_encoder->base != connector->base.encoder) {
11420                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11421                         config->mode_changed = true;
11422                 }
11423         }
11424         /* connector->new_encoder is now updated for all connectors. */
11425
11426         /* Update crtc of enabled connectors. */
11427         list_for_each_entry(connector, &dev->mode_config.connector_list,
11428                             base.head) {
11429                 struct drm_crtc *new_crtc;
11430
11431                 if (!connector->new_encoder)
11432                         continue;
11433
11434                 new_crtc = connector->new_encoder->base.crtc;
11435
11436                 for (ro = 0; ro < set->num_connectors; ro++) {
11437                         if (set->connectors[ro] == &connector->base)
11438                                 new_crtc = set->crtc;
11439                 }
11440
11441                 /* Make sure the new CRTC will work with the encoder */
11442                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11443                                          new_crtc)) {
11444                         return -EINVAL;
11445                 }
11446                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11447
11448                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11449                         connector->base.base.id,
11450                         connector->base.name,
11451                         new_crtc->base.id);
11452         }
11453
11454         /* Check for any encoders that needs to be disabled. */
11455         for_each_intel_encoder(dev, encoder) {
11456                 int num_connectors = 0;
11457                 list_for_each_entry(connector,
11458                                     &dev->mode_config.connector_list,
11459                                     base.head) {
11460                         if (connector->new_encoder == encoder) {
11461                                 WARN_ON(!connector->new_encoder->new_crtc);
11462                                 num_connectors++;
11463                         }
11464                 }
11465
11466                 if (num_connectors == 0)
11467                         encoder->new_crtc = NULL;
11468                 else if (num_connectors > 1)
11469                         return -EINVAL;
11470
11471                 /* Only now check for crtc changes so we don't miss encoders
11472                  * that will be disabled. */
11473                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11474                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11475                         config->mode_changed = true;
11476                 }
11477         }
11478         /* Now we've also updated encoder->new_crtc for all encoders. */
11479         list_for_each_entry(connector, &dev->mode_config.connector_list,
11480                             base.head) {
11481                 if (connector->new_encoder)
11482                         if (connector->new_encoder != connector->encoder)
11483                                 connector->encoder = connector->new_encoder;
11484         }
11485         for_each_intel_crtc(dev, crtc) {
11486                 crtc->new_enabled = false;
11487
11488                 for_each_intel_encoder(dev, encoder) {
11489                         if (encoder->new_crtc == crtc) {
11490                                 crtc->new_enabled = true;
11491                                 break;
11492                         }
11493                 }
11494
11495                 if (crtc->new_enabled != crtc->base.state->enable) {
11496                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11497                                       crtc->new_enabled ? "en" : "dis");
11498                         config->mode_changed = true;
11499                 }
11500
11501                 if (crtc->new_enabled)
11502                         crtc->new_config = crtc->config;
11503                 else
11504                         crtc->new_config = NULL;
11505         }
11506
11507         return 0;
11508 }
11509
11510 static void disable_crtc_nofb(struct intel_crtc *crtc)
11511 {
11512         struct drm_device *dev = crtc->base.dev;
11513         struct intel_encoder *encoder;
11514         struct intel_connector *connector;
11515
11516         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11517                       pipe_name(crtc->pipe));
11518
11519         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11520                 if (connector->new_encoder &&
11521                     connector->new_encoder->new_crtc == crtc)
11522                         connector->new_encoder = NULL;
11523         }
11524
11525         for_each_intel_encoder(dev, encoder) {
11526                 if (encoder->new_crtc == crtc)
11527                         encoder->new_crtc = NULL;
11528         }
11529
11530         crtc->new_enabled = false;
11531         crtc->new_config = NULL;
11532 }
11533
11534 static int intel_crtc_set_config(struct drm_mode_set *set)
11535 {
11536         struct drm_device *dev;
11537         struct drm_mode_set save_set;
11538         struct intel_set_config *config;
11539         struct intel_crtc_state *pipe_config;
11540         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11541         int ret;
11542
11543         BUG_ON(!set);
11544         BUG_ON(!set->crtc);
11545         BUG_ON(!set->crtc->helper_private);
11546
11547         /* Enforce sane interface api - has been abused by the fb helper. */
11548         BUG_ON(!set->mode && set->fb);
11549         BUG_ON(set->fb && set->num_connectors == 0);
11550
11551         if (set->fb) {
11552                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11553                                 set->crtc->base.id, set->fb->base.id,
11554                                 (int)set->num_connectors, set->x, set->y);
11555         } else {
11556                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11557         }
11558
11559         dev = set->crtc->dev;
11560
11561         ret = -ENOMEM;
11562         config = kzalloc(sizeof(*config), GFP_KERNEL);
11563         if (!config)
11564                 goto out_config;
11565
11566         ret = intel_set_config_save_state(dev, config);
11567         if (ret)
11568                 goto out_config;
11569
11570         save_set.crtc = set->crtc;
11571         save_set.mode = &set->crtc->mode;
11572         save_set.x = set->crtc->x;
11573         save_set.y = set->crtc->y;
11574         save_set.fb = set->crtc->primary->fb;
11575
11576         /* Compute whether we need a full modeset, only an fb base update or no
11577          * change at all. In the future we might also check whether only the
11578          * mode changed, e.g. for LVDS where we only change the panel fitter in
11579          * such cases. */
11580         intel_set_config_compute_mode_changes(set, config);
11581
11582         ret = intel_modeset_stage_output_state(dev, set, config);
11583         if (ret)
11584                 goto fail;
11585
11586         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11587                                                    set->fb,
11588                                                    &modeset_pipes,
11589                                                    &prepare_pipes,
11590                                                    &disable_pipes);
11591         if (IS_ERR(pipe_config)) {
11592                 ret = PTR_ERR(pipe_config);
11593                 goto fail;
11594         } else if (pipe_config) {
11595                 if (pipe_config->has_audio !=
11596                     to_intel_crtc(set->crtc)->config->has_audio)
11597                         config->mode_changed = true;
11598
11599                 /*
11600                  * Note we have an issue here with infoframes: current code
11601                  * only updates them on the full mode set path per hw
11602                  * requirements.  So here we should be checking for any
11603                  * required changes and forcing a mode set.
11604                  */
11605         }
11606
11607         /* set_mode will free it in the mode_changed case */
11608         if (!config->mode_changed)
11609                 kfree(pipe_config);
11610
11611         intel_update_pipe_size(to_intel_crtc(set->crtc));
11612
11613         if (config->mode_changed) {
11614                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11615                                            set->x, set->y, set->fb, pipe_config,
11616                                            modeset_pipes, prepare_pipes,
11617                                            disable_pipes);
11618         } else if (config->fb_changed) {
11619                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11620                 struct drm_plane *primary = set->crtc->primary;
11621                 int vdisplay, hdisplay;
11622
11623                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11624                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11625                                                    0, 0, hdisplay, vdisplay,
11626                                                    set->x << 16, set->y << 16,
11627                                                    hdisplay << 16, vdisplay << 16);
11628
11629                 /*
11630                  * We need to make sure the primary plane is re-enabled if it
11631                  * has previously been turned off.
11632                  */
11633                 if (!intel_crtc->primary_enabled && ret == 0) {
11634                         WARN_ON(!intel_crtc->active);
11635                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11636                 }
11637
11638                 /*
11639                  * In the fastboot case this may be our only check of the
11640                  * state after boot.  It would be better to only do it on
11641                  * the first update, but we don't have a nice way of doing that
11642                  * (and really, set_config isn't used much for high freq page
11643                  * flipping, so increasing its cost here shouldn't be a big
11644                  * deal).
11645                  */
11646                 if (i915.fastboot && ret == 0)
11647                         intel_modeset_check_state(set->crtc->dev);
11648         }
11649
11650         if (ret) {
11651                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11652                               set->crtc->base.id, ret);
11653 fail:
11654                 intel_set_config_restore_state(dev, config);
11655
11656                 /*
11657                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11658                  * force the pipe off to avoid oopsing in the modeset code
11659                  * due to fb==NULL. This should only happen during boot since
11660                  * we don't yet reconstruct the FB from the hardware state.
11661                  */
11662                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11663                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11664
11665                 /* Try to restore the config */
11666                 if (config->mode_changed &&
11667                     intel_set_mode(save_set.crtc, save_set.mode,
11668                                    save_set.x, save_set.y, save_set.fb))
11669                         DRM_ERROR("failed to restore config after modeset failure\n");
11670         }
11671
11672 out_config:
11673         intel_set_config_free(config);
11674         return ret;
11675 }
11676
11677 static const struct drm_crtc_funcs intel_crtc_funcs = {
11678         .gamma_set = intel_crtc_gamma_set,
11679         .set_config = intel_crtc_set_config,
11680         .destroy = intel_crtc_destroy,
11681         .page_flip = intel_crtc_page_flip,
11682         .atomic_duplicate_state = intel_crtc_duplicate_state,
11683         .atomic_destroy_state = intel_crtc_destroy_state,
11684 };
11685
11686 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11687                                       struct intel_shared_dpll *pll,
11688                                       struct intel_dpll_hw_state *hw_state)
11689 {
11690         uint32_t val;
11691
11692         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11693                 return false;
11694
11695         val = I915_READ(PCH_DPLL(pll->id));
11696         hw_state->dpll = val;
11697         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11698         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11699
11700         return val & DPLL_VCO_ENABLE;
11701 }
11702
11703 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11704                                   struct intel_shared_dpll *pll)
11705 {
11706         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11707         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11708 }
11709
11710 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11711                                 struct intel_shared_dpll *pll)
11712 {
11713         /* PCH refclock must be enabled first */
11714         ibx_assert_pch_refclk_enabled(dev_priv);
11715
11716         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11717
11718         /* Wait for the clocks to stabilize. */
11719         POSTING_READ(PCH_DPLL(pll->id));
11720         udelay(150);
11721
11722         /* The pixel multiplier can only be updated once the
11723          * DPLL is enabled and the clocks are stable.
11724          *
11725          * So write it again.
11726          */
11727         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11728         POSTING_READ(PCH_DPLL(pll->id));
11729         udelay(200);
11730 }
11731
11732 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11733                                  struct intel_shared_dpll *pll)
11734 {
11735         struct drm_device *dev = dev_priv->dev;
11736         struct intel_crtc *crtc;
11737
11738         /* Make sure no transcoder isn't still depending on us. */
11739         for_each_intel_crtc(dev, crtc) {
11740                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11741                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11742         }
11743
11744         I915_WRITE(PCH_DPLL(pll->id), 0);
11745         POSTING_READ(PCH_DPLL(pll->id));
11746         udelay(200);
11747 }
11748
11749 static char *ibx_pch_dpll_names[] = {
11750         "PCH DPLL A",
11751         "PCH DPLL B",
11752 };
11753
11754 static void ibx_pch_dpll_init(struct drm_device *dev)
11755 {
11756         struct drm_i915_private *dev_priv = dev->dev_private;
11757         int i;
11758
11759         dev_priv->num_shared_dpll = 2;
11760
11761         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11762                 dev_priv->shared_dplls[i].id = i;
11763                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11764                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11765                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11766                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11767                 dev_priv->shared_dplls[i].get_hw_state =
11768                         ibx_pch_dpll_get_hw_state;
11769         }
11770 }
11771
11772 static void intel_shared_dpll_init(struct drm_device *dev)
11773 {
11774         struct drm_i915_private *dev_priv = dev->dev_private;
11775
11776         if (HAS_DDI(dev))
11777                 intel_ddi_pll_init(dev);
11778         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11779                 ibx_pch_dpll_init(dev);
11780         else
11781                 dev_priv->num_shared_dpll = 0;
11782
11783         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11784 }
11785
11786 /**
11787  * intel_prepare_plane_fb - Prepare fb for usage on plane
11788  * @plane: drm plane to prepare for
11789  * @fb: framebuffer to prepare for presentation
11790  *
11791  * Prepares a framebuffer for usage on a display plane.  Generally this
11792  * involves pinning the underlying object and updating the frontbuffer tracking
11793  * bits.  Some older platforms need special physical address handling for
11794  * cursor planes.
11795  *
11796  * Returns 0 on success, negative error code on failure.
11797  */
11798 int
11799 intel_prepare_plane_fb(struct drm_plane *plane,
11800                        struct drm_framebuffer *fb)
11801 {
11802         struct drm_device *dev = plane->dev;
11803         struct intel_plane *intel_plane = to_intel_plane(plane);
11804         enum pipe pipe = intel_plane->pipe;
11805         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11806         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11807         unsigned frontbuffer_bits = 0;
11808         int ret = 0;
11809
11810         if (!obj)
11811                 return 0;
11812
11813         switch (plane->type) {
11814         case DRM_PLANE_TYPE_PRIMARY:
11815                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11816                 break;
11817         case DRM_PLANE_TYPE_CURSOR:
11818                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11819                 break;
11820         case DRM_PLANE_TYPE_OVERLAY:
11821                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11822                 break;
11823         }
11824
11825         mutex_lock(&dev->struct_mutex);
11826
11827         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11828             INTEL_INFO(dev)->cursor_needs_physical) {
11829                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11830                 ret = i915_gem_object_attach_phys(obj, align);
11831                 if (ret)
11832                         DRM_DEBUG_KMS("failed to attach phys object\n");
11833         } else {
11834                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11835         }
11836
11837         if (ret == 0)
11838                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11839
11840         mutex_unlock(&dev->struct_mutex);
11841
11842         return ret;
11843 }
11844
11845 /**
11846  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11847  * @plane: drm plane to clean up for
11848  * @fb: old framebuffer that was on plane
11849  *
11850  * Cleans up a framebuffer that has just been removed from a plane.
11851  */
11852 void
11853 intel_cleanup_plane_fb(struct drm_plane *plane,
11854                        struct drm_framebuffer *fb)
11855 {
11856         struct drm_device *dev = plane->dev;
11857         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11858
11859         if (WARN_ON(!obj))
11860                 return;
11861
11862         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11863             !INTEL_INFO(dev)->cursor_needs_physical) {
11864                 mutex_lock(&dev->struct_mutex);
11865                 intel_unpin_fb_obj(obj);
11866                 mutex_unlock(&dev->struct_mutex);
11867         }
11868 }
11869
11870 static int
11871 intel_check_primary_plane(struct drm_plane *plane,
11872                           struct intel_plane_state *state)
11873 {
11874         struct drm_device *dev = plane->dev;
11875         struct drm_i915_private *dev_priv = dev->dev_private;
11876         struct drm_crtc *crtc = state->base.crtc;
11877         struct intel_crtc *intel_crtc;
11878         struct drm_framebuffer *fb = state->base.fb;
11879         struct drm_rect *dest = &state->dst;
11880         struct drm_rect *src = &state->src;
11881         const struct drm_rect *clip = &state->clip;
11882         int ret;
11883
11884         crtc = crtc ? crtc : plane->crtc;
11885         intel_crtc = to_intel_crtc(crtc);
11886
11887         ret = drm_plane_helper_check_update(plane, crtc, fb,
11888                                             src, dest, clip,
11889                                             DRM_PLANE_HELPER_NO_SCALING,
11890                                             DRM_PLANE_HELPER_NO_SCALING,
11891                                             false, true, &state->visible);
11892         if (ret)
11893                 return ret;
11894
11895         if (intel_crtc->active) {
11896                 intel_crtc->atomic.wait_for_flips = true;
11897
11898                 /*
11899                  * FBC does not work on some platforms for rotated
11900                  * planes, so disable it when rotation is not 0 and
11901                  * update it when rotation is set back to 0.
11902                  *
11903                  * FIXME: This is redundant with the fbc update done in
11904                  * the primary plane enable function except that that
11905                  * one is done too late. We eventually need to unify
11906                  * this.
11907                  */
11908                 if (intel_crtc->primary_enabled &&
11909                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11910                     dev_priv->fbc.crtc == intel_crtc &&
11911                     state->base.rotation != BIT(DRM_ROTATE_0)) {
11912                         intel_crtc->atomic.disable_fbc = true;
11913                 }
11914
11915                 if (state->visible) {
11916                         /*
11917                          * BDW signals flip done immediately if the plane
11918                          * is disabled, even if the plane enable is already
11919                          * armed to occur at the next vblank :(
11920                          */
11921                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11922                                 intel_crtc->atomic.wait_vblank = true;
11923                 }
11924
11925                 intel_crtc->atomic.fb_bits |=
11926                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11927
11928                 intel_crtc->atomic.update_fbc = true;
11929         }
11930
11931         return 0;
11932 }
11933
11934 static void
11935 intel_commit_primary_plane(struct drm_plane *plane,
11936                            struct intel_plane_state *state)
11937 {
11938         struct drm_crtc *crtc = state->base.crtc;
11939         struct drm_framebuffer *fb = state->base.fb;
11940         struct drm_device *dev = plane->dev;
11941         struct drm_i915_private *dev_priv = dev->dev_private;
11942         struct intel_crtc *intel_crtc;
11943         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11944         struct intel_plane *intel_plane = to_intel_plane(plane);
11945         struct drm_rect *src = &state->src;
11946
11947         crtc = crtc ? crtc : plane->crtc;
11948         intel_crtc = to_intel_crtc(crtc);
11949
11950         plane->fb = fb;
11951         crtc->x = src->x1 >> 16;
11952         crtc->y = src->y1 >> 16;
11953
11954         intel_plane->obj = obj;
11955
11956         if (intel_crtc->active) {
11957                 if (state->visible) {
11958                         /* FIXME: kill this fastboot hack */
11959                         intel_update_pipe_size(intel_crtc);
11960
11961                         intel_crtc->primary_enabled = true;
11962
11963                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11964                                         crtc->x, crtc->y);
11965                 } else {
11966                         /*
11967                          * If clipping results in a non-visible primary plane,
11968                          * we'll disable the primary plane.  Note that this is
11969                          * a bit different than what happens if userspace
11970                          * explicitly disables the plane by passing fb=0
11971                          * because plane->fb still gets set and pinned.
11972                          */
11973                         intel_disable_primary_hw_plane(plane, crtc);
11974                 }
11975         }
11976 }
11977
11978 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11979 {
11980         struct drm_device *dev = crtc->dev;
11981         struct drm_i915_private *dev_priv = dev->dev_private;
11982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11983         struct intel_plane *intel_plane;
11984         struct drm_plane *p;
11985         unsigned fb_bits = 0;
11986
11987         /* Track fb's for any planes being disabled */
11988         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11989                 intel_plane = to_intel_plane(p);
11990
11991                 if (intel_crtc->atomic.disabled_planes &
11992                     (1 << drm_plane_index(p))) {
11993                         switch (p->type) {
11994                         case DRM_PLANE_TYPE_PRIMARY:
11995                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11996                                 break;
11997                         case DRM_PLANE_TYPE_CURSOR:
11998                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11999                                 break;
12000                         case DRM_PLANE_TYPE_OVERLAY:
12001                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12002                                 break;
12003                         }
12004
12005                         mutex_lock(&dev->struct_mutex);
12006                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12007                         mutex_unlock(&dev->struct_mutex);
12008                 }
12009         }
12010
12011         if (intel_crtc->atomic.wait_for_flips)
12012                 intel_crtc_wait_for_pending_flips(crtc);
12013
12014         if (intel_crtc->atomic.disable_fbc)
12015                 intel_fbc_disable(dev);
12016
12017         if (intel_crtc->atomic.pre_disable_primary)
12018                 intel_pre_disable_primary(crtc);
12019
12020         if (intel_crtc->atomic.update_wm)
12021                 intel_update_watermarks(crtc);
12022
12023         intel_runtime_pm_get(dev_priv);
12024
12025         /* Perform vblank evasion around commit operation */
12026         if (intel_crtc->active)
12027                 intel_crtc->atomic.evade =
12028                         intel_pipe_update_start(intel_crtc,
12029                                                 &intel_crtc->atomic.start_vbl_count);
12030 }
12031
12032 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12033 {
12034         struct drm_device *dev = crtc->dev;
12035         struct drm_i915_private *dev_priv = dev->dev_private;
12036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12037         struct drm_plane *p;
12038
12039         if (intel_crtc->atomic.evade)
12040                 intel_pipe_update_end(intel_crtc,
12041                                       intel_crtc->atomic.start_vbl_count);
12042
12043         intel_runtime_pm_put(dev_priv);
12044
12045         if (intel_crtc->atomic.wait_vblank)
12046                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12047
12048         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12049
12050         if (intel_crtc->atomic.update_fbc) {
12051                 mutex_lock(&dev->struct_mutex);
12052                 intel_fbc_update(dev);
12053                 mutex_unlock(&dev->struct_mutex);
12054         }
12055
12056         if (intel_crtc->atomic.post_enable_primary)
12057                 intel_post_enable_primary(crtc);
12058
12059         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12060                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12061                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12062                                                        false, false);
12063
12064         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12065 }
12066
12067 /**
12068  * intel_plane_destroy - destroy a plane
12069  * @plane: plane to destroy
12070  *
12071  * Common destruction function for all types of planes (primary, cursor,
12072  * sprite).
12073  */
12074 void intel_plane_destroy(struct drm_plane *plane)
12075 {
12076         struct intel_plane *intel_plane = to_intel_plane(plane);
12077         drm_plane_cleanup(plane);
12078         kfree(intel_plane);
12079 }
12080
12081 const struct drm_plane_funcs intel_plane_funcs = {
12082         .update_plane = drm_atomic_helper_update_plane,
12083         .disable_plane = drm_atomic_helper_disable_plane,
12084         .destroy = intel_plane_destroy,
12085         .set_property = drm_atomic_helper_plane_set_property,
12086         .atomic_get_property = intel_plane_atomic_get_property,
12087         .atomic_set_property = intel_plane_atomic_set_property,
12088         .atomic_duplicate_state = intel_plane_duplicate_state,
12089         .atomic_destroy_state = intel_plane_destroy_state,
12090
12091 };
12092
12093 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12094                                                     int pipe)
12095 {
12096         struct intel_plane *primary;
12097         struct intel_plane_state *state;
12098         const uint32_t *intel_primary_formats;
12099         int num_formats;
12100
12101         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12102         if (primary == NULL)
12103                 return NULL;
12104
12105         state = intel_create_plane_state(&primary->base);
12106         if (!state) {
12107                 kfree(primary);
12108                 return NULL;
12109         }
12110         primary->base.state = &state->base;
12111
12112         primary->can_scale = false;
12113         primary->max_downscale = 1;
12114         primary->pipe = pipe;
12115         primary->plane = pipe;
12116         primary->check_plane = intel_check_primary_plane;
12117         primary->commit_plane = intel_commit_primary_plane;
12118         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12119                 primary->plane = !pipe;
12120
12121         if (INTEL_INFO(dev)->gen <= 3) {
12122                 intel_primary_formats = intel_primary_formats_gen2;
12123                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12124         } else {
12125                 intel_primary_formats = intel_primary_formats_gen4;
12126                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12127         }
12128
12129         drm_universal_plane_init(dev, &primary->base, 0,
12130                                  &intel_plane_funcs,
12131                                  intel_primary_formats, num_formats,
12132                                  DRM_PLANE_TYPE_PRIMARY);
12133
12134         if (INTEL_INFO(dev)->gen >= 4) {
12135                 if (!dev->mode_config.rotation_property)
12136                         dev->mode_config.rotation_property =
12137                                 drm_mode_create_rotation_property(dev,
12138                                                         BIT(DRM_ROTATE_0) |
12139                                                         BIT(DRM_ROTATE_180));
12140                 if (dev->mode_config.rotation_property)
12141                         drm_object_attach_property(&primary->base.base,
12142                                 dev->mode_config.rotation_property,
12143                                 state->base.rotation);
12144         }
12145
12146         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12147
12148         return &primary->base;
12149 }
12150
12151 static int
12152 intel_check_cursor_plane(struct drm_plane *plane,
12153                          struct intel_plane_state *state)
12154 {
12155         struct drm_crtc *crtc = state->base.crtc;
12156         struct drm_device *dev = plane->dev;
12157         struct drm_framebuffer *fb = state->base.fb;
12158         struct drm_rect *dest = &state->dst;
12159         struct drm_rect *src = &state->src;
12160         const struct drm_rect *clip = &state->clip;
12161         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12162         struct intel_crtc *intel_crtc;
12163         unsigned stride;
12164         int ret;
12165
12166         crtc = crtc ? crtc : plane->crtc;
12167         intel_crtc = to_intel_crtc(crtc);
12168
12169         ret = drm_plane_helper_check_update(plane, crtc, fb,
12170                                             src, dest, clip,
12171                                             DRM_PLANE_HELPER_NO_SCALING,
12172                                             DRM_PLANE_HELPER_NO_SCALING,
12173                                             true, true, &state->visible);
12174         if (ret)
12175                 return ret;
12176
12177
12178         /* if we want to turn off the cursor ignore width and height */
12179         if (!obj)
12180                 goto finish;
12181
12182         /* Check for which cursor types we support */
12183         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12184                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12185                           state->base.crtc_w, state->base.crtc_h);
12186                 return -EINVAL;
12187         }
12188
12189         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12190         if (obj->base.size < stride * state->base.crtc_h) {
12191                 DRM_DEBUG_KMS("buffer is too small\n");
12192                 return -ENOMEM;
12193         }
12194
12195         if (fb == crtc->cursor->fb)
12196                 return 0;
12197
12198         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12199                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12200                 ret = -EINVAL;
12201         }
12202
12203 finish:
12204         if (intel_crtc->active) {
12205                 if (intel_crtc->cursor_width != state->base.crtc_w)
12206                         intel_crtc->atomic.update_wm = true;
12207
12208                 intel_crtc->atomic.fb_bits |=
12209                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12210         }
12211
12212         return ret;
12213 }
12214
12215 static void
12216 intel_commit_cursor_plane(struct drm_plane *plane,
12217                           struct intel_plane_state *state)
12218 {
12219         struct drm_crtc *crtc = state->base.crtc;
12220         struct drm_device *dev = plane->dev;
12221         struct intel_crtc *intel_crtc;
12222         struct intel_plane *intel_plane = to_intel_plane(plane);
12223         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12224         uint32_t addr;
12225
12226         crtc = crtc ? crtc : plane->crtc;
12227         intel_crtc = to_intel_crtc(crtc);
12228
12229         plane->fb = state->base.fb;
12230         crtc->cursor_x = state->base.crtc_x;
12231         crtc->cursor_y = state->base.crtc_y;
12232
12233         intel_plane->obj = obj;
12234
12235         if (intel_crtc->cursor_bo == obj)
12236                 goto update;
12237
12238         if (!obj)
12239                 addr = 0;
12240         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12241                 addr = i915_gem_obj_ggtt_offset(obj);
12242         else
12243                 addr = obj->phys_handle->busaddr;
12244
12245         intel_crtc->cursor_addr = addr;
12246         intel_crtc->cursor_bo = obj;
12247 update:
12248         intel_crtc->cursor_width = state->base.crtc_w;
12249         intel_crtc->cursor_height = state->base.crtc_h;
12250
12251         if (intel_crtc->active)
12252                 intel_crtc_update_cursor(crtc, state->visible);
12253 }
12254
12255 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12256                                                    int pipe)
12257 {
12258         struct intel_plane *cursor;
12259         struct intel_plane_state *state;
12260
12261         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12262         if (cursor == NULL)
12263                 return NULL;
12264
12265         state = intel_create_plane_state(&cursor->base);
12266         if (!state) {
12267                 kfree(cursor);
12268                 return NULL;
12269         }
12270         cursor->base.state = &state->base;
12271
12272         cursor->can_scale = false;
12273         cursor->max_downscale = 1;
12274         cursor->pipe = pipe;
12275         cursor->plane = pipe;
12276         cursor->check_plane = intel_check_cursor_plane;
12277         cursor->commit_plane = intel_commit_cursor_plane;
12278
12279         drm_universal_plane_init(dev, &cursor->base, 0,
12280                                  &intel_plane_funcs,
12281                                  intel_cursor_formats,
12282                                  ARRAY_SIZE(intel_cursor_formats),
12283                                  DRM_PLANE_TYPE_CURSOR);
12284
12285         if (INTEL_INFO(dev)->gen >= 4) {
12286                 if (!dev->mode_config.rotation_property)
12287                         dev->mode_config.rotation_property =
12288                                 drm_mode_create_rotation_property(dev,
12289                                                         BIT(DRM_ROTATE_0) |
12290                                                         BIT(DRM_ROTATE_180));
12291                 if (dev->mode_config.rotation_property)
12292                         drm_object_attach_property(&cursor->base.base,
12293                                 dev->mode_config.rotation_property,
12294                                 state->base.rotation);
12295         }
12296
12297         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12298
12299         return &cursor->base;
12300 }
12301
12302 static void intel_crtc_init(struct drm_device *dev, int pipe)
12303 {
12304         struct drm_i915_private *dev_priv = dev->dev_private;
12305         struct intel_crtc *intel_crtc;
12306         struct intel_crtc_state *crtc_state = NULL;
12307         struct drm_plane *primary = NULL;
12308         struct drm_plane *cursor = NULL;
12309         int i, ret;
12310
12311         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12312         if (intel_crtc == NULL)
12313                 return;
12314
12315         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12316         if (!crtc_state)
12317                 goto fail;
12318         intel_crtc_set_state(intel_crtc, crtc_state);
12319         crtc_state->base.crtc = &intel_crtc->base;
12320
12321         primary = intel_primary_plane_create(dev, pipe);
12322         if (!primary)
12323                 goto fail;
12324
12325         cursor = intel_cursor_plane_create(dev, pipe);
12326         if (!cursor)
12327                 goto fail;
12328
12329         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12330                                         cursor, &intel_crtc_funcs);
12331         if (ret)
12332                 goto fail;
12333
12334         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12335         for (i = 0; i < 256; i++) {
12336                 intel_crtc->lut_r[i] = i;
12337                 intel_crtc->lut_g[i] = i;
12338                 intel_crtc->lut_b[i] = i;
12339         }
12340
12341         /*
12342          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12343          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12344          */
12345         intel_crtc->pipe = pipe;
12346         intel_crtc->plane = pipe;
12347         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12348                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12349                 intel_crtc->plane = !pipe;
12350         }
12351
12352         intel_crtc->cursor_base = ~0;
12353         intel_crtc->cursor_cntl = ~0;
12354         intel_crtc->cursor_size = ~0;
12355
12356         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12357                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12358         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12359         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12360
12361         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12362
12363         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12364
12365         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12366         return;
12367
12368 fail:
12369         if (primary)
12370                 drm_plane_cleanup(primary);
12371         if (cursor)
12372                 drm_plane_cleanup(cursor);
12373         kfree(crtc_state);
12374         kfree(intel_crtc);
12375 }
12376
12377 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12378 {
12379         struct drm_encoder *encoder = connector->base.encoder;
12380         struct drm_device *dev = connector->base.dev;
12381
12382         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12383
12384         if (!encoder || WARN_ON(!encoder->crtc))
12385                 return INVALID_PIPE;
12386
12387         return to_intel_crtc(encoder->crtc)->pipe;
12388 }
12389
12390 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12391                                 struct drm_file *file)
12392 {
12393         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12394         struct drm_crtc *drmmode_crtc;
12395         struct intel_crtc *crtc;
12396
12397         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12398
12399         if (!drmmode_crtc) {
12400                 DRM_ERROR("no such CRTC id\n");
12401                 return -ENOENT;
12402         }
12403
12404         crtc = to_intel_crtc(drmmode_crtc);
12405         pipe_from_crtc_id->pipe = crtc->pipe;
12406
12407         return 0;
12408 }
12409
12410 static int intel_encoder_clones(struct intel_encoder *encoder)
12411 {
12412         struct drm_device *dev = encoder->base.dev;
12413         struct intel_encoder *source_encoder;
12414         int index_mask = 0;
12415         int entry = 0;
12416
12417         for_each_intel_encoder(dev, source_encoder) {
12418                 if (encoders_cloneable(encoder, source_encoder))
12419                         index_mask |= (1 << entry);
12420
12421                 entry++;
12422         }
12423
12424         return index_mask;
12425 }
12426
12427 static bool has_edp_a(struct drm_device *dev)
12428 {
12429         struct drm_i915_private *dev_priv = dev->dev_private;
12430
12431         if (!IS_MOBILE(dev))
12432                 return false;
12433
12434         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12435                 return false;
12436
12437         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12438                 return false;
12439
12440         return true;
12441 }
12442
12443 static bool intel_crt_present(struct drm_device *dev)
12444 {
12445         struct drm_i915_private *dev_priv = dev->dev_private;
12446
12447         if (INTEL_INFO(dev)->gen >= 9)
12448                 return false;
12449
12450         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12451                 return false;
12452
12453         if (IS_CHERRYVIEW(dev))
12454                 return false;
12455
12456         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12457                 return false;
12458
12459         return true;
12460 }
12461
12462 static void intel_setup_outputs(struct drm_device *dev)
12463 {
12464         struct drm_i915_private *dev_priv = dev->dev_private;
12465         struct intel_encoder *encoder;
12466         struct drm_connector *connector;
12467         bool dpd_is_edp = false;
12468
12469         intel_lvds_init(dev);
12470
12471         if (intel_crt_present(dev))
12472                 intel_crt_init(dev);
12473
12474         if (HAS_DDI(dev)) {
12475                 int found;
12476
12477                 /* Haswell uses DDI functions to detect digital outputs */
12478                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12479                 /* DDI A only supports eDP */
12480                 if (found)
12481                         intel_ddi_init(dev, PORT_A);
12482
12483                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12484                  * register */
12485                 found = I915_READ(SFUSE_STRAP);
12486
12487                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12488                         intel_ddi_init(dev, PORT_B);
12489                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12490                         intel_ddi_init(dev, PORT_C);
12491                 if (found & SFUSE_STRAP_DDID_DETECTED)
12492                         intel_ddi_init(dev, PORT_D);
12493         } else if (HAS_PCH_SPLIT(dev)) {
12494                 int found;
12495                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12496
12497                 if (has_edp_a(dev))
12498                         intel_dp_init(dev, DP_A, PORT_A);
12499
12500                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12501                         /* PCH SDVOB multiplex with HDMIB */
12502                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12503                         if (!found)
12504                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12505                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12506                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12507                 }
12508
12509                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12510                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12511
12512                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12513                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12514
12515                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12516                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12517
12518                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12519                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12520         } else if (IS_VALLEYVIEW(dev)) {
12521                 /*
12522                  * The DP_DETECTED bit is the latched state of the DDC
12523                  * SDA pin at boot. However since eDP doesn't require DDC
12524                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12525                  * eDP ports may have been muxed to an alternate function.
12526                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12527                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12528                  * detect eDP ports.
12529                  */
12530                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12531                     !intel_dp_is_edp(dev, PORT_B))
12532                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12533                                         PORT_B);
12534                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12535                     intel_dp_is_edp(dev, PORT_B))
12536                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12537
12538                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12539                     !intel_dp_is_edp(dev, PORT_C))
12540                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12541                                         PORT_C);
12542                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12543                     intel_dp_is_edp(dev, PORT_C))
12544                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12545
12546                 if (IS_CHERRYVIEW(dev)) {
12547                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12548                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12549                                                 PORT_D);
12550                         /* eDP not supported on port D, so don't check VBT */
12551                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12552                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12553                 }
12554
12555                 intel_dsi_init(dev);
12556         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12557                 bool found = false;
12558
12559                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12560                         DRM_DEBUG_KMS("probing SDVOB\n");
12561                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12562                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12563                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12564                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12565                         }
12566
12567                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12568                                 intel_dp_init(dev, DP_B, PORT_B);
12569                 }
12570
12571                 /* Before G4X SDVOC doesn't have its own detect register */
12572
12573                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12574                         DRM_DEBUG_KMS("probing SDVOC\n");
12575                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12576                 }
12577
12578                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12579
12580                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12581                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12582                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12583                         }
12584                         if (SUPPORTS_INTEGRATED_DP(dev))
12585                                 intel_dp_init(dev, DP_C, PORT_C);
12586                 }
12587
12588                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12589                     (I915_READ(DP_D) & DP_DETECTED))
12590                         intel_dp_init(dev, DP_D, PORT_D);
12591         } else if (IS_GEN2(dev))
12592                 intel_dvo_init(dev);
12593
12594         if (SUPPORTS_TV(dev))
12595                 intel_tv_init(dev);
12596
12597         /*
12598          * FIXME:  We don't have full atomic support yet, but we want to be
12599          * able to enable/test plane updates via the atomic interface in the
12600          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12601          * will take some atomic codepaths to lookup properties during
12602          * drmModeGetConnector() that unconditionally dereference
12603          * connector->state.
12604          *
12605          * We create a dummy connector state here for each connector to ensure
12606          * the DRM core doesn't try to dereference a NULL connector->state.
12607          * The actual connector properties will never be updated or contain
12608          * useful information, but since we're doing this specifically for
12609          * testing/debug of the plane operations (and only when a specific
12610          * kernel module option is given), that shouldn't really matter.
12611          *
12612          * Once atomic support for crtc's + connectors lands, this loop should
12613          * be removed since we'll be setting up real connector state, which
12614          * will contain Intel-specific properties.
12615          */
12616         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12617                 list_for_each_entry(connector,
12618                                     &dev->mode_config.connector_list,
12619                                     head) {
12620                         if (!WARN_ON(connector->state)) {
12621                                 connector->state =
12622                                         kzalloc(sizeof(*connector->state),
12623                                                 GFP_KERNEL);
12624                         }
12625                 }
12626         }
12627
12628         intel_psr_init(dev);
12629
12630         for_each_intel_encoder(dev, encoder) {
12631                 encoder->base.possible_crtcs = encoder->crtc_mask;
12632                 encoder->base.possible_clones =
12633                         intel_encoder_clones(encoder);
12634         }
12635
12636         intel_init_pch_refclk(dev);
12637
12638         drm_helper_move_panel_connectors_to_head(dev);
12639 }
12640
12641 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12642 {
12643         struct drm_device *dev = fb->dev;
12644         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12645
12646         drm_framebuffer_cleanup(fb);
12647         mutex_lock(&dev->struct_mutex);
12648         WARN_ON(!intel_fb->obj->framebuffer_references--);
12649         drm_gem_object_unreference(&intel_fb->obj->base);
12650         mutex_unlock(&dev->struct_mutex);
12651         kfree(intel_fb);
12652 }
12653
12654 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12655                                                 struct drm_file *file,
12656                                                 unsigned int *handle)
12657 {
12658         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12659         struct drm_i915_gem_object *obj = intel_fb->obj;
12660
12661         return drm_gem_handle_create(file, &obj->base, handle);
12662 }
12663
12664 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12665         .destroy = intel_user_framebuffer_destroy,
12666         .create_handle = intel_user_framebuffer_create_handle,
12667 };
12668
12669 static int intel_framebuffer_init(struct drm_device *dev,
12670                                   struct intel_framebuffer *intel_fb,
12671                                   struct drm_mode_fb_cmd2 *mode_cmd,
12672                                   struct drm_i915_gem_object *obj)
12673 {
12674         int aligned_height;
12675         int pitch_limit;
12676         int ret;
12677
12678         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12679
12680         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12681                 /* Enforce that fb modifier and tiling mode match, but only for
12682                  * X-tiled. This is needed for FBC. */
12683                 if (!!(obj->tiling_mode == I915_TILING_X) !=
12684                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12685                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12686                         return -EINVAL;
12687                 }
12688         } else {
12689                 if (obj->tiling_mode == I915_TILING_X)
12690                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12691                 else if (obj->tiling_mode == I915_TILING_Y) {
12692                         DRM_DEBUG("No Y tiling for legacy addfb\n");
12693                         return -EINVAL;
12694                 }
12695         }
12696
12697         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED) {
12698                 DRM_DEBUG("hardware does not support tiling Y\n");
12699                 return -EINVAL;
12700         }
12701
12702         if (mode_cmd->pitches[0] & 63) {
12703                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12704                           mode_cmd->pitches[0]);
12705                 return -EINVAL;
12706         }
12707
12708         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12709                 pitch_limit = 32*1024;
12710         } else if (INTEL_INFO(dev)->gen >= 4) {
12711                 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12712                         pitch_limit = 16*1024;
12713                 else
12714                         pitch_limit = 32*1024;
12715         } else if (INTEL_INFO(dev)->gen >= 3) {
12716                 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12717                         pitch_limit = 8*1024;
12718                 else
12719                         pitch_limit = 16*1024;
12720         } else
12721                 /* XXX DSPC is limited to 4k tiled */
12722                 pitch_limit = 8*1024;
12723
12724         if (mode_cmd->pitches[0] > pitch_limit) {
12725                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12726                           mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED ?
12727                           "tiled" : "linear",
12728                           mode_cmd->pitches[0], pitch_limit);
12729                 return -EINVAL;
12730         }
12731
12732         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12733             mode_cmd->pitches[0] != obj->stride) {
12734                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12735                           mode_cmd->pitches[0], obj->stride);
12736                 return -EINVAL;
12737         }
12738
12739         /* Reject formats not supported by any plane early. */
12740         switch (mode_cmd->pixel_format) {
12741         case DRM_FORMAT_C8:
12742         case DRM_FORMAT_RGB565:
12743         case DRM_FORMAT_XRGB8888:
12744         case DRM_FORMAT_ARGB8888:
12745                 break;
12746         case DRM_FORMAT_XRGB1555:
12747         case DRM_FORMAT_ARGB1555:
12748                 if (INTEL_INFO(dev)->gen > 3) {
12749                         DRM_DEBUG("unsupported pixel format: %s\n",
12750                                   drm_get_format_name(mode_cmd->pixel_format));
12751                         return -EINVAL;
12752                 }
12753                 break;
12754         case DRM_FORMAT_XBGR8888:
12755         case DRM_FORMAT_ABGR8888:
12756         case DRM_FORMAT_XRGB2101010:
12757         case DRM_FORMAT_ARGB2101010:
12758         case DRM_FORMAT_XBGR2101010:
12759         case DRM_FORMAT_ABGR2101010:
12760                 if (INTEL_INFO(dev)->gen < 4) {
12761                         DRM_DEBUG("unsupported pixel format: %s\n",
12762                                   drm_get_format_name(mode_cmd->pixel_format));
12763                         return -EINVAL;
12764                 }
12765                 break;
12766         case DRM_FORMAT_YUYV:
12767         case DRM_FORMAT_UYVY:
12768         case DRM_FORMAT_YVYU:
12769         case DRM_FORMAT_VYUY:
12770                 if (INTEL_INFO(dev)->gen < 5) {
12771                         DRM_DEBUG("unsupported pixel format: %s\n",
12772                                   drm_get_format_name(mode_cmd->pixel_format));
12773                         return -EINVAL;
12774                 }
12775                 break;
12776         default:
12777                 DRM_DEBUG("unsupported pixel format: %s\n",
12778                           drm_get_format_name(mode_cmd->pixel_format));
12779                 return -EINVAL;
12780         }
12781
12782         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12783         if (mode_cmd->offsets[0] != 0)
12784                 return -EINVAL;
12785
12786         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12787                                                mode_cmd->pixel_format,
12788                                                mode_cmd->modifier[0]);
12789         /* FIXME drm helper for size checks (especially planar formats)? */
12790         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12791                 return -EINVAL;
12792
12793         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12794         intel_fb->obj = obj;
12795         intel_fb->obj->framebuffer_references++;
12796
12797         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12798         if (ret) {
12799                 DRM_ERROR("framebuffer init failed %d\n", ret);
12800                 return ret;
12801         }
12802
12803         return 0;
12804 }
12805
12806 static struct drm_framebuffer *
12807 intel_user_framebuffer_create(struct drm_device *dev,
12808                               struct drm_file *filp,
12809                               struct drm_mode_fb_cmd2 *mode_cmd)
12810 {
12811         struct drm_i915_gem_object *obj;
12812
12813         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12814                                                 mode_cmd->handles[0]));
12815         if (&obj->base == NULL)
12816                 return ERR_PTR(-ENOENT);
12817
12818         return intel_framebuffer_create(dev, mode_cmd, obj);
12819 }
12820
12821 #ifndef CONFIG_DRM_I915_FBDEV
12822 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12823 {
12824 }
12825 #endif
12826
12827 static const struct drm_mode_config_funcs intel_mode_funcs = {
12828         .fb_create = intel_user_framebuffer_create,
12829         .output_poll_changed = intel_fbdev_output_poll_changed,
12830         .atomic_check = intel_atomic_check,
12831         .atomic_commit = intel_atomic_commit,
12832 };
12833
12834 /* Set up chip specific display functions */
12835 static void intel_init_display(struct drm_device *dev)
12836 {
12837         struct drm_i915_private *dev_priv = dev->dev_private;
12838
12839         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12840                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12841         else if (IS_CHERRYVIEW(dev))
12842                 dev_priv->display.find_dpll = chv_find_best_dpll;
12843         else if (IS_VALLEYVIEW(dev))
12844                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12845         else if (IS_PINEVIEW(dev))
12846                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12847         else
12848                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12849
12850         if (INTEL_INFO(dev)->gen >= 9) {
12851                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12852                 dev_priv->display.get_initial_plane_config =
12853                         skylake_get_initial_plane_config;
12854                 dev_priv->display.crtc_compute_clock =
12855                         haswell_crtc_compute_clock;
12856                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12857                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12858                 dev_priv->display.off = ironlake_crtc_off;
12859                 dev_priv->display.update_primary_plane =
12860                         skylake_update_primary_plane;
12861         } else if (HAS_DDI(dev)) {
12862                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12863                 dev_priv->display.get_initial_plane_config =
12864                         ironlake_get_initial_plane_config;
12865                 dev_priv->display.crtc_compute_clock =
12866                         haswell_crtc_compute_clock;
12867                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12868                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12869                 dev_priv->display.off = ironlake_crtc_off;
12870                 dev_priv->display.update_primary_plane =
12871                         ironlake_update_primary_plane;
12872         } else if (HAS_PCH_SPLIT(dev)) {
12873                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12874                 dev_priv->display.get_initial_plane_config =
12875                         ironlake_get_initial_plane_config;
12876                 dev_priv->display.crtc_compute_clock =
12877                         ironlake_crtc_compute_clock;
12878                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12879                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12880                 dev_priv->display.off = ironlake_crtc_off;
12881                 dev_priv->display.update_primary_plane =
12882                         ironlake_update_primary_plane;
12883         } else if (IS_VALLEYVIEW(dev)) {
12884                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12885                 dev_priv->display.get_initial_plane_config =
12886                         i9xx_get_initial_plane_config;
12887                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12888                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12889                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12890                 dev_priv->display.off = i9xx_crtc_off;
12891                 dev_priv->display.update_primary_plane =
12892                         i9xx_update_primary_plane;
12893         } else {
12894                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12895                 dev_priv->display.get_initial_plane_config =
12896                         i9xx_get_initial_plane_config;
12897                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12898                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12899                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12900                 dev_priv->display.off = i9xx_crtc_off;
12901                 dev_priv->display.update_primary_plane =
12902                         i9xx_update_primary_plane;
12903         }
12904
12905         /* Returns the core display clock speed */
12906         if (IS_VALLEYVIEW(dev))
12907                 dev_priv->display.get_display_clock_speed =
12908                         valleyview_get_display_clock_speed;
12909         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12910                 dev_priv->display.get_display_clock_speed =
12911                         i945_get_display_clock_speed;
12912         else if (IS_I915G(dev))
12913                 dev_priv->display.get_display_clock_speed =
12914                         i915_get_display_clock_speed;
12915         else if (IS_I945GM(dev) || IS_845G(dev))
12916                 dev_priv->display.get_display_clock_speed =
12917                         i9xx_misc_get_display_clock_speed;
12918         else if (IS_PINEVIEW(dev))
12919                 dev_priv->display.get_display_clock_speed =
12920                         pnv_get_display_clock_speed;
12921         else if (IS_I915GM(dev))
12922                 dev_priv->display.get_display_clock_speed =
12923                         i915gm_get_display_clock_speed;
12924         else if (IS_I865G(dev))
12925                 dev_priv->display.get_display_clock_speed =
12926                         i865_get_display_clock_speed;
12927         else if (IS_I85X(dev))
12928                 dev_priv->display.get_display_clock_speed =
12929                         i855_get_display_clock_speed;
12930         else /* 852, 830 */
12931                 dev_priv->display.get_display_clock_speed =
12932                         i830_get_display_clock_speed;
12933
12934         if (IS_GEN5(dev)) {
12935                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12936         } else if (IS_GEN6(dev)) {
12937                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12938         } else if (IS_IVYBRIDGE(dev)) {
12939                 /* FIXME: detect B0+ stepping and use auto training */
12940                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12941                 dev_priv->display.modeset_global_resources =
12942                         ivb_modeset_global_resources;
12943         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12944                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12945         } else if (IS_VALLEYVIEW(dev)) {
12946                 dev_priv->display.modeset_global_resources =
12947                         valleyview_modeset_global_resources;
12948         }
12949
12950         switch (INTEL_INFO(dev)->gen) {
12951         case 2:
12952                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12953                 break;
12954
12955         case 3:
12956                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12957                 break;
12958
12959         case 4:
12960         case 5:
12961                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12962                 break;
12963
12964         case 6:
12965                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12966                 break;
12967         case 7:
12968         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12969                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12970                 break;
12971         case 9:
12972                 /* Drop through - unsupported since execlist only. */
12973         default:
12974                 /* Default just returns -ENODEV to indicate unsupported */
12975                 dev_priv->display.queue_flip = intel_default_queue_flip;
12976         }
12977
12978         intel_panel_init_backlight_funcs(dev);
12979
12980         mutex_init(&dev_priv->pps_mutex);
12981 }
12982
12983 /*
12984  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12985  * resume, or other times.  This quirk makes sure that's the case for
12986  * affected systems.
12987  */
12988 static void quirk_pipea_force(struct drm_device *dev)
12989 {
12990         struct drm_i915_private *dev_priv = dev->dev_private;
12991
12992         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12993         DRM_INFO("applying pipe a force quirk\n");
12994 }
12995
12996 static void quirk_pipeb_force(struct drm_device *dev)
12997 {
12998         struct drm_i915_private *dev_priv = dev->dev_private;
12999
13000         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13001         DRM_INFO("applying pipe b force quirk\n");
13002 }
13003
13004 /*
13005  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13006  */
13007 static void quirk_ssc_force_disable(struct drm_device *dev)
13008 {
13009         struct drm_i915_private *dev_priv = dev->dev_private;
13010         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13011         DRM_INFO("applying lvds SSC disable quirk\n");
13012 }
13013
13014 /*
13015  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13016  * brightness value
13017  */
13018 static void quirk_invert_brightness(struct drm_device *dev)
13019 {
13020         struct drm_i915_private *dev_priv = dev->dev_private;
13021         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13022         DRM_INFO("applying inverted panel brightness quirk\n");
13023 }
13024
13025 /* Some VBT's incorrectly indicate no backlight is present */
13026 static void quirk_backlight_present(struct drm_device *dev)
13027 {
13028         struct drm_i915_private *dev_priv = dev->dev_private;
13029         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13030         DRM_INFO("applying backlight present quirk\n");
13031 }
13032
13033 struct intel_quirk {
13034         int device;
13035         int subsystem_vendor;
13036         int subsystem_device;
13037         void (*hook)(struct drm_device *dev);
13038 };
13039
13040 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13041 struct intel_dmi_quirk {
13042         void (*hook)(struct drm_device *dev);
13043         const struct dmi_system_id (*dmi_id_list)[];
13044 };
13045
13046 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13047 {
13048         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13049         return 1;
13050 }
13051
13052 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13053         {
13054                 .dmi_id_list = &(const struct dmi_system_id[]) {
13055                         {
13056                                 .callback = intel_dmi_reverse_brightness,
13057                                 .ident = "NCR Corporation",
13058                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13059                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13060                                 },
13061                         },
13062                         { }  /* terminating entry */
13063                 },
13064                 .hook = quirk_invert_brightness,
13065         },
13066 };
13067
13068 static struct intel_quirk intel_quirks[] = {
13069         /* HP Mini needs pipe A force quirk (LP: #322104) */
13070         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13071
13072         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13073         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13074
13075         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13076         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13077
13078         /* 830 needs to leave pipe A & dpll A up */
13079         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13080
13081         /* 830 needs to leave pipe B & dpll B up */
13082         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13083
13084         /* Lenovo U160 cannot use SSC on LVDS */
13085         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13086
13087         /* Sony Vaio Y cannot use SSC on LVDS */
13088         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13089
13090         /* Acer Aspire 5734Z must invert backlight brightness */
13091         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13092
13093         /* Acer/eMachines G725 */
13094         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13095
13096         /* Acer/eMachines e725 */
13097         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13098
13099         /* Acer/Packard Bell NCL20 */
13100         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13101
13102         /* Acer Aspire 4736Z */
13103         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13104
13105         /* Acer Aspire 5336 */
13106         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13107
13108         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13109         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13110
13111         /* Acer C720 Chromebook (Core i3 4005U) */
13112         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13113
13114         /* Apple Macbook 2,1 (Core 2 T7400) */
13115         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13116
13117         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13118         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13119
13120         /* HP Chromebook 14 (Celeron 2955U) */
13121         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13122 };
13123
13124 static void intel_init_quirks(struct drm_device *dev)
13125 {
13126         struct pci_dev *d = dev->pdev;
13127         int i;
13128
13129         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13130                 struct intel_quirk *q = &intel_quirks[i];
13131
13132                 if (d->device == q->device &&
13133                     (d->subsystem_vendor == q->subsystem_vendor ||
13134                      q->subsystem_vendor == PCI_ANY_ID) &&
13135                     (d->subsystem_device == q->subsystem_device ||
13136                      q->subsystem_device == PCI_ANY_ID))
13137                         q->hook(dev);
13138         }
13139         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13140                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13141                         intel_dmi_quirks[i].hook(dev);
13142         }
13143 }
13144
13145 /* Disable the VGA plane that we never use */
13146 static void i915_disable_vga(struct drm_device *dev)
13147 {
13148         struct drm_i915_private *dev_priv = dev->dev_private;
13149         u8 sr1;
13150         u32 vga_reg = i915_vgacntrl_reg(dev);
13151
13152         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13153         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13154         outb(SR01, VGA_SR_INDEX);
13155         sr1 = inb(VGA_SR_DATA);
13156         outb(sr1 | 1<<5, VGA_SR_DATA);
13157         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13158         udelay(300);
13159
13160         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13161         POSTING_READ(vga_reg);
13162 }
13163
13164 void intel_modeset_init_hw(struct drm_device *dev)
13165 {
13166         intel_prepare_ddi(dev);
13167
13168         if (IS_VALLEYVIEW(dev))
13169                 vlv_update_cdclk(dev);
13170
13171         intel_init_clock_gating(dev);
13172
13173         intel_enable_gt_powersave(dev);
13174 }
13175
13176 void intel_modeset_init(struct drm_device *dev)
13177 {
13178         struct drm_i915_private *dev_priv = dev->dev_private;
13179         int sprite, ret;
13180         enum pipe pipe;
13181         struct intel_crtc *crtc;
13182
13183         drm_mode_config_init(dev);
13184
13185         dev->mode_config.min_width = 0;
13186         dev->mode_config.min_height = 0;
13187
13188         dev->mode_config.preferred_depth = 24;
13189         dev->mode_config.prefer_shadow = 1;
13190
13191         dev->mode_config.allow_fb_modifiers = true;
13192
13193         dev->mode_config.funcs = &intel_mode_funcs;
13194
13195         intel_init_quirks(dev);
13196
13197         intel_init_pm(dev);
13198
13199         if (INTEL_INFO(dev)->num_pipes == 0)
13200                 return;
13201
13202         intel_init_display(dev);
13203         intel_init_audio(dev);
13204
13205         if (IS_GEN2(dev)) {
13206                 dev->mode_config.max_width = 2048;
13207                 dev->mode_config.max_height = 2048;
13208         } else if (IS_GEN3(dev)) {
13209                 dev->mode_config.max_width = 4096;
13210                 dev->mode_config.max_height = 4096;
13211         } else {
13212                 dev->mode_config.max_width = 8192;
13213                 dev->mode_config.max_height = 8192;
13214         }
13215
13216         if (IS_845G(dev) || IS_I865G(dev)) {
13217                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13218                 dev->mode_config.cursor_height = 1023;
13219         } else if (IS_GEN2(dev)) {
13220                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13221                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13222         } else {
13223                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13224                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13225         }
13226
13227         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13228
13229         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13230                       INTEL_INFO(dev)->num_pipes,
13231                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13232
13233         for_each_pipe(dev_priv, pipe) {
13234                 intel_crtc_init(dev, pipe);
13235                 for_each_sprite(pipe, sprite) {
13236                         ret = intel_plane_init(dev, pipe, sprite);
13237                         if (ret)
13238                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13239                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13240                 }
13241         }
13242
13243         intel_init_dpio(dev);
13244
13245         intel_shared_dpll_init(dev);
13246
13247         /* Just disable it once at startup */
13248         i915_disable_vga(dev);
13249         intel_setup_outputs(dev);
13250
13251         /* Just in case the BIOS is doing something questionable. */
13252         intel_fbc_disable(dev);
13253
13254         drm_modeset_lock_all(dev);
13255         intel_modeset_setup_hw_state(dev, false);
13256         drm_modeset_unlock_all(dev);
13257
13258         for_each_intel_crtc(dev, crtc) {
13259                 if (!crtc->active)
13260                         continue;
13261
13262                 /*
13263                  * Note that reserving the BIOS fb up front prevents us
13264                  * from stuffing other stolen allocations like the ring
13265                  * on top.  This prevents some ugliness at boot time, and
13266                  * can even allow for smooth boot transitions if the BIOS
13267                  * fb is large enough for the active pipe configuration.
13268                  */
13269                 if (dev_priv->display.get_initial_plane_config) {
13270                         dev_priv->display.get_initial_plane_config(crtc,
13271                                                            &crtc->plane_config);
13272                         /*
13273                          * If the fb is shared between multiple heads, we'll
13274                          * just get the first one.
13275                          */
13276                         intel_find_plane_obj(crtc, &crtc->plane_config);
13277                 }
13278         }
13279 }
13280
13281 static void intel_enable_pipe_a(struct drm_device *dev)
13282 {
13283         struct intel_connector *connector;
13284         struct drm_connector *crt = NULL;
13285         struct intel_load_detect_pipe load_detect_temp;
13286         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13287
13288         /* We can't just switch on the pipe A, we need to set things up with a
13289          * proper mode and output configuration. As a gross hack, enable pipe A
13290          * by enabling the load detect pipe once. */
13291         list_for_each_entry(connector,
13292                             &dev->mode_config.connector_list,
13293                             base.head) {
13294                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13295                         crt = &connector->base;
13296                         break;
13297                 }
13298         }
13299
13300         if (!crt)
13301                 return;
13302
13303         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13304                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13305 }
13306
13307 static bool
13308 intel_check_plane_mapping(struct intel_crtc *crtc)
13309 {
13310         struct drm_device *dev = crtc->base.dev;
13311         struct drm_i915_private *dev_priv = dev->dev_private;
13312         u32 reg, val;
13313
13314         if (INTEL_INFO(dev)->num_pipes == 1)
13315                 return true;
13316
13317         reg = DSPCNTR(!crtc->plane);
13318         val = I915_READ(reg);
13319
13320         if ((val & DISPLAY_PLANE_ENABLE) &&
13321             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13322                 return false;
13323
13324         return true;
13325 }
13326
13327 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13328 {
13329         struct drm_device *dev = crtc->base.dev;
13330         struct drm_i915_private *dev_priv = dev->dev_private;
13331         u32 reg;
13332
13333         /* Clear any frame start delays used for debugging left by the BIOS */
13334         reg = PIPECONF(crtc->config->cpu_transcoder);
13335         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13336
13337         /* restore vblank interrupts to correct state */
13338         drm_crtc_vblank_reset(&crtc->base);
13339         if (crtc->active) {
13340                 update_scanline_offset(crtc);
13341                 drm_crtc_vblank_on(&crtc->base);
13342         }
13343
13344         /* We need to sanitize the plane -> pipe mapping first because this will
13345          * disable the crtc (and hence change the state) if it is wrong. Note
13346          * that gen4+ has a fixed plane -> pipe mapping.  */
13347         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13348                 struct intel_connector *connector;
13349                 bool plane;
13350
13351                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13352                               crtc->base.base.id);
13353
13354                 /* Pipe has the wrong plane attached and the plane is active.
13355                  * Temporarily change the plane mapping and disable everything
13356                  * ...  */
13357                 plane = crtc->plane;
13358                 crtc->plane = !plane;
13359                 crtc->primary_enabled = true;
13360                 dev_priv->display.crtc_disable(&crtc->base);
13361                 crtc->plane = plane;
13362
13363                 /* ... and break all links. */
13364                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13365                                     base.head) {
13366                         if (connector->encoder->base.crtc != &crtc->base)
13367                                 continue;
13368
13369                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13370                         connector->base.encoder = NULL;
13371                 }
13372                 /* multiple connectors may have the same encoder:
13373                  *  handle them and break crtc link separately */
13374                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13375                                     base.head)
13376                         if (connector->encoder->base.crtc == &crtc->base) {
13377                                 connector->encoder->base.crtc = NULL;
13378                                 connector->encoder->connectors_active = false;
13379                         }
13380
13381                 WARN_ON(crtc->active);
13382                 crtc->base.state->enable = false;
13383                 crtc->base.enabled = false;
13384         }
13385
13386         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13387             crtc->pipe == PIPE_A && !crtc->active) {
13388                 /* BIOS forgot to enable pipe A, this mostly happens after
13389                  * resume. Force-enable the pipe to fix this, the update_dpms
13390                  * call below we restore the pipe to the right state, but leave
13391                  * the required bits on. */
13392                 intel_enable_pipe_a(dev);
13393         }
13394
13395         /* Adjust the state of the output pipe according to whether we
13396          * have active connectors/encoders. */
13397         intel_crtc_update_dpms(&crtc->base);
13398
13399         if (crtc->active != crtc->base.state->enable) {
13400                 struct intel_encoder *encoder;
13401
13402                 /* This can happen either due to bugs in the get_hw_state
13403                  * functions or because the pipe is force-enabled due to the
13404                  * pipe A quirk. */
13405                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13406                               crtc->base.base.id,
13407                               crtc->base.state->enable ? "enabled" : "disabled",
13408                               crtc->active ? "enabled" : "disabled");
13409
13410                 crtc->base.state->enable = crtc->active;
13411                 crtc->base.enabled = crtc->active;
13412
13413                 /* Because we only establish the connector -> encoder ->
13414                  * crtc links if something is active, this means the
13415                  * crtc is now deactivated. Break the links. connector
13416                  * -> encoder links are only establish when things are
13417                  *  actually up, hence no need to break them. */
13418                 WARN_ON(crtc->active);
13419
13420                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13421                         WARN_ON(encoder->connectors_active);
13422                         encoder->base.crtc = NULL;
13423                 }
13424         }
13425
13426         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13427                 /*
13428                  * We start out with underrun reporting disabled to avoid races.
13429                  * For correct bookkeeping mark this on active crtcs.
13430                  *
13431                  * Also on gmch platforms we dont have any hardware bits to
13432                  * disable the underrun reporting. Which means we need to start
13433                  * out with underrun reporting disabled also on inactive pipes,
13434                  * since otherwise we'll complain about the garbage we read when
13435                  * e.g. coming up after runtime pm.
13436                  *
13437                  * No protection against concurrent access is required - at
13438                  * worst a fifo underrun happens which also sets this to false.
13439                  */
13440                 crtc->cpu_fifo_underrun_disabled = true;
13441                 crtc->pch_fifo_underrun_disabled = true;
13442         }
13443 }
13444
13445 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13446 {
13447         struct intel_connector *connector;
13448         struct drm_device *dev = encoder->base.dev;
13449
13450         /* We need to check both for a crtc link (meaning that the
13451          * encoder is active and trying to read from a pipe) and the
13452          * pipe itself being active. */
13453         bool has_active_crtc = encoder->base.crtc &&
13454                 to_intel_crtc(encoder->base.crtc)->active;
13455
13456         if (encoder->connectors_active && !has_active_crtc) {
13457                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13458                               encoder->base.base.id,
13459                               encoder->base.name);
13460
13461                 /* Connector is active, but has no active pipe. This is
13462                  * fallout from our resume register restoring. Disable
13463                  * the encoder manually again. */
13464                 if (encoder->base.crtc) {
13465                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13466                                       encoder->base.base.id,
13467                                       encoder->base.name);
13468                         encoder->disable(encoder);
13469                         if (encoder->post_disable)
13470                                 encoder->post_disable(encoder);
13471                 }
13472                 encoder->base.crtc = NULL;
13473                 encoder->connectors_active = false;
13474
13475                 /* Inconsistent output/port/pipe state happens presumably due to
13476                  * a bug in one of the get_hw_state functions. Or someplace else
13477                  * in our code, like the register restore mess on resume. Clamp
13478                  * things to off as a safer default. */
13479                 list_for_each_entry(connector,
13480                                     &dev->mode_config.connector_list,
13481                                     base.head) {
13482                         if (connector->encoder != encoder)
13483                                 continue;
13484                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13485                         connector->base.encoder = NULL;
13486                 }
13487         }
13488         /* Enabled encoders without active connectors will be fixed in
13489          * the crtc fixup. */
13490 }
13491
13492 void i915_redisable_vga_power_on(struct drm_device *dev)
13493 {
13494         struct drm_i915_private *dev_priv = dev->dev_private;
13495         u32 vga_reg = i915_vgacntrl_reg(dev);
13496
13497         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13498                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13499                 i915_disable_vga(dev);
13500         }
13501 }
13502
13503 void i915_redisable_vga(struct drm_device *dev)
13504 {
13505         struct drm_i915_private *dev_priv = dev->dev_private;
13506
13507         /* This function can be called both from intel_modeset_setup_hw_state or
13508          * at a very early point in our resume sequence, where the power well
13509          * structures are not yet restored. Since this function is at a very
13510          * paranoid "someone might have enabled VGA while we were not looking"
13511          * level, just check if the power well is enabled instead of trying to
13512          * follow the "don't touch the power well if we don't need it" policy
13513          * the rest of the driver uses. */
13514         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13515                 return;
13516
13517         i915_redisable_vga_power_on(dev);
13518 }
13519
13520 static bool primary_get_hw_state(struct intel_crtc *crtc)
13521 {
13522         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13523
13524         if (!crtc->active)
13525                 return false;
13526
13527         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13528 }
13529
13530 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13531 {
13532         struct drm_i915_private *dev_priv = dev->dev_private;
13533         enum pipe pipe;
13534         struct intel_crtc *crtc;
13535         struct intel_encoder *encoder;
13536         struct intel_connector *connector;
13537         int i;
13538
13539         for_each_intel_crtc(dev, crtc) {
13540                 memset(crtc->config, 0, sizeof(*crtc->config));
13541
13542                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13543
13544                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13545                                                                  crtc->config);
13546
13547                 crtc->base.state->enable = crtc->active;
13548                 crtc->base.enabled = crtc->active;
13549                 crtc->primary_enabled = primary_get_hw_state(crtc);
13550
13551                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13552                               crtc->base.base.id,
13553                               crtc->active ? "enabled" : "disabled");
13554         }
13555
13556         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13557                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13558
13559                 pll->on = pll->get_hw_state(dev_priv, pll,
13560                                             &pll->config.hw_state);
13561                 pll->active = 0;
13562                 pll->config.crtc_mask = 0;
13563                 for_each_intel_crtc(dev, crtc) {
13564                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13565                                 pll->active++;
13566                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13567                         }
13568                 }
13569
13570                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13571                               pll->name, pll->config.crtc_mask, pll->on);
13572
13573                 if (pll->config.crtc_mask)
13574                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13575         }
13576
13577         for_each_intel_encoder(dev, encoder) {
13578                 pipe = 0;
13579
13580                 if (encoder->get_hw_state(encoder, &pipe)) {
13581                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13582                         encoder->base.crtc = &crtc->base;
13583                         encoder->get_config(encoder, crtc->config);
13584                 } else {
13585                         encoder->base.crtc = NULL;
13586                 }
13587
13588                 encoder->connectors_active = false;
13589                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13590                               encoder->base.base.id,
13591                               encoder->base.name,
13592                               encoder->base.crtc ? "enabled" : "disabled",
13593                               pipe_name(pipe));
13594         }
13595
13596         list_for_each_entry(connector, &dev->mode_config.connector_list,
13597                             base.head) {
13598                 if (connector->get_hw_state(connector)) {
13599                         connector->base.dpms = DRM_MODE_DPMS_ON;
13600                         connector->encoder->connectors_active = true;
13601                         connector->base.encoder = &connector->encoder->base;
13602                 } else {
13603                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13604                         connector->base.encoder = NULL;
13605                 }
13606                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13607                               connector->base.base.id,
13608                               connector->base.name,
13609                               connector->base.encoder ? "enabled" : "disabled");
13610         }
13611 }
13612
13613 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13614  * and i915 state tracking structures. */
13615 void intel_modeset_setup_hw_state(struct drm_device *dev,
13616                                   bool force_restore)
13617 {
13618         struct drm_i915_private *dev_priv = dev->dev_private;
13619         enum pipe pipe;
13620         struct intel_crtc *crtc;
13621         struct intel_encoder *encoder;
13622         int i;
13623
13624         intel_modeset_readout_hw_state(dev);
13625
13626         /*
13627          * Now that we have the config, copy it to each CRTC struct
13628          * Note that this could go away if we move to using crtc_config
13629          * checking everywhere.
13630          */
13631         for_each_intel_crtc(dev, crtc) {
13632                 if (crtc->active && i915.fastboot) {
13633                         intel_mode_from_pipe_config(&crtc->base.mode,
13634                                                     crtc->config);
13635                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13636                                       crtc->base.base.id);
13637                         drm_mode_debug_printmodeline(&crtc->base.mode);
13638                 }
13639         }
13640
13641         /* HW state is read out, now we need to sanitize this mess. */
13642         for_each_intel_encoder(dev, encoder) {
13643                 intel_sanitize_encoder(encoder);
13644         }
13645
13646         for_each_pipe(dev_priv, pipe) {
13647                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13648                 intel_sanitize_crtc(crtc);
13649                 intel_dump_pipe_config(crtc, crtc->config,
13650                                        "[setup_hw_state]");
13651         }
13652
13653         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13654                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13655
13656                 if (!pll->on || pll->active)
13657                         continue;
13658
13659                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13660
13661                 pll->disable(dev_priv, pll);
13662                 pll->on = false;
13663         }
13664
13665         if (IS_GEN9(dev))
13666                 skl_wm_get_hw_state(dev);
13667         else if (HAS_PCH_SPLIT(dev))
13668                 ilk_wm_get_hw_state(dev);
13669
13670         if (force_restore) {
13671                 i915_redisable_vga(dev);
13672
13673                 /*
13674                  * We need to use raw interfaces for restoring state to avoid
13675                  * checking (bogus) intermediate states.
13676                  */
13677                 for_each_pipe(dev_priv, pipe) {
13678                         struct drm_crtc *crtc =
13679                                 dev_priv->pipe_to_crtc_mapping[pipe];
13680
13681                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13682                                        crtc->primary->fb);
13683                 }
13684         } else {
13685                 intel_modeset_update_staged_output_state(dev);
13686         }
13687
13688         intel_modeset_check_state(dev);
13689 }
13690
13691 void intel_modeset_gem_init(struct drm_device *dev)
13692 {
13693         struct drm_i915_private *dev_priv = dev->dev_private;
13694         struct drm_crtc *c;
13695         struct drm_i915_gem_object *obj;
13696
13697         mutex_lock(&dev->struct_mutex);
13698         intel_init_gt_powersave(dev);
13699         mutex_unlock(&dev->struct_mutex);
13700
13701         /*
13702          * There may be no VBT; and if the BIOS enabled SSC we can
13703          * just keep using it to avoid unnecessary flicker.  Whereas if the
13704          * BIOS isn't using it, don't assume it will work even if the VBT
13705          * indicates as much.
13706          */
13707         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13708                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13709                                                 DREF_SSC1_ENABLE);
13710
13711         intel_modeset_init_hw(dev);
13712
13713         intel_setup_overlay(dev);
13714
13715         /*
13716          * Make sure any fbs we allocated at startup are properly
13717          * pinned & fenced.  When we do the allocation it's too early
13718          * for this.
13719          */
13720         mutex_lock(&dev->struct_mutex);
13721         for_each_crtc(dev, c) {
13722                 obj = intel_fb_obj(c->primary->fb);
13723                 if (obj == NULL)
13724                         continue;
13725
13726                 if (intel_pin_and_fence_fb_obj(c->primary,
13727                                                c->primary->fb,
13728                                                NULL)) {
13729                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13730                                   to_intel_crtc(c)->pipe);
13731                         drm_framebuffer_unreference(c->primary->fb);
13732                         c->primary->fb = NULL;
13733                         update_state_fb(c->primary);
13734                 }
13735         }
13736         mutex_unlock(&dev->struct_mutex);
13737
13738         intel_backlight_register(dev);
13739 }
13740
13741 void intel_connector_unregister(struct intel_connector *intel_connector)
13742 {
13743         struct drm_connector *connector = &intel_connector->base;
13744
13745         intel_panel_destroy_backlight(connector);
13746         drm_connector_unregister(connector);
13747 }
13748
13749 void intel_modeset_cleanup(struct drm_device *dev)
13750 {
13751         struct drm_i915_private *dev_priv = dev->dev_private;
13752         struct drm_connector *connector;
13753
13754         intel_disable_gt_powersave(dev);
13755
13756         intel_backlight_unregister(dev);
13757
13758         /*
13759          * Interrupts and polling as the first thing to avoid creating havoc.
13760          * Too much stuff here (turning of connectors, ...) would
13761          * experience fancy races otherwise.
13762          */
13763         intel_irq_uninstall(dev_priv);
13764
13765         /*
13766          * Due to the hpd irq storm handling the hotplug work can re-arm the
13767          * poll handlers. Hence disable polling after hpd handling is shut down.
13768          */
13769         drm_kms_helper_poll_fini(dev);
13770
13771         mutex_lock(&dev->struct_mutex);
13772
13773         intel_unregister_dsm_handler();
13774
13775         intel_fbc_disable(dev);
13776
13777         ironlake_teardown_rc6(dev);
13778
13779         mutex_unlock(&dev->struct_mutex);
13780
13781         /* flush any delayed tasks or pending work */
13782         flush_scheduled_work();
13783
13784         /* destroy the backlight and sysfs files before encoders/connectors */
13785         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13786                 struct intel_connector *intel_connector;
13787
13788                 intel_connector = to_intel_connector(connector);
13789                 intel_connector->unregister(intel_connector);
13790         }
13791
13792         drm_mode_config_cleanup(dev);
13793
13794         intel_cleanup_overlay(dev);
13795
13796         mutex_lock(&dev->struct_mutex);
13797         intel_cleanup_gt_powersave(dev);
13798         mutex_unlock(&dev->struct_mutex);
13799 }
13800
13801 /*
13802  * Return which encoder is currently attached for connector.
13803  */
13804 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13805 {
13806         return &intel_attached_encoder(connector)->base;
13807 }
13808
13809 void intel_connector_attach_encoder(struct intel_connector *connector,
13810                                     struct intel_encoder *encoder)
13811 {
13812         connector->encoder = encoder;
13813         drm_mode_connector_attach_encoder(&connector->base,
13814                                           &encoder->base);
13815 }
13816
13817 /*
13818  * set vga decode state - true == enable VGA decode
13819  */
13820 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13821 {
13822         struct drm_i915_private *dev_priv = dev->dev_private;
13823         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13824         u16 gmch_ctrl;
13825
13826         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13827                 DRM_ERROR("failed to read control word\n");
13828                 return -EIO;
13829         }
13830
13831         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13832                 return 0;
13833
13834         if (state)
13835                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13836         else
13837                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13838
13839         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13840                 DRM_ERROR("failed to write control word\n");
13841                 return -EIO;
13842         }
13843
13844         return 0;
13845 }
13846
13847 struct intel_display_error_state {
13848
13849         u32 power_well_driver;
13850
13851         int num_transcoders;
13852
13853         struct intel_cursor_error_state {
13854                 u32 control;
13855                 u32 position;
13856                 u32 base;
13857                 u32 size;
13858         } cursor[I915_MAX_PIPES];
13859
13860         struct intel_pipe_error_state {
13861                 bool power_domain_on;
13862                 u32 source;
13863                 u32 stat;
13864         } pipe[I915_MAX_PIPES];
13865
13866         struct intel_plane_error_state {
13867                 u32 control;
13868                 u32 stride;
13869                 u32 size;
13870                 u32 pos;
13871                 u32 addr;
13872                 u32 surface;
13873                 u32 tile_offset;
13874         } plane[I915_MAX_PIPES];
13875
13876         struct intel_transcoder_error_state {
13877                 bool power_domain_on;
13878                 enum transcoder cpu_transcoder;
13879
13880                 u32 conf;
13881
13882                 u32 htotal;
13883                 u32 hblank;
13884                 u32 hsync;
13885                 u32 vtotal;
13886                 u32 vblank;
13887                 u32 vsync;
13888         } transcoder[4];
13889 };
13890
13891 struct intel_display_error_state *
13892 intel_display_capture_error_state(struct drm_device *dev)
13893 {
13894         struct drm_i915_private *dev_priv = dev->dev_private;
13895         struct intel_display_error_state *error;
13896         int transcoders[] = {
13897                 TRANSCODER_A,
13898                 TRANSCODER_B,
13899                 TRANSCODER_C,
13900                 TRANSCODER_EDP,
13901         };
13902         int i;
13903
13904         if (INTEL_INFO(dev)->num_pipes == 0)
13905                 return NULL;
13906
13907         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13908         if (error == NULL)
13909                 return NULL;
13910
13911         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13912                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13913
13914         for_each_pipe(dev_priv, i) {
13915                 error->pipe[i].power_domain_on =
13916                         __intel_display_power_is_enabled(dev_priv,
13917                                                          POWER_DOMAIN_PIPE(i));
13918                 if (!error->pipe[i].power_domain_on)
13919                         continue;
13920
13921                 error->cursor[i].control = I915_READ(CURCNTR(i));
13922                 error->cursor[i].position = I915_READ(CURPOS(i));
13923                 error->cursor[i].base = I915_READ(CURBASE(i));
13924
13925                 error->plane[i].control = I915_READ(DSPCNTR(i));
13926                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13927                 if (INTEL_INFO(dev)->gen <= 3) {
13928                         error->plane[i].size = I915_READ(DSPSIZE(i));
13929                         error->plane[i].pos = I915_READ(DSPPOS(i));
13930                 }
13931                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13932                         error->plane[i].addr = I915_READ(DSPADDR(i));
13933                 if (INTEL_INFO(dev)->gen >= 4) {
13934                         error->plane[i].surface = I915_READ(DSPSURF(i));
13935                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13936                 }
13937
13938                 error->pipe[i].source = I915_READ(PIPESRC(i));
13939
13940                 if (HAS_GMCH_DISPLAY(dev))
13941                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13942         }
13943
13944         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13945         if (HAS_DDI(dev_priv->dev))
13946                 error->num_transcoders++; /* Account for eDP. */
13947
13948         for (i = 0; i < error->num_transcoders; i++) {
13949                 enum transcoder cpu_transcoder = transcoders[i];
13950
13951                 error->transcoder[i].power_domain_on =
13952                         __intel_display_power_is_enabled(dev_priv,
13953                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13954                 if (!error->transcoder[i].power_domain_on)
13955                         continue;
13956
13957                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13958
13959                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13960                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13961                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13962                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13963                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13964                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13965                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13966         }
13967
13968         return error;
13969 }
13970
13971 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13972
13973 void
13974 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13975                                 struct drm_device *dev,
13976                                 struct intel_display_error_state *error)
13977 {
13978         struct drm_i915_private *dev_priv = dev->dev_private;
13979         int i;
13980
13981         if (!error)
13982                 return;
13983
13984         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13985         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13986                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13987                            error->power_well_driver);
13988         for_each_pipe(dev_priv, i) {
13989                 err_printf(m, "Pipe [%d]:\n", i);
13990                 err_printf(m, "  Power: %s\n",
13991                            error->pipe[i].power_domain_on ? "on" : "off");
13992                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13993                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13994
13995                 err_printf(m, "Plane [%d]:\n", i);
13996                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13997                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13998                 if (INTEL_INFO(dev)->gen <= 3) {
13999                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14000                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14001                 }
14002                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14003                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14004                 if (INTEL_INFO(dev)->gen >= 4) {
14005                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14006                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14007                 }
14008
14009                 err_printf(m, "Cursor [%d]:\n", i);
14010                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14011                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14012                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14013         }
14014
14015         for (i = 0; i < error->num_transcoders; i++) {
14016                 err_printf(m, "CPU transcoder: %c\n",
14017                            transcoder_name(error->transcoder[i].cpu_transcoder));
14018                 err_printf(m, "  Power: %s\n",
14019                            error->transcoder[i].power_domain_on ? "on" : "off");
14020                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14021                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14022                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14023                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14024                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14025                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14026                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14027         }
14028 }
14029
14030 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14031 {
14032         struct intel_crtc *crtc;
14033
14034         for_each_intel_crtc(dev, crtc) {
14035                 struct intel_unpin_work *work;
14036
14037                 spin_lock_irq(&dev->event_lock);
14038
14039                 work = crtc->unpin_work;
14040
14041                 if (work && work->event &&
14042                     work->event->base.file_priv == file) {
14043                         kfree(work->event);
14044                         work->event = NULL;
14045                 }
14046
14047                 spin_unlock_irq(&dev->event_lock);
14048         }
14049 }