drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265
2266         i915_gem_object_pin_fence(obj);
2267
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343
2344         if (plane_config->size == 0)
2345                 return false;
2346
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362         mutex_lock(&dev->struct_mutex);
2363
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409
2410                 if (!i->active)
2411                         continue;
2412
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544
2545         I915_WRITE(reg, dspcntr);
2546
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648
2649         I915_WRITE(reg, dspcntr);
2650
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765         return 0;
2766 }
2767
2768 static void intel_complete_page_flips(struct drm_device *dev)
2769 {
2770         struct drm_crtc *crtc;
2771
2772         for_each_crtc(dev, crtc) {
2773                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774                 enum plane plane = intel_crtc->plane;
2775
2776                 intel_prepare_page_flip(dev, plane);
2777                 intel_finish_page_flip_plane(dev, plane);
2778         }
2779 }
2780
2781 static void intel_update_primary_planes(struct drm_device *dev)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct drm_crtc *crtc;
2785
2786         for_each_crtc(dev, crtc) {
2787                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788
2789                 drm_modeset_lock(&crtc->mutex, NULL);
2790                 /*
2791                  * FIXME: Once we have proper support for primary planes (and
2792                  * disabling them without disabling the entire crtc) allow again
2793                  * a NULL crtc->primary->fb.
2794                  */
2795                 if (intel_crtc->active && crtc->primary->fb)
2796                         dev_priv->display.update_primary_plane(crtc,
2797                                                                crtc->primary->fb,
2798                                                                crtc->x,
2799                                                                crtc->y);
2800                 drm_modeset_unlock(&crtc->mutex);
2801         }
2802 }
2803
2804 void intel_prepare_reset(struct drm_device *dev)
2805 {
2806         struct drm_i915_private *dev_priv = to_i915(dev);
2807         struct intel_crtc *crtc;
2808
2809         /* no reset support for gen2 */
2810         if (IS_GEN2(dev))
2811                 return;
2812
2813         /* reset doesn't touch the display */
2814         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2815                 return;
2816
2817         drm_modeset_lock_all(dev);
2818
2819         /*
2820          * Disabling the crtcs gracefully seems nicer. Also the
2821          * g33 docs say we should at least disable all the planes.
2822          */
2823         for_each_intel_crtc(dev, crtc) {
2824                 if (crtc->active)
2825                         dev_priv->display.crtc_disable(&crtc->base);
2826         }
2827 }
2828
2829 void intel_finish_reset(struct drm_device *dev)
2830 {
2831         struct drm_i915_private *dev_priv = to_i915(dev);
2832
2833         /*
2834          * Flips in the rings will be nuked by the reset,
2835          * so complete all pending flips so that user space
2836          * will get its events and not get stuck.
2837          */
2838         intel_complete_page_flips(dev);
2839
2840         /* no reset support for gen2 */
2841         if (IS_GEN2(dev))
2842                 return;
2843
2844         /* reset doesn't touch the display */
2845         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2846                 /*
2847                  * Flips in the rings have been nuked by the reset,
2848                  * so update the base address of all primary
2849                  * planes to the the last fb to make sure we're
2850                  * showing the correct fb after a reset.
2851                  */
2852                 intel_update_primary_planes(dev);
2853                 return;
2854         }
2855
2856         /*
2857          * The display has been reset as well,
2858          * so need a full re-initialization.
2859          */
2860         intel_runtime_pm_disable_interrupts(dev_priv);
2861         intel_runtime_pm_enable_interrupts(dev_priv);
2862
2863         intel_modeset_init_hw(dev);
2864
2865         spin_lock_irq(&dev_priv->irq_lock);
2866         if (dev_priv->display.hpd_irq_setup)
2867                 dev_priv->display.hpd_irq_setup(dev);
2868         spin_unlock_irq(&dev_priv->irq_lock);
2869
2870         intel_modeset_setup_hw_state(dev, true);
2871
2872         intel_hpd_init(dev_priv);
2873
2874         drm_modeset_unlock_all(dev);
2875 }
2876
2877 static int
2878 intel_finish_fb(struct drm_framebuffer *old_fb)
2879 {
2880         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2881         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2882         bool was_interruptible = dev_priv->mm.interruptible;
2883         int ret;
2884
2885         /* Big Hammer, we also need to ensure that any pending
2886          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2887          * current scanout is retired before unpinning the old
2888          * framebuffer.
2889          *
2890          * This should only fail upon a hung GPU, in which case we
2891          * can safely continue.
2892          */
2893         dev_priv->mm.interruptible = false;
2894         ret = i915_gem_object_finish_gpu(obj);
2895         dev_priv->mm.interruptible = was_interruptible;
2896
2897         return ret;
2898 }
2899
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905         bool pending;
2906
2907         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2908             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2909                 return false;
2910
2911         spin_lock_irq(&dev->event_lock);
2912         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2913         spin_unlock_irq(&dev->event_lock);
2914
2915         return pending;
2916 }
2917
2918 static void intel_update_pipe_size(struct intel_crtc *crtc)
2919 {
2920         struct drm_device *dev = crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         const struct drm_display_mode *adjusted_mode;
2923
2924         if (!i915.fastboot)
2925                 return;
2926
2927         /*
2928          * Update pipe size and adjust fitter if needed: the reason for this is
2929          * that in compute_mode_changes we check the native mode (not the pfit
2930          * mode) to see if we can flip rather than do a full mode set. In the
2931          * fastboot case, we'll flip, but if we don't update the pipesrc and
2932          * pfit state, we'll end up with a big fb scanned out into the wrong
2933          * sized surface.
2934          *
2935          * To fix this properly, we need to hoist the checks up into
2936          * compute_mode_changes (or above), check the actual pfit state and
2937          * whether the platform allows pfit disable with pipe active, and only
2938          * then update the pipesrc and pfit state, even on the flip path.
2939          */
2940
2941         adjusted_mode = &crtc->config.adjusted_mode;
2942
2943         I915_WRITE(PIPESRC(crtc->pipe),
2944                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2945                    (adjusted_mode->crtc_vdisplay - 1));
2946         if (!crtc->config.pch_pfit.enabled &&
2947             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2948              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2949                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2950                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2951                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2952         }
2953         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2954         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2955 }
2956
2957 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2958 {
2959         struct drm_device *dev = crtc->dev;
2960         struct drm_i915_private *dev_priv = dev->dev_private;
2961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2962         int pipe = intel_crtc->pipe;
2963         u32 reg, temp;
2964
2965         /* enable normal train */
2966         reg = FDI_TX_CTL(pipe);
2967         temp = I915_READ(reg);
2968         if (IS_IVYBRIDGE(dev)) {
2969                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2970                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2971         } else {
2972                 temp &= ~FDI_LINK_TRAIN_NONE;
2973                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2974         }
2975         I915_WRITE(reg, temp);
2976
2977         reg = FDI_RX_CTL(pipe);
2978         temp = I915_READ(reg);
2979         if (HAS_PCH_CPT(dev)) {
2980                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2981                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2982         } else {
2983                 temp &= ~FDI_LINK_TRAIN_NONE;
2984                 temp |= FDI_LINK_TRAIN_NONE;
2985         }
2986         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2987
2988         /* wait one idle pattern time */
2989         POSTING_READ(reg);
2990         udelay(1000);
2991
2992         /* IVB wants error correction enabled */
2993         if (IS_IVYBRIDGE(dev))
2994                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2995                            FDI_FE_ERRC_ENABLE);
2996 }
2997
2998 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2999 {
3000         return crtc->base.enabled && crtc->active &&
3001                 crtc->config.has_pch_encoder;
3002 }
3003
3004 static void ivb_modeset_global_resources(struct drm_device *dev)
3005 {
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         struct intel_crtc *pipe_B_crtc =
3008                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3009         struct intel_crtc *pipe_C_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3011         uint32_t temp;
3012
3013         /*
3014          * When everything is off disable fdi C so that we could enable fdi B
3015          * with all lanes. Note that we don't care about enabled pipes without
3016          * an enabled pch encoder.
3017          */
3018         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3019             !pipe_has_enabled_pch(pipe_C_crtc)) {
3020                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3021                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3022
3023                 temp = I915_READ(SOUTH_CHICKEN1);
3024                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3025                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3026                 I915_WRITE(SOUTH_CHICKEN1, temp);
3027         }
3028 }
3029
3030 /* The FDI link training functions for ILK/Ibexpeak. */
3031 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3032 {
3033         struct drm_device *dev = crtc->dev;
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3036         int pipe = intel_crtc->pipe;
3037         u32 reg, temp, tries;
3038
3039         /* FDI needs bits from pipe first */
3040         assert_pipe_enabled(dev_priv, pipe);
3041
3042         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3043            for train result */
3044         reg = FDI_RX_IMR(pipe);
3045         temp = I915_READ(reg);
3046         temp &= ~FDI_RX_SYMBOL_LOCK;
3047         temp &= ~FDI_RX_BIT_LOCK;
3048         I915_WRITE(reg, temp);
3049         I915_READ(reg);
3050         udelay(150);
3051
3052         /* enable CPU FDI TX and PCH FDI RX */
3053         reg = FDI_TX_CTL(pipe);
3054         temp = I915_READ(reg);
3055         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3056         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3057         temp &= ~FDI_LINK_TRAIN_NONE;
3058         temp |= FDI_LINK_TRAIN_PATTERN_1;
3059         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3060
3061         reg = FDI_RX_CTL(pipe);
3062         temp = I915_READ(reg);
3063         temp &= ~FDI_LINK_TRAIN_NONE;
3064         temp |= FDI_LINK_TRAIN_PATTERN_1;
3065         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3066
3067         POSTING_READ(reg);
3068         udelay(150);
3069
3070         /* Ironlake workaround, enable clock pointer after FDI enable*/
3071         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3072         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3073                    FDI_RX_PHASE_SYNC_POINTER_EN);
3074
3075         reg = FDI_RX_IIR(pipe);
3076         for (tries = 0; tries < 5; tries++) {
3077                 temp = I915_READ(reg);
3078                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3079
3080                 if ((temp & FDI_RX_BIT_LOCK)) {
3081                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3082                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3083                         break;
3084                 }
3085         }
3086         if (tries == 5)
3087                 DRM_ERROR("FDI train 1 fail!\n");
3088
3089         /* Train 2 */
3090         reg = FDI_TX_CTL(pipe);
3091         temp = I915_READ(reg);
3092         temp &= ~FDI_LINK_TRAIN_NONE;
3093         temp |= FDI_LINK_TRAIN_PATTERN_2;
3094         I915_WRITE(reg, temp);
3095
3096         reg = FDI_RX_CTL(pipe);
3097         temp = I915_READ(reg);
3098         temp &= ~FDI_LINK_TRAIN_NONE;
3099         temp |= FDI_LINK_TRAIN_PATTERN_2;
3100         I915_WRITE(reg, temp);
3101
3102         POSTING_READ(reg);
3103         udelay(150);
3104
3105         reg = FDI_RX_IIR(pipe);
3106         for (tries = 0; tries < 5; tries++) {
3107                 temp = I915_READ(reg);
3108                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3109
3110                 if (temp & FDI_RX_SYMBOL_LOCK) {
3111                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3112                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3113                         break;
3114                 }
3115         }
3116         if (tries == 5)
3117                 DRM_ERROR("FDI train 2 fail!\n");
3118
3119         DRM_DEBUG_KMS("FDI train done\n");
3120
3121 }
3122
3123 static const int snb_b_fdi_train_param[] = {
3124         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3125         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3126         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3127         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3128 };
3129
3130 /* The FDI link training functions for SNB/Cougarpoint. */
3131 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3132 {
3133         struct drm_device *dev = crtc->dev;
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136         int pipe = intel_crtc->pipe;
3137         u32 reg, temp, i, retry;
3138
3139         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3140            for train result */
3141         reg = FDI_RX_IMR(pipe);
3142         temp = I915_READ(reg);
3143         temp &= ~FDI_RX_SYMBOL_LOCK;
3144         temp &= ~FDI_RX_BIT_LOCK;
3145         I915_WRITE(reg, temp);
3146
3147         POSTING_READ(reg);
3148         udelay(150);
3149
3150         /* enable CPU FDI TX and PCH FDI RX */
3151         reg = FDI_TX_CTL(pipe);
3152         temp = I915_READ(reg);
3153         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3154         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3155         temp &= ~FDI_LINK_TRAIN_NONE;
3156         temp |= FDI_LINK_TRAIN_PATTERN_1;
3157         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3158         /* SNB-B */
3159         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3160         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3161
3162         I915_WRITE(FDI_RX_MISC(pipe),
3163                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3164
3165         reg = FDI_RX_CTL(pipe);
3166         temp = I915_READ(reg);
3167         if (HAS_PCH_CPT(dev)) {
3168                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3169                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3170         } else {
3171                 temp &= ~FDI_LINK_TRAIN_NONE;
3172                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3173         }
3174         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3175
3176         POSTING_READ(reg);
3177         udelay(150);
3178
3179         for (i = 0; i < 4; i++) {
3180                 reg = FDI_TX_CTL(pipe);
3181                 temp = I915_READ(reg);
3182                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3183                 temp |= snb_b_fdi_train_param[i];
3184                 I915_WRITE(reg, temp);
3185
3186                 POSTING_READ(reg);
3187                 udelay(500);
3188
3189                 for (retry = 0; retry < 5; retry++) {
3190                         reg = FDI_RX_IIR(pipe);
3191                         temp = I915_READ(reg);
3192                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3193                         if (temp & FDI_RX_BIT_LOCK) {
3194                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3195                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3196                                 break;
3197                         }
3198                         udelay(50);
3199                 }
3200                 if (retry < 5)
3201                         break;
3202         }
3203         if (i == 4)
3204                 DRM_ERROR("FDI train 1 fail!\n");
3205
3206         /* Train 2 */
3207         reg = FDI_TX_CTL(pipe);
3208         temp = I915_READ(reg);
3209         temp &= ~FDI_LINK_TRAIN_NONE;
3210         temp |= FDI_LINK_TRAIN_PATTERN_2;
3211         if (IS_GEN6(dev)) {
3212                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3213                 /* SNB-B */
3214                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3215         }
3216         I915_WRITE(reg, temp);
3217
3218         reg = FDI_RX_CTL(pipe);
3219         temp = I915_READ(reg);
3220         if (HAS_PCH_CPT(dev)) {
3221                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3222                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3223         } else {
3224                 temp &= ~FDI_LINK_TRAIN_NONE;
3225                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3226         }
3227         I915_WRITE(reg, temp);
3228
3229         POSTING_READ(reg);
3230         udelay(150);
3231
3232         for (i = 0; i < 4; i++) {
3233                 reg = FDI_TX_CTL(pipe);
3234                 temp = I915_READ(reg);
3235                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3236                 temp |= snb_b_fdi_train_param[i];
3237                 I915_WRITE(reg, temp);
3238
3239                 POSTING_READ(reg);
3240                 udelay(500);
3241
3242                 for (retry = 0; retry < 5; retry++) {
3243                         reg = FDI_RX_IIR(pipe);
3244                         temp = I915_READ(reg);
3245                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3246                         if (temp & FDI_RX_SYMBOL_LOCK) {
3247                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3248                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3249                                 break;
3250                         }
3251                         udelay(50);
3252                 }
3253                 if (retry < 5)
3254                         break;
3255         }
3256         if (i == 4)
3257                 DRM_ERROR("FDI train 2 fail!\n");
3258
3259         DRM_DEBUG_KMS("FDI train done.\n");
3260 }
3261
3262 /* Manual link training for Ivy Bridge A0 parts */
3263 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3264 {
3265         struct drm_device *dev = crtc->dev;
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3268         int pipe = intel_crtc->pipe;
3269         u32 reg, temp, i, j;
3270
3271         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3272            for train result */
3273         reg = FDI_RX_IMR(pipe);
3274         temp = I915_READ(reg);
3275         temp &= ~FDI_RX_SYMBOL_LOCK;
3276         temp &= ~FDI_RX_BIT_LOCK;
3277         I915_WRITE(reg, temp);
3278
3279         POSTING_READ(reg);
3280         udelay(150);
3281
3282         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3283                       I915_READ(FDI_RX_IIR(pipe)));
3284
3285         /* Try each vswing and preemphasis setting twice before moving on */
3286         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3287                 /* disable first in case we need to retry */
3288                 reg = FDI_TX_CTL(pipe);
3289                 temp = I915_READ(reg);
3290                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3291                 temp &= ~FDI_TX_ENABLE;
3292                 I915_WRITE(reg, temp);
3293
3294                 reg = FDI_RX_CTL(pipe);
3295                 temp = I915_READ(reg);
3296                 temp &= ~FDI_LINK_TRAIN_AUTO;
3297                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3298                 temp &= ~FDI_RX_ENABLE;
3299                 I915_WRITE(reg, temp);
3300
3301                 /* enable CPU FDI TX and PCH FDI RX */
3302                 reg = FDI_TX_CTL(pipe);
3303                 temp = I915_READ(reg);
3304                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3305                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3306                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3307                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3308                 temp |= snb_b_fdi_train_param[j/2];
3309                 temp |= FDI_COMPOSITE_SYNC;
3310                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3311
3312                 I915_WRITE(FDI_RX_MISC(pipe),
3313                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3314
3315                 reg = FDI_RX_CTL(pipe);
3316                 temp = I915_READ(reg);
3317                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3318                 temp |= FDI_COMPOSITE_SYNC;
3319                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3320
3321                 POSTING_READ(reg);
3322                 udelay(1); /* should be 0.5us */
3323
3324                 for (i = 0; i < 4; i++) {
3325                         reg = FDI_RX_IIR(pipe);
3326                         temp = I915_READ(reg);
3327                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3328
3329                         if (temp & FDI_RX_BIT_LOCK ||
3330                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3331                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3332                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3333                                               i);
3334                                 break;
3335                         }
3336                         udelay(1); /* should be 0.5us */
3337                 }
3338                 if (i == 4) {
3339                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3340                         continue;
3341                 }
3342
3343                 /* Train 2 */
3344                 reg = FDI_TX_CTL(pipe);
3345                 temp = I915_READ(reg);
3346                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3347                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3348                 I915_WRITE(reg, temp);
3349
3350                 reg = FDI_RX_CTL(pipe);
3351                 temp = I915_READ(reg);
3352                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3353                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3354                 I915_WRITE(reg, temp);
3355
3356                 POSTING_READ(reg);
3357                 udelay(2); /* should be 1.5us */
3358
3359                 for (i = 0; i < 4; i++) {
3360                         reg = FDI_RX_IIR(pipe);
3361                         temp = I915_READ(reg);
3362                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3363
3364                         if (temp & FDI_RX_SYMBOL_LOCK ||
3365                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3366                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3367                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3368                                               i);
3369                                 goto train_done;
3370                         }
3371                         udelay(2); /* should be 1.5us */
3372                 }
3373                 if (i == 4)
3374                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3375         }
3376
3377 train_done:
3378         DRM_DEBUG_KMS("FDI train done.\n");
3379 }
3380
3381 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3382 {
3383         struct drm_device *dev = intel_crtc->base.dev;
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385         int pipe = intel_crtc->pipe;
3386         u32 reg, temp;
3387
3388
3389         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3390         reg = FDI_RX_CTL(pipe);
3391         temp = I915_READ(reg);
3392         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3393         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3394         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3395         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3396
3397         POSTING_READ(reg);
3398         udelay(200);
3399
3400         /* Switch from Rawclk to PCDclk */
3401         temp = I915_READ(reg);
3402         I915_WRITE(reg, temp | FDI_PCDCLK);
3403
3404         POSTING_READ(reg);
3405         udelay(200);
3406
3407         /* Enable CPU FDI TX PLL, always on for Ironlake */
3408         reg = FDI_TX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3411                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3412
3413                 POSTING_READ(reg);
3414                 udelay(100);
3415         }
3416 }
3417
3418 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3419 {
3420         struct drm_device *dev = intel_crtc->base.dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         int pipe = intel_crtc->pipe;
3423         u32 reg, temp;
3424
3425         /* Switch from PCDclk to Rawclk */
3426         reg = FDI_RX_CTL(pipe);
3427         temp = I915_READ(reg);
3428         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3429
3430         /* Disable CPU FDI TX PLL */
3431         reg = FDI_TX_CTL(pipe);
3432         temp = I915_READ(reg);
3433         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3434
3435         POSTING_READ(reg);
3436         udelay(100);
3437
3438         reg = FDI_RX_CTL(pipe);
3439         temp = I915_READ(reg);
3440         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3441
3442         /* Wait for the clocks to turn off. */
3443         POSTING_READ(reg);
3444         udelay(100);
3445 }
3446
3447 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3448 {
3449         struct drm_device *dev = crtc->dev;
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         int pipe = intel_crtc->pipe;
3453         u32 reg, temp;
3454
3455         /* disable CPU FDI tx and PCH FDI rx */
3456         reg = FDI_TX_CTL(pipe);
3457         temp = I915_READ(reg);
3458         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3459         POSTING_READ(reg);
3460
3461         reg = FDI_RX_CTL(pipe);
3462         temp = I915_READ(reg);
3463         temp &= ~(0x7 << 16);
3464         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3465         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3466
3467         POSTING_READ(reg);
3468         udelay(100);
3469
3470         /* Ironlake workaround, disable clock pointer after downing FDI */
3471         if (HAS_PCH_IBX(dev))
3472                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3473
3474         /* still set train pattern 1 */
3475         reg = FDI_TX_CTL(pipe);
3476         temp = I915_READ(reg);
3477         temp &= ~FDI_LINK_TRAIN_NONE;
3478         temp |= FDI_LINK_TRAIN_PATTERN_1;
3479         I915_WRITE(reg, temp);
3480
3481         reg = FDI_RX_CTL(pipe);
3482         temp = I915_READ(reg);
3483         if (HAS_PCH_CPT(dev)) {
3484                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3485                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3486         } else {
3487                 temp &= ~FDI_LINK_TRAIN_NONE;
3488                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3489         }
3490         /* BPC in FDI rx is consistent with that in PIPECONF */
3491         temp &= ~(0x07 << 16);
3492         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3493         I915_WRITE(reg, temp);
3494
3495         POSTING_READ(reg);
3496         udelay(100);
3497 }
3498
3499 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3500 {
3501         struct intel_crtc *crtc;
3502
3503         /* Note that we don't need to be called with mode_config.lock here
3504          * as our list of CRTC objects is static for the lifetime of the
3505          * device and so cannot disappear as we iterate. Similarly, we can
3506          * happily treat the predicates as racy, atomic checks as userspace
3507          * cannot claim and pin a new fb without at least acquring the
3508          * struct_mutex and so serialising with us.
3509          */
3510         for_each_intel_crtc(dev, crtc) {
3511                 if (atomic_read(&crtc->unpin_work_count) == 0)
3512                         continue;
3513
3514                 if (crtc->unpin_work)
3515                         intel_wait_for_vblank(dev, crtc->pipe);
3516
3517                 return true;
3518         }
3519
3520         return false;
3521 }
3522
3523 static void page_flip_completed(struct intel_crtc *intel_crtc)
3524 {
3525         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3526         struct intel_unpin_work *work = intel_crtc->unpin_work;
3527
3528         /* ensure that the unpin work is consistent wrt ->pending. */
3529         smp_rmb();
3530         intel_crtc->unpin_work = NULL;
3531
3532         if (work->event)
3533                 drm_send_vblank_event(intel_crtc->base.dev,
3534                                       intel_crtc->pipe,
3535                                       work->event);
3536
3537         drm_crtc_vblank_put(&intel_crtc->base);
3538
3539         wake_up_all(&dev_priv->pending_flip_queue);
3540         queue_work(dev_priv->wq, &work->work);
3541
3542         trace_i915_flip_complete(intel_crtc->plane,
3543                                  work->pending_flip_obj);
3544 }
3545
3546 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3547 {
3548         struct drm_device *dev = crtc->dev;
3549         struct drm_i915_private *dev_priv = dev->dev_private;
3550
3551         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3552         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3553                                        !intel_crtc_has_pending_flip(crtc),
3554                                        60*HZ) == 0)) {
3555                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3556
3557                 spin_lock_irq(&dev->event_lock);
3558                 if (intel_crtc->unpin_work) {
3559                         WARN_ONCE(1, "Removing stuck page flip\n");
3560                         page_flip_completed(intel_crtc);
3561                 }
3562                 spin_unlock_irq(&dev->event_lock);
3563         }
3564
3565         if (crtc->primary->fb) {
3566                 mutex_lock(&dev->struct_mutex);
3567                 intel_finish_fb(crtc->primary->fb);
3568                 mutex_unlock(&dev->struct_mutex);
3569         }
3570 }
3571
3572 /* Program iCLKIP clock to the desired frequency */
3573 static void lpt_program_iclkip(struct drm_crtc *crtc)
3574 {
3575         struct drm_device *dev = crtc->dev;
3576         struct drm_i915_private *dev_priv = dev->dev_private;
3577         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3578         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3579         u32 temp;
3580
3581         mutex_lock(&dev_priv->dpio_lock);
3582
3583         /* It is necessary to ungate the pixclk gate prior to programming
3584          * the divisors, and gate it back when it is done.
3585          */
3586         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3587
3588         /* Disable SSCCTL */
3589         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3590                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3591                                 SBI_SSCCTL_DISABLE,
3592                         SBI_ICLK);
3593
3594         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3595         if (clock == 20000) {
3596                 auxdiv = 1;
3597                 divsel = 0x41;
3598                 phaseinc = 0x20;
3599         } else {
3600                 /* The iCLK virtual clock root frequency is in MHz,
3601                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3602                  * divisors, it is necessary to divide one by another, so we
3603                  * convert the virtual clock precision to KHz here for higher
3604                  * precision.
3605                  */
3606                 u32 iclk_virtual_root_freq = 172800 * 1000;
3607                 u32 iclk_pi_range = 64;
3608                 u32 desired_divisor, msb_divisor_value, pi_value;
3609
3610                 desired_divisor = (iclk_virtual_root_freq / clock);
3611                 msb_divisor_value = desired_divisor / iclk_pi_range;
3612                 pi_value = desired_divisor % iclk_pi_range;
3613
3614                 auxdiv = 0;
3615                 divsel = msb_divisor_value - 2;
3616                 phaseinc = pi_value;
3617         }
3618
3619         /* This should not happen with any sane values */
3620         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3621                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3623                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3624
3625         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3626                         clock,
3627                         auxdiv,
3628                         divsel,
3629                         phasedir,
3630                         phaseinc);
3631
3632         /* Program SSCDIVINTPHASE6 */
3633         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3634         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3635         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3636         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3638         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3639         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3640         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3641
3642         /* Program SSCAUXDIV */
3643         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3644         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3645         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3646         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3647
3648         /* Enable modulator and associated divider */
3649         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3650         temp &= ~SBI_SSCCTL_DISABLE;
3651         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3652
3653         /* Wait for initialization time */
3654         udelay(24);
3655
3656         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3657
3658         mutex_unlock(&dev_priv->dpio_lock);
3659 }
3660
3661 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3662                                                 enum pipe pch_transcoder)
3663 {
3664         struct drm_device *dev = crtc->base.dev;
3665         struct drm_i915_private *dev_priv = dev->dev_private;
3666         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3667
3668         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3669                    I915_READ(HTOTAL(cpu_transcoder)));
3670         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3671                    I915_READ(HBLANK(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3673                    I915_READ(HSYNC(cpu_transcoder)));
3674
3675         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3676                    I915_READ(VTOTAL(cpu_transcoder)));
3677         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3678                    I915_READ(VBLANK(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3680                    I915_READ(VSYNC(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3682                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3683 }
3684
3685 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3686 {
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         uint32_t temp;
3689
3690         temp = I915_READ(SOUTH_CHICKEN1);
3691         if (temp & FDI_BC_BIFURCATION_SELECT)
3692                 return;
3693
3694         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3695         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3696
3697         temp |= FDI_BC_BIFURCATION_SELECT;
3698         DRM_DEBUG_KMS("enabling fdi C rx\n");
3699         I915_WRITE(SOUTH_CHICKEN1, temp);
3700         POSTING_READ(SOUTH_CHICKEN1);
3701 }
3702
3703 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3704 {
3705         struct drm_device *dev = intel_crtc->base.dev;
3706         struct drm_i915_private *dev_priv = dev->dev_private;
3707
3708         switch (intel_crtc->pipe) {
3709         case PIPE_A:
3710                 break;
3711         case PIPE_B:
3712                 if (intel_crtc->config.fdi_lanes > 2)
3713                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3714                 else
3715                         cpt_enable_fdi_bc_bifurcation(dev);
3716
3717                 break;
3718         case PIPE_C:
3719                 cpt_enable_fdi_bc_bifurcation(dev);
3720
3721                 break;
3722         default:
3723                 BUG();
3724         }
3725 }
3726
3727 /*
3728  * Enable PCH resources required for PCH ports:
3729  *   - PCH PLLs
3730  *   - FDI training & RX/TX
3731  *   - update transcoder timings
3732  *   - DP transcoding bits
3733  *   - transcoder
3734  */
3735 static void ironlake_pch_enable(struct drm_crtc *crtc)
3736 {
3737         struct drm_device *dev = crtc->dev;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740         int pipe = intel_crtc->pipe;
3741         u32 reg, temp;
3742
3743         assert_pch_transcoder_disabled(dev_priv, pipe);
3744
3745         if (IS_IVYBRIDGE(dev))
3746                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3747
3748         /* Write the TU size bits before fdi link training, so that error
3749          * detection works. */
3750         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3751                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3752
3753         /* For PCH output, training FDI link */
3754         dev_priv->display.fdi_link_train(crtc);
3755
3756         /* We need to program the right clock selection before writing the pixel
3757          * mutliplier into the DPLL. */
3758         if (HAS_PCH_CPT(dev)) {
3759                 u32 sel;
3760
3761                 temp = I915_READ(PCH_DPLL_SEL);
3762                 temp |= TRANS_DPLL_ENABLE(pipe);
3763                 sel = TRANS_DPLLB_SEL(pipe);
3764                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3765                         temp |= sel;
3766                 else
3767                         temp &= ~sel;
3768                 I915_WRITE(PCH_DPLL_SEL, temp);
3769         }
3770
3771         /* XXX: pch pll's can be enabled any time before we enable the PCH
3772          * transcoder, and we actually should do this to not upset any PCH
3773          * transcoder that already use the clock when we share it.
3774          *
3775          * Note that enable_shared_dpll tries to do the right thing, but
3776          * get_shared_dpll unconditionally resets the pll - we need that to have
3777          * the right LVDS enable sequence. */
3778         intel_enable_shared_dpll(intel_crtc);
3779
3780         /* set transcoder timing, panel must allow it */
3781         assert_panel_unlocked(dev_priv, pipe);
3782         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3783
3784         intel_fdi_normal_train(crtc);
3785
3786         /* For PCH DP, enable TRANS_DP_CTL */
3787         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3788                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3789                 reg = TRANS_DP_CTL(pipe);
3790                 temp = I915_READ(reg);
3791                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3792                           TRANS_DP_SYNC_MASK |
3793                           TRANS_DP_BPC_MASK);
3794                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3795                          TRANS_DP_ENH_FRAMING);
3796                 temp |= bpc << 9; /* same format but at 11:9 */
3797
3798                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3799                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3801                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3802
3803                 switch (intel_trans_dp_port_sel(crtc)) {
3804                 case PCH_DP_B:
3805                         temp |= TRANS_DP_PORT_SEL_B;
3806                         break;
3807                 case PCH_DP_C:
3808                         temp |= TRANS_DP_PORT_SEL_C;
3809                         break;
3810                 case PCH_DP_D:
3811                         temp |= TRANS_DP_PORT_SEL_D;
3812                         break;
3813                 default:
3814                         BUG();
3815                 }
3816
3817                 I915_WRITE(reg, temp);
3818         }
3819
3820         ironlake_enable_pch_transcoder(dev_priv, pipe);
3821 }
3822
3823 static void lpt_pch_enable(struct drm_crtc *crtc)
3824 {
3825         struct drm_device *dev = crtc->dev;
3826         struct drm_i915_private *dev_priv = dev->dev_private;
3827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3829
3830         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3831
3832         lpt_program_iclkip(crtc);
3833
3834         /* Set transcoder timing. */
3835         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3836
3837         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3838 }
3839
3840 void intel_put_shared_dpll(struct intel_crtc *crtc)
3841 {
3842         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3843
3844         if (pll == NULL)
3845                 return;
3846
3847         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3848                 WARN(1, "bad %s crtc mask\n", pll->name);
3849                 return;
3850         }
3851
3852         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3853         if (pll->config.crtc_mask == 0) {
3854                 WARN_ON(pll->on);
3855                 WARN_ON(pll->active);
3856         }
3857
3858         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3859 }
3860
3861 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3862 {
3863         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3864         struct intel_shared_dpll *pll;
3865         enum intel_dpll_id i;
3866
3867         if (HAS_PCH_IBX(dev_priv->dev)) {
3868                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3869                 i = (enum intel_dpll_id) crtc->pipe;
3870                 pll = &dev_priv->shared_dplls[i];
3871
3872                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3873                               crtc->base.base.id, pll->name);
3874
3875                 WARN_ON(pll->new_config->crtc_mask);
3876
3877                 goto found;
3878         }
3879
3880         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3881                 pll = &dev_priv->shared_dplls[i];
3882
3883                 /* Only want to check enabled timings first */
3884                 if (pll->new_config->crtc_mask == 0)
3885                         continue;
3886
3887                 if (memcmp(&crtc->new_config->dpll_hw_state,
3888                            &pll->new_config->hw_state,
3889                            sizeof(pll->new_config->hw_state)) == 0) {
3890                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3891                                       crtc->base.base.id, pll->name,
3892                                       pll->new_config->crtc_mask,
3893                                       pll->active);
3894                         goto found;
3895                 }
3896         }
3897
3898         /* Ok no matching timings, maybe there's a free one? */
3899         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3900                 pll = &dev_priv->shared_dplls[i];
3901                 if (pll->new_config->crtc_mask == 0) {
3902                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3903                                       crtc->base.base.id, pll->name);
3904                         goto found;
3905                 }
3906         }
3907
3908         return NULL;
3909
3910 found:
3911         if (pll->new_config->crtc_mask == 0)
3912                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3913
3914         crtc->new_config->shared_dpll = i;
3915         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3916                          pipe_name(crtc->pipe));
3917
3918         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3919
3920         return pll;
3921 }
3922
3923 /**
3924  * intel_shared_dpll_start_config - start a new PLL staged config
3925  * @dev_priv: DRM device
3926  * @clear_pipes: mask of pipes that will have their PLLs freed
3927  *
3928  * Starts a new PLL staged config, copying the current config but
3929  * releasing the references of pipes specified in clear_pipes.
3930  */
3931 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3932                                           unsigned clear_pipes)
3933 {
3934         struct intel_shared_dpll *pll;
3935         enum intel_dpll_id i;
3936
3937         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3938                 pll = &dev_priv->shared_dplls[i];
3939
3940                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3941                                           GFP_KERNEL);
3942                 if (!pll->new_config)
3943                         goto cleanup;
3944
3945                 pll->new_config->crtc_mask &= ~clear_pipes;
3946         }
3947
3948         return 0;
3949
3950 cleanup:
3951         while (--i >= 0) {
3952                 pll = &dev_priv->shared_dplls[i];
3953                 kfree(pll->new_config);
3954                 pll->new_config = NULL;
3955         }
3956
3957         return -ENOMEM;
3958 }
3959
3960 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3961 {
3962         struct intel_shared_dpll *pll;
3963         enum intel_dpll_id i;
3964
3965         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3966                 pll = &dev_priv->shared_dplls[i];
3967
3968                 WARN_ON(pll->new_config == &pll->config);
3969
3970                 pll->config = *pll->new_config;
3971                 kfree(pll->new_config);
3972                 pll->new_config = NULL;
3973         }
3974 }
3975
3976 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3977 {
3978         struct intel_shared_dpll *pll;
3979         enum intel_dpll_id i;
3980
3981         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3982                 pll = &dev_priv->shared_dplls[i];
3983
3984                 WARN_ON(pll->new_config == &pll->config);
3985
3986                 kfree(pll->new_config);
3987                 pll->new_config = NULL;
3988         }
3989 }
3990
3991 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         int dslreg = PIPEDSL(pipe);
3995         u32 temp;
3996
3997         temp = I915_READ(dslreg);
3998         udelay(500);
3999         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4000                 if (wait_for(I915_READ(dslreg) != temp, 5))
4001                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4002         }
4003 }
4004
4005 static void skylake_pfit_enable(struct intel_crtc *crtc)
4006 {
4007         struct drm_device *dev = crtc->base.dev;
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         int pipe = crtc->pipe;
4010
4011         if (crtc->config.pch_pfit.enabled) {
4012                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4013                 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4014                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4015         }
4016 }
4017
4018 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4019 {
4020         struct drm_device *dev = crtc->base.dev;
4021         struct drm_i915_private *dev_priv = dev->dev_private;
4022         int pipe = crtc->pipe;
4023
4024         if (crtc->config.pch_pfit.enabled) {
4025                 /* Force use of hard-coded filter coefficients
4026                  * as some pre-programmed values are broken,
4027                  * e.g. x201.
4028                  */
4029                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4030                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4031                                                  PF_PIPE_SEL_IVB(pipe));
4032                 else
4033                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4034                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4035                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4036         }
4037 }
4038
4039 static void intel_enable_planes(struct drm_crtc *crtc)
4040 {
4041         struct drm_device *dev = crtc->dev;
4042         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4043         struct drm_plane *plane;
4044         struct intel_plane *intel_plane;
4045
4046         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4047                 intel_plane = to_intel_plane(plane);
4048                 if (intel_plane->pipe == pipe)
4049                         intel_plane_restore(&intel_plane->base);
4050         }
4051 }
4052
4053 static void intel_disable_planes(struct drm_crtc *crtc)
4054 {
4055         struct drm_device *dev = crtc->dev;
4056         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4057         struct drm_plane *plane;
4058         struct intel_plane *intel_plane;
4059
4060         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4061                 intel_plane = to_intel_plane(plane);
4062                 if (intel_plane->pipe == pipe)
4063                         plane->funcs->disable_plane(plane);
4064         }
4065 }
4066
4067 void hsw_enable_ips(struct intel_crtc *crtc)
4068 {
4069         struct drm_device *dev = crtc->base.dev;
4070         struct drm_i915_private *dev_priv = dev->dev_private;
4071
4072         if (!crtc->config.ips_enabled)
4073                 return;
4074
4075         /* We can only enable IPS after we enable a plane and wait for a vblank */
4076         intel_wait_for_vblank(dev, crtc->pipe);
4077
4078         assert_plane_enabled(dev_priv, crtc->plane);
4079         if (IS_BROADWELL(dev)) {
4080                 mutex_lock(&dev_priv->rps.hw_lock);
4081                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4082                 mutex_unlock(&dev_priv->rps.hw_lock);
4083                 /* Quoting Art Runyan: "its not safe to expect any particular
4084                  * value in IPS_CTL bit 31 after enabling IPS through the
4085                  * mailbox." Moreover, the mailbox may return a bogus state,
4086                  * so we need to just enable it and continue on.
4087                  */
4088         } else {
4089                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4090                 /* The bit only becomes 1 in the next vblank, so this wait here
4091                  * is essentially intel_wait_for_vblank. If we don't have this
4092                  * and don't wait for vblanks until the end of crtc_enable, then
4093                  * the HW state readout code will complain that the expected
4094                  * IPS_CTL value is not the one we read. */
4095                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4096                         DRM_ERROR("Timed out waiting for IPS enable\n");
4097         }
4098 }
4099
4100 void hsw_disable_ips(struct intel_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->base.dev;
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104
4105         if (!crtc->config.ips_enabled)
4106                 return;
4107
4108         assert_plane_enabled(dev_priv, crtc->plane);
4109         if (IS_BROADWELL(dev)) {
4110                 mutex_lock(&dev_priv->rps.hw_lock);
4111                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4112                 mutex_unlock(&dev_priv->rps.hw_lock);
4113                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4114                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4115                         DRM_ERROR("Timed out waiting for IPS disable\n");
4116         } else {
4117                 I915_WRITE(IPS_CTL, 0);
4118                 POSTING_READ(IPS_CTL);
4119         }
4120
4121         /* We need to wait for a vblank before we can disable the plane. */
4122         intel_wait_for_vblank(dev, crtc->pipe);
4123 }
4124
4125 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4126 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4127 {
4128         struct drm_device *dev = crtc->dev;
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131         enum pipe pipe = intel_crtc->pipe;
4132         int palreg = PALETTE(pipe);
4133         int i;
4134         bool reenable_ips = false;
4135
4136         /* The clocks have to be on to load the palette. */
4137         if (!crtc->enabled || !intel_crtc->active)
4138                 return;
4139
4140         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4141                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4142                         assert_dsi_pll_enabled(dev_priv);
4143                 else
4144                         assert_pll_enabled(dev_priv, pipe);
4145         }
4146
4147         /* use legacy palette for Ironlake */
4148         if (!HAS_GMCH_DISPLAY(dev))
4149                 palreg = LGC_PALETTE(pipe);
4150
4151         /* Workaround : Do not read or write the pipe palette/gamma data while
4152          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4153          */
4154         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4155             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4156              GAMMA_MODE_MODE_SPLIT)) {
4157                 hsw_disable_ips(intel_crtc);
4158                 reenable_ips = true;
4159         }
4160
4161         for (i = 0; i < 256; i++) {
4162                 I915_WRITE(palreg + 4 * i,
4163                            (intel_crtc->lut_r[i] << 16) |
4164                            (intel_crtc->lut_g[i] << 8) |
4165                            intel_crtc->lut_b[i]);
4166         }
4167
4168         if (reenable_ips)
4169                 hsw_enable_ips(intel_crtc);
4170 }
4171
4172 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4173 {
4174         if (!enable && intel_crtc->overlay) {
4175                 struct drm_device *dev = intel_crtc->base.dev;
4176                 struct drm_i915_private *dev_priv = dev->dev_private;
4177
4178                 mutex_lock(&dev->struct_mutex);
4179                 dev_priv->mm.interruptible = false;
4180                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4181                 dev_priv->mm.interruptible = true;
4182                 mutex_unlock(&dev->struct_mutex);
4183         }
4184
4185         /* Let userspace switch the overlay on again. In most cases userspace
4186          * has to recompute where to put it anyway.
4187          */
4188 }
4189
4190 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4191 {
4192         struct drm_device *dev = crtc->dev;
4193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194         int pipe = intel_crtc->pipe;
4195
4196         intel_enable_primary_hw_plane(crtc->primary, crtc);
4197         intel_enable_planes(crtc);
4198         intel_crtc_update_cursor(crtc, true);
4199         intel_crtc_dpms_overlay(intel_crtc, true);
4200
4201         hsw_enable_ips(intel_crtc);
4202
4203         mutex_lock(&dev->struct_mutex);
4204         intel_update_fbc(dev);
4205         mutex_unlock(&dev->struct_mutex);
4206
4207         /*
4208          * FIXME: Once we grow proper nuclear flip support out of this we need
4209          * to compute the mask of flip planes precisely. For the time being
4210          * consider this a flip from a NULL plane.
4211          */
4212         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4213 }
4214
4215 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4216 {
4217         struct drm_device *dev = crtc->dev;
4218         struct drm_i915_private *dev_priv = dev->dev_private;
4219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220         int pipe = intel_crtc->pipe;
4221         int plane = intel_crtc->plane;
4222
4223         intel_crtc_wait_for_pending_flips(crtc);
4224
4225         if (dev_priv->fbc.plane == plane)
4226                 intel_disable_fbc(dev);
4227
4228         hsw_disable_ips(intel_crtc);
4229
4230         intel_crtc_dpms_overlay(intel_crtc, false);
4231         intel_crtc_update_cursor(crtc, false);
4232         intel_disable_planes(crtc);
4233         intel_disable_primary_hw_plane(crtc->primary, crtc);
4234
4235         /*
4236          * FIXME: Once we grow proper nuclear flip support out of this we need
4237          * to compute the mask of flip planes precisely. For the time being
4238          * consider this a flip to a NULL plane.
4239          */
4240         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4241 }
4242
4243 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4244 {
4245         struct drm_device *dev = crtc->dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248         struct intel_encoder *encoder;
4249         int pipe = intel_crtc->pipe;
4250
4251         WARN_ON(!crtc->enabled);
4252
4253         if (intel_crtc->active)
4254                 return;
4255
4256         if (intel_crtc->config.has_pch_encoder)
4257                 intel_prepare_shared_dpll(intel_crtc);
4258
4259         if (intel_crtc->config.has_dp_encoder)
4260                 intel_dp_set_m_n(intel_crtc);
4261
4262         intel_set_pipe_timings(intel_crtc);
4263
4264         if (intel_crtc->config.has_pch_encoder) {
4265                 intel_cpu_transcoder_set_m_n(intel_crtc,
4266                                      &intel_crtc->config.fdi_m_n, NULL);
4267         }
4268
4269         ironlake_set_pipeconf(crtc);
4270
4271         intel_crtc->active = true;
4272
4273         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4274         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4275
4276         for_each_encoder_on_crtc(dev, crtc, encoder)
4277                 if (encoder->pre_enable)
4278                         encoder->pre_enable(encoder);
4279
4280         if (intel_crtc->config.has_pch_encoder) {
4281                 /* Note: FDI PLL enabling _must_ be done before we enable the
4282                  * cpu pipes, hence this is separate from all the other fdi/pch
4283                  * enabling. */
4284                 ironlake_fdi_pll_enable(intel_crtc);
4285         } else {
4286                 assert_fdi_tx_disabled(dev_priv, pipe);
4287                 assert_fdi_rx_disabled(dev_priv, pipe);
4288         }
4289
4290         ironlake_pfit_enable(intel_crtc);
4291
4292         /*
4293          * On ILK+ LUT must be loaded before the pipe is running but with
4294          * clocks enabled
4295          */
4296         intel_crtc_load_lut(crtc);
4297
4298         intel_update_watermarks(crtc);
4299         intel_enable_pipe(intel_crtc);
4300
4301         if (intel_crtc->config.has_pch_encoder)
4302                 ironlake_pch_enable(crtc);
4303
4304         for_each_encoder_on_crtc(dev, crtc, encoder)
4305                 encoder->enable(encoder);
4306
4307         if (HAS_PCH_CPT(dev))
4308                 cpt_verify_modeset(dev, intel_crtc->pipe);
4309
4310         assert_vblank_disabled(crtc);
4311         drm_crtc_vblank_on(crtc);
4312
4313         intel_crtc_enable_planes(crtc);
4314 }
4315
4316 /* IPS only exists on ULT machines and is tied to pipe A. */
4317 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4318 {
4319         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4320 }
4321
4322 /*
4323  * This implements the workaround described in the "notes" section of the mode
4324  * set sequence documentation. When going from no pipes or single pipe to
4325  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4326  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4327  */
4328 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4332
4333         /* We want to get the other_active_crtc only if there's only 1 other
4334          * active crtc. */
4335         for_each_intel_crtc(dev, crtc_it) {
4336                 if (!crtc_it->active || crtc_it == crtc)
4337                         continue;
4338
4339                 if (other_active_crtc)
4340                         return;
4341
4342                 other_active_crtc = crtc_it;
4343         }
4344         if (!other_active_crtc)
4345                 return;
4346
4347         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4348         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4349 }
4350
4351 static void haswell_crtc_enable(struct drm_crtc *crtc)
4352 {
4353         struct drm_device *dev = crtc->dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4356         struct intel_encoder *encoder;
4357         int pipe = intel_crtc->pipe;
4358
4359         WARN_ON(!crtc->enabled);
4360
4361         if (intel_crtc->active)
4362                 return;
4363
4364         if (intel_crtc_to_shared_dpll(intel_crtc))
4365                 intel_enable_shared_dpll(intel_crtc);
4366
4367         if (intel_crtc->config.has_dp_encoder)
4368                 intel_dp_set_m_n(intel_crtc);
4369
4370         intel_set_pipe_timings(intel_crtc);
4371
4372         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4373                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4374                            intel_crtc->config.pixel_multiplier - 1);
4375         }
4376
4377         if (intel_crtc->config.has_pch_encoder) {
4378                 intel_cpu_transcoder_set_m_n(intel_crtc,
4379                                      &intel_crtc->config.fdi_m_n, NULL);
4380         }
4381
4382         haswell_set_pipeconf(crtc);
4383
4384         intel_set_pipe_csc(crtc);
4385
4386         intel_crtc->active = true;
4387
4388         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4389         for_each_encoder_on_crtc(dev, crtc, encoder)
4390                 if (encoder->pre_enable)
4391                         encoder->pre_enable(encoder);
4392
4393         if (intel_crtc->config.has_pch_encoder) {
4394                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4395                                                       true);
4396                 dev_priv->display.fdi_link_train(crtc);
4397         }
4398
4399         intel_ddi_enable_pipe_clock(intel_crtc);
4400
4401         if (IS_SKYLAKE(dev))
4402                 skylake_pfit_enable(intel_crtc);
4403         else
4404                 ironlake_pfit_enable(intel_crtc);
4405
4406         /*
4407          * On ILK+ LUT must be loaded before the pipe is running but with
4408          * clocks enabled
4409          */
4410         intel_crtc_load_lut(crtc);
4411
4412         intel_ddi_set_pipe_settings(crtc);
4413         intel_ddi_enable_transcoder_func(crtc);
4414
4415         intel_update_watermarks(crtc);
4416         intel_enable_pipe(intel_crtc);
4417
4418         if (intel_crtc->config.has_pch_encoder)
4419                 lpt_pch_enable(crtc);
4420
4421         if (intel_crtc->config.dp_encoder_is_mst)
4422                 intel_ddi_set_vc_payload_alloc(crtc, true);
4423
4424         for_each_encoder_on_crtc(dev, crtc, encoder) {
4425                 encoder->enable(encoder);
4426                 intel_opregion_notify_encoder(encoder, true);
4427         }
4428
4429         assert_vblank_disabled(crtc);
4430         drm_crtc_vblank_on(crtc);
4431
4432         /* If we change the relative order between pipe/planes enabling, we need
4433          * to change the workaround. */
4434         haswell_mode_set_planes_workaround(intel_crtc);
4435         intel_crtc_enable_planes(crtc);
4436 }
4437
4438 static void skylake_pfit_disable(struct intel_crtc *crtc)
4439 {
4440         struct drm_device *dev = crtc->base.dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         int pipe = crtc->pipe;
4443
4444         /* To avoid upsetting the power well on haswell only disable the pfit if
4445          * it's in use. The hw state code will make sure we get this right. */
4446         if (crtc->config.pch_pfit.enabled) {
4447                 I915_WRITE(PS_CTL(pipe), 0);
4448                 I915_WRITE(PS_WIN_POS(pipe), 0);
4449                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4450         }
4451 }
4452
4453 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4454 {
4455         struct drm_device *dev = crtc->base.dev;
4456         struct drm_i915_private *dev_priv = dev->dev_private;
4457         int pipe = crtc->pipe;
4458
4459         /* To avoid upsetting the power well on haswell only disable the pfit if
4460          * it's in use. The hw state code will make sure we get this right. */
4461         if (crtc->config.pch_pfit.enabled) {
4462                 I915_WRITE(PF_CTL(pipe), 0);
4463                 I915_WRITE(PF_WIN_POS(pipe), 0);
4464                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4465         }
4466 }
4467
4468 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4469 {
4470         struct drm_device *dev = crtc->dev;
4471         struct drm_i915_private *dev_priv = dev->dev_private;
4472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4473         struct intel_encoder *encoder;
4474         int pipe = intel_crtc->pipe;
4475         u32 reg, temp;
4476
4477         if (!intel_crtc->active)
4478                 return;
4479
4480         intel_crtc_disable_planes(crtc);
4481
4482         drm_crtc_vblank_off(crtc);
4483         assert_vblank_disabled(crtc);
4484
4485         for_each_encoder_on_crtc(dev, crtc, encoder)
4486                 encoder->disable(encoder);
4487
4488         if (intel_crtc->config.has_pch_encoder)
4489                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4490
4491         intel_disable_pipe(intel_crtc);
4492
4493         ironlake_pfit_disable(intel_crtc);
4494
4495         for_each_encoder_on_crtc(dev, crtc, encoder)
4496                 if (encoder->post_disable)
4497                         encoder->post_disable(encoder);
4498
4499         if (intel_crtc->config.has_pch_encoder) {
4500                 ironlake_fdi_disable(crtc);
4501
4502                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4503                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4504
4505                 if (HAS_PCH_CPT(dev)) {
4506                         /* disable TRANS_DP_CTL */
4507                         reg = TRANS_DP_CTL(pipe);
4508                         temp = I915_READ(reg);
4509                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4510                                   TRANS_DP_PORT_SEL_MASK);
4511                         temp |= TRANS_DP_PORT_SEL_NONE;
4512                         I915_WRITE(reg, temp);
4513
4514                         /* disable DPLL_SEL */
4515                         temp = I915_READ(PCH_DPLL_SEL);
4516                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4517                         I915_WRITE(PCH_DPLL_SEL, temp);
4518                 }
4519
4520                 /* disable PCH DPLL */
4521                 intel_disable_shared_dpll(intel_crtc);
4522
4523                 ironlake_fdi_pll_disable(intel_crtc);
4524         }
4525
4526         intel_crtc->active = false;
4527         intel_update_watermarks(crtc);
4528
4529         mutex_lock(&dev->struct_mutex);
4530         intel_update_fbc(dev);
4531         mutex_unlock(&dev->struct_mutex);
4532 }
4533
4534 static void haswell_crtc_disable(struct drm_crtc *crtc)
4535 {
4536         struct drm_device *dev = crtc->dev;
4537         struct drm_i915_private *dev_priv = dev->dev_private;
4538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4539         struct intel_encoder *encoder;
4540         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4541
4542         if (!intel_crtc->active)
4543                 return;
4544
4545         intel_crtc_disable_planes(crtc);
4546
4547         drm_crtc_vblank_off(crtc);
4548         assert_vblank_disabled(crtc);
4549
4550         for_each_encoder_on_crtc(dev, crtc, encoder) {
4551                 intel_opregion_notify_encoder(encoder, false);
4552                 encoder->disable(encoder);
4553         }
4554
4555         if (intel_crtc->config.has_pch_encoder)
4556                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4557                                                       false);
4558         intel_disable_pipe(intel_crtc);
4559
4560         if (intel_crtc->config.dp_encoder_is_mst)
4561                 intel_ddi_set_vc_payload_alloc(crtc, false);
4562
4563         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4564
4565         if (IS_SKYLAKE(dev))
4566                 skylake_pfit_disable(intel_crtc);
4567         else
4568                 ironlake_pfit_disable(intel_crtc);
4569
4570         intel_ddi_disable_pipe_clock(intel_crtc);
4571
4572         if (intel_crtc->config.has_pch_encoder) {
4573                 lpt_disable_pch_transcoder(dev_priv);
4574                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4575                                                       true);
4576                 intel_ddi_fdi_disable(crtc);
4577         }
4578
4579         for_each_encoder_on_crtc(dev, crtc, encoder)
4580                 if (encoder->post_disable)
4581                         encoder->post_disable(encoder);
4582
4583         intel_crtc->active = false;
4584         intel_update_watermarks(crtc);
4585
4586         mutex_lock(&dev->struct_mutex);
4587         intel_update_fbc(dev);
4588         mutex_unlock(&dev->struct_mutex);
4589
4590         if (intel_crtc_to_shared_dpll(intel_crtc))
4591                 intel_disable_shared_dpll(intel_crtc);
4592 }
4593
4594 static void ironlake_crtc_off(struct drm_crtc *crtc)
4595 {
4596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597         intel_put_shared_dpll(intel_crtc);
4598 }
4599
4600
4601 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4602 {
4603         struct drm_device *dev = crtc->base.dev;
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605         struct intel_crtc_config *pipe_config = &crtc->config;
4606
4607         if (!crtc->config.gmch_pfit.control)
4608                 return;
4609
4610         /*
4611          * The panel fitter should only be adjusted whilst the pipe is disabled,
4612          * according to register description and PRM.
4613          */
4614         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4615         assert_pipe_disabled(dev_priv, crtc->pipe);
4616
4617         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4618         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4619
4620         /* Border color in case we don't scale up to the full screen. Black by
4621          * default, change to something else for debugging. */
4622         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4623 }
4624
4625 static enum intel_display_power_domain port_to_power_domain(enum port port)
4626 {
4627         switch (port) {
4628         case PORT_A:
4629                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4630         case PORT_B:
4631                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4632         case PORT_C:
4633                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4634         case PORT_D:
4635                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4636         default:
4637                 WARN_ON_ONCE(1);
4638                 return POWER_DOMAIN_PORT_OTHER;
4639         }
4640 }
4641
4642 #define for_each_power_domain(domain, mask)                             \
4643         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4644                 if ((1 << (domain)) & (mask))
4645
4646 enum intel_display_power_domain
4647 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4648 {
4649         struct drm_device *dev = intel_encoder->base.dev;
4650         struct intel_digital_port *intel_dig_port;
4651
4652         switch (intel_encoder->type) {
4653         case INTEL_OUTPUT_UNKNOWN:
4654                 /* Only DDI platforms should ever use this output type */
4655                 WARN_ON_ONCE(!HAS_DDI(dev));
4656         case INTEL_OUTPUT_DISPLAYPORT:
4657         case INTEL_OUTPUT_HDMI:
4658         case INTEL_OUTPUT_EDP:
4659                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4660                 return port_to_power_domain(intel_dig_port->port);
4661         case INTEL_OUTPUT_DP_MST:
4662                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4663                 return port_to_power_domain(intel_dig_port->port);
4664         case INTEL_OUTPUT_ANALOG:
4665                 return POWER_DOMAIN_PORT_CRT;
4666         case INTEL_OUTPUT_DSI:
4667                 return POWER_DOMAIN_PORT_DSI;
4668         default:
4669                 return POWER_DOMAIN_PORT_OTHER;
4670         }
4671 }
4672
4673 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4674 {
4675         struct drm_device *dev = crtc->dev;
4676         struct intel_encoder *intel_encoder;
4677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678         enum pipe pipe = intel_crtc->pipe;
4679         unsigned long mask;
4680         enum transcoder transcoder;
4681
4682         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4683
4684         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4685         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4686         if (intel_crtc->config.pch_pfit.enabled ||
4687             intel_crtc->config.pch_pfit.force_thru)
4688                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4689
4690         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4691                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4692
4693         return mask;
4694 }
4695
4696 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4697 {
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4700         struct intel_crtc *crtc;
4701
4702         /*
4703          * First get all needed power domains, then put all unneeded, to avoid
4704          * any unnecessary toggling of the power wells.
4705          */
4706         for_each_intel_crtc(dev, crtc) {
4707                 enum intel_display_power_domain domain;
4708
4709                 if (!crtc->base.enabled)
4710                         continue;
4711
4712                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4713
4714                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4715                         intel_display_power_get(dev_priv, domain);
4716         }
4717
4718         if (dev_priv->display.modeset_global_resources)
4719                 dev_priv->display.modeset_global_resources(dev);
4720
4721         for_each_intel_crtc(dev, crtc) {
4722                 enum intel_display_power_domain domain;
4723
4724                 for_each_power_domain(domain, crtc->enabled_power_domains)
4725                         intel_display_power_put(dev_priv, domain);
4726
4727                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4728         }
4729
4730         intel_display_set_init_power(dev_priv, false);
4731 }
4732
4733 /* returns HPLL frequency in kHz */
4734 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4735 {
4736         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4737
4738         /* Obtain SKU information */
4739         mutex_lock(&dev_priv->dpio_lock);
4740         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4741                 CCK_FUSE_HPLL_FREQ_MASK;
4742         mutex_unlock(&dev_priv->dpio_lock);
4743
4744         return vco_freq[hpll_freq] * 1000;
4745 }
4746
4747 static void vlv_update_cdclk(struct drm_device *dev)
4748 {
4749         struct drm_i915_private *dev_priv = dev->dev_private;
4750
4751         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4752         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4753                          dev_priv->vlv_cdclk_freq);
4754
4755         /*
4756          * Program the gmbus_freq based on the cdclk frequency.
4757          * BSpec erroneously claims we should aim for 4MHz, but
4758          * in fact 1MHz is the correct frequency.
4759          */
4760         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4761 }
4762
4763 /* Adjust CDclk dividers to allow high res or save power if possible */
4764 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4765 {
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767         u32 val, cmd;
4768
4769         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4770
4771         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4772                 cmd = 2;
4773         else if (cdclk == 266667)
4774                 cmd = 1;
4775         else
4776                 cmd = 0;
4777
4778         mutex_lock(&dev_priv->rps.hw_lock);
4779         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4780         val &= ~DSPFREQGUAR_MASK;
4781         val |= (cmd << DSPFREQGUAR_SHIFT);
4782         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4783         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4784                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4785                      50)) {
4786                 DRM_ERROR("timed out waiting for CDclk change\n");
4787         }
4788         mutex_unlock(&dev_priv->rps.hw_lock);
4789
4790         if (cdclk == 400000) {
4791                 u32 divider;
4792
4793                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4794
4795                 mutex_lock(&dev_priv->dpio_lock);
4796                 /* adjust cdclk divider */
4797                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4798                 val &= ~DISPLAY_FREQUENCY_VALUES;
4799                 val |= divider;
4800                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4801
4802                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4803                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4804                              50))
4805                         DRM_ERROR("timed out waiting for CDclk change\n");
4806                 mutex_unlock(&dev_priv->dpio_lock);
4807         }
4808
4809         mutex_lock(&dev_priv->dpio_lock);
4810         /* adjust self-refresh exit latency value */
4811         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4812         val &= ~0x7f;
4813
4814         /*
4815          * For high bandwidth configs, we set a higher latency in the bunit
4816          * so that the core display fetch happens in time to avoid underruns.
4817          */
4818         if (cdclk == 400000)
4819                 val |= 4500 / 250; /* 4.5 usec */
4820         else
4821                 val |= 3000 / 250; /* 3.0 usec */
4822         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4823         mutex_unlock(&dev_priv->dpio_lock);
4824
4825         vlv_update_cdclk(dev);
4826 }
4827
4828 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4829 {
4830         struct drm_i915_private *dev_priv = dev->dev_private;
4831         u32 val, cmd;
4832
4833         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4834
4835         switch (cdclk) {
4836         case 400000:
4837                 cmd = 3;
4838                 break;
4839         case 333333:
4840         case 320000:
4841                 cmd = 2;
4842                 break;
4843         case 266667:
4844                 cmd = 1;
4845                 break;
4846         case 200000:
4847                 cmd = 0;
4848                 break;
4849         default:
4850                 WARN_ON(1);
4851                 return;
4852         }
4853
4854         mutex_lock(&dev_priv->rps.hw_lock);
4855         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4856         val &= ~DSPFREQGUAR_MASK_CHV;
4857         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4858         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4859         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4860                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4861                      50)) {
4862                 DRM_ERROR("timed out waiting for CDclk change\n");
4863         }
4864         mutex_unlock(&dev_priv->rps.hw_lock);
4865
4866         vlv_update_cdclk(dev);
4867 }
4868
4869 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4870                                  int max_pixclk)
4871 {
4872         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4873
4874         /* FIXME: Punit isn't quite ready yet */
4875         if (IS_CHERRYVIEW(dev_priv->dev))
4876                 return 400000;
4877
4878         /*
4879          * Really only a few cases to deal with, as only 4 CDclks are supported:
4880          *   200MHz
4881          *   267MHz
4882          *   320/333MHz (depends on HPLL freq)
4883          *   400MHz
4884          * So we check to see whether we're above 90% of the lower bin and
4885          * adjust if needed.
4886          *
4887          * We seem to get an unstable or solid color picture at 200MHz.
4888          * Not sure what's wrong. For now use 200MHz only when all pipes
4889          * are off.
4890          */
4891         if (max_pixclk > freq_320*9/10)
4892                 return 400000;
4893         else if (max_pixclk > 266667*9/10)
4894                 return freq_320;
4895         else if (max_pixclk > 0)
4896                 return 266667;
4897         else
4898                 return 200000;
4899 }
4900
4901 /* compute the max pixel clock for new configuration */
4902 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4903 {
4904         struct drm_device *dev = dev_priv->dev;
4905         struct intel_crtc *intel_crtc;
4906         int max_pixclk = 0;
4907
4908         for_each_intel_crtc(dev, intel_crtc) {
4909                 if (intel_crtc->new_enabled)
4910                         max_pixclk = max(max_pixclk,
4911                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4912         }
4913
4914         return max_pixclk;
4915 }
4916
4917 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4918                                             unsigned *prepare_pipes)
4919 {
4920         struct drm_i915_private *dev_priv = dev->dev_private;
4921         struct intel_crtc *intel_crtc;
4922         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4923
4924         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4925             dev_priv->vlv_cdclk_freq)
4926                 return;
4927
4928         /* disable/enable all currently active pipes while we change cdclk */
4929         for_each_intel_crtc(dev, intel_crtc)
4930                 if (intel_crtc->base.enabled)
4931                         *prepare_pipes |= (1 << intel_crtc->pipe);
4932 }
4933
4934 static void valleyview_modeset_global_resources(struct drm_device *dev)
4935 {
4936         struct drm_i915_private *dev_priv = dev->dev_private;
4937         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4938         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4939
4940         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4941                 /*
4942                  * FIXME: We can end up here with all power domains off, yet
4943                  * with a CDCLK frequency other than the minimum. To account
4944                  * for this take the PIPE-A power domain, which covers the HW
4945                  * blocks needed for the following programming. This can be
4946                  * removed once it's guaranteed that we get here either with
4947                  * the minimum CDCLK set, or the required power domains
4948                  * enabled.
4949                  */
4950                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4951
4952                 if (IS_CHERRYVIEW(dev))
4953                         cherryview_set_cdclk(dev, req_cdclk);
4954                 else
4955                         valleyview_set_cdclk(dev, req_cdclk);
4956
4957                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4958         }
4959 }
4960
4961 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4962 {
4963         struct drm_device *dev = crtc->dev;
4964         struct drm_i915_private *dev_priv = to_i915(dev);
4965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966         struct intel_encoder *encoder;
4967         int pipe = intel_crtc->pipe;
4968         bool is_dsi;
4969
4970         WARN_ON(!crtc->enabled);
4971
4972         if (intel_crtc->active)
4973                 return;
4974
4975         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4976
4977         if (!is_dsi) {
4978                 if (IS_CHERRYVIEW(dev))
4979                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4980                 else
4981                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4982         }
4983
4984         if (intel_crtc->config.has_dp_encoder)
4985                 intel_dp_set_m_n(intel_crtc);
4986
4987         intel_set_pipe_timings(intel_crtc);
4988
4989         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4990                 struct drm_i915_private *dev_priv = dev->dev_private;
4991
4992                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4993                 I915_WRITE(CHV_CANVAS(pipe), 0);
4994         }
4995
4996         i9xx_set_pipeconf(intel_crtc);
4997
4998         intel_crtc->active = true;
4999
5000         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5001
5002         for_each_encoder_on_crtc(dev, crtc, encoder)
5003                 if (encoder->pre_pll_enable)
5004                         encoder->pre_pll_enable(encoder);
5005
5006         if (!is_dsi) {
5007                 if (IS_CHERRYVIEW(dev))
5008                         chv_enable_pll(intel_crtc, &intel_crtc->config);
5009                 else
5010                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
5011         }
5012
5013         for_each_encoder_on_crtc(dev, crtc, encoder)
5014                 if (encoder->pre_enable)
5015                         encoder->pre_enable(encoder);
5016
5017         i9xx_pfit_enable(intel_crtc);
5018
5019         intel_crtc_load_lut(crtc);
5020
5021         intel_update_watermarks(crtc);
5022         intel_enable_pipe(intel_crtc);
5023
5024         for_each_encoder_on_crtc(dev, crtc, encoder)
5025                 encoder->enable(encoder);
5026
5027         assert_vblank_disabled(crtc);
5028         drm_crtc_vblank_on(crtc);
5029
5030         intel_crtc_enable_planes(crtc);
5031
5032         /* Underruns don't raise interrupts, so check manually. */
5033         i9xx_check_fifo_underruns(dev_priv);
5034 }
5035
5036 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5037 {
5038         struct drm_device *dev = crtc->base.dev;
5039         struct drm_i915_private *dev_priv = dev->dev_private;
5040
5041         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5042         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5043 }
5044
5045 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5046 {
5047         struct drm_device *dev = crtc->dev;
5048         struct drm_i915_private *dev_priv = to_i915(dev);
5049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5050         struct intel_encoder *encoder;
5051         int pipe = intel_crtc->pipe;
5052
5053         WARN_ON(!crtc->enabled);
5054
5055         if (intel_crtc->active)
5056                 return;
5057
5058         i9xx_set_pll_dividers(intel_crtc);
5059
5060         if (intel_crtc->config.has_dp_encoder)
5061                 intel_dp_set_m_n(intel_crtc);
5062
5063         intel_set_pipe_timings(intel_crtc);
5064
5065         i9xx_set_pipeconf(intel_crtc);
5066
5067         intel_crtc->active = true;
5068
5069         if (!IS_GEN2(dev))
5070                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5071
5072         for_each_encoder_on_crtc(dev, crtc, encoder)
5073                 if (encoder->pre_enable)
5074                         encoder->pre_enable(encoder);
5075
5076         i9xx_enable_pll(intel_crtc);
5077
5078         i9xx_pfit_enable(intel_crtc);
5079
5080         intel_crtc_load_lut(crtc);
5081
5082         intel_update_watermarks(crtc);
5083         intel_enable_pipe(intel_crtc);
5084
5085         for_each_encoder_on_crtc(dev, crtc, encoder)
5086                 encoder->enable(encoder);
5087
5088         assert_vblank_disabled(crtc);
5089         drm_crtc_vblank_on(crtc);
5090
5091         intel_crtc_enable_planes(crtc);
5092
5093         /*
5094          * Gen2 reports pipe underruns whenever all planes are disabled.
5095          * So don't enable underrun reporting before at least some planes
5096          * are enabled.
5097          * FIXME: Need to fix the logic to work when we turn off all planes
5098          * but leave the pipe running.
5099          */
5100         if (IS_GEN2(dev))
5101                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5102
5103         /* Underruns don't raise interrupts, so check manually. */
5104         i9xx_check_fifo_underruns(dev_priv);
5105 }
5106
5107 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5108 {
5109         struct drm_device *dev = crtc->base.dev;
5110         struct drm_i915_private *dev_priv = dev->dev_private;
5111
5112         if (!crtc->config.gmch_pfit.control)
5113                 return;
5114
5115         assert_pipe_disabled(dev_priv, crtc->pipe);
5116
5117         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5118                          I915_READ(PFIT_CONTROL));
5119         I915_WRITE(PFIT_CONTROL, 0);
5120 }
5121
5122 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5123 {
5124         struct drm_device *dev = crtc->dev;
5125         struct drm_i915_private *dev_priv = dev->dev_private;
5126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5127         struct intel_encoder *encoder;
5128         int pipe = intel_crtc->pipe;
5129
5130         if (!intel_crtc->active)
5131                 return;
5132
5133         /*
5134          * Gen2 reports pipe underruns whenever all planes are disabled.
5135          * So diasble underrun reporting before all the planes get disabled.
5136          * FIXME: Need to fix the logic to work when we turn off all planes
5137          * but leave the pipe running.
5138          */
5139         if (IS_GEN2(dev))
5140                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5141
5142         /*
5143          * Vblank time updates from the shadow to live plane control register
5144          * are blocked if the memory self-refresh mode is active at that
5145          * moment. So to make sure the plane gets truly disabled, disable
5146          * first the self-refresh mode. The self-refresh enable bit in turn
5147          * will be checked/applied by the HW only at the next frame start
5148          * event which is after the vblank start event, so we need to have a
5149          * wait-for-vblank between disabling the plane and the pipe.
5150          */
5151         intel_set_memory_cxsr(dev_priv, false);
5152         intel_crtc_disable_planes(crtc);
5153
5154         /*
5155          * On gen2 planes are double buffered but the pipe isn't, so we must
5156          * wait for planes to fully turn off before disabling the pipe.
5157          * We also need to wait on all gmch platforms because of the
5158          * self-refresh mode constraint explained above.
5159          */
5160         intel_wait_for_vblank(dev, pipe);
5161
5162         drm_crtc_vblank_off(crtc);
5163         assert_vblank_disabled(crtc);
5164
5165         for_each_encoder_on_crtc(dev, crtc, encoder)
5166                 encoder->disable(encoder);
5167
5168         intel_disable_pipe(intel_crtc);
5169
5170         i9xx_pfit_disable(intel_crtc);
5171
5172         for_each_encoder_on_crtc(dev, crtc, encoder)
5173                 if (encoder->post_disable)
5174                         encoder->post_disable(encoder);
5175
5176         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5177                 if (IS_CHERRYVIEW(dev))
5178                         chv_disable_pll(dev_priv, pipe);
5179                 else if (IS_VALLEYVIEW(dev))
5180                         vlv_disable_pll(dev_priv, pipe);
5181                 else
5182                         i9xx_disable_pll(intel_crtc);
5183         }
5184
5185         if (!IS_GEN2(dev))
5186                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5187
5188         intel_crtc->active = false;
5189         intel_update_watermarks(crtc);
5190
5191         mutex_lock(&dev->struct_mutex);
5192         intel_update_fbc(dev);
5193         mutex_unlock(&dev->struct_mutex);
5194 }
5195
5196 static void i9xx_crtc_off(struct drm_crtc *crtc)
5197 {
5198 }
5199
5200 /* Master function to enable/disable CRTC and corresponding power wells */
5201 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5202 {
5203         struct drm_device *dev = crtc->dev;
5204         struct drm_i915_private *dev_priv = dev->dev_private;
5205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206         enum intel_display_power_domain domain;
5207         unsigned long domains;
5208
5209         if (enable) {
5210                 if (!intel_crtc->active) {
5211                         domains = get_crtc_power_domains(crtc);
5212                         for_each_power_domain(domain, domains)
5213                                 intel_display_power_get(dev_priv, domain);
5214                         intel_crtc->enabled_power_domains = domains;
5215
5216                         dev_priv->display.crtc_enable(crtc);
5217                 }
5218         } else {
5219                 if (intel_crtc->active) {
5220                         dev_priv->display.crtc_disable(crtc);
5221
5222                         domains = intel_crtc->enabled_power_domains;
5223                         for_each_power_domain(domain, domains)
5224                                 intel_display_power_put(dev_priv, domain);
5225                         intel_crtc->enabled_power_domains = 0;
5226                 }
5227         }
5228 }
5229
5230 /**
5231  * Sets the power management mode of the pipe and plane.
5232  */
5233 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5234 {
5235         struct drm_device *dev = crtc->dev;
5236         struct intel_encoder *intel_encoder;
5237         bool enable = false;
5238
5239         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5240                 enable |= intel_encoder->connectors_active;
5241
5242         intel_crtc_control(crtc, enable);
5243 }
5244
5245 static void intel_crtc_disable(struct drm_crtc *crtc)
5246 {
5247         struct drm_device *dev = crtc->dev;
5248         struct drm_connector *connector;
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250
5251         /* crtc should still be enabled when we disable it. */
5252         WARN_ON(!crtc->enabled);
5253
5254         dev_priv->display.crtc_disable(crtc);
5255         dev_priv->display.off(crtc);
5256
5257         crtc->primary->funcs->disable_plane(crtc->primary);
5258
5259         /* Update computed state. */
5260         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5261                 if (!connector->encoder || !connector->encoder->crtc)
5262                         continue;
5263
5264                 if (connector->encoder->crtc != crtc)
5265                         continue;
5266
5267                 connector->dpms = DRM_MODE_DPMS_OFF;
5268                 to_intel_encoder(connector->encoder)->connectors_active = false;
5269         }
5270 }
5271
5272 void intel_encoder_destroy(struct drm_encoder *encoder)
5273 {
5274         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5275
5276         drm_encoder_cleanup(encoder);
5277         kfree(intel_encoder);
5278 }
5279
5280 /* Simple dpms helper for encoders with just one connector, no cloning and only
5281  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5282  * state of the entire output pipe. */
5283 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5284 {
5285         if (mode == DRM_MODE_DPMS_ON) {
5286                 encoder->connectors_active = true;
5287
5288                 intel_crtc_update_dpms(encoder->base.crtc);
5289         } else {
5290                 encoder->connectors_active = false;
5291
5292                 intel_crtc_update_dpms(encoder->base.crtc);
5293         }
5294 }
5295
5296 /* Cross check the actual hw state with our own modeset state tracking (and it's
5297  * internal consistency). */
5298 static void intel_connector_check_state(struct intel_connector *connector)
5299 {
5300         if (connector->get_hw_state(connector)) {
5301                 struct intel_encoder *encoder = connector->encoder;
5302                 struct drm_crtc *crtc;
5303                 bool encoder_enabled;
5304                 enum pipe pipe;
5305
5306                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5307                               connector->base.base.id,
5308                               connector->base.name);
5309
5310                 /* there is no real hw state for MST connectors */
5311                 if (connector->mst_port)
5312                         return;
5313
5314                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5315                      "wrong connector dpms state\n");
5316                 WARN(connector->base.encoder != &encoder->base,
5317                      "active connector not linked to encoder\n");
5318
5319                 if (encoder) {
5320                         WARN(!encoder->connectors_active,
5321                              "encoder->connectors_active not set\n");
5322
5323                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5324                         WARN(!encoder_enabled, "encoder not enabled\n");
5325                         if (WARN_ON(!encoder->base.crtc))
5326                                 return;
5327
5328                         crtc = encoder->base.crtc;
5329
5330                         WARN(!crtc->enabled, "crtc not enabled\n");
5331                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5332                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5333                              "encoder active on the wrong pipe\n");
5334                 }
5335         }
5336 }
5337
5338 /* Even simpler default implementation, if there's really no special case to
5339  * consider. */
5340 void intel_connector_dpms(struct drm_connector *connector, int mode)
5341 {
5342         /* All the simple cases only support two dpms states. */
5343         if (mode != DRM_MODE_DPMS_ON)
5344                 mode = DRM_MODE_DPMS_OFF;
5345
5346         if (mode == connector->dpms)
5347                 return;
5348
5349         connector->dpms = mode;
5350
5351         /* Only need to change hw state when actually enabled */
5352         if (connector->encoder)
5353                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5354
5355         intel_modeset_check_state(connector->dev);
5356 }
5357
5358 /* Simple connector->get_hw_state implementation for encoders that support only
5359  * one connector and no cloning and hence the encoder state determines the state
5360  * of the connector. */
5361 bool intel_connector_get_hw_state(struct intel_connector *connector)
5362 {
5363         enum pipe pipe = 0;
5364         struct intel_encoder *encoder = connector->encoder;
5365
5366         return encoder->get_hw_state(encoder, &pipe);
5367 }
5368
5369 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5370                                      struct intel_crtc_config *pipe_config)
5371 {
5372         struct drm_i915_private *dev_priv = dev->dev_private;
5373         struct intel_crtc *pipe_B_crtc =
5374                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5375
5376         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5377                       pipe_name(pipe), pipe_config->fdi_lanes);
5378         if (pipe_config->fdi_lanes > 4) {
5379                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5380                               pipe_name(pipe), pipe_config->fdi_lanes);
5381                 return false;
5382         }
5383
5384         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5385                 if (pipe_config->fdi_lanes > 2) {
5386                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5387                                       pipe_config->fdi_lanes);
5388                         return false;
5389                 } else {
5390                         return true;
5391                 }
5392         }
5393
5394         if (INTEL_INFO(dev)->num_pipes == 2)
5395                 return true;
5396
5397         /* Ivybridge 3 pipe is really complicated */
5398         switch (pipe) {
5399         case PIPE_A:
5400                 return true;
5401         case PIPE_B:
5402                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5403                     pipe_config->fdi_lanes > 2) {
5404                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5405                                       pipe_name(pipe), pipe_config->fdi_lanes);
5406                         return false;
5407                 }
5408                 return true;
5409         case PIPE_C:
5410                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5411                     pipe_B_crtc->config.fdi_lanes <= 2) {
5412                         if (pipe_config->fdi_lanes > 2) {
5413                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5414                                               pipe_name(pipe), pipe_config->fdi_lanes);
5415                                 return false;
5416                         }
5417                 } else {
5418                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5419                         return false;
5420                 }
5421                 return true;
5422         default:
5423                 BUG();
5424         }
5425 }
5426
5427 #define RETRY 1
5428 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5429                                        struct intel_crtc_config *pipe_config)
5430 {
5431         struct drm_device *dev = intel_crtc->base.dev;
5432         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5433         int lane, link_bw, fdi_dotclock;
5434         bool setup_ok, needs_recompute = false;
5435
5436 retry:
5437         /* FDI is a binary signal running at ~2.7GHz, encoding
5438          * each output octet as 10 bits. The actual frequency
5439          * is stored as a divider into a 100MHz clock, and the
5440          * mode pixel clock is stored in units of 1KHz.
5441          * Hence the bw of each lane in terms of the mode signal
5442          * is:
5443          */
5444         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5445
5446         fdi_dotclock = adjusted_mode->crtc_clock;
5447
5448         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5449                                            pipe_config->pipe_bpp);
5450
5451         pipe_config->fdi_lanes = lane;
5452
5453         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5454                                link_bw, &pipe_config->fdi_m_n);
5455
5456         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5457                                             intel_crtc->pipe, pipe_config);
5458         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5459                 pipe_config->pipe_bpp -= 2*3;
5460                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5461                               pipe_config->pipe_bpp);
5462                 needs_recompute = true;
5463                 pipe_config->bw_constrained = true;
5464
5465                 goto retry;
5466         }
5467
5468         if (needs_recompute)
5469                 return RETRY;
5470
5471         return setup_ok ? 0 : -EINVAL;
5472 }
5473
5474 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5475                                    struct intel_crtc_config *pipe_config)
5476 {
5477         pipe_config->ips_enabled = i915.enable_ips &&
5478                                    hsw_crtc_supports_ips(crtc) &&
5479                                    pipe_config->pipe_bpp <= 24;
5480 }
5481
5482 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5483                                      struct intel_crtc_config *pipe_config)
5484 {
5485         struct drm_device *dev = crtc->base.dev;
5486         struct drm_i915_private *dev_priv = dev->dev_private;
5487         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5488
5489         /* FIXME should check pixel clock limits on all platforms */
5490         if (INTEL_INFO(dev)->gen < 4) {
5491                 int clock_limit =
5492                         dev_priv->display.get_display_clock_speed(dev);
5493
5494                 /*
5495                  * Enable pixel doubling when the dot clock
5496                  * is > 90% of the (display) core speed.
5497                  *
5498                  * GDG double wide on either pipe,
5499                  * otherwise pipe A only.
5500                  */
5501                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5502                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5503                         clock_limit *= 2;
5504                         pipe_config->double_wide = true;
5505                 }
5506
5507                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5508                         return -EINVAL;
5509         }
5510
5511         /*
5512          * Pipe horizontal size must be even in:
5513          * - DVO ganged mode
5514          * - LVDS dual channel mode
5515          * - Double wide pipe
5516          */
5517         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5518              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5519                 pipe_config->pipe_src_w &= ~1;
5520
5521         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5522          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5523          */
5524         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5525                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5526                 return -EINVAL;
5527
5528         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5529                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5530         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5531                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5532                  * for lvds. */
5533                 pipe_config->pipe_bpp = 8*3;
5534         }
5535
5536         if (HAS_IPS(dev))
5537                 hsw_compute_ips_config(crtc, pipe_config);
5538
5539         if (pipe_config->has_pch_encoder)
5540                 return ironlake_fdi_compute_config(crtc, pipe_config);
5541
5542         return 0;
5543 }
5544
5545 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5546 {
5547         struct drm_i915_private *dev_priv = dev->dev_private;
5548         u32 val;
5549         int divider;
5550
5551         /* FIXME: Punit isn't quite ready yet */
5552         if (IS_CHERRYVIEW(dev))
5553                 return 400000;
5554
5555         if (dev_priv->hpll_freq == 0)
5556                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5557
5558         mutex_lock(&dev_priv->dpio_lock);
5559         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5560         mutex_unlock(&dev_priv->dpio_lock);
5561
5562         divider = val & DISPLAY_FREQUENCY_VALUES;
5563
5564         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5565              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5566              "cdclk change in progress\n");
5567
5568         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5569 }
5570
5571 static int i945_get_display_clock_speed(struct drm_device *dev)
5572 {
5573         return 400000;
5574 }
5575
5576 static int i915_get_display_clock_speed(struct drm_device *dev)
5577 {
5578         return 333000;
5579 }
5580
5581 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5582 {
5583         return 200000;
5584 }
5585
5586 static int pnv_get_display_clock_speed(struct drm_device *dev)
5587 {
5588         u16 gcfgc = 0;
5589
5590         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5591
5592         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5593         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5594                 return 267000;
5595         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5596                 return 333000;
5597         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5598                 return 444000;
5599         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5600                 return 200000;
5601         default:
5602                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5603         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5604                 return 133000;
5605         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5606                 return 167000;
5607         }
5608 }
5609
5610 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5611 {
5612         u16 gcfgc = 0;
5613
5614         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5615
5616         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5617                 return 133000;
5618         else {
5619                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5620                 case GC_DISPLAY_CLOCK_333_MHZ:
5621                         return 333000;
5622                 default:
5623                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5624                         return 190000;
5625                 }
5626         }
5627 }
5628
5629 static int i865_get_display_clock_speed(struct drm_device *dev)
5630 {
5631         return 266000;
5632 }
5633
5634 static int i855_get_display_clock_speed(struct drm_device *dev)
5635 {
5636         u16 hpllcc = 0;
5637         /* Assume that the hardware is in the high speed state.  This
5638          * should be the default.
5639          */
5640         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5641         case GC_CLOCK_133_200:
5642         case GC_CLOCK_100_200:
5643                 return 200000;
5644         case GC_CLOCK_166_250:
5645                 return 250000;
5646         case GC_CLOCK_100_133:
5647                 return 133000;
5648         }
5649
5650         /* Shouldn't happen */
5651         return 0;
5652 }
5653
5654 static int i830_get_display_clock_speed(struct drm_device *dev)
5655 {
5656         return 133000;
5657 }
5658
5659 static void
5660 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5661 {
5662         while (*num > DATA_LINK_M_N_MASK ||
5663                *den > DATA_LINK_M_N_MASK) {
5664                 *num >>= 1;
5665                 *den >>= 1;
5666         }
5667 }
5668
5669 static void compute_m_n(unsigned int m, unsigned int n,
5670                         uint32_t *ret_m, uint32_t *ret_n)
5671 {
5672         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5673         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5674         intel_reduce_m_n_ratio(ret_m, ret_n);
5675 }
5676
5677 void
5678 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5679                        int pixel_clock, int link_clock,
5680                        struct intel_link_m_n *m_n)
5681 {
5682         m_n->tu = 64;
5683
5684         compute_m_n(bits_per_pixel * pixel_clock,
5685                     link_clock * nlanes * 8,
5686                     &m_n->gmch_m, &m_n->gmch_n);
5687
5688         compute_m_n(pixel_clock, link_clock,
5689                     &m_n->link_m, &m_n->link_n);
5690 }
5691
5692 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5693 {
5694         if (i915.panel_use_ssc >= 0)
5695                 return i915.panel_use_ssc != 0;
5696         return dev_priv->vbt.lvds_use_ssc
5697                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5698 }
5699
5700 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5701 {
5702         struct drm_device *dev = crtc->base.dev;
5703         struct drm_i915_private *dev_priv = dev->dev_private;
5704         int refclk;
5705
5706         if (IS_VALLEYVIEW(dev)) {
5707                 refclk = 100000;
5708         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5709             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5710                 refclk = dev_priv->vbt.lvds_ssc_freq;
5711                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5712         } else if (!IS_GEN2(dev)) {
5713                 refclk = 96000;
5714         } else {
5715                 refclk = 48000;
5716         }
5717
5718         return refclk;
5719 }
5720
5721 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5722 {
5723         return (1 << dpll->n) << 16 | dpll->m2;
5724 }
5725
5726 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5727 {
5728         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5729 }
5730
5731 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5732                                      intel_clock_t *reduced_clock)
5733 {
5734         struct drm_device *dev = crtc->base.dev;
5735         u32 fp, fp2 = 0;
5736
5737         if (IS_PINEVIEW(dev)) {
5738                 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5739                 if (reduced_clock)
5740                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5741         } else {
5742                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5743                 if (reduced_clock)
5744                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5745         }
5746
5747         crtc->new_config->dpll_hw_state.fp0 = fp;
5748
5749         crtc->lowfreq_avail = false;
5750         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5751             reduced_clock && i915.powersave) {
5752                 crtc->new_config->dpll_hw_state.fp1 = fp2;
5753                 crtc->lowfreq_avail = true;
5754         } else {
5755                 crtc->new_config->dpll_hw_state.fp1 = fp;
5756         }
5757 }
5758
5759 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5760                 pipe)
5761 {
5762         u32 reg_val;
5763
5764         /*
5765          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5766          * and set it to a reasonable value instead.
5767          */
5768         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5769         reg_val &= 0xffffff00;
5770         reg_val |= 0x00000030;
5771         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5772
5773         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5774         reg_val &= 0x8cffffff;
5775         reg_val = 0x8c000000;
5776         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5777
5778         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5779         reg_val &= 0xffffff00;
5780         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5781
5782         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5783         reg_val &= 0x00ffffff;
5784         reg_val |= 0xb0000000;
5785         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5786 }
5787
5788 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5789                                          struct intel_link_m_n *m_n)
5790 {
5791         struct drm_device *dev = crtc->base.dev;
5792         struct drm_i915_private *dev_priv = dev->dev_private;
5793         int pipe = crtc->pipe;
5794
5795         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5796         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5797         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5798         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5799 }
5800
5801 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5802                                          struct intel_link_m_n *m_n,
5803                                          struct intel_link_m_n *m2_n2)
5804 {
5805         struct drm_device *dev = crtc->base.dev;
5806         struct drm_i915_private *dev_priv = dev->dev_private;
5807         int pipe = crtc->pipe;
5808         enum transcoder transcoder = crtc->config.cpu_transcoder;
5809
5810         if (INTEL_INFO(dev)->gen >= 5) {
5811                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5812                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5813                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5814                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5815                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5816                  * for gen < 8) and if DRRS is supported (to make sure the
5817                  * registers are not unnecessarily accessed).
5818                  */
5819                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5820                         crtc->config.has_drrs) {
5821                         I915_WRITE(PIPE_DATA_M2(transcoder),
5822                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5823                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5824                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5825                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5826                 }
5827         } else {
5828                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5829                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5830                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5831                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5832         }
5833 }
5834
5835 void intel_dp_set_m_n(struct intel_crtc *crtc)
5836 {
5837         if (crtc->config.has_pch_encoder)
5838                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5839         else
5840                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5841                                                    &crtc->config.dp_m2_n2);
5842 }
5843
5844 static void vlv_update_pll(struct intel_crtc *crtc,
5845                            struct intel_crtc_config *pipe_config)
5846 {
5847         u32 dpll, dpll_md;
5848
5849         /*
5850          * Enable DPIO clock input. We should never disable the reference
5851          * clock for pipe B, since VGA hotplug / manual detection depends
5852          * on it.
5853          */
5854         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5855                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5856         /* We should never disable this, set it here for state tracking */
5857         if (crtc->pipe == PIPE_B)
5858                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5859         dpll |= DPLL_VCO_ENABLE;
5860         pipe_config->dpll_hw_state.dpll = dpll;
5861
5862         dpll_md = (pipe_config->pixel_multiplier - 1)
5863                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5864         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5865 }
5866
5867 static void vlv_prepare_pll(struct intel_crtc *crtc,
5868                             const struct intel_crtc_config *pipe_config)
5869 {
5870         struct drm_device *dev = crtc->base.dev;
5871         struct drm_i915_private *dev_priv = dev->dev_private;
5872         int pipe = crtc->pipe;
5873         u32 mdiv;
5874         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5875         u32 coreclk, reg_val;
5876
5877         mutex_lock(&dev_priv->dpio_lock);
5878
5879         bestn = pipe_config->dpll.n;
5880         bestm1 = pipe_config->dpll.m1;
5881         bestm2 = pipe_config->dpll.m2;
5882         bestp1 = pipe_config->dpll.p1;
5883         bestp2 = pipe_config->dpll.p2;
5884
5885         /* See eDP HDMI DPIO driver vbios notes doc */
5886
5887         /* PLL B needs special handling */
5888         if (pipe == PIPE_B)
5889                 vlv_pllb_recal_opamp(dev_priv, pipe);
5890
5891         /* Set up Tx target for periodic Rcomp update */
5892         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5893
5894         /* Disable target IRef on PLL */
5895         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5896         reg_val &= 0x00ffffff;
5897         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5898
5899         /* Disable fast lock */
5900         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5901
5902         /* Set idtafcrecal before PLL is enabled */
5903         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5904         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5905         mdiv |= ((bestn << DPIO_N_SHIFT));
5906         mdiv |= (1 << DPIO_K_SHIFT);
5907
5908         /*
5909          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5910          * but we don't support that).
5911          * Note: don't use the DAC post divider as it seems unstable.
5912          */
5913         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5915
5916         mdiv |= DPIO_ENABLE_CALIBRATION;
5917         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5918
5919         /* Set HBR and RBR LPF coefficients */
5920         if (pipe_config->port_clock == 162000 ||
5921             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5922             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5923                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5924                                  0x009f0003);
5925         else
5926                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5927                                  0x00d0000f);
5928
5929         if (crtc->config.has_dp_encoder) {
5930                 /* Use SSC source */
5931                 if (pipe == PIPE_A)
5932                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5933                                          0x0df40000);
5934                 else
5935                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5936                                          0x0df70000);
5937         } else { /* HDMI or VGA */
5938                 /* Use bend source */
5939                 if (pipe == PIPE_A)
5940                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5941                                          0x0df70000);
5942                 else
5943                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5944                                          0x0df40000);
5945         }
5946
5947         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5948         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5949         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5950             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5951                 coreclk |= 0x01000000;
5952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5953
5954         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5955         mutex_unlock(&dev_priv->dpio_lock);
5956 }
5957
5958 static void chv_update_pll(struct intel_crtc *crtc,
5959                            struct intel_crtc_config *pipe_config)
5960 {
5961         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5962                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5963                 DPLL_VCO_ENABLE;
5964         if (crtc->pipe != PIPE_A)
5965                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5966
5967         pipe_config->dpll_hw_state.dpll_md =
5968                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5969 }
5970
5971 static void chv_prepare_pll(struct intel_crtc *crtc,
5972                             const struct intel_crtc_config *pipe_config)
5973 {
5974         struct drm_device *dev = crtc->base.dev;
5975         struct drm_i915_private *dev_priv = dev->dev_private;
5976         int pipe = crtc->pipe;
5977         int dpll_reg = DPLL(crtc->pipe);
5978         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5979         u32 loopfilter, intcoeff;
5980         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5981         int refclk;
5982
5983         bestn = pipe_config->dpll.n;
5984         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5985         bestm1 = pipe_config->dpll.m1;
5986         bestm2 = pipe_config->dpll.m2 >> 22;
5987         bestp1 = pipe_config->dpll.p1;
5988         bestp2 = pipe_config->dpll.p2;
5989
5990         /*
5991          * Enable Refclk and SSC
5992          */
5993         I915_WRITE(dpll_reg,
5994                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5995
5996         mutex_lock(&dev_priv->dpio_lock);
5997
5998         /* p1 and p2 divider */
5999         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6000                         5 << DPIO_CHV_S1_DIV_SHIFT |
6001                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6002                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6003                         1 << DPIO_CHV_K_DIV_SHIFT);
6004
6005         /* Feedback post-divider - m2 */
6006         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6007
6008         /* Feedback refclk divider - n and m1 */
6009         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6010                         DPIO_CHV_M1_DIV_BY_2 |
6011                         1 << DPIO_CHV_N_DIV_SHIFT);
6012
6013         /* M2 fraction division */
6014         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6015
6016         /* M2 fraction division enable */
6017         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6018                        DPIO_CHV_FRAC_DIV_EN |
6019                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6020
6021         /* Loop filter */
6022         refclk = i9xx_get_refclk(crtc, 0);
6023         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6024                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6025         if (refclk == 100000)
6026                 intcoeff = 11;
6027         else if (refclk == 38400)
6028                 intcoeff = 10;
6029         else
6030                 intcoeff = 9;
6031         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6032         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6033
6034         /* AFC Recal */
6035         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6036                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6037                         DPIO_AFC_RECAL);
6038
6039         mutex_unlock(&dev_priv->dpio_lock);
6040 }
6041
6042 /**
6043  * vlv_force_pll_on - forcibly enable just the PLL
6044  * @dev_priv: i915 private structure
6045  * @pipe: pipe PLL to enable
6046  * @dpll: PLL configuration
6047  *
6048  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6049  * in cases where we need the PLL enabled even when @pipe is not going to
6050  * be enabled.
6051  */
6052 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6053                       const struct dpll *dpll)
6054 {
6055         struct intel_crtc *crtc =
6056                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6057         struct intel_crtc_config pipe_config = {
6058                 .pixel_multiplier = 1,
6059                 .dpll = *dpll,
6060         };
6061
6062         if (IS_CHERRYVIEW(dev)) {
6063                 chv_update_pll(crtc, &pipe_config);
6064                 chv_prepare_pll(crtc, &pipe_config);
6065                 chv_enable_pll(crtc, &pipe_config);
6066         } else {
6067                 vlv_update_pll(crtc, &pipe_config);
6068                 vlv_prepare_pll(crtc, &pipe_config);
6069                 vlv_enable_pll(crtc, &pipe_config);
6070         }
6071 }
6072
6073 /**
6074  * vlv_force_pll_off - forcibly disable just the PLL
6075  * @dev_priv: i915 private structure
6076  * @pipe: pipe PLL to disable
6077  *
6078  * Disable the PLL for @pipe. To be used in cases where we need
6079  * the PLL enabled even when @pipe is not going to be enabled.
6080  */
6081 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6082 {
6083         if (IS_CHERRYVIEW(dev))
6084                 chv_disable_pll(to_i915(dev), pipe);
6085         else
6086                 vlv_disable_pll(to_i915(dev), pipe);
6087 }
6088
6089 static void i9xx_update_pll(struct intel_crtc *crtc,
6090                             intel_clock_t *reduced_clock,
6091                             int num_connectors)
6092 {
6093         struct drm_device *dev = crtc->base.dev;
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095         u32 dpll;
6096         bool is_sdvo;
6097         struct dpll *clock = &crtc->new_config->dpll;
6098
6099         i9xx_update_pll_dividers(crtc, reduced_clock);
6100
6101         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6102                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6103
6104         dpll = DPLL_VGA_MODE_DIS;
6105
6106         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6107                 dpll |= DPLLB_MODE_LVDS;
6108         else
6109                 dpll |= DPLLB_MODE_DAC_SERIAL;
6110
6111         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6112                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6113                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6114         }
6115
6116         if (is_sdvo)
6117                 dpll |= DPLL_SDVO_HIGH_SPEED;
6118
6119         if (crtc->new_config->has_dp_encoder)
6120                 dpll |= DPLL_SDVO_HIGH_SPEED;
6121
6122         /* compute bitmask from p1 value */
6123         if (IS_PINEVIEW(dev))
6124                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6125         else {
6126                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6127                 if (IS_G4X(dev) && reduced_clock)
6128                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6129         }
6130         switch (clock->p2) {
6131         case 5:
6132                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6133                 break;
6134         case 7:
6135                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6136                 break;
6137         case 10:
6138                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6139                 break;
6140         case 14:
6141                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6142                 break;
6143         }
6144         if (INTEL_INFO(dev)->gen >= 4)
6145                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6146
6147         if (crtc->new_config->sdvo_tv_clock)
6148                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6149         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6150                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6151                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6152         else
6153                 dpll |= PLL_REF_INPUT_DREFCLK;
6154
6155         dpll |= DPLL_VCO_ENABLE;
6156         crtc->new_config->dpll_hw_state.dpll = dpll;
6157
6158         if (INTEL_INFO(dev)->gen >= 4) {
6159                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6160                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6161                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6162         }
6163 }
6164
6165 static void i8xx_update_pll(struct intel_crtc *crtc,
6166                             intel_clock_t *reduced_clock,
6167                             int num_connectors)
6168 {
6169         struct drm_device *dev = crtc->base.dev;
6170         struct drm_i915_private *dev_priv = dev->dev_private;
6171         u32 dpll;
6172         struct dpll *clock = &crtc->new_config->dpll;
6173
6174         i9xx_update_pll_dividers(crtc, reduced_clock);
6175
6176         dpll = DPLL_VGA_MODE_DIS;
6177
6178         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6179                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6180         } else {
6181                 if (clock->p1 == 2)
6182                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6183                 else
6184                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6185                 if (clock->p2 == 4)
6186                         dpll |= PLL_P2_DIVIDE_BY_4;
6187         }
6188
6189         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6190                 dpll |= DPLL_DVO_2X_MODE;
6191
6192         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6193                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6194                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6195         else
6196                 dpll |= PLL_REF_INPUT_DREFCLK;
6197
6198         dpll |= DPLL_VCO_ENABLE;
6199         crtc->new_config->dpll_hw_state.dpll = dpll;
6200 }
6201
6202 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6203 {
6204         struct drm_device *dev = intel_crtc->base.dev;
6205         struct drm_i915_private *dev_priv = dev->dev_private;
6206         enum pipe pipe = intel_crtc->pipe;
6207         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6208         struct drm_display_mode *adjusted_mode =
6209                 &intel_crtc->config.adjusted_mode;
6210         uint32_t crtc_vtotal, crtc_vblank_end;
6211         int vsyncshift = 0;
6212
6213         /* We need to be careful not to changed the adjusted mode, for otherwise
6214          * the hw state checker will get angry at the mismatch. */
6215         crtc_vtotal = adjusted_mode->crtc_vtotal;
6216         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6217
6218         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6219                 /* the chip adds 2 halflines automatically */
6220                 crtc_vtotal -= 1;
6221                 crtc_vblank_end -= 1;
6222
6223                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6224                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6225                 else
6226                         vsyncshift = adjusted_mode->crtc_hsync_start -
6227                                 adjusted_mode->crtc_htotal / 2;
6228                 if (vsyncshift < 0)
6229                         vsyncshift += adjusted_mode->crtc_htotal;
6230         }
6231
6232         if (INTEL_INFO(dev)->gen > 3)
6233                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6234
6235         I915_WRITE(HTOTAL(cpu_transcoder),
6236                    (adjusted_mode->crtc_hdisplay - 1) |
6237                    ((adjusted_mode->crtc_htotal - 1) << 16));
6238         I915_WRITE(HBLANK(cpu_transcoder),
6239                    (adjusted_mode->crtc_hblank_start - 1) |
6240                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6241         I915_WRITE(HSYNC(cpu_transcoder),
6242                    (adjusted_mode->crtc_hsync_start - 1) |
6243                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6244
6245         I915_WRITE(VTOTAL(cpu_transcoder),
6246                    (adjusted_mode->crtc_vdisplay - 1) |
6247                    ((crtc_vtotal - 1) << 16));
6248         I915_WRITE(VBLANK(cpu_transcoder),
6249                    (adjusted_mode->crtc_vblank_start - 1) |
6250                    ((crtc_vblank_end - 1) << 16));
6251         I915_WRITE(VSYNC(cpu_transcoder),
6252                    (adjusted_mode->crtc_vsync_start - 1) |
6253                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6254
6255         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6256          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6257          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6258          * bits. */
6259         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6260             (pipe == PIPE_B || pipe == PIPE_C))
6261                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6262
6263         /* pipesrc controls the size that is scaled from, which should
6264          * always be the user's requested size.
6265          */
6266         I915_WRITE(PIPESRC(pipe),
6267                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6268                    (intel_crtc->config.pipe_src_h - 1));
6269 }
6270
6271 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6272                                    struct intel_crtc_config *pipe_config)
6273 {
6274         struct drm_device *dev = crtc->base.dev;
6275         struct drm_i915_private *dev_priv = dev->dev_private;
6276         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6277         uint32_t tmp;
6278
6279         tmp = I915_READ(HTOTAL(cpu_transcoder));
6280         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6281         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6282         tmp = I915_READ(HBLANK(cpu_transcoder));
6283         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6284         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6285         tmp = I915_READ(HSYNC(cpu_transcoder));
6286         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6287         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6288
6289         tmp = I915_READ(VTOTAL(cpu_transcoder));
6290         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6291         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6292         tmp = I915_READ(VBLANK(cpu_transcoder));
6293         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6294         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6295         tmp = I915_READ(VSYNC(cpu_transcoder));
6296         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6297         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6298
6299         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6300                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6301                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6302                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6303         }
6304
6305         tmp = I915_READ(PIPESRC(crtc->pipe));
6306         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6307         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6308
6309         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6310         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6311 }
6312
6313 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6314                                  struct intel_crtc_config *pipe_config)
6315 {
6316         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6317         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6318         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6319         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6320
6321         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6322         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6323         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6324         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6325
6326         mode->flags = pipe_config->adjusted_mode.flags;
6327
6328         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6329         mode->flags |= pipe_config->adjusted_mode.flags;
6330 }
6331
6332 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6333 {
6334         struct drm_device *dev = intel_crtc->base.dev;
6335         struct drm_i915_private *dev_priv = dev->dev_private;
6336         uint32_t pipeconf;
6337
6338         pipeconf = 0;
6339
6340         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6341             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6342                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6343
6344         if (intel_crtc->config.double_wide)
6345                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6346
6347         /* only g4x and later have fancy bpc/dither controls */
6348         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6349                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6350                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6351                         pipeconf |= PIPECONF_DITHER_EN |
6352                                     PIPECONF_DITHER_TYPE_SP;
6353
6354                 switch (intel_crtc->config.pipe_bpp) {
6355                 case 18:
6356                         pipeconf |= PIPECONF_6BPC;
6357                         break;
6358                 case 24:
6359                         pipeconf |= PIPECONF_8BPC;
6360                         break;
6361                 case 30:
6362                         pipeconf |= PIPECONF_10BPC;
6363                         break;
6364                 default:
6365                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6366                         BUG();
6367                 }
6368         }
6369
6370         if (HAS_PIPE_CXSR(dev)) {
6371                 if (intel_crtc->lowfreq_avail) {
6372                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6373                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6374                 } else {
6375                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6376                 }
6377         }
6378
6379         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6380                 if (INTEL_INFO(dev)->gen < 4 ||
6381                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6382                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6383                 else
6384                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6385         } else
6386                 pipeconf |= PIPECONF_PROGRESSIVE;
6387
6388         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6389                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6390
6391         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6392         POSTING_READ(PIPECONF(intel_crtc->pipe));
6393 }
6394
6395 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6396 {
6397         struct drm_device *dev = crtc->base.dev;
6398         struct drm_i915_private *dev_priv = dev->dev_private;
6399         int refclk, num_connectors = 0;
6400         intel_clock_t clock, reduced_clock;
6401         bool ok, has_reduced_clock = false;
6402         bool is_lvds = false, is_dsi = false;
6403         struct intel_encoder *encoder;
6404         const intel_limit_t *limit;
6405
6406         for_each_intel_encoder(dev, encoder) {
6407                 if (encoder->new_crtc != crtc)
6408                         continue;
6409
6410                 switch (encoder->type) {
6411                 case INTEL_OUTPUT_LVDS:
6412                         is_lvds = true;
6413                         break;
6414                 case INTEL_OUTPUT_DSI:
6415                         is_dsi = true;
6416                         break;
6417                 default:
6418                         break;
6419                 }
6420
6421                 num_connectors++;
6422         }
6423
6424         if (is_dsi)
6425                 return 0;
6426
6427         if (!crtc->new_config->clock_set) {
6428                 refclk = i9xx_get_refclk(crtc, num_connectors);
6429
6430                 /*
6431                  * Returns a set of divisors for the desired target clock with
6432                  * the given refclk, or FALSE.  The returned values represent
6433                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6434                  * 2) / p1 / p2.
6435                  */
6436                 limit = intel_limit(crtc, refclk);
6437                 ok = dev_priv->display.find_dpll(limit, crtc,
6438                                                  crtc->new_config->port_clock,
6439                                                  refclk, NULL, &clock);
6440                 if (!ok) {
6441                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6442                         return -EINVAL;
6443                 }
6444
6445                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6446                         /*
6447                          * Ensure we match the reduced clock's P to the target
6448                          * clock.  If the clocks don't match, we can't switch
6449                          * the display clock by using the FP0/FP1. In such case
6450                          * we will disable the LVDS downclock feature.
6451                          */
6452                         has_reduced_clock =
6453                                 dev_priv->display.find_dpll(limit, crtc,
6454                                                             dev_priv->lvds_downclock,
6455                                                             refclk, &clock,
6456                                                             &reduced_clock);
6457                 }
6458                 /* Compat-code for transition, will disappear. */
6459                 crtc->new_config->dpll.n = clock.n;
6460                 crtc->new_config->dpll.m1 = clock.m1;
6461                 crtc->new_config->dpll.m2 = clock.m2;
6462                 crtc->new_config->dpll.p1 = clock.p1;
6463                 crtc->new_config->dpll.p2 = clock.p2;
6464         }
6465
6466         if (IS_GEN2(dev)) {
6467                 i8xx_update_pll(crtc,
6468                                 has_reduced_clock ? &reduced_clock : NULL,
6469                                 num_connectors);
6470         } else if (IS_CHERRYVIEW(dev)) {
6471                 chv_update_pll(crtc, crtc->new_config);
6472         } else if (IS_VALLEYVIEW(dev)) {
6473                 vlv_update_pll(crtc, crtc->new_config);
6474         } else {
6475                 i9xx_update_pll(crtc,
6476                                 has_reduced_clock ? &reduced_clock : NULL,
6477                                 num_connectors);
6478         }
6479
6480         return 0;
6481 }
6482
6483 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6484                                  struct intel_crtc_config *pipe_config)
6485 {
6486         struct drm_device *dev = crtc->base.dev;
6487         struct drm_i915_private *dev_priv = dev->dev_private;
6488         uint32_t tmp;
6489
6490         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6491                 return;
6492
6493         tmp = I915_READ(PFIT_CONTROL);
6494         if (!(tmp & PFIT_ENABLE))
6495                 return;
6496
6497         /* Check whether the pfit is attached to our pipe. */
6498         if (INTEL_INFO(dev)->gen < 4) {
6499                 if (crtc->pipe != PIPE_B)
6500                         return;
6501         } else {
6502                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6503                         return;
6504         }
6505
6506         pipe_config->gmch_pfit.control = tmp;
6507         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6508         if (INTEL_INFO(dev)->gen < 5)
6509                 pipe_config->gmch_pfit.lvds_border_bits =
6510                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6511 }
6512
6513 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6514                                struct intel_crtc_config *pipe_config)
6515 {
6516         struct drm_device *dev = crtc->base.dev;
6517         struct drm_i915_private *dev_priv = dev->dev_private;
6518         int pipe = pipe_config->cpu_transcoder;
6519         intel_clock_t clock;
6520         u32 mdiv;
6521         int refclk = 100000;
6522
6523         /* In case of MIPI DPLL will not even be used */
6524         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6525                 return;
6526
6527         mutex_lock(&dev_priv->dpio_lock);
6528         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6529         mutex_unlock(&dev_priv->dpio_lock);
6530
6531         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6532         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6533         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6534         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6535         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6536
6537         vlv_clock(refclk, &clock);
6538
6539         /* clock.dot is the fast clock */
6540         pipe_config->port_clock = clock.dot / 5;
6541 }
6542
6543 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6544                                   struct intel_plane_config *plane_config)
6545 {
6546         struct drm_device *dev = crtc->base.dev;
6547         struct drm_i915_private *dev_priv = dev->dev_private;
6548         u32 val, base, offset;
6549         int pipe = crtc->pipe, plane = crtc->plane;
6550         int fourcc, pixel_format;
6551         int aligned_height;
6552
6553         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6554         if (!crtc->base.primary->fb) {
6555                 DRM_DEBUG_KMS("failed to alloc fb\n");
6556                 return;
6557         }
6558
6559         val = I915_READ(DSPCNTR(plane));
6560
6561         if (INTEL_INFO(dev)->gen >= 4)
6562                 if (val & DISPPLANE_TILED)
6563                         plane_config->tiled = true;
6564
6565         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6566         fourcc = intel_format_to_fourcc(pixel_format);
6567         crtc->base.primary->fb->pixel_format = fourcc;
6568         crtc->base.primary->fb->bits_per_pixel =
6569                 drm_format_plane_cpp(fourcc, 0) * 8;
6570
6571         if (INTEL_INFO(dev)->gen >= 4) {
6572                 if (plane_config->tiled)
6573                         offset = I915_READ(DSPTILEOFF(plane));
6574                 else
6575                         offset = I915_READ(DSPLINOFF(plane));
6576                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6577         } else {
6578                 base = I915_READ(DSPADDR(plane));
6579         }
6580         plane_config->base = base;
6581
6582         val = I915_READ(PIPESRC(pipe));
6583         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6584         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6585
6586         val = I915_READ(DSPSTRIDE(pipe));
6587         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6588
6589         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6590                                             plane_config->tiled);
6591
6592         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6593                                         aligned_height);
6594
6595         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6596                       pipe, plane, crtc->base.primary->fb->width,
6597                       crtc->base.primary->fb->height,
6598                       crtc->base.primary->fb->bits_per_pixel, base,
6599                       crtc->base.primary->fb->pitches[0],
6600                       plane_config->size);
6601
6602 }
6603
6604 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6605                                struct intel_crtc_config *pipe_config)
6606 {
6607         struct drm_device *dev = crtc->base.dev;
6608         struct drm_i915_private *dev_priv = dev->dev_private;
6609         int pipe = pipe_config->cpu_transcoder;
6610         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6611         intel_clock_t clock;
6612         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6613         int refclk = 100000;
6614
6615         mutex_lock(&dev_priv->dpio_lock);
6616         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6617         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6618         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6619         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6620         mutex_unlock(&dev_priv->dpio_lock);
6621
6622         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6623         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6624         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6625         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6626         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6627
6628         chv_clock(refclk, &clock);
6629
6630         /* clock.dot is the fast clock */
6631         pipe_config->port_clock = clock.dot / 5;
6632 }
6633
6634 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6635                                  struct intel_crtc_config *pipe_config)
6636 {
6637         struct drm_device *dev = crtc->base.dev;
6638         struct drm_i915_private *dev_priv = dev->dev_private;
6639         uint32_t tmp;
6640
6641         if (!intel_display_power_is_enabled(dev_priv,
6642                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6643                 return false;
6644
6645         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6646         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6647
6648         tmp = I915_READ(PIPECONF(crtc->pipe));
6649         if (!(tmp & PIPECONF_ENABLE))
6650                 return false;
6651
6652         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6653                 switch (tmp & PIPECONF_BPC_MASK) {
6654                 case PIPECONF_6BPC:
6655                         pipe_config->pipe_bpp = 18;
6656                         break;
6657                 case PIPECONF_8BPC:
6658                         pipe_config->pipe_bpp = 24;
6659                         break;
6660                 case PIPECONF_10BPC:
6661                         pipe_config->pipe_bpp = 30;
6662                         break;
6663                 default:
6664                         break;
6665                 }
6666         }
6667
6668         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6669                 pipe_config->limited_color_range = true;
6670
6671         if (INTEL_INFO(dev)->gen < 4)
6672                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6673
6674         intel_get_pipe_timings(crtc, pipe_config);
6675
6676         i9xx_get_pfit_config(crtc, pipe_config);
6677
6678         if (INTEL_INFO(dev)->gen >= 4) {
6679                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6680                 pipe_config->pixel_multiplier =
6681                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6682                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6683                 pipe_config->dpll_hw_state.dpll_md = tmp;
6684         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6685                 tmp = I915_READ(DPLL(crtc->pipe));
6686                 pipe_config->pixel_multiplier =
6687                         ((tmp & SDVO_MULTIPLIER_MASK)
6688                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6689         } else {
6690                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6691                  * port and will be fixed up in the encoder->get_config
6692                  * function. */
6693                 pipe_config->pixel_multiplier = 1;
6694         }
6695         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6696         if (!IS_VALLEYVIEW(dev)) {
6697                 /*
6698                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6699                  * on 830. Filter it out here so that we don't
6700                  * report errors due to that.
6701                  */
6702                 if (IS_I830(dev))
6703                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6704
6705                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6706                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6707         } else {
6708                 /* Mask out read-only status bits. */
6709                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6710                                                      DPLL_PORTC_READY_MASK |
6711                                                      DPLL_PORTB_READY_MASK);
6712         }
6713
6714         if (IS_CHERRYVIEW(dev))
6715                 chv_crtc_clock_get(crtc, pipe_config);
6716         else if (IS_VALLEYVIEW(dev))
6717                 vlv_crtc_clock_get(crtc, pipe_config);
6718         else
6719                 i9xx_crtc_clock_get(crtc, pipe_config);
6720
6721         return true;
6722 }
6723
6724 static void ironlake_init_pch_refclk(struct drm_device *dev)
6725 {
6726         struct drm_i915_private *dev_priv = dev->dev_private;
6727         struct intel_encoder *encoder;
6728         u32 val, final;
6729         bool has_lvds = false;
6730         bool has_cpu_edp = false;
6731         bool has_panel = false;
6732         bool has_ck505 = false;
6733         bool can_ssc = false;
6734
6735         /* We need to take the global config into account */
6736         for_each_intel_encoder(dev, encoder) {
6737                 switch (encoder->type) {
6738                 case INTEL_OUTPUT_LVDS:
6739                         has_panel = true;
6740                         has_lvds = true;
6741                         break;
6742                 case INTEL_OUTPUT_EDP:
6743                         has_panel = true;
6744                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6745                                 has_cpu_edp = true;
6746                         break;
6747                 default:
6748                         break;
6749                 }
6750         }
6751
6752         if (HAS_PCH_IBX(dev)) {
6753                 has_ck505 = dev_priv->vbt.display_clock_mode;
6754                 can_ssc = has_ck505;
6755         } else {
6756                 has_ck505 = false;
6757                 can_ssc = true;
6758         }
6759
6760         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6761                       has_panel, has_lvds, has_ck505);
6762
6763         /* Ironlake: try to setup display ref clock before DPLL
6764          * enabling. This is only under driver's control after
6765          * PCH B stepping, previous chipset stepping should be
6766          * ignoring this setting.
6767          */
6768         val = I915_READ(PCH_DREF_CONTROL);
6769
6770         /* As we must carefully and slowly disable/enable each source in turn,
6771          * compute the final state we want first and check if we need to
6772          * make any changes at all.
6773          */
6774         final = val;
6775         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6776         if (has_ck505)
6777                 final |= DREF_NONSPREAD_CK505_ENABLE;
6778         else
6779                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6780
6781         final &= ~DREF_SSC_SOURCE_MASK;
6782         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6783         final &= ~DREF_SSC1_ENABLE;
6784
6785         if (has_panel) {
6786                 final |= DREF_SSC_SOURCE_ENABLE;
6787
6788                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6789                         final |= DREF_SSC1_ENABLE;
6790
6791                 if (has_cpu_edp) {
6792                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6793                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6794                         else
6795                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6796                 } else
6797                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6798         } else {
6799                 final |= DREF_SSC_SOURCE_DISABLE;
6800                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6801         }
6802
6803         if (final == val)
6804                 return;
6805
6806         /* Always enable nonspread source */
6807         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6808
6809         if (has_ck505)
6810                 val |= DREF_NONSPREAD_CK505_ENABLE;
6811         else
6812                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6813
6814         if (has_panel) {
6815                 val &= ~DREF_SSC_SOURCE_MASK;
6816                 val |= DREF_SSC_SOURCE_ENABLE;
6817
6818                 /* SSC must be turned on before enabling the CPU output  */
6819                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6820                         DRM_DEBUG_KMS("Using SSC on panel\n");
6821                         val |= DREF_SSC1_ENABLE;
6822                 } else
6823                         val &= ~DREF_SSC1_ENABLE;
6824
6825                 /* Get SSC going before enabling the outputs */
6826                 I915_WRITE(PCH_DREF_CONTROL, val);
6827                 POSTING_READ(PCH_DREF_CONTROL);
6828                 udelay(200);
6829
6830                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6831
6832                 /* Enable CPU source on CPU attached eDP */
6833                 if (has_cpu_edp) {
6834                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6835                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6836                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6837                         } else
6838                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6839                 } else
6840                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6841
6842                 I915_WRITE(PCH_DREF_CONTROL, val);
6843                 POSTING_READ(PCH_DREF_CONTROL);
6844                 udelay(200);
6845         } else {
6846                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6847
6848                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6849
6850                 /* Turn off CPU output */
6851                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6852
6853                 I915_WRITE(PCH_DREF_CONTROL, val);
6854                 POSTING_READ(PCH_DREF_CONTROL);
6855                 udelay(200);
6856
6857                 /* Turn off the SSC source */
6858                 val &= ~DREF_SSC_SOURCE_MASK;
6859                 val |= DREF_SSC_SOURCE_DISABLE;
6860
6861                 /* Turn off SSC1 */
6862                 val &= ~DREF_SSC1_ENABLE;
6863
6864                 I915_WRITE(PCH_DREF_CONTROL, val);
6865                 POSTING_READ(PCH_DREF_CONTROL);
6866                 udelay(200);
6867         }
6868
6869         BUG_ON(val != final);
6870 }
6871
6872 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6873 {
6874         uint32_t tmp;
6875
6876         tmp = I915_READ(SOUTH_CHICKEN2);
6877         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6878         I915_WRITE(SOUTH_CHICKEN2, tmp);
6879
6880         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6881                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6882                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6883
6884         tmp = I915_READ(SOUTH_CHICKEN2);
6885         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6886         I915_WRITE(SOUTH_CHICKEN2, tmp);
6887
6888         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6889                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6890                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6891 }
6892
6893 /* WaMPhyProgramming:hsw */
6894 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6895 {
6896         uint32_t tmp;
6897
6898         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6899         tmp &= ~(0xFF << 24);
6900         tmp |= (0x12 << 24);
6901         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6902
6903         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6904         tmp |= (1 << 11);
6905         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6906
6907         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6908         tmp |= (1 << 11);
6909         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6910
6911         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6912         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6913         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6914
6915         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6916         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6917         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6918
6919         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6920         tmp &= ~(7 << 13);
6921         tmp |= (5 << 13);
6922         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6923
6924         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6925         tmp &= ~(7 << 13);
6926         tmp |= (5 << 13);
6927         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6928
6929         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6930         tmp &= ~0xFF;
6931         tmp |= 0x1C;
6932         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6933
6934         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6935         tmp &= ~0xFF;
6936         tmp |= 0x1C;
6937         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6938
6939         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6940         tmp &= ~(0xFF << 16);
6941         tmp |= (0x1C << 16);
6942         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6943
6944         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6945         tmp &= ~(0xFF << 16);
6946         tmp |= (0x1C << 16);
6947         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6948
6949         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6950         tmp |= (1 << 27);
6951         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6952
6953         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6954         tmp |= (1 << 27);
6955         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6956
6957         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6958         tmp &= ~(0xF << 28);
6959         tmp |= (4 << 28);
6960         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6961
6962         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6963         tmp &= ~(0xF << 28);
6964         tmp |= (4 << 28);
6965         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6966 }
6967
6968 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6969  * Programming" based on the parameters passed:
6970  * - Sequence to enable CLKOUT_DP
6971  * - Sequence to enable CLKOUT_DP without spread
6972  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6973  */
6974 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6975                                  bool with_fdi)
6976 {
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978         uint32_t reg, tmp;
6979
6980         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6981                 with_spread = true;
6982         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6983                  with_fdi, "LP PCH doesn't have FDI\n"))
6984                 with_fdi = false;
6985
6986         mutex_lock(&dev_priv->dpio_lock);
6987
6988         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6989         tmp &= ~SBI_SSCCTL_DISABLE;
6990         tmp |= SBI_SSCCTL_PATHALT;
6991         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6992
6993         udelay(24);
6994
6995         if (with_spread) {
6996                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6997                 tmp &= ~SBI_SSCCTL_PATHALT;
6998                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6999
7000                 if (with_fdi) {
7001                         lpt_reset_fdi_mphy(dev_priv);
7002                         lpt_program_fdi_mphy(dev_priv);
7003                 }
7004         }
7005
7006         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7007                SBI_GEN0 : SBI_DBUFF0;
7008         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7009         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7010         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7011
7012         mutex_unlock(&dev_priv->dpio_lock);
7013 }
7014
7015 /* Sequence to disable CLKOUT_DP */
7016 static void lpt_disable_clkout_dp(struct drm_device *dev)
7017 {
7018         struct drm_i915_private *dev_priv = dev->dev_private;
7019         uint32_t reg, tmp;
7020
7021         mutex_lock(&dev_priv->dpio_lock);
7022
7023         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7024                SBI_GEN0 : SBI_DBUFF0;
7025         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7026         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7027         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7028
7029         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7030         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7031                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7032                         tmp |= SBI_SSCCTL_PATHALT;
7033                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7034                         udelay(32);
7035                 }
7036                 tmp |= SBI_SSCCTL_DISABLE;
7037                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7038         }
7039
7040         mutex_unlock(&dev_priv->dpio_lock);
7041 }
7042
7043 static void lpt_init_pch_refclk(struct drm_device *dev)
7044 {
7045         struct intel_encoder *encoder;
7046         bool has_vga = false;
7047
7048         for_each_intel_encoder(dev, encoder) {
7049                 switch (encoder->type) {
7050                 case INTEL_OUTPUT_ANALOG:
7051                         has_vga = true;
7052                         break;
7053                 default:
7054                         break;
7055                 }
7056         }
7057
7058         if (has_vga)
7059                 lpt_enable_clkout_dp(dev, true, true);
7060         else
7061                 lpt_disable_clkout_dp(dev);
7062 }
7063
7064 /*
7065  * Initialize reference clocks when the driver loads
7066  */
7067 void intel_init_pch_refclk(struct drm_device *dev)
7068 {
7069         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7070                 ironlake_init_pch_refclk(dev);
7071         else if (HAS_PCH_LPT(dev))
7072                 lpt_init_pch_refclk(dev);
7073 }
7074
7075 static int ironlake_get_refclk(struct drm_crtc *crtc)
7076 {
7077         struct drm_device *dev = crtc->dev;
7078         struct drm_i915_private *dev_priv = dev->dev_private;
7079         struct intel_encoder *encoder;
7080         int num_connectors = 0;
7081         bool is_lvds = false;
7082
7083         for_each_intel_encoder(dev, encoder) {
7084                 if (encoder->new_crtc != to_intel_crtc(crtc))
7085                         continue;
7086
7087                 switch (encoder->type) {
7088                 case INTEL_OUTPUT_LVDS:
7089                         is_lvds = true;
7090                         break;
7091                 default:
7092                         break;
7093                 }
7094                 num_connectors++;
7095         }
7096
7097         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7098                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7099                               dev_priv->vbt.lvds_ssc_freq);
7100                 return dev_priv->vbt.lvds_ssc_freq;
7101         }
7102
7103         return 120000;
7104 }
7105
7106 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7107 {
7108         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7110         int pipe = intel_crtc->pipe;
7111         uint32_t val;
7112
7113         val = 0;
7114
7115         switch (intel_crtc->config.pipe_bpp) {
7116         case 18:
7117                 val |= PIPECONF_6BPC;
7118                 break;
7119         case 24:
7120                 val |= PIPECONF_8BPC;
7121                 break;
7122         case 30:
7123                 val |= PIPECONF_10BPC;
7124                 break;
7125         case 36:
7126                 val |= PIPECONF_12BPC;
7127                 break;
7128         default:
7129                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7130                 BUG();
7131         }
7132
7133         if (intel_crtc->config.dither)
7134                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7135
7136         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7137                 val |= PIPECONF_INTERLACED_ILK;
7138         else
7139                 val |= PIPECONF_PROGRESSIVE;
7140
7141         if (intel_crtc->config.limited_color_range)
7142                 val |= PIPECONF_COLOR_RANGE_SELECT;
7143
7144         I915_WRITE(PIPECONF(pipe), val);
7145         POSTING_READ(PIPECONF(pipe));
7146 }
7147
7148 /*
7149  * Set up the pipe CSC unit.
7150  *
7151  * Currently only full range RGB to limited range RGB conversion
7152  * is supported, but eventually this should handle various
7153  * RGB<->YCbCr scenarios as well.
7154  */
7155 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7156 {
7157         struct drm_device *dev = crtc->dev;
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7160         int pipe = intel_crtc->pipe;
7161         uint16_t coeff = 0x7800; /* 1.0 */
7162
7163         /*
7164          * TODO: Check what kind of values actually come out of the pipe
7165          * with these coeff/postoff values and adjust to get the best
7166          * accuracy. Perhaps we even need to take the bpc value into
7167          * consideration.
7168          */
7169
7170         if (intel_crtc->config.limited_color_range)
7171                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7172
7173         /*
7174          * GY/GU and RY/RU should be the other way around according
7175          * to BSpec, but reality doesn't agree. Just set them up in
7176          * a way that results in the correct picture.
7177          */
7178         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7179         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7180
7181         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7182         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7183
7184         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7185         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7186
7187         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7188         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7189         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7190
7191         if (INTEL_INFO(dev)->gen > 6) {
7192                 uint16_t postoff = 0;
7193
7194                 if (intel_crtc->config.limited_color_range)
7195                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7196
7197                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7198                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7199                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7200
7201                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7202         } else {
7203                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7204
7205                 if (intel_crtc->config.limited_color_range)
7206                         mode |= CSC_BLACK_SCREEN_OFFSET;
7207
7208                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7209         }
7210 }
7211
7212 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7213 {
7214         struct drm_device *dev = crtc->dev;
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217         enum pipe pipe = intel_crtc->pipe;
7218         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7219         uint32_t val;
7220
7221         val = 0;
7222
7223         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7224                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7225
7226         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7227                 val |= PIPECONF_INTERLACED_ILK;
7228         else
7229                 val |= PIPECONF_PROGRESSIVE;
7230
7231         I915_WRITE(PIPECONF(cpu_transcoder), val);
7232         POSTING_READ(PIPECONF(cpu_transcoder));
7233
7234         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7235         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7236
7237         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7238                 val = 0;
7239
7240                 switch (intel_crtc->config.pipe_bpp) {
7241                 case 18:
7242                         val |= PIPEMISC_DITHER_6_BPC;
7243                         break;
7244                 case 24:
7245                         val |= PIPEMISC_DITHER_8_BPC;
7246                         break;
7247                 case 30:
7248                         val |= PIPEMISC_DITHER_10_BPC;
7249                         break;
7250                 case 36:
7251                         val |= PIPEMISC_DITHER_12_BPC;
7252                         break;
7253                 default:
7254                         /* Case prevented by pipe_config_set_bpp. */
7255                         BUG();
7256                 }
7257
7258                 if (intel_crtc->config.dither)
7259                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7260
7261                 I915_WRITE(PIPEMISC(pipe), val);
7262         }
7263 }
7264
7265 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7266                                     intel_clock_t *clock,
7267                                     bool *has_reduced_clock,
7268                                     intel_clock_t *reduced_clock)
7269 {
7270         struct drm_device *dev = crtc->dev;
7271         struct drm_i915_private *dev_priv = dev->dev_private;
7272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7273         int refclk;
7274         const intel_limit_t *limit;
7275         bool ret, is_lvds = false;
7276
7277         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7278
7279         refclk = ironlake_get_refclk(crtc);
7280
7281         /*
7282          * Returns a set of divisors for the desired target clock with the given
7283          * refclk, or FALSE.  The returned values represent the clock equation:
7284          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7285          */
7286         limit = intel_limit(intel_crtc, refclk);
7287         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7288                                           intel_crtc->new_config->port_clock,
7289                                           refclk, NULL, clock);
7290         if (!ret)
7291                 return false;
7292
7293         if (is_lvds && dev_priv->lvds_downclock_avail) {
7294                 /*
7295                  * Ensure we match the reduced clock's P to the target clock.
7296                  * If the clocks don't match, we can't switch the display clock
7297                  * by using the FP0/FP1. In such case we will disable the LVDS
7298                  * downclock feature.
7299                 */
7300                 *has_reduced_clock =
7301                         dev_priv->display.find_dpll(limit, intel_crtc,
7302                                                     dev_priv->lvds_downclock,
7303                                                     refclk, clock,
7304                                                     reduced_clock);
7305         }
7306
7307         return true;
7308 }
7309
7310 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7311 {
7312         /*
7313          * Account for spread spectrum to avoid
7314          * oversubscribing the link. Max center spread
7315          * is 2.5%; use 5% for safety's sake.
7316          */
7317         u32 bps = target_clock * bpp * 21 / 20;
7318         return DIV_ROUND_UP(bps, link_bw * 8);
7319 }
7320
7321 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7322 {
7323         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7324 }
7325
7326 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7327                                       u32 *fp,
7328                                       intel_clock_t *reduced_clock, u32 *fp2)
7329 {
7330         struct drm_crtc *crtc = &intel_crtc->base;
7331         struct drm_device *dev = crtc->dev;
7332         struct drm_i915_private *dev_priv = dev->dev_private;
7333         struct intel_encoder *intel_encoder;
7334         uint32_t dpll;
7335         int factor, num_connectors = 0;
7336         bool is_lvds = false, is_sdvo = false;
7337
7338         for_each_intel_encoder(dev, intel_encoder) {
7339                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7340                         continue;
7341
7342                 switch (intel_encoder->type) {
7343                 case INTEL_OUTPUT_LVDS:
7344                         is_lvds = true;
7345                         break;
7346                 case INTEL_OUTPUT_SDVO:
7347                 case INTEL_OUTPUT_HDMI:
7348                         is_sdvo = true;
7349                         break;
7350                 default:
7351                         break;
7352                 }
7353
7354                 num_connectors++;
7355         }
7356
7357         /* Enable autotuning of the PLL clock (if permissible) */
7358         factor = 21;
7359         if (is_lvds) {
7360                 if ((intel_panel_use_ssc(dev_priv) &&
7361                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7362                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7363                         factor = 25;
7364         } else if (intel_crtc->new_config->sdvo_tv_clock)
7365                 factor = 20;
7366
7367         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7368                 *fp |= FP_CB_TUNE;
7369
7370         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7371                 *fp2 |= FP_CB_TUNE;
7372
7373         dpll = 0;
7374
7375         if (is_lvds)
7376                 dpll |= DPLLB_MODE_LVDS;
7377         else
7378                 dpll |= DPLLB_MODE_DAC_SERIAL;
7379
7380         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7381                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7382
7383         if (is_sdvo)
7384                 dpll |= DPLL_SDVO_HIGH_SPEED;
7385         if (intel_crtc->new_config->has_dp_encoder)
7386                 dpll |= DPLL_SDVO_HIGH_SPEED;
7387
7388         /* compute bitmask from p1 value */
7389         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7390         /* also FPA1 */
7391         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7392
7393         switch (intel_crtc->new_config->dpll.p2) {
7394         case 5:
7395                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7396                 break;
7397         case 7:
7398                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7399                 break;
7400         case 10:
7401                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7402                 break;
7403         case 14:
7404                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7405                 break;
7406         }
7407
7408         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7409                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7410         else
7411                 dpll |= PLL_REF_INPUT_DREFCLK;
7412
7413         return dpll | DPLL_VCO_ENABLE;
7414 }
7415
7416 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7417 {
7418         struct drm_device *dev = crtc->base.dev;
7419         intel_clock_t clock, reduced_clock;
7420         u32 dpll = 0, fp = 0, fp2 = 0;
7421         bool ok, has_reduced_clock = false;
7422         bool is_lvds = false;
7423         struct intel_shared_dpll *pll;
7424
7425         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7426
7427         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7428              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7429
7430         ok = ironlake_compute_clocks(&crtc->base, &clock,
7431                                      &has_reduced_clock, &reduced_clock);
7432         if (!ok && !crtc->new_config->clock_set) {
7433                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7434                 return -EINVAL;
7435         }
7436         /* Compat-code for transition, will disappear. */
7437         if (!crtc->new_config->clock_set) {
7438                 crtc->new_config->dpll.n = clock.n;
7439                 crtc->new_config->dpll.m1 = clock.m1;
7440                 crtc->new_config->dpll.m2 = clock.m2;
7441                 crtc->new_config->dpll.p1 = clock.p1;
7442                 crtc->new_config->dpll.p2 = clock.p2;
7443         }
7444
7445         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7446         if (crtc->new_config->has_pch_encoder) {
7447                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7448                 if (has_reduced_clock)
7449                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7450
7451                 dpll = ironlake_compute_dpll(crtc,
7452                                              &fp, &reduced_clock,
7453                                              has_reduced_clock ? &fp2 : NULL);
7454
7455                 crtc->new_config->dpll_hw_state.dpll = dpll;
7456                 crtc->new_config->dpll_hw_state.fp0 = fp;
7457                 if (has_reduced_clock)
7458                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7459                 else
7460                         crtc->new_config->dpll_hw_state.fp1 = fp;
7461
7462                 pll = intel_get_shared_dpll(crtc);
7463                 if (pll == NULL) {
7464                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7465                                          pipe_name(crtc->pipe));
7466                         return -EINVAL;
7467                 }
7468         }
7469
7470         if (is_lvds && has_reduced_clock && i915.powersave)
7471                 crtc->lowfreq_avail = true;
7472         else
7473                 crtc->lowfreq_avail = false;
7474
7475         return 0;
7476 }
7477
7478 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7479                                          struct intel_link_m_n *m_n)
7480 {
7481         struct drm_device *dev = crtc->base.dev;
7482         struct drm_i915_private *dev_priv = dev->dev_private;
7483         enum pipe pipe = crtc->pipe;
7484
7485         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7486         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7487         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7488                 & ~TU_SIZE_MASK;
7489         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7490         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7491                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7492 }
7493
7494 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7495                                          enum transcoder transcoder,
7496                                          struct intel_link_m_n *m_n,
7497                                          struct intel_link_m_n *m2_n2)
7498 {
7499         struct drm_device *dev = crtc->base.dev;
7500         struct drm_i915_private *dev_priv = dev->dev_private;
7501         enum pipe pipe = crtc->pipe;
7502
7503         if (INTEL_INFO(dev)->gen >= 5) {
7504                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7505                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7506                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7507                         & ~TU_SIZE_MASK;
7508                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7509                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7510                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7511                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7512                  * gen < 8) and if DRRS is supported (to make sure the
7513                  * registers are not unnecessarily read).
7514                  */
7515                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7516                         crtc->config.has_drrs) {
7517                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7518                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7519                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7520                                         & ~TU_SIZE_MASK;
7521                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7522                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7523                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7524                 }
7525         } else {
7526                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7527                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7528                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7529                         & ~TU_SIZE_MASK;
7530                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7531                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7532                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7533         }
7534 }
7535
7536 void intel_dp_get_m_n(struct intel_crtc *crtc,
7537                       struct intel_crtc_config *pipe_config)
7538 {
7539         if (crtc->config.has_pch_encoder)
7540                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7541         else
7542                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7543                                              &pipe_config->dp_m_n,
7544                                              &pipe_config->dp_m2_n2);
7545 }
7546
7547 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7548                                         struct intel_crtc_config *pipe_config)
7549 {
7550         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7551                                      &pipe_config->fdi_m_n, NULL);
7552 }
7553
7554 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7555                                     struct intel_crtc_config *pipe_config)
7556 {
7557         struct drm_device *dev = crtc->base.dev;
7558         struct drm_i915_private *dev_priv = dev->dev_private;
7559         uint32_t tmp;
7560
7561         tmp = I915_READ(PS_CTL(crtc->pipe));
7562
7563         if (tmp & PS_ENABLE) {
7564                 pipe_config->pch_pfit.enabled = true;
7565                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7566                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7567         }
7568 }
7569
7570 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7571                                      struct intel_crtc_config *pipe_config)
7572 {
7573         struct drm_device *dev = crtc->base.dev;
7574         struct drm_i915_private *dev_priv = dev->dev_private;
7575         uint32_t tmp;
7576
7577         tmp = I915_READ(PF_CTL(crtc->pipe));
7578
7579         if (tmp & PF_ENABLE) {
7580                 pipe_config->pch_pfit.enabled = true;
7581                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7582                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7583
7584                 /* We currently do not free assignements of panel fitters on
7585                  * ivb/hsw (since we don't use the higher upscaling modes which
7586                  * differentiates them) so just WARN about this case for now. */
7587                 if (IS_GEN7(dev)) {
7588                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7589                                 PF_PIPE_SEL_IVB(crtc->pipe));
7590                 }
7591         }
7592 }
7593
7594 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7595                                       struct intel_plane_config *plane_config)
7596 {
7597         struct drm_device *dev = crtc->base.dev;
7598         struct drm_i915_private *dev_priv = dev->dev_private;
7599         u32 val, base, offset;
7600         int pipe = crtc->pipe, plane = crtc->plane;
7601         int fourcc, pixel_format;
7602         int aligned_height;
7603
7604         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7605         if (!crtc->base.primary->fb) {
7606                 DRM_DEBUG_KMS("failed to alloc fb\n");
7607                 return;
7608         }
7609
7610         val = I915_READ(DSPCNTR(plane));
7611
7612         if (INTEL_INFO(dev)->gen >= 4)
7613                 if (val & DISPPLANE_TILED)
7614                         plane_config->tiled = true;
7615
7616         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7617         fourcc = intel_format_to_fourcc(pixel_format);
7618         crtc->base.primary->fb->pixel_format = fourcc;
7619         crtc->base.primary->fb->bits_per_pixel =
7620                 drm_format_plane_cpp(fourcc, 0) * 8;
7621
7622         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7623         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7624                 offset = I915_READ(DSPOFFSET(plane));
7625         } else {
7626                 if (plane_config->tiled)
7627                         offset = I915_READ(DSPTILEOFF(plane));
7628                 else
7629                         offset = I915_READ(DSPLINOFF(plane));
7630         }
7631         plane_config->base = base;
7632
7633         val = I915_READ(PIPESRC(pipe));
7634         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7635         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7636
7637         val = I915_READ(DSPSTRIDE(pipe));
7638         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7639
7640         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7641                                             plane_config->tiled);
7642
7643         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7644                                         aligned_height);
7645
7646         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7647                       pipe, plane, crtc->base.primary->fb->width,
7648                       crtc->base.primary->fb->height,
7649                       crtc->base.primary->fb->bits_per_pixel, base,
7650                       crtc->base.primary->fb->pitches[0],
7651                       plane_config->size);
7652 }
7653
7654 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7655                                      struct intel_crtc_config *pipe_config)
7656 {
7657         struct drm_device *dev = crtc->base.dev;
7658         struct drm_i915_private *dev_priv = dev->dev_private;
7659         uint32_t tmp;
7660
7661         if (!intel_display_power_is_enabled(dev_priv,
7662                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7663                 return false;
7664
7665         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7666         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7667
7668         tmp = I915_READ(PIPECONF(crtc->pipe));
7669         if (!(tmp & PIPECONF_ENABLE))
7670                 return false;
7671
7672         switch (tmp & PIPECONF_BPC_MASK) {
7673         case PIPECONF_6BPC:
7674                 pipe_config->pipe_bpp = 18;
7675                 break;
7676         case PIPECONF_8BPC:
7677                 pipe_config->pipe_bpp = 24;
7678                 break;
7679         case PIPECONF_10BPC:
7680                 pipe_config->pipe_bpp = 30;
7681                 break;
7682         case PIPECONF_12BPC:
7683                 pipe_config->pipe_bpp = 36;
7684                 break;
7685         default:
7686                 break;
7687         }
7688
7689         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7690                 pipe_config->limited_color_range = true;
7691
7692         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7693                 struct intel_shared_dpll *pll;
7694
7695                 pipe_config->has_pch_encoder = true;
7696
7697                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7698                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7699                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7700
7701                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7702
7703                 if (HAS_PCH_IBX(dev_priv->dev)) {
7704                         pipe_config->shared_dpll =
7705                                 (enum intel_dpll_id) crtc->pipe;
7706                 } else {
7707                         tmp = I915_READ(PCH_DPLL_SEL);
7708                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7709                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7710                         else
7711                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7712                 }
7713
7714                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7715
7716                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7717                                            &pipe_config->dpll_hw_state));
7718
7719                 tmp = pipe_config->dpll_hw_state.dpll;
7720                 pipe_config->pixel_multiplier =
7721                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7722                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7723
7724                 ironlake_pch_clock_get(crtc, pipe_config);
7725         } else {
7726                 pipe_config->pixel_multiplier = 1;
7727         }
7728
7729         intel_get_pipe_timings(crtc, pipe_config);
7730
7731         ironlake_get_pfit_config(crtc, pipe_config);
7732
7733         return true;
7734 }
7735
7736 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7737 {
7738         struct drm_device *dev = dev_priv->dev;
7739         struct intel_crtc *crtc;
7740
7741         for_each_intel_crtc(dev, crtc)
7742                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7743                      pipe_name(crtc->pipe));
7744
7745         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7746         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7747         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7748         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7749         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7750         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7751              "CPU PWM1 enabled\n");
7752         if (IS_HASWELL(dev))
7753                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7754                      "CPU PWM2 enabled\n");
7755         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7756              "PCH PWM1 enabled\n");
7757         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7758              "Utility pin enabled\n");
7759         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7760
7761         /*
7762          * In theory we can still leave IRQs enabled, as long as only the HPD
7763          * interrupts remain enabled. We used to check for that, but since it's
7764          * gen-specific and since we only disable LCPLL after we fully disable
7765          * the interrupts, the check below should be enough.
7766          */
7767         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7768 }
7769
7770 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7771 {
7772         struct drm_device *dev = dev_priv->dev;
7773
7774         if (IS_HASWELL(dev))
7775                 return I915_READ(D_COMP_HSW);
7776         else
7777                 return I915_READ(D_COMP_BDW);
7778 }
7779
7780 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7781 {
7782         struct drm_device *dev = dev_priv->dev;
7783
7784         if (IS_HASWELL(dev)) {
7785                 mutex_lock(&dev_priv->rps.hw_lock);
7786                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7787                                             val))
7788                         DRM_ERROR("Failed to write to D_COMP\n");
7789                 mutex_unlock(&dev_priv->rps.hw_lock);
7790         } else {
7791                 I915_WRITE(D_COMP_BDW, val);
7792                 POSTING_READ(D_COMP_BDW);
7793         }
7794 }
7795
7796 /*
7797  * This function implements pieces of two sequences from BSpec:
7798  * - Sequence for display software to disable LCPLL
7799  * - Sequence for display software to allow package C8+
7800  * The steps implemented here are just the steps that actually touch the LCPLL
7801  * register. Callers should take care of disabling all the display engine
7802  * functions, doing the mode unset, fixing interrupts, etc.
7803  */
7804 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7805                               bool switch_to_fclk, bool allow_power_down)
7806 {
7807         uint32_t val;
7808
7809         assert_can_disable_lcpll(dev_priv);
7810
7811         val = I915_READ(LCPLL_CTL);
7812
7813         if (switch_to_fclk) {
7814                 val |= LCPLL_CD_SOURCE_FCLK;
7815                 I915_WRITE(LCPLL_CTL, val);
7816
7817                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7818                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7819                         DRM_ERROR("Switching to FCLK failed\n");
7820
7821                 val = I915_READ(LCPLL_CTL);
7822         }
7823
7824         val |= LCPLL_PLL_DISABLE;
7825         I915_WRITE(LCPLL_CTL, val);
7826         POSTING_READ(LCPLL_CTL);
7827
7828         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7829                 DRM_ERROR("LCPLL still locked\n");
7830
7831         val = hsw_read_dcomp(dev_priv);
7832         val |= D_COMP_COMP_DISABLE;
7833         hsw_write_dcomp(dev_priv, val);
7834         ndelay(100);
7835
7836         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7837                      1))
7838                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7839
7840         if (allow_power_down) {
7841                 val = I915_READ(LCPLL_CTL);
7842                 val |= LCPLL_POWER_DOWN_ALLOW;
7843                 I915_WRITE(LCPLL_CTL, val);
7844                 POSTING_READ(LCPLL_CTL);
7845         }
7846 }
7847
7848 /*
7849  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7850  * source.
7851  */
7852 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7853 {
7854         uint32_t val;
7855
7856         val = I915_READ(LCPLL_CTL);
7857
7858         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7859                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7860                 return;
7861
7862         /*
7863          * Make sure we're not on PC8 state before disabling PC8, otherwise
7864          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7865          *
7866          * The other problem is that hsw_restore_lcpll() is called as part of
7867          * the runtime PM resume sequence, so we can't just call
7868          * gen6_gt_force_wake_get() because that function calls
7869          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7870          * while we are on the resume sequence. So to solve this problem we have
7871          * to call special forcewake code that doesn't touch runtime PM and
7872          * doesn't enable the forcewake delayed work.
7873          */
7874         spin_lock_irq(&dev_priv->uncore.lock);
7875         if (dev_priv->uncore.forcewake_count++ == 0)
7876                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7877         spin_unlock_irq(&dev_priv->uncore.lock);
7878
7879         if (val & LCPLL_POWER_DOWN_ALLOW) {
7880                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7881                 I915_WRITE(LCPLL_CTL, val);
7882                 POSTING_READ(LCPLL_CTL);
7883         }
7884
7885         val = hsw_read_dcomp(dev_priv);
7886         val |= D_COMP_COMP_FORCE;
7887         val &= ~D_COMP_COMP_DISABLE;
7888         hsw_write_dcomp(dev_priv, val);
7889
7890         val = I915_READ(LCPLL_CTL);
7891         val &= ~LCPLL_PLL_DISABLE;
7892         I915_WRITE(LCPLL_CTL, val);
7893
7894         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7895                 DRM_ERROR("LCPLL not locked yet\n");
7896
7897         if (val & LCPLL_CD_SOURCE_FCLK) {
7898                 val = I915_READ(LCPLL_CTL);
7899                 val &= ~LCPLL_CD_SOURCE_FCLK;
7900                 I915_WRITE(LCPLL_CTL, val);
7901
7902                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7903                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7904                         DRM_ERROR("Switching back to LCPLL failed\n");
7905         }
7906
7907         /* See the big comment above. */
7908         spin_lock_irq(&dev_priv->uncore.lock);
7909         if (--dev_priv->uncore.forcewake_count == 0)
7910                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7911         spin_unlock_irq(&dev_priv->uncore.lock);
7912 }
7913
7914 /*
7915  * Package states C8 and deeper are really deep PC states that can only be
7916  * reached when all the devices on the system allow it, so even if the graphics
7917  * device allows PC8+, it doesn't mean the system will actually get to these
7918  * states. Our driver only allows PC8+ when going into runtime PM.
7919  *
7920  * The requirements for PC8+ are that all the outputs are disabled, the power
7921  * well is disabled and most interrupts are disabled, and these are also
7922  * requirements for runtime PM. When these conditions are met, we manually do
7923  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7924  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7925  * hang the machine.
7926  *
7927  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7928  * the state of some registers, so when we come back from PC8+ we need to
7929  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7930  * need to take care of the registers kept by RC6. Notice that this happens even
7931  * if we don't put the device in PCI D3 state (which is what currently happens
7932  * because of the runtime PM support).
7933  *
7934  * For more, read "Display Sequences for Package C8" on the hardware
7935  * documentation.
7936  */
7937 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7938 {
7939         struct drm_device *dev = dev_priv->dev;
7940         uint32_t val;
7941
7942         DRM_DEBUG_KMS("Enabling package C8+\n");
7943
7944         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7945                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7946                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7947                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7948         }
7949
7950         lpt_disable_clkout_dp(dev);
7951         hsw_disable_lcpll(dev_priv, true, true);
7952 }
7953
7954 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7955 {
7956         struct drm_device *dev = dev_priv->dev;
7957         uint32_t val;
7958
7959         DRM_DEBUG_KMS("Disabling package C8+\n");
7960
7961         hsw_restore_lcpll(dev_priv);
7962         lpt_init_pch_refclk(dev);
7963
7964         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7965                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7966                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7967                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7968         }
7969
7970         intel_prepare_ddi(dev);
7971 }
7972
7973 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7974 {
7975         if (!intel_ddi_pll_select(crtc))
7976                 return -EINVAL;
7977
7978         crtc->lowfreq_avail = false;
7979
7980         return 0;
7981 }
7982
7983 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7984                                 enum port port,
7985                                 struct intel_crtc_config *pipe_config)
7986 {
7987         u32 temp, dpll_ctl1;
7988
7989         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
7990         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
7991
7992         switch (pipe_config->ddi_pll_sel) {
7993         case SKL_DPLL0:
7994                 /*
7995                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
7996                  * of the shared DPLL framework and thus needs to be read out
7997                  * separately
7998                  */
7999                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8000                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8001                 break;
8002         case SKL_DPLL1:
8003                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8004                 break;
8005         case SKL_DPLL2:
8006                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8007                 break;
8008         case SKL_DPLL3:
8009                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8010                 break;
8011         }
8012 }
8013
8014 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8015                                 enum port port,
8016                                 struct intel_crtc_config *pipe_config)
8017 {
8018         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8019
8020         switch (pipe_config->ddi_pll_sel) {
8021         case PORT_CLK_SEL_WRPLL1:
8022                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8023                 break;
8024         case PORT_CLK_SEL_WRPLL2:
8025                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8026                 break;
8027         }
8028 }
8029
8030 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8031                                        struct intel_crtc_config *pipe_config)
8032 {
8033         struct drm_device *dev = crtc->base.dev;
8034         struct drm_i915_private *dev_priv = dev->dev_private;
8035         struct intel_shared_dpll *pll;
8036         enum port port;
8037         uint32_t tmp;
8038
8039         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8040
8041         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8042
8043         if (IS_SKYLAKE(dev))
8044                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8045         else
8046                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8047
8048         if (pipe_config->shared_dpll >= 0) {
8049                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8050
8051                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8052                                            &pipe_config->dpll_hw_state));
8053         }
8054
8055         /*
8056          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8057          * DDI E. So just check whether this pipe is wired to DDI E and whether
8058          * the PCH transcoder is on.
8059          */
8060         if (INTEL_INFO(dev)->gen < 9 &&
8061             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8062                 pipe_config->has_pch_encoder = true;
8063
8064                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8065                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8066                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8067
8068                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8069         }
8070 }
8071
8072 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8073                                     struct intel_crtc_config *pipe_config)
8074 {
8075         struct drm_device *dev = crtc->base.dev;
8076         struct drm_i915_private *dev_priv = dev->dev_private;
8077         enum intel_display_power_domain pfit_domain;
8078         uint32_t tmp;
8079
8080         if (!intel_display_power_is_enabled(dev_priv,
8081                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8082                 return false;
8083
8084         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8085         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8086
8087         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8088         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8089                 enum pipe trans_edp_pipe;
8090                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8091                 default:
8092                         WARN(1, "unknown pipe linked to edp transcoder\n");
8093                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8094                 case TRANS_DDI_EDP_INPUT_A_ON:
8095                         trans_edp_pipe = PIPE_A;
8096                         break;
8097                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8098                         trans_edp_pipe = PIPE_B;
8099                         break;
8100                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8101                         trans_edp_pipe = PIPE_C;
8102                         break;
8103                 }
8104
8105                 if (trans_edp_pipe == crtc->pipe)
8106                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8107         }
8108
8109         if (!intel_display_power_is_enabled(dev_priv,
8110                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8111                 return false;
8112
8113         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8114         if (!(tmp & PIPECONF_ENABLE))
8115                 return false;
8116
8117         haswell_get_ddi_port_state(crtc, pipe_config);
8118
8119         intel_get_pipe_timings(crtc, pipe_config);
8120
8121         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8122         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8123                 if (IS_SKYLAKE(dev))
8124                         skylake_get_pfit_config(crtc, pipe_config);
8125                 else
8126                         ironlake_get_pfit_config(crtc, pipe_config);
8127         }
8128
8129         if (IS_HASWELL(dev))
8130                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8131                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8132
8133         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8134                 pipe_config->pixel_multiplier =
8135                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8136         } else {
8137                 pipe_config->pixel_multiplier = 1;
8138         }
8139
8140         return true;
8141 }
8142
8143 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8144 {
8145         struct drm_device *dev = crtc->dev;
8146         struct drm_i915_private *dev_priv = dev->dev_private;
8147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8148         uint32_t cntl = 0, size = 0;
8149
8150         if (base) {
8151                 unsigned int width = intel_crtc->cursor_width;
8152                 unsigned int height = intel_crtc->cursor_height;
8153                 unsigned int stride = roundup_pow_of_two(width) * 4;
8154
8155                 switch (stride) {
8156                 default:
8157                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8158                                   width, stride);
8159                         stride = 256;
8160                         /* fallthrough */
8161                 case 256:
8162                 case 512:
8163                 case 1024:
8164                 case 2048:
8165                         break;
8166                 }
8167
8168                 cntl |= CURSOR_ENABLE |
8169                         CURSOR_GAMMA_ENABLE |
8170                         CURSOR_FORMAT_ARGB |
8171                         CURSOR_STRIDE(stride);
8172
8173                 size = (height << 12) | width;
8174         }
8175
8176         if (intel_crtc->cursor_cntl != 0 &&
8177             (intel_crtc->cursor_base != base ||
8178              intel_crtc->cursor_size != size ||
8179              intel_crtc->cursor_cntl != cntl)) {
8180                 /* On these chipsets we can only modify the base/size/stride
8181                  * whilst the cursor is disabled.
8182                  */
8183                 I915_WRITE(_CURACNTR, 0);
8184                 POSTING_READ(_CURACNTR);
8185                 intel_crtc->cursor_cntl = 0;
8186         }
8187
8188         if (intel_crtc->cursor_base != base) {
8189                 I915_WRITE(_CURABASE, base);
8190                 intel_crtc->cursor_base = base;
8191         }
8192
8193         if (intel_crtc->cursor_size != size) {
8194                 I915_WRITE(CURSIZE, size);
8195                 intel_crtc->cursor_size = size;
8196         }
8197
8198         if (intel_crtc->cursor_cntl != cntl) {
8199                 I915_WRITE(_CURACNTR, cntl);
8200                 POSTING_READ(_CURACNTR);
8201                 intel_crtc->cursor_cntl = cntl;
8202         }
8203 }
8204
8205 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8206 {
8207         struct drm_device *dev = crtc->dev;
8208         struct drm_i915_private *dev_priv = dev->dev_private;
8209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8210         int pipe = intel_crtc->pipe;
8211         uint32_t cntl;
8212
8213         cntl = 0;
8214         if (base) {
8215                 cntl = MCURSOR_GAMMA_ENABLE;
8216                 switch (intel_crtc->cursor_width) {
8217                         case 64:
8218                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8219                                 break;
8220                         case 128:
8221                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8222                                 break;
8223                         case 256:
8224                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8225                                 break;
8226                         default:
8227                                 WARN_ON(1);
8228                                 return;
8229                 }
8230                 cntl |= pipe << 28; /* Connect to correct pipe */
8231
8232                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8233                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8234         }
8235
8236         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8237                 cntl |= CURSOR_ROTATE_180;
8238
8239         if (intel_crtc->cursor_cntl != cntl) {
8240                 I915_WRITE(CURCNTR(pipe), cntl);
8241                 POSTING_READ(CURCNTR(pipe));
8242                 intel_crtc->cursor_cntl = cntl;
8243         }
8244
8245         /* and commit changes on next vblank */
8246         I915_WRITE(CURBASE(pipe), base);
8247         POSTING_READ(CURBASE(pipe));
8248
8249         intel_crtc->cursor_base = base;
8250 }
8251
8252 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8253 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8254                                      bool on)
8255 {
8256         struct drm_device *dev = crtc->dev;
8257         struct drm_i915_private *dev_priv = dev->dev_private;
8258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8259         int pipe = intel_crtc->pipe;
8260         int x = crtc->cursor_x;
8261         int y = crtc->cursor_y;
8262         u32 base = 0, pos = 0;
8263
8264         if (on)
8265                 base = intel_crtc->cursor_addr;
8266
8267         if (x >= intel_crtc->config.pipe_src_w)
8268                 base = 0;
8269
8270         if (y >= intel_crtc->config.pipe_src_h)
8271                 base = 0;
8272
8273         if (x < 0) {
8274                 if (x + intel_crtc->cursor_width <= 0)
8275                         base = 0;
8276
8277                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8278                 x = -x;
8279         }
8280         pos |= x << CURSOR_X_SHIFT;
8281
8282         if (y < 0) {
8283                 if (y + intel_crtc->cursor_height <= 0)
8284                         base = 0;
8285
8286                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8287                 y = -y;
8288         }
8289         pos |= y << CURSOR_Y_SHIFT;
8290
8291         if (base == 0 && intel_crtc->cursor_base == 0)
8292                 return;
8293
8294         I915_WRITE(CURPOS(pipe), pos);
8295
8296         /* ILK+ do this automagically */
8297         if (HAS_GMCH_DISPLAY(dev) &&
8298                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8299                 base += (intel_crtc->cursor_height *
8300                         intel_crtc->cursor_width - 1) * 4;
8301         }
8302
8303         if (IS_845G(dev) || IS_I865G(dev))
8304                 i845_update_cursor(crtc, base);
8305         else
8306                 i9xx_update_cursor(crtc, base);
8307 }
8308
8309 static bool cursor_size_ok(struct drm_device *dev,
8310                            uint32_t width, uint32_t height)
8311 {
8312         if (width == 0 || height == 0)
8313                 return false;
8314
8315         /*
8316          * 845g/865g are special in that they are only limited by
8317          * the width of their cursors, the height is arbitrary up to
8318          * the precision of the register. Everything else requires
8319          * square cursors, limited to a few power-of-two sizes.
8320          */
8321         if (IS_845G(dev) || IS_I865G(dev)) {
8322                 if ((width & 63) != 0)
8323                         return false;
8324
8325                 if (width > (IS_845G(dev) ? 64 : 512))
8326                         return false;
8327
8328                 if (height > 1023)
8329                         return false;
8330         } else {
8331                 switch (width | height) {
8332                 case 256:
8333                 case 128:
8334                         if (IS_GEN2(dev))
8335                                 return false;
8336                 case 64:
8337                         break;
8338                 default:
8339                         return false;
8340                 }
8341         }
8342
8343         return true;
8344 }
8345
8346 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8347                                  u16 *blue, uint32_t start, uint32_t size)
8348 {
8349         int end = (start + size > 256) ? 256 : start + size, i;
8350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8351
8352         for (i = start; i < end; i++) {
8353                 intel_crtc->lut_r[i] = red[i] >> 8;
8354                 intel_crtc->lut_g[i] = green[i] >> 8;
8355                 intel_crtc->lut_b[i] = blue[i] >> 8;
8356         }
8357
8358         intel_crtc_load_lut(crtc);
8359 }
8360
8361 /* VESA 640x480x72Hz mode to set on the pipe */
8362 static struct drm_display_mode load_detect_mode = {
8363         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8364                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8365 };
8366
8367 struct drm_framebuffer *
8368 __intel_framebuffer_create(struct drm_device *dev,
8369                            struct drm_mode_fb_cmd2 *mode_cmd,
8370                            struct drm_i915_gem_object *obj)
8371 {
8372         struct intel_framebuffer *intel_fb;
8373         int ret;
8374
8375         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8376         if (!intel_fb) {
8377                 drm_gem_object_unreference(&obj->base);
8378                 return ERR_PTR(-ENOMEM);
8379         }
8380
8381         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8382         if (ret)
8383                 goto err;
8384
8385         return &intel_fb->base;
8386 err:
8387         drm_gem_object_unreference(&obj->base);
8388         kfree(intel_fb);
8389
8390         return ERR_PTR(ret);
8391 }
8392
8393 static struct drm_framebuffer *
8394 intel_framebuffer_create(struct drm_device *dev,
8395                          struct drm_mode_fb_cmd2 *mode_cmd,
8396                          struct drm_i915_gem_object *obj)
8397 {
8398         struct drm_framebuffer *fb;
8399         int ret;
8400
8401         ret = i915_mutex_lock_interruptible(dev);
8402         if (ret)
8403                 return ERR_PTR(ret);
8404         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8405         mutex_unlock(&dev->struct_mutex);
8406
8407         return fb;
8408 }
8409
8410 static u32
8411 intel_framebuffer_pitch_for_width(int width, int bpp)
8412 {
8413         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8414         return ALIGN(pitch, 64);
8415 }
8416
8417 static u32
8418 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8419 {
8420         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8421         return PAGE_ALIGN(pitch * mode->vdisplay);
8422 }
8423
8424 static struct drm_framebuffer *
8425 intel_framebuffer_create_for_mode(struct drm_device *dev,
8426                                   struct drm_display_mode *mode,
8427                                   int depth, int bpp)
8428 {
8429         struct drm_i915_gem_object *obj;
8430         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8431
8432         obj = i915_gem_alloc_object(dev,
8433                                     intel_framebuffer_size_for_mode(mode, bpp));
8434         if (obj == NULL)
8435                 return ERR_PTR(-ENOMEM);
8436
8437         mode_cmd.width = mode->hdisplay;
8438         mode_cmd.height = mode->vdisplay;
8439         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8440                                                                 bpp);
8441         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8442
8443         return intel_framebuffer_create(dev, &mode_cmd, obj);
8444 }
8445
8446 static struct drm_framebuffer *
8447 mode_fits_in_fbdev(struct drm_device *dev,
8448                    struct drm_display_mode *mode)
8449 {
8450 #ifdef CONFIG_DRM_I915_FBDEV
8451         struct drm_i915_private *dev_priv = dev->dev_private;
8452         struct drm_i915_gem_object *obj;
8453         struct drm_framebuffer *fb;
8454
8455         if (!dev_priv->fbdev)
8456                 return NULL;
8457
8458         if (!dev_priv->fbdev->fb)
8459                 return NULL;
8460
8461         obj = dev_priv->fbdev->fb->obj;
8462         BUG_ON(!obj);
8463
8464         fb = &dev_priv->fbdev->fb->base;
8465         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8466                                                                fb->bits_per_pixel))
8467                 return NULL;
8468
8469         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8470                 return NULL;
8471
8472         return fb;
8473 #else
8474         return NULL;
8475 #endif
8476 }
8477
8478 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8479                                 struct drm_display_mode *mode,
8480                                 struct intel_load_detect_pipe *old,
8481                                 struct drm_modeset_acquire_ctx *ctx)
8482 {
8483         struct intel_crtc *intel_crtc;
8484         struct intel_encoder *intel_encoder =
8485                 intel_attached_encoder(connector);
8486         struct drm_crtc *possible_crtc;
8487         struct drm_encoder *encoder = &intel_encoder->base;
8488         struct drm_crtc *crtc = NULL;
8489         struct drm_device *dev = encoder->dev;
8490         struct drm_framebuffer *fb;
8491         struct drm_mode_config *config = &dev->mode_config;
8492         int ret, i = -1;
8493
8494         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8495                       connector->base.id, connector->name,
8496                       encoder->base.id, encoder->name);
8497
8498 retry:
8499         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8500         if (ret)
8501                 goto fail_unlock;
8502
8503         /*
8504          * Algorithm gets a little messy:
8505          *
8506          *   - if the connector already has an assigned crtc, use it (but make
8507          *     sure it's on first)
8508          *
8509          *   - try to find the first unused crtc that can drive this connector,
8510          *     and use that if we find one
8511          */
8512
8513         /* See if we already have a CRTC for this connector */
8514         if (encoder->crtc) {
8515                 crtc = encoder->crtc;
8516
8517                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8518                 if (ret)
8519                         goto fail_unlock;
8520                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8521                 if (ret)
8522                         goto fail_unlock;
8523
8524                 old->dpms_mode = connector->dpms;
8525                 old->load_detect_temp = false;
8526
8527                 /* Make sure the crtc and connector are running */
8528                 if (connector->dpms != DRM_MODE_DPMS_ON)
8529                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8530
8531                 return true;
8532         }
8533
8534         /* Find an unused one (if possible) */
8535         for_each_crtc(dev, possible_crtc) {
8536                 i++;
8537                 if (!(encoder->possible_crtcs & (1 << i)))
8538                         continue;
8539                 if (possible_crtc->enabled)
8540                         continue;
8541                 /* This can occur when applying the pipe A quirk on resume. */
8542                 if (to_intel_crtc(possible_crtc)->new_enabled)
8543                         continue;
8544
8545                 crtc = possible_crtc;
8546                 break;
8547         }
8548
8549         /*
8550          * If we didn't find an unused CRTC, don't use any.
8551          */
8552         if (!crtc) {
8553                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8554                 goto fail_unlock;
8555         }
8556
8557         ret = drm_modeset_lock(&crtc->mutex, ctx);
8558         if (ret)
8559                 goto fail_unlock;
8560         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8561         if (ret)
8562                 goto fail_unlock;
8563         intel_encoder->new_crtc = to_intel_crtc(crtc);
8564         to_intel_connector(connector)->new_encoder = intel_encoder;
8565
8566         intel_crtc = to_intel_crtc(crtc);
8567         intel_crtc->new_enabled = true;
8568         intel_crtc->new_config = &intel_crtc->config;
8569         old->dpms_mode = connector->dpms;
8570         old->load_detect_temp = true;
8571         old->release_fb = NULL;
8572
8573         if (!mode)
8574                 mode = &load_detect_mode;
8575
8576         /* We need a framebuffer large enough to accommodate all accesses
8577          * that the plane may generate whilst we perform load detection.
8578          * We can not rely on the fbcon either being present (we get called
8579          * during its initialisation to detect all boot displays, or it may
8580          * not even exist) or that it is large enough to satisfy the
8581          * requested mode.
8582          */
8583         fb = mode_fits_in_fbdev(dev, mode);
8584         if (fb == NULL) {
8585                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8586                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8587                 old->release_fb = fb;
8588         } else
8589                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8590         if (IS_ERR(fb)) {
8591                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8592                 goto fail;
8593         }
8594
8595         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8596                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8597                 if (old->release_fb)
8598                         old->release_fb->funcs->destroy(old->release_fb);
8599                 goto fail;
8600         }
8601
8602         /* let the connector get through one full cycle before testing */
8603         intel_wait_for_vblank(dev, intel_crtc->pipe);
8604         return true;
8605
8606  fail:
8607         intel_crtc->new_enabled = crtc->enabled;
8608         if (intel_crtc->new_enabled)
8609                 intel_crtc->new_config = &intel_crtc->config;
8610         else
8611                 intel_crtc->new_config = NULL;
8612 fail_unlock:
8613         if (ret == -EDEADLK) {
8614                 drm_modeset_backoff(ctx);
8615                 goto retry;
8616         }
8617
8618         return false;
8619 }
8620
8621 void intel_release_load_detect_pipe(struct drm_connector *connector,
8622                                     struct intel_load_detect_pipe *old)
8623 {
8624         struct intel_encoder *intel_encoder =
8625                 intel_attached_encoder(connector);
8626         struct drm_encoder *encoder = &intel_encoder->base;
8627         struct drm_crtc *crtc = encoder->crtc;
8628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629
8630         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8631                       connector->base.id, connector->name,
8632                       encoder->base.id, encoder->name);
8633
8634         if (old->load_detect_temp) {
8635                 to_intel_connector(connector)->new_encoder = NULL;
8636                 intel_encoder->new_crtc = NULL;
8637                 intel_crtc->new_enabled = false;
8638                 intel_crtc->new_config = NULL;
8639                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8640
8641                 if (old->release_fb) {
8642                         drm_framebuffer_unregister_private(old->release_fb);
8643                         drm_framebuffer_unreference(old->release_fb);
8644                 }
8645
8646                 return;
8647         }
8648
8649         /* Switch crtc and encoder back off if necessary */
8650         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8651                 connector->funcs->dpms(connector, old->dpms_mode);
8652 }
8653
8654 static int i9xx_pll_refclk(struct drm_device *dev,
8655                            const struct intel_crtc_config *pipe_config)
8656 {
8657         struct drm_i915_private *dev_priv = dev->dev_private;
8658         u32 dpll = pipe_config->dpll_hw_state.dpll;
8659
8660         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8661                 return dev_priv->vbt.lvds_ssc_freq;
8662         else if (HAS_PCH_SPLIT(dev))
8663                 return 120000;
8664         else if (!IS_GEN2(dev))
8665                 return 96000;
8666         else
8667                 return 48000;
8668 }
8669
8670 /* Returns the clock of the currently programmed mode of the given pipe. */
8671 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8672                                 struct intel_crtc_config *pipe_config)
8673 {
8674         struct drm_device *dev = crtc->base.dev;
8675         struct drm_i915_private *dev_priv = dev->dev_private;
8676         int pipe = pipe_config->cpu_transcoder;
8677         u32 dpll = pipe_config->dpll_hw_state.dpll;
8678         u32 fp;
8679         intel_clock_t clock;
8680         int refclk = i9xx_pll_refclk(dev, pipe_config);
8681
8682         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8683                 fp = pipe_config->dpll_hw_state.fp0;
8684         else
8685                 fp = pipe_config->dpll_hw_state.fp1;
8686
8687         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8688         if (IS_PINEVIEW(dev)) {
8689                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8690                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8691         } else {
8692                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8693                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8694         }
8695
8696         if (!IS_GEN2(dev)) {
8697                 if (IS_PINEVIEW(dev))
8698                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8699                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8700                 else
8701                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8702                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8703
8704                 switch (dpll & DPLL_MODE_MASK) {
8705                 case DPLLB_MODE_DAC_SERIAL:
8706                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8707                                 5 : 10;
8708                         break;
8709                 case DPLLB_MODE_LVDS:
8710                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8711                                 7 : 14;
8712                         break;
8713                 default:
8714                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8715                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8716                         return;
8717                 }
8718
8719                 if (IS_PINEVIEW(dev))
8720                         pineview_clock(refclk, &clock);
8721                 else
8722                         i9xx_clock(refclk, &clock);
8723         } else {
8724                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8725                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8726
8727                 if (is_lvds) {
8728                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8729                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8730
8731                         if (lvds & LVDS_CLKB_POWER_UP)
8732                                 clock.p2 = 7;
8733                         else
8734                                 clock.p2 = 14;
8735                 } else {
8736                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8737                                 clock.p1 = 2;
8738                         else {
8739                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8740                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8741                         }
8742                         if (dpll & PLL_P2_DIVIDE_BY_4)
8743                                 clock.p2 = 4;
8744                         else
8745                                 clock.p2 = 2;
8746                 }
8747
8748                 i9xx_clock(refclk, &clock);
8749         }
8750
8751         /*
8752          * This value includes pixel_multiplier. We will use
8753          * port_clock to compute adjusted_mode.crtc_clock in the
8754          * encoder's get_config() function.
8755          */
8756         pipe_config->port_clock = clock.dot;
8757 }
8758
8759 int intel_dotclock_calculate(int link_freq,
8760                              const struct intel_link_m_n *m_n)
8761 {
8762         /*
8763          * The calculation for the data clock is:
8764          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8765          * But we want to avoid losing precison if possible, so:
8766          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8767          *
8768          * and the link clock is simpler:
8769          * link_clock = (m * link_clock) / n
8770          */
8771
8772         if (!m_n->link_n)
8773                 return 0;
8774
8775         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8776 }
8777
8778 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8779                                    struct intel_crtc_config *pipe_config)
8780 {
8781         struct drm_device *dev = crtc->base.dev;
8782
8783         /* read out port_clock from the DPLL */
8784         i9xx_crtc_clock_get(crtc, pipe_config);
8785
8786         /*
8787          * This value does not include pixel_multiplier.
8788          * We will check that port_clock and adjusted_mode.crtc_clock
8789          * agree once we know their relationship in the encoder's
8790          * get_config() function.
8791          */
8792         pipe_config->adjusted_mode.crtc_clock =
8793                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8794                                          &pipe_config->fdi_m_n);
8795 }
8796
8797 /** Returns the currently programmed mode of the given pipe. */
8798 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8799                                              struct drm_crtc *crtc)
8800 {
8801         struct drm_i915_private *dev_priv = dev->dev_private;
8802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8803         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8804         struct drm_display_mode *mode;
8805         struct intel_crtc_config pipe_config;
8806         int htot = I915_READ(HTOTAL(cpu_transcoder));
8807         int hsync = I915_READ(HSYNC(cpu_transcoder));
8808         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8809         int vsync = I915_READ(VSYNC(cpu_transcoder));
8810         enum pipe pipe = intel_crtc->pipe;
8811
8812         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8813         if (!mode)
8814                 return NULL;
8815
8816         /*
8817          * Construct a pipe_config sufficient for getting the clock info
8818          * back out of crtc_clock_get.
8819          *
8820          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8821          * to use a real value here instead.
8822          */
8823         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8824         pipe_config.pixel_multiplier = 1;
8825         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8826         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8827         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8828         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8829
8830         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8831         mode->hdisplay = (htot & 0xffff) + 1;
8832         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8833         mode->hsync_start = (hsync & 0xffff) + 1;
8834         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8835         mode->vdisplay = (vtot & 0xffff) + 1;
8836         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8837         mode->vsync_start = (vsync & 0xffff) + 1;
8838         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8839
8840         drm_mode_set_name(mode);
8841
8842         return mode;
8843 }
8844
8845 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8846 {
8847         struct drm_device *dev = crtc->dev;
8848         struct drm_i915_private *dev_priv = dev->dev_private;
8849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8850
8851         if (!HAS_GMCH_DISPLAY(dev))
8852                 return;
8853
8854         if (!dev_priv->lvds_downclock_avail)
8855                 return;
8856
8857         /*
8858          * Since this is called by a timer, we should never get here in
8859          * the manual case.
8860          */
8861         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8862                 int pipe = intel_crtc->pipe;
8863                 int dpll_reg = DPLL(pipe);
8864                 int dpll;
8865
8866                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8867
8868                 assert_panel_unlocked(dev_priv, pipe);
8869
8870                 dpll = I915_READ(dpll_reg);
8871                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8872                 I915_WRITE(dpll_reg, dpll);
8873                 intel_wait_for_vblank(dev, pipe);
8874                 dpll = I915_READ(dpll_reg);
8875                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8876                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8877         }
8878
8879 }
8880
8881 void intel_mark_busy(struct drm_device *dev)
8882 {
8883         struct drm_i915_private *dev_priv = dev->dev_private;
8884
8885         if (dev_priv->mm.busy)
8886                 return;
8887
8888         intel_runtime_pm_get(dev_priv);
8889         i915_update_gfx_val(dev_priv);
8890         dev_priv->mm.busy = true;
8891 }
8892
8893 void intel_mark_idle(struct drm_device *dev)
8894 {
8895         struct drm_i915_private *dev_priv = dev->dev_private;
8896         struct drm_crtc *crtc;
8897
8898         if (!dev_priv->mm.busy)
8899                 return;
8900
8901         dev_priv->mm.busy = false;
8902
8903         if (!i915.powersave)
8904                 goto out;
8905
8906         for_each_crtc(dev, crtc) {
8907                 if (!crtc->primary->fb)
8908                         continue;
8909
8910                 intel_decrease_pllclock(crtc);
8911         }
8912
8913         if (INTEL_INFO(dev)->gen >= 6)
8914                 gen6_rps_idle(dev->dev_private);
8915
8916 out:
8917         intel_runtime_pm_put(dev_priv);
8918 }
8919
8920 static void intel_crtc_destroy(struct drm_crtc *crtc)
8921 {
8922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8923         struct drm_device *dev = crtc->dev;
8924         struct intel_unpin_work *work;
8925
8926         spin_lock_irq(&dev->event_lock);
8927         work = intel_crtc->unpin_work;
8928         intel_crtc->unpin_work = NULL;
8929         spin_unlock_irq(&dev->event_lock);
8930
8931         if (work) {
8932                 cancel_work_sync(&work->work);
8933                 kfree(work);
8934         }
8935
8936         drm_crtc_cleanup(crtc);
8937
8938         kfree(intel_crtc);
8939 }
8940
8941 static void intel_unpin_work_fn(struct work_struct *__work)
8942 {
8943         struct intel_unpin_work *work =
8944                 container_of(__work, struct intel_unpin_work, work);
8945         struct drm_device *dev = work->crtc->dev;
8946         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8947
8948         mutex_lock(&dev->struct_mutex);
8949         intel_unpin_fb_obj(work->old_fb_obj);
8950         drm_gem_object_unreference(&work->pending_flip_obj->base);
8951         drm_gem_object_unreference(&work->old_fb_obj->base);
8952
8953         intel_update_fbc(dev);
8954
8955         if (work->flip_queued_req)
8956                 i915_gem_request_assign(&work->flip_queued_req, NULL);
8957         mutex_unlock(&dev->struct_mutex);
8958
8959         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8960
8961         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8962         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8963
8964         kfree(work);
8965 }
8966
8967 static void do_intel_finish_page_flip(struct drm_device *dev,
8968                                       struct drm_crtc *crtc)
8969 {
8970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8971         struct intel_unpin_work *work;
8972         unsigned long flags;
8973
8974         /* Ignore early vblank irqs */
8975         if (intel_crtc == NULL)
8976                 return;
8977
8978         /*
8979          * This is called both by irq handlers and the reset code (to complete
8980          * lost pageflips) so needs the full irqsave spinlocks.
8981          */
8982         spin_lock_irqsave(&dev->event_lock, flags);
8983         work = intel_crtc->unpin_work;
8984
8985         /* Ensure we don't miss a work->pending update ... */
8986         smp_rmb();
8987
8988         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8989                 spin_unlock_irqrestore(&dev->event_lock, flags);
8990                 return;
8991         }
8992
8993         page_flip_completed(intel_crtc);
8994
8995         spin_unlock_irqrestore(&dev->event_lock, flags);
8996 }
8997
8998 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8999 {
9000         struct drm_i915_private *dev_priv = dev->dev_private;
9001         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9002
9003         do_intel_finish_page_flip(dev, crtc);
9004 }
9005
9006 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9007 {
9008         struct drm_i915_private *dev_priv = dev->dev_private;
9009         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9010
9011         do_intel_finish_page_flip(dev, crtc);
9012 }
9013
9014 /* Is 'a' after or equal to 'b'? */
9015 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9016 {
9017         return !((a - b) & 0x80000000);
9018 }
9019
9020 static bool page_flip_finished(struct intel_crtc *crtc)
9021 {
9022         struct drm_device *dev = crtc->base.dev;
9023         struct drm_i915_private *dev_priv = dev->dev_private;
9024
9025         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9026             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9027                 return true;
9028
9029         /*
9030          * The relevant registers doen't exist on pre-ctg.
9031          * As the flip done interrupt doesn't trigger for mmio
9032          * flips on gmch platforms, a flip count check isn't
9033          * really needed there. But since ctg has the registers,
9034          * include it in the check anyway.
9035          */
9036         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9037                 return true;
9038
9039         /*
9040          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9041          * used the same base address. In that case the mmio flip might
9042          * have completed, but the CS hasn't even executed the flip yet.
9043          *
9044          * A flip count check isn't enough as the CS might have updated
9045          * the base address just after start of vblank, but before we
9046          * managed to process the interrupt. This means we'd complete the
9047          * CS flip too soon.
9048          *
9049          * Combining both checks should get us a good enough result. It may
9050          * still happen that the CS flip has been executed, but has not
9051          * yet actually completed. But in case the base address is the same
9052          * anyway, we don't really care.
9053          */
9054         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9055                 crtc->unpin_work->gtt_offset &&
9056                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9057                                     crtc->unpin_work->flip_count);
9058 }
9059
9060 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9061 {
9062         struct drm_i915_private *dev_priv = dev->dev_private;
9063         struct intel_crtc *intel_crtc =
9064                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9065         unsigned long flags;
9066
9067
9068         /*
9069          * This is called both by irq handlers and the reset code (to complete
9070          * lost pageflips) so needs the full irqsave spinlocks.
9071          *
9072          * NB: An MMIO update of the plane base pointer will also
9073          * generate a page-flip completion irq, i.e. every modeset
9074          * is also accompanied by a spurious intel_prepare_page_flip().
9075          */
9076         spin_lock_irqsave(&dev->event_lock, flags);
9077         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9078                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9079         spin_unlock_irqrestore(&dev->event_lock, flags);
9080 }
9081
9082 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9083 {
9084         /* Ensure that the work item is consistent when activating it ... */
9085         smp_wmb();
9086         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9087         /* and that it is marked active as soon as the irq could fire. */
9088         smp_wmb();
9089 }
9090
9091 static int intel_gen2_queue_flip(struct drm_device *dev,
9092                                  struct drm_crtc *crtc,
9093                                  struct drm_framebuffer *fb,
9094                                  struct drm_i915_gem_object *obj,
9095                                  struct intel_engine_cs *ring,
9096                                  uint32_t flags)
9097 {
9098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9099         u32 flip_mask;
9100         int ret;
9101
9102         ret = intel_ring_begin(ring, 6);
9103         if (ret)
9104                 return ret;
9105
9106         /* Can't queue multiple flips, so wait for the previous
9107          * one to finish before executing the next.
9108          */
9109         if (intel_crtc->plane)
9110                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9111         else
9112                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9113         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9114         intel_ring_emit(ring, MI_NOOP);
9115         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9116                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9117         intel_ring_emit(ring, fb->pitches[0]);
9118         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9119         intel_ring_emit(ring, 0); /* aux display base address, unused */
9120
9121         intel_mark_page_flip_active(intel_crtc);
9122         __intel_ring_advance(ring);
9123         return 0;
9124 }
9125
9126 static int intel_gen3_queue_flip(struct drm_device *dev,
9127                                  struct drm_crtc *crtc,
9128                                  struct drm_framebuffer *fb,
9129                                  struct drm_i915_gem_object *obj,
9130                                  struct intel_engine_cs *ring,
9131                                  uint32_t flags)
9132 {
9133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9134         u32 flip_mask;
9135         int ret;
9136
9137         ret = intel_ring_begin(ring, 6);
9138         if (ret)
9139                 return ret;
9140
9141         if (intel_crtc->plane)
9142                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9143         else
9144                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9145         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9146         intel_ring_emit(ring, MI_NOOP);
9147         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9148                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9149         intel_ring_emit(ring, fb->pitches[0]);
9150         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9151         intel_ring_emit(ring, MI_NOOP);
9152
9153         intel_mark_page_flip_active(intel_crtc);
9154         __intel_ring_advance(ring);
9155         return 0;
9156 }
9157
9158 static int intel_gen4_queue_flip(struct drm_device *dev,
9159                                  struct drm_crtc *crtc,
9160                                  struct drm_framebuffer *fb,
9161                                  struct drm_i915_gem_object *obj,
9162                                  struct intel_engine_cs *ring,
9163                                  uint32_t flags)
9164 {
9165         struct drm_i915_private *dev_priv = dev->dev_private;
9166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9167         uint32_t pf, pipesrc;
9168         int ret;
9169
9170         ret = intel_ring_begin(ring, 4);
9171         if (ret)
9172                 return ret;
9173
9174         /* i965+ uses the linear or tiled offsets from the
9175          * Display Registers (which do not change across a page-flip)
9176          * so we need only reprogram the base address.
9177          */
9178         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9179                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9180         intel_ring_emit(ring, fb->pitches[0]);
9181         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9182                         obj->tiling_mode);
9183
9184         /* XXX Enabling the panel-fitter across page-flip is so far
9185          * untested on non-native modes, so ignore it for now.
9186          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9187          */
9188         pf = 0;
9189         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9190         intel_ring_emit(ring, pf | pipesrc);
9191
9192         intel_mark_page_flip_active(intel_crtc);
9193         __intel_ring_advance(ring);
9194         return 0;
9195 }
9196
9197 static int intel_gen6_queue_flip(struct drm_device *dev,
9198                                  struct drm_crtc *crtc,
9199                                  struct drm_framebuffer *fb,
9200                                  struct drm_i915_gem_object *obj,
9201                                  struct intel_engine_cs *ring,
9202                                  uint32_t flags)
9203 {
9204         struct drm_i915_private *dev_priv = dev->dev_private;
9205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9206         uint32_t pf, pipesrc;
9207         int ret;
9208
9209         ret = intel_ring_begin(ring, 4);
9210         if (ret)
9211                 return ret;
9212
9213         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9214                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9215         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9216         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9217
9218         /* Contrary to the suggestions in the documentation,
9219          * "Enable Panel Fitter" does not seem to be required when page
9220          * flipping with a non-native mode, and worse causes a normal
9221          * modeset to fail.
9222          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9223          */
9224         pf = 0;
9225         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9226         intel_ring_emit(ring, pf | pipesrc);
9227
9228         intel_mark_page_flip_active(intel_crtc);
9229         __intel_ring_advance(ring);
9230         return 0;
9231 }
9232
9233 static int intel_gen7_queue_flip(struct drm_device *dev,
9234                                  struct drm_crtc *crtc,
9235                                  struct drm_framebuffer *fb,
9236                                  struct drm_i915_gem_object *obj,
9237                                  struct intel_engine_cs *ring,
9238                                  uint32_t flags)
9239 {
9240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9241         uint32_t plane_bit = 0;
9242         int len, ret;
9243
9244         switch (intel_crtc->plane) {
9245         case PLANE_A:
9246                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9247                 break;
9248         case PLANE_B:
9249                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9250                 break;
9251         case PLANE_C:
9252                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9253                 break;
9254         default:
9255                 WARN_ONCE(1, "unknown plane in flip command\n");
9256                 return -ENODEV;
9257         }
9258
9259         len = 4;
9260         if (ring->id == RCS) {
9261                 len += 6;
9262                 /*
9263                  * On Gen 8, SRM is now taking an extra dword to accommodate
9264                  * 48bits addresses, and we need a NOOP for the batch size to
9265                  * stay even.
9266                  */
9267                 if (IS_GEN8(dev))
9268                         len += 2;
9269         }
9270
9271         /*
9272          * BSpec MI_DISPLAY_FLIP for IVB:
9273          * "The full packet must be contained within the same cache line."
9274          *
9275          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9276          * cacheline, if we ever start emitting more commands before
9277          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9278          * then do the cacheline alignment, and finally emit the
9279          * MI_DISPLAY_FLIP.
9280          */
9281         ret = intel_ring_cacheline_align(ring);
9282         if (ret)
9283                 return ret;
9284
9285         ret = intel_ring_begin(ring, len);
9286         if (ret)
9287                 return ret;
9288
9289         /* Unmask the flip-done completion message. Note that the bspec says that
9290          * we should do this for both the BCS and RCS, and that we must not unmask
9291          * more than one flip event at any time (or ensure that one flip message
9292          * can be sent by waiting for flip-done prior to queueing new flips).
9293          * Experimentation says that BCS works despite DERRMR masking all
9294          * flip-done completion events and that unmasking all planes at once
9295          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9296          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9297          */
9298         if (ring->id == RCS) {
9299                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9300                 intel_ring_emit(ring, DERRMR);
9301                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9302                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9303                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9304                 if (IS_GEN8(dev))
9305                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9306                                               MI_SRM_LRM_GLOBAL_GTT);
9307                 else
9308                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9309                                               MI_SRM_LRM_GLOBAL_GTT);
9310                 intel_ring_emit(ring, DERRMR);
9311                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9312                 if (IS_GEN8(dev)) {
9313                         intel_ring_emit(ring, 0);
9314                         intel_ring_emit(ring, MI_NOOP);
9315                 }
9316         }
9317
9318         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9319         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9320         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9321         intel_ring_emit(ring, (MI_NOOP));
9322
9323         intel_mark_page_flip_active(intel_crtc);
9324         __intel_ring_advance(ring);
9325         return 0;
9326 }
9327
9328 static bool use_mmio_flip(struct intel_engine_cs *ring,
9329                           struct drm_i915_gem_object *obj)
9330 {
9331         /*
9332          * This is not being used for older platforms, because
9333          * non-availability of flip done interrupt forces us to use
9334          * CS flips. Older platforms derive flip done using some clever
9335          * tricks involving the flip_pending status bits and vblank irqs.
9336          * So using MMIO flips there would disrupt this mechanism.
9337          */
9338
9339         if (ring == NULL)
9340                 return true;
9341
9342         if (INTEL_INFO(ring->dev)->gen < 5)
9343                 return false;
9344
9345         if (i915.use_mmio_flip < 0)
9346                 return false;
9347         else if (i915.use_mmio_flip > 0)
9348                 return true;
9349         else if (i915.enable_execlists)
9350                 return true;
9351         else
9352                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9353 }
9354
9355 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9356 {
9357         struct drm_device *dev = intel_crtc->base.dev;
9358         struct drm_i915_private *dev_priv = dev->dev_private;
9359         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9360         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9361         struct drm_i915_gem_object *obj = intel_fb->obj;
9362         const enum pipe pipe = intel_crtc->pipe;
9363         u32 ctl, stride;
9364
9365         ctl = I915_READ(PLANE_CTL(pipe, 0));
9366         ctl &= ~PLANE_CTL_TILED_MASK;
9367         if (obj->tiling_mode == I915_TILING_X)
9368                 ctl |= PLANE_CTL_TILED_X;
9369
9370         /*
9371          * The stride is either expressed as a multiple of 64 bytes chunks for
9372          * linear buffers or in number of tiles for tiled buffers.
9373          */
9374         stride = fb->pitches[0] >> 6;
9375         if (obj->tiling_mode == I915_TILING_X)
9376                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9377
9378         /*
9379          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9380          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9381          */
9382         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9383         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9384
9385         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9386         POSTING_READ(PLANE_SURF(pipe, 0));
9387 }
9388
9389 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9390 {
9391         struct drm_device *dev = intel_crtc->base.dev;
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         struct intel_framebuffer *intel_fb =
9394                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9395         struct drm_i915_gem_object *obj = intel_fb->obj;
9396         u32 dspcntr;
9397         u32 reg;
9398
9399         reg = DSPCNTR(intel_crtc->plane);
9400         dspcntr = I915_READ(reg);
9401
9402         if (obj->tiling_mode != I915_TILING_NONE)
9403                 dspcntr |= DISPPLANE_TILED;
9404         else
9405                 dspcntr &= ~DISPPLANE_TILED;
9406
9407         I915_WRITE(reg, dspcntr);
9408
9409         I915_WRITE(DSPSURF(intel_crtc->plane),
9410                    intel_crtc->unpin_work->gtt_offset);
9411         POSTING_READ(DSPSURF(intel_crtc->plane));
9412
9413 }
9414
9415 /*
9416  * XXX: This is the temporary way to update the plane registers until we get
9417  * around to using the usual plane update functions for MMIO flips
9418  */
9419 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9420 {
9421         struct drm_device *dev = intel_crtc->base.dev;
9422         bool atomic_update;
9423         u32 start_vbl_count;
9424
9425         intel_mark_page_flip_active(intel_crtc);
9426
9427         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9428
9429         if (INTEL_INFO(dev)->gen >= 9)
9430                 skl_do_mmio_flip(intel_crtc);
9431         else
9432                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9433                 ilk_do_mmio_flip(intel_crtc);
9434
9435         if (atomic_update)
9436                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9437 }
9438
9439 static void intel_mmio_flip_work_func(struct work_struct *work)
9440 {
9441         struct intel_crtc *crtc =
9442                 container_of(work, struct intel_crtc, mmio_flip.work);
9443         struct intel_mmio_flip *mmio_flip;
9444
9445         mmio_flip = &crtc->mmio_flip;
9446         if (mmio_flip->req)
9447                 WARN_ON(__i915_wait_request(mmio_flip->req,
9448                                             crtc->reset_counter,
9449                                             false, NULL, NULL) != 0);
9450
9451         intel_do_mmio_flip(crtc);
9452         if (mmio_flip->req) {
9453                 mutex_lock(&crtc->base.dev->struct_mutex);
9454                 i915_gem_request_assign(&mmio_flip->req, NULL);
9455                 mutex_unlock(&crtc->base.dev->struct_mutex);
9456         }
9457 }
9458
9459 static int intel_queue_mmio_flip(struct drm_device *dev,
9460                                  struct drm_crtc *crtc,
9461                                  struct drm_framebuffer *fb,
9462                                  struct drm_i915_gem_object *obj,
9463                                  struct intel_engine_cs *ring,
9464                                  uint32_t flags)
9465 {
9466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9467
9468         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9469                                 obj->last_write_req);
9470
9471         schedule_work(&intel_crtc->mmio_flip.work);
9472
9473         return 0;
9474 }
9475
9476 static int intel_gen9_queue_flip(struct drm_device *dev,
9477                                  struct drm_crtc *crtc,
9478                                  struct drm_framebuffer *fb,
9479                                  struct drm_i915_gem_object *obj,
9480                                  struct intel_engine_cs *ring,
9481                                  uint32_t flags)
9482 {
9483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9484         uint32_t plane = 0, stride;
9485         int ret;
9486
9487         switch(intel_crtc->pipe) {
9488         case PIPE_A:
9489                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9490                 break;
9491         case PIPE_B:
9492                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9493                 break;
9494         case PIPE_C:
9495                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9496                 break;
9497         default:
9498                 WARN_ONCE(1, "unknown plane in flip command\n");
9499                 return -ENODEV;
9500         }
9501
9502         switch (obj->tiling_mode) {
9503         case I915_TILING_NONE:
9504                 stride = fb->pitches[0] >> 6;
9505                 break;
9506         case I915_TILING_X:
9507                 stride = fb->pitches[0] >> 9;
9508                 break;
9509         default:
9510                 WARN_ONCE(1, "unknown tiling in flip command\n");
9511                 return -ENODEV;
9512         }
9513
9514         ret = intel_ring_begin(ring, 10);
9515         if (ret)
9516                 return ret;
9517
9518         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9519         intel_ring_emit(ring, DERRMR);
9520         intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9521                                 DERRMR_PIPEB_PRI_FLIP_DONE |
9522                                 DERRMR_PIPEC_PRI_FLIP_DONE));
9523         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9524                               MI_SRM_LRM_GLOBAL_GTT);
9525         intel_ring_emit(ring, DERRMR);
9526         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9527         intel_ring_emit(ring, 0);
9528
9529         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9530         intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9531         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9532
9533         intel_mark_page_flip_active(intel_crtc);
9534         __intel_ring_advance(ring);
9535
9536         return 0;
9537 }
9538
9539 static int intel_default_queue_flip(struct drm_device *dev,
9540                                     struct drm_crtc *crtc,
9541                                     struct drm_framebuffer *fb,
9542                                     struct drm_i915_gem_object *obj,
9543                                     struct intel_engine_cs *ring,
9544                                     uint32_t flags)
9545 {
9546         return -ENODEV;
9547 }
9548
9549 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9550                                          struct drm_crtc *crtc)
9551 {
9552         struct drm_i915_private *dev_priv = dev->dev_private;
9553         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9554         struct intel_unpin_work *work = intel_crtc->unpin_work;
9555         u32 addr;
9556
9557         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9558                 return true;
9559
9560         if (!work->enable_stall_check)
9561                 return false;
9562
9563         if (work->flip_ready_vblank == 0) {
9564                 if (work->flip_queued_req &&
9565                     !i915_gem_request_completed(work->flip_queued_req, true))
9566                         return false;
9567
9568                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9569         }
9570
9571         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9572                 return false;
9573
9574         /* Potential stall - if we see that the flip has happened,
9575          * assume a missed interrupt. */
9576         if (INTEL_INFO(dev)->gen >= 4)
9577                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9578         else
9579                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9580
9581         /* There is a potential issue here with a false positive after a flip
9582          * to the same address. We could address this by checking for a
9583          * non-incrementing frame counter.
9584          */
9585         return addr == work->gtt_offset;
9586 }
9587
9588 void intel_check_page_flip(struct drm_device *dev, int pipe)
9589 {
9590         struct drm_i915_private *dev_priv = dev->dev_private;
9591         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9593
9594         WARN_ON(!in_irq());
9595
9596         if (crtc == NULL)
9597                 return;
9598
9599         spin_lock(&dev->event_lock);
9600         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9601                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9602                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9603                 page_flip_completed(intel_crtc);
9604         }
9605         spin_unlock(&dev->event_lock);
9606 }
9607
9608 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9609                                 struct drm_framebuffer *fb,
9610                                 struct drm_pending_vblank_event *event,
9611                                 uint32_t page_flip_flags)
9612 {
9613         struct drm_device *dev = crtc->dev;
9614         struct drm_i915_private *dev_priv = dev->dev_private;
9615         struct drm_framebuffer *old_fb = crtc->primary->fb;
9616         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9618         struct drm_plane *primary = crtc->primary;
9619         struct intel_plane *intel_plane = to_intel_plane(primary);
9620         enum pipe pipe = intel_crtc->pipe;
9621         struct intel_unpin_work *work;
9622         struct intel_engine_cs *ring;
9623         int ret;
9624
9625         /*
9626          * drm_mode_page_flip_ioctl() should already catch this, but double
9627          * check to be safe.  In the future we may enable pageflipping from
9628          * a disabled primary plane.
9629          */
9630         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9631                 return -EBUSY;
9632
9633         /* Can't change pixel format via MI display flips. */
9634         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9635                 return -EINVAL;
9636
9637         /*
9638          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9639          * Note that pitch changes could also affect these register.
9640          */
9641         if (INTEL_INFO(dev)->gen > 3 &&
9642             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9643              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9644                 return -EINVAL;
9645
9646         if (i915_terminally_wedged(&dev_priv->gpu_error))
9647                 goto out_hang;
9648
9649         work = kzalloc(sizeof(*work), GFP_KERNEL);
9650         if (work == NULL)
9651                 return -ENOMEM;
9652
9653         work->event = event;
9654         work->crtc = crtc;
9655         work->old_fb_obj = intel_fb_obj(old_fb);
9656         INIT_WORK(&work->work, intel_unpin_work_fn);
9657
9658         ret = drm_crtc_vblank_get(crtc);
9659         if (ret)
9660                 goto free_work;
9661
9662         /* We borrow the event spin lock for protecting unpin_work */
9663         spin_lock_irq(&dev->event_lock);
9664         if (intel_crtc->unpin_work) {
9665                 /* Before declaring the flip queue wedged, check if
9666                  * the hardware completed the operation behind our backs.
9667                  */
9668                 if (__intel_pageflip_stall_check(dev, crtc)) {
9669                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9670                         page_flip_completed(intel_crtc);
9671                 } else {
9672                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9673                         spin_unlock_irq(&dev->event_lock);
9674
9675                         drm_crtc_vblank_put(crtc);
9676                         kfree(work);
9677                         return -EBUSY;
9678                 }
9679         }
9680         intel_crtc->unpin_work = work;
9681         spin_unlock_irq(&dev->event_lock);
9682
9683         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9684                 flush_workqueue(dev_priv->wq);
9685
9686         ret = i915_mutex_lock_interruptible(dev);
9687         if (ret)
9688                 goto cleanup;
9689
9690         /* Reference the objects for the scheduled work. */
9691         drm_gem_object_reference(&work->old_fb_obj->base);
9692         drm_gem_object_reference(&obj->base);
9693
9694         crtc->primary->fb = fb;
9695
9696         work->pending_flip_obj = obj;
9697
9698         atomic_inc(&intel_crtc->unpin_work_count);
9699         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9700
9701         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9702                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9703
9704         if (IS_VALLEYVIEW(dev)) {
9705                 ring = &dev_priv->ring[BCS];
9706                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9707                         /* vlv: DISPLAY_FLIP fails to change tiling */
9708                         ring = NULL;
9709         } else if (IS_IVYBRIDGE(dev)) {
9710                 ring = &dev_priv->ring[BCS];
9711         } else if (INTEL_INFO(dev)->gen >= 7) {
9712                 ring = i915_gem_request_get_ring(obj->last_read_req);
9713                 if (ring == NULL || ring->id != RCS)
9714                         ring = &dev_priv->ring[BCS];
9715         } else {
9716                 ring = &dev_priv->ring[RCS];
9717         }
9718
9719         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9720         if (ret)
9721                 goto cleanup_pending;
9722
9723         work->gtt_offset =
9724                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9725
9726         if (use_mmio_flip(ring, obj)) {
9727                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9728                                             page_flip_flags);
9729                 if (ret)
9730                         goto cleanup_unpin;
9731
9732                 i915_gem_request_assign(&work->flip_queued_req,
9733                                         obj->last_write_req);
9734         } else {
9735                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9736                                                    page_flip_flags);
9737                 if (ret)
9738                         goto cleanup_unpin;
9739
9740                 i915_gem_request_assign(&work->flip_queued_req,
9741                                         intel_ring_get_request(ring));
9742         }
9743
9744         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9745         work->enable_stall_check = true;
9746
9747         i915_gem_track_fb(work->old_fb_obj, obj,
9748                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9749
9750         intel_disable_fbc(dev);
9751         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9752         mutex_unlock(&dev->struct_mutex);
9753
9754         trace_i915_flip_request(intel_crtc->plane, obj);
9755
9756         return 0;
9757
9758 cleanup_unpin:
9759         intel_unpin_fb_obj(obj);
9760 cleanup_pending:
9761         atomic_dec(&intel_crtc->unpin_work_count);
9762         crtc->primary->fb = old_fb;
9763         drm_gem_object_unreference(&work->old_fb_obj->base);
9764         drm_gem_object_unreference(&obj->base);
9765         mutex_unlock(&dev->struct_mutex);
9766
9767 cleanup:
9768         spin_lock_irq(&dev->event_lock);
9769         intel_crtc->unpin_work = NULL;
9770         spin_unlock_irq(&dev->event_lock);
9771
9772         drm_crtc_vblank_put(crtc);
9773 free_work:
9774         kfree(work);
9775
9776         if (ret == -EIO) {
9777 out_hang:
9778                 ret = primary->funcs->update_plane(primary, crtc, fb,
9779                                                    intel_plane->crtc_x,
9780                                                    intel_plane->crtc_y,
9781                                                    intel_plane->crtc_h,
9782                                                    intel_plane->crtc_w,
9783                                                    intel_plane->src_x,
9784                                                    intel_plane->src_y,
9785                                                    intel_plane->src_h,
9786                                                    intel_plane->src_w);
9787                 if (ret == 0 && event) {
9788                         spin_lock_irq(&dev->event_lock);
9789                         drm_send_vblank_event(dev, pipe, event);
9790                         spin_unlock_irq(&dev->event_lock);
9791                 }
9792         }
9793         return ret;
9794 }
9795
9796 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9797         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9798         .load_lut = intel_crtc_load_lut,
9799 };
9800
9801 /**
9802  * intel_modeset_update_staged_output_state
9803  *
9804  * Updates the staged output configuration state, e.g. after we've read out the
9805  * current hw state.
9806  */
9807 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9808 {
9809         struct intel_crtc *crtc;
9810         struct intel_encoder *encoder;
9811         struct intel_connector *connector;
9812
9813         list_for_each_entry(connector, &dev->mode_config.connector_list,
9814                             base.head) {
9815                 connector->new_encoder =
9816                         to_intel_encoder(connector->base.encoder);
9817         }
9818
9819         for_each_intel_encoder(dev, encoder) {
9820                 encoder->new_crtc =
9821                         to_intel_crtc(encoder->base.crtc);
9822         }
9823
9824         for_each_intel_crtc(dev, crtc) {
9825                 crtc->new_enabled = crtc->base.enabled;
9826
9827                 if (crtc->new_enabled)
9828                         crtc->new_config = &crtc->config;
9829                 else
9830                         crtc->new_config = NULL;
9831         }
9832 }
9833
9834 /**
9835  * intel_modeset_commit_output_state
9836  *
9837  * This function copies the stage display pipe configuration to the real one.
9838  */
9839 static void intel_modeset_commit_output_state(struct drm_device *dev)
9840 {
9841         struct intel_crtc *crtc;
9842         struct intel_encoder *encoder;
9843         struct intel_connector *connector;
9844
9845         list_for_each_entry(connector, &dev->mode_config.connector_list,
9846                             base.head) {
9847                 connector->base.encoder = &connector->new_encoder->base;
9848         }
9849
9850         for_each_intel_encoder(dev, encoder) {
9851                 encoder->base.crtc = &encoder->new_crtc->base;
9852         }
9853
9854         for_each_intel_crtc(dev, crtc) {
9855                 crtc->base.enabled = crtc->new_enabled;
9856         }
9857 }
9858
9859 static void
9860 connected_sink_compute_bpp(struct intel_connector *connector,
9861                            struct intel_crtc_config *pipe_config)
9862 {
9863         int bpp = pipe_config->pipe_bpp;
9864
9865         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9866                 connector->base.base.id,
9867                 connector->base.name);
9868
9869         /* Don't use an invalid EDID bpc value */
9870         if (connector->base.display_info.bpc &&
9871             connector->base.display_info.bpc * 3 < bpp) {
9872                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9873                               bpp, connector->base.display_info.bpc*3);
9874                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9875         }
9876
9877         /* Clamp bpp to 8 on screens without EDID 1.4 */
9878         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9879                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9880                               bpp);
9881                 pipe_config->pipe_bpp = 24;
9882         }
9883 }
9884
9885 static int
9886 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9887                           struct drm_framebuffer *fb,
9888                           struct intel_crtc_config *pipe_config)
9889 {
9890         struct drm_device *dev = crtc->base.dev;
9891         struct intel_connector *connector;
9892         int bpp;
9893
9894         switch (fb->pixel_format) {
9895         case DRM_FORMAT_C8:
9896                 bpp = 8*3; /* since we go through a colormap */
9897                 break;
9898         case DRM_FORMAT_XRGB1555:
9899         case DRM_FORMAT_ARGB1555:
9900                 /* checked in intel_framebuffer_init already */
9901                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9902                         return -EINVAL;
9903         case DRM_FORMAT_RGB565:
9904                 bpp = 6*3; /* min is 18bpp */
9905                 break;
9906         case DRM_FORMAT_XBGR8888:
9907         case DRM_FORMAT_ABGR8888:
9908                 /* checked in intel_framebuffer_init already */
9909                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9910                         return -EINVAL;
9911         case DRM_FORMAT_XRGB8888:
9912         case DRM_FORMAT_ARGB8888:
9913                 bpp = 8*3;
9914                 break;
9915         case DRM_FORMAT_XRGB2101010:
9916         case DRM_FORMAT_ARGB2101010:
9917         case DRM_FORMAT_XBGR2101010:
9918         case DRM_FORMAT_ABGR2101010:
9919                 /* checked in intel_framebuffer_init already */
9920                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9921                         return -EINVAL;
9922                 bpp = 10*3;
9923                 break;
9924         /* TODO: gen4+ supports 16 bpc floating point, too. */
9925         default:
9926                 DRM_DEBUG_KMS("unsupported depth\n");
9927                 return -EINVAL;
9928         }
9929
9930         pipe_config->pipe_bpp = bpp;
9931
9932         /* Clamp display bpp to EDID value */
9933         list_for_each_entry(connector, &dev->mode_config.connector_list,
9934                             base.head) {
9935                 if (!connector->new_encoder ||
9936                     connector->new_encoder->new_crtc != crtc)
9937                         continue;
9938
9939                 connected_sink_compute_bpp(connector, pipe_config);
9940         }
9941
9942         return bpp;
9943 }
9944
9945 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9946 {
9947         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9948                         "type: 0x%x flags: 0x%x\n",
9949                 mode->crtc_clock,
9950                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9951                 mode->crtc_hsync_end, mode->crtc_htotal,
9952                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9953                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9954 }
9955
9956 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9957                                    struct intel_crtc_config *pipe_config,
9958                                    const char *context)
9959 {
9960         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9961                       context, pipe_name(crtc->pipe));
9962
9963         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9964         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9965                       pipe_config->pipe_bpp, pipe_config->dither);
9966         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9967                       pipe_config->has_pch_encoder,
9968                       pipe_config->fdi_lanes,
9969                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9970                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9971                       pipe_config->fdi_m_n.tu);
9972         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9973                       pipe_config->has_dp_encoder,
9974                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9975                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9976                       pipe_config->dp_m_n.tu);
9977
9978         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9979                       pipe_config->has_dp_encoder,
9980                       pipe_config->dp_m2_n2.gmch_m,
9981                       pipe_config->dp_m2_n2.gmch_n,
9982                       pipe_config->dp_m2_n2.link_m,
9983                       pipe_config->dp_m2_n2.link_n,
9984                       pipe_config->dp_m2_n2.tu);
9985
9986         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
9987                       pipe_config->has_audio,
9988                       pipe_config->has_infoframe);
9989
9990         DRM_DEBUG_KMS("requested mode:\n");
9991         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9992         DRM_DEBUG_KMS("adjusted mode:\n");
9993         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9994         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9995         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9996         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9997                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9998         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9999                       pipe_config->gmch_pfit.control,
10000                       pipe_config->gmch_pfit.pgm_ratios,
10001                       pipe_config->gmch_pfit.lvds_border_bits);
10002         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10003                       pipe_config->pch_pfit.pos,
10004                       pipe_config->pch_pfit.size,
10005                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10006         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10007         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10008 }
10009
10010 static bool encoders_cloneable(const struct intel_encoder *a,
10011                                const struct intel_encoder *b)
10012 {
10013         /* masks could be asymmetric, so check both ways */
10014         return a == b || (a->cloneable & (1 << b->type) &&
10015                           b->cloneable & (1 << a->type));
10016 }
10017
10018 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10019                                          struct intel_encoder *encoder)
10020 {
10021         struct drm_device *dev = crtc->base.dev;
10022         struct intel_encoder *source_encoder;
10023
10024         for_each_intel_encoder(dev, source_encoder) {
10025                 if (source_encoder->new_crtc != crtc)
10026                         continue;
10027
10028                 if (!encoders_cloneable(encoder, source_encoder))
10029                         return false;
10030         }
10031
10032         return true;
10033 }
10034
10035 static bool check_encoder_cloning(struct intel_crtc *crtc)
10036 {
10037         struct drm_device *dev = crtc->base.dev;
10038         struct intel_encoder *encoder;
10039
10040         for_each_intel_encoder(dev, encoder) {
10041                 if (encoder->new_crtc != crtc)
10042                         continue;
10043
10044                 if (!check_single_encoder_cloning(crtc, encoder))
10045                         return false;
10046         }
10047
10048         return true;
10049 }
10050
10051 static bool check_digital_port_conflicts(struct drm_device *dev)
10052 {
10053         struct intel_connector *connector;
10054         unsigned int used_ports = 0;
10055
10056         /*
10057          * Walk the connector list instead of the encoder
10058          * list to detect the problem on ddi platforms
10059          * where there's just one encoder per digital port.
10060          */
10061         list_for_each_entry(connector,
10062                             &dev->mode_config.connector_list, base.head) {
10063                 struct intel_encoder *encoder = connector->new_encoder;
10064
10065                 if (!encoder)
10066                         continue;
10067
10068                 WARN_ON(!encoder->new_crtc);
10069
10070                 switch (encoder->type) {
10071                         unsigned int port_mask;
10072                 case INTEL_OUTPUT_UNKNOWN:
10073                         if (WARN_ON(!HAS_DDI(dev)))
10074                                 break;
10075                 case INTEL_OUTPUT_DISPLAYPORT:
10076                 case INTEL_OUTPUT_HDMI:
10077                 case INTEL_OUTPUT_EDP:
10078                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10079
10080                         /* the same port mustn't appear more than once */
10081                         if (used_ports & port_mask)
10082                                 return false;
10083
10084                         used_ports |= port_mask;
10085                 default:
10086                         break;
10087                 }
10088         }
10089
10090         return true;
10091 }
10092
10093 static struct intel_crtc_config *
10094 intel_modeset_pipe_config(struct drm_crtc *crtc,
10095                           struct drm_framebuffer *fb,
10096                           struct drm_display_mode *mode)
10097 {
10098         struct drm_device *dev = crtc->dev;
10099         struct intel_encoder *encoder;
10100         struct intel_crtc_config *pipe_config;
10101         int plane_bpp, ret = -EINVAL;
10102         bool retry = true;
10103
10104         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10105                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10106                 return ERR_PTR(-EINVAL);
10107         }
10108
10109         if (!check_digital_port_conflicts(dev)) {
10110                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10111                 return ERR_PTR(-EINVAL);
10112         }
10113
10114         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10115         if (!pipe_config)
10116                 return ERR_PTR(-ENOMEM);
10117
10118         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10119         drm_mode_copy(&pipe_config->requested_mode, mode);
10120
10121         pipe_config->cpu_transcoder =
10122                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10123         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10124
10125         /*
10126          * Sanitize sync polarity flags based on requested ones. If neither
10127          * positive or negative polarity is requested, treat this as meaning
10128          * negative polarity.
10129          */
10130         if (!(pipe_config->adjusted_mode.flags &
10131               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10132                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10133
10134         if (!(pipe_config->adjusted_mode.flags &
10135               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10136                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10137
10138         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10139          * plane pixel format and any sink constraints into account. Returns the
10140          * source plane bpp so that dithering can be selected on mismatches
10141          * after encoders and crtc also have had their say. */
10142         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10143                                               fb, pipe_config);
10144         if (plane_bpp < 0)
10145                 goto fail;
10146
10147         /*
10148          * Determine the real pipe dimensions. Note that stereo modes can
10149          * increase the actual pipe size due to the frame doubling and
10150          * insertion of additional space for blanks between the frame. This
10151          * is stored in the crtc timings. We use the requested mode to do this
10152          * computation to clearly distinguish it from the adjusted mode, which
10153          * can be changed by the connectors in the below retry loop.
10154          */
10155         drm_crtc_get_hv_timing(&pipe_config->requested_mode,
10156                                &pipe_config->pipe_src_w,
10157                                &pipe_config->pipe_src_h);
10158
10159 encoder_retry:
10160         /* Ensure the port clock defaults are reset when retrying. */
10161         pipe_config->port_clock = 0;
10162         pipe_config->pixel_multiplier = 1;
10163
10164         /* Fill in default crtc timings, allow encoders to overwrite them. */
10165         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10166
10167         /* Pass our mode to the connectors and the CRTC to give them a chance to
10168          * adjust it according to limitations or connector properties, and also
10169          * a chance to reject the mode entirely.
10170          */
10171         for_each_intel_encoder(dev, encoder) {
10172
10173                 if (&encoder->new_crtc->base != crtc)
10174                         continue;
10175
10176                 if (!(encoder->compute_config(encoder, pipe_config))) {
10177                         DRM_DEBUG_KMS("Encoder config failure\n");
10178                         goto fail;
10179                 }
10180         }
10181
10182         /* Set default port clock if not overwritten by the encoder. Needs to be
10183          * done afterwards in case the encoder adjusts the mode. */
10184         if (!pipe_config->port_clock)
10185                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10186                         * pipe_config->pixel_multiplier;
10187
10188         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10189         if (ret < 0) {
10190                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10191                 goto fail;
10192         }
10193
10194         if (ret == RETRY) {
10195                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10196                         ret = -EINVAL;
10197                         goto fail;
10198                 }
10199
10200                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10201                 retry = false;
10202                 goto encoder_retry;
10203         }
10204
10205         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10206         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10207                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10208
10209         return pipe_config;
10210 fail:
10211         kfree(pipe_config);
10212         return ERR_PTR(ret);
10213 }
10214
10215 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10216  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10217 static void
10218 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10219                              unsigned *prepare_pipes, unsigned *disable_pipes)
10220 {
10221         struct intel_crtc *intel_crtc;
10222         struct drm_device *dev = crtc->dev;
10223         struct intel_encoder *encoder;
10224         struct intel_connector *connector;
10225         struct drm_crtc *tmp_crtc;
10226
10227         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10228
10229         /* Check which crtcs have changed outputs connected to them, these need
10230          * to be part of the prepare_pipes mask. We don't (yet) support global
10231          * modeset across multiple crtcs, so modeset_pipes will only have one
10232          * bit set at most. */
10233         list_for_each_entry(connector, &dev->mode_config.connector_list,
10234                             base.head) {
10235                 if (connector->base.encoder == &connector->new_encoder->base)
10236                         continue;
10237
10238                 if (connector->base.encoder) {
10239                         tmp_crtc = connector->base.encoder->crtc;
10240
10241                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10242                 }
10243
10244                 if (connector->new_encoder)
10245                         *prepare_pipes |=
10246                                 1 << connector->new_encoder->new_crtc->pipe;
10247         }
10248
10249         for_each_intel_encoder(dev, encoder) {
10250                 if (encoder->base.crtc == &encoder->new_crtc->base)
10251                         continue;
10252
10253                 if (encoder->base.crtc) {
10254                         tmp_crtc = encoder->base.crtc;
10255
10256                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10257                 }
10258
10259                 if (encoder->new_crtc)
10260                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10261         }
10262
10263         /* Check for pipes that will be enabled/disabled ... */
10264         for_each_intel_crtc(dev, intel_crtc) {
10265                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10266                         continue;
10267
10268                 if (!intel_crtc->new_enabled)
10269                         *disable_pipes |= 1 << intel_crtc->pipe;
10270                 else
10271                         *prepare_pipes |= 1 << intel_crtc->pipe;
10272         }
10273
10274
10275         /* set_mode is also used to update properties on life display pipes. */
10276         intel_crtc = to_intel_crtc(crtc);
10277         if (intel_crtc->new_enabled)
10278                 *prepare_pipes |= 1 << intel_crtc->pipe;
10279
10280         /*
10281          * For simplicity do a full modeset on any pipe where the output routing
10282          * changed. We could be more clever, but that would require us to be
10283          * more careful with calling the relevant encoder->mode_set functions.
10284          */
10285         if (*prepare_pipes)
10286                 *modeset_pipes = *prepare_pipes;
10287
10288         /* ... and mask these out. */
10289         *modeset_pipes &= ~(*disable_pipes);
10290         *prepare_pipes &= ~(*disable_pipes);
10291
10292         /*
10293          * HACK: We don't (yet) fully support global modesets. intel_set_config
10294          * obies this rule, but the modeset restore mode of
10295          * intel_modeset_setup_hw_state does not.
10296          */
10297         *modeset_pipes &= 1 << intel_crtc->pipe;
10298         *prepare_pipes &= 1 << intel_crtc->pipe;
10299
10300         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10301                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10302 }
10303
10304 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10305 {
10306         struct drm_encoder *encoder;
10307         struct drm_device *dev = crtc->dev;
10308
10309         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10310                 if (encoder->crtc == crtc)
10311                         return true;
10312
10313         return false;
10314 }
10315
10316 static void
10317 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10318 {
10319         struct drm_i915_private *dev_priv = dev->dev_private;
10320         struct intel_encoder *intel_encoder;
10321         struct intel_crtc *intel_crtc;
10322         struct drm_connector *connector;
10323
10324         intel_shared_dpll_commit(dev_priv);
10325
10326         for_each_intel_encoder(dev, intel_encoder) {
10327                 if (!intel_encoder->base.crtc)
10328                         continue;
10329
10330                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10331
10332                 if (prepare_pipes & (1 << intel_crtc->pipe))
10333                         intel_encoder->connectors_active = false;
10334         }
10335
10336         intel_modeset_commit_output_state(dev);
10337
10338         /* Double check state. */
10339         for_each_intel_crtc(dev, intel_crtc) {
10340                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10341                 WARN_ON(intel_crtc->new_config &&
10342                         intel_crtc->new_config != &intel_crtc->config);
10343                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10344         }
10345
10346         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10347                 if (!connector->encoder || !connector->encoder->crtc)
10348                         continue;
10349
10350                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10351
10352                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10353                         struct drm_property *dpms_property =
10354                                 dev->mode_config.dpms_property;
10355
10356                         connector->dpms = DRM_MODE_DPMS_ON;
10357                         drm_object_property_set_value(&connector->base,
10358                                                          dpms_property,
10359                                                          DRM_MODE_DPMS_ON);
10360
10361                         intel_encoder = to_intel_encoder(connector->encoder);
10362                         intel_encoder->connectors_active = true;
10363                 }
10364         }
10365
10366 }
10367
10368 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10369 {
10370         int diff;
10371
10372         if (clock1 == clock2)
10373                 return true;
10374
10375         if (!clock1 || !clock2)
10376                 return false;
10377
10378         diff = abs(clock1 - clock2);
10379
10380         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10381                 return true;
10382
10383         return false;
10384 }
10385
10386 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10387         list_for_each_entry((intel_crtc), \
10388                             &(dev)->mode_config.crtc_list, \
10389                             base.head) \
10390                 if (mask & (1 <<(intel_crtc)->pipe))
10391
10392 static bool
10393 intel_pipe_config_compare(struct drm_device *dev,
10394                           struct intel_crtc_config *current_config,
10395                           struct intel_crtc_config *pipe_config)
10396 {
10397 #define PIPE_CONF_CHECK_X(name) \
10398         if (current_config->name != pipe_config->name) { \
10399                 DRM_ERROR("mismatch in " #name " " \
10400                           "(expected 0x%08x, found 0x%08x)\n", \
10401                           current_config->name, \
10402                           pipe_config->name); \
10403                 return false; \
10404         }
10405
10406 #define PIPE_CONF_CHECK_I(name) \
10407         if (current_config->name != pipe_config->name) { \
10408                 DRM_ERROR("mismatch in " #name " " \
10409                           "(expected %i, found %i)\n", \
10410                           current_config->name, \
10411                           pipe_config->name); \
10412                 return false; \
10413         }
10414
10415 /* This is required for BDW+ where there is only one set of registers for
10416  * switching between high and low RR.
10417  * This macro can be used whenever a comparison has to be made between one
10418  * hw state and multiple sw state variables.
10419  */
10420 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10421         if ((current_config->name != pipe_config->name) && \
10422                 (current_config->alt_name != pipe_config->name)) { \
10423                         DRM_ERROR("mismatch in " #name " " \
10424                                   "(expected %i or %i, found %i)\n", \
10425                                   current_config->name, \
10426                                   current_config->alt_name, \
10427                                   pipe_config->name); \
10428                         return false; \
10429         }
10430
10431 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10432         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10433                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10434                           "(expected %i, found %i)\n", \
10435                           current_config->name & (mask), \
10436                           pipe_config->name & (mask)); \
10437                 return false; \
10438         }
10439
10440 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10441         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10442                 DRM_ERROR("mismatch in " #name " " \
10443                           "(expected %i, found %i)\n", \
10444                           current_config->name, \
10445                           pipe_config->name); \
10446                 return false; \
10447         }
10448
10449 #define PIPE_CONF_QUIRK(quirk)  \
10450         ((current_config->quirks | pipe_config->quirks) & (quirk))
10451
10452         PIPE_CONF_CHECK_I(cpu_transcoder);
10453
10454         PIPE_CONF_CHECK_I(has_pch_encoder);
10455         PIPE_CONF_CHECK_I(fdi_lanes);
10456         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10457         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10458         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10459         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10460         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10461
10462         PIPE_CONF_CHECK_I(has_dp_encoder);
10463
10464         if (INTEL_INFO(dev)->gen < 8) {
10465                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10466                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10467                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10468                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10469                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10470
10471                 if (current_config->has_drrs) {
10472                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10473                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10474                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10475                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10476                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10477                 }
10478         } else {
10479                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10480                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10481                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10482                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10483                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10484         }
10485
10486         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10487         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10488         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10489         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10490         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10491         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10492
10493         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10494         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10495         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10496         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10497         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10498         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10499
10500         PIPE_CONF_CHECK_I(pixel_multiplier);
10501         PIPE_CONF_CHECK_I(has_hdmi_sink);
10502         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10503             IS_VALLEYVIEW(dev))
10504                 PIPE_CONF_CHECK_I(limited_color_range);
10505         PIPE_CONF_CHECK_I(has_infoframe);
10506
10507         PIPE_CONF_CHECK_I(has_audio);
10508
10509         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10510                               DRM_MODE_FLAG_INTERLACE);
10511
10512         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10513                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10514                                       DRM_MODE_FLAG_PHSYNC);
10515                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10516                                       DRM_MODE_FLAG_NHSYNC);
10517                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10518                                       DRM_MODE_FLAG_PVSYNC);
10519                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10520                                       DRM_MODE_FLAG_NVSYNC);
10521         }
10522
10523         PIPE_CONF_CHECK_I(pipe_src_w);
10524         PIPE_CONF_CHECK_I(pipe_src_h);
10525
10526         /*
10527          * FIXME: BIOS likes to set up a cloned config with lvds+external
10528          * screen. Since we don't yet re-compute the pipe config when moving
10529          * just the lvds port away to another pipe the sw tracking won't match.
10530          *
10531          * Proper atomic modesets with recomputed global state will fix this.
10532          * Until then just don't check gmch state for inherited modes.
10533          */
10534         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10535                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10536                 /* pfit ratios are autocomputed by the hw on gen4+ */
10537                 if (INTEL_INFO(dev)->gen < 4)
10538                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10539                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10540         }
10541
10542         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10543         if (current_config->pch_pfit.enabled) {
10544                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10545                 PIPE_CONF_CHECK_I(pch_pfit.size);
10546         }
10547
10548         /* BDW+ don't expose a synchronous way to read the state */
10549         if (IS_HASWELL(dev))
10550                 PIPE_CONF_CHECK_I(ips_enabled);
10551
10552         PIPE_CONF_CHECK_I(double_wide);
10553
10554         PIPE_CONF_CHECK_X(ddi_pll_sel);
10555
10556         PIPE_CONF_CHECK_I(shared_dpll);
10557         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10558         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10559         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10560         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10561         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10562         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10563         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10564         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10565
10566         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10567                 PIPE_CONF_CHECK_I(pipe_bpp);
10568
10569         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10570         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10571
10572 #undef PIPE_CONF_CHECK_X
10573 #undef PIPE_CONF_CHECK_I
10574 #undef PIPE_CONF_CHECK_I_ALT
10575 #undef PIPE_CONF_CHECK_FLAGS
10576 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10577 #undef PIPE_CONF_QUIRK
10578
10579         return true;
10580 }
10581
10582 static void check_wm_state(struct drm_device *dev)
10583 {
10584         struct drm_i915_private *dev_priv = dev->dev_private;
10585         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10586         struct intel_crtc *intel_crtc;
10587         int plane;
10588
10589         if (INTEL_INFO(dev)->gen < 9)
10590                 return;
10591
10592         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10593         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10594
10595         for_each_intel_crtc(dev, intel_crtc) {
10596                 struct skl_ddb_entry *hw_entry, *sw_entry;
10597                 const enum pipe pipe = intel_crtc->pipe;
10598
10599                 if (!intel_crtc->active)
10600                         continue;
10601
10602                 /* planes */
10603                 for_each_plane(pipe, plane) {
10604                         hw_entry = &hw_ddb.plane[pipe][plane];
10605                         sw_entry = &sw_ddb->plane[pipe][plane];
10606
10607                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10608                                 continue;
10609
10610                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10611                                   "(expected (%u,%u), found (%u,%u))\n",
10612                                   pipe_name(pipe), plane + 1,
10613                                   sw_entry->start, sw_entry->end,
10614                                   hw_entry->start, hw_entry->end);
10615                 }
10616
10617                 /* cursor */
10618                 hw_entry = &hw_ddb.cursor[pipe];
10619                 sw_entry = &sw_ddb->cursor[pipe];
10620
10621                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10622                         continue;
10623
10624                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10625                           "(expected (%u,%u), found (%u,%u))\n",
10626                           pipe_name(pipe),
10627                           sw_entry->start, sw_entry->end,
10628                           hw_entry->start, hw_entry->end);
10629         }
10630 }
10631
10632 static void
10633 check_connector_state(struct drm_device *dev)
10634 {
10635         struct intel_connector *connector;
10636
10637         list_for_each_entry(connector, &dev->mode_config.connector_list,
10638                             base.head) {
10639                 /* This also checks the encoder/connector hw state with the
10640                  * ->get_hw_state callbacks. */
10641                 intel_connector_check_state(connector);
10642
10643                 WARN(&connector->new_encoder->base != connector->base.encoder,
10644                      "connector's staged encoder doesn't match current encoder\n");
10645         }
10646 }
10647
10648 static void
10649 check_encoder_state(struct drm_device *dev)
10650 {
10651         struct intel_encoder *encoder;
10652         struct intel_connector *connector;
10653
10654         for_each_intel_encoder(dev, encoder) {
10655                 bool enabled = false;
10656                 bool active = false;
10657                 enum pipe pipe, tracked_pipe;
10658
10659                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10660                               encoder->base.base.id,
10661                               encoder->base.name);
10662
10663                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10664                      "encoder's stage crtc doesn't match current crtc\n");
10665                 WARN(encoder->connectors_active && !encoder->base.crtc,
10666                      "encoder's active_connectors set, but no crtc\n");
10667
10668                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10669                                     base.head) {
10670                         if (connector->base.encoder != &encoder->base)
10671                                 continue;
10672                         enabled = true;
10673                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10674                                 active = true;
10675                 }
10676                 /*
10677                  * for MST connectors if we unplug the connector is gone
10678                  * away but the encoder is still connected to a crtc
10679                  * until a modeset happens in response to the hotplug.
10680                  */
10681                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10682                         continue;
10683
10684                 WARN(!!encoder->base.crtc != enabled,
10685                      "encoder's enabled state mismatch "
10686                      "(expected %i, found %i)\n",
10687                      !!encoder->base.crtc, enabled);
10688                 WARN(active && !encoder->base.crtc,
10689                      "active encoder with no crtc\n");
10690
10691                 WARN(encoder->connectors_active != active,
10692                      "encoder's computed active state doesn't match tracked active state "
10693                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10694
10695                 active = encoder->get_hw_state(encoder, &pipe);
10696                 WARN(active != encoder->connectors_active,
10697                      "encoder's hw state doesn't match sw tracking "
10698                      "(expected %i, found %i)\n",
10699                      encoder->connectors_active, active);
10700
10701                 if (!encoder->base.crtc)
10702                         continue;
10703
10704                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10705                 WARN(active && pipe != tracked_pipe,
10706                      "active encoder's pipe doesn't match"
10707                      "(expected %i, found %i)\n",
10708                      tracked_pipe, pipe);
10709
10710         }
10711 }
10712
10713 static void
10714 check_crtc_state(struct drm_device *dev)
10715 {
10716         struct drm_i915_private *dev_priv = dev->dev_private;
10717         struct intel_crtc *crtc;
10718         struct intel_encoder *encoder;
10719         struct intel_crtc_config pipe_config;
10720
10721         for_each_intel_crtc(dev, crtc) {
10722                 bool enabled = false;
10723                 bool active = false;
10724
10725                 memset(&pipe_config, 0, sizeof(pipe_config));
10726
10727                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10728                               crtc->base.base.id);
10729
10730                 WARN(crtc->active && !crtc->base.enabled,
10731                      "active crtc, but not enabled in sw tracking\n");
10732
10733                 for_each_intel_encoder(dev, encoder) {
10734                         if (encoder->base.crtc != &crtc->base)
10735                                 continue;
10736                         enabled = true;
10737                         if (encoder->connectors_active)
10738                                 active = true;
10739                 }
10740
10741                 WARN(active != crtc->active,
10742                      "crtc's computed active state doesn't match tracked active state "
10743                      "(expected %i, found %i)\n", active, crtc->active);
10744                 WARN(enabled != crtc->base.enabled,
10745                      "crtc's computed enabled state doesn't match tracked enabled state "
10746                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10747
10748                 active = dev_priv->display.get_pipe_config(crtc,
10749                                                            &pipe_config);
10750
10751                 /* hw state is inconsistent with the pipe quirk */
10752                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10753                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10754                         active = crtc->active;
10755
10756                 for_each_intel_encoder(dev, encoder) {
10757                         enum pipe pipe;
10758                         if (encoder->base.crtc != &crtc->base)
10759                                 continue;
10760                         if (encoder->get_hw_state(encoder, &pipe))
10761                                 encoder->get_config(encoder, &pipe_config);
10762                 }
10763
10764                 WARN(crtc->active != active,
10765                      "crtc active state doesn't match with hw state "
10766                      "(expected %i, found %i)\n", crtc->active, active);
10767
10768                 if (active &&
10769                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10770                         WARN(1, "pipe state doesn't match!\n");
10771                         intel_dump_pipe_config(crtc, &pipe_config,
10772                                                "[hw state]");
10773                         intel_dump_pipe_config(crtc, &crtc->config,
10774                                                "[sw state]");
10775                 }
10776         }
10777 }
10778
10779 static void
10780 check_shared_dpll_state(struct drm_device *dev)
10781 {
10782         struct drm_i915_private *dev_priv = dev->dev_private;
10783         struct intel_crtc *crtc;
10784         struct intel_dpll_hw_state dpll_hw_state;
10785         int i;
10786
10787         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10788                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10789                 int enabled_crtcs = 0, active_crtcs = 0;
10790                 bool active;
10791
10792                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10793
10794                 DRM_DEBUG_KMS("%s\n", pll->name);
10795
10796                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10797
10798                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10799                      "more active pll users than references: %i vs %i\n",
10800                      pll->active, hweight32(pll->config.crtc_mask));
10801                 WARN(pll->active && !pll->on,
10802                      "pll in active use but not on in sw tracking\n");
10803                 WARN(pll->on && !pll->active,
10804                      "pll in on but not on in use in sw tracking\n");
10805                 WARN(pll->on != active,
10806                      "pll on state mismatch (expected %i, found %i)\n",
10807                      pll->on, active);
10808
10809                 for_each_intel_crtc(dev, crtc) {
10810                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10811                                 enabled_crtcs++;
10812                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10813                                 active_crtcs++;
10814                 }
10815                 WARN(pll->active != active_crtcs,
10816                      "pll active crtcs mismatch (expected %i, found %i)\n",
10817                      pll->active, active_crtcs);
10818                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10819                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10820                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10821
10822                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10823                                        sizeof(dpll_hw_state)),
10824                      "pll hw state mismatch\n");
10825         }
10826 }
10827
10828 void
10829 intel_modeset_check_state(struct drm_device *dev)
10830 {
10831         check_wm_state(dev);
10832         check_connector_state(dev);
10833         check_encoder_state(dev);
10834         check_crtc_state(dev);
10835         check_shared_dpll_state(dev);
10836 }
10837
10838 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10839                                      int dotclock)
10840 {
10841         /*
10842          * FDI already provided one idea for the dotclock.
10843          * Yell if the encoder disagrees.
10844          */
10845         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10846              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10847              pipe_config->adjusted_mode.crtc_clock, dotclock);
10848 }
10849
10850 static void update_scanline_offset(struct intel_crtc *crtc)
10851 {
10852         struct drm_device *dev = crtc->base.dev;
10853
10854         /*
10855          * The scanline counter increments at the leading edge of hsync.
10856          *
10857          * On most platforms it starts counting from vtotal-1 on the
10858          * first active line. That means the scanline counter value is
10859          * always one less than what we would expect. Ie. just after
10860          * start of vblank, which also occurs at start of hsync (on the
10861          * last active line), the scanline counter will read vblank_start-1.
10862          *
10863          * On gen2 the scanline counter starts counting from 1 instead
10864          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10865          * to keep the value positive), instead of adding one.
10866          *
10867          * On HSW+ the behaviour of the scanline counter depends on the output
10868          * type. For DP ports it behaves like most other platforms, but on HDMI
10869          * there's an extra 1 line difference. So we need to add two instead of
10870          * one to the value.
10871          */
10872         if (IS_GEN2(dev)) {
10873                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10874                 int vtotal;
10875
10876                 vtotal = mode->crtc_vtotal;
10877                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10878                         vtotal /= 2;
10879
10880                 crtc->scanline_offset = vtotal - 1;
10881         } else if (HAS_DDI(dev) &&
10882                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10883                 crtc->scanline_offset = 2;
10884         } else
10885                 crtc->scanline_offset = 1;
10886 }
10887
10888 static struct intel_crtc_config *
10889 intel_modeset_compute_config(struct drm_crtc *crtc,
10890                              struct drm_display_mode *mode,
10891                              struct drm_framebuffer *fb,
10892                              unsigned *modeset_pipes,
10893                              unsigned *prepare_pipes,
10894                              unsigned *disable_pipes)
10895 {
10896         struct intel_crtc_config *pipe_config = NULL;
10897
10898         intel_modeset_affected_pipes(crtc, modeset_pipes,
10899                                      prepare_pipes, disable_pipes);
10900
10901         if ((*modeset_pipes) == 0)
10902                 goto out;
10903
10904         /*
10905          * Note this needs changes when we start tracking multiple modes
10906          * and crtcs.  At that point we'll need to compute the whole config
10907          * (i.e. one pipe_config for each crtc) rather than just the one
10908          * for this crtc.
10909          */
10910         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10911         if (IS_ERR(pipe_config)) {
10912                 goto out;
10913         }
10914         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10915                                "[modeset]");
10916
10917 out:
10918         return pipe_config;
10919 }
10920
10921 static int __intel_set_mode(struct drm_crtc *crtc,
10922                             struct drm_display_mode *mode,
10923                             int x, int y, struct drm_framebuffer *fb,
10924                             struct intel_crtc_config *pipe_config,
10925                             unsigned modeset_pipes,
10926                             unsigned prepare_pipes,
10927                             unsigned disable_pipes)
10928 {
10929         struct drm_device *dev = crtc->dev;
10930         struct drm_i915_private *dev_priv = dev->dev_private;
10931         struct drm_display_mode *saved_mode;
10932         struct intel_crtc *intel_crtc;
10933         int ret = 0;
10934
10935         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10936         if (!saved_mode)
10937                 return -ENOMEM;
10938
10939         *saved_mode = crtc->mode;
10940
10941         if (modeset_pipes)
10942                 to_intel_crtc(crtc)->new_config = pipe_config;
10943
10944         /*
10945          * See if the config requires any additional preparation, e.g.
10946          * to adjust global state with pipes off.  We need to do this
10947          * here so we can get the modeset_pipe updated config for the new
10948          * mode set on this crtc.  For other crtcs we need to use the
10949          * adjusted_mode bits in the crtc directly.
10950          */
10951         if (IS_VALLEYVIEW(dev)) {
10952                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10953
10954                 /* may have added more to prepare_pipes than we should */
10955                 prepare_pipes &= ~disable_pipes;
10956         }
10957
10958         if (dev_priv->display.crtc_compute_clock) {
10959                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10960
10961                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10962                 if (ret)
10963                         goto done;
10964
10965                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10966                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10967                         if (ret) {
10968                                 intel_shared_dpll_abort_config(dev_priv);
10969                                 goto done;
10970                         }
10971                 }
10972         }
10973
10974         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10975                 intel_crtc_disable(&intel_crtc->base);
10976
10977         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10978                 if (intel_crtc->base.enabled)
10979                         dev_priv->display.crtc_disable(&intel_crtc->base);
10980         }
10981
10982         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10983          * to set it here already despite that we pass it down the callchain.
10984          *
10985          * Note we'll need to fix this up when we start tracking multiple
10986          * pipes; here we assume a single modeset_pipe and only track the
10987          * single crtc and mode.
10988          */
10989         if (modeset_pipes) {
10990                 crtc->mode = *mode;
10991                 /* mode_set/enable/disable functions rely on a correct pipe
10992                  * config. */
10993                 to_intel_crtc(crtc)->config = *pipe_config;
10994                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10995
10996                 /*
10997                  * Calculate and store various constants which
10998                  * are later needed by vblank and swap-completion
10999                  * timestamping. They are derived from true hwmode.
11000                  */
11001                 drm_calc_timestamping_constants(crtc,
11002                                                 &pipe_config->adjusted_mode);
11003         }
11004
11005         /* Only after disabling all output pipelines that will be changed can we
11006          * update the the output configuration. */
11007         intel_modeset_update_state(dev, prepare_pipes);
11008
11009         modeset_update_crtc_power_domains(dev);
11010
11011         /* Set up the DPLL and any encoders state that needs to adjust or depend
11012          * on the DPLL.
11013          */
11014         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11015                 struct drm_plane *primary = intel_crtc->base.primary;
11016                 int vdisplay, hdisplay;
11017
11018                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11019                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11020                                                    fb, 0, 0,
11021                                                    hdisplay, vdisplay,
11022                                                    x << 16, y << 16,
11023                                                    hdisplay << 16, vdisplay << 16);
11024         }
11025
11026         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11027         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11028                 update_scanline_offset(intel_crtc);
11029
11030                 dev_priv->display.crtc_enable(&intel_crtc->base);
11031         }
11032
11033         /* FIXME: add subpixel order */
11034 done:
11035         if (ret && crtc->enabled)
11036                 crtc->mode = *saved_mode;
11037
11038         kfree(pipe_config);
11039         kfree(saved_mode);
11040         return ret;
11041 }
11042
11043 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11044                                 struct drm_display_mode *mode,
11045                                 int x, int y, struct drm_framebuffer *fb,
11046                                 struct intel_crtc_config *pipe_config,
11047                                 unsigned modeset_pipes,
11048                                 unsigned prepare_pipes,
11049                                 unsigned disable_pipes)
11050 {
11051         int ret;
11052
11053         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11054                                prepare_pipes, disable_pipes);
11055
11056         if (ret == 0)
11057                 intel_modeset_check_state(crtc->dev);
11058
11059         return ret;
11060 }
11061
11062 static int intel_set_mode(struct drm_crtc *crtc,
11063                           struct drm_display_mode *mode,
11064                           int x, int y, struct drm_framebuffer *fb)
11065 {
11066         struct intel_crtc_config *pipe_config;
11067         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11068
11069         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11070                                                    &modeset_pipes,
11071                                                    &prepare_pipes,
11072                                                    &disable_pipes);
11073
11074         if (IS_ERR(pipe_config))
11075                 return PTR_ERR(pipe_config);
11076
11077         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11078                                     modeset_pipes, prepare_pipes,
11079                                     disable_pipes);
11080 }
11081
11082 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11083 {
11084         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11085 }
11086
11087 #undef for_each_intel_crtc_masked
11088
11089 static void intel_set_config_free(struct intel_set_config *config)
11090 {
11091         if (!config)
11092                 return;
11093
11094         kfree(config->save_connector_encoders);
11095         kfree(config->save_encoder_crtcs);
11096         kfree(config->save_crtc_enabled);
11097         kfree(config);
11098 }
11099
11100 static int intel_set_config_save_state(struct drm_device *dev,
11101                                        struct intel_set_config *config)
11102 {
11103         struct drm_crtc *crtc;
11104         struct drm_encoder *encoder;
11105         struct drm_connector *connector;
11106         int count;
11107
11108         config->save_crtc_enabled =
11109                 kcalloc(dev->mode_config.num_crtc,
11110                         sizeof(bool), GFP_KERNEL);
11111         if (!config->save_crtc_enabled)
11112                 return -ENOMEM;
11113
11114         config->save_encoder_crtcs =
11115                 kcalloc(dev->mode_config.num_encoder,
11116                         sizeof(struct drm_crtc *), GFP_KERNEL);
11117         if (!config->save_encoder_crtcs)
11118                 return -ENOMEM;
11119
11120         config->save_connector_encoders =
11121                 kcalloc(dev->mode_config.num_connector,
11122                         sizeof(struct drm_encoder *), GFP_KERNEL);
11123         if (!config->save_connector_encoders)
11124                 return -ENOMEM;
11125
11126         /* Copy data. Note that driver private data is not affected.
11127          * Should anything bad happen only the expected state is
11128          * restored, not the drivers personal bookkeeping.
11129          */
11130         count = 0;
11131         for_each_crtc(dev, crtc) {
11132                 config->save_crtc_enabled[count++] = crtc->enabled;
11133         }
11134
11135         count = 0;
11136         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11137                 config->save_encoder_crtcs[count++] = encoder->crtc;
11138         }
11139
11140         count = 0;
11141         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11142                 config->save_connector_encoders[count++] = connector->encoder;
11143         }
11144
11145         return 0;
11146 }
11147
11148 static void intel_set_config_restore_state(struct drm_device *dev,
11149                                            struct intel_set_config *config)
11150 {
11151         struct intel_crtc *crtc;
11152         struct intel_encoder *encoder;
11153         struct intel_connector *connector;
11154         int count;
11155
11156         count = 0;
11157         for_each_intel_crtc(dev, crtc) {
11158                 crtc->new_enabled = config->save_crtc_enabled[count++];
11159
11160                 if (crtc->new_enabled)
11161                         crtc->new_config = &crtc->config;
11162                 else
11163                         crtc->new_config = NULL;
11164         }
11165
11166         count = 0;
11167         for_each_intel_encoder(dev, encoder) {
11168                 encoder->new_crtc =
11169                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11170         }
11171
11172         count = 0;
11173         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11174                 connector->new_encoder =
11175                         to_intel_encoder(config->save_connector_encoders[count++]);
11176         }
11177 }
11178
11179 static bool
11180 is_crtc_connector_off(struct drm_mode_set *set)
11181 {
11182         int i;
11183
11184         if (set->num_connectors == 0)
11185                 return false;
11186
11187         if (WARN_ON(set->connectors == NULL))
11188                 return false;
11189
11190         for (i = 0; i < set->num_connectors; i++)
11191                 if (set->connectors[i]->encoder &&
11192                     set->connectors[i]->encoder->crtc == set->crtc &&
11193                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11194                         return true;
11195
11196         return false;
11197 }
11198
11199 static void
11200 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11201                                       struct intel_set_config *config)
11202 {
11203
11204         /* We should be able to check here if the fb has the same properties
11205          * and then just flip_or_move it */
11206         if (is_crtc_connector_off(set)) {
11207                 config->mode_changed = true;
11208         } else if (set->crtc->primary->fb != set->fb) {
11209                 /*
11210                  * If we have no fb, we can only flip as long as the crtc is
11211                  * active, otherwise we need a full mode set.  The crtc may
11212                  * be active if we've only disabled the primary plane, or
11213                  * in fastboot situations.
11214                  */
11215                 if (set->crtc->primary->fb == NULL) {
11216                         struct intel_crtc *intel_crtc =
11217                                 to_intel_crtc(set->crtc);
11218
11219                         if (intel_crtc->active) {
11220                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11221                                 config->fb_changed = true;
11222                         } else {
11223                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11224                                 config->mode_changed = true;
11225                         }
11226                 } else if (set->fb == NULL) {
11227                         config->mode_changed = true;
11228                 } else if (set->fb->pixel_format !=
11229                            set->crtc->primary->fb->pixel_format) {
11230                         config->mode_changed = true;
11231                 } else {
11232                         config->fb_changed = true;
11233                 }
11234         }
11235
11236         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11237                 config->fb_changed = true;
11238
11239         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11240                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11241                 drm_mode_debug_printmodeline(&set->crtc->mode);
11242                 drm_mode_debug_printmodeline(set->mode);
11243                 config->mode_changed = true;
11244         }
11245
11246         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11247                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11248 }
11249
11250 static int
11251 intel_modeset_stage_output_state(struct drm_device *dev,
11252                                  struct drm_mode_set *set,
11253                                  struct intel_set_config *config)
11254 {
11255         struct intel_connector *connector;
11256         struct intel_encoder *encoder;
11257         struct intel_crtc *crtc;
11258         int ro;
11259
11260         /* The upper layers ensure that we either disable a crtc or have a list
11261          * of connectors. For paranoia, double-check this. */
11262         WARN_ON(!set->fb && (set->num_connectors != 0));
11263         WARN_ON(set->fb && (set->num_connectors == 0));
11264
11265         list_for_each_entry(connector, &dev->mode_config.connector_list,
11266                             base.head) {
11267                 /* Otherwise traverse passed in connector list and get encoders
11268                  * for them. */
11269                 for (ro = 0; ro < set->num_connectors; ro++) {
11270                         if (set->connectors[ro] == &connector->base) {
11271                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11272                                 break;
11273                         }
11274                 }
11275
11276                 /* If we disable the crtc, disable all its connectors. Also, if
11277                  * the connector is on the changing crtc but not on the new
11278                  * connector list, disable it. */
11279                 if ((!set->fb || ro == set->num_connectors) &&
11280                     connector->base.encoder &&
11281                     connector->base.encoder->crtc == set->crtc) {
11282                         connector->new_encoder = NULL;
11283
11284                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11285                                 connector->base.base.id,
11286                                 connector->base.name);
11287                 }
11288
11289
11290                 if (&connector->new_encoder->base != connector->base.encoder) {
11291                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11292                         config->mode_changed = true;
11293                 }
11294         }
11295         /* connector->new_encoder is now updated for all connectors. */
11296
11297         /* Update crtc of enabled connectors. */
11298         list_for_each_entry(connector, &dev->mode_config.connector_list,
11299                             base.head) {
11300                 struct drm_crtc *new_crtc;
11301
11302                 if (!connector->new_encoder)
11303                         continue;
11304
11305                 new_crtc = connector->new_encoder->base.crtc;
11306
11307                 for (ro = 0; ro < set->num_connectors; ro++) {
11308                         if (set->connectors[ro] == &connector->base)
11309                                 new_crtc = set->crtc;
11310                 }
11311
11312                 /* Make sure the new CRTC will work with the encoder */
11313                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11314                                          new_crtc)) {
11315                         return -EINVAL;
11316                 }
11317                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11318
11319                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11320                         connector->base.base.id,
11321                         connector->base.name,
11322                         new_crtc->base.id);
11323         }
11324
11325         /* Check for any encoders that needs to be disabled. */
11326         for_each_intel_encoder(dev, encoder) {
11327                 int num_connectors = 0;
11328                 list_for_each_entry(connector,
11329                                     &dev->mode_config.connector_list,
11330                                     base.head) {
11331                         if (connector->new_encoder == encoder) {
11332                                 WARN_ON(!connector->new_encoder->new_crtc);
11333                                 num_connectors++;
11334                         }
11335                 }
11336
11337                 if (num_connectors == 0)
11338                         encoder->new_crtc = NULL;
11339                 else if (num_connectors > 1)
11340                         return -EINVAL;
11341
11342                 /* Only now check for crtc changes so we don't miss encoders
11343                  * that will be disabled. */
11344                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11345                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11346                         config->mode_changed = true;
11347                 }
11348         }
11349         /* Now we've also updated encoder->new_crtc for all encoders. */
11350         list_for_each_entry(connector, &dev->mode_config.connector_list,
11351                             base.head) {
11352                 if (connector->new_encoder)
11353                         if (connector->new_encoder != connector->encoder)
11354                                 connector->encoder = connector->new_encoder;
11355         }
11356         for_each_intel_crtc(dev, crtc) {
11357                 crtc->new_enabled = false;
11358
11359                 for_each_intel_encoder(dev, encoder) {
11360                         if (encoder->new_crtc == crtc) {
11361                                 crtc->new_enabled = true;
11362                                 break;
11363                         }
11364                 }
11365
11366                 if (crtc->new_enabled != crtc->base.enabled) {
11367                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11368                                       crtc->new_enabled ? "en" : "dis");
11369                         config->mode_changed = true;
11370                 }
11371
11372                 if (crtc->new_enabled)
11373                         crtc->new_config = &crtc->config;
11374                 else
11375                         crtc->new_config = NULL;
11376         }
11377
11378         return 0;
11379 }
11380
11381 static void disable_crtc_nofb(struct intel_crtc *crtc)
11382 {
11383         struct drm_device *dev = crtc->base.dev;
11384         struct intel_encoder *encoder;
11385         struct intel_connector *connector;
11386
11387         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11388                       pipe_name(crtc->pipe));
11389
11390         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11391                 if (connector->new_encoder &&
11392                     connector->new_encoder->new_crtc == crtc)
11393                         connector->new_encoder = NULL;
11394         }
11395
11396         for_each_intel_encoder(dev, encoder) {
11397                 if (encoder->new_crtc == crtc)
11398                         encoder->new_crtc = NULL;
11399         }
11400
11401         crtc->new_enabled = false;
11402         crtc->new_config = NULL;
11403 }
11404
11405 static int intel_crtc_set_config(struct drm_mode_set *set)
11406 {
11407         struct drm_device *dev;
11408         struct drm_mode_set save_set;
11409         struct intel_set_config *config;
11410         struct intel_crtc_config *pipe_config;
11411         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11412         int ret;
11413
11414         BUG_ON(!set);
11415         BUG_ON(!set->crtc);
11416         BUG_ON(!set->crtc->helper_private);
11417
11418         /* Enforce sane interface api - has been abused by the fb helper. */
11419         BUG_ON(!set->mode && set->fb);
11420         BUG_ON(set->fb && set->num_connectors == 0);
11421
11422         if (set->fb) {
11423                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11424                                 set->crtc->base.id, set->fb->base.id,
11425                                 (int)set->num_connectors, set->x, set->y);
11426         } else {
11427                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11428         }
11429
11430         dev = set->crtc->dev;
11431
11432         ret = -ENOMEM;
11433         config = kzalloc(sizeof(*config), GFP_KERNEL);
11434         if (!config)
11435                 goto out_config;
11436
11437         ret = intel_set_config_save_state(dev, config);
11438         if (ret)
11439                 goto out_config;
11440
11441         save_set.crtc = set->crtc;
11442         save_set.mode = &set->crtc->mode;
11443         save_set.x = set->crtc->x;
11444         save_set.y = set->crtc->y;
11445         save_set.fb = set->crtc->primary->fb;
11446
11447         /* Compute whether we need a full modeset, only an fb base update or no
11448          * change at all. In the future we might also check whether only the
11449          * mode changed, e.g. for LVDS where we only change the panel fitter in
11450          * such cases. */
11451         intel_set_config_compute_mode_changes(set, config);
11452
11453         ret = intel_modeset_stage_output_state(dev, set, config);
11454         if (ret)
11455                 goto fail;
11456
11457         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11458                                                    set->fb,
11459                                                    &modeset_pipes,
11460                                                    &prepare_pipes,
11461                                                    &disable_pipes);
11462         if (IS_ERR(pipe_config)) {
11463                 ret = PTR_ERR(pipe_config);
11464                 goto fail;
11465         } else if (pipe_config) {
11466                 if (pipe_config->has_audio !=
11467                     to_intel_crtc(set->crtc)->config.has_audio)
11468                         config->mode_changed = true;
11469
11470                 /* Force mode sets for any infoframe stuff */
11471                 if (pipe_config->has_infoframe ||
11472                     to_intel_crtc(set->crtc)->config.has_infoframe)
11473                         config->mode_changed = true;
11474         }
11475
11476         /* set_mode will free it in the mode_changed case */
11477         if (!config->mode_changed)
11478                 kfree(pipe_config);
11479
11480         intel_update_pipe_size(to_intel_crtc(set->crtc));
11481
11482         if (config->mode_changed) {
11483                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11484                                            set->x, set->y, set->fb, pipe_config,
11485                                            modeset_pipes, prepare_pipes,
11486                                            disable_pipes);
11487         } else if (config->fb_changed) {
11488                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11489                 struct drm_plane *primary = set->crtc->primary;
11490                 int vdisplay, hdisplay;
11491
11492                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11493                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11494                                                    0, 0, hdisplay, vdisplay,
11495                                                    set->x << 16, set->y << 16,
11496                                                    hdisplay << 16, vdisplay << 16);
11497
11498                 /*
11499                  * We need to make sure the primary plane is re-enabled if it
11500                  * has previously been turned off.
11501                  */
11502                 if (!intel_crtc->primary_enabled && ret == 0) {
11503                         WARN_ON(!intel_crtc->active);
11504                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11505                 }
11506
11507                 /*
11508                  * In the fastboot case this may be our only check of the
11509                  * state after boot.  It would be better to only do it on
11510                  * the first update, but we don't have a nice way of doing that
11511                  * (and really, set_config isn't used much for high freq page
11512                  * flipping, so increasing its cost here shouldn't be a big
11513                  * deal).
11514                  */
11515                 if (i915.fastboot && ret == 0)
11516                         intel_modeset_check_state(set->crtc->dev);
11517         }
11518
11519         if (ret) {
11520                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11521                               set->crtc->base.id, ret);
11522 fail:
11523                 intel_set_config_restore_state(dev, config);
11524
11525                 /*
11526                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11527                  * force the pipe off to avoid oopsing in the modeset code
11528                  * due to fb==NULL. This should only happen during boot since
11529                  * we don't yet reconstruct the FB from the hardware state.
11530                  */
11531                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11532                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11533
11534                 /* Try to restore the config */
11535                 if (config->mode_changed &&
11536                     intel_set_mode(save_set.crtc, save_set.mode,
11537                                    save_set.x, save_set.y, save_set.fb))
11538                         DRM_ERROR("failed to restore config after modeset failure\n");
11539         }
11540
11541 out_config:
11542         intel_set_config_free(config);
11543         return ret;
11544 }
11545
11546 static const struct drm_crtc_funcs intel_crtc_funcs = {
11547         .gamma_set = intel_crtc_gamma_set,
11548         .set_config = intel_crtc_set_config,
11549         .destroy = intel_crtc_destroy,
11550         .page_flip = intel_crtc_page_flip,
11551 };
11552
11553 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11554                                       struct intel_shared_dpll *pll,
11555                                       struct intel_dpll_hw_state *hw_state)
11556 {
11557         uint32_t val;
11558
11559         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11560                 return false;
11561
11562         val = I915_READ(PCH_DPLL(pll->id));
11563         hw_state->dpll = val;
11564         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11565         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11566
11567         return val & DPLL_VCO_ENABLE;
11568 }
11569
11570 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11571                                   struct intel_shared_dpll *pll)
11572 {
11573         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11574         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11575 }
11576
11577 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11578                                 struct intel_shared_dpll *pll)
11579 {
11580         /* PCH refclock must be enabled first */
11581         ibx_assert_pch_refclk_enabled(dev_priv);
11582
11583         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11584
11585         /* Wait for the clocks to stabilize. */
11586         POSTING_READ(PCH_DPLL(pll->id));
11587         udelay(150);
11588
11589         /* The pixel multiplier can only be updated once the
11590          * DPLL is enabled and the clocks are stable.
11591          *
11592          * So write it again.
11593          */
11594         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11595         POSTING_READ(PCH_DPLL(pll->id));
11596         udelay(200);
11597 }
11598
11599 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11600                                  struct intel_shared_dpll *pll)
11601 {
11602         struct drm_device *dev = dev_priv->dev;
11603         struct intel_crtc *crtc;
11604
11605         /* Make sure no transcoder isn't still depending on us. */
11606         for_each_intel_crtc(dev, crtc) {
11607                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11608                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11609         }
11610
11611         I915_WRITE(PCH_DPLL(pll->id), 0);
11612         POSTING_READ(PCH_DPLL(pll->id));
11613         udelay(200);
11614 }
11615
11616 static char *ibx_pch_dpll_names[] = {
11617         "PCH DPLL A",
11618         "PCH DPLL B",
11619 };
11620
11621 static void ibx_pch_dpll_init(struct drm_device *dev)
11622 {
11623         struct drm_i915_private *dev_priv = dev->dev_private;
11624         int i;
11625
11626         dev_priv->num_shared_dpll = 2;
11627
11628         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11629                 dev_priv->shared_dplls[i].id = i;
11630                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11631                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11632                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11633                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11634                 dev_priv->shared_dplls[i].get_hw_state =
11635                         ibx_pch_dpll_get_hw_state;
11636         }
11637 }
11638
11639 static void intel_shared_dpll_init(struct drm_device *dev)
11640 {
11641         struct drm_i915_private *dev_priv = dev->dev_private;
11642
11643         if (HAS_DDI(dev))
11644                 intel_ddi_pll_init(dev);
11645         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11646                 ibx_pch_dpll_init(dev);
11647         else
11648                 dev_priv->num_shared_dpll = 0;
11649
11650         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11651 }
11652
11653 /**
11654  * intel_prepare_plane_fb - Prepare fb for usage on plane
11655  * @plane: drm plane to prepare for
11656  * @fb: framebuffer to prepare for presentation
11657  *
11658  * Prepares a framebuffer for usage on a display plane.  Generally this
11659  * involves pinning the underlying object and updating the frontbuffer tracking
11660  * bits.  Some older platforms need special physical address handling for
11661  * cursor planes.
11662  *
11663  * Returns 0 on success, negative error code on failure.
11664  */
11665 int
11666 intel_prepare_plane_fb(struct drm_plane *plane,
11667                        struct drm_framebuffer *fb)
11668 {
11669         struct drm_device *dev = plane->dev;
11670         struct intel_plane *intel_plane = to_intel_plane(plane);
11671         enum pipe pipe = intel_plane->pipe;
11672         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11673         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11674         unsigned frontbuffer_bits = 0;
11675         int ret = 0;
11676
11677         if (WARN_ON(fb == plane->fb || !obj))
11678                 return 0;
11679
11680         switch (plane->type) {
11681         case DRM_PLANE_TYPE_PRIMARY:
11682                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11683                 break;
11684         case DRM_PLANE_TYPE_CURSOR:
11685                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11686                 break;
11687         case DRM_PLANE_TYPE_OVERLAY:
11688                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11689                 break;
11690         }
11691
11692         mutex_lock(&dev->struct_mutex);
11693
11694         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11695             INTEL_INFO(dev)->cursor_needs_physical) {
11696                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11697                 ret = i915_gem_object_attach_phys(obj, align);
11698                 if (ret)
11699                         DRM_DEBUG_KMS("failed to attach phys object\n");
11700         } else {
11701                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11702         }
11703
11704         if (ret == 0)
11705                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11706
11707         mutex_unlock(&dev->struct_mutex);
11708
11709         return ret;
11710 }
11711
11712 /**
11713  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11714  * @plane: drm plane to clean up for
11715  * @fb: old framebuffer that was on plane
11716  *
11717  * Cleans up a framebuffer that has just been removed from a plane.
11718  */
11719 void
11720 intel_cleanup_plane_fb(struct drm_plane *plane,
11721                        struct drm_framebuffer *fb)
11722 {
11723         struct drm_device *dev = plane->dev;
11724         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11725
11726         if (WARN_ON(!obj))
11727                 return;
11728
11729         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11730             !INTEL_INFO(dev)->cursor_needs_physical) {
11731                 mutex_lock(&dev->struct_mutex);
11732                 intel_unpin_fb_obj(obj);
11733                 mutex_unlock(&dev->struct_mutex);
11734         }
11735 }
11736
11737 static int
11738 intel_check_primary_plane(struct drm_plane *plane,
11739                           struct intel_plane_state *state)
11740 {
11741         struct drm_crtc *crtc = state->base.crtc;
11742         struct drm_framebuffer *fb = state->base.fb;
11743         struct drm_rect *dest = &state->dst;
11744         struct drm_rect *src = &state->src;
11745         const struct drm_rect *clip = &state->clip;
11746         int ret;
11747
11748         ret = drm_plane_helper_check_update(plane, crtc, fb,
11749                                             src, dest, clip,
11750                                             DRM_PLANE_HELPER_NO_SCALING,
11751                                             DRM_PLANE_HELPER_NO_SCALING,
11752                                             false, true, &state->visible);
11753         if (ret)
11754                 return ret;
11755
11756         intel_crtc_wait_for_pending_flips(crtc);
11757         if (intel_crtc_has_pending_flip(crtc)) {
11758                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11759                 return -EBUSY;
11760         }
11761
11762         return 0;
11763 }
11764
11765 static void
11766 intel_commit_primary_plane(struct drm_plane *plane,
11767                            struct intel_plane_state *state)
11768 {
11769         struct drm_crtc *crtc = state->base.crtc;
11770         struct drm_framebuffer *fb = state->base.fb;
11771         struct drm_device *dev = plane->dev;
11772         struct drm_i915_private *dev_priv = dev->dev_private;
11773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11774         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11775         struct intel_plane *intel_plane = to_intel_plane(plane);
11776         struct drm_rect *src = &state->src;
11777         enum pipe pipe = intel_plane->pipe;
11778
11779         if (!fb) {
11780                 /*
11781                  * 'prepare' is never called when plane is being disabled, so
11782                  * we need to handle frontbuffer tracking here
11783                  */
11784                 mutex_lock(&dev->struct_mutex);
11785                 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11786                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
11787                 mutex_unlock(&dev->struct_mutex);
11788         }
11789
11790         plane->fb = fb;
11791         crtc->x = src->x1 >> 16;
11792         crtc->y = src->y1 >> 16;
11793
11794         intel_plane->crtc_x = state->orig_dst.x1;
11795         intel_plane->crtc_y = state->orig_dst.y1;
11796         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11797         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11798         intel_plane->src_x = state->orig_src.x1;
11799         intel_plane->src_y = state->orig_src.y1;
11800         intel_plane->src_w = drm_rect_width(&state->orig_src);
11801         intel_plane->src_h = drm_rect_height(&state->orig_src);
11802         intel_plane->obj = obj;
11803
11804         if (intel_crtc->active) {
11805                 /*
11806                  * FBC does not work on some platforms for rotated
11807                  * planes, so disable it when rotation is not 0 and
11808                  * update it when rotation is set back to 0.
11809                  *
11810                  * FIXME: This is redundant with the fbc update done in
11811                  * the primary plane enable function except that that
11812                  * one is done too late. We eventually need to unify
11813                  * this.
11814                  */
11815                 if (intel_crtc->primary_enabled &&
11816                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11817                     dev_priv->fbc.plane == intel_crtc->plane &&
11818                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11819                         intel_disable_fbc(dev);
11820                 }
11821
11822                 if (state->visible) {
11823                         bool was_enabled = intel_crtc->primary_enabled;
11824
11825                         /* FIXME: kill this fastboot hack */
11826                         intel_update_pipe_size(intel_crtc);
11827
11828                         intel_crtc->primary_enabled = true;
11829
11830                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11831                                         crtc->x, crtc->y);
11832
11833                         /*
11834                          * BDW signals flip done immediately if the plane
11835                          * is disabled, even if the plane enable is already
11836                          * armed to occur at the next vblank :(
11837                          */
11838                         if (IS_BROADWELL(dev) && !was_enabled)
11839                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11840                 } else {
11841                         /*
11842                          * If clipping results in a non-visible primary plane,
11843                          * we'll disable the primary plane.  Note that this is
11844                          * a bit different than what happens if userspace
11845                          * explicitly disables the plane by passing fb=0
11846                          * because plane->fb still gets set and pinned.
11847                          */
11848                         intel_disable_primary_hw_plane(plane, crtc);
11849                 }
11850
11851                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11852
11853                 mutex_lock(&dev->struct_mutex);
11854                 intel_update_fbc(dev);
11855                 mutex_unlock(&dev->struct_mutex);
11856         }
11857 }
11858
11859 int
11860 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
11861                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11862                    unsigned int crtc_w, unsigned int crtc_h,
11863                    uint32_t src_x, uint32_t src_y,
11864                    uint32_t src_w, uint32_t src_h)
11865 {
11866         struct drm_device *dev = plane->dev;
11867         struct drm_framebuffer *old_fb = plane->fb;
11868         struct intel_plane_state state;
11869         struct intel_plane *intel_plane = to_intel_plane(plane);
11870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11871         int ret;
11872
11873         state.base.crtc = crtc ? crtc : plane->crtc;
11874         state.base.fb = fb;
11875
11876         /* sample coordinates in 16.16 fixed point */
11877         state.src.x1 = src_x;
11878         state.src.x2 = src_x + src_w;
11879         state.src.y1 = src_y;
11880         state.src.y2 = src_y + src_h;
11881
11882         /* integer pixels */
11883         state.dst.x1 = crtc_x;
11884         state.dst.x2 = crtc_x + crtc_w;
11885         state.dst.y1 = crtc_y;
11886         state.dst.y2 = crtc_y + crtc_h;
11887
11888         state.clip.x1 = 0;
11889         state.clip.y1 = 0;
11890         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11891         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11892
11893         state.orig_src = state.src;
11894         state.orig_dst = state.dst;
11895
11896         ret = intel_plane->check_plane(plane, &state);
11897         if (ret)
11898                 return ret;
11899
11900         if (fb != old_fb && fb) {
11901                 ret = intel_prepare_plane_fb(plane, fb);
11902                 if (ret)
11903                         return ret;
11904         }
11905
11906         intel_plane->commit_plane(plane, &state);
11907
11908         if (fb != old_fb && old_fb) {
11909                 if (intel_crtc->active)
11910                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11911                 intel_cleanup_plane_fb(plane, old_fb);
11912         }
11913
11914         plane->fb = fb;
11915
11916         return 0;
11917 }
11918
11919 /**
11920  * intel_disable_plane - disable a plane
11921  * @plane: plane to disable
11922  *
11923  * General disable handler for all plane types.
11924  */
11925 int
11926 intel_disable_plane(struct drm_plane *plane)
11927 {
11928         if (!plane->fb)
11929                 return 0;
11930
11931         if (WARN_ON(!plane->crtc))
11932                 return -EINVAL;
11933
11934         return plane->funcs->update_plane(plane, plane->crtc, NULL,
11935                                           0, 0, 0, 0, 0, 0, 0, 0);
11936 }
11937
11938 /* Common destruction function for both primary and cursor planes */
11939 static void intel_plane_destroy(struct drm_plane *plane)
11940 {
11941         struct intel_plane *intel_plane = to_intel_plane(plane);
11942         drm_plane_cleanup(plane);
11943         kfree(intel_plane);
11944 }
11945
11946 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11947         .update_plane = intel_update_plane,
11948         .disable_plane = intel_disable_plane,
11949         .destroy = intel_plane_destroy,
11950         .set_property = intel_plane_set_property
11951 };
11952
11953 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11954                                                     int pipe)
11955 {
11956         struct intel_plane *primary;
11957         const uint32_t *intel_primary_formats;
11958         int num_formats;
11959
11960         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11961         if (primary == NULL)
11962                 return NULL;
11963
11964         primary->can_scale = false;
11965         primary->max_downscale = 1;
11966         primary->pipe = pipe;
11967         primary->plane = pipe;
11968         primary->rotation = BIT(DRM_ROTATE_0);
11969         primary->check_plane = intel_check_primary_plane;
11970         primary->commit_plane = intel_commit_primary_plane;
11971         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11972                 primary->plane = !pipe;
11973
11974         if (INTEL_INFO(dev)->gen <= 3) {
11975                 intel_primary_formats = intel_primary_formats_gen2;
11976                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11977         } else {
11978                 intel_primary_formats = intel_primary_formats_gen4;
11979                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11980         }
11981
11982         drm_universal_plane_init(dev, &primary->base, 0,
11983                                  &intel_primary_plane_funcs,
11984                                  intel_primary_formats, num_formats,
11985                                  DRM_PLANE_TYPE_PRIMARY);
11986
11987         if (INTEL_INFO(dev)->gen >= 4) {
11988                 if (!dev->mode_config.rotation_property)
11989                         dev->mode_config.rotation_property =
11990                                 drm_mode_create_rotation_property(dev,
11991                                                         BIT(DRM_ROTATE_0) |
11992                                                         BIT(DRM_ROTATE_180));
11993                 if (dev->mode_config.rotation_property)
11994                         drm_object_attach_property(&primary->base.base,
11995                                 dev->mode_config.rotation_property,
11996                                 primary->rotation);
11997         }
11998
11999         return &primary->base;
12000 }
12001
12002 static int
12003 intel_check_cursor_plane(struct drm_plane *plane,
12004                          struct intel_plane_state *state)
12005 {
12006         struct drm_crtc *crtc = state->base.crtc;
12007         struct drm_device *dev = crtc->dev;
12008         struct drm_framebuffer *fb = state->base.fb;
12009         struct drm_rect *dest = &state->dst;
12010         struct drm_rect *src = &state->src;
12011         const struct drm_rect *clip = &state->clip;
12012         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12013         int crtc_w, crtc_h;
12014         unsigned stride;
12015         int ret;
12016
12017         ret = drm_plane_helper_check_update(plane, crtc, fb,
12018                                             src, dest, clip,
12019                                             DRM_PLANE_HELPER_NO_SCALING,
12020                                             DRM_PLANE_HELPER_NO_SCALING,
12021                                             true, true, &state->visible);
12022         if (ret)
12023                 return ret;
12024
12025
12026         /* if we want to turn off the cursor ignore width and height */
12027         if (!obj)
12028                 return 0;
12029
12030         /* Check for which cursor types we support */
12031         crtc_w = drm_rect_width(&state->orig_dst);
12032         crtc_h = drm_rect_height(&state->orig_dst);
12033         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
12034                 DRM_DEBUG("Cursor dimension not supported\n");
12035                 return -EINVAL;
12036         }
12037
12038         stride = roundup_pow_of_two(crtc_w) * 4;
12039         if (obj->base.size < stride * crtc_h) {
12040                 DRM_DEBUG_KMS("buffer is too small\n");
12041                 return -ENOMEM;
12042         }
12043
12044         if (fb == crtc->cursor->fb)
12045                 return 0;
12046
12047         /* we only need to pin inside GTT if cursor is non-phy */
12048         mutex_lock(&dev->struct_mutex);
12049         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12050                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12051                 ret = -EINVAL;
12052         }
12053         mutex_unlock(&dev->struct_mutex);
12054
12055         return ret;
12056 }
12057
12058 static void
12059 intel_commit_cursor_plane(struct drm_plane *plane,
12060                           struct intel_plane_state *state)
12061 {
12062         struct drm_crtc *crtc = state->base.crtc;
12063         struct drm_device *dev = crtc->dev;
12064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12065         struct intel_plane *intel_plane = to_intel_plane(plane);
12066         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12067         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12068         enum pipe pipe = intel_crtc->pipe;
12069         unsigned old_width;
12070         uint32_t addr;
12071
12072         plane->fb = state->base.fb;
12073         crtc->cursor_x = state->orig_dst.x1;
12074         crtc->cursor_y = state->orig_dst.y1;
12075
12076         intel_plane->crtc_x = state->orig_dst.x1;
12077         intel_plane->crtc_y = state->orig_dst.y1;
12078         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12079         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12080         intel_plane->src_x = state->orig_src.x1;
12081         intel_plane->src_y = state->orig_src.y1;
12082         intel_plane->src_w = drm_rect_width(&state->orig_src);
12083         intel_plane->src_h = drm_rect_height(&state->orig_src);
12084         intel_plane->obj = obj;
12085
12086         if (intel_crtc->cursor_bo == obj)
12087                 goto update;
12088
12089         /*
12090          * 'prepare' is only called when fb != NULL; we still need to update
12091          * frontbuffer tracking for the 'disable' case here.
12092          */
12093         if (!obj) {
12094                 mutex_lock(&dev->struct_mutex);
12095                 i915_gem_track_fb(old_obj, NULL,
12096                                   INTEL_FRONTBUFFER_CURSOR(pipe));
12097                 mutex_unlock(&dev->struct_mutex);
12098         }
12099
12100         if (!obj)
12101                 addr = 0;
12102         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12103                 addr = i915_gem_obj_ggtt_offset(obj);
12104         else
12105                 addr = obj->phys_handle->busaddr;
12106
12107         intel_crtc->cursor_addr = addr;
12108         intel_crtc->cursor_bo = obj;
12109 update:
12110         old_width = intel_crtc->cursor_width;
12111
12112         intel_crtc->cursor_width = drm_rect_width(&state->orig_dst);
12113         intel_crtc->cursor_height = drm_rect_height(&state->orig_dst);
12114
12115         if (intel_crtc->active) {
12116                 if (old_width != intel_crtc->cursor_width)
12117                         intel_update_watermarks(crtc);
12118                 intel_crtc_update_cursor(crtc, state->visible);
12119
12120                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
12121         }
12122 }
12123
12124 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12125         .update_plane = intel_update_plane,
12126         .disable_plane = intel_disable_plane,
12127         .destroy = intel_plane_destroy,
12128         .set_property = intel_plane_set_property,
12129 };
12130
12131 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12132                                                    int pipe)
12133 {
12134         struct intel_plane *cursor;
12135
12136         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12137         if (cursor == NULL)
12138                 return NULL;
12139
12140         cursor->can_scale = false;
12141         cursor->max_downscale = 1;
12142         cursor->pipe = pipe;
12143         cursor->plane = pipe;
12144         cursor->rotation = BIT(DRM_ROTATE_0);
12145         cursor->check_plane = intel_check_cursor_plane;
12146         cursor->commit_plane = intel_commit_cursor_plane;
12147
12148         drm_universal_plane_init(dev, &cursor->base, 0,
12149                                  &intel_cursor_plane_funcs,
12150                                  intel_cursor_formats,
12151                                  ARRAY_SIZE(intel_cursor_formats),
12152                                  DRM_PLANE_TYPE_CURSOR);
12153
12154         if (INTEL_INFO(dev)->gen >= 4) {
12155                 if (!dev->mode_config.rotation_property)
12156                         dev->mode_config.rotation_property =
12157                                 drm_mode_create_rotation_property(dev,
12158                                                         BIT(DRM_ROTATE_0) |
12159                                                         BIT(DRM_ROTATE_180));
12160                 if (dev->mode_config.rotation_property)
12161                         drm_object_attach_property(&cursor->base.base,
12162                                 dev->mode_config.rotation_property,
12163                                 cursor->rotation);
12164         }
12165
12166         return &cursor->base;
12167 }
12168
12169 static void intel_crtc_init(struct drm_device *dev, int pipe)
12170 {
12171         struct drm_i915_private *dev_priv = dev->dev_private;
12172         struct intel_crtc *intel_crtc;
12173         struct drm_plane *primary = NULL;
12174         struct drm_plane *cursor = NULL;
12175         int i, ret;
12176
12177         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12178         if (intel_crtc == NULL)
12179                 return;
12180
12181         primary = intel_primary_plane_create(dev, pipe);
12182         if (!primary)
12183                 goto fail;
12184
12185         cursor = intel_cursor_plane_create(dev, pipe);
12186         if (!cursor)
12187                 goto fail;
12188
12189         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12190                                         cursor, &intel_crtc_funcs);
12191         if (ret)
12192                 goto fail;
12193
12194         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12195         for (i = 0; i < 256; i++) {
12196                 intel_crtc->lut_r[i] = i;
12197                 intel_crtc->lut_g[i] = i;
12198                 intel_crtc->lut_b[i] = i;
12199         }
12200
12201         /*
12202          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12203          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12204          */
12205         intel_crtc->pipe = pipe;
12206         intel_crtc->plane = pipe;
12207         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12208                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12209                 intel_crtc->plane = !pipe;
12210         }
12211
12212         intel_crtc->cursor_base = ~0;
12213         intel_crtc->cursor_cntl = ~0;
12214         intel_crtc->cursor_size = ~0;
12215
12216         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12217                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12218         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12219         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12220
12221         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12222
12223         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12224
12225         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12226         return;
12227
12228 fail:
12229         if (primary)
12230                 drm_plane_cleanup(primary);
12231         if (cursor)
12232                 drm_plane_cleanup(cursor);
12233         kfree(intel_crtc);
12234 }
12235
12236 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12237 {
12238         struct drm_encoder *encoder = connector->base.encoder;
12239         struct drm_device *dev = connector->base.dev;
12240
12241         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12242
12243         if (!encoder || WARN_ON(!encoder->crtc))
12244                 return INVALID_PIPE;
12245
12246         return to_intel_crtc(encoder->crtc)->pipe;
12247 }
12248
12249 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12250                                 struct drm_file *file)
12251 {
12252         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12253         struct drm_crtc *drmmode_crtc;
12254         struct intel_crtc *crtc;
12255
12256         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12257                 return -ENODEV;
12258
12259         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12260
12261         if (!drmmode_crtc) {
12262                 DRM_ERROR("no such CRTC id\n");
12263                 return -ENOENT;
12264         }
12265
12266         crtc = to_intel_crtc(drmmode_crtc);
12267         pipe_from_crtc_id->pipe = crtc->pipe;
12268
12269         return 0;
12270 }
12271
12272 static int intel_encoder_clones(struct intel_encoder *encoder)
12273 {
12274         struct drm_device *dev = encoder->base.dev;
12275         struct intel_encoder *source_encoder;
12276         int index_mask = 0;
12277         int entry = 0;
12278
12279         for_each_intel_encoder(dev, source_encoder) {
12280                 if (encoders_cloneable(encoder, source_encoder))
12281                         index_mask |= (1 << entry);
12282
12283                 entry++;
12284         }
12285
12286         return index_mask;
12287 }
12288
12289 static bool has_edp_a(struct drm_device *dev)
12290 {
12291         struct drm_i915_private *dev_priv = dev->dev_private;
12292
12293         if (!IS_MOBILE(dev))
12294                 return false;
12295
12296         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12297                 return false;
12298
12299         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12300                 return false;
12301
12302         return true;
12303 }
12304
12305 static bool intel_crt_present(struct drm_device *dev)
12306 {
12307         struct drm_i915_private *dev_priv = dev->dev_private;
12308
12309         if (INTEL_INFO(dev)->gen >= 9)
12310                 return false;
12311
12312         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12313                 return false;
12314
12315         if (IS_CHERRYVIEW(dev))
12316                 return false;
12317
12318         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12319                 return false;
12320
12321         return true;
12322 }
12323
12324 static void intel_setup_outputs(struct drm_device *dev)
12325 {
12326         struct drm_i915_private *dev_priv = dev->dev_private;
12327         struct intel_encoder *encoder;
12328         bool dpd_is_edp = false;
12329
12330         intel_lvds_init(dev);
12331
12332         if (intel_crt_present(dev))
12333                 intel_crt_init(dev);
12334
12335         if (HAS_DDI(dev)) {
12336                 int found;
12337
12338                 /* Haswell uses DDI functions to detect digital outputs */
12339                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12340                 /* DDI A only supports eDP */
12341                 if (found)
12342                         intel_ddi_init(dev, PORT_A);
12343
12344                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12345                  * register */
12346                 found = I915_READ(SFUSE_STRAP);
12347
12348                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12349                         intel_ddi_init(dev, PORT_B);
12350                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12351                         intel_ddi_init(dev, PORT_C);
12352                 if (found & SFUSE_STRAP_DDID_DETECTED)
12353                         intel_ddi_init(dev, PORT_D);
12354         } else if (HAS_PCH_SPLIT(dev)) {
12355                 int found;
12356                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12357
12358                 if (has_edp_a(dev))
12359                         intel_dp_init(dev, DP_A, PORT_A);
12360
12361                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12362                         /* PCH SDVOB multiplex with HDMIB */
12363                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12364                         if (!found)
12365                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12366                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12367                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12368                 }
12369
12370                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12371                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12372
12373                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12374                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12375
12376                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12377                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12378
12379                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12380                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12381         } else if (IS_VALLEYVIEW(dev)) {
12382                 /*
12383                  * The DP_DETECTED bit is the latched state of the DDC
12384                  * SDA pin at boot. However since eDP doesn't require DDC
12385                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12386                  * eDP ports may have been muxed to an alternate function.
12387                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12388                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12389                  * detect eDP ports.
12390                  */
12391                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12392                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12393                                         PORT_B);
12394                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12395                     intel_dp_is_edp(dev, PORT_B))
12396                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12397
12398                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12399                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12400                                         PORT_C);
12401                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12402                     intel_dp_is_edp(dev, PORT_C))
12403                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12404
12405                 if (IS_CHERRYVIEW(dev)) {
12406                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12407                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12408                                                 PORT_D);
12409                         /* eDP not supported on port D, so don't check VBT */
12410                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12411                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12412                 }
12413
12414                 intel_dsi_init(dev);
12415         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12416                 bool found = false;
12417
12418                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12419                         DRM_DEBUG_KMS("probing SDVOB\n");
12420                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12421                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12422                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12423                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12424                         }
12425
12426                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12427                                 intel_dp_init(dev, DP_B, PORT_B);
12428                 }
12429
12430                 /* Before G4X SDVOC doesn't have its own detect register */
12431
12432                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12433                         DRM_DEBUG_KMS("probing SDVOC\n");
12434                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12435                 }
12436
12437                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12438
12439                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12440                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12441                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12442                         }
12443                         if (SUPPORTS_INTEGRATED_DP(dev))
12444                                 intel_dp_init(dev, DP_C, PORT_C);
12445                 }
12446
12447                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12448                     (I915_READ(DP_D) & DP_DETECTED))
12449                         intel_dp_init(dev, DP_D, PORT_D);
12450         } else if (IS_GEN2(dev))
12451                 intel_dvo_init(dev);
12452
12453         if (SUPPORTS_TV(dev))
12454                 intel_tv_init(dev);
12455
12456         intel_psr_init(dev);
12457
12458         for_each_intel_encoder(dev, encoder) {
12459                 encoder->base.possible_crtcs = encoder->crtc_mask;
12460                 encoder->base.possible_clones =
12461                         intel_encoder_clones(encoder);
12462         }
12463
12464         intel_init_pch_refclk(dev);
12465
12466         drm_helper_move_panel_connectors_to_head(dev);
12467 }
12468
12469 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12470 {
12471         struct drm_device *dev = fb->dev;
12472         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12473
12474         drm_framebuffer_cleanup(fb);
12475         mutex_lock(&dev->struct_mutex);
12476         WARN_ON(!intel_fb->obj->framebuffer_references--);
12477         drm_gem_object_unreference(&intel_fb->obj->base);
12478         mutex_unlock(&dev->struct_mutex);
12479         kfree(intel_fb);
12480 }
12481
12482 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12483                                                 struct drm_file *file,
12484                                                 unsigned int *handle)
12485 {
12486         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12487         struct drm_i915_gem_object *obj = intel_fb->obj;
12488
12489         return drm_gem_handle_create(file, &obj->base, handle);
12490 }
12491
12492 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12493         .destroy = intel_user_framebuffer_destroy,
12494         .create_handle = intel_user_framebuffer_create_handle,
12495 };
12496
12497 static int intel_framebuffer_init(struct drm_device *dev,
12498                                   struct intel_framebuffer *intel_fb,
12499                                   struct drm_mode_fb_cmd2 *mode_cmd,
12500                                   struct drm_i915_gem_object *obj)
12501 {
12502         int aligned_height;
12503         int pitch_limit;
12504         int ret;
12505
12506         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12507
12508         if (obj->tiling_mode == I915_TILING_Y) {
12509                 DRM_DEBUG("hardware does not support tiling Y\n");
12510                 return -EINVAL;
12511         }
12512
12513         if (mode_cmd->pitches[0] & 63) {
12514                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12515                           mode_cmd->pitches[0]);
12516                 return -EINVAL;
12517         }
12518
12519         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12520                 pitch_limit = 32*1024;
12521         } else if (INTEL_INFO(dev)->gen >= 4) {
12522                 if (obj->tiling_mode)
12523                         pitch_limit = 16*1024;
12524                 else
12525                         pitch_limit = 32*1024;
12526         } else if (INTEL_INFO(dev)->gen >= 3) {
12527                 if (obj->tiling_mode)
12528                         pitch_limit = 8*1024;
12529                 else
12530                         pitch_limit = 16*1024;
12531         } else
12532                 /* XXX DSPC is limited to 4k tiled */
12533                 pitch_limit = 8*1024;
12534
12535         if (mode_cmd->pitches[0] > pitch_limit) {
12536                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12537                           obj->tiling_mode ? "tiled" : "linear",
12538                           mode_cmd->pitches[0], pitch_limit);
12539                 return -EINVAL;
12540         }
12541
12542         if (obj->tiling_mode != I915_TILING_NONE &&
12543             mode_cmd->pitches[0] != obj->stride) {
12544                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12545                           mode_cmd->pitches[0], obj->stride);
12546                 return -EINVAL;
12547         }
12548
12549         /* Reject formats not supported by any plane early. */
12550         switch (mode_cmd->pixel_format) {
12551         case DRM_FORMAT_C8:
12552         case DRM_FORMAT_RGB565:
12553         case DRM_FORMAT_XRGB8888:
12554         case DRM_FORMAT_ARGB8888:
12555                 break;
12556         case DRM_FORMAT_XRGB1555:
12557         case DRM_FORMAT_ARGB1555:
12558                 if (INTEL_INFO(dev)->gen > 3) {
12559                         DRM_DEBUG("unsupported pixel format: %s\n",
12560                                   drm_get_format_name(mode_cmd->pixel_format));
12561                         return -EINVAL;
12562                 }
12563                 break;
12564         case DRM_FORMAT_XBGR8888:
12565         case DRM_FORMAT_ABGR8888:
12566         case DRM_FORMAT_XRGB2101010:
12567         case DRM_FORMAT_ARGB2101010:
12568         case DRM_FORMAT_XBGR2101010:
12569         case DRM_FORMAT_ABGR2101010:
12570                 if (INTEL_INFO(dev)->gen < 4) {
12571                         DRM_DEBUG("unsupported pixel format: %s\n",
12572                                   drm_get_format_name(mode_cmd->pixel_format));
12573                         return -EINVAL;
12574                 }
12575                 break;
12576         case DRM_FORMAT_YUYV:
12577         case DRM_FORMAT_UYVY:
12578         case DRM_FORMAT_YVYU:
12579         case DRM_FORMAT_VYUY:
12580                 if (INTEL_INFO(dev)->gen < 5) {
12581                         DRM_DEBUG("unsupported pixel format: %s\n",
12582                                   drm_get_format_name(mode_cmd->pixel_format));
12583                         return -EINVAL;
12584                 }
12585                 break;
12586         default:
12587                 DRM_DEBUG("unsupported pixel format: %s\n",
12588                           drm_get_format_name(mode_cmd->pixel_format));
12589                 return -EINVAL;
12590         }
12591
12592         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12593         if (mode_cmd->offsets[0] != 0)
12594                 return -EINVAL;
12595
12596         aligned_height = intel_align_height(dev, mode_cmd->height,
12597                                             obj->tiling_mode);
12598         /* FIXME drm helper for size checks (especially planar formats)? */
12599         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12600                 return -EINVAL;
12601
12602         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12603         intel_fb->obj = obj;
12604         intel_fb->obj->framebuffer_references++;
12605
12606         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12607         if (ret) {
12608                 DRM_ERROR("framebuffer init failed %d\n", ret);
12609                 return ret;
12610         }
12611
12612         return 0;
12613 }
12614
12615 static struct drm_framebuffer *
12616 intel_user_framebuffer_create(struct drm_device *dev,
12617                               struct drm_file *filp,
12618                               struct drm_mode_fb_cmd2 *mode_cmd)
12619 {
12620         struct drm_i915_gem_object *obj;
12621
12622         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12623                                                 mode_cmd->handles[0]));
12624         if (&obj->base == NULL)
12625                 return ERR_PTR(-ENOENT);
12626
12627         return intel_framebuffer_create(dev, mode_cmd, obj);
12628 }
12629
12630 #ifndef CONFIG_DRM_I915_FBDEV
12631 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12632 {
12633 }
12634 #endif
12635
12636 static const struct drm_mode_config_funcs intel_mode_funcs = {
12637         .fb_create = intel_user_framebuffer_create,
12638         .output_poll_changed = intel_fbdev_output_poll_changed,
12639 };
12640
12641 /* Set up chip specific display functions */
12642 static void intel_init_display(struct drm_device *dev)
12643 {
12644         struct drm_i915_private *dev_priv = dev->dev_private;
12645
12646         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12647                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12648         else if (IS_CHERRYVIEW(dev))
12649                 dev_priv->display.find_dpll = chv_find_best_dpll;
12650         else if (IS_VALLEYVIEW(dev))
12651                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12652         else if (IS_PINEVIEW(dev))
12653                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12654         else
12655                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12656
12657         if (HAS_DDI(dev)) {
12658                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12659                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12660                 dev_priv->display.crtc_compute_clock =
12661                         haswell_crtc_compute_clock;
12662                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12663                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12664                 dev_priv->display.off = ironlake_crtc_off;
12665                 if (INTEL_INFO(dev)->gen >= 9)
12666                         dev_priv->display.update_primary_plane =
12667                                 skylake_update_primary_plane;
12668                 else
12669                         dev_priv->display.update_primary_plane =
12670                                 ironlake_update_primary_plane;
12671         } else if (HAS_PCH_SPLIT(dev)) {
12672                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12673                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12674                 dev_priv->display.crtc_compute_clock =
12675                         ironlake_crtc_compute_clock;
12676                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12677                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12678                 dev_priv->display.off = ironlake_crtc_off;
12679                 dev_priv->display.update_primary_plane =
12680                         ironlake_update_primary_plane;
12681         } else if (IS_VALLEYVIEW(dev)) {
12682                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12683                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12684                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12685                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12686                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12687                 dev_priv->display.off = i9xx_crtc_off;
12688                 dev_priv->display.update_primary_plane =
12689                         i9xx_update_primary_plane;
12690         } else {
12691                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12692                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12693                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12694                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12695                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12696                 dev_priv->display.off = i9xx_crtc_off;
12697                 dev_priv->display.update_primary_plane =
12698                         i9xx_update_primary_plane;
12699         }
12700
12701         /* Returns the core display clock speed */
12702         if (IS_VALLEYVIEW(dev))
12703                 dev_priv->display.get_display_clock_speed =
12704                         valleyview_get_display_clock_speed;
12705         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12706                 dev_priv->display.get_display_clock_speed =
12707                         i945_get_display_clock_speed;
12708         else if (IS_I915G(dev))
12709                 dev_priv->display.get_display_clock_speed =
12710                         i915_get_display_clock_speed;
12711         else if (IS_I945GM(dev) || IS_845G(dev))
12712                 dev_priv->display.get_display_clock_speed =
12713                         i9xx_misc_get_display_clock_speed;
12714         else if (IS_PINEVIEW(dev))
12715                 dev_priv->display.get_display_clock_speed =
12716                         pnv_get_display_clock_speed;
12717         else if (IS_I915GM(dev))
12718                 dev_priv->display.get_display_clock_speed =
12719                         i915gm_get_display_clock_speed;
12720         else if (IS_I865G(dev))
12721                 dev_priv->display.get_display_clock_speed =
12722                         i865_get_display_clock_speed;
12723         else if (IS_I85X(dev))
12724                 dev_priv->display.get_display_clock_speed =
12725                         i855_get_display_clock_speed;
12726         else /* 852, 830 */
12727                 dev_priv->display.get_display_clock_speed =
12728                         i830_get_display_clock_speed;
12729
12730         if (IS_GEN5(dev)) {
12731                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12732         } else if (IS_GEN6(dev)) {
12733                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12734         } else if (IS_IVYBRIDGE(dev)) {
12735                 /* FIXME: detect B0+ stepping and use auto training */
12736                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12737                 dev_priv->display.modeset_global_resources =
12738                         ivb_modeset_global_resources;
12739         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12740                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12741         } else if (IS_VALLEYVIEW(dev)) {
12742                 dev_priv->display.modeset_global_resources =
12743                         valleyview_modeset_global_resources;
12744         }
12745
12746         /* Default just returns -ENODEV to indicate unsupported */
12747         dev_priv->display.queue_flip = intel_default_queue_flip;
12748
12749         switch (INTEL_INFO(dev)->gen) {
12750         case 2:
12751                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12752                 break;
12753
12754         case 3:
12755                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12756                 break;
12757
12758         case 4:
12759         case 5:
12760                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12761                 break;
12762
12763         case 6:
12764                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12765                 break;
12766         case 7:
12767         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12768                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12769                 break;
12770         case 9:
12771                 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12772                 break;
12773         }
12774
12775         intel_panel_init_backlight_funcs(dev);
12776
12777         mutex_init(&dev_priv->pps_mutex);
12778 }
12779
12780 /*
12781  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12782  * resume, or other times.  This quirk makes sure that's the case for
12783  * affected systems.
12784  */
12785 static void quirk_pipea_force(struct drm_device *dev)
12786 {
12787         struct drm_i915_private *dev_priv = dev->dev_private;
12788
12789         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12790         DRM_INFO("applying pipe a force quirk\n");
12791 }
12792
12793 static void quirk_pipeb_force(struct drm_device *dev)
12794 {
12795         struct drm_i915_private *dev_priv = dev->dev_private;
12796
12797         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12798         DRM_INFO("applying pipe b force quirk\n");
12799 }
12800
12801 /*
12802  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12803  */
12804 static void quirk_ssc_force_disable(struct drm_device *dev)
12805 {
12806         struct drm_i915_private *dev_priv = dev->dev_private;
12807         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12808         DRM_INFO("applying lvds SSC disable quirk\n");
12809 }
12810
12811 /*
12812  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12813  * brightness value
12814  */
12815 static void quirk_invert_brightness(struct drm_device *dev)
12816 {
12817         struct drm_i915_private *dev_priv = dev->dev_private;
12818         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12819         DRM_INFO("applying inverted panel brightness quirk\n");
12820 }
12821
12822 /* Some VBT's incorrectly indicate no backlight is present */
12823 static void quirk_backlight_present(struct drm_device *dev)
12824 {
12825         struct drm_i915_private *dev_priv = dev->dev_private;
12826         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12827         DRM_INFO("applying backlight present quirk\n");
12828 }
12829
12830 struct intel_quirk {
12831         int device;
12832         int subsystem_vendor;
12833         int subsystem_device;
12834         void (*hook)(struct drm_device *dev);
12835 };
12836
12837 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12838 struct intel_dmi_quirk {
12839         void (*hook)(struct drm_device *dev);
12840         const struct dmi_system_id (*dmi_id_list)[];
12841 };
12842
12843 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12844 {
12845         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12846         return 1;
12847 }
12848
12849 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12850         {
12851                 .dmi_id_list = &(const struct dmi_system_id[]) {
12852                         {
12853                                 .callback = intel_dmi_reverse_brightness,
12854                                 .ident = "NCR Corporation",
12855                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12856                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12857                                 },
12858                         },
12859                         { }  /* terminating entry */
12860                 },
12861                 .hook = quirk_invert_brightness,
12862         },
12863 };
12864
12865 static struct intel_quirk intel_quirks[] = {
12866         /* HP Mini needs pipe A force quirk (LP: #322104) */
12867         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12868
12869         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12870         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12871
12872         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12873         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12874
12875         /* 830 needs to leave pipe A & dpll A up */
12876         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12877
12878         /* 830 needs to leave pipe B & dpll B up */
12879         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12880
12881         /* Lenovo U160 cannot use SSC on LVDS */
12882         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12883
12884         /* Sony Vaio Y cannot use SSC on LVDS */
12885         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12886
12887         /* Acer Aspire 5734Z must invert backlight brightness */
12888         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12889
12890         /* Acer/eMachines G725 */
12891         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12892
12893         /* Acer/eMachines e725 */
12894         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12895
12896         /* Acer/Packard Bell NCL20 */
12897         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12898
12899         /* Acer Aspire 4736Z */
12900         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12901
12902         /* Acer Aspire 5336 */
12903         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12904
12905         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12906         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12907
12908         /* Acer C720 Chromebook (Core i3 4005U) */
12909         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12910
12911         /* Apple Macbook 2,1 (Core 2 T7400) */
12912         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12913
12914         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12915         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12916
12917         /* HP Chromebook 14 (Celeron 2955U) */
12918         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12919 };
12920
12921 static void intel_init_quirks(struct drm_device *dev)
12922 {
12923         struct pci_dev *d = dev->pdev;
12924         int i;
12925
12926         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12927                 struct intel_quirk *q = &intel_quirks[i];
12928
12929                 if (d->device == q->device &&
12930                     (d->subsystem_vendor == q->subsystem_vendor ||
12931                      q->subsystem_vendor == PCI_ANY_ID) &&
12932                     (d->subsystem_device == q->subsystem_device ||
12933                      q->subsystem_device == PCI_ANY_ID))
12934                         q->hook(dev);
12935         }
12936         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12937                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12938                         intel_dmi_quirks[i].hook(dev);
12939         }
12940 }
12941
12942 /* Disable the VGA plane that we never use */
12943 static void i915_disable_vga(struct drm_device *dev)
12944 {
12945         struct drm_i915_private *dev_priv = dev->dev_private;
12946         u8 sr1;
12947         u32 vga_reg = i915_vgacntrl_reg(dev);
12948
12949         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12950         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12951         outb(SR01, VGA_SR_INDEX);
12952         sr1 = inb(VGA_SR_DATA);
12953         outb(sr1 | 1<<5, VGA_SR_DATA);
12954         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12955         udelay(300);
12956
12957         /*
12958          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12959          * from S3 without preserving (some of?) the other bits.
12960          */
12961         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12962         POSTING_READ(vga_reg);
12963 }
12964
12965 void intel_modeset_init_hw(struct drm_device *dev)
12966 {
12967         intel_prepare_ddi(dev);
12968
12969         if (IS_VALLEYVIEW(dev))
12970                 vlv_update_cdclk(dev);
12971
12972         intel_init_clock_gating(dev);
12973
12974         intel_enable_gt_powersave(dev);
12975 }
12976
12977 void intel_modeset_init(struct drm_device *dev)
12978 {
12979         struct drm_i915_private *dev_priv = dev->dev_private;
12980         int sprite, ret;
12981         enum pipe pipe;
12982         struct intel_crtc *crtc;
12983
12984         drm_mode_config_init(dev);
12985
12986         dev->mode_config.min_width = 0;
12987         dev->mode_config.min_height = 0;
12988
12989         dev->mode_config.preferred_depth = 24;
12990         dev->mode_config.prefer_shadow = 1;
12991
12992         dev->mode_config.funcs = &intel_mode_funcs;
12993
12994         intel_init_quirks(dev);
12995
12996         intel_init_pm(dev);
12997
12998         if (INTEL_INFO(dev)->num_pipes == 0)
12999                 return;
13000
13001         intel_init_display(dev);
13002         intel_init_audio(dev);
13003
13004         if (IS_GEN2(dev)) {
13005                 dev->mode_config.max_width = 2048;
13006                 dev->mode_config.max_height = 2048;
13007         } else if (IS_GEN3(dev)) {
13008                 dev->mode_config.max_width = 4096;
13009                 dev->mode_config.max_height = 4096;
13010         } else {
13011                 dev->mode_config.max_width = 8192;
13012                 dev->mode_config.max_height = 8192;
13013         }
13014
13015         if (IS_845G(dev) || IS_I865G(dev)) {
13016                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13017                 dev->mode_config.cursor_height = 1023;
13018         } else if (IS_GEN2(dev)) {
13019                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13020                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13021         } else {
13022                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13023                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13024         }
13025
13026         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13027
13028         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13029                       INTEL_INFO(dev)->num_pipes,
13030                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13031
13032         for_each_pipe(dev_priv, pipe) {
13033                 intel_crtc_init(dev, pipe);
13034                 for_each_sprite(pipe, sprite) {
13035                         ret = intel_plane_init(dev, pipe, sprite);
13036                         if (ret)
13037                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13038                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13039                 }
13040         }
13041
13042         intel_init_dpio(dev);
13043
13044         intel_shared_dpll_init(dev);
13045
13046         /* save the BIOS value before clobbering it */
13047         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13048         /* Just disable it once at startup */
13049         i915_disable_vga(dev);
13050         intel_setup_outputs(dev);
13051
13052         /* Just in case the BIOS is doing something questionable. */
13053         intel_disable_fbc(dev);
13054
13055         drm_modeset_lock_all(dev);
13056         intel_modeset_setup_hw_state(dev, false);
13057         drm_modeset_unlock_all(dev);
13058
13059         for_each_intel_crtc(dev, crtc) {
13060                 if (!crtc->active)
13061                         continue;
13062
13063                 /*
13064                  * Note that reserving the BIOS fb up front prevents us
13065                  * from stuffing other stolen allocations like the ring
13066                  * on top.  This prevents some ugliness at boot time, and
13067                  * can even allow for smooth boot transitions if the BIOS
13068                  * fb is large enough for the active pipe configuration.
13069                  */
13070                 if (dev_priv->display.get_plane_config) {
13071                         dev_priv->display.get_plane_config(crtc,
13072                                                            &crtc->plane_config);
13073                         /*
13074                          * If the fb is shared between multiple heads, we'll
13075                          * just get the first one.
13076                          */
13077                         intel_find_plane_obj(crtc, &crtc->plane_config);
13078                 }
13079         }
13080 }
13081
13082 static void intel_enable_pipe_a(struct drm_device *dev)
13083 {
13084         struct intel_connector *connector;
13085         struct drm_connector *crt = NULL;
13086         struct intel_load_detect_pipe load_detect_temp;
13087         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13088
13089         /* We can't just switch on the pipe A, we need to set things up with a
13090          * proper mode and output configuration. As a gross hack, enable pipe A
13091          * by enabling the load detect pipe once. */
13092         list_for_each_entry(connector,
13093                             &dev->mode_config.connector_list,
13094                             base.head) {
13095                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13096                         crt = &connector->base;
13097                         break;
13098                 }
13099         }
13100
13101         if (!crt)
13102                 return;
13103
13104         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13105                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13106 }
13107
13108 static bool
13109 intel_check_plane_mapping(struct intel_crtc *crtc)
13110 {
13111         struct drm_device *dev = crtc->base.dev;
13112         struct drm_i915_private *dev_priv = dev->dev_private;
13113         u32 reg, val;
13114
13115         if (INTEL_INFO(dev)->num_pipes == 1)
13116                 return true;
13117
13118         reg = DSPCNTR(!crtc->plane);
13119         val = I915_READ(reg);
13120
13121         if ((val & DISPLAY_PLANE_ENABLE) &&
13122             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13123                 return false;
13124
13125         return true;
13126 }
13127
13128 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13129 {
13130         struct drm_device *dev = crtc->base.dev;
13131         struct drm_i915_private *dev_priv = dev->dev_private;
13132         u32 reg;
13133
13134         /* Clear any frame start delays used for debugging left by the BIOS */
13135         reg = PIPECONF(crtc->config.cpu_transcoder);
13136         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13137
13138         /* restore vblank interrupts to correct state */
13139         if (crtc->active) {
13140                 update_scanline_offset(crtc);
13141                 drm_vblank_on(dev, crtc->pipe);
13142         } else
13143                 drm_vblank_off(dev, crtc->pipe);
13144
13145         /* We need to sanitize the plane -> pipe mapping first because this will
13146          * disable the crtc (and hence change the state) if it is wrong. Note
13147          * that gen4+ has a fixed plane -> pipe mapping.  */
13148         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13149                 struct intel_connector *connector;
13150                 bool plane;
13151
13152                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13153                               crtc->base.base.id);
13154
13155                 /* Pipe has the wrong plane attached and the plane is active.
13156                  * Temporarily change the plane mapping and disable everything
13157                  * ...  */
13158                 plane = crtc->plane;
13159                 crtc->plane = !plane;
13160                 crtc->primary_enabled = true;
13161                 dev_priv->display.crtc_disable(&crtc->base);
13162                 crtc->plane = plane;
13163
13164                 /* ... and break all links. */
13165                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13166                                     base.head) {
13167                         if (connector->encoder->base.crtc != &crtc->base)
13168                                 continue;
13169
13170                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13171                         connector->base.encoder = NULL;
13172                 }
13173                 /* multiple connectors may have the same encoder:
13174                  *  handle them and break crtc link separately */
13175                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13176                                     base.head)
13177                         if (connector->encoder->base.crtc == &crtc->base) {
13178                                 connector->encoder->base.crtc = NULL;
13179                                 connector->encoder->connectors_active = false;
13180                         }
13181
13182                 WARN_ON(crtc->active);
13183                 crtc->base.enabled = false;
13184         }
13185
13186         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13187             crtc->pipe == PIPE_A && !crtc->active) {
13188                 /* BIOS forgot to enable pipe A, this mostly happens after
13189                  * resume. Force-enable the pipe to fix this, the update_dpms
13190                  * call below we restore the pipe to the right state, but leave
13191                  * the required bits on. */
13192                 intel_enable_pipe_a(dev);
13193         }
13194
13195         /* Adjust the state of the output pipe according to whether we
13196          * have active connectors/encoders. */
13197         intel_crtc_update_dpms(&crtc->base);
13198
13199         if (crtc->active != crtc->base.enabled) {
13200                 struct intel_encoder *encoder;
13201
13202                 /* This can happen either due to bugs in the get_hw_state
13203                  * functions or because the pipe is force-enabled due to the
13204                  * pipe A quirk. */
13205                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13206                               crtc->base.base.id,
13207                               crtc->base.enabled ? "enabled" : "disabled",
13208                               crtc->active ? "enabled" : "disabled");
13209
13210                 crtc->base.enabled = crtc->active;
13211
13212                 /* Because we only establish the connector -> encoder ->
13213                  * crtc links if something is active, this means the
13214                  * crtc is now deactivated. Break the links. connector
13215                  * -> encoder links are only establish when things are
13216                  *  actually up, hence no need to break them. */
13217                 WARN_ON(crtc->active);
13218
13219                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13220                         WARN_ON(encoder->connectors_active);
13221                         encoder->base.crtc = NULL;
13222                 }
13223         }
13224
13225         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13226                 /*
13227                  * We start out with underrun reporting disabled to avoid races.
13228                  * For correct bookkeeping mark this on active crtcs.
13229                  *
13230                  * Also on gmch platforms we dont have any hardware bits to
13231                  * disable the underrun reporting. Which means we need to start
13232                  * out with underrun reporting disabled also on inactive pipes,
13233                  * since otherwise we'll complain about the garbage we read when
13234                  * e.g. coming up after runtime pm.
13235                  *
13236                  * No protection against concurrent access is required - at
13237                  * worst a fifo underrun happens which also sets this to false.
13238                  */
13239                 crtc->cpu_fifo_underrun_disabled = true;
13240                 crtc->pch_fifo_underrun_disabled = true;
13241         }
13242 }
13243
13244 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13245 {
13246         struct intel_connector *connector;
13247         struct drm_device *dev = encoder->base.dev;
13248
13249         /* We need to check both for a crtc link (meaning that the
13250          * encoder is active and trying to read from a pipe) and the
13251          * pipe itself being active. */
13252         bool has_active_crtc = encoder->base.crtc &&
13253                 to_intel_crtc(encoder->base.crtc)->active;
13254
13255         if (encoder->connectors_active && !has_active_crtc) {
13256                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13257                               encoder->base.base.id,
13258                               encoder->base.name);
13259
13260                 /* Connector is active, but has no active pipe. This is
13261                  * fallout from our resume register restoring. Disable
13262                  * the encoder manually again. */
13263                 if (encoder->base.crtc) {
13264                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13265                                       encoder->base.base.id,
13266                                       encoder->base.name);
13267                         encoder->disable(encoder);
13268                         if (encoder->post_disable)
13269                                 encoder->post_disable(encoder);
13270                 }
13271                 encoder->base.crtc = NULL;
13272                 encoder->connectors_active = false;
13273
13274                 /* Inconsistent output/port/pipe state happens presumably due to
13275                  * a bug in one of the get_hw_state functions. Or someplace else
13276                  * in our code, like the register restore mess on resume. Clamp
13277                  * things to off as a safer default. */
13278                 list_for_each_entry(connector,
13279                                     &dev->mode_config.connector_list,
13280                                     base.head) {
13281                         if (connector->encoder != encoder)
13282                                 continue;
13283                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13284                         connector->base.encoder = NULL;
13285                 }
13286         }
13287         /* Enabled encoders without active connectors will be fixed in
13288          * the crtc fixup. */
13289 }
13290
13291 void i915_redisable_vga_power_on(struct drm_device *dev)
13292 {
13293         struct drm_i915_private *dev_priv = dev->dev_private;
13294         u32 vga_reg = i915_vgacntrl_reg(dev);
13295
13296         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13297                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13298                 i915_disable_vga(dev);
13299         }
13300 }
13301
13302 void i915_redisable_vga(struct drm_device *dev)
13303 {
13304         struct drm_i915_private *dev_priv = dev->dev_private;
13305
13306         /* This function can be called both from intel_modeset_setup_hw_state or
13307          * at a very early point in our resume sequence, where the power well
13308          * structures are not yet restored. Since this function is at a very
13309          * paranoid "someone might have enabled VGA while we were not looking"
13310          * level, just check if the power well is enabled instead of trying to
13311          * follow the "don't touch the power well if we don't need it" policy
13312          * the rest of the driver uses. */
13313         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13314                 return;
13315
13316         i915_redisable_vga_power_on(dev);
13317 }
13318
13319 static bool primary_get_hw_state(struct intel_crtc *crtc)
13320 {
13321         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13322
13323         if (!crtc->active)
13324                 return false;
13325
13326         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13327 }
13328
13329 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13330 {
13331         struct drm_i915_private *dev_priv = dev->dev_private;
13332         enum pipe pipe;
13333         struct intel_crtc *crtc;
13334         struct intel_encoder *encoder;
13335         struct intel_connector *connector;
13336         int i;
13337
13338         for_each_intel_crtc(dev, crtc) {
13339                 memset(&crtc->config, 0, sizeof(crtc->config));
13340
13341                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13342
13343                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13344                                                                  &crtc->config);
13345
13346                 crtc->base.enabled = crtc->active;
13347                 crtc->primary_enabled = primary_get_hw_state(crtc);
13348
13349                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13350                               crtc->base.base.id,
13351                               crtc->active ? "enabled" : "disabled");
13352         }
13353
13354         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13355                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13356
13357                 pll->on = pll->get_hw_state(dev_priv, pll,
13358                                             &pll->config.hw_state);
13359                 pll->active = 0;
13360                 pll->config.crtc_mask = 0;
13361                 for_each_intel_crtc(dev, crtc) {
13362                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13363                                 pll->active++;
13364                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13365                         }
13366                 }
13367
13368                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13369                               pll->name, pll->config.crtc_mask, pll->on);
13370
13371                 if (pll->config.crtc_mask)
13372                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13373         }
13374
13375         for_each_intel_encoder(dev, encoder) {
13376                 pipe = 0;
13377
13378                 if (encoder->get_hw_state(encoder, &pipe)) {
13379                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13380                         encoder->base.crtc = &crtc->base;
13381                         encoder->get_config(encoder, &crtc->config);
13382                 } else {
13383                         encoder->base.crtc = NULL;
13384                 }
13385
13386                 encoder->connectors_active = false;
13387                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13388                               encoder->base.base.id,
13389                               encoder->base.name,
13390                               encoder->base.crtc ? "enabled" : "disabled",
13391                               pipe_name(pipe));
13392         }
13393
13394         list_for_each_entry(connector, &dev->mode_config.connector_list,
13395                             base.head) {
13396                 if (connector->get_hw_state(connector)) {
13397                         connector->base.dpms = DRM_MODE_DPMS_ON;
13398                         connector->encoder->connectors_active = true;
13399                         connector->base.encoder = &connector->encoder->base;
13400                 } else {
13401                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13402                         connector->base.encoder = NULL;
13403                 }
13404                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13405                               connector->base.base.id,
13406                               connector->base.name,
13407                               connector->base.encoder ? "enabled" : "disabled");
13408         }
13409 }
13410
13411 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13412  * and i915 state tracking structures. */
13413 void intel_modeset_setup_hw_state(struct drm_device *dev,
13414                                   bool force_restore)
13415 {
13416         struct drm_i915_private *dev_priv = dev->dev_private;
13417         enum pipe pipe;
13418         struct intel_crtc *crtc;
13419         struct intel_encoder *encoder;
13420         int i;
13421
13422         intel_modeset_readout_hw_state(dev);
13423
13424         /*
13425          * Now that we have the config, copy it to each CRTC struct
13426          * Note that this could go away if we move to using crtc_config
13427          * checking everywhere.
13428          */
13429         for_each_intel_crtc(dev, crtc) {
13430                 if (crtc->active && i915.fastboot) {
13431                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13432                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13433                                       crtc->base.base.id);
13434                         drm_mode_debug_printmodeline(&crtc->base.mode);
13435                 }
13436         }
13437
13438         /* HW state is read out, now we need to sanitize this mess. */
13439         for_each_intel_encoder(dev, encoder) {
13440                 intel_sanitize_encoder(encoder);
13441         }
13442
13443         for_each_pipe(dev_priv, pipe) {
13444                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13445                 intel_sanitize_crtc(crtc);
13446                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13447         }
13448
13449         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13450                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13451
13452                 if (!pll->on || pll->active)
13453                         continue;
13454
13455                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13456
13457                 pll->disable(dev_priv, pll);
13458                 pll->on = false;
13459         }
13460
13461         if (IS_GEN9(dev))
13462                 skl_wm_get_hw_state(dev);
13463         else if (HAS_PCH_SPLIT(dev))
13464                 ilk_wm_get_hw_state(dev);
13465
13466         if (force_restore) {
13467                 i915_redisable_vga(dev);
13468
13469                 /*
13470                  * We need to use raw interfaces for restoring state to avoid
13471                  * checking (bogus) intermediate states.
13472                  */
13473                 for_each_pipe(dev_priv, pipe) {
13474                         struct drm_crtc *crtc =
13475                                 dev_priv->pipe_to_crtc_mapping[pipe];
13476
13477                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13478                                        crtc->primary->fb);
13479                 }
13480         } else {
13481                 intel_modeset_update_staged_output_state(dev);
13482         }
13483
13484         intel_modeset_check_state(dev);
13485 }
13486
13487 void intel_modeset_gem_init(struct drm_device *dev)
13488 {
13489         struct drm_i915_private *dev_priv = dev->dev_private;
13490         struct drm_crtc *c;
13491         struct drm_i915_gem_object *obj;
13492
13493         mutex_lock(&dev->struct_mutex);
13494         intel_init_gt_powersave(dev);
13495         mutex_unlock(&dev->struct_mutex);
13496
13497         /*
13498          * There may be no VBT; and if the BIOS enabled SSC we can
13499          * just keep using it to avoid unnecessary flicker.  Whereas if the
13500          * BIOS isn't using it, don't assume it will work even if the VBT
13501          * indicates as much.
13502          */
13503         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13504                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13505                                                 DREF_SSC1_ENABLE);
13506
13507         intel_modeset_init_hw(dev);
13508
13509         intel_setup_overlay(dev);
13510
13511         /*
13512          * Make sure any fbs we allocated at startup are properly
13513          * pinned & fenced.  When we do the allocation it's too early
13514          * for this.
13515          */
13516         mutex_lock(&dev->struct_mutex);
13517         for_each_crtc(dev, c) {
13518                 obj = intel_fb_obj(c->primary->fb);
13519                 if (obj == NULL)
13520                         continue;
13521
13522                 if (intel_pin_and_fence_fb_obj(c->primary,
13523                                                c->primary->fb,
13524                                                NULL)) {
13525                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13526                                   to_intel_crtc(c)->pipe);
13527                         drm_framebuffer_unreference(c->primary->fb);
13528                         c->primary->fb = NULL;
13529                 }
13530         }
13531         mutex_unlock(&dev->struct_mutex);
13532
13533         intel_backlight_register(dev);
13534 }
13535
13536 void intel_connector_unregister(struct intel_connector *intel_connector)
13537 {
13538         struct drm_connector *connector = &intel_connector->base;
13539
13540         intel_panel_destroy_backlight(connector);
13541         drm_connector_unregister(connector);
13542 }
13543
13544 void intel_modeset_cleanup(struct drm_device *dev)
13545 {
13546         struct drm_i915_private *dev_priv = dev->dev_private;
13547         struct drm_connector *connector;
13548
13549         intel_disable_gt_powersave(dev);
13550
13551         intel_backlight_unregister(dev);
13552
13553         /*
13554          * Interrupts and polling as the first thing to avoid creating havoc.
13555          * Too much stuff here (turning of connectors, ...) would
13556          * experience fancy races otherwise.
13557          */
13558         intel_irq_uninstall(dev_priv);
13559
13560         /*
13561          * Due to the hpd irq storm handling the hotplug work can re-arm the
13562          * poll handlers. Hence disable polling after hpd handling is shut down.
13563          */
13564         drm_kms_helper_poll_fini(dev);
13565
13566         mutex_lock(&dev->struct_mutex);
13567
13568         intel_unregister_dsm_handler();
13569
13570         intel_disable_fbc(dev);
13571
13572         ironlake_teardown_rc6(dev);
13573
13574         mutex_unlock(&dev->struct_mutex);
13575
13576         /* flush any delayed tasks or pending work */
13577         flush_scheduled_work();
13578
13579         /* destroy the backlight and sysfs files before encoders/connectors */
13580         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13581                 struct intel_connector *intel_connector;
13582
13583                 intel_connector = to_intel_connector(connector);
13584                 intel_connector->unregister(intel_connector);
13585         }
13586
13587         drm_mode_config_cleanup(dev);
13588
13589         intel_cleanup_overlay(dev);
13590
13591         mutex_lock(&dev->struct_mutex);
13592         intel_cleanup_gt_powersave(dev);
13593         mutex_unlock(&dev->struct_mutex);
13594 }
13595
13596 /*
13597  * Return which encoder is currently attached for connector.
13598  */
13599 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13600 {
13601         return &intel_attached_encoder(connector)->base;
13602 }
13603
13604 void intel_connector_attach_encoder(struct intel_connector *connector,
13605                                     struct intel_encoder *encoder)
13606 {
13607         connector->encoder = encoder;
13608         drm_mode_connector_attach_encoder(&connector->base,
13609                                           &encoder->base);
13610 }
13611
13612 /*
13613  * set vga decode state - true == enable VGA decode
13614  */
13615 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13616 {
13617         struct drm_i915_private *dev_priv = dev->dev_private;
13618         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13619         u16 gmch_ctrl;
13620
13621         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13622                 DRM_ERROR("failed to read control word\n");
13623                 return -EIO;
13624         }
13625
13626         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13627                 return 0;
13628
13629         if (state)
13630                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13631         else
13632                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13633
13634         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13635                 DRM_ERROR("failed to write control word\n");
13636                 return -EIO;
13637         }
13638
13639         return 0;
13640 }
13641
13642 struct intel_display_error_state {
13643
13644         u32 power_well_driver;
13645
13646         int num_transcoders;
13647
13648         struct intel_cursor_error_state {
13649                 u32 control;
13650                 u32 position;
13651                 u32 base;
13652                 u32 size;
13653         } cursor[I915_MAX_PIPES];
13654
13655         struct intel_pipe_error_state {
13656                 bool power_domain_on;
13657                 u32 source;
13658                 u32 stat;
13659         } pipe[I915_MAX_PIPES];
13660
13661         struct intel_plane_error_state {
13662                 u32 control;
13663                 u32 stride;
13664                 u32 size;
13665                 u32 pos;
13666                 u32 addr;
13667                 u32 surface;
13668                 u32 tile_offset;
13669         } plane[I915_MAX_PIPES];
13670
13671         struct intel_transcoder_error_state {
13672                 bool power_domain_on;
13673                 enum transcoder cpu_transcoder;
13674
13675                 u32 conf;
13676
13677                 u32 htotal;
13678                 u32 hblank;
13679                 u32 hsync;
13680                 u32 vtotal;
13681                 u32 vblank;
13682                 u32 vsync;
13683         } transcoder[4];
13684 };
13685
13686 struct intel_display_error_state *
13687 intel_display_capture_error_state(struct drm_device *dev)
13688 {
13689         struct drm_i915_private *dev_priv = dev->dev_private;
13690         struct intel_display_error_state *error;
13691         int transcoders[] = {
13692                 TRANSCODER_A,
13693                 TRANSCODER_B,
13694                 TRANSCODER_C,
13695                 TRANSCODER_EDP,
13696         };
13697         int i;
13698
13699         if (INTEL_INFO(dev)->num_pipes == 0)
13700                 return NULL;
13701
13702         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13703         if (error == NULL)
13704                 return NULL;
13705
13706         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13707                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13708
13709         for_each_pipe(dev_priv, i) {
13710                 error->pipe[i].power_domain_on =
13711                         __intel_display_power_is_enabled(dev_priv,
13712                                                          POWER_DOMAIN_PIPE(i));
13713                 if (!error->pipe[i].power_domain_on)
13714                         continue;
13715
13716                 error->cursor[i].control = I915_READ(CURCNTR(i));
13717                 error->cursor[i].position = I915_READ(CURPOS(i));
13718                 error->cursor[i].base = I915_READ(CURBASE(i));
13719
13720                 error->plane[i].control = I915_READ(DSPCNTR(i));
13721                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13722                 if (INTEL_INFO(dev)->gen <= 3) {
13723                         error->plane[i].size = I915_READ(DSPSIZE(i));
13724                         error->plane[i].pos = I915_READ(DSPPOS(i));
13725                 }
13726                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13727                         error->plane[i].addr = I915_READ(DSPADDR(i));
13728                 if (INTEL_INFO(dev)->gen >= 4) {
13729                         error->plane[i].surface = I915_READ(DSPSURF(i));
13730                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13731                 }
13732
13733                 error->pipe[i].source = I915_READ(PIPESRC(i));
13734
13735                 if (HAS_GMCH_DISPLAY(dev))
13736                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13737         }
13738
13739         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13740         if (HAS_DDI(dev_priv->dev))
13741                 error->num_transcoders++; /* Account for eDP. */
13742
13743         for (i = 0; i < error->num_transcoders; i++) {
13744                 enum transcoder cpu_transcoder = transcoders[i];
13745
13746                 error->transcoder[i].power_domain_on =
13747                         __intel_display_power_is_enabled(dev_priv,
13748                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13749                 if (!error->transcoder[i].power_domain_on)
13750                         continue;
13751
13752                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13753
13754                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13755                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13756                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13757                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13758                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13759                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13760                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13761         }
13762
13763         return error;
13764 }
13765
13766 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13767
13768 void
13769 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13770                                 struct drm_device *dev,
13771                                 struct intel_display_error_state *error)
13772 {
13773         struct drm_i915_private *dev_priv = dev->dev_private;
13774         int i;
13775
13776         if (!error)
13777                 return;
13778
13779         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13780         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13781                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13782                            error->power_well_driver);
13783         for_each_pipe(dev_priv, i) {
13784                 err_printf(m, "Pipe [%d]:\n", i);
13785                 err_printf(m, "  Power: %s\n",
13786                            error->pipe[i].power_domain_on ? "on" : "off");
13787                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13788                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13789
13790                 err_printf(m, "Plane [%d]:\n", i);
13791                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13792                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13793                 if (INTEL_INFO(dev)->gen <= 3) {
13794                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13795                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13796                 }
13797                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13798                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13799                 if (INTEL_INFO(dev)->gen >= 4) {
13800                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13801                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13802                 }
13803
13804                 err_printf(m, "Cursor [%d]:\n", i);
13805                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13806                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13807                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13808         }
13809
13810         for (i = 0; i < error->num_transcoders; i++) {
13811                 err_printf(m, "CPU transcoder: %c\n",
13812                            transcoder_name(error->transcoder[i].cpu_transcoder));
13813                 err_printf(m, "  Power: %s\n",
13814                            error->transcoder[i].power_domain_on ? "on" : "off");
13815                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13816                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13817                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13818                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13819                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13820                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13821                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13822         }
13823 }
13824
13825 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13826 {
13827         struct intel_crtc *crtc;
13828
13829         for_each_intel_crtc(dev, crtc) {
13830                 struct intel_unpin_work *work;
13831
13832                 spin_lock_irq(&dev->event_lock);
13833
13834                 work = crtc->unpin_work;
13835
13836                 if (work && work->event &&
13837                     work->event->base.file_priv == file) {
13838                         kfree(work->event);
13839                         work->event = NULL;
13840                 }
13841
13842                 spin_unlock_irq(&dev->event_lock);
13843         }
13844 }