drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 typedef struct intel_limit intel_limit_t;
  63 struct intel_limit {
  64         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  65         intel_p2_t          p2;
  66 };
  67
  68 /* FDI */
  69 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv_dac = {
 313         .dot = { .min = 25000, .max = 270000 },
 314         .vco = { .min = 4000000, .max = 6000000 },
 315         .n = { .min = 1, .max = 7 },
 316         .m = { .min = 22, .max = 450 }, /* guess */
 317         .m1 = { .min = 2, .max = 3 },
 318         .m2 = { .min = 11, .max = 156 },
 319         .p = { .min = 10, .max = 30 },
 320         .p1 = { .min = 1, .max = 3 },
 321         .p2 = { .dot_limit = 270000,
 322                 .p2_slow = 2, .p2_fast = 20 },
 323 };
 324
 325 static const intel_limit_t intel_limits_vlv_hdmi = {
 326         .dot = { .min = 25000, .max = 270000 },
 327         .vco = { .min = 4000000, .max = 6000000 },
 328         .n = { .min = 1, .max = 7 },
 329         .m = { .min = 60, .max = 300 }, /* guess */
 330         .m1 = { .min = 2, .max = 3 },
 331         .m2 = { .min = 11, .max = 156 },
 332         .p = { .min = 10, .max = 30 },
 333         .p1 = { .min = 2, .max = 3 },
 334         .p2 = { .dot_limit = 270000,
 335                 .p2_slow = 2, .p2_fast = 20 },
 336 };
 337
 338 static const intel_limit_t intel_limits_vlv_dp = {
 339         .dot = { .min = 25000, .max = 270000 },
 340         .vco = { .min = 4000000, .max = 6000000 },
 341         .n = { .min = 1, .max = 7 },
 342         .m = { .min = 22, .max = 450 },
 343         .m1 = { .min = 2, .max = 3 },
 344         .m2 = { .min = 11, .max = 156 },
 345         .p = { .min = 10, .max = 30 },
 346         .p1 = { .min = 1, .max = 3 },
 347         .p2 = { .dot_limit = 270000,
 348                 .p2_slow = 2, .p2_fast = 20 },
 349 };
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 412                         limit = &intel_limits_vlv_dac;
 413                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 414                         limit = &intel_limits_vlv_hdmi;
 415                 else
 416                         limit = &intel_limits_vlv_dp;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         clock->vco = refclk * clock->m / clock->n;
 439         clock->dot = clock->vco / clock->p;
 440 }
 441
 442 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 443 {
 444         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 445 }
 446
 447 static void i9xx_clock(int refclk, intel_clock_t *clock)
 448 {
 449         clock->m = i9xx_dpll_compute_m(clock);
 450         clock->p = clock->p1 * clock->p2;
 451         clock->vco = refclk * clock->m / (clock->n + 2);
 452         clock->dot = clock->vco / clock->p;
 453 }
 454
 455 /**
 456  * Returns whether any output on the specified pipe is of the specified type
 457  */
 458 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 459 {
 460         struct drm_device *dev = crtc->dev;
 461         struct intel_encoder *encoder;
 462
 463         for_each_encoder_on_crtc(dev, crtc, encoder)
 464                 if (encoder->type == type)
 465                         return true;
 466
 467         return false;
 468 }
 469
 470 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 471 /**
 472  * Returns whether the given set of divisors are valid for a given refclk with
 473  * the given connectors.
 474  */
 475
 476 static bool intel_PLL_is_valid(struct drm_device *dev,
 477                                const intel_limit_t *limit,
 478                                const intel_clock_t *clock)
 479 {
 480         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 481                 INTELPllInvalid("p1 out of range\n");
 482         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 483                 INTELPllInvalid("p out of range\n");
 484         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 485                 INTELPllInvalid("m2 out of range\n");
 486         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 487                 INTELPllInvalid("m1 out of range\n");
 488         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 489                 INTELPllInvalid("m1 <= m2\n");
 490         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 491                 INTELPllInvalid("m out of range\n");
 492         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 493                 INTELPllInvalid("n out of range\n");
 494         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 495                 INTELPllInvalid("vco out of range\n");
 496         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 497          * connector, etc., rather than just a single range.
 498          */
 499         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 500                 INTELPllInvalid("dot out of range\n");
 501
 502         return true;
 503 }
 504
 505 static bool
 506 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 507                     int target, int refclk, intel_clock_t *match_clock,
 508                     intel_clock_t *best_clock)
 509 {
 510         struct drm_device *dev = crtc->dev;
 511         intel_clock_t clock;
 512         int err = target;
 513
 514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 515                 /*
 516                  * For LVDS just rely on its current settings for dual-channel.
 517                  * We haven't figured out how to reliably set up different
 518                  * single/dual channel state, if we even can.
 519                  */
 520                 if (intel_is_dual_link_lvds(dev))
 521                         clock.p2 = limit->p2.p2_fast;
 522                 else
 523                         clock.p2 = limit->p2.p2_slow;
 524         } else {
 525                 if (target < limit->p2.dot_limit)
 526                         clock.p2 = limit->p2.p2_slow;
 527                 else
 528                         clock.p2 = limit->p2.p2_fast;
 529         }
 530
 531         memset(best_clock, 0, sizeof(*best_clock));
 532
 533         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 534              clock.m1++) {
 535                 for (clock.m2 = limit->m2.min;
 536                      clock.m2 <= limit->m2.max; clock.m2++) {
 537                         if (clock.m2 >= clock.m1)
 538                                 break;
 539                         for (clock.n = limit->n.min;
 540                              clock.n <= limit->n.max; clock.n++) {
 541                                 for (clock.p1 = limit->p1.min;
 542                                         clock.p1 <= limit->p1.max; clock.p1++) {
 543                                         int this_err;
 544
 545                                         i9xx_clock(refclk, &clock);
 546                                         if (!intel_PLL_is_valid(dev, limit,
 547                                                                 &clock))
 548                                                 continue;
 549                                         if (match_clock &&
 550                                             clock.p != match_clock->p)
 551                                                 continue;
 552
 553                                         this_err = abs(clock.dot - target);
 554                                         if (this_err < err) {
 555                                                 *best_clock = clock;
 556                                                 err = this_err;
 557                                         }
 558                                 }
 559                         }
 560                 }
 561         }
 562
 563         return (err != target);
 564 }
 565
 566 static bool
 567 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 568                    int target, int refclk, intel_clock_t *match_clock,
 569                    intel_clock_t *best_clock)
 570 {
 571         struct drm_device *dev = crtc->dev;
 572         intel_clock_t clock;
 573         int err = target;
 574
 575         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 576                 /*
 577                  * For LVDS just rely on its current settings for dual-channel.
 578                  * We haven't figured out how to reliably set up different
 579                  * single/dual channel state, if we even can.
 580                  */
 581                 if (intel_is_dual_link_lvds(dev))
 582                         clock.p2 = limit->p2.p2_fast;
 583                 else
 584                         clock.p2 = limit->p2.p2_slow;
 585         } else {
 586                 if (target < limit->p2.dot_limit)
 587                         clock.p2 = limit->p2.p2_slow;
 588                 else
 589                         clock.p2 = limit->p2.p2_fast;
 590         }
 591
 592         memset(best_clock, 0, sizeof(*best_clock));
 593
 594         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 595              clock.m1++) {
 596                 for (clock.m2 = limit->m2.min;
 597                      clock.m2 <= limit->m2.max; clock.m2++) {
 598                         for (clock.n = limit->n.min;
 599                              clock.n <= limit->n.max; clock.n++) {
 600                                 for (clock.p1 = limit->p1.min;
 601                                         clock.p1 <= limit->p1.max; clock.p1++) {
 602                                         int this_err;
 603
 604                                         pineview_clock(refclk, &clock);
 605                                         if (!intel_PLL_is_valid(dev, limit,
 606                                                                 &clock))
 607                                                 continue;
 608                                         if (match_clock &&
 609                                             clock.p != match_clock->p)
 610                                                 continue;
 611
 612                                         this_err = abs(clock.dot - target);
 613                                         if (this_err < err) {
 614                                                 *best_clock = clock;
 615                                                 err = this_err;
 616                                         }
 617                                 }
 618                         }
 619                 }
 620         }
 621
 622         return (err != target);
 623 }
 624
 625 static bool
 626 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                    int target, int refclk, intel_clock_t *match_clock,
 628                    intel_clock_t *best_clock)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         intel_clock_t clock;
 632         int max_n;
 633         bool found;
 634         /* approximately equals target * 0.00585 */
 635         int err_most = (target >> 8) + (target >> 9);
 636         found = false;
 637
 638         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 639                 if (intel_is_dual_link_lvds(dev))
 640                         clock.p2 = limit->p2.p2_fast;
 641                 else
 642                         clock.p2 = limit->p2.p2_slow;
 643         } else {
 644                 if (target < limit->p2.dot_limit)
 645                         clock.p2 = limit->p2.p2_slow;
 646                 else
 647                         clock.p2 = limit->p2.p2_fast;
 648         }
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651         max_n = limit->n.max;
 652         /* based on hardware requirement, prefer smaller n to precision */
 653         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 654                 /* based on hardware requirement, prefere larger m1,m2 */
 655                 for (clock.m1 = limit->m1.max;
 656                      clock.m1 >= limit->m1.min; clock.m1--) {
 657                         for (clock.m2 = limit->m2.max;
 658                              clock.m2 >= limit->m2.min; clock.m2--) {
 659                                 for (clock.p1 = limit->p1.max;
 660                                      clock.p1 >= limit->p1.min; clock.p1--) {
 661                                         int this_err;
 662
 663                                         i9xx_clock(refclk, &clock);
 664                                         if (!intel_PLL_is_valid(dev, limit,
 665                                                                 &clock))
 666                                                 continue;
 667
 668                                         this_err = abs(clock.dot - target);
 669                                         if (this_err < err_most) {
 670                                                 *best_clock = clock;
 671                                                 err_most = this_err;
 672                                                 max_n = clock.n;
 673                                                 found = true;
 674                                         }
 675                                 }
 676                         }
 677                 }
 678         }
 679         return found;
 680 }
 681
 682 static bool
 683 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                    int target, int refclk, intel_clock_t *match_clock,
 685                    intel_clock_t *best_clock)
 686 {
 687         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 688         u32 m, n, fastclk;
 689         u32 updrate, minupdate, fracbits, p;
 690         unsigned long bestppm, ppm, absppm;
 691         int dotclk, flag;
 692
 693         flag = 0;
 694         dotclk = target * 1000;
 695         bestppm = 1000000;
 696         ppm = absppm = 0;
 697         fastclk = dotclk / (2*100);
 698         updrate = 0;
 699         minupdate = 19200;
 700         fracbits = 1;
 701         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 702         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 703
 704         /* based on hardware requirement, prefer smaller n to precision */
 705         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 706                 updrate = refclk / n;
 707                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 708                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 709                                 if (p2 > 10)
 710                                         p2 = p2 - 1;
 711                                 p = p1 * p2;
 712                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 713                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 714                                         m2 = (((2*(fastclk * p * n / m1 )) +
 715                                                refclk) / (2*refclk));
 716                                         m = m1 * m2;
 717                                         vco = updrate * m;
 718                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 719                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 720                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 721                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 722                                                         bestppm = 0;
 723                                                         flag = 1;
 724                                                 }
 725                                                 if (absppm < bestppm - 10) {
 726                                                         bestppm = absppm;
 727                                                         flag = 1;
 728                                                 }
 729                                                 if (flag) {
 730                                                         bestn = n;
 731                                                         bestm1 = m1;
 732                                                         bestm2 = m2;
 733                                                         bestp1 = p1;
 734                                                         bestp2 = p2;
 735                                                         flag = 0;
 736                                                 }
 737                                         }
 738                                 }
 739                         }
 740                 }
 741         }
 742         best_clock->n = bestn;
 743         best_clock->m1 = bestm1;
 744         best_clock->m2 = bestm2;
 745         best_clock->p1 = bestp1;
 746         best_clock->p2 = bestp2;
 747
 748         return true;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPEFRAME(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 DRM_DEBUG_KMS("vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (INTEL_INFO(dev)->gen >= 5) {
 785                 ironlake_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 /*
 813  * intel_wait_for_pipe_off - wait for pipe to turn off
 814  * @dev: drm device
 815  * @pipe: pipe to wait for
 816  *
 817  * After disabling a pipe, we can't wait for vblank in the usual way,
 818  * spinning on the vblank interrupt status bit, since we won't actually
 819  * see an interrupt when the pipe is disabled.
 820  *
 821  * On Gen4 and above:
 822  *   wait for the pipe register state bit to turn off
 823  *
 824  * Otherwise:
 825  *   wait for the display line value to settle (it usually
 826  *   ends up stopping at the start of the next frame).
 827  *
 828  */
 829 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 830 {
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 833                                                                       pipe);
 834
 835         if (INTEL_INFO(dev)->gen >= 4) {
 836                 int reg = PIPECONF(cpu_transcoder);
 837
 838                 /* Wait for the Pipe State to go off */
 839                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 840                              100))
 841                         WARN(1, "pipe_off wait timed out\n");
 842         } else {
 843                 u32 last_line, line_mask;
 844                 int reg = PIPEDSL(pipe);
 845                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 846
 847                 if (IS_GEN2(dev))
 848                         line_mask = DSL_LINEMASK_GEN2;
 849                 else
 850                         line_mask = DSL_LINEMASK_GEN3;
 851
 852                 /* Wait for the display line to settle */
 853                 do {
 854                         last_line = I915_READ(reg) & line_mask;
 855                         mdelay(5);
 856                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 857                          time_after(timeout, jiffies));
 858                 if (time_after(jiffies, timeout))
 859                         WARN(1, "pipe_off wait timed out\n");
 860         }
 861 }
 862
 863 /*
 864  * ibx_digital_port_connected - is the specified port connected?
 865  * @dev_priv: i915 private structure
 866  * @port: the port to test
 867  *
 868  * Returns true if @port is connected, false otherwise.
 869  */
 870 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 871                                 struct intel_digital_port *port)
 872 {
 873         u32 bit;
 874
 875         if (HAS_PCH_IBX(dev_priv->dev)) {
 876                 switch(port->port) {
 877                 case PORT_B:
 878                         bit = SDE_PORTB_HOTPLUG;
 879                         break;
 880                 case PORT_C:
 881                         bit = SDE_PORTC_HOTPLUG;
 882                         break;
 883                 case PORT_D:
 884                         bit = SDE_PORTD_HOTPLUG;
 885                         break;
 886                 default:
 887                         return true;
 888                 }
 889         } else {
 890                 switch(port->port) {
 891                 case PORT_B:
 892                         bit = SDE_PORTB_HOTPLUG_CPT;
 893                         break;
 894                 case PORT_C:
 895                         bit = SDE_PORTC_HOTPLUG_CPT;
 896                         break;
 897                 case PORT_D:
 898                         bit = SDE_PORTD_HOTPLUG_CPT;
 899                         break;
 900                 default:
 901                         return true;
 902                 }
 903         }
 904
 905         return I915_READ(SDEISR) & bit;
 906 }
 907
 908 static const char *state_string(bool enabled)
 909 {
 910         return enabled ? "on" : "off";
 911 }
 912
 913 /* Only for pre-ILK configs */
 914 void assert_pll(struct drm_i915_private *dev_priv,
 915                 enum pipe pipe, bool state)
 916 {
 917         int reg;
 918         u32 val;
 919         bool cur_state;
 920
 921         reg = DPLL(pipe);
 922         val = I915_READ(reg);
 923         cur_state = !!(val & DPLL_VCO_ENABLE);
 924         WARN(cur_state != state,
 925              "PLL state assertion failure (expected %s, current %s)\n",
 926              state_string(state), state_string(cur_state));
 927 }
 928
 929 struct intel_shared_dpll *
 930 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 931 {
 932         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 933
 934         if (crtc->config.shared_dpll < 0)
 935                 return NULL;
 936
 937         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 938 }
 939
 940 /* For ILK+ */
 941 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 942                         struct intel_shared_dpll *pll,
 943                         bool state)
 944 {
 945         bool cur_state;
 946         struct intel_dpll_hw_state hw_state;
 947
 948         if (HAS_PCH_LPT(dev_priv->dev)) {
 949                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 950                 return;
 951         }
 952
 953         if (WARN (!pll,
 954                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 955                 return;
 956
 957         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 958         WARN(cur_state != state,
 959              "%s assertion failure (expected %s, current %s)\n",
 960              pll->name, state_string(state), state_string(cur_state));
 961 }
 962
 963 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 964                           enum pipe pipe, bool state)
 965 {
 966         int reg;
 967         u32 val;
 968         bool cur_state;
 969         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 970                                                                       pipe);
 971
 972         if (HAS_DDI(dev_priv->dev)) {
 973                 /* DDI does not have a specific FDI_TX register */
 974                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 975                 val = I915_READ(reg);
 976                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 977         } else {
 978                 reg = FDI_TX_CTL(pipe);
 979                 val = I915_READ(reg);
 980                 cur_state = !!(val & FDI_TX_ENABLE);
 981         }
 982         WARN(cur_state != state,
 983              "FDI TX state assertion failure (expected %s, current %s)\n",
 984              state_string(state), state_string(cur_state));
 985 }
 986 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 987 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 988
 989 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 990                           enum pipe pipe, bool state)
 991 {
 992         int reg;
 993         u32 val;
 994         bool cur_state;
 995
 996         reg = FDI_RX_CTL(pipe);
 997         val = I915_READ(reg);
 998         cur_state = !!(val & FDI_RX_ENABLE);
 999         WARN(cur_state != state,
1000              "FDI RX state assertion failure (expected %s, current %s)\n",
1001              state_string(state), state_string(cur_state));
1002 }
1003 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1004 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1005
1006 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1007                                       enum pipe pipe)
1008 {
1009         int reg;
1010         u32 val;
1011
1012         /* ILK FDI PLL is always enabled */
1013         if (dev_priv->info->gen == 5)
1014                 return;
1015
1016         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1017         if (HAS_DDI(dev_priv->dev))
1018                 return;
1019
1020         reg = FDI_TX_CTL(pipe);
1021         val = I915_READ(reg);
1022         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1023 }
1024
1025 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1026                        enum pipe pipe, bool state)
1027 {
1028         int reg;
1029         u32 val;
1030         bool cur_state;
1031
1032         reg = FDI_RX_CTL(pipe);
1033         val = I915_READ(reg);
1034         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1035         WARN(cur_state != state,
1036              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1037              state_string(state), state_string(cur_state));
1038 }
1039
1040 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1041                                   enum pipe pipe)
1042 {
1043         int pp_reg, lvds_reg;
1044         u32 val;
1045         enum pipe panel_pipe = PIPE_A;
1046         bool locked = true;
1047
1048         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1049                 pp_reg = PCH_PP_CONTROL;
1050                 lvds_reg = PCH_LVDS;
1051         } else {
1052                 pp_reg = PP_CONTROL;
1053                 lvds_reg = LVDS;
1054         }
1055
1056         val = I915_READ(pp_reg);
1057         if (!(val & PANEL_POWER_ON) ||
1058             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1059                 locked = false;
1060
1061         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1062                 panel_pipe = PIPE_B;
1063
1064         WARN(panel_pipe == pipe && locked,
1065              "panel assertion failure, pipe %c regs locked\n",
1066              pipe_name(pipe));
1067 }
1068
1069 void assert_pipe(struct drm_i915_private *dev_priv,
1070                  enum pipe pipe, bool state)
1071 {
1072         int reg;
1073         u32 val;
1074         bool cur_state;
1075         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1076                                                                       pipe);
1077
1078         /* if we need the pipe A quirk it must be always on */
1079         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1080                 state = true;
1081
1082         if (!intel_display_power_enabled(dev_priv->dev,
1083                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1084                 cur_state = false;
1085         } else {
1086                 reg = PIPECONF(cpu_transcoder);
1087                 val = I915_READ(reg);
1088                 cur_state = !!(val & PIPECONF_ENABLE);
1089         }
1090
1091         WARN(cur_state != state,
1092              "pipe %c assertion failure (expected %s, current %s)\n",
1093              pipe_name(pipe), state_string(state), state_string(cur_state));
1094 }
1095
1096 static void assert_plane(struct drm_i915_private *dev_priv,
1097                          enum plane plane, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = DSPCNTR(plane);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1106         WARN(cur_state != state,
1107              "plane %c assertion failure (expected %s, current %s)\n",
1108              plane_name(plane), state_string(state), state_string(cur_state));
1109 }
1110
1111 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1112 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1113
1114 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1115                                    enum pipe pipe)
1116 {
1117         struct drm_device *dev = dev_priv->dev;
1118         int reg, i;
1119         u32 val;
1120         int cur_pipe;
1121
1122         /* Primary planes are fixed to pipes on gen4+ */
1123         if (INTEL_INFO(dev)->gen >= 4) {
1124                 reg = DSPCNTR(pipe);
1125                 val = I915_READ(reg);
1126                 WARN((val & DISPLAY_PLANE_ENABLE),
1127                      "plane %c assertion failure, should be disabled but not\n",
1128                      plane_name(pipe));
1129                 return;
1130         }
1131
1132         /* Need to check both planes against the pipe */
1133         for_each_pipe(i) {
1134                 reg = DSPCNTR(i);
1135                 val = I915_READ(reg);
1136                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1137                         DISPPLANE_SEL_PIPE_SHIFT;
1138                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1139                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1140                      plane_name(i), pipe_name(pipe));
1141         }
1142 }
1143
1144 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1145                                     enum pipe pipe)
1146 {
1147         struct drm_device *dev = dev_priv->dev;
1148         int reg, i;
1149         u32 val;
1150
1151         if (IS_VALLEYVIEW(dev)) {
1152                 for (i = 0; i < dev_priv->num_plane; i++) {
1153                         reg = SPCNTR(pipe, i);
1154                         val = I915_READ(reg);
1155                         WARN((val & SP_ENABLE),
1156                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1157                              sprite_name(pipe, i), pipe_name(pipe));
1158                 }
1159         } else if (INTEL_INFO(dev)->gen >= 7) {
1160                 reg = SPRCTL(pipe);
1161                 val = I915_READ(reg);
1162                 WARN((val & SPRITE_ENABLE),
1163                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1164                      plane_name(pipe), pipe_name(pipe));
1165         } else if (INTEL_INFO(dev)->gen >= 5) {
1166                 reg = DVSCNTR(pipe);
1167                 val = I915_READ(reg);
1168                 WARN((val & DVS_ENABLE),
1169                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(pipe), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1175 {
1176         u32 val;
1177         bool enabled;
1178
1179         if (HAS_PCH_LPT(dev_priv->dev)) {
1180                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1181                 return;
1182         }
1183
1184         val = I915_READ(PCH_DREF_CONTROL);
1185         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1186                             DREF_SUPERSPREAD_SOURCE_MASK));
1187         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1188 }
1189
1190 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1191                                            enum pipe pipe)
1192 {
1193         int reg;
1194         u32 val;
1195         bool enabled;
1196
1197         reg = PCH_TRANSCONF(pipe);
1198         val = I915_READ(reg);
1199         enabled = !!(val & TRANS_ENABLE);
1200         WARN(enabled,
1201              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1202              pipe_name(pipe));
1203 }
1204
1205 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1206                             enum pipe pipe, u32 port_sel, u32 val)
1207 {
1208         if ((val & DP_PORT_EN) == 0)
1209                 return false;
1210
1211         if (HAS_PCH_CPT(dev_priv->dev)) {
1212                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1213                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1214                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1215                         return false;
1216         } else {
1217                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1218                         return false;
1219         }
1220         return true;
1221 }
1222
1223 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1224                               enum pipe pipe, u32 val)
1225 {
1226         if ((val & SDVO_ENABLE) == 0)
1227                 return false;
1228
1229         if (HAS_PCH_CPT(dev_priv->dev)) {
1230                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1231                         return false;
1232         } else {
1233                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1234                         return false;
1235         }
1236         return true;
1237 }
1238
1239 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1240                               enum pipe pipe, u32 val)
1241 {
1242         if ((val & LVDS_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1247                         return false;
1248         } else {
1249                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1250                         return false;
1251         }
1252         return true;
1253 }
1254
1255 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1256                               enum pipe pipe, u32 val)
1257 {
1258         if ((val & ADPA_DAC_ENABLE) == 0)
1259                 return false;
1260         if (HAS_PCH_CPT(dev_priv->dev)) {
1261                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1262                         return false;
1263         } else {
1264                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1265                         return false;
1266         }
1267         return true;
1268 }
1269
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271                                    enum pipe pipe, int reg, u32 port_sel)
1272 {
1273         u32 val = I915_READ(reg);
1274         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1275              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276              reg, pipe_name(pipe));
1277
1278         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1279              && (val & DP_PIPEB_SELECT),
1280              "IBX PCH dp port still using transcoder B\n");
1281 }
1282
1283 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1284                                      enum pipe pipe, int reg)
1285 {
1286         u32 val = I915_READ(reg);
1287         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1288              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1289              reg, pipe_name(pipe));
1290
1291         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1292              && (val & SDVO_PIPE_B_SELECT),
1293              "IBX PCH hdmi port still using transcoder B\n");
1294 }
1295
1296 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1297                                       enum pipe pipe)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1303         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1304         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1305
1306         reg = PCH_ADPA;
1307         val = I915_READ(reg);
1308         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1309              "PCH VGA enabled on transcoder %c, should be disabled\n",
1310              pipe_name(pipe));
1311
1312         reg = PCH_LVDS;
1313         val = I915_READ(reg);
1314         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1315              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1316              pipe_name(pipe));
1317
1318         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1319         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1320         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1321 }
1322
1323 static void vlv_enable_pll(struct intel_crtc *crtc)
1324 {
1325         struct drm_device *dev = crtc->base.dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         int reg = DPLL(crtc->pipe);
1328         u32 dpll = crtc->config.dpll_hw_state.dpll;
1329
1330         assert_pipe_disabled(dev_priv, crtc->pipe);
1331
1332         /* No really, not for ILK+ */
1333         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1334
1335         /* PLL is protected by panel, make sure we can write it */
1336         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1337                 assert_panel_unlocked(dev_priv, crtc->pipe);
1338
1339         I915_WRITE(reg, dpll);
1340         POSTING_READ(reg);
1341         udelay(150);
1342
1343         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1344                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1345
1346         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1347         POSTING_READ(DPLL_MD(crtc->pipe));
1348
1349         /* We do this three times for luck */
1350         I915_WRITE(reg, dpll);
1351         POSTING_READ(reg);
1352         udelay(150); /* wait for warmup */
1353         I915_WRITE(reg, dpll);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, dpll);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359 }
1360
1361 static void i9xx_enable_pll(struct intel_crtc *crtc)
1362 {
1363         struct drm_device *dev = crtc->base.dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         int reg = DPLL(crtc->pipe);
1366         u32 dpll = crtc->config.dpll_hw_state.dpll;
1367
1368         assert_pipe_disabled(dev_priv, crtc->pipe);
1369
1370         /* No really, not for ILK+ */
1371         BUG_ON(dev_priv->info->gen >= 5);
1372
1373         /* PLL is protected by panel, make sure we can write it */
1374         if (IS_MOBILE(dev) && !IS_I830(dev))
1375                 assert_panel_unlocked(dev_priv, crtc->pipe);
1376
1377         I915_WRITE(reg, dpll);
1378
1379         /* Wait for the clocks to stabilize. */
1380         POSTING_READ(reg);
1381         udelay(150);
1382
1383         if (INTEL_INFO(dev)->gen >= 4) {
1384                 I915_WRITE(DPLL_MD(crtc->pipe),
1385                            crtc->config.dpll_hw_state.dpll_md);
1386         } else {
1387                 /* The pixel multiplier can only be updated once the
1388                  * DPLL is enabled and the clocks are stable.
1389                  *
1390                  * So write it again.
1391                  */
1392                 I915_WRITE(reg, dpll);
1393         }
1394
1395         /* We do this three times for luck */
1396         I915_WRITE(reg, dpll);
1397         POSTING_READ(reg);
1398         udelay(150); /* wait for warmup */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405 }
1406
1407 /**
1408  * i9xx_disable_pll - disable a PLL
1409  * @dev_priv: i915 private structure
1410  * @pipe: pipe PLL to disable
1411  *
1412  * Disable the PLL for @pipe, making sure the pipe is off first.
1413  *
1414  * Note!  This is for pre-ILK only.
1415  */
1416 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1417 {
1418         /* Don't disable pipe A or pipe A PLLs if needed */
1419         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1420                 return;
1421
1422         /* Make sure the pipe isn't still relying on us */
1423         assert_pipe_disabled(dev_priv, pipe);
1424
1425         I915_WRITE(DPLL(pipe), 0);
1426         POSTING_READ(DPLL(pipe));
1427 }
1428
1429 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1430 {
1431         u32 port_mask;
1432
1433         if (!port)
1434                 port_mask = DPLL_PORTB_READY_MASK;
1435         else
1436                 port_mask = DPLL_PORTC_READY_MASK;
1437
1438         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1439                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1440                      'B' + port, I915_READ(DPLL(0)));
1441 }
1442
1443 /**
1444  * ironlake_enable_shared_dpll - enable PCH PLL
1445  * @dev_priv: i915 private structure
1446  * @pipe: pipe PLL to enable
1447  *
1448  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1449  * drives the transcoder clock.
1450  */
1451 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1452 {
1453         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1454         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1455
1456         /* PCH PLLs only available on ILK, SNB and IVB */
1457         BUG_ON(dev_priv->info->gen < 5);
1458         if (WARN_ON(pll == NULL))
1459                 return;
1460
1461         if (WARN_ON(pll->refcount == 0))
1462                 return;
1463
1464         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1465                       pll->name, pll->active, pll->on,
1466                       crtc->base.base.id);
1467
1468         if (pll->active++) {
1469                 WARN_ON(!pll->on);
1470                 assert_shared_dpll_enabled(dev_priv, pll);
1471                 return;
1472         }
1473         WARN_ON(pll->on);
1474
1475         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1476         pll->enable(dev_priv, pll);
1477         pll->on = true;
1478 }
1479
1480 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1481 {
1482         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1483         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1484
1485         /* PCH only available on ILK+ */
1486         BUG_ON(dev_priv->info->gen < 5);
1487         if (WARN_ON(pll == NULL))
1488                return;
1489
1490         if (WARN_ON(pll->refcount == 0))
1491                 return;
1492
1493         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1494                       pll->name, pll->active, pll->on,
1495                       crtc->base.base.id);
1496
1497         if (WARN_ON(pll->active == 0)) {
1498                 assert_shared_dpll_disabled(dev_priv, pll);
1499                 return;
1500         }
1501
1502         assert_shared_dpll_enabled(dev_priv, pll);
1503         WARN_ON(!pll->on);
1504         if (--pll->active)
1505                 return;
1506
1507         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1508         pll->disable(dev_priv, pll);
1509         pll->on = false;
1510 }
1511
1512 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1513                                            enum pipe pipe)
1514 {
1515         struct drm_device *dev = dev_priv->dev;
1516         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1518         uint32_t reg, val, pipeconf_val;
1519
1520         /* PCH only available on ILK+ */
1521         BUG_ON(dev_priv->info->gen < 5);
1522
1523         /* Make sure PCH DPLL is enabled */
1524         assert_shared_dpll_enabled(dev_priv,
1525                                    intel_crtc_to_shared_dpll(intel_crtc));
1526
1527         /* FDI must be feeding us bits for PCH ports */
1528         assert_fdi_tx_enabled(dev_priv, pipe);
1529         assert_fdi_rx_enabled(dev_priv, pipe);
1530
1531         if (HAS_PCH_CPT(dev)) {
1532                 /* Workaround: Set the timing override bit before enabling the
1533                  * pch transcoder. */
1534                 reg = TRANS_CHICKEN2(pipe);
1535                 val = I915_READ(reg);
1536                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1537                 I915_WRITE(reg, val);
1538         }
1539
1540         reg = PCH_TRANSCONF(pipe);
1541         val = I915_READ(reg);
1542         pipeconf_val = I915_READ(PIPECONF(pipe));
1543
1544         if (HAS_PCH_IBX(dev_priv->dev)) {
1545                 /*
1546                  * make the BPC in transcoder be consistent with
1547                  * that in pipeconf reg.
1548                  */
1549                 val &= ~PIPECONF_BPC_MASK;
1550                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1551         }
1552
1553         val &= ~TRANS_INTERLACE_MASK;
1554         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1555                 if (HAS_PCH_IBX(dev_priv->dev) &&
1556                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1557                         val |= TRANS_LEGACY_INTERLACED_ILK;
1558                 else
1559                         val |= TRANS_INTERLACED;
1560         else
1561                 val |= TRANS_PROGRESSIVE;
1562
1563         I915_WRITE(reg, val | TRANS_ENABLE);
1564         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1565                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1566 }
1567
1568 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1569                                       enum transcoder cpu_transcoder)
1570 {
1571         u32 val, pipeconf_val;
1572
1573         /* PCH only available on ILK+ */
1574         BUG_ON(dev_priv->info->gen < 5);
1575
1576         /* FDI must be feeding us bits for PCH ports */
1577         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1578         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1579
1580         /* Workaround: set timing override bit. */
1581         val = I915_READ(_TRANSA_CHICKEN2);
1582         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1583         I915_WRITE(_TRANSA_CHICKEN2, val);
1584
1585         val = TRANS_ENABLE;
1586         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1587
1588         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1589             PIPECONF_INTERLACED_ILK)
1590                 val |= TRANS_INTERLACED;
1591         else
1592                 val |= TRANS_PROGRESSIVE;
1593
1594         I915_WRITE(LPT_TRANSCONF, val);
1595         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1596                 DRM_ERROR("Failed to enable PCH transcoder\n");
1597 }
1598
1599 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1600                                             enum pipe pipe)
1601 {
1602         struct drm_device *dev = dev_priv->dev;
1603         uint32_t reg, val;
1604
1605         /* FDI relies on the transcoder */
1606         assert_fdi_tx_disabled(dev_priv, pipe);
1607         assert_fdi_rx_disabled(dev_priv, pipe);
1608
1609         /* Ports must be off as well */
1610         assert_pch_ports_disabled(dev_priv, pipe);
1611
1612         reg = PCH_TRANSCONF(pipe);
1613         val = I915_READ(reg);
1614         val &= ~TRANS_ENABLE;
1615         I915_WRITE(reg, val);
1616         /* wait for PCH transcoder off, transcoder state */
1617         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1618                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1619
1620         if (!HAS_PCH_IBX(dev)) {
1621                 /* Workaround: Clear the timing override chicken bit again. */
1622                 reg = TRANS_CHICKEN2(pipe);
1623                 val = I915_READ(reg);
1624                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1625                 I915_WRITE(reg, val);
1626         }
1627 }
1628
1629 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1630 {
1631         u32 val;
1632
1633         val = I915_READ(LPT_TRANSCONF);
1634         val &= ~TRANS_ENABLE;
1635         I915_WRITE(LPT_TRANSCONF, val);
1636         /* wait for PCH transcoder off, transcoder state */
1637         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1638                 DRM_ERROR("Failed to disable PCH transcoder\n");
1639
1640         /* Workaround: clear timing override bit. */
1641         val = I915_READ(_TRANSA_CHICKEN2);
1642         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1643         I915_WRITE(_TRANSA_CHICKEN2, val);
1644 }
1645
1646 /**
1647  * intel_enable_pipe - enable a pipe, asserting requirements
1648  * @dev_priv: i915 private structure
1649  * @pipe: pipe to enable
1650  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1651  *
1652  * Enable @pipe, making sure that various hardware specific requirements
1653  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1654  *
1655  * @pipe should be %PIPE_A or %PIPE_B.
1656  *
1657  * Will wait until the pipe is actually running (i.e. first vblank) before
1658  * returning.
1659  */
1660 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1661                               bool pch_port)
1662 {
1663         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1664                                                                       pipe);
1665         enum pipe pch_transcoder;
1666         int reg;
1667         u32 val;
1668
1669         assert_planes_disabled(dev_priv, pipe);
1670         assert_sprites_disabled(dev_priv, pipe);
1671
1672         if (HAS_PCH_LPT(dev_priv->dev))
1673                 pch_transcoder = TRANSCODER_A;
1674         else
1675                 pch_transcoder = pipe;
1676
1677         /*
1678          * A pipe without a PLL won't actually be able to drive bits from
1679          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1680          * need the check.
1681          */
1682         if (!HAS_PCH_SPLIT(dev_priv->dev))
1683                 assert_pll_enabled(dev_priv, pipe);
1684         else {
1685                 if (pch_port) {
1686                         /* if driving the PCH, we need FDI enabled */
1687                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1688                         assert_fdi_tx_pll_enabled(dev_priv,
1689                                                   (enum pipe) cpu_transcoder);
1690                 }
1691                 /* FIXME: assert CPU port conditions for SNB+ */
1692         }
1693
1694         reg = PIPECONF(cpu_transcoder);
1695         val = I915_READ(reg);
1696         if (val & PIPECONF_ENABLE)
1697                 return;
1698
1699         I915_WRITE(reg, val | PIPECONF_ENABLE);
1700         intel_wait_for_vblank(dev_priv->dev, pipe);
1701 }
1702
1703 /**
1704  * intel_disable_pipe - disable a pipe, asserting requirements
1705  * @dev_priv: i915 private structure
1706  * @pipe: pipe to disable
1707  *
1708  * Disable @pipe, making sure that various hardware specific requirements
1709  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1710  *
1711  * @pipe should be %PIPE_A or %PIPE_B.
1712  *
1713  * Will wait until the pipe has shut down before returning.
1714  */
1715 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1716                                enum pipe pipe)
1717 {
1718         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1719                                                                       pipe);
1720         int reg;
1721         u32 val;
1722
1723         /*
1724          * Make sure planes won't keep trying to pump pixels to us,
1725          * or we might hang the display.
1726          */
1727         assert_planes_disabled(dev_priv, pipe);
1728         assert_sprites_disabled(dev_priv, pipe);
1729
1730         /* Don't disable pipe A or pipe A PLLs if needed */
1731         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1732                 return;
1733
1734         reg = PIPECONF(cpu_transcoder);
1735         val = I915_READ(reg);
1736         if ((val & PIPECONF_ENABLE) == 0)
1737                 return;
1738
1739         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1740         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1741 }
1742
1743 /*
1744  * Plane regs are double buffered, going from enabled->disabled needs a
1745  * trigger in order to latch.  The display address reg provides this.
1746  */
1747 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1748                                       enum plane plane)
1749 {
1750         if (dev_priv->info->gen >= 4)
1751                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1752         else
1753                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1754 }
1755
1756 /**
1757  * intel_enable_plane - enable a display plane on a given pipe
1758  * @dev_priv: i915 private structure
1759  * @plane: plane to enable
1760  * @pipe: pipe being fed
1761  *
1762  * Enable @plane on @pipe, making sure that @pipe is running first.
1763  */
1764 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1765                                enum plane plane, enum pipe pipe)
1766 {
1767         int reg;
1768         u32 val;
1769
1770         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1771         assert_pipe_enabled(dev_priv, pipe);
1772
1773         reg = DSPCNTR(plane);
1774         val = I915_READ(reg);
1775         if (val & DISPLAY_PLANE_ENABLE)
1776                 return;
1777
1778         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1779         intel_flush_display_plane(dev_priv, plane);
1780         intel_wait_for_vblank(dev_priv->dev, pipe);
1781 }
1782
1783 /**
1784  * intel_disable_plane - disable a display plane
1785  * @dev_priv: i915 private structure
1786  * @plane: plane to disable
1787  * @pipe: pipe consuming the data
1788  *
1789  * Disable @plane; should be an independent operation.
1790  */
1791 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1792                                 enum plane plane, enum pipe pipe)
1793 {
1794         int reg;
1795         u32 val;
1796
1797         reg = DSPCNTR(plane);
1798         val = I915_READ(reg);
1799         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1800                 return;
1801
1802         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1803         intel_flush_display_plane(dev_priv, plane);
1804         intel_wait_for_vblank(dev_priv->dev, pipe);
1805 }
1806
1807 static bool need_vtd_wa(struct drm_device *dev)
1808 {
1809 #ifdef CONFIG_INTEL_IOMMU
1810         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1811                 return true;
1812 #endif
1813         return false;
1814 }
1815
1816 int
1817 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1818                            struct drm_i915_gem_object *obj,
1819                            struct intel_ring_buffer *pipelined)
1820 {
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         u32 alignment;
1823         int ret;
1824
1825         switch (obj->tiling_mode) {
1826         case I915_TILING_NONE:
1827                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1828                         alignment = 128 * 1024;
1829                 else if (INTEL_INFO(dev)->gen >= 4)
1830                         alignment = 4 * 1024;
1831                 else
1832                         alignment = 64 * 1024;
1833                 break;
1834         case I915_TILING_X:
1835                 /* pin() will align the object as required by fence */
1836                 alignment = 0;
1837                 break;
1838         case I915_TILING_Y:
1839                 /* Despite that we check this in framebuffer_init userspace can
1840                  * screw us over and change the tiling after the fact. Only
1841                  * pinned buffers can't change their tiling. */
1842                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1843                 return -EINVAL;
1844         default:
1845                 BUG();
1846         }
1847
1848         /* Note that the w/a also requires 64 PTE of padding following the
1849          * bo. We currently fill all unused PTE with the shadow page and so
1850          * we should always have valid PTE following the scanout preventing
1851          * the VT-d warning.
1852          */
1853         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1854                 alignment = 256 * 1024;
1855
1856         dev_priv->mm.interruptible = false;
1857         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1858         if (ret)
1859                 goto err_interruptible;
1860
1861         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1862          * fence, whereas 965+ only requires a fence if using
1863          * framebuffer compression.  For simplicity, we always install
1864          * a fence as the cost is not that onerous.
1865          */
1866         ret = i915_gem_object_get_fence(obj);
1867         if (ret)
1868                 goto err_unpin;
1869
1870         i915_gem_object_pin_fence(obj);
1871
1872         dev_priv->mm.interruptible = true;
1873         return 0;
1874
1875 err_unpin:
1876         i915_gem_object_unpin(obj);
1877 err_interruptible:
1878         dev_priv->mm.interruptible = true;
1879         return ret;
1880 }
1881
1882 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1883 {
1884         i915_gem_object_unpin_fence(obj);
1885         i915_gem_object_unpin(obj);
1886 }
1887
1888 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1889  * is assumed to be a power-of-two. */
1890 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1891                                              unsigned int tiling_mode,
1892                                              unsigned int cpp,
1893                                              unsigned int pitch)
1894 {
1895         if (tiling_mode != I915_TILING_NONE) {
1896                 unsigned int tile_rows, tiles;
1897
1898                 tile_rows = *y / 8;
1899                 *y %= 8;
1900
1901                 tiles = *x / (512/cpp);
1902                 *x %= 512/cpp;
1903
1904                 return tile_rows * pitch * 8 + tiles * 4096;
1905         } else {
1906                 unsigned int offset;
1907
1908                 offset = *y * pitch + *x * cpp;
1909                 *y = 0;
1910                 *x = (offset & 4095) / cpp;
1911                 return offset & -4096;
1912         }
1913 }
1914
1915 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1916                              int x, int y)
1917 {
1918         struct drm_device *dev = crtc->dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1921         struct intel_framebuffer *intel_fb;
1922         struct drm_i915_gem_object *obj;
1923         int plane = intel_crtc->plane;
1924         unsigned long linear_offset;
1925         u32 dspcntr;
1926         u32 reg;
1927
1928         switch (plane) {
1929         case 0:
1930         case 1:
1931                 break;
1932         default:
1933                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1934                 return -EINVAL;
1935         }
1936
1937         intel_fb = to_intel_framebuffer(fb);
1938         obj = intel_fb->obj;
1939
1940         reg = DSPCNTR(plane);
1941         dspcntr = I915_READ(reg);
1942         /* Mask out pixel format bits in case we change it */
1943         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1944         switch (fb->pixel_format) {
1945         case DRM_FORMAT_C8:
1946                 dspcntr |= DISPPLANE_8BPP;
1947                 break;
1948         case DRM_FORMAT_XRGB1555:
1949         case DRM_FORMAT_ARGB1555:
1950                 dspcntr |= DISPPLANE_BGRX555;
1951                 break;
1952         case DRM_FORMAT_RGB565:
1953                 dspcntr |= DISPPLANE_BGRX565;
1954                 break;
1955         case DRM_FORMAT_XRGB8888:
1956         case DRM_FORMAT_ARGB8888:
1957                 dspcntr |= DISPPLANE_BGRX888;
1958                 break;
1959         case DRM_FORMAT_XBGR8888:
1960         case DRM_FORMAT_ABGR8888:
1961                 dspcntr |= DISPPLANE_RGBX888;
1962                 break;
1963         case DRM_FORMAT_XRGB2101010:
1964         case DRM_FORMAT_ARGB2101010:
1965                 dspcntr |= DISPPLANE_BGRX101010;
1966                 break;
1967         case DRM_FORMAT_XBGR2101010:
1968         case DRM_FORMAT_ABGR2101010:
1969                 dspcntr |= DISPPLANE_RGBX101010;
1970                 break;
1971         default:
1972                 BUG();
1973         }
1974
1975         if (INTEL_INFO(dev)->gen >= 4) {
1976                 if (obj->tiling_mode != I915_TILING_NONE)
1977                         dspcntr |= DISPPLANE_TILED;
1978                 else
1979                         dspcntr &= ~DISPPLANE_TILED;
1980         }
1981
1982         if (IS_G4X(dev))
1983                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1984
1985         I915_WRITE(reg, dspcntr);
1986
1987         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1988
1989         if (INTEL_INFO(dev)->gen >= 4) {
1990                 intel_crtc->dspaddr_offset =
1991                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1992                                                        fb->bits_per_pixel / 8,
1993                                                        fb->pitches[0]);
1994                 linear_offset -= intel_crtc->dspaddr_offset;
1995         } else {
1996                 intel_crtc->dspaddr_offset = linear_offset;
1997         }
1998
1999         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2000                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2001                       fb->pitches[0]);
2002         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2003         if (INTEL_INFO(dev)->gen >= 4) {
2004                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2005                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2006                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2007                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2008         } else
2009                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2010         POSTING_READ(reg);
2011
2012         return 0;
2013 }
2014
2015 static int ironlake_update_plane(struct drm_crtc *crtc,
2016                                  struct drm_framebuffer *fb, int x, int y)
2017 {
2018         struct drm_device *dev = crtc->dev;
2019         struct drm_i915_private *dev_priv = dev->dev_private;
2020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021         struct intel_framebuffer *intel_fb;
2022         struct drm_i915_gem_object *obj;
2023         int plane = intel_crtc->plane;
2024         unsigned long linear_offset;
2025         u32 dspcntr;
2026         u32 reg;
2027
2028         switch (plane) {
2029         case 0:
2030         case 1:
2031         case 2:
2032                 break;
2033         default:
2034                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2035                 return -EINVAL;
2036         }
2037
2038         intel_fb = to_intel_framebuffer(fb);
2039         obj = intel_fb->obj;
2040
2041         reg = DSPCNTR(plane);
2042         dspcntr = I915_READ(reg);
2043         /* Mask out pixel format bits in case we change it */
2044         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2045         switch (fb->pixel_format) {
2046         case DRM_FORMAT_C8:
2047                 dspcntr |= DISPPLANE_8BPP;
2048                 break;
2049         case DRM_FORMAT_RGB565:
2050                 dspcntr |= DISPPLANE_BGRX565;
2051                 break;
2052         case DRM_FORMAT_XRGB8888:
2053         case DRM_FORMAT_ARGB8888:
2054                 dspcntr |= DISPPLANE_BGRX888;
2055                 break;
2056         case DRM_FORMAT_XBGR8888:
2057         case DRM_FORMAT_ABGR8888:
2058                 dspcntr |= DISPPLANE_RGBX888;
2059                 break;
2060         case DRM_FORMAT_XRGB2101010:
2061         case DRM_FORMAT_ARGB2101010:
2062                 dspcntr |= DISPPLANE_BGRX101010;
2063                 break;
2064         case DRM_FORMAT_XBGR2101010:
2065         case DRM_FORMAT_ABGR2101010:
2066                 dspcntr |= DISPPLANE_RGBX101010;
2067                 break;
2068         default:
2069                 BUG();
2070         }
2071
2072         if (obj->tiling_mode != I915_TILING_NONE)
2073                 dspcntr |= DISPPLANE_TILED;
2074         else
2075                 dspcntr &= ~DISPPLANE_TILED;
2076
2077         /* must disable */
2078         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2079
2080         I915_WRITE(reg, dspcntr);
2081
2082         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2083         intel_crtc->dspaddr_offset =
2084                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2085                                                fb->bits_per_pixel / 8,
2086                                                fb->pitches[0]);
2087         linear_offset -= intel_crtc->dspaddr_offset;
2088
2089         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2090                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2091                       fb->pitches[0]);
2092         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2093         I915_MODIFY_DISPBASE(DSPSURF(plane),
2094                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2095         if (IS_HASWELL(dev)) {
2096                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2097         } else {
2098                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2099                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2100         }
2101         POSTING_READ(reg);
2102
2103         return 0;
2104 }
2105
2106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2107 static int
2108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2109                            int x, int y, enum mode_set_atomic state)
2110 {
2111         struct drm_device *dev = crtc->dev;
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114         if (dev_priv->display.disable_fbc)
2115                 dev_priv->display.disable_fbc(dev);
2116         intel_increase_pllclock(crtc);
2117
2118         return dev_priv->display.update_plane(crtc, fb, x, y);
2119 }
2120
2121 void intel_display_handle_reset(struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct drm_crtc *crtc;
2125
2126         /*
2127          * Flips in the rings have been nuked by the reset,
2128          * so complete all pending flips so that user space
2129          * will get its events and not get stuck.
2130          *
2131          * Also update the base address of all primary
2132          * planes to the the last fb to make sure we're
2133          * showing the correct fb after a reset.
2134          *
2135          * Need to make two loops over the crtcs so that we
2136          * don't try to grab a crtc mutex before the
2137          * pending_flip_queue really got woken up.
2138          */
2139
2140         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2141                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2142                 enum plane plane = intel_crtc->plane;
2143
2144                 intel_prepare_page_flip(dev, plane);
2145                 intel_finish_page_flip_plane(dev, plane);
2146         }
2147
2148         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2149                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150
2151                 mutex_lock(&crtc->mutex);
2152                 if (intel_crtc->active)
2153                         dev_priv->display.update_plane(crtc, crtc->fb,
2154                                                        crtc->x, crtc->y);
2155                 mutex_unlock(&crtc->mutex);
2156         }
2157 }
2158
2159 static int
2160 intel_finish_fb(struct drm_framebuffer *old_fb)
2161 {
2162         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2163         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2164         bool was_interruptible = dev_priv->mm.interruptible;
2165         int ret;
2166
2167         /* Big Hammer, we also need to ensure that any pending
2168          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2169          * current scanout is retired before unpinning the old
2170          * framebuffer.
2171          *
2172          * This should only fail upon a hung GPU, in which case we
2173          * can safely continue.
2174          */
2175         dev_priv->mm.interruptible = false;
2176         ret = i915_gem_object_finish_gpu(obj);
2177         dev_priv->mm.interruptible = was_interruptible;
2178
2179         return ret;
2180 }
2181
2182 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2183 {
2184         struct drm_device *dev = crtc->dev;
2185         struct drm_i915_master_private *master_priv;
2186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2187
2188         if (!dev->primary->master)
2189                 return;
2190
2191         master_priv = dev->primary->master->driver_priv;
2192         if (!master_priv->sarea_priv)
2193                 return;
2194
2195         switch (intel_crtc->pipe) {
2196         case 0:
2197                 master_priv->sarea_priv->pipeA_x = x;
2198                 master_priv->sarea_priv->pipeA_y = y;
2199                 break;
2200         case 1:
2201                 master_priv->sarea_priv->pipeB_x = x;
2202                 master_priv->sarea_priv->pipeB_y = y;
2203                 break;
2204         default:
2205                 break;
2206         }
2207 }
2208
2209 static int
2210 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2211                     struct drm_framebuffer *fb)
2212 {
2213         struct drm_device *dev = crtc->dev;
2214         struct drm_i915_private *dev_priv = dev->dev_private;
2215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216         struct drm_framebuffer *old_fb;
2217         int ret;
2218
2219         /* no fb bound */
2220         if (!fb) {
2221                 DRM_ERROR("No FB bound\n");
2222                 return 0;
2223         }
2224
2225         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2226                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2227                           plane_name(intel_crtc->plane),
2228                           INTEL_INFO(dev)->num_pipes);
2229                 return -EINVAL;
2230         }
2231
2232         mutex_lock(&dev->struct_mutex);
2233         ret = intel_pin_and_fence_fb_obj(dev,
2234                                          to_intel_framebuffer(fb)->obj,
2235                                          NULL);
2236         if (ret != 0) {
2237                 mutex_unlock(&dev->struct_mutex);
2238                 DRM_ERROR("pin & fence failed\n");
2239                 return ret;
2240         }
2241
2242         /* Update pipe size and adjust fitter if needed */
2243         if (i915_fastboot) {
2244                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2245                            ((crtc->mode.hdisplay - 1) << 16) |
2246                            (crtc->mode.vdisplay - 1));
2247                 if (!intel_crtc->config.pch_pfit.size &&
2248                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2249                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2250                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2251                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2252                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2253                 }
2254         }
2255
2256         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2257         if (ret) {
2258                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("failed to update base address\n");
2261                 return ret;
2262         }
2263
2264         old_fb = crtc->fb;
2265         crtc->fb = fb;
2266         crtc->x = x;
2267         crtc->y = y;
2268
2269         if (old_fb) {
2270                 if (intel_crtc->active && old_fb != fb)
2271                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2272                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2273         }
2274
2275         intel_update_fbc(dev);
2276         intel_edp_psr_update(dev);
2277         mutex_unlock(&dev->struct_mutex);
2278
2279         intel_crtc_update_sarea_pos(crtc, x, y);
2280
2281         return 0;
2282 }
2283
2284 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         int pipe = intel_crtc->pipe;
2290         u32 reg, temp;
2291
2292         /* enable normal train */
2293         reg = FDI_TX_CTL(pipe);
2294         temp = I915_READ(reg);
2295         if (IS_IVYBRIDGE(dev)) {
2296                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2297                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2298         } else {
2299                 temp &= ~FDI_LINK_TRAIN_NONE;
2300                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2301         }
2302         I915_WRITE(reg, temp);
2303
2304         reg = FDI_RX_CTL(pipe);
2305         temp = I915_READ(reg);
2306         if (HAS_PCH_CPT(dev)) {
2307                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2308                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2309         } else {
2310                 temp &= ~FDI_LINK_TRAIN_NONE;
2311                 temp |= FDI_LINK_TRAIN_NONE;
2312         }
2313         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2314
2315         /* wait one idle pattern time */
2316         POSTING_READ(reg);
2317         udelay(1000);
2318
2319         /* IVB wants error correction enabled */
2320         if (IS_IVYBRIDGE(dev))
2321                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2322                            FDI_FE_ERRC_ENABLE);
2323 }
2324
2325 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2326 {
2327         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2328 }
2329
2330 static void ivb_modeset_global_resources(struct drm_device *dev)
2331 {
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct intel_crtc *pipe_B_crtc =
2334                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2335         struct intel_crtc *pipe_C_crtc =
2336                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2337         uint32_t temp;
2338
2339         /*
2340          * When everything is off disable fdi C so that we could enable fdi B
2341          * with all lanes. Note that we don't care about enabled pipes without
2342          * an enabled pch encoder.
2343          */
2344         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2345             !pipe_has_enabled_pch(pipe_C_crtc)) {
2346                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2347                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2348
2349                 temp = I915_READ(SOUTH_CHICKEN1);
2350                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2351                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2352                 I915_WRITE(SOUTH_CHICKEN1, temp);
2353         }
2354 }
2355
2356 /* The FDI link training functions for ILK/Ibexpeak. */
2357 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2358 {
2359         struct drm_device *dev = crtc->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362         int pipe = intel_crtc->pipe;
2363         int plane = intel_crtc->plane;
2364         u32 reg, temp, tries;
2365
2366         /* FDI needs bits from pipe & plane first */
2367         assert_pipe_enabled(dev_priv, pipe);
2368         assert_plane_enabled(dev_priv, plane);
2369
2370         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2371            for train result */
2372         reg = FDI_RX_IMR(pipe);
2373         temp = I915_READ(reg);
2374         temp &= ~FDI_RX_SYMBOL_LOCK;
2375         temp &= ~FDI_RX_BIT_LOCK;
2376         I915_WRITE(reg, temp);
2377         I915_READ(reg);
2378         udelay(150);
2379
2380         /* enable CPU FDI TX and PCH FDI RX */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2384         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2385         temp &= ~FDI_LINK_TRAIN_NONE;
2386         temp |= FDI_LINK_TRAIN_PATTERN_1;
2387         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2388
2389         reg = FDI_RX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2394
2395         POSTING_READ(reg);
2396         udelay(150);
2397
2398         /* Ironlake workaround, enable clock pointer after FDI enable*/
2399         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2400         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2401                    FDI_RX_PHASE_SYNC_POINTER_EN);
2402
2403         reg = FDI_RX_IIR(pipe);
2404         for (tries = 0; tries < 5; tries++) {
2405                 temp = I915_READ(reg);
2406                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408                 if ((temp & FDI_RX_BIT_LOCK)) {
2409                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2410                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2411                         break;
2412                 }
2413         }
2414         if (tries == 5)
2415                 DRM_ERROR("FDI train 1 fail!\n");
2416
2417         /* Train 2 */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~FDI_LINK_TRAIN_NONE;
2421         temp |= FDI_LINK_TRAIN_PATTERN_2;
2422         I915_WRITE(reg, temp);
2423
2424         reg = FDI_RX_CTL(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_2;
2428         I915_WRITE(reg, temp);
2429
2430         POSTING_READ(reg);
2431         udelay(150);
2432
2433         reg = FDI_RX_IIR(pipe);
2434         for (tries = 0; tries < 5; tries++) {
2435                 temp = I915_READ(reg);
2436                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438                 if (temp & FDI_RX_SYMBOL_LOCK) {
2439                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2440                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2441                         break;
2442                 }
2443         }
2444         if (tries == 5)
2445                 DRM_ERROR("FDI train 2 fail!\n");
2446
2447         DRM_DEBUG_KMS("FDI train done\n");
2448
2449 }
2450
2451 static const int snb_b_fdi_train_param[] = {
2452         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2453         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2454         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2455         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2456 };
2457
2458 /* The FDI link training functions for SNB/Cougarpoint. */
2459 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         int pipe = intel_crtc->pipe;
2465         u32 reg, temp, i, retry;
2466
2467         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468            for train result */
2469         reg = FDI_RX_IMR(pipe);
2470         temp = I915_READ(reg);
2471         temp &= ~FDI_RX_SYMBOL_LOCK;
2472         temp &= ~FDI_RX_BIT_LOCK;
2473         I915_WRITE(reg, temp);
2474
2475         POSTING_READ(reg);
2476         udelay(150);
2477
2478         /* enable CPU FDI TX and PCH FDI RX */
2479         reg = FDI_TX_CTL(pipe);
2480         temp = I915_READ(reg);
2481         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2482         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_1;
2485         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486         /* SNB-B */
2487         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2488         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2489
2490         I915_WRITE(FDI_RX_MISC(pipe),
2491                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2492
2493         reg = FDI_RX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         if (HAS_PCH_CPT(dev)) {
2496                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2498         } else {
2499                 temp &= ~FDI_LINK_TRAIN_NONE;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2501         }
2502         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
2504         POSTING_READ(reg);
2505         udelay(150);
2506
2507         for (i = 0; i < 4; i++) {
2508                 reg = FDI_TX_CTL(pipe);
2509                 temp = I915_READ(reg);
2510                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511                 temp |= snb_b_fdi_train_param[i];
2512                 I915_WRITE(reg, temp);
2513
2514                 POSTING_READ(reg);
2515                 udelay(500);
2516
2517                 for (retry = 0; retry < 5; retry++) {
2518                         reg = FDI_RX_IIR(pipe);
2519                         temp = I915_READ(reg);
2520                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521                         if (temp & FDI_RX_BIT_LOCK) {
2522                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2523                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524                                 break;
2525                         }
2526                         udelay(50);
2527                 }
2528                 if (retry < 5)
2529                         break;
2530         }
2531         if (i == 4)
2532                 DRM_ERROR("FDI train 1 fail!\n");
2533
2534         /* Train 2 */
2535         reg = FDI_TX_CTL(pipe);
2536         temp = I915_READ(reg);
2537         temp &= ~FDI_LINK_TRAIN_NONE;
2538         temp |= FDI_LINK_TRAIN_PATTERN_2;
2539         if (IS_GEN6(dev)) {
2540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541                 /* SNB-B */
2542                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2543         }
2544         I915_WRITE(reg, temp);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         if (HAS_PCH_CPT(dev)) {
2549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2551         } else {
2552                 temp &= ~FDI_LINK_TRAIN_NONE;
2553                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2554         }
2555         I915_WRITE(reg, temp);
2556
2557         POSTING_READ(reg);
2558         udelay(150);
2559
2560         for (i = 0; i < 4; i++) {
2561                 reg = FDI_TX_CTL(pipe);
2562                 temp = I915_READ(reg);
2563                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564                 temp |= snb_b_fdi_train_param[i];
2565                 I915_WRITE(reg, temp);
2566
2567                 POSTING_READ(reg);
2568                 udelay(500);
2569
2570                 for (retry = 0; retry < 5; retry++) {
2571                         reg = FDI_RX_IIR(pipe);
2572                         temp = I915_READ(reg);
2573                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574                         if (temp & FDI_RX_SYMBOL_LOCK) {
2575                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2576                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577                                 break;
2578                         }
2579                         udelay(50);
2580                 }
2581                 if (retry < 5)
2582                         break;
2583         }
2584         if (i == 4)
2585                 DRM_ERROR("FDI train 2 fail!\n");
2586
2587         DRM_DEBUG_KMS("FDI train done.\n");
2588 }
2589
2590 /* Manual link training for Ivy Bridge A0 parts */
2591 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2592 {
2593         struct drm_device *dev = crtc->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596         int pipe = intel_crtc->pipe;
2597         u32 reg, temp, i;
2598
2599         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2600            for train result */
2601         reg = FDI_RX_IMR(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_RX_SYMBOL_LOCK;
2604         temp &= ~FDI_RX_BIT_LOCK;
2605         I915_WRITE(reg, temp);
2606
2607         POSTING_READ(reg);
2608         udelay(150);
2609
2610         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2611                       I915_READ(FDI_RX_IIR(pipe)));
2612
2613         /* enable CPU FDI TX and PCH FDI RX */
2614         reg = FDI_TX_CTL(pipe);
2615         temp = I915_READ(reg);
2616         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2617         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2618         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2619         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2620         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2622         temp |= FDI_COMPOSITE_SYNC;
2623         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625         I915_WRITE(FDI_RX_MISC(pipe),
2626                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_AUTO;
2631         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633         temp |= FDI_COMPOSITE_SYNC;
2634         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636         POSTING_READ(reg);
2637         udelay(150);
2638
2639         for (i = 0; i < 4; i++) {
2640                 reg = FDI_TX_CTL(pipe);
2641                 temp = I915_READ(reg);
2642                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643                 temp |= snb_b_fdi_train_param[i];
2644                 I915_WRITE(reg, temp);
2645
2646                 POSTING_READ(reg);
2647                 udelay(500);
2648
2649                 reg = FDI_RX_IIR(pipe);
2650                 temp = I915_READ(reg);
2651                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652
2653                 if (temp & FDI_RX_BIT_LOCK ||
2654                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2655                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2656                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2657                         break;
2658                 }
2659         }
2660         if (i == 4)
2661                 DRM_ERROR("FDI train 1 fail!\n");
2662
2663         /* Train 2 */
2664         reg = FDI_TX_CTL(pipe);
2665         temp = I915_READ(reg);
2666         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2667         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2668         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2670         I915_WRITE(reg, temp);
2671
2672         reg = FDI_RX_CTL(pipe);
2673         temp = I915_READ(reg);
2674         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2675         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2676         I915_WRITE(reg, temp);
2677
2678         POSTING_READ(reg);
2679         udelay(150);
2680
2681         for (i = 0; i < 4; i++) {
2682                 reg = FDI_TX_CTL(pipe);
2683                 temp = I915_READ(reg);
2684                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685                 temp |= snb_b_fdi_train_param[i];
2686                 I915_WRITE(reg, temp);
2687
2688                 POSTING_READ(reg);
2689                 udelay(500);
2690
2691                 reg = FDI_RX_IIR(pipe);
2692                 temp = I915_READ(reg);
2693                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694
2695                 if (temp & FDI_RX_SYMBOL_LOCK) {
2696                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2697                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2698                         break;
2699                 }
2700         }
2701         if (i == 4)
2702                 DRM_ERROR("FDI train 2 fail!\n");
2703
2704         DRM_DEBUG_KMS("FDI train done.\n");
2705 }
2706
2707 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2708 {
2709         struct drm_device *dev = intel_crtc->base.dev;
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711         int pipe = intel_crtc->pipe;
2712         u32 reg, temp;
2713
2714
2715         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2719         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2720         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2721         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(200);
2725
2726         /* Switch from Rawclk to PCDclk */
2727         temp = I915_READ(reg);
2728         I915_WRITE(reg, temp | FDI_PCDCLK);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Enable CPU FDI TX PLL, always on for Ironlake */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2737                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2738
2739                 POSTING_READ(reg);
2740                 udelay(100);
2741         }
2742 }
2743
2744 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         int pipe = intel_crtc->pipe;
2749         u32 reg, temp;
2750
2751         /* Switch from PCDclk to Rawclk */
2752         reg = FDI_RX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2755
2756         /* Disable CPU FDI TX PLL */
2757         reg = FDI_TX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2760
2761         POSTING_READ(reg);
2762         udelay(100);
2763
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2767
2768         /* Wait for the clocks to turn off. */
2769         POSTING_READ(reg);
2770         udelay(100);
2771 }
2772
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int pipe = intel_crtc->pipe;
2779         u32 reg, temp;
2780
2781         /* disable CPU FDI tx and PCH FDI rx */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785         POSTING_READ(reg);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~(0x7 << 16);
2790         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2791         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         /* Ironlake workaround, disable clock pointer after downing FDI */
2797         if (HAS_PCH_IBX(dev)) {
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799         }
2800
2801         /* still set train pattern 1 */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         temp &= ~FDI_LINK_TRAIN_NONE;
2805         temp |= FDI_LINK_TRAIN_PATTERN_1;
2806         I915_WRITE(reg, temp);
2807
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         if (HAS_PCH_CPT(dev)) {
2811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813         } else {
2814                 temp &= ~FDI_LINK_TRAIN_NONE;
2815                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816         }
2817         /* BPC in FDI rx is consistent with that in PIPECONF */
2818         temp &= ~(0x07 << 16);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824 }
2825
2826 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2831         unsigned long flags;
2832         bool pending;
2833
2834         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2835             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2836                 return false;
2837
2838         spin_lock_irqsave(&dev->event_lock, flags);
2839         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2840         spin_unlock_irqrestore(&dev->event_lock, flags);
2841
2842         return pending;
2843 }
2844
2845 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849
2850         if (crtc->fb == NULL)
2851                 return;
2852
2853         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2854
2855         wait_event(dev_priv->pending_flip_queue,
2856                    !intel_crtc_has_pending_flip(crtc));
2857
2858         mutex_lock(&dev->struct_mutex);
2859         intel_finish_fb(crtc->fb);
2860         mutex_unlock(&dev->struct_mutex);
2861 }
2862
2863 /* Program iCLKIP clock to the desired frequency */
2864 static void lpt_program_iclkip(struct drm_crtc *crtc)
2865 {
2866         struct drm_device *dev = crtc->dev;
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2869         u32 temp;
2870
2871         mutex_lock(&dev_priv->dpio_lock);
2872
2873         /* It is necessary to ungate the pixclk gate prior to programming
2874          * the divisors, and gate it back when it is done.
2875          */
2876         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2877
2878         /* Disable SSCCTL */
2879         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2880                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2881                                 SBI_SSCCTL_DISABLE,
2882                         SBI_ICLK);
2883
2884         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2885         if (crtc->mode.clock == 20000) {
2886                 auxdiv = 1;
2887                 divsel = 0x41;
2888                 phaseinc = 0x20;
2889         } else {
2890                 /* The iCLK virtual clock root frequency is in MHz,
2891                  * but the crtc->mode.clock in in KHz. To get the divisors,
2892                  * it is necessary to divide one by another, so we
2893                  * convert the virtual clock precision to KHz here for higher
2894                  * precision.
2895                  */
2896                 u32 iclk_virtual_root_freq = 172800 * 1000;
2897                 u32 iclk_pi_range = 64;
2898                 u32 desired_divisor, msb_divisor_value, pi_value;
2899
2900                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2901                 msb_divisor_value = desired_divisor / iclk_pi_range;
2902                 pi_value = desired_divisor % iclk_pi_range;
2903
2904                 auxdiv = 0;
2905                 divsel = msb_divisor_value - 2;
2906                 phaseinc = pi_value;
2907         }
2908
2909         /* This should not happen with any sane values */
2910         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2911                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2912         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2913                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2914
2915         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2916                         crtc->mode.clock,
2917                         auxdiv,
2918                         divsel,
2919                         phasedir,
2920                         phaseinc);
2921
2922         /* Program SSCDIVINTPHASE6 */
2923         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2924         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2925         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2926         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2927         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2928         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2929         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2930         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2931
2932         /* Program SSCAUXDIV */
2933         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2934         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2935         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2936         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2937
2938         /* Enable modulator and associated divider */
2939         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2940         temp &= ~SBI_SSCCTL_DISABLE;
2941         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2942
2943         /* Wait for initialization time */
2944         udelay(24);
2945
2946         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2947
2948         mutex_unlock(&dev_priv->dpio_lock);
2949 }
2950
2951 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2952                                                 enum pipe pch_transcoder)
2953 {
2954         struct drm_device *dev = crtc->base.dev;
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2957
2958         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2959                    I915_READ(HTOTAL(cpu_transcoder)));
2960         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2961                    I915_READ(HBLANK(cpu_transcoder)));
2962         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2963                    I915_READ(HSYNC(cpu_transcoder)));
2964
2965         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2966                    I915_READ(VTOTAL(cpu_transcoder)));
2967         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2968                    I915_READ(VBLANK(cpu_transcoder)));
2969         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2970                    I915_READ(VSYNC(cpu_transcoder)));
2971         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2972                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2973 }
2974
2975 /*
2976  * Enable PCH resources required for PCH ports:
2977  *   - PCH PLLs
2978  *   - FDI training & RX/TX
2979  *   - update transcoder timings
2980  *   - DP transcoding bits
2981  *   - transcoder
2982  */
2983 static void ironlake_pch_enable(struct drm_crtc *crtc)
2984 {
2985         struct drm_device *dev = crtc->dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988         int pipe = intel_crtc->pipe;
2989         u32 reg, temp;
2990
2991         assert_pch_transcoder_disabled(dev_priv, pipe);
2992
2993         /* Write the TU size bits before fdi link training, so that error
2994          * detection works. */
2995         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2996                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2997
2998         /* For PCH output, training FDI link */
2999         dev_priv->display.fdi_link_train(crtc);
3000
3001         /* We need to program the right clock selection before writing the pixel
3002          * mutliplier into the DPLL. */
3003         if (HAS_PCH_CPT(dev)) {
3004                 u32 sel;
3005
3006                 temp = I915_READ(PCH_DPLL_SEL);
3007                 temp |= TRANS_DPLL_ENABLE(pipe);
3008                 sel = TRANS_DPLLB_SEL(pipe);
3009                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3010                         temp |= sel;
3011                 else
3012                         temp &= ~sel;
3013                 I915_WRITE(PCH_DPLL_SEL, temp);
3014         }
3015
3016         /* XXX: pch pll's can be enabled any time before we enable the PCH
3017          * transcoder, and we actually should do this to not upset any PCH
3018          * transcoder that already use the clock when we share it.
3019          *
3020          * Note that enable_shared_dpll tries to do the right thing, but
3021          * get_shared_dpll unconditionally resets the pll - we need that to have
3022          * the right LVDS enable sequence. */
3023         ironlake_enable_shared_dpll(intel_crtc);
3024
3025         /* set transcoder timing, panel must allow it */
3026         assert_panel_unlocked(dev_priv, pipe);
3027         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3028
3029         intel_fdi_normal_train(crtc);
3030
3031         /* For PCH DP, enable TRANS_DP_CTL */
3032         if (HAS_PCH_CPT(dev) &&
3033             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3034              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3035                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3036                 reg = TRANS_DP_CTL(pipe);
3037                 temp = I915_READ(reg);
3038                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3039                           TRANS_DP_SYNC_MASK |
3040                           TRANS_DP_BPC_MASK);
3041                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3042                          TRANS_DP_ENH_FRAMING);
3043                 temp |= bpc << 9; /* same format but at 11:9 */
3044
3045                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3046                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3047                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3048                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3049
3050                 switch (intel_trans_dp_port_sel(crtc)) {
3051                 case PCH_DP_B:
3052                         temp |= TRANS_DP_PORT_SEL_B;
3053                         break;
3054                 case PCH_DP_C:
3055                         temp |= TRANS_DP_PORT_SEL_C;
3056                         break;
3057                 case PCH_DP_D:
3058                         temp |= TRANS_DP_PORT_SEL_D;
3059                         break;
3060                 default:
3061                         BUG();
3062                 }
3063
3064                 I915_WRITE(reg, temp);
3065         }
3066
3067         ironlake_enable_pch_transcoder(dev_priv, pipe);
3068 }
3069
3070 static void lpt_pch_enable(struct drm_crtc *crtc)
3071 {
3072         struct drm_device *dev = crtc->dev;
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3076
3077         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3078
3079         lpt_program_iclkip(crtc);
3080
3081         /* Set transcoder timing. */
3082         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3083
3084         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3085 }
3086
3087 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3088 {
3089         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090
3091         if (pll == NULL)
3092                 return;
3093
3094         if (pll->refcount == 0) {
3095                 WARN(1, "bad %s refcount\n", pll->name);
3096                 return;
3097         }
3098
3099         if (--pll->refcount == 0) {
3100                 WARN_ON(pll->on);
3101                 WARN_ON(pll->active);
3102         }
3103
3104         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3105 }
3106
3107 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3108 {
3109         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3110         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3111         enum intel_dpll_id i;
3112
3113         if (pll) {
3114                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3115                               crtc->base.base.id, pll->name);
3116                 intel_put_shared_dpll(crtc);
3117         }
3118
3119         if (HAS_PCH_IBX(dev_priv->dev)) {
3120                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3121                 i = (enum intel_dpll_id) crtc->pipe;
3122                 pll = &dev_priv->shared_dplls[i];
3123
3124                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3125                               crtc->base.base.id, pll->name);
3126
3127                 goto found;
3128         }
3129
3130         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3131                 pll = &dev_priv->shared_dplls[i];
3132
3133                 /* Only want to check enabled timings first */
3134                 if (pll->refcount == 0)
3135                         continue;
3136
3137                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3138                            sizeof(pll->hw_state)) == 0) {
3139                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3140                                       crtc->base.base.id,
3141                                       pll->name, pll->refcount, pll->active);
3142
3143                         goto found;
3144                 }
3145         }
3146
3147         /* Ok no matching timings, maybe there's a free one? */
3148         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3149                 pll = &dev_priv->shared_dplls[i];
3150                 if (pll->refcount == 0) {
3151                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3152                                       crtc->base.base.id, pll->name);
3153                         goto found;
3154                 }
3155         }
3156
3157         return NULL;
3158
3159 found:
3160         crtc->config.shared_dpll = i;
3161         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3162                          pipe_name(crtc->pipe));
3163
3164         if (pll->active == 0) {
3165                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3166                        sizeof(pll->hw_state));
3167
3168                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3169                 WARN_ON(pll->on);
3170                 assert_shared_dpll_disabled(dev_priv, pll);
3171
3172                 pll->mode_set(dev_priv, pll);
3173         }
3174         pll->refcount++;
3175
3176         return pll;
3177 }
3178
3179 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3180 {
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         int dslreg = PIPEDSL(pipe);
3183         u32 temp;
3184
3185         temp = I915_READ(dslreg);
3186         udelay(500);
3187         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3188                 if (wait_for(I915_READ(dslreg) != temp, 5))
3189                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3190         }
3191 }
3192
3193 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->base.dev;
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         int pipe = crtc->pipe;
3198
3199         if (crtc->config.pch_pfit.size) {
3200                 /* Force use of hard-coded filter coefficients
3201                  * as some pre-programmed values are broken,
3202                  * e.g. x201.
3203                  */
3204                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3205                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3206                                                  PF_PIPE_SEL_IVB(pipe));
3207                 else
3208                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3209                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3210                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3211         }
3212 }
3213
3214 static void intel_enable_planes(struct drm_crtc *crtc)
3215 {
3216         struct drm_device *dev = crtc->dev;
3217         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3218         struct intel_plane *intel_plane;
3219
3220         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3221                 if (intel_plane->pipe == pipe)
3222                         intel_plane_restore(&intel_plane->base);
3223 }
3224
3225 static void intel_disable_planes(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3229         struct intel_plane *intel_plane;
3230
3231         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3232                 if (intel_plane->pipe == pipe)
3233                         intel_plane_disable(&intel_plane->base);
3234 }
3235
3236 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         struct intel_encoder *encoder;
3242         int pipe = intel_crtc->pipe;
3243         int plane = intel_crtc->plane;
3244
3245         WARN_ON(!crtc->enabled);
3246
3247         if (intel_crtc->active)
3248                 return;
3249
3250         intel_crtc->active = true;
3251
3252         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3253         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3254
3255         intel_update_watermarks(dev);
3256
3257         for_each_encoder_on_crtc(dev, crtc, encoder)
3258                 if (encoder->pre_enable)
3259                         encoder->pre_enable(encoder);
3260
3261         if (intel_crtc->config.has_pch_encoder) {
3262                 /* Note: FDI PLL enabling _must_ be done before we enable the
3263                  * cpu pipes, hence this is separate from all the other fdi/pch
3264                  * enabling. */
3265                 ironlake_fdi_pll_enable(intel_crtc);
3266         } else {
3267                 assert_fdi_tx_disabled(dev_priv, pipe);
3268                 assert_fdi_rx_disabled(dev_priv, pipe);
3269         }
3270
3271         ironlake_pfit_enable(intel_crtc);
3272
3273         /*
3274          * On ILK+ LUT must be loaded before the pipe is running but with
3275          * clocks enabled
3276          */
3277         intel_crtc_load_lut(crtc);
3278
3279         intel_enable_pipe(dev_priv, pipe,
3280                           intel_crtc->config.has_pch_encoder);
3281         intel_enable_plane(dev_priv, plane, pipe);
3282         intel_enable_planes(crtc);
3283         intel_crtc_update_cursor(crtc, true);
3284
3285         if (intel_crtc->config.has_pch_encoder)
3286                 ironlake_pch_enable(crtc);
3287
3288         mutex_lock(&dev->struct_mutex);
3289         intel_update_fbc(dev);
3290         mutex_unlock(&dev->struct_mutex);
3291
3292         for_each_encoder_on_crtc(dev, crtc, encoder)
3293                 encoder->enable(encoder);
3294
3295         if (HAS_PCH_CPT(dev))
3296                 cpt_verify_modeset(dev, intel_crtc->pipe);
3297
3298         /*
3299          * There seems to be a race in PCH platform hw (at least on some
3300          * outputs) where an enabled pipe still completes any pageflip right
3301          * away (as if the pipe is off) instead of waiting for vblank. As soon
3302          * as the first vblank happend, everything works as expected. Hence just
3303          * wait for one vblank before returning to avoid strange things
3304          * happening.
3305          */
3306         intel_wait_for_vblank(dev, intel_crtc->pipe);
3307 }
3308
3309 /* IPS only exists on ULT machines and is tied to pipe A. */
3310 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3311 {
3312         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3313 }
3314
3315 static void hsw_enable_ips(struct intel_crtc *crtc)
3316 {
3317         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3318
3319         if (!crtc->config.ips_enabled)
3320                 return;
3321
3322         /* We can only enable IPS after we enable a plane and wait for a vblank.
3323          * We guarantee that the plane is enabled by calling intel_enable_ips
3324          * only after intel_enable_plane. And intel_enable_plane already waits
3325          * for a vblank, so all we need to do here is to enable the IPS bit. */
3326         assert_plane_enabled(dev_priv, crtc->plane);
3327         I915_WRITE(IPS_CTL, IPS_ENABLE);
3328 }
3329
3330 static void hsw_disable_ips(struct intel_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->base.dev;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335         if (!crtc->config.ips_enabled)
3336                 return;
3337
3338         assert_plane_enabled(dev_priv, crtc->plane);
3339         I915_WRITE(IPS_CTL, 0);
3340
3341         /* We need to wait for a vblank before we can disable the plane. */
3342         intel_wait_for_vblank(dev, crtc->pipe);
3343 }
3344
3345 static void haswell_crtc_enable(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         struct intel_encoder *encoder;
3351         int pipe = intel_crtc->pipe;
3352         int plane = intel_crtc->plane;
3353
3354         WARN_ON(!crtc->enabled);
3355
3356         if (intel_crtc->active)
3357                 return;
3358
3359         intel_crtc->active = true;
3360
3361         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3362         if (intel_crtc->config.has_pch_encoder)
3363                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3364
3365         intel_update_watermarks(dev);
3366
3367         if (intel_crtc->config.has_pch_encoder)
3368                 dev_priv->display.fdi_link_train(crtc);
3369
3370         for_each_encoder_on_crtc(dev, crtc, encoder)
3371                 if (encoder->pre_enable)
3372                         encoder->pre_enable(encoder);
3373
3374         intel_ddi_enable_pipe_clock(intel_crtc);
3375
3376         ironlake_pfit_enable(intel_crtc);
3377
3378         /*
3379          * On ILK+ LUT must be loaded before the pipe is running but with
3380          * clocks enabled
3381          */
3382         intel_crtc_load_lut(crtc);
3383
3384         intel_ddi_set_pipe_settings(crtc);
3385         intel_ddi_enable_transcoder_func(crtc);
3386
3387         intel_enable_pipe(dev_priv, pipe,
3388                           intel_crtc->config.has_pch_encoder);
3389         intel_enable_plane(dev_priv, plane, pipe);
3390         intel_enable_planes(crtc);
3391         intel_crtc_update_cursor(crtc, true);
3392
3393         hsw_enable_ips(intel_crtc);
3394
3395         if (intel_crtc->config.has_pch_encoder)
3396                 lpt_pch_enable(crtc);
3397
3398         mutex_lock(&dev->struct_mutex);
3399         intel_update_fbc(dev);
3400         mutex_unlock(&dev->struct_mutex);
3401
3402         for_each_encoder_on_crtc(dev, crtc, encoder)
3403                 encoder->enable(encoder);
3404
3405         /*
3406          * There seems to be a race in PCH platform hw (at least on some
3407          * outputs) where an enabled pipe still completes any pageflip right
3408          * away (as if the pipe is off) instead of waiting for vblank. As soon
3409          * as the first vblank happend, everything works as expected. Hence just
3410          * wait for one vblank before returning to avoid strange things
3411          * happening.
3412          */
3413         intel_wait_for_vblank(dev, intel_crtc->pipe);
3414 }
3415
3416 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3417 {
3418         struct drm_device *dev = crtc->base.dev;
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         int pipe = crtc->pipe;
3421
3422         /* To avoid upsetting the power well on haswell only disable the pfit if
3423          * it's in use. The hw state code will make sure we get this right. */
3424         if (crtc->config.pch_pfit.size) {
3425                 I915_WRITE(PF_CTL(pipe), 0);
3426                 I915_WRITE(PF_WIN_POS(pipe), 0);
3427                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3428         }
3429 }
3430
3431 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3432 {
3433         struct drm_device *dev = crtc->dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436         struct intel_encoder *encoder;
3437         int pipe = intel_crtc->pipe;
3438         int plane = intel_crtc->plane;
3439         u32 reg, temp;
3440
3441
3442         if (!intel_crtc->active)
3443                 return;
3444
3445         for_each_encoder_on_crtc(dev, crtc, encoder)
3446                 encoder->disable(encoder);
3447
3448         intel_crtc_wait_for_pending_flips(crtc);
3449         drm_vblank_off(dev, pipe);
3450
3451         if (dev_priv->fbc.plane == plane)
3452                 intel_disable_fbc(dev);
3453
3454         intel_crtc_update_cursor(crtc, false);
3455         intel_disable_planes(crtc);
3456         intel_disable_plane(dev_priv, plane, pipe);
3457
3458         if (intel_crtc->config.has_pch_encoder)
3459                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3460
3461         intel_disable_pipe(dev_priv, pipe);
3462
3463         ironlake_pfit_disable(intel_crtc);
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 if (encoder->post_disable)
3467                         encoder->post_disable(encoder);
3468
3469         if (intel_crtc->config.has_pch_encoder) {
3470                 ironlake_fdi_disable(crtc);
3471
3472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3473                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3474
3475                 if (HAS_PCH_CPT(dev)) {
3476                         /* disable TRANS_DP_CTL */
3477                         reg = TRANS_DP_CTL(pipe);
3478                         temp = I915_READ(reg);
3479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3480                                   TRANS_DP_PORT_SEL_MASK);
3481                         temp |= TRANS_DP_PORT_SEL_NONE;
3482                         I915_WRITE(reg, temp);
3483
3484                         /* disable DPLL_SEL */
3485                         temp = I915_READ(PCH_DPLL_SEL);
3486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3487                         I915_WRITE(PCH_DPLL_SEL, temp);
3488                 }
3489
3490                 /* disable PCH DPLL */
3491                 intel_disable_shared_dpll(intel_crtc);
3492
3493                 ironlake_fdi_pll_disable(intel_crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void haswell_crtc_disable(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509         struct intel_encoder *encoder;
3510         int pipe = intel_crtc->pipe;
3511         int plane = intel_crtc->plane;
3512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3513
3514         if (!intel_crtc->active)
3515                 return;
3516
3517         for_each_encoder_on_crtc(dev, crtc, encoder)
3518                 encoder->disable(encoder);
3519
3520         intel_crtc_wait_for_pending_flips(crtc);
3521         drm_vblank_off(dev, pipe);
3522
3523         /* FBC must be disabled before disabling the plane on HSW. */
3524         if (dev_priv->fbc.plane == plane)
3525                 intel_disable_fbc(dev);
3526
3527         hsw_disable_ips(intel_crtc);
3528
3529         intel_crtc_update_cursor(crtc, false);
3530         intel_disable_planes(crtc);
3531         intel_disable_plane(dev_priv, plane, pipe);
3532
3533         if (intel_crtc->config.has_pch_encoder)
3534                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3535         intel_disable_pipe(dev_priv, pipe);
3536
3537         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3538
3539         ironlake_pfit_disable(intel_crtc);
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_shared_dpll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         intel_ddi_put_crtc_pll(crtc);
3570 }
3571
3572 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3573 {
3574         if (!enable && intel_crtc->overlay) {
3575                 struct drm_device *dev = intel_crtc->base.dev;
3576                 struct drm_i915_private *dev_priv = dev->dev_private;
3577
3578                 mutex_lock(&dev->struct_mutex);
3579                 dev_priv->mm.interruptible = false;
3580                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3581                 dev_priv->mm.interruptible = true;
3582                 mutex_unlock(&dev->struct_mutex);
3583         }
3584
3585         /* Let userspace switch the overlay on again. In most cases userspace
3586          * has to recompute where to put it anyway.
3587          */
3588 }
3589
3590 /**
3591  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3592  * cursor plane briefly if not already running after enabling the display
3593  * plane.
3594  * This workaround avoids occasional blank screens when self refresh is
3595  * enabled.
3596  */
3597 static void
3598 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3599 {
3600         u32 cntl = I915_READ(CURCNTR(pipe));
3601
3602         if ((cntl & CURSOR_MODE) == 0) {
3603                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3604
3605                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3606                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3607                 intel_wait_for_vblank(dev_priv->dev, pipe);
3608                 I915_WRITE(CURCNTR(pipe), cntl);
3609                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3610                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3611         }
3612 }
3613
3614 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3615 {
3616         struct drm_device *dev = crtc->base.dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         struct intel_crtc_config *pipe_config = &crtc->config;
3619
3620         if (!crtc->config.gmch_pfit.control)
3621                 return;
3622
3623         /*
3624          * The panel fitter should only be adjusted whilst the pipe is disabled,
3625          * according to register description and PRM.
3626          */
3627         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3628         assert_pipe_disabled(dev_priv, crtc->pipe);
3629
3630         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3631         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3632
3633         /* Border color in case we don't scale up to the full screen. Black by
3634          * default, change to something else for debugging. */
3635         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3636 }
3637
3638 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         struct intel_encoder *encoder;
3644         int pipe = intel_crtc->pipe;
3645         int plane = intel_crtc->plane;
3646
3647         WARN_ON(!crtc->enabled);
3648
3649         if (intel_crtc->active)
3650                 return;
3651
3652         intel_crtc->active = true;
3653         intel_update_watermarks(dev);
3654
3655         mutex_lock(&dev_priv->dpio_lock);
3656
3657         for_each_encoder_on_crtc(dev, crtc, encoder)
3658                 if (encoder->pre_pll_enable)
3659                         encoder->pre_pll_enable(encoder);
3660
3661         vlv_enable_pll(intel_crtc);
3662
3663         for_each_encoder_on_crtc(dev, crtc, encoder)
3664                 if (encoder->pre_enable)
3665                         encoder->pre_enable(encoder);
3666
3667         /* VLV wants encoder enabling _before_ the pipe is up. */
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->enable(encoder);
3670
3671         i9xx_pfit_enable(intel_crtc);
3672
3673         intel_crtc_load_lut(crtc);
3674
3675         intel_enable_pipe(dev_priv, pipe, false);
3676         intel_enable_plane(dev_priv, plane, pipe);
3677         intel_enable_planes(crtc);
3678         intel_crtc_update_cursor(crtc, true);
3679
3680         intel_update_fbc(dev);
3681
3682         mutex_unlock(&dev_priv->dpio_lock);
3683 }
3684
3685 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3686 {
3687         struct drm_device *dev = crtc->dev;
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690         struct intel_encoder *encoder;
3691         int pipe = intel_crtc->pipe;
3692         int plane = intel_crtc->plane;
3693
3694         WARN_ON(!crtc->enabled);
3695
3696         if (intel_crtc->active)
3697                 return;
3698
3699         intel_crtc->active = true;
3700         intel_update_watermarks(dev);
3701
3702         for_each_encoder_on_crtc(dev, crtc, encoder)
3703                 if (encoder->pre_enable)
3704                         encoder->pre_enable(encoder);
3705
3706         i9xx_enable_pll(intel_crtc);
3707
3708         i9xx_pfit_enable(intel_crtc);
3709
3710         intel_crtc_load_lut(crtc);
3711
3712         intel_enable_pipe(dev_priv, pipe, false);
3713         intel_enable_plane(dev_priv, plane, pipe);
3714         intel_enable_planes(crtc);
3715         /* The fixup needs to happen before cursor is enabled */
3716         if (IS_G4X(dev))
3717                 g4x_fixup_plane(dev_priv, pipe);
3718         intel_crtc_update_cursor(crtc, true);
3719
3720         /* Give the overlay scaler a chance to enable if it's on this pipe */
3721         intel_crtc_dpms_overlay(intel_crtc, true);
3722
3723         intel_update_fbc(dev);
3724
3725         for_each_encoder_on_crtc(dev, crtc, encoder)
3726                 encoder->enable(encoder);
3727 }
3728
3729 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3730 {
3731         struct drm_device *dev = crtc->base.dev;
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733
3734         if (!crtc->config.gmch_pfit.control)
3735                 return;
3736
3737         assert_pipe_disabled(dev_priv, crtc->pipe);
3738
3739         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3740                          I915_READ(PFIT_CONTROL));
3741         I915_WRITE(PFIT_CONTROL, 0);
3742 }
3743
3744 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3745 {
3746         struct drm_device *dev = crtc->dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3749         struct intel_encoder *encoder;
3750         int pipe = intel_crtc->pipe;
3751         int plane = intel_crtc->plane;
3752
3753         if (!intel_crtc->active)
3754                 return;
3755
3756         for_each_encoder_on_crtc(dev, crtc, encoder)
3757                 encoder->disable(encoder);
3758
3759         /* Give the overlay scaler a chance to disable if it's on this pipe */
3760         intel_crtc_wait_for_pending_flips(crtc);
3761         drm_vblank_off(dev, pipe);
3762
3763         if (dev_priv->fbc.plane == plane)
3764                 intel_disable_fbc(dev);
3765
3766         intel_crtc_dpms_overlay(intel_crtc, false);
3767         intel_crtc_update_cursor(crtc, false);
3768         intel_disable_planes(crtc);
3769         intel_disable_plane(dev_priv, plane, pipe);
3770
3771         intel_disable_pipe(dev_priv, pipe);
3772
3773         i9xx_pfit_disable(intel_crtc);
3774
3775         for_each_encoder_on_crtc(dev, crtc, encoder)
3776                 if (encoder->post_disable)
3777                         encoder->post_disable(encoder);
3778
3779         i9xx_disable_pll(dev_priv, pipe);
3780
3781         intel_crtc->active = false;
3782         intel_update_fbc(dev);
3783         intel_update_watermarks(dev);
3784 }
3785
3786 static void i9xx_crtc_off(struct drm_crtc *crtc)
3787 {
3788 }
3789
3790 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3791                                     bool enabled)
3792 {
3793         struct drm_device *dev = crtc->dev;
3794         struct drm_i915_master_private *master_priv;
3795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796         int pipe = intel_crtc->pipe;
3797
3798         if (!dev->primary->master)
3799                 return;
3800
3801         master_priv = dev->primary->master->driver_priv;
3802         if (!master_priv->sarea_priv)
3803                 return;
3804
3805         switch (pipe) {
3806         case 0:
3807                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3808                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3809                 break;
3810         case 1:
3811                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3812                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3813                 break;
3814         default:
3815                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3816                 break;
3817         }
3818 }
3819
3820 /**
3821  * Sets the power management mode of the pipe and plane.
3822  */
3823 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3824 {
3825         struct drm_device *dev = crtc->dev;
3826         struct drm_i915_private *dev_priv = dev->dev_private;
3827         struct intel_encoder *intel_encoder;
3828         bool enable = false;
3829
3830         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3831                 enable |= intel_encoder->connectors_active;
3832
3833         if (enable)
3834                 dev_priv->display.crtc_enable(crtc);
3835         else
3836                 dev_priv->display.crtc_disable(crtc);
3837
3838         intel_crtc_update_sarea(crtc, enable);
3839 }
3840
3841 static void intel_crtc_disable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_connector *connector;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847
3848         /* crtc should still be enabled when we disable it. */
3849         WARN_ON(!crtc->enabled);
3850
3851         dev_priv->display.crtc_disable(crtc);
3852         intel_crtc->eld_vld = false;
3853         intel_crtc_update_sarea(crtc, false);
3854         dev_priv->display.off(crtc);
3855
3856         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3857         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3858
3859         if (crtc->fb) {
3860                 mutex_lock(&dev->struct_mutex);
3861                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3862                 mutex_unlock(&dev->struct_mutex);
3863                 crtc->fb = NULL;
3864         }
3865
3866         /* Update computed state. */
3867         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3868                 if (!connector->encoder || !connector->encoder->crtc)
3869                         continue;
3870
3871                 if (connector->encoder->crtc != crtc)
3872                         continue;
3873
3874                 connector->dpms = DRM_MODE_DPMS_OFF;
3875                 to_intel_encoder(connector->encoder)->connectors_active = false;
3876         }
3877 }
3878
3879 void intel_modeset_disable(struct drm_device *dev)
3880 {
3881         struct drm_crtc *crtc;
3882
3883         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3884                 if (crtc->enabled)
3885                         intel_crtc_disable(crtc);
3886         }
3887 }
3888
3889 void intel_encoder_destroy(struct drm_encoder *encoder)
3890 {
3891         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3892
3893         drm_encoder_cleanup(encoder);
3894         kfree(intel_encoder);
3895 }
3896
3897 /* Simple dpms helper for encodres with just one connector, no cloning and only
3898  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3899  * state of the entire output pipe. */
3900 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3901 {
3902         if (mode == DRM_MODE_DPMS_ON) {
3903                 encoder->connectors_active = true;
3904
3905                 intel_crtc_update_dpms(encoder->base.crtc);
3906         } else {
3907                 encoder->connectors_active = false;
3908
3909                 intel_crtc_update_dpms(encoder->base.crtc);
3910         }
3911 }
3912
3913 /* Cross check the actual hw state with our own modeset state tracking (and it's
3914  * internal consistency). */
3915 static void intel_connector_check_state(struct intel_connector *connector)
3916 {
3917         if (connector->get_hw_state(connector)) {
3918                 struct intel_encoder *encoder = connector->encoder;
3919                 struct drm_crtc *crtc;
3920                 bool encoder_enabled;
3921                 enum pipe pipe;
3922
3923                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3924                               connector->base.base.id,
3925                               drm_get_connector_name(&connector->base));
3926
3927                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3928                      "wrong connector dpms state\n");
3929                 WARN(connector->base.encoder != &encoder->base,
3930                      "active connector not linked to encoder\n");
3931                 WARN(!encoder->connectors_active,
3932                      "encoder->connectors_active not set\n");
3933
3934                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3935                 WARN(!encoder_enabled, "encoder not enabled\n");
3936                 if (WARN_ON(!encoder->base.crtc))
3937                         return;
3938
3939                 crtc = encoder->base.crtc;
3940
3941                 WARN(!crtc->enabled, "crtc not enabled\n");
3942                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3943                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3944                      "encoder active on the wrong pipe\n");
3945         }
3946 }
3947
3948 /* Even simpler default implementation, if there's really no special case to
3949  * consider. */
3950 void intel_connector_dpms(struct drm_connector *connector, int mode)
3951 {
3952         struct intel_encoder *encoder = intel_attached_encoder(connector);
3953
3954         /* All the simple cases only support two dpms states. */
3955         if (mode != DRM_MODE_DPMS_ON)
3956                 mode = DRM_MODE_DPMS_OFF;
3957
3958         if (mode == connector->dpms)
3959                 return;
3960
3961         connector->dpms = mode;
3962
3963         /* Only need to change hw state when actually enabled */
3964         if (encoder->base.crtc)
3965                 intel_encoder_dpms(encoder, mode);
3966         else
3967                 WARN_ON(encoder->connectors_active != false);
3968
3969         intel_modeset_check_state(connector->dev);
3970 }
3971
3972 /* Simple connector->get_hw_state implementation for encoders that support only
3973  * one connector and no cloning and hence the encoder state determines the state
3974  * of the connector. */
3975 bool intel_connector_get_hw_state(struct intel_connector *connector)
3976 {
3977         enum pipe pipe = 0;
3978         struct intel_encoder *encoder = connector->encoder;
3979
3980         return encoder->get_hw_state(encoder, &pipe);
3981 }
3982
3983 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3984                                      struct intel_crtc_config *pipe_config)
3985 {
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         struct intel_crtc *pipe_B_crtc =
3988                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3989
3990         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3991                       pipe_name(pipe), pipe_config->fdi_lanes);
3992         if (pipe_config->fdi_lanes > 4) {
3993                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3994                               pipe_name(pipe), pipe_config->fdi_lanes);
3995                 return false;
3996         }
3997
3998         if (IS_HASWELL(dev)) {
3999                 if (pipe_config->fdi_lanes > 2) {
4000                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4001                                       pipe_config->fdi_lanes);
4002                         return false;
4003                 } else {
4004                         return true;
4005                 }
4006         }
4007
4008         if (INTEL_INFO(dev)->num_pipes == 2)
4009                 return true;
4010
4011         /* Ivybridge 3 pipe is really complicated */
4012         switch (pipe) {
4013         case PIPE_A:
4014                 return true;
4015         case PIPE_B:
4016                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4017                     pipe_config->fdi_lanes > 2) {
4018                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4019                                       pipe_name(pipe), pipe_config->fdi_lanes);
4020                         return false;
4021                 }
4022                 return true;
4023         case PIPE_C:
4024                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4025                     pipe_B_crtc->config.fdi_lanes <= 2) {
4026                         if (pipe_config->fdi_lanes > 2) {
4027                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4028                                               pipe_name(pipe), pipe_config->fdi_lanes);
4029                                 return false;
4030                         }
4031                 } else {
4032                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4033                         return false;
4034                 }
4035                 return true;
4036         default:
4037                 BUG();
4038         }
4039 }
4040
4041 #define RETRY 1
4042 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4043                                        struct intel_crtc_config *pipe_config)
4044 {
4045         struct drm_device *dev = intel_crtc->base.dev;
4046         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047         int lane, link_bw, fdi_dotclock;
4048         bool setup_ok, needs_recompute = false;
4049
4050 retry:
4051         /* FDI is a binary signal running at ~2.7GHz, encoding
4052          * each output octet as 10 bits. The actual frequency
4053          * is stored as a divider into a 100MHz clock, and the
4054          * mode pixel clock is stored in units of 1KHz.
4055          * Hence the bw of each lane in terms of the mode signal
4056          * is:
4057          */
4058         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4059
4060         fdi_dotclock = adjusted_mode->clock;
4061         fdi_dotclock /= pipe_config->pixel_multiplier;
4062
4063         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4064                                            pipe_config->pipe_bpp);
4065
4066         pipe_config->fdi_lanes = lane;
4067
4068         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4069                                link_bw, &pipe_config->fdi_m_n);
4070
4071         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4072                                             intel_crtc->pipe, pipe_config);
4073         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4074                 pipe_config->pipe_bpp -= 2*3;
4075                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4076                               pipe_config->pipe_bpp);
4077                 needs_recompute = true;
4078                 pipe_config->bw_constrained = true;
4079
4080                 goto retry;
4081         }
4082
4083         if (needs_recompute)
4084                 return RETRY;
4085
4086         return setup_ok ? 0 : -EINVAL;
4087 }
4088
4089 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4090                                    struct intel_crtc_config *pipe_config)
4091 {
4092         pipe_config->ips_enabled = i915_enable_ips &&
4093                                    hsw_crtc_supports_ips(crtc) &&
4094                                    pipe_config->pipe_bpp <= 24;
4095 }
4096
4097 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4098                                      struct intel_crtc_config *pipe_config)
4099 {
4100         struct drm_device *dev = crtc->base.dev;
4101         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4102
4103         if (HAS_PCH_SPLIT(dev)) {
4104                 /* FDI link clock is fixed at 2.7G */
4105                 if (pipe_config->requested_mode.clock * 3
4106                     > IRONLAKE_FDI_FREQ * 4)
4107                         return -EINVAL;
4108         }
4109
4110         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4111          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4112          */
4113         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4114                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4115                 return -EINVAL;
4116
4117         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4118                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4119         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4120                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4121                  * for lvds. */
4122                 pipe_config->pipe_bpp = 8*3;
4123         }
4124
4125         if (HAS_IPS(dev))
4126                 hsw_compute_ips_config(crtc, pipe_config);
4127
4128         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4129          * clock survives for now. */
4130         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4131                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4132
4133         if (pipe_config->has_pch_encoder)
4134                 return ironlake_fdi_compute_config(crtc, pipe_config);
4135
4136         return 0;
4137 }
4138
4139 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4140 {
4141         return 400000; /* FIXME */
4142 }
4143
4144 static int i945_get_display_clock_speed(struct drm_device *dev)
4145 {
4146         return 400000;
4147 }
4148
4149 static int i915_get_display_clock_speed(struct drm_device *dev)
4150 {
4151         return 333000;
4152 }
4153
4154 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         return 200000;
4157 }
4158
4159 static int pnv_get_display_clock_speed(struct drm_device *dev)
4160 {
4161         u16 gcfgc = 0;
4162
4163         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4164
4165         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4166         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4167                 return 267000;
4168         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4169                 return 333000;
4170         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4171                 return 444000;
4172         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4173                 return 200000;
4174         default:
4175                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4176         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4177                 return 133000;
4178         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4179                 return 167000;
4180         }
4181 }
4182
4183 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4184 {
4185         u16 gcfgc = 0;
4186
4187         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4188
4189         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4190                 return 133000;
4191         else {
4192                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4193                 case GC_DISPLAY_CLOCK_333_MHZ:
4194                         return 333000;
4195                 default:
4196                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4197                         return 190000;
4198                 }
4199         }
4200 }
4201
4202 static int i865_get_display_clock_speed(struct drm_device *dev)
4203 {
4204         return 266000;
4205 }
4206
4207 static int i855_get_display_clock_speed(struct drm_device *dev)
4208 {
4209         u16 hpllcc = 0;
4210         /* Assume that the hardware is in the high speed state.  This
4211          * should be the default.
4212          */
4213         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4214         case GC_CLOCK_133_200:
4215         case GC_CLOCK_100_200:
4216                 return 200000;
4217         case GC_CLOCK_166_250:
4218                 return 250000;
4219         case GC_CLOCK_100_133:
4220                 return 133000;
4221         }
4222
4223         /* Shouldn't happen */
4224         return 0;
4225 }
4226
4227 static int i830_get_display_clock_speed(struct drm_device *dev)
4228 {
4229         return 133000;
4230 }
4231
4232 static void
4233 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4234 {
4235         while (*num > DATA_LINK_M_N_MASK ||
4236                *den > DATA_LINK_M_N_MASK) {
4237                 *num >>= 1;
4238                 *den >>= 1;
4239         }
4240 }
4241
4242 static void compute_m_n(unsigned int m, unsigned int n,
4243                         uint32_t *ret_m, uint32_t *ret_n)
4244 {
4245         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4246         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4247         intel_reduce_m_n_ratio(ret_m, ret_n);
4248 }
4249
4250 void
4251 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4252                        int pixel_clock, int link_clock,
4253                        struct intel_link_m_n *m_n)
4254 {
4255         m_n->tu = 64;
4256
4257         compute_m_n(bits_per_pixel * pixel_clock,
4258                     link_clock * nlanes * 8,
4259                     &m_n->gmch_m, &m_n->gmch_n);
4260
4261         compute_m_n(pixel_clock, link_clock,
4262                     &m_n->link_m, &m_n->link_n);
4263 }
4264
4265 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4266 {
4267         if (i915_panel_use_ssc >= 0)
4268                 return i915_panel_use_ssc != 0;
4269         return dev_priv->vbt.lvds_use_ssc
4270                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4271 }
4272
4273 static int vlv_get_refclk(struct drm_crtc *crtc)
4274 {
4275         struct drm_device *dev = crtc->dev;
4276         struct drm_i915_private *dev_priv = dev->dev_private;
4277         int refclk = 27000; /* for DP & HDMI */
4278
4279         return 100000; /* only one validated so far */
4280
4281         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4282                 refclk = 96000;
4283         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4284                 if (intel_panel_use_ssc(dev_priv))
4285                         refclk = 100000;
4286                 else
4287                         refclk = 96000;
4288         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4289                 refclk = 100000;
4290         }
4291
4292         return refclk;
4293 }
4294
4295 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4296 {
4297         struct drm_device *dev = crtc->dev;
4298         struct drm_i915_private *dev_priv = dev->dev_private;
4299         int refclk;
4300
4301         if (IS_VALLEYVIEW(dev)) {
4302                 refclk = vlv_get_refclk(crtc);
4303         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4304             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4305                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4306                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4307                               refclk / 1000);
4308         } else if (!IS_GEN2(dev)) {
4309                 refclk = 96000;
4310         } else {
4311                 refclk = 48000;
4312         }
4313
4314         return refclk;
4315 }
4316
4317 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4318 {
4319         return (1 << dpll->n) << 16 | dpll->m2;
4320 }
4321
4322 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4323 {
4324         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4325 }
4326
4327 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4328                                      intel_clock_t *reduced_clock)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         int pipe = crtc->pipe;
4333         u32 fp, fp2 = 0;
4334
4335         if (IS_PINEVIEW(dev)) {
4336                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4337                 if (reduced_clock)
4338                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4339         } else {
4340                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4341                 if (reduced_clock)
4342                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4343         }
4344
4345         I915_WRITE(FP0(pipe), fp);
4346         crtc->config.dpll_hw_state.fp0 = fp;
4347
4348         crtc->lowfreq_avail = false;
4349         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4350             reduced_clock && i915_powersave) {
4351                 I915_WRITE(FP1(pipe), fp2);
4352                 crtc->config.dpll_hw_state.fp1 = fp2;
4353                 crtc->lowfreq_avail = true;
4354         } else {
4355                 I915_WRITE(FP1(pipe), fp);
4356                 crtc->config.dpll_hw_state.fp1 = fp;
4357         }
4358 }
4359
4360 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4361 {
4362         u32 reg_val;
4363
4364         /*
4365          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4366          * and set it to a reasonable value instead.
4367          */
4368         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4369         reg_val &= 0xffffff00;
4370         reg_val |= 0x00000030;
4371         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4372
4373         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4374         reg_val &= 0x8cffffff;
4375         reg_val = 0x8c000000;
4376         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4377
4378         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4379         reg_val &= 0xffffff00;
4380         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4381
4382         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4383         reg_val &= 0x00ffffff;
4384         reg_val |= 0xb0000000;
4385         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4386 }
4387
4388 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4389                                          struct intel_link_m_n *m_n)
4390 {
4391         struct drm_device *dev = crtc->base.dev;
4392         struct drm_i915_private *dev_priv = dev->dev_private;
4393         int pipe = crtc->pipe;
4394
4395         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4396         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4397         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4398         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4399 }
4400
4401 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4402                                          struct intel_link_m_n *m_n)
4403 {
4404         struct drm_device *dev = crtc->base.dev;
4405         struct drm_i915_private *dev_priv = dev->dev_private;
4406         int pipe = crtc->pipe;
4407         enum transcoder transcoder = crtc->config.cpu_transcoder;
4408
4409         if (INTEL_INFO(dev)->gen >= 5) {
4410                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4411                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4412                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4413                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4414         } else {
4415                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4416                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4417                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4418                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4419         }
4420 }
4421
4422 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4423 {
4424         if (crtc->config.has_pch_encoder)
4425                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4426         else
4427                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4428 }
4429
4430 static void vlv_update_pll(struct intel_crtc *crtc)
4431 {
4432         struct drm_device *dev = crtc->base.dev;
4433         struct drm_i915_private *dev_priv = dev->dev_private;
4434         int pipe = crtc->pipe;
4435         u32 dpll, mdiv;
4436         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4437         bool is_hdmi;
4438         u32 coreclk, reg_val, dpll_md;
4439
4440         mutex_lock(&dev_priv->dpio_lock);
4441
4442         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4443
4444         bestn = crtc->config.dpll.n;
4445         bestm1 = crtc->config.dpll.m1;
4446         bestm2 = crtc->config.dpll.m2;
4447         bestp1 = crtc->config.dpll.p1;
4448         bestp2 = crtc->config.dpll.p2;
4449
4450         /* See eDP HDMI DPIO driver vbios notes doc */
4451
4452         /* PLL B needs special handling */
4453         if (pipe)
4454                 vlv_pllb_recal_opamp(dev_priv);
4455
4456         /* Set up Tx target for periodic Rcomp update */
4457         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4458
4459         /* Disable target IRef on PLL */
4460         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4461         reg_val &= 0x00ffffff;
4462         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4463
4464         /* Disable fast lock */
4465         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4466
4467         /* Set idtafcrecal before PLL is enabled */
4468         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4469         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4470         mdiv |= ((bestn << DPIO_N_SHIFT));
4471         mdiv |= (1 << DPIO_K_SHIFT);
4472
4473         /*
4474          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4475          * but we don't support that).
4476          * Note: don't use the DAC post divider as it seems unstable.
4477          */
4478         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4479         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4480
4481         mdiv |= DPIO_ENABLE_CALIBRATION;
4482         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4483
4484         /* Set HBR and RBR LPF coefficients */
4485         if (crtc->config.port_clock == 162000 ||
4486             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4487             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4488                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4489                                  0x009f0003);
4490         else
4491                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4492                                  0x00d0000f);
4493
4494         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4495             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4496                 /* Use SSC source */
4497                 if (!pipe)
4498                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4499                                          0x0df40000);
4500                 else
4501                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4502                                          0x0df70000);
4503         } else { /* HDMI or VGA */
4504                 /* Use bend source */
4505                 if (!pipe)
4506                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4507                                          0x0df70000);
4508                 else
4509                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4510                                          0x0df40000);
4511         }
4512
4513         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4514         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4515         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4516             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4517                 coreclk |= 0x01000000;
4518         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4519
4520         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4521
4522         /* Enable DPIO clock input */
4523         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4524                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4525         if (pipe)
4526                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4527
4528         dpll |= DPLL_VCO_ENABLE;
4529         crtc->config.dpll_hw_state.dpll = dpll;
4530
4531         dpll_md = (crtc->config.pixel_multiplier - 1)
4532                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4533         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4534
4535         if (crtc->config.has_dp_encoder)
4536                 intel_dp_set_m_n(crtc);
4537
4538         mutex_unlock(&dev_priv->dpio_lock);
4539 }
4540
4541 static void i9xx_update_pll(struct intel_crtc *crtc,
4542                             intel_clock_t *reduced_clock,
4543                             int num_connectors)
4544 {
4545         struct drm_device *dev = crtc->base.dev;
4546         struct drm_i915_private *dev_priv = dev->dev_private;
4547         u32 dpll;
4548         bool is_sdvo;
4549         struct dpll *clock = &crtc->config.dpll;
4550
4551         i9xx_update_pll_dividers(crtc, reduced_clock);
4552
4553         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4554                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4555
4556         dpll = DPLL_VGA_MODE_DIS;
4557
4558         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4559                 dpll |= DPLLB_MODE_LVDS;
4560         else
4561                 dpll |= DPLLB_MODE_DAC_SERIAL;
4562
4563         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4564                 dpll |= (crtc->config.pixel_multiplier - 1)
4565                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4566         }
4567
4568         if (is_sdvo)
4569                 dpll |= DPLL_SDVO_HIGH_SPEED;
4570
4571         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4572                 dpll |= DPLL_SDVO_HIGH_SPEED;
4573
4574         /* compute bitmask from p1 value */
4575         if (IS_PINEVIEW(dev))
4576                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4577         else {
4578                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4579                 if (IS_G4X(dev) && reduced_clock)
4580                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4581         }
4582         switch (clock->p2) {
4583         case 5:
4584                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4585                 break;
4586         case 7:
4587                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4588                 break;
4589         case 10:
4590                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4591                 break;
4592         case 14:
4593                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4594                 break;
4595         }
4596         if (INTEL_INFO(dev)->gen >= 4)
4597                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4598
4599         if (crtc->config.sdvo_tv_clock)
4600                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4601         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4602                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604         else
4605                 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607         dpll |= DPLL_VCO_ENABLE;
4608         crtc->config.dpll_hw_state.dpll = dpll;
4609
4610         if (INTEL_INFO(dev)->gen >= 4) {
4611                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4612                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4613                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4614         }
4615
4616         if (crtc->config.has_dp_encoder)
4617                 intel_dp_set_m_n(crtc);
4618 }
4619
4620 static void i8xx_update_pll(struct intel_crtc *crtc,
4621                             intel_clock_t *reduced_clock,
4622                             int num_connectors)
4623 {
4624         struct drm_device *dev = crtc->base.dev;
4625         struct drm_i915_private *dev_priv = dev->dev_private;
4626         u32 dpll;
4627         struct dpll *clock = &crtc->config.dpll;
4628
4629         i9xx_update_pll_dividers(crtc, reduced_clock);
4630
4631         dpll = DPLL_VGA_MODE_DIS;
4632
4633         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4634                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4635         } else {
4636                 if (clock->p1 == 2)
4637                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4638                 else
4639                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4640                 if (clock->p2 == 4)
4641                         dpll |= PLL_P2_DIVIDE_BY_4;
4642         }
4643
4644         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4645                 dpll |= DPLL_DVO_2X_MODE;
4646
4647         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4648                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4649                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4650         else
4651                 dpll |= PLL_REF_INPUT_DREFCLK;
4652
4653         dpll |= DPLL_VCO_ENABLE;
4654         crtc->config.dpll_hw_state.dpll = dpll;
4655 }
4656
4657 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4658 {
4659         struct drm_device *dev = intel_crtc->base.dev;
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         enum pipe pipe = intel_crtc->pipe;
4662         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4663         struct drm_display_mode *adjusted_mode =
4664                 &intel_crtc->config.adjusted_mode;
4665         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4666         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4667
4668         /* We need to be careful not to changed the adjusted mode, for otherwise
4669          * the hw state checker will get angry at the mismatch. */
4670         crtc_vtotal = adjusted_mode->crtc_vtotal;
4671         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4672
4673         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4674                 /* the chip adds 2 halflines automatically */
4675                 crtc_vtotal -= 1;
4676                 crtc_vblank_end -= 1;
4677                 vsyncshift = adjusted_mode->crtc_hsync_start
4678                              - adjusted_mode->crtc_htotal / 2;
4679         } else {
4680                 vsyncshift = 0;
4681         }
4682
4683         if (INTEL_INFO(dev)->gen > 3)
4684                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4685
4686         I915_WRITE(HTOTAL(cpu_transcoder),
4687                    (adjusted_mode->crtc_hdisplay - 1) |
4688                    ((adjusted_mode->crtc_htotal - 1) << 16));
4689         I915_WRITE(HBLANK(cpu_transcoder),
4690                    (adjusted_mode->crtc_hblank_start - 1) |
4691                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4692         I915_WRITE(HSYNC(cpu_transcoder),
4693                    (adjusted_mode->crtc_hsync_start - 1) |
4694                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4695
4696         I915_WRITE(VTOTAL(cpu_transcoder),
4697                    (adjusted_mode->crtc_vdisplay - 1) |
4698                    ((crtc_vtotal - 1) << 16));
4699         I915_WRITE(VBLANK(cpu_transcoder),
4700                    (adjusted_mode->crtc_vblank_start - 1) |
4701                    ((crtc_vblank_end - 1) << 16));
4702         I915_WRITE(VSYNC(cpu_transcoder),
4703                    (adjusted_mode->crtc_vsync_start - 1) |
4704                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4705
4706         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4707          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4708          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4709          * bits. */
4710         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4711             (pipe == PIPE_B || pipe == PIPE_C))
4712                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4713
4714         /* pipesrc controls the size that is scaled from, which should
4715          * always be the user's requested size.
4716          */
4717         I915_WRITE(PIPESRC(pipe),
4718                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4719 }
4720
4721 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4722                                    struct intel_crtc_config *pipe_config)
4723 {
4724         struct drm_device *dev = crtc->base.dev;
4725         struct drm_i915_private *dev_priv = dev->dev_private;
4726         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4727         uint32_t tmp;
4728
4729         tmp = I915_READ(HTOTAL(cpu_transcoder));
4730         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4731         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4732         tmp = I915_READ(HBLANK(cpu_transcoder));
4733         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4734         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4735         tmp = I915_READ(HSYNC(cpu_transcoder));
4736         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4737         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4738
4739         tmp = I915_READ(VTOTAL(cpu_transcoder));
4740         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4741         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4742         tmp = I915_READ(VBLANK(cpu_transcoder));
4743         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4744         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4745         tmp = I915_READ(VSYNC(cpu_transcoder));
4746         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4747         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4748
4749         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4750                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4751                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4752                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4753         }
4754
4755         tmp = I915_READ(PIPESRC(crtc->pipe));
4756         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4757         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4758 }
4759
4760 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4761                                              struct intel_crtc_config *pipe_config)
4762 {
4763         struct drm_crtc *crtc = &intel_crtc->base;
4764
4765         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4766         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4767         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4768         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4769
4770         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4771         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4772         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4773         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4774
4775         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4776
4777         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4778         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4779 }
4780
4781 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4782 {
4783         struct drm_device *dev = intel_crtc->base.dev;
4784         struct drm_i915_private *dev_priv = dev->dev_private;
4785         uint32_t pipeconf;
4786
4787         pipeconf = 0;
4788
4789         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4790                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4791                  * core speed.
4792                  *
4793                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4794                  * pipe == 0 check?
4795                  */
4796                 if (intel_crtc->config.requested_mode.clock >
4797                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4798                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4799         }
4800
4801         /* only g4x and later have fancy bpc/dither controls */
4802         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4803                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4804                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4805                         pipeconf |= PIPECONF_DITHER_EN |
4806                                     PIPECONF_DITHER_TYPE_SP;
4807
4808                 switch (intel_crtc->config.pipe_bpp) {
4809                 case 18:
4810                         pipeconf |= PIPECONF_6BPC;
4811                         break;
4812                 case 24:
4813                         pipeconf |= PIPECONF_8BPC;
4814                         break;
4815                 case 30:
4816                         pipeconf |= PIPECONF_10BPC;
4817                         break;
4818                 default:
4819                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4820                         BUG();
4821                 }
4822         }
4823
4824         if (HAS_PIPE_CXSR(dev)) {
4825                 if (intel_crtc->lowfreq_avail) {
4826                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4827                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4828                 } else {
4829                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4830                 }
4831         }
4832
4833         if (!IS_GEN2(dev) &&
4834             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4835                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4836         else
4837                 pipeconf |= PIPECONF_PROGRESSIVE;
4838
4839         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4840                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4841
4842         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4843         POSTING_READ(PIPECONF(intel_crtc->pipe));
4844 }
4845
4846 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4847                               int x, int y,
4848                               struct drm_framebuffer *fb)
4849 {
4850         struct drm_device *dev = crtc->dev;
4851         struct drm_i915_private *dev_priv = dev->dev_private;
4852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4854         int pipe = intel_crtc->pipe;
4855         int plane = intel_crtc->plane;
4856         int refclk, num_connectors = 0;
4857         intel_clock_t clock, reduced_clock;
4858         u32 dspcntr;
4859         bool ok, has_reduced_clock = false;
4860         bool is_lvds = false;
4861         struct intel_encoder *encoder;
4862         const intel_limit_t *limit;
4863         int ret;
4864
4865         for_each_encoder_on_crtc(dev, crtc, encoder) {
4866                 switch (encoder->type) {
4867                 case INTEL_OUTPUT_LVDS:
4868                         is_lvds = true;
4869                         break;
4870                 }
4871
4872                 num_connectors++;
4873         }
4874
4875         refclk = i9xx_get_refclk(crtc, num_connectors);
4876
4877         /*
4878          * Returns a set of divisors for the desired target clock with the given
4879          * refclk, or FALSE.  The returned values represent the clock equation:
4880          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4881          */
4882         limit = intel_limit(crtc, refclk);
4883         ok = dev_priv->display.find_dpll(limit, crtc,
4884                                          intel_crtc->config.port_clock,
4885                                          refclk, NULL, &clock);
4886         if (!ok && !intel_crtc->config.clock_set) {
4887                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4888                 return -EINVAL;
4889         }
4890
4891         /* Ensure that the cursor is valid for the new mode before changing... */
4892         intel_crtc_update_cursor(crtc, true);
4893
4894         if (is_lvds && dev_priv->lvds_downclock_avail) {
4895                 /*
4896                  * Ensure we match the reduced clock's P to the target clock.
4897                  * If the clocks don't match, we can't switch the display clock
4898                  * by using the FP0/FP1. In such case we will disable the LVDS
4899                  * downclock feature.
4900                 */
4901                 has_reduced_clock =
4902                         dev_priv->display.find_dpll(limit, crtc,
4903                                                     dev_priv->lvds_downclock,
4904                                                     refclk, &clock,
4905                                                     &reduced_clock);
4906         }
4907         /* Compat-code for transition, will disappear. */
4908         if (!intel_crtc->config.clock_set) {
4909                 intel_crtc->config.dpll.n = clock.n;
4910                 intel_crtc->config.dpll.m1 = clock.m1;
4911                 intel_crtc->config.dpll.m2 = clock.m2;
4912                 intel_crtc->config.dpll.p1 = clock.p1;
4913                 intel_crtc->config.dpll.p2 = clock.p2;
4914         }
4915
4916         if (IS_GEN2(dev))
4917                 i8xx_update_pll(intel_crtc,
4918                                 has_reduced_clock ? &reduced_clock : NULL,
4919                                 num_connectors);
4920         else if (IS_VALLEYVIEW(dev))
4921                 vlv_update_pll(intel_crtc);
4922         else
4923                 i9xx_update_pll(intel_crtc,
4924                                 has_reduced_clock ? &reduced_clock : NULL,
4925                                 num_connectors);
4926
4927         /* Set up the display plane register */
4928         dspcntr = DISPPLANE_GAMMA_ENABLE;
4929
4930         if (!IS_VALLEYVIEW(dev)) {
4931                 if (pipe == 0)
4932                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4933                 else
4934                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4935         }
4936
4937         intel_set_pipe_timings(intel_crtc);
4938
4939         /* pipesrc and dspsize control the size that is scaled from,
4940          * which should always be the user's requested size.
4941          */
4942         I915_WRITE(DSPSIZE(plane),
4943                    ((mode->vdisplay - 1) << 16) |
4944                    (mode->hdisplay - 1));
4945         I915_WRITE(DSPPOS(plane), 0);
4946
4947         i9xx_set_pipeconf(intel_crtc);
4948
4949         I915_WRITE(DSPCNTR(plane), dspcntr);
4950         POSTING_READ(DSPCNTR(plane));
4951
4952         ret = intel_pipe_set_base(crtc, x, y, fb);
4953
4954         intel_update_watermarks(dev);
4955
4956         return ret;
4957 }
4958
4959 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4960                                  struct intel_crtc_config *pipe_config)
4961 {
4962         struct drm_device *dev = crtc->base.dev;
4963         struct drm_i915_private *dev_priv = dev->dev_private;
4964         uint32_t tmp;
4965
4966         tmp = I915_READ(PFIT_CONTROL);
4967         if (!(tmp & PFIT_ENABLE))
4968                 return;
4969
4970         /* Check whether the pfit is attached to our pipe. */
4971         if (INTEL_INFO(dev)->gen < 4) {
4972                 if (crtc->pipe != PIPE_B)
4973                         return;
4974         } else {
4975                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4976                         return;
4977         }
4978
4979         pipe_config->gmch_pfit.control = tmp;
4980         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4981         if (INTEL_INFO(dev)->gen < 5)
4982                 pipe_config->gmch_pfit.lvds_border_bits =
4983                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4984 }
4985
4986 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4987                                  struct intel_crtc_config *pipe_config)
4988 {
4989         struct drm_device *dev = crtc->base.dev;
4990         struct drm_i915_private *dev_priv = dev->dev_private;
4991         uint32_t tmp;
4992
4993         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4994         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4995
4996         tmp = I915_READ(PIPECONF(crtc->pipe));
4997         if (!(tmp & PIPECONF_ENABLE))
4998                 return false;
4999
5000         intel_get_pipe_timings(crtc, pipe_config);
5001
5002         i9xx_get_pfit_config(crtc, pipe_config);
5003
5004         if (INTEL_INFO(dev)->gen >= 4) {
5005                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5006                 pipe_config->pixel_multiplier =
5007                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5008                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5009                 pipe_config->dpll_hw_state.dpll_md = tmp;
5010         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5011                 tmp = I915_READ(DPLL(crtc->pipe));
5012                 pipe_config->pixel_multiplier =
5013                         ((tmp & SDVO_MULTIPLIER_MASK)
5014                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5015         } else {
5016                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5017                  * port and will be fixed up in the encoder->get_config
5018                  * function. */
5019                 pipe_config->pixel_multiplier = 1;
5020         }
5021         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5022         if (!IS_VALLEYVIEW(dev)) {
5023                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5024                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5025         } else {
5026                 /* Mask out read-only status bits. */
5027                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5028                                                      DPLL_PORTC_READY_MASK |
5029                                                      DPLL_PORTB_READY_MASK);
5030         }
5031
5032         return true;
5033 }
5034
5035 static void ironlake_init_pch_refclk(struct drm_device *dev)
5036 {
5037         struct drm_i915_private *dev_priv = dev->dev_private;
5038         struct drm_mode_config *mode_config = &dev->mode_config;
5039         struct intel_encoder *encoder;
5040         u32 val, final;
5041         bool has_lvds = false;
5042         bool has_cpu_edp = false;
5043         bool has_panel = false;
5044         bool has_ck505 = false;
5045         bool can_ssc = false;
5046
5047         /* We need to take the global config into account */
5048         list_for_each_entry(encoder, &mode_config->encoder_list,
5049                             base.head) {
5050                 switch (encoder->type) {
5051                 case INTEL_OUTPUT_LVDS:
5052                         has_panel = true;
5053                         has_lvds = true;
5054                         break;
5055                 case INTEL_OUTPUT_EDP:
5056                         has_panel = true;
5057                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5058                                 has_cpu_edp = true;
5059                         break;
5060                 }
5061         }
5062
5063         if (HAS_PCH_IBX(dev)) {
5064                 has_ck505 = dev_priv->vbt.display_clock_mode;
5065                 can_ssc = has_ck505;
5066         } else {
5067                 has_ck505 = false;
5068                 can_ssc = true;
5069         }
5070
5071         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5072                       has_panel, has_lvds, has_ck505);
5073
5074         /* Ironlake: try to setup display ref clock before DPLL
5075          * enabling. This is only under driver's control after
5076          * PCH B stepping, previous chipset stepping should be
5077          * ignoring this setting.
5078          */
5079         val = I915_READ(PCH_DREF_CONTROL);
5080
5081         /* As we must carefully and slowly disable/enable each source in turn,
5082          * compute the final state we want first and check if we need to
5083          * make any changes at all.
5084          */
5085         final = val;
5086         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5087         if (has_ck505)
5088                 final |= DREF_NONSPREAD_CK505_ENABLE;
5089         else
5090                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5091
5092         final &= ~DREF_SSC_SOURCE_MASK;
5093         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5094         final &= ~DREF_SSC1_ENABLE;
5095
5096         if (has_panel) {
5097                 final |= DREF_SSC_SOURCE_ENABLE;
5098
5099                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5100                         final |= DREF_SSC1_ENABLE;
5101
5102                 if (has_cpu_edp) {
5103                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5104                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5105                         else
5106                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5107                 } else
5108                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5109         } else {
5110                 final |= DREF_SSC_SOURCE_DISABLE;
5111                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5112         }
5113
5114         if (final == val)
5115                 return;
5116
5117         /* Always enable nonspread source */
5118         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5119
5120         if (has_ck505)
5121                 val |= DREF_NONSPREAD_CK505_ENABLE;
5122         else
5123                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5124
5125         if (has_panel) {
5126                 val &= ~DREF_SSC_SOURCE_MASK;
5127                 val |= DREF_SSC_SOURCE_ENABLE;
5128
5129                 /* SSC must be turned on before enabling the CPU output  */
5130                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5131                         DRM_DEBUG_KMS("Using SSC on panel\n");
5132                         val |= DREF_SSC1_ENABLE;
5133                 } else
5134                         val &= ~DREF_SSC1_ENABLE;
5135
5136                 /* Get SSC going before enabling the outputs */
5137                 I915_WRITE(PCH_DREF_CONTROL, val);
5138                 POSTING_READ(PCH_DREF_CONTROL);
5139                 udelay(200);
5140
5141                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5142
5143                 /* Enable CPU source on CPU attached eDP */
5144                 if (has_cpu_edp) {
5145                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5146                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5147                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5148                         }
5149                         else
5150                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5151                 } else
5152                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5153
5154                 I915_WRITE(PCH_DREF_CONTROL, val);
5155                 POSTING_READ(PCH_DREF_CONTROL);
5156                 udelay(200);
5157         } else {
5158                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5159
5160                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5161
5162                 /* Turn off CPU output */
5163                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5164
5165                 I915_WRITE(PCH_DREF_CONTROL, val);
5166                 POSTING_READ(PCH_DREF_CONTROL);
5167                 udelay(200);
5168
5169                 /* Turn off the SSC source */
5170                 val &= ~DREF_SSC_SOURCE_MASK;
5171                 val |= DREF_SSC_SOURCE_DISABLE;
5172
5173                 /* Turn off SSC1 */
5174                 val &= ~DREF_SSC1_ENABLE;
5175
5176                 I915_WRITE(PCH_DREF_CONTROL, val);
5177                 POSTING_READ(PCH_DREF_CONTROL);
5178                 udelay(200);
5179         }
5180
5181         BUG_ON(val != final);
5182 }
5183
5184 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5185 {
5186         uint32_t tmp;
5187
5188         tmp = I915_READ(SOUTH_CHICKEN2);
5189         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5190         I915_WRITE(SOUTH_CHICKEN2, tmp);
5191
5192         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5193                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5194                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5195
5196         tmp = I915_READ(SOUTH_CHICKEN2);
5197         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5198         I915_WRITE(SOUTH_CHICKEN2, tmp);
5199
5200         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5201                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5202                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5203 }
5204
5205 /* WaMPhyProgramming:hsw */
5206 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5207 {
5208         uint32_t tmp;
5209
5210         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5211         tmp &= ~(0xFF << 24);
5212         tmp |= (0x12 << 24);
5213         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5214
5215         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5216         tmp |= (1 << 11);
5217         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5218
5219         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5220         tmp |= (1 << 11);
5221         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5222
5223         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5224         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5226
5227         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5228         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5229         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5230
5231         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5232         tmp &= ~(7 << 13);
5233         tmp |= (5 << 13);
5234         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5235
5236         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5237         tmp &= ~(7 << 13);
5238         tmp |= (5 << 13);
5239         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5240
5241         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5242         tmp &= ~0xFF;
5243         tmp |= 0x1C;
5244         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5247         tmp &= ~0xFF;
5248         tmp |= 0x1C;
5249         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5252         tmp &= ~(0xFF << 16);
5253         tmp |= (0x1C << 16);
5254         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5255
5256         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5257         tmp &= ~(0xFF << 16);
5258         tmp |= (0x1C << 16);
5259         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5260
5261         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5262         tmp |= (1 << 27);
5263         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5264
5265         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5266         tmp |= (1 << 27);
5267         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5268
5269         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5270         tmp &= ~(0xF << 28);
5271         tmp |= (4 << 28);
5272         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5273
5274         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5275         tmp &= ~(0xF << 28);
5276         tmp |= (4 << 28);
5277         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5278 }
5279
5280 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5281  * Programming" based on the parameters passed:
5282  * - Sequence to enable CLKOUT_DP
5283  * - Sequence to enable CLKOUT_DP without spread
5284  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5285  */
5286 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5287                                  bool with_fdi)
5288 {
5289         struct drm_i915_private *dev_priv = dev->dev_private;
5290         uint32_t reg, tmp;
5291
5292         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5293                 with_spread = true;
5294         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5295                  with_fdi, "LP PCH doesn't have FDI\n"))
5296                 with_fdi = false;
5297
5298         mutex_lock(&dev_priv->dpio_lock);
5299
5300         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5301         tmp &= ~SBI_SSCCTL_DISABLE;
5302         tmp |= SBI_SSCCTL_PATHALT;
5303         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5304
5305         udelay(24);
5306
5307         if (with_spread) {
5308                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5309                 tmp &= ~SBI_SSCCTL_PATHALT;
5310                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5311
5312                 if (with_fdi) {
5313                         lpt_reset_fdi_mphy(dev_priv);
5314                         lpt_program_fdi_mphy(dev_priv);
5315                 }
5316         }
5317
5318         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5319                SBI_GEN0 : SBI_DBUFF0;
5320         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5321         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5322         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5323
5324         mutex_unlock(&dev_priv->dpio_lock);
5325 }
5326
5327 /* Sequence to disable CLKOUT_DP */
5328 static void lpt_disable_clkout_dp(struct drm_device *dev)
5329 {
5330         struct drm_i915_private *dev_priv = dev->dev_private;
5331         uint32_t reg, tmp;
5332
5333         mutex_lock(&dev_priv->dpio_lock);
5334
5335         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5336                SBI_GEN0 : SBI_DBUFF0;
5337         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5338         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5339         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5340
5341         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5342         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5343                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5344                         tmp |= SBI_SSCCTL_PATHALT;
5345                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5346                         udelay(32);
5347                 }
5348                 tmp |= SBI_SSCCTL_DISABLE;
5349                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5350         }
5351
5352         mutex_unlock(&dev_priv->dpio_lock);
5353 }
5354
5355 static void lpt_init_pch_refclk(struct drm_device *dev)
5356 {
5357         struct drm_mode_config *mode_config = &dev->mode_config;
5358         struct intel_encoder *encoder;
5359         bool has_vga = false;
5360
5361         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5362                 switch (encoder->type) {
5363                 case INTEL_OUTPUT_ANALOG:
5364                         has_vga = true;
5365                         break;
5366                 }
5367         }
5368
5369         if (has_vga)
5370                 lpt_enable_clkout_dp(dev, true, true);
5371         else
5372                 lpt_disable_clkout_dp(dev);
5373 }
5374
5375 /*
5376  * Initialize reference clocks when the driver loads
5377  */
5378 void intel_init_pch_refclk(struct drm_device *dev)
5379 {
5380         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5381                 ironlake_init_pch_refclk(dev);
5382         else if (HAS_PCH_LPT(dev))
5383                 lpt_init_pch_refclk(dev);
5384 }
5385
5386 static int ironlake_get_refclk(struct drm_crtc *crtc)
5387 {
5388         struct drm_device *dev = crtc->dev;
5389         struct drm_i915_private *dev_priv = dev->dev_private;
5390         struct intel_encoder *encoder;
5391         int num_connectors = 0;
5392         bool is_lvds = false;
5393
5394         for_each_encoder_on_crtc(dev, crtc, encoder) {
5395                 switch (encoder->type) {
5396                 case INTEL_OUTPUT_LVDS:
5397                         is_lvds = true;
5398                         break;
5399                 }
5400                 num_connectors++;
5401         }
5402
5403         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5404                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5405                               dev_priv->vbt.lvds_ssc_freq);
5406                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5407         }
5408
5409         return 120000;
5410 }
5411
5412 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5413 {
5414         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5416         int pipe = intel_crtc->pipe;
5417         uint32_t val;
5418
5419         val = 0;
5420
5421         switch (intel_crtc->config.pipe_bpp) {
5422         case 18:
5423                 val |= PIPECONF_6BPC;
5424                 break;
5425         case 24:
5426                 val |= PIPECONF_8BPC;
5427                 break;
5428         case 30:
5429                 val |= PIPECONF_10BPC;
5430                 break;
5431         case 36:
5432                 val |= PIPECONF_12BPC;
5433                 break;
5434         default:
5435                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5436                 BUG();
5437         }
5438
5439         if (intel_crtc->config.dither)
5440                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5441
5442         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5443                 val |= PIPECONF_INTERLACED_ILK;
5444         else
5445                 val |= PIPECONF_PROGRESSIVE;
5446
5447         if (intel_crtc->config.limited_color_range)
5448                 val |= PIPECONF_COLOR_RANGE_SELECT;
5449
5450         I915_WRITE(PIPECONF(pipe), val);
5451         POSTING_READ(PIPECONF(pipe));
5452 }
5453
5454 /*
5455  * Set up the pipe CSC unit.
5456  *
5457  * Currently only full range RGB to limited range RGB conversion
5458  * is supported, but eventually this should handle various
5459  * RGB<->YCbCr scenarios as well.
5460  */
5461 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5462 {
5463         struct drm_device *dev = crtc->dev;
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5466         int pipe = intel_crtc->pipe;
5467         uint16_t coeff = 0x7800; /* 1.0 */
5468
5469         /*
5470          * TODO: Check what kind of values actually come out of the pipe
5471          * with these coeff/postoff values and adjust to get the best
5472          * accuracy. Perhaps we even need to take the bpc value into
5473          * consideration.
5474          */
5475
5476         if (intel_crtc->config.limited_color_range)
5477                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5478
5479         /*
5480          * GY/GU and RY/RU should be the other way around according
5481          * to BSpec, but reality doesn't agree. Just set them up in
5482          * a way that results in the correct picture.
5483          */
5484         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5485         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5486
5487         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5488         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5489
5490         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5491         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5492
5493         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5494         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5495         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5496
5497         if (INTEL_INFO(dev)->gen > 6) {
5498                 uint16_t postoff = 0;
5499
5500                 if (intel_crtc->config.limited_color_range)
5501                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5502
5503                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5504                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5505                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5506
5507                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5508         } else {
5509                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5510
5511                 if (intel_crtc->config.limited_color_range)
5512                         mode |= CSC_BLACK_SCREEN_OFFSET;
5513
5514                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5515         }
5516 }
5517
5518 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5519 {
5520         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5522         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5523         uint32_t val;
5524
5525         val = 0;
5526
5527         if (intel_crtc->config.dither)
5528                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5529
5530         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5531                 val |= PIPECONF_INTERLACED_ILK;
5532         else
5533                 val |= PIPECONF_PROGRESSIVE;
5534
5535         I915_WRITE(PIPECONF(cpu_transcoder), val);
5536         POSTING_READ(PIPECONF(cpu_transcoder));
5537
5538         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5539         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5540 }
5541
5542 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5543                                     intel_clock_t *clock,
5544                                     bool *has_reduced_clock,
5545                                     intel_clock_t *reduced_clock)
5546 {
5547         struct drm_device *dev = crtc->dev;
5548         struct drm_i915_private *dev_priv = dev->dev_private;
5549         struct intel_encoder *intel_encoder;
5550         int refclk;
5551         const intel_limit_t *limit;
5552         bool ret, is_lvds = false;
5553
5554         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5555                 switch (intel_encoder->type) {
5556                 case INTEL_OUTPUT_LVDS:
5557                         is_lvds = true;
5558                         break;
5559                 }
5560         }
5561
5562         refclk = ironlake_get_refclk(crtc);
5563
5564         /*
5565          * Returns a set of divisors for the desired target clock with the given
5566          * refclk, or FALSE.  The returned values represent the clock equation:
5567          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5568          */
5569         limit = intel_limit(crtc, refclk);
5570         ret = dev_priv->display.find_dpll(limit, crtc,
5571                                           to_intel_crtc(crtc)->config.port_clock,
5572                                           refclk, NULL, clock);
5573         if (!ret)
5574                 return false;
5575
5576         if (is_lvds && dev_priv->lvds_downclock_avail) {
5577                 /*
5578                  * Ensure we match the reduced clock's P to the target clock.
5579                  * If the clocks don't match, we can't switch the display clock
5580                  * by using the FP0/FP1. In such case we will disable the LVDS
5581                  * downclock feature.
5582                 */
5583                 *has_reduced_clock =
5584                         dev_priv->display.find_dpll(limit, crtc,
5585                                                     dev_priv->lvds_downclock,
5586                                                     refclk, clock,
5587                                                     reduced_clock);
5588         }
5589
5590         return true;
5591 }
5592
5593 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5594 {
5595         struct drm_i915_private *dev_priv = dev->dev_private;
5596         uint32_t temp;
5597
5598         temp = I915_READ(SOUTH_CHICKEN1);
5599         if (temp & FDI_BC_BIFURCATION_SELECT)
5600                 return;
5601
5602         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5603         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5604
5605         temp |= FDI_BC_BIFURCATION_SELECT;
5606         DRM_DEBUG_KMS("enabling fdi C rx\n");
5607         I915_WRITE(SOUTH_CHICKEN1, temp);
5608         POSTING_READ(SOUTH_CHICKEN1);
5609 }
5610
5611 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5612 {
5613         struct drm_device *dev = intel_crtc->base.dev;
5614         struct drm_i915_private *dev_priv = dev->dev_private;
5615
5616         switch (intel_crtc->pipe) {
5617         case PIPE_A:
5618                 break;
5619         case PIPE_B:
5620                 if (intel_crtc->config.fdi_lanes > 2)
5621                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5622                 else
5623                         cpt_enable_fdi_bc_bifurcation(dev);
5624
5625                 break;
5626         case PIPE_C:
5627                 cpt_enable_fdi_bc_bifurcation(dev);
5628
5629                 break;
5630         default:
5631                 BUG();
5632         }
5633 }
5634
5635 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5636 {
5637         /*
5638          * Account for spread spectrum to avoid
5639          * oversubscribing the link. Max center spread
5640          * is 2.5%; use 5% for safety's sake.
5641          */
5642         u32 bps = target_clock * bpp * 21 / 20;
5643         return bps / (link_bw * 8) + 1;
5644 }
5645
5646 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5647 {
5648         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5649 }
5650
5651 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5652                                       u32 *fp,
5653                                       intel_clock_t *reduced_clock, u32 *fp2)
5654 {
5655         struct drm_crtc *crtc = &intel_crtc->base;
5656         struct drm_device *dev = crtc->dev;
5657         struct drm_i915_private *dev_priv = dev->dev_private;
5658         struct intel_encoder *intel_encoder;
5659         uint32_t dpll;
5660         int factor, num_connectors = 0;
5661         bool is_lvds = false, is_sdvo = false;
5662
5663         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5664                 switch (intel_encoder->type) {
5665                 case INTEL_OUTPUT_LVDS:
5666                         is_lvds = true;
5667                         break;
5668                 case INTEL_OUTPUT_SDVO:
5669                 case INTEL_OUTPUT_HDMI:
5670                         is_sdvo = true;
5671                         break;
5672                 }
5673
5674                 num_connectors++;
5675         }
5676
5677         /* Enable autotuning of the PLL clock (if permissible) */
5678         factor = 21;
5679         if (is_lvds) {
5680                 if ((intel_panel_use_ssc(dev_priv) &&
5681                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5682                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5683                         factor = 25;
5684         } else if (intel_crtc->config.sdvo_tv_clock)
5685                 factor = 20;
5686
5687         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5688                 *fp |= FP_CB_TUNE;
5689
5690         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5691                 *fp2 |= FP_CB_TUNE;
5692
5693         dpll = 0;
5694
5695         if (is_lvds)
5696                 dpll |= DPLLB_MODE_LVDS;
5697         else
5698                 dpll |= DPLLB_MODE_DAC_SERIAL;
5699
5700         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5701                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5702
5703         if (is_sdvo)
5704                 dpll |= DPLL_SDVO_HIGH_SPEED;
5705         if (intel_crtc->config.has_dp_encoder)
5706                 dpll |= DPLL_SDVO_HIGH_SPEED;
5707
5708         /* compute bitmask from p1 value */
5709         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5710         /* also FPA1 */
5711         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5712
5713         switch (intel_crtc->config.dpll.p2) {
5714         case 5:
5715                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5716                 break;
5717         case 7:
5718                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5719                 break;
5720         case 10:
5721                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5722                 break;
5723         case 14:
5724                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5725                 break;
5726         }
5727
5728         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5729                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5730         else
5731                 dpll |= PLL_REF_INPUT_DREFCLK;
5732
5733         return dpll | DPLL_VCO_ENABLE;
5734 }
5735
5736 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5737                                   int x, int y,
5738                                   struct drm_framebuffer *fb)
5739 {
5740         struct drm_device *dev = crtc->dev;
5741         struct drm_i915_private *dev_priv = dev->dev_private;
5742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5743         int pipe = intel_crtc->pipe;
5744         int plane = intel_crtc->plane;
5745         int num_connectors = 0;
5746         intel_clock_t clock, reduced_clock;
5747         u32 dpll = 0, fp = 0, fp2 = 0;
5748         bool ok, has_reduced_clock = false;
5749         bool is_lvds = false;
5750         struct intel_encoder *encoder;
5751         struct intel_shared_dpll *pll;
5752         int ret;
5753
5754         for_each_encoder_on_crtc(dev, crtc, encoder) {
5755                 switch (encoder->type) {
5756                 case INTEL_OUTPUT_LVDS:
5757                         is_lvds = true;
5758                         break;
5759                 }
5760
5761                 num_connectors++;
5762         }
5763
5764         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5765              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5766
5767         ok = ironlake_compute_clocks(crtc, &clock,
5768                                      &has_reduced_clock, &reduced_clock);
5769         if (!ok && !intel_crtc->config.clock_set) {
5770                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5771                 return -EINVAL;
5772         }
5773         /* Compat-code for transition, will disappear. */
5774         if (!intel_crtc->config.clock_set) {
5775                 intel_crtc->config.dpll.n = clock.n;
5776                 intel_crtc->config.dpll.m1 = clock.m1;
5777                 intel_crtc->config.dpll.m2 = clock.m2;
5778                 intel_crtc->config.dpll.p1 = clock.p1;
5779                 intel_crtc->config.dpll.p2 = clock.p2;
5780         }
5781
5782         /* Ensure that the cursor is valid for the new mode before changing... */
5783         intel_crtc_update_cursor(crtc, true);
5784
5785         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5786         if (intel_crtc->config.has_pch_encoder) {
5787                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5788                 if (has_reduced_clock)
5789                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5790
5791                 dpll = ironlake_compute_dpll(intel_crtc,
5792                                              &fp, &reduced_clock,
5793                                              has_reduced_clock ? &fp2 : NULL);
5794
5795                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5796                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5797                 if (has_reduced_clock)
5798                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5799                 else
5800                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5801
5802                 pll = intel_get_shared_dpll(intel_crtc);
5803                 if (pll == NULL) {
5804                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5805                                          pipe_name(pipe));
5806                         return -EINVAL;
5807                 }
5808         } else
5809                 intel_put_shared_dpll(intel_crtc);
5810
5811         if (intel_crtc->config.has_dp_encoder)
5812                 intel_dp_set_m_n(intel_crtc);
5813
5814         if (is_lvds && has_reduced_clock && i915_powersave)
5815                 intel_crtc->lowfreq_avail = true;
5816         else
5817                 intel_crtc->lowfreq_avail = false;
5818
5819         if (intel_crtc->config.has_pch_encoder) {
5820                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5821
5822         }
5823
5824         intel_set_pipe_timings(intel_crtc);
5825
5826         if (intel_crtc->config.has_pch_encoder) {
5827                 intel_cpu_transcoder_set_m_n(intel_crtc,
5828                                              &intel_crtc->config.fdi_m_n);
5829         }
5830
5831         if (IS_IVYBRIDGE(dev))
5832                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5833
5834         ironlake_set_pipeconf(crtc);
5835
5836         /* Set up the display plane register */
5837         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5838         POSTING_READ(DSPCNTR(plane));
5839
5840         ret = intel_pipe_set_base(crtc, x, y, fb);
5841
5842         intel_update_watermarks(dev);
5843
5844         return ret;
5845 }
5846
5847 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5848                                         struct intel_crtc_config *pipe_config)
5849 {
5850         struct drm_device *dev = crtc->base.dev;
5851         struct drm_i915_private *dev_priv = dev->dev_private;
5852         enum transcoder transcoder = pipe_config->cpu_transcoder;
5853
5854         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5855         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5856         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5857                                         & ~TU_SIZE_MASK;
5858         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5859         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5860                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5861 }
5862
5863 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5864                                      struct intel_crtc_config *pipe_config)
5865 {
5866         struct drm_device *dev = crtc->base.dev;
5867         struct drm_i915_private *dev_priv = dev->dev_private;
5868         uint32_t tmp;
5869
5870         tmp = I915_READ(PF_CTL(crtc->pipe));
5871
5872         if (tmp & PF_ENABLE) {
5873                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5874                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5875
5876                 /* We currently do not free assignements of panel fitters on
5877                  * ivb/hsw (since we don't use the higher upscaling modes which
5878                  * differentiates them) so just WARN about this case for now. */
5879                 if (IS_GEN7(dev)) {
5880                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5881                                 PF_PIPE_SEL_IVB(crtc->pipe));
5882                 }
5883         }
5884 }
5885
5886 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5887                                      struct intel_crtc_config *pipe_config)
5888 {
5889         struct drm_device *dev = crtc->base.dev;
5890         struct drm_i915_private *dev_priv = dev->dev_private;
5891         uint32_t tmp;
5892
5893         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5894         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5895
5896         tmp = I915_READ(PIPECONF(crtc->pipe));
5897         if (!(tmp & PIPECONF_ENABLE))
5898                 return false;
5899
5900         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5901                 struct intel_shared_dpll *pll;
5902
5903                 pipe_config->has_pch_encoder = true;
5904
5905                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5906                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5907                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5908
5909                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5910
5911                 if (HAS_PCH_IBX(dev_priv->dev)) {
5912                         pipe_config->shared_dpll =
5913                                 (enum intel_dpll_id) crtc->pipe;
5914                 } else {
5915                         tmp = I915_READ(PCH_DPLL_SEL);
5916                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5917                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5918                         else
5919                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5920                 }
5921
5922                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5923
5924                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5925                                            &pipe_config->dpll_hw_state));
5926
5927                 tmp = pipe_config->dpll_hw_state.dpll;
5928                 pipe_config->pixel_multiplier =
5929                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5930                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5931         } else {
5932                 pipe_config->pixel_multiplier = 1;
5933         }
5934
5935         intel_get_pipe_timings(crtc, pipe_config);
5936
5937         ironlake_get_pfit_config(crtc, pipe_config);
5938
5939         return true;
5940 }
5941
5942 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5943 {
5944         struct drm_device *dev = dev_priv->dev;
5945         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5946         struct intel_crtc *crtc;
5947         unsigned long irqflags;
5948         uint32_t val, pch_hpd_mask;
5949
5950         pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5951         if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5952                 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5953
5954         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5955                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5956                      pipe_name(crtc->pipe));
5957
5958         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5959         WARN(plls->spll_refcount, "SPLL enabled\n");
5960         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5961         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5962         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5963         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5964              "CPU PWM1 enabled\n");
5965         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5966              "CPU PWM2 enabled\n");
5967         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5968              "PCH PWM1 enabled\n");
5969         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5970              "Utility pin enabled\n");
5971         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5972
5973         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5974         val = I915_READ(DEIMR);
5975         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5976              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5977         val = I915_READ(SDEIMR);
5978         WARN((val & ~pch_hpd_mask) != val,
5979              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5980         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5981 }
5982
5983 /*
5984  * This function implements pieces of two sequences from BSpec:
5985  * - Sequence for display software to disable LCPLL
5986  * - Sequence for display software to allow package C8+
5987  * The steps implemented here are just the steps that actually touch the LCPLL
5988  * register. Callers should take care of disabling all the display engine
5989  * functions, doing the mode unset, fixing interrupts, etc.
5990  */
5991 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5992                        bool switch_to_fclk, bool allow_power_down)
5993 {
5994         uint32_t val;
5995
5996         assert_can_disable_lcpll(dev_priv);
5997
5998         val = I915_READ(LCPLL_CTL);
5999
6000         if (switch_to_fclk) {
6001                 val |= LCPLL_CD_SOURCE_FCLK;
6002                 I915_WRITE(LCPLL_CTL, val);
6003
6004                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6005                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6006                         DRM_ERROR("Switching to FCLK failed\n");
6007
6008                 val = I915_READ(LCPLL_CTL);
6009         }
6010
6011         val |= LCPLL_PLL_DISABLE;
6012         I915_WRITE(LCPLL_CTL, val);
6013         POSTING_READ(LCPLL_CTL);
6014
6015         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6016                 DRM_ERROR("LCPLL still locked\n");
6017
6018         val = I915_READ(D_COMP);
6019         val |= D_COMP_COMP_DISABLE;
6020         I915_WRITE(D_COMP, val);
6021         POSTING_READ(D_COMP);
6022         ndelay(100);
6023
6024         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6025                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6026
6027         if (allow_power_down) {
6028                 val = I915_READ(LCPLL_CTL);
6029                 val |= LCPLL_POWER_DOWN_ALLOW;
6030                 I915_WRITE(LCPLL_CTL, val);
6031                 POSTING_READ(LCPLL_CTL);
6032         }
6033 }
6034
6035 /*
6036  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6037  * source.
6038  */
6039 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6040 {
6041         uint32_t val;
6042
6043         val = I915_READ(LCPLL_CTL);
6044
6045         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6046                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6047                 return;
6048
6049         if (val & LCPLL_POWER_DOWN_ALLOW) {
6050                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6051                 I915_WRITE(LCPLL_CTL, val);
6052         }
6053
6054         val = I915_READ(D_COMP);
6055         val |= D_COMP_COMP_FORCE;
6056         val &= ~D_COMP_COMP_DISABLE;
6057         I915_WRITE(D_COMP, val);
6058         I915_READ(D_COMP);
6059
6060         val = I915_READ(LCPLL_CTL);
6061         val &= ~LCPLL_PLL_DISABLE;
6062         I915_WRITE(LCPLL_CTL, val);
6063
6064         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6065                 DRM_ERROR("LCPLL not locked yet\n");
6066
6067         if (val & LCPLL_CD_SOURCE_FCLK) {
6068                 val = I915_READ(LCPLL_CTL);
6069                 val &= ~LCPLL_CD_SOURCE_FCLK;
6070                 I915_WRITE(LCPLL_CTL, val);
6071
6072                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6073                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6074                         DRM_ERROR("Switching back to LCPLL failed\n");
6075         }
6076 }
6077
6078 static void haswell_modeset_global_resources(struct drm_device *dev)
6079 {
6080         bool enable = false;
6081         struct intel_crtc *crtc;
6082
6083         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6084                 if (!crtc->base.enabled)
6085                         continue;
6086
6087                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6088                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6089                         enable = true;
6090         }
6091
6092         intel_set_power_well(dev, enable);
6093 }
6094
6095 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6096                                  int x, int y,
6097                                  struct drm_framebuffer *fb)
6098 {
6099         struct drm_device *dev = crtc->dev;
6100         struct drm_i915_private *dev_priv = dev->dev_private;
6101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102         int plane = intel_crtc->plane;
6103         int ret;
6104
6105         if (!intel_ddi_pll_mode_set(crtc))
6106                 return -EINVAL;
6107
6108         /* Ensure that the cursor is valid for the new mode before changing... */
6109         intel_crtc_update_cursor(crtc, true);
6110
6111         if (intel_crtc->config.has_dp_encoder)
6112                 intel_dp_set_m_n(intel_crtc);
6113
6114         intel_crtc->lowfreq_avail = false;
6115
6116         intel_set_pipe_timings(intel_crtc);
6117
6118         if (intel_crtc->config.has_pch_encoder) {
6119                 intel_cpu_transcoder_set_m_n(intel_crtc,
6120                                              &intel_crtc->config.fdi_m_n);
6121         }
6122
6123         haswell_set_pipeconf(crtc);
6124
6125         intel_set_pipe_csc(crtc);
6126
6127         /* Set up the display plane register */
6128         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6129         POSTING_READ(DSPCNTR(plane));
6130
6131         ret = intel_pipe_set_base(crtc, x, y, fb);
6132
6133         intel_update_watermarks(dev);
6134
6135         return ret;
6136 }
6137
6138 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6139                                     struct intel_crtc_config *pipe_config)
6140 {
6141         struct drm_device *dev = crtc->base.dev;
6142         struct drm_i915_private *dev_priv = dev->dev_private;
6143         enum intel_display_power_domain pfit_domain;
6144         uint32_t tmp;
6145
6146         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6147         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6148
6149         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6150         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6151                 enum pipe trans_edp_pipe;
6152                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6153                 default:
6154                         WARN(1, "unknown pipe linked to edp transcoder\n");
6155                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6156                 case TRANS_DDI_EDP_INPUT_A_ON:
6157                         trans_edp_pipe = PIPE_A;
6158                         break;
6159                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6160                         trans_edp_pipe = PIPE_B;
6161                         break;
6162                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6163                         trans_edp_pipe = PIPE_C;
6164                         break;
6165                 }
6166
6167                 if (trans_edp_pipe == crtc->pipe)
6168                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6169         }
6170
6171         if (!intel_display_power_enabled(dev,
6172                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6173                 return false;
6174
6175         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6176         if (!(tmp & PIPECONF_ENABLE))
6177                 return false;
6178
6179         /*
6180          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6181          * DDI E. So just check whether this pipe is wired to DDI E and whether
6182          * the PCH transcoder is on.
6183          */
6184         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6185         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6186             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6187                 pipe_config->has_pch_encoder = true;
6188
6189                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6190                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6191                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6192
6193                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6194         }
6195
6196         intel_get_pipe_timings(crtc, pipe_config);
6197
6198         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6199         if (intel_display_power_enabled(dev, pfit_domain))
6200                 ironlake_get_pfit_config(crtc, pipe_config);
6201
6202         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6203                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6204
6205         pipe_config->pixel_multiplier = 1;
6206
6207         return true;
6208 }
6209
6210 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6211                                int x, int y,
6212                                struct drm_framebuffer *fb)
6213 {
6214         struct drm_device *dev = crtc->dev;
6215         struct drm_i915_private *dev_priv = dev->dev_private;
6216         struct intel_encoder *encoder;
6217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6218         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6219         int pipe = intel_crtc->pipe;
6220         int ret;
6221
6222         drm_vblank_pre_modeset(dev, pipe);
6223
6224         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6225
6226         drm_vblank_post_modeset(dev, pipe);
6227
6228         if (ret != 0)
6229                 return ret;
6230
6231         for_each_encoder_on_crtc(dev, crtc, encoder) {
6232                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6233                         encoder->base.base.id,
6234                         drm_get_encoder_name(&encoder->base),
6235                         mode->base.id, mode->name);
6236                 encoder->mode_set(encoder);
6237         }
6238
6239         return 0;
6240 }
6241
6242 static bool intel_eld_uptodate(struct drm_connector *connector,
6243                                int reg_eldv, uint32_t bits_eldv,
6244                                int reg_elda, uint32_t bits_elda,
6245                                int reg_edid)
6246 {
6247         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6248         uint8_t *eld = connector->eld;
6249         uint32_t i;
6250
6251         i = I915_READ(reg_eldv);
6252         i &= bits_eldv;
6253
6254         if (!eld[0])
6255                 return !i;
6256
6257         if (!i)
6258                 return false;
6259
6260         i = I915_READ(reg_elda);
6261         i &= ~bits_elda;
6262         I915_WRITE(reg_elda, i);
6263
6264         for (i = 0; i < eld[2]; i++)
6265                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6266                         return false;
6267
6268         return true;
6269 }
6270
6271 static void g4x_write_eld(struct drm_connector *connector,
6272                           struct drm_crtc *crtc)
6273 {
6274         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6275         uint8_t *eld = connector->eld;
6276         uint32_t eldv;
6277         uint32_t len;
6278         uint32_t i;
6279
6280         i = I915_READ(G4X_AUD_VID_DID);
6281
6282         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6283                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6284         else
6285                 eldv = G4X_ELDV_DEVCTG;
6286
6287         if (intel_eld_uptodate(connector,
6288                                G4X_AUD_CNTL_ST, eldv,
6289                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6290                                G4X_HDMIW_HDMIEDID))
6291                 return;
6292
6293         i = I915_READ(G4X_AUD_CNTL_ST);
6294         i &= ~(eldv | G4X_ELD_ADDR);
6295         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6296         I915_WRITE(G4X_AUD_CNTL_ST, i);
6297
6298         if (!eld[0])
6299                 return;
6300
6301         len = min_t(uint8_t, eld[2], len);
6302         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6303         for (i = 0; i < len; i++)
6304                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6305
6306         i = I915_READ(G4X_AUD_CNTL_ST);
6307         i |= eldv;
6308         I915_WRITE(G4X_AUD_CNTL_ST, i);
6309 }
6310
6311 static void haswell_write_eld(struct drm_connector *connector,
6312                                      struct drm_crtc *crtc)
6313 {
6314         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6315         uint8_t *eld = connector->eld;
6316         struct drm_device *dev = crtc->dev;
6317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6318         uint32_t eldv;
6319         uint32_t i;
6320         int len;
6321         int pipe = to_intel_crtc(crtc)->pipe;
6322         int tmp;
6323
6324         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6325         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6326         int aud_config = HSW_AUD_CFG(pipe);
6327         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6328
6329
6330         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6331
6332         /* Audio output enable */
6333         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6334         tmp = I915_READ(aud_cntrl_st2);
6335         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6336         I915_WRITE(aud_cntrl_st2, tmp);
6337
6338         /* Wait for 1 vertical blank */
6339         intel_wait_for_vblank(dev, pipe);
6340
6341         /* Set ELD valid state */
6342         tmp = I915_READ(aud_cntrl_st2);
6343         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6344         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6345         I915_WRITE(aud_cntrl_st2, tmp);
6346         tmp = I915_READ(aud_cntrl_st2);
6347         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6348
6349         /* Enable HDMI mode */
6350         tmp = I915_READ(aud_config);
6351         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6352         /* clear N_programing_enable and N_value_index */
6353         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6354         I915_WRITE(aud_config, tmp);
6355
6356         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6357
6358         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6359         intel_crtc->eld_vld = true;
6360
6361         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6362                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6363                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6364                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6365         } else
6366                 I915_WRITE(aud_config, 0);
6367
6368         if (intel_eld_uptodate(connector,
6369                                aud_cntrl_st2, eldv,
6370                                aud_cntl_st, IBX_ELD_ADDRESS,
6371                                hdmiw_hdmiedid))
6372                 return;
6373
6374         i = I915_READ(aud_cntrl_st2);
6375         i &= ~eldv;
6376         I915_WRITE(aud_cntrl_st2, i);
6377
6378         if (!eld[0])
6379                 return;
6380
6381         i = I915_READ(aud_cntl_st);
6382         i &= ~IBX_ELD_ADDRESS;
6383         I915_WRITE(aud_cntl_st, i);
6384         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6385         DRM_DEBUG_DRIVER("port num:%d\n", i);
6386
6387         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6388         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6389         for (i = 0; i < len; i++)
6390                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6391
6392         i = I915_READ(aud_cntrl_st2);
6393         i |= eldv;
6394         I915_WRITE(aud_cntrl_st2, i);
6395
6396 }
6397
6398 static void ironlake_write_eld(struct drm_connector *connector,
6399                                      struct drm_crtc *crtc)
6400 {
6401         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6402         uint8_t *eld = connector->eld;
6403         uint32_t eldv;
6404         uint32_t i;
6405         int len;
6406         int hdmiw_hdmiedid;
6407         int aud_config;
6408         int aud_cntl_st;
6409         int aud_cntrl_st2;
6410         int pipe = to_intel_crtc(crtc)->pipe;
6411
6412         if (HAS_PCH_IBX(connector->dev)) {
6413                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6414                 aud_config = IBX_AUD_CFG(pipe);
6415                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6416                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6417         } else {
6418                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6419                 aud_config = CPT_AUD_CFG(pipe);
6420                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6421                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6422         }
6423
6424         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6425
6426         i = I915_READ(aud_cntl_st);
6427         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6428         if (!i) {
6429                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6430                 /* operate blindly on all ports */
6431                 eldv = IBX_ELD_VALIDB;
6432                 eldv |= IBX_ELD_VALIDB << 4;
6433                 eldv |= IBX_ELD_VALIDB << 8;
6434         } else {
6435                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6436                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6437         }
6438
6439         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6440                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6441                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6442                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6443         } else
6444                 I915_WRITE(aud_config, 0);
6445
6446         if (intel_eld_uptodate(connector,
6447                                aud_cntrl_st2, eldv,
6448                                aud_cntl_st, IBX_ELD_ADDRESS,
6449                                hdmiw_hdmiedid))
6450                 return;
6451
6452         i = I915_READ(aud_cntrl_st2);
6453         i &= ~eldv;
6454         I915_WRITE(aud_cntrl_st2, i);
6455
6456         if (!eld[0])
6457                 return;
6458
6459         i = I915_READ(aud_cntl_st);
6460         i &= ~IBX_ELD_ADDRESS;
6461         I915_WRITE(aud_cntl_st, i);
6462
6463         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6464         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6465         for (i = 0; i < len; i++)
6466                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6467
6468         i = I915_READ(aud_cntrl_st2);
6469         i |= eldv;
6470         I915_WRITE(aud_cntrl_st2, i);
6471 }
6472
6473 void intel_write_eld(struct drm_encoder *encoder,
6474                      struct drm_display_mode *mode)
6475 {
6476         struct drm_crtc *crtc = encoder->crtc;
6477         struct drm_connector *connector;
6478         struct drm_device *dev = encoder->dev;
6479         struct drm_i915_private *dev_priv = dev->dev_private;
6480
6481         connector = drm_select_eld(encoder, mode);
6482         if (!connector)
6483                 return;
6484
6485         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6486                          connector->base.id,
6487                          drm_get_connector_name(connector),
6488                          connector->encoder->base.id,
6489                          drm_get_encoder_name(connector->encoder));
6490
6491         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6492
6493         if (dev_priv->display.write_eld)
6494                 dev_priv->display.write_eld(connector, crtc);
6495 }
6496
6497 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6498 void intel_crtc_load_lut(struct drm_crtc *crtc)
6499 {
6500         struct drm_device *dev = crtc->dev;
6501         struct drm_i915_private *dev_priv = dev->dev_private;
6502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6503         enum pipe pipe = intel_crtc->pipe;
6504         int palreg = PALETTE(pipe);
6505         int i;
6506         bool reenable_ips = false;
6507
6508         /* The clocks have to be on to load the palette. */
6509         if (!crtc->enabled || !intel_crtc->active)
6510                 return;
6511
6512         if (!HAS_PCH_SPLIT(dev_priv->dev))
6513                 assert_pll_enabled(dev_priv, pipe);
6514
6515         /* use legacy palette for Ironlake */
6516         if (HAS_PCH_SPLIT(dev))
6517                 palreg = LGC_PALETTE(pipe);
6518
6519         /* Workaround : Do not read or write the pipe palette/gamma data while
6520          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6521          */
6522         if (intel_crtc->config.ips_enabled &&
6523             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6524              GAMMA_MODE_MODE_SPLIT)) {
6525                 hsw_disable_ips(intel_crtc);
6526                 reenable_ips = true;
6527         }
6528
6529         for (i = 0; i < 256; i++) {
6530                 I915_WRITE(palreg + 4 * i,
6531                            (intel_crtc->lut_r[i] << 16) |
6532                            (intel_crtc->lut_g[i] << 8) |
6533                            intel_crtc->lut_b[i]);
6534         }
6535
6536         if (reenable_ips)
6537                 hsw_enable_ips(intel_crtc);
6538 }
6539
6540 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6541 {
6542         struct drm_device *dev = crtc->dev;
6543         struct drm_i915_private *dev_priv = dev->dev_private;
6544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6545         bool visible = base != 0;
6546         u32 cntl;
6547
6548         if (intel_crtc->cursor_visible == visible)
6549                 return;
6550
6551         cntl = I915_READ(_CURACNTR);
6552         if (visible) {
6553                 /* On these chipsets we can only modify the base whilst
6554                  * the cursor is disabled.
6555                  */
6556                 I915_WRITE(_CURABASE, base);
6557
6558                 cntl &= ~(CURSOR_FORMAT_MASK);
6559                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6560                 cntl |= CURSOR_ENABLE |
6561                         CURSOR_GAMMA_ENABLE |
6562                         CURSOR_FORMAT_ARGB;
6563         } else
6564                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6565         I915_WRITE(_CURACNTR, cntl);
6566
6567         intel_crtc->cursor_visible = visible;
6568 }
6569
6570 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6571 {
6572         struct drm_device *dev = crtc->dev;
6573         struct drm_i915_private *dev_priv = dev->dev_private;
6574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575         int pipe = intel_crtc->pipe;
6576         bool visible = base != 0;
6577
6578         if (intel_crtc->cursor_visible != visible) {
6579                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6580                 if (base) {
6581                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6582                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6583                         cntl |= pipe << 28; /* Connect to correct pipe */
6584                 } else {
6585                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6586                         cntl |= CURSOR_MODE_DISABLE;
6587                 }
6588                 I915_WRITE(CURCNTR(pipe), cntl);
6589
6590                 intel_crtc->cursor_visible = visible;
6591         }
6592         /* and commit changes on next vblank */
6593         I915_WRITE(CURBASE(pipe), base);
6594 }
6595
6596 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6597 {
6598         struct drm_device *dev = crtc->dev;
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601         int pipe = intel_crtc->pipe;
6602         bool visible = base != 0;
6603
6604         if (intel_crtc->cursor_visible != visible) {
6605                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6606                 if (base) {
6607                         cntl &= ~CURSOR_MODE;
6608                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6609                 } else {
6610                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6611                         cntl |= CURSOR_MODE_DISABLE;
6612                 }
6613                 if (IS_HASWELL(dev))
6614                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6615                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6616
6617                 intel_crtc->cursor_visible = visible;
6618         }
6619         /* and commit changes on next vblank */
6620         I915_WRITE(CURBASE_IVB(pipe), base);
6621 }
6622
6623 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6624 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6625                                      bool on)
6626 {
6627         struct drm_device *dev = crtc->dev;
6628         struct drm_i915_private *dev_priv = dev->dev_private;
6629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6630         int pipe = intel_crtc->pipe;
6631         int x = intel_crtc->cursor_x;
6632         int y = intel_crtc->cursor_y;
6633         u32 base, pos;
6634         bool visible;
6635
6636         pos = 0;
6637
6638         if (on && crtc->enabled && crtc->fb) {
6639                 base = intel_crtc->cursor_addr;
6640                 if (x > (int) crtc->fb->width)
6641                         base = 0;
6642
6643                 if (y > (int) crtc->fb->height)
6644                         base = 0;
6645         } else
6646                 base = 0;
6647
6648         if (x < 0) {
6649                 if (x + intel_crtc->cursor_width < 0)
6650                         base = 0;
6651
6652                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6653                 x = -x;
6654         }
6655         pos |= x << CURSOR_X_SHIFT;
6656
6657         if (y < 0) {
6658                 if (y + intel_crtc->cursor_height < 0)
6659                         base = 0;
6660
6661                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6662                 y = -y;
6663         }
6664         pos |= y << CURSOR_Y_SHIFT;
6665
6666         visible = base != 0;
6667         if (!visible && !intel_crtc->cursor_visible)
6668                 return;
6669
6670         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6671                 I915_WRITE(CURPOS_IVB(pipe), pos);
6672                 ivb_update_cursor(crtc, base);
6673         } else {
6674                 I915_WRITE(CURPOS(pipe), pos);
6675                 if (IS_845G(dev) || IS_I865G(dev))
6676                         i845_update_cursor(crtc, base);
6677                 else
6678                         i9xx_update_cursor(crtc, base);
6679         }
6680 }
6681
6682 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6683                                  struct drm_file *file,
6684                                  uint32_t handle,
6685                                  uint32_t width, uint32_t height)
6686 {
6687         struct drm_device *dev = crtc->dev;
6688         struct drm_i915_private *dev_priv = dev->dev_private;
6689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6690         struct drm_i915_gem_object *obj;
6691         uint32_t addr;
6692         int ret;
6693
6694         /* if we want to turn off the cursor ignore width and height */
6695         if (!handle) {
6696                 DRM_DEBUG_KMS("cursor off\n");
6697                 addr = 0;
6698                 obj = NULL;
6699                 mutex_lock(&dev->struct_mutex);
6700                 goto finish;
6701         }
6702
6703         /* Currently we only support 64x64 cursors */
6704         if (width != 64 || height != 64) {
6705                 DRM_ERROR("we currently only support 64x64 cursors\n");
6706                 return -EINVAL;
6707         }
6708
6709         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6710         if (&obj->base == NULL)
6711                 return -ENOENT;
6712
6713         if (obj->base.size < width * height * 4) {
6714                 DRM_ERROR("buffer is to small\n");
6715                 ret = -ENOMEM;
6716                 goto fail;
6717         }
6718
6719         /* we only need to pin inside GTT if cursor is non-phy */
6720         mutex_lock(&dev->struct_mutex);
6721         if (!dev_priv->info->cursor_needs_physical) {
6722                 unsigned alignment;
6723
6724                 if (obj->tiling_mode) {
6725                         DRM_ERROR("cursor cannot be tiled\n");
6726                         ret = -EINVAL;
6727                         goto fail_locked;
6728                 }
6729
6730                 /* Note that the w/a also requires 2 PTE of padding following
6731                  * the bo. We currently fill all unused PTE with the shadow
6732                  * page and so we should always have valid PTE following the
6733                  * cursor preventing the VT-d warning.
6734                  */
6735                 alignment = 0;
6736                 if (need_vtd_wa(dev))
6737                         alignment = 64*1024;
6738
6739                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6740                 if (ret) {
6741                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6742                         goto fail_locked;
6743                 }
6744
6745                 ret = i915_gem_object_put_fence(obj);
6746                 if (ret) {
6747                         DRM_ERROR("failed to release fence for cursor");
6748                         goto fail_unpin;
6749                 }
6750
6751                 addr = i915_gem_obj_ggtt_offset(obj);
6752         } else {
6753                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6754                 ret = i915_gem_attach_phys_object(dev, obj,
6755                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6756                                                   align);
6757                 if (ret) {
6758                         DRM_ERROR("failed to attach phys object\n");
6759                         goto fail_locked;
6760                 }
6761                 addr = obj->phys_obj->handle->busaddr;
6762         }
6763
6764         if (IS_GEN2(dev))
6765                 I915_WRITE(CURSIZE, (height << 12) | width);
6766
6767  finish:
6768         if (intel_crtc->cursor_bo) {
6769                 if (dev_priv->info->cursor_needs_physical) {
6770                         if (intel_crtc->cursor_bo != obj)
6771                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6772                 } else
6773                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6774                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6775         }
6776
6777         mutex_unlock(&dev->struct_mutex);
6778
6779         intel_crtc->cursor_addr = addr;
6780         intel_crtc->cursor_bo = obj;
6781         intel_crtc->cursor_width = width;
6782         intel_crtc->cursor_height = height;
6783
6784         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6785
6786         return 0;
6787 fail_unpin:
6788         i915_gem_object_unpin(obj);
6789 fail_locked:
6790         mutex_unlock(&dev->struct_mutex);
6791 fail:
6792         drm_gem_object_unreference_unlocked(&obj->base);
6793         return ret;
6794 }
6795
6796 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6797 {
6798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6799
6800         intel_crtc->cursor_x = x;
6801         intel_crtc->cursor_y = y;
6802
6803         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6804
6805         return 0;
6806 }
6807
6808 /** Sets the color ramps on behalf of RandR */
6809 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6810                                  u16 blue, int regno)
6811 {
6812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6813
6814         intel_crtc->lut_r[regno] = red >> 8;
6815         intel_crtc->lut_g[regno] = green >> 8;
6816         intel_crtc->lut_b[regno] = blue >> 8;
6817 }
6818
6819 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6820                              u16 *blue, int regno)
6821 {
6822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6823
6824         *red = intel_crtc->lut_r[regno] << 8;
6825         *green = intel_crtc->lut_g[regno] << 8;
6826         *blue = intel_crtc->lut_b[regno] << 8;
6827 }
6828
6829 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6830                                  u16 *blue, uint32_t start, uint32_t size)
6831 {
6832         int end = (start + size > 256) ? 256 : start + size, i;
6833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6834
6835         for (i = start; i < end; i++) {
6836                 intel_crtc->lut_r[i] = red[i] >> 8;
6837                 intel_crtc->lut_g[i] = green[i] >> 8;
6838                 intel_crtc->lut_b[i] = blue[i] >> 8;
6839         }
6840
6841         intel_crtc_load_lut(crtc);
6842 }
6843
6844 /* VESA 640x480x72Hz mode to set on the pipe */
6845 static struct drm_display_mode load_detect_mode = {
6846         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6847                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6848 };
6849
6850 static struct drm_framebuffer *
6851 intel_framebuffer_create(struct drm_device *dev,
6852                          struct drm_mode_fb_cmd2 *mode_cmd,
6853                          struct drm_i915_gem_object *obj)
6854 {
6855         struct intel_framebuffer *intel_fb;
6856         int ret;
6857
6858         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6859         if (!intel_fb) {
6860                 drm_gem_object_unreference_unlocked(&obj->base);
6861                 return ERR_PTR(-ENOMEM);
6862         }
6863
6864         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6865         if (ret) {
6866                 drm_gem_object_unreference_unlocked(&obj->base);
6867                 kfree(intel_fb);
6868                 return ERR_PTR(ret);
6869         }
6870
6871         return &intel_fb->base;
6872 }
6873
6874 static u32
6875 intel_framebuffer_pitch_for_width(int width, int bpp)
6876 {
6877         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6878         return ALIGN(pitch, 64);
6879 }
6880
6881 static u32
6882 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6883 {
6884         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6885         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6886 }
6887
6888 static struct drm_framebuffer *
6889 intel_framebuffer_create_for_mode(struct drm_device *dev,
6890                                   struct drm_display_mode *mode,
6891                                   int depth, int bpp)
6892 {
6893         struct drm_i915_gem_object *obj;
6894         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6895
6896         obj = i915_gem_alloc_object(dev,
6897                                     intel_framebuffer_size_for_mode(mode, bpp));
6898         if (obj == NULL)
6899                 return ERR_PTR(-ENOMEM);
6900
6901         mode_cmd.width = mode->hdisplay;
6902         mode_cmd.height = mode->vdisplay;
6903         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6904                                                                 bpp);
6905         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6906
6907         return intel_framebuffer_create(dev, &mode_cmd, obj);
6908 }
6909
6910 static struct drm_framebuffer *
6911 mode_fits_in_fbdev(struct drm_device *dev,
6912                    struct drm_display_mode *mode)
6913 {
6914         struct drm_i915_private *dev_priv = dev->dev_private;
6915         struct drm_i915_gem_object *obj;
6916         struct drm_framebuffer *fb;
6917
6918         if (dev_priv->fbdev == NULL)
6919                 return NULL;
6920
6921         obj = dev_priv->fbdev->ifb.obj;
6922         if (obj == NULL)
6923                 return NULL;
6924
6925         fb = &dev_priv->fbdev->ifb.base;
6926         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6927                                                                fb->bits_per_pixel))
6928                 return NULL;
6929
6930         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6931                 return NULL;
6932
6933         return fb;
6934 }
6935
6936 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6937                                 struct drm_display_mode *mode,
6938                                 struct intel_load_detect_pipe *old)
6939 {
6940         struct intel_crtc *intel_crtc;
6941         struct intel_encoder *intel_encoder =
6942                 intel_attached_encoder(connector);
6943         struct drm_crtc *possible_crtc;
6944         struct drm_encoder *encoder = &intel_encoder->base;
6945         struct drm_crtc *crtc = NULL;
6946         struct drm_device *dev = encoder->dev;
6947         struct drm_framebuffer *fb;
6948         int i = -1;
6949
6950         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6951                       connector->base.id, drm_get_connector_name(connector),
6952                       encoder->base.id, drm_get_encoder_name(encoder));
6953
6954         /*
6955          * Algorithm gets a little messy:
6956          *
6957          *   - if the connector already has an assigned crtc, use it (but make
6958          *     sure it's on first)
6959          *
6960          *   - try to find the first unused crtc that can drive this connector,
6961          *     and use that if we find one
6962          */
6963
6964         /* See if we already have a CRTC for this connector */
6965         if (encoder->crtc) {
6966                 crtc = encoder->crtc;
6967
6968                 mutex_lock(&crtc->mutex);
6969
6970                 old->dpms_mode = connector->dpms;
6971                 old->load_detect_temp = false;
6972
6973                 /* Make sure the crtc and connector are running */
6974                 if (connector->dpms != DRM_MODE_DPMS_ON)
6975                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6976
6977                 return true;
6978         }
6979
6980         /* Find an unused one (if possible) */
6981         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6982                 i++;
6983                 if (!(encoder->possible_crtcs & (1 << i)))
6984                         continue;
6985                 if (!possible_crtc->enabled) {
6986                         crtc = possible_crtc;
6987                         break;
6988                 }
6989         }
6990
6991         /*
6992          * If we didn't find an unused CRTC, don't use any.
6993          */
6994         if (!crtc) {
6995                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6996                 return false;
6997         }
6998
6999         mutex_lock(&crtc->mutex);
7000         intel_encoder->new_crtc = to_intel_crtc(crtc);
7001         to_intel_connector(connector)->new_encoder = intel_encoder;
7002
7003         intel_crtc = to_intel_crtc(crtc);
7004         old->dpms_mode = connector->dpms;
7005         old->load_detect_temp = true;
7006         old->release_fb = NULL;
7007
7008         if (!mode)
7009                 mode = &load_detect_mode;
7010
7011         /* We need a framebuffer large enough to accommodate all accesses
7012          * that the plane may generate whilst we perform load detection.
7013          * We can not rely on the fbcon either being present (we get called
7014          * during its initialisation to detect all boot displays, or it may
7015          * not even exist) or that it is large enough to satisfy the
7016          * requested mode.
7017          */
7018         fb = mode_fits_in_fbdev(dev, mode);
7019         if (fb == NULL) {
7020                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7021                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7022                 old->release_fb = fb;
7023         } else
7024                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7025         if (IS_ERR(fb)) {
7026                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7027                 mutex_unlock(&crtc->mutex);
7028                 return false;
7029         }
7030
7031         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7032                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7033                 if (old->release_fb)
7034                         old->release_fb->funcs->destroy(old->release_fb);
7035                 mutex_unlock(&crtc->mutex);
7036                 return false;
7037         }
7038
7039         /* let the connector get through one full cycle before testing */
7040         intel_wait_for_vblank(dev, intel_crtc->pipe);
7041         return true;
7042 }
7043
7044 void intel_release_load_detect_pipe(struct drm_connector *connector,
7045                                     struct intel_load_detect_pipe *old)
7046 {
7047         struct intel_encoder *intel_encoder =
7048                 intel_attached_encoder(connector);
7049         struct drm_encoder *encoder = &intel_encoder->base;
7050         struct drm_crtc *crtc = encoder->crtc;
7051
7052         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7053                       connector->base.id, drm_get_connector_name(connector),
7054                       encoder->base.id, drm_get_encoder_name(encoder));
7055
7056         if (old->load_detect_temp) {
7057                 to_intel_connector(connector)->new_encoder = NULL;
7058                 intel_encoder->new_crtc = NULL;
7059                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7060
7061                 if (old->release_fb) {
7062                         drm_framebuffer_unregister_private(old->release_fb);
7063                         drm_framebuffer_unreference(old->release_fb);
7064                 }
7065
7066                 mutex_unlock(&crtc->mutex);
7067                 return;
7068         }
7069
7070         /* Switch crtc and encoder back off if necessary */
7071         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7072                 connector->funcs->dpms(connector, old->dpms_mode);
7073
7074         mutex_unlock(&crtc->mutex);
7075 }
7076
7077 /* Returns the clock of the currently programmed mode of the given pipe. */
7078 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7079                                 struct intel_crtc_config *pipe_config)
7080 {
7081         struct drm_device *dev = crtc->base.dev;
7082         struct drm_i915_private *dev_priv = dev->dev_private;
7083         int pipe = pipe_config->cpu_transcoder;
7084         u32 dpll = I915_READ(DPLL(pipe));
7085         u32 fp;
7086         intel_clock_t clock;
7087
7088         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7089                 fp = I915_READ(FP0(pipe));
7090         else
7091                 fp = I915_READ(FP1(pipe));
7092
7093         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7094         if (IS_PINEVIEW(dev)) {
7095                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7096                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7097         } else {
7098                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7099                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7100         }
7101
7102         if (!IS_GEN2(dev)) {
7103                 if (IS_PINEVIEW(dev))
7104                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7105                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7106                 else
7107                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7108                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7109
7110                 switch (dpll & DPLL_MODE_MASK) {
7111                 case DPLLB_MODE_DAC_SERIAL:
7112                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7113                                 5 : 10;
7114                         break;
7115                 case DPLLB_MODE_LVDS:
7116                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7117                                 7 : 14;
7118                         break;
7119                 default:
7120                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7121                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7122                         pipe_config->adjusted_mode.clock = 0;
7123                         return;
7124                 }
7125
7126                 if (IS_PINEVIEW(dev))
7127                         pineview_clock(96000, &clock);
7128                 else
7129                         i9xx_clock(96000, &clock);
7130         } else {
7131                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7132
7133                 if (is_lvds) {
7134                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7135                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7136                         clock.p2 = 14;
7137
7138                         if ((dpll & PLL_REF_INPUT_MASK) ==
7139                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7140                                 /* XXX: might not be 66MHz */
7141                                 i9xx_clock(66000, &clock);
7142                         } else
7143                                 i9xx_clock(48000, &clock);
7144                 } else {
7145                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7146                                 clock.p1 = 2;
7147                         else {
7148                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7149                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7150                         }
7151                         if (dpll & PLL_P2_DIVIDE_BY_4)
7152                                 clock.p2 = 4;
7153                         else
7154                                 clock.p2 = 2;
7155
7156                         i9xx_clock(48000, &clock);
7157                 }
7158         }
7159
7160         pipe_config->adjusted_mode.clock = clock.dot *
7161                 pipe_config->pixel_multiplier;
7162 }
7163
7164 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7165                                     struct intel_crtc_config *pipe_config)
7166 {
7167         struct drm_device *dev = crtc->base.dev;
7168         struct drm_i915_private *dev_priv = dev->dev_private;
7169         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7170         int link_freq, repeat;
7171         u64 clock;
7172         u32 link_m, link_n;
7173
7174         repeat = pipe_config->pixel_multiplier;
7175
7176         /*
7177          * The calculation for the data clock is:
7178          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7179          * But we want to avoid losing precison if possible, so:
7180          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7181          *
7182          * and the link clock is simpler:
7183          * link_clock = (m * link_clock * repeat) / n
7184          */
7185
7186         /*
7187          * We need to get the FDI or DP link clock here to derive
7188          * the M/N dividers.
7189          *
7190          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7191          * For DP, it's either 1.62GHz or 2.7GHz.
7192          * We do our calculations in 10*MHz since we don't need much precison.
7193          */
7194         if (pipe_config->has_pch_encoder)
7195                 link_freq = intel_fdi_link_freq(dev) * 10000;
7196         else
7197                 link_freq = pipe_config->port_clock;
7198
7199         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7200         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7201
7202         if (!link_m || !link_n)
7203                 return;
7204
7205         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7206         do_div(clock, link_n);
7207
7208         pipe_config->adjusted_mode.clock = clock;
7209 }
7210
7211 /** Returns the currently programmed mode of the given pipe. */
7212 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7213                                              struct drm_crtc *crtc)
7214 {
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7218         struct drm_display_mode *mode;
7219         struct intel_crtc_config pipe_config;
7220         int htot = I915_READ(HTOTAL(cpu_transcoder));
7221         int hsync = I915_READ(HSYNC(cpu_transcoder));
7222         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7223         int vsync = I915_READ(VSYNC(cpu_transcoder));
7224
7225         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7226         if (!mode)
7227                 return NULL;
7228
7229         /*
7230          * Construct a pipe_config sufficient for getting the clock info
7231          * back out of crtc_clock_get.
7232          *
7233          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7234          * to use a real value here instead.
7235          */
7236         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7237         pipe_config.pixel_multiplier = 1;
7238         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7239
7240         mode->clock = pipe_config.adjusted_mode.clock;
7241         mode->hdisplay = (htot & 0xffff) + 1;
7242         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7243         mode->hsync_start = (hsync & 0xffff) + 1;
7244         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7245         mode->vdisplay = (vtot & 0xffff) + 1;
7246         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7247         mode->vsync_start = (vsync & 0xffff) + 1;
7248         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7249
7250         drm_mode_set_name(mode);
7251
7252         return mode;
7253 }
7254
7255 static void intel_increase_pllclock(struct drm_crtc *crtc)
7256 {
7257         struct drm_device *dev = crtc->dev;
7258         drm_i915_private_t *dev_priv = dev->dev_private;
7259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7260         int pipe = intel_crtc->pipe;
7261         int dpll_reg = DPLL(pipe);
7262         int dpll;
7263
7264         if (HAS_PCH_SPLIT(dev))
7265                 return;
7266
7267         if (!dev_priv->lvds_downclock_avail)
7268                 return;
7269
7270         dpll = I915_READ(dpll_reg);
7271         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7272                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7273
7274                 assert_panel_unlocked(dev_priv, pipe);
7275
7276                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7277                 I915_WRITE(dpll_reg, dpll);
7278                 intel_wait_for_vblank(dev, pipe);
7279
7280                 dpll = I915_READ(dpll_reg);
7281                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7282                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7283         }
7284 }
7285
7286 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7287 {
7288         struct drm_device *dev = crtc->dev;
7289         drm_i915_private_t *dev_priv = dev->dev_private;
7290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291
7292         if (HAS_PCH_SPLIT(dev))
7293                 return;
7294
7295         if (!dev_priv->lvds_downclock_avail)
7296                 return;
7297
7298         /*
7299          * Since this is called by a timer, we should never get here in
7300          * the manual case.
7301          */
7302         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7303                 int pipe = intel_crtc->pipe;
7304                 int dpll_reg = DPLL(pipe);
7305                 int dpll;
7306
7307                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7308
7309                 assert_panel_unlocked(dev_priv, pipe);
7310
7311                 dpll = I915_READ(dpll_reg);
7312                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7313                 I915_WRITE(dpll_reg, dpll);
7314                 intel_wait_for_vblank(dev, pipe);
7315                 dpll = I915_READ(dpll_reg);
7316                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7317                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7318         }
7319
7320 }
7321
7322 void intel_mark_busy(struct drm_device *dev)
7323 {
7324         i915_update_gfx_val(dev->dev_private);
7325 }
7326
7327 void intel_mark_idle(struct drm_device *dev)
7328 {
7329         struct drm_crtc *crtc;
7330
7331         if (!i915_powersave)
7332                 return;
7333
7334         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7335                 if (!crtc->fb)
7336                         continue;
7337
7338                 intel_decrease_pllclock(crtc);
7339         }
7340 }
7341
7342 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7343                         struct intel_ring_buffer *ring)
7344 {
7345         struct drm_device *dev = obj->base.dev;
7346         struct drm_crtc *crtc;
7347
7348         if (!i915_powersave)
7349                 return;
7350
7351         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7352                 if (!crtc->fb)
7353                         continue;
7354
7355                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7356                         continue;
7357
7358                 intel_increase_pllclock(crtc);
7359                 if (ring && intel_fbc_enabled(dev))
7360                         ring->fbc_dirty = true;
7361         }
7362 }
7363
7364 static void intel_crtc_destroy(struct drm_crtc *crtc)
7365 {
7366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7367         struct drm_device *dev = crtc->dev;
7368         struct intel_unpin_work *work;
7369         unsigned long flags;
7370
7371         spin_lock_irqsave(&dev->event_lock, flags);
7372         work = intel_crtc->unpin_work;
7373         intel_crtc->unpin_work = NULL;
7374         spin_unlock_irqrestore(&dev->event_lock, flags);
7375
7376         if (work) {
7377                 cancel_work_sync(&work->work);
7378                 kfree(work);
7379         }
7380
7381         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7382
7383         drm_crtc_cleanup(crtc);
7384
7385         kfree(intel_crtc);
7386 }
7387
7388 static void intel_unpin_work_fn(struct work_struct *__work)
7389 {
7390         struct intel_unpin_work *work =
7391                 container_of(__work, struct intel_unpin_work, work);
7392         struct drm_device *dev = work->crtc->dev;
7393
7394         mutex_lock(&dev->struct_mutex);
7395         intel_unpin_fb_obj(work->old_fb_obj);
7396         drm_gem_object_unreference(&work->pending_flip_obj->base);
7397         drm_gem_object_unreference(&work->old_fb_obj->base);
7398
7399         intel_update_fbc(dev);
7400         mutex_unlock(&dev->struct_mutex);
7401
7402         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7403         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7404
7405         kfree(work);
7406 }
7407
7408 static void do_intel_finish_page_flip(struct drm_device *dev,
7409                                       struct drm_crtc *crtc)
7410 {
7411         drm_i915_private_t *dev_priv = dev->dev_private;
7412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413         struct intel_unpin_work *work;
7414         unsigned long flags;
7415
7416         /* Ignore early vblank irqs */
7417         if (intel_crtc == NULL)
7418                 return;
7419
7420         spin_lock_irqsave(&dev->event_lock, flags);
7421         work = intel_crtc->unpin_work;
7422
7423         /* Ensure we don't miss a work->pending update ... */
7424         smp_rmb();
7425
7426         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7427                 spin_unlock_irqrestore(&dev->event_lock, flags);
7428                 return;
7429         }
7430
7431         /* and that the unpin work is consistent wrt ->pending. */
7432         smp_rmb();
7433
7434         intel_crtc->unpin_work = NULL;
7435
7436         if (work->event)
7437                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7438
7439         drm_vblank_put(dev, intel_crtc->pipe);
7440
7441         spin_unlock_irqrestore(&dev->event_lock, flags);
7442
7443         wake_up_all(&dev_priv->pending_flip_queue);
7444
7445         queue_work(dev_priv->wq, &work->work);
7446
7447         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7448 }
7449
7450 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7451 {
7452         drm_i915_private_t *dev_priv = dev->dev_private;
7453         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7454
7455         do_intel_finish_page_flip(dev, crtc);
7456 }
7457
7458 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7459 {
7460         drm_i915_private_t *dev_priv = dev->dev_private;
7461         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7462
7463         do_intel_finish_page_flip(dev, crtc);
7464 }
7465
7466 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7467 {
7468         drm_i915_private_t *dev_priv = dev->dev_private;
7469         struct intel_crtc *intel_crtc =
7470                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7471         unsigned long flags;
7472
7473         /* NB: An MMIO update of the plane base pointer will also
7474          * generate a page-flip completion irq, i.e. every modeset
7475          * is also accompanied by a spurious intel_prepare_page_flip().
7476          */
7477         spin_lock_irqsave(&dev->event_lock, flags);
7478         if (intel_crtc->unpin_work)
7479                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7480         spin_unlock_irqrestore(&dev->event_lock, flags);
7481 }
7482
7483 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7484 {
7485         /* Ensure that the work item is consistent when activating it ... */
7486         smp_wmb();
7487         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7488         /* and that it is marked active as soon as the irq could fire. */
7489         smp_wmb();
7490 }
7491
7492 static int intel_gen2_queue_flip(struct drm_device *dev,
7493                                  struct drm_crtc *crtc,
7494                                  struct drm_framebuffer *fb,
7495                                  struct drm_i915_gem_object *obj)
7496 {
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7499         u32 flip_mask;
7500         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7501         int ret;
7502
7503         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7504         if (ret)
7505                 goto err;
7506
7507         ret = intel_ring_begin(ring, 6);
7508         if (ret)
7509                 goto err_unpin;
7510
7511         /* Can't queue multiple flips, so wait for the previous
7512          * one to finish before executing the next.
7513          */
7514         if (intel_crtc->plane)
7515                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7516         else
7517                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7518         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7519         intel_ring_emit(ring, MI_NOOP);
7520         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7521                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7522         intel_ring_emit(ring, fb->pitches[0]);
7523         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7524         intel_ring_emit(ring, 0); /* aux display base address, unused */
7525
7526         intel_mark_page_flip_active(intel_crtc);
7527         intel_ring_advance(ring);
7528         return 0;
7529
7530 err_unpin:
7531         intel_unpin_fb_obj(obj);
7532 err:
7533         return ret;
7534 }
7535
7536 static int intel_gen3_queue_flip(struct drm_device *dev,
7537                                  struct drm_crtc *crtc,
7538                                  struct drm_framebuffer *fb,
7539                                  struct drm_i915_gem_object *obj)
7540 {
7541         struct drm_i915_private *dev_priv = dev->dev_private;
7542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7543         u32 flip_mask;
7544         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7545         int ret;
7546
7547         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7548         if (ret)
7549                 goto err;
7550
7551         ret = intel_ring_begin(ring, 6);
7552         if (ret)
7553                 goto err_unpin;
7554
7555         if (intel_crtc->plane)
7556                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7557         else
7558                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7559         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7560         intel_ring_emit(ring, MI_NOOP);
7561         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7562                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7563         intel_ring_emit(ring, fb->pitches[0]);
7564         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7565         intel_ring_emit(ring, MI_NOOP);
7566
7567         intel_mark_page_flip_active(intel_crtc);
7568         intel_ring_advance(ring);
7569         return 0;
7570
7571 err_unpin:
7572         intel_unpin_fb_obj(obj);
7573 err:
7574         return ret;
7575 }
7576
7577 static int intel_gen4_queue_flip(struct drm_device *dev,
7578                                  struct drm_crtc *crtc,
7579                                  struct drm_framebuffer *fb,
7580                                  struct drm_i915_gem_object *obj)
7581 {
7582         struct drm_i915_private *dev_priv = dev->dev_private;
7583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7584         uint32_t pf, pipesrc;
7585         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7586         int ret;
7587
7588         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7589         if (ret)
7590                 goto err;
7591
7592         ret = intel_ring_begin(ring, 4);
7593         if (ret)
7594                 goto err_unpin;
7595
7596         /* i965+ uses the linear or tiled offsets from the
7597          * Display Registers (which do not change across a page-flip)
7598          * so we need only reprogram the base address.
7599          */
7600         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7601                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7602         intel_ring_emit(ring, fb->pitches[0]);
7603         intel_ring_emit(ring,
7604                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7605                         obj->tiling_mode);
7606
7607         /* XXX Enabling the panel-fitter across page-flip is so far
7608          * untested on non-native modes, so ignore it for now.
7609          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7610          */
7611         pf = 0;
7612         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7613         intel_ring_emit(ring, pf | pipesrc);
7614
7615         intel_mark_page_flip_active(intel_crtc);
7616         intel_ring_advance(ring);
7617         return 0;
7618
7619 err_unpin:
7620         intel_unpin_fb_obj(obj);
7621 err:
7622         return ret;
7623 }
7624
7625 static int intel_gen6_queue_flip(struct drm_device *dev,
7626                                  struct drm_crtc *crtc,
7627                                  struct drm_framebuffer *fb,
7628                                  struct drm_i915_gem_object *obj)
7629 {
7630         struct drm_i915_private *dev_priv = dev->dev_private;
7631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7632         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7633         uint32_t pf, pipesrc;
7634         int ret;
7635
7636         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7637         if (ret)
7638                 goto err;
7639
7640         ret = intel_ring_begin(ring, 4);
7641         if (ret)
7642                 goto err_unpin;
7643
7644         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7645                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7646         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7647         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7648
7649         /* Contrary to the suggestions in the documentation,
7650          * "Enable Panel Fitter" does not seem to be required when page
7651          * flipping with a non-native mode, and worse causes a normal
7652          * modeset to fail.
7653          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7654          */
7655         pf = 0;
7656         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7657         intel_ring_emit(ring, pf | pipesrc);
7658
7659         intel_mark_page_flip_active(intel_crtc);
7660         intel_ring_advance(ring);
7661         return 0;
7662
7663 err_unpin:
7664         intel_unpin_fb_obj(obj);
7665 err:
7666         return ret;
7667 }
7668
7669 /*
7670  * On gen7 we currently use the blit ring because (in early silicon at least)
7671  * the render ring doesn't give us interrpts for page flip completion, which
7672  * means clients will hang after the first flip is queued.  Fortunately the
7673  * blit ring generates interrupts properly, so use it instead.
7674  */
7675 static int intel_gen7_queue_flip(struct drm_device *dev,
7676                                  struct drm_crtc *crtc,
7677                                  struct drm_framebuffer *fb,
7678                                  struct drm_i915_gem_object *obj)
7679 {
7680         struct drm_i915_private *dev_priv = dev->dev_private;
7681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7682         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7683         uint32_t plane_bit = 0;
7684         int ret;
7685
7686         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7687         if (ret)
7688                 goto err;
7689
7690         switch(intel_crtc->plane) {
7691         case PLANE_A:
7692                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7693                 break;
7694         case PLANE_B:
7695                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7696                 break;
7697         case PLANE_C:
7698                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7699                 break;
7700         default:
7701                 WARN_ONCE(1, "unknown plane in flip command\n");
7702                 ret = -ENODEV;
7703                 goto err_unpin;
7704         }
7705
7706         ret = intel_ring_begin(ring, 4);
7707         if (ret)
7708                 goto err_unpin;
7709
7710         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7711         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7712         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7713         intel_ring_emit(ring, (MI_NOOP));
7714
7715         intel_mark_page_flip_active(intel_crtc);
7716         intel_ring_advance(ring);
7717         return 0;
7718
7719 err_unpin:
7720         intel_unpin_fb_obj(obj);
7721 err:
7722         return ret;
7723 }
7724
7725 static int intel_default_queue_flip(struct drm_device *dev,
7726                                     struct drm_crtc *crtc,
7727                                     struct drm_framebuffer *fb,
7728                                     struct drm_i915_gem_object *obj)
7729 {
7730         return -ENODEV;
7731 }
7732
7733 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7734                                 struct drm_framebuffer *fb,
7735                                 struct drm_pending_vblank_event *event)
7736 {
7737         struct drm_device *dev = crtc->dev;
7738         struct drm_i915_private *dev_priv = dev->dev_private;
7739         struct drm_framebuffer *old_fb = crtc->fb;
7740         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7742         struct intel_unpin_work *work;
7743         unsigned long flags;
7744         int ret;
7745
7746         /* Can't change pixel format via MI display flips. */
7747         if (fb->pixel_format != crtc->fb->pixel_format)
7748                 return -EINVAL;
7749
7750         /*
7751          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7752          * Note that pitch changes could also affect these register.
7753          */
7754         if (INTEL_INFO(dev)->gen > 3 &&
7755             (fb->offsets[0] != crtc->fb->offsets[0] ||
7756              fb->pitches[0] != crtc->fb->pitches[0]))
7757                 return -EINVAL;
7758
7759         work = kzalloc(sizeof *work, GFP_KERNEL);
7760         if (work == NULL)
7761                 return -ENOMEM;
7762
7763         work->event = event;
7764         work->crtc = crtc;
7765         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7766         INIT_WORK(&work->work, intel_unpin_work_fn);
7767
7768         ret = drm_vblank_get(dev, intel_crtc->pipe);
7769         if (ret)
7770                 goto free_work;
7771
7772         /* We borrow the event spin lock for protecting unpin_work */
7773         spin_lock_irqsave(&dev->event_lock, flags);
7774         if (intel_crtc->unpin_work) {
7775                 spin_unlock_irqrestore(&dev->event_lock, flags);
7776                 kfree(work);
7777                 drm_vblank_put(dev, intel_crtc->pipe);
7778
7779                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7780                 return -EBUSY;
7781         }
7782         intel_crtc->unpin_work = work;
7783         spin_unlock_irqrestore(&dev->event_lock, flags);
7784
7785         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7786                 flush_workqueue(dev_priv->wq);
7787
7788         ret = i915_mutex_lock_interruptible(dev);
7789         if (ret)
7790                 goto cleanup;
7791
7792         /* Reference the objects for the scheduled work. */
7793         drm_gem_object_reference(&work->old_fb_obj->base);
7794         drm_gem_object_reference(&obj->base);
7795
7796         crtc->fb = fb;
7797
7798         work->pending_flip_obj = obj;
7799
7800         work->enable_stall_check = true;
7801
7802         atomic_inc(&intel_crtc->unpin_work_count);
7803         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7804
7805         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7806         if (ret)
7807                 goto cleanup_pending;
7808
7809         intel_disable_fbc(dev);
7810         intel_mark_fb_busy(obj, NULL);
7811         mutex_unlock(&dev->struct_mutex);
7812
7813         trace_i915_flip_request(intel_crtc->plane, obj);
7814
7815         return 0;
7816
7817 cleanup_pending:
7818         atomic_dec(&intel_crtc->unpin_work_count);
7819         crtc->fb = old_fb;
7820         drm_gem_object_unreference(&work->old_fb_obj->base);
7821         drm_gem_object_unreference(&obj->base);
7822         mutex_unlock(&dev->struct_mutex);
7823
7824 cleanup:
7825         spin_lock_irqsave(&dev->event_lock, flags);
7826         intel_crtc->unpin_work = NULL;
7827         spin_unlock_irqrestore(&dev->event_lock, flags);
7828
7829         drm_vblank_put(dev, intel_crtc->pipe);
7830 free_work:
7831         kfree(work);
7832
7833         return ret;
7834 }
7835
7836 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7837         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7838         .load_lut = intel_crtc_load_lut,
7839 };
7840
7841 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7842                                   struct drm_crtc *crtc)
7843 {
7844         struct drm_device *dev;
7845         struct drm_crtc *tmp;
7846         int crtc_mask = 1;
7847
7848         WARN(!crtc, "checking null crtc?\n");
7849
7850         dev = crtc->dev;
7851
7852         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7853                 if (tmp == crtc)
7854                         break;
7855                 crtc_mask <<= 1;
7856         }
7857
7858         if (encoder->possible_crtcs & crtc_mask)
7859                 return true;
7860         return false;
7861 }
7862
7863 /**
7864  * intel_modeset_update_staged_output_state
7865  *
7866  * Updates the staged output configuration state, e.g. after we've read out the
7867  * current hw state.
7868  */
7869 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7870 {
7871         struct intel_encoder *encoder;
7872         struct intel_connector *connector;
7873
7874         list_for_each_entry(connector, &dev->mode_config.connector_list,
7875                             base.head) {
7876                 connector->new_encoder =
7877                         to_intel_encoder(connector->base.encoder);
7878         }
7879
7880         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7881                             base.head) {
7882                 encoder->new_crtc =
7883                         to_intel_crtc(encoder->base.crtc);
7884         }
7885 }
7886
7887 /**
7888  * intel_modeset_commit_output_state
7889  *
7890  * This function copies the stage display pipe configuration to the real one.
7891  */
7892 static void intel_modeset_commit_output_state(struct drm_device *dev)
7893 {
7894         struct intel_encoder *encoder;
7895         struct intel_connector *connector;
7896
7897         list_for_each_entry(connector, &dev->mode_config.connector_list,
7898                             base.head) {
7899                 connector->base.encoder = &connector->new_encoder->base;
7900         }
7901
7902         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7903                             base.head) {
7904                 encoder->base.crtc = &encoder->new_crtc->base;
7905         }
7906 }
7907
7908 static void
7909 connected_sink_compute_bpp(struct intel_connector * connector,
7910                            struct intel_crtc_config *pipe_config)
7911 {
7912         int bpp = pipe_config->pipe_bpp;
7913
7914         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7915                 connector->base.base.id,
7916                 drm_get_connector_name(&connector->base));
7917
7918         /* Don't use an invalid EDID bpc value */
7919         if (connector->base.display_info.bpc &&
7920             connector->base.display_info.bpc * 3 < bpp) {
7921                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7922                               bpp, connector->base.display_info.bpc*3);
7923                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7924         }
7925
7926         /* Clamp bpp to 8 on screens without EDID 1.4 */
7927         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7928                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7929                               bpp);
7930                 pipe_config->pipe_bpp = 24;
7931         }
7932 }
7933
7934 static int
7935 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7936                           struct drm_framebuffer *fb,
7937                           struct intel_crtc_config *pipe_config)
7938 {
7939         struct drm_device *dev = crtc->base.dev;
7940         struct intel_connector *connector;
7941         int bpp;
7942
7943         switch (fb->pixel_format) {
7944         case DRM_FORMAT_C8:
7945                 bpp = 8*3; /* since we go through a colormap */
7946                 break;
7947         case DRM_FORMAT_XRGB1555:
7948         case DRM_FORMAT_ARGB1555:
7949                 /* checked in intel_framebuffer_init already */
7950                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7951                         return -EINVAL;
7952         case DRM_FORMAT_RGB565:
7953                 bpp = 6*3; /* min is 18bpp */
7954                 break;
7955         case DRM_FORMAT_XBGR8888:
7956         case DRM_FORMAT_ABGR8888:
7957                 /* checked in intel_framebuffer_init already */
7958                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7959                         return -EINVAL;
7960         case DRM_FORMAT_XRGB8888:
7961         case DRM_FORMAT_ARGB8888:
7962                 bpp = 8*3;
7963                 break;
7964         case DRM_FORMAT_XRGB2101010:
7965         case DRM_FORMAT_ARGB2101010:
7966         case DRM_FORMAT_XBGR2101010:
7967         case DRM_FORMAT_ABGR2101010:
7968                 /* checked in intel_framebuffer_init already */
7969                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7970                         return -EINVAL;
7971                 bpp = 10*3;
7972                 break;
7973         /* TODO: gen4+ supports 16 bpc floating point, too. */
7974         default:
7975                 DRM_DEBUG_KMS("unsupported depth\n");
7976                 return -EINVAL;
7977         }
7978
7979         pipe_config->pipe_bpp = bpp;
7980
7981         /* Clamp display bpp to EDID value */
7982         list_for_each_entry(connector, &dev->mode_config.connector_list,
7983                             base.head) {
7984                 if (!connector->new_encoder ||
7985                     connector->new_encoder->new_crtc != crtc)
7986                         continue;
7987
7988                 connected_sink_compute_bpp(connector, pipe_config);
7989         }
7990
7991         return bpp;
7992 }
7993
7994 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7995                                    struct intel_crtc_config *pipe_config,
7996                                    const char *context)
7997 {
7998         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7999                       context, pipe_name(crtc->pipe));
8000
8001         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8002         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8003                       pipe_config->pipe_bpp, pipe_config->dither);
8004         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8005                       pipe_config->has_pch_encoder,
8006                       pipe_config->fdi_lanes,
8007                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8008                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8009                       pipe_config->fdi_m_n.tu);
8010         DRM_DEBUG_KMS("requested mode:\n");
8011         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8012         DRM_DEBUG_KMS("adjusted mode:\n");
8013         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8014         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8015                       pipe_config->gmch_pfit.control,
8016                       pipe_config->gmch_pfit.pgm_ratios,
8017                       pipe_config->gmch_pfit.lvds_border_bits);
8018         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8019                       pipe_config->pch_pfit.pos,
8020                       pipe_config->pch_pfit.size);
8021         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8022 }
8023
8024 static bool check_encoder_cloning(struct drm_crtc *crtc)
8025 {
8026         int num_encoders = 0;
8027         bool uncloneable_encoders = false;
8028         struct intel_encoder *encoder;
8029
8030         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8031                             base.head) {
8032                 if (&encoder->new_crtc->base != crtc)
8033                         continue;
8034
8035                 num_encoders++;
8036                 if (!encoder->cloneable)
8037                         uncloneable_encoders = true;
8038         }
8039
8040         return !(num_encoders > 1 && uncloneable_encoders);
8041 }
8042
8043 static struct intel_crtc_config *
8044 intel_modeset_pipe_config(struct drm_crtc *crtc,
8045                           struct drm_framebuffer *fb,
8046                           struct drm_display_mode *mode)
8047 {
8048         struct drm_device *dev = crtc->dev;
8049         struct intel_encoder *encoder;
8050         struct intel_crtc_config *pipe_config;
8051         int plane_bpp, ret = -EINVAL;
8052         bool retry = true;
8053
8054         if (!check_encoder_cloning(crtc)) {
8055                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8056                 return ERR_PTR(-EINVAL);
8057         }
8058
8059         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8060         if (!pipe_config)
8061                 return ERR_PTR(-ENOMEM);
8062
8063         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8064         drm_mode_copy(&pipe_config->requested_mode, mode);
8065         pipe_config->cpu_transcoder =
8066                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8067         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8068
8069         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8070          * plane pixel format and any sink constraints into account. Returns the
8071          * source plane bpp so that dithering can be selected on mismatches
8072          * after encoders and crtc also have had their say. */
8073         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8074                                               fb, pipe_config);
8075         if (plane_bpp < 0)
8076                 goto fail;
8077
8078 encoder_retry:
8079         /* Ensure the port clock defaults are reset when retrying. */
8080         pipe_config->port_clock = 0;
8081         pipe_config->pixel_multiplier = 1;
8082
8083         /* Fill in default crtc timings, allow encoders to overwrite them. */
8084         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8085
8086         /* Pass our mode to the connectors and the CRTC to give them a chance to
8087          * adjust it according to limitations or connector properties, and also
8088          * a chance to reject the mode entirely.
8089          */
8090         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8091                             base.head) {
8092
8093                 if (&encoder->new_crtc->base != crtc)
8094                         continue;
8095
8096                 if (!(encoder->compute_config(encoder, pipe_config))) {
8097                         DRM_DEBUG_KMS("Encoder config failure\n");
8098                         goto fail;
8099                 }
8100         }
8101
8102         /* Set default port clock if not overwritten by the encoder. Needs to be
8103          * done afterwards in case the encoder adjusts the mode. */
8104         if (!pipe_config->port_clock)
8105                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8106
8107         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8108         if (ret < 0) {
8109                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8110                 goto fail;
8111         }
8112
8113         if (ret == RETRY) {
8114                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8115                         ret = -EINVAL;
8116                         goto fail;
8117                 }
8118
8119                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8120                 retry = false;
8121                 goto encoder_retry;
8122         }
8123
8124         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8125         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8126                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8127
8128         return pipe_config;
8129 fail:
8130         kfree(pipe_config);
8131         return ERR_PTR(ret);
8132 }
8133
8134 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8135  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8136 static void
8137 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8138                              unsigned *prepare_pipes, unsigned *disable_pipes)
8139 {
8140         struct intel_crtc *intel_crtc;
8141         struct drm_device *dev = crtc->dev;
8142         struct intel_encoder *encoder;
8143         struct intel_connector *connector;
8144         struct drm_crtc *tmp_crtc;
8145
8146         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8147
8148         /* Check which crtcs have changed outputs connected to them, these need
8149          * to be part of the prepare_pipes mask. We don't (yet) support global
8150          * modeset across multiple crtcs, so modeset_pipes will only have one
8151          * bit set at most. */
8152         list_for_each_entry(connector, &dev->mode_config.connector_list,
8153                             base.head) {
8154                 if (connector->base.encoder == &connector->new_encoder->base)
8155                         continue;
8156
8157                 if (connector->base.encoder) {
8158                         tmp_crtc = connector->base.encoder->crtc;
8159
8160                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8161                 }
8162
8163                 if (connector->new_encoder)
8164                         *prepare_pipes |=
8165                                 1 << connector->new_encoder->new_crtc->pipe;
8166         }
8167
8168         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8169                             base.head) {
8170                 if (encoder->base.crtc == &encoder->new_crtc->base)
8171                         continue;
8172
8173                 if (encoder->base.crtc) {
8174                         tmp_crtc = encoder->base.crtc;
8175
8176                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8177                 }
8178
8179                 if (encoder->new_crtc)
8180                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8181         }
8182
8183         /* Check for any pipes that will be fully disabled ... */
8184         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8185                             base.head) {
8186                 bool used = false;
8187
8188                 /* Don't try to disable disabled crtcs. */
8189                 if (!intel_crtc->base.enabled)
8190                         continue;
8191
8192                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8193                                     base.head) {
8194                         if (encoder->new_crtc == intel_crtc)
8195                                 used = true;
8196                 }
8197
8198                 if (!used)
8199                         *disable_pipes |= 1 << intel_crtc->pipe;
8200         }
8201
8202
8203         /* set_mode is also used to update properties on life display pipes. */
8204         intel_crtc = to_intel_crtc(crtc);
8205         if (crtc->enabled)
8206                 *prepare_pipes |= 1 << intel_crtc->pipe;
8207
8208         /*
8209          * For simplicity do a full modeset on any pipe where the output routing
8210          * changed. We could be more clever, but that would require us to be
8211          * more careful with calling the relevant encoder->mode_set functions.
8212          */
8213         if (*prepare_pipes)
8214                 *modeset_pipes = *prepare_pipes;
8215
8216         /* ... and mask these out. */
8217         *modeset_pipes &= ~(*disable_pipes);
8218         *prepare_pipes &= ~(*disable_pipes);
8219
8220         /*
8221          * HACK: We don't (yet) fully support global modesets. intel_set_config
8222          * obies this rule, but the modeset restore mode of
8223          * intel_modeset_setup_hw_state does not.
8224          */
8225         *modeset_pipes &= 1 << intel_crtc->pipe;
8226         *prepare_pipes &= 1 << intel_crtc->pipe;
8227
8228         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8229                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8230 }
8231
8232 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8233 {
8234         struct drm_encoder *encoder;
8235         struct drm_device *dev = crtc->dev;
8236
8237         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8238                 if (encoder->crtc == crtc)
8239                         return true;
8240
8241         return false;
8242 }
8243
8244 static void
8245 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8246 {
8247         struct intel_encoder *intel_encoder;
8248         struct intel_crtc *intel_crtc;
8249         struct drm_connector *connector;
8250
8251         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8252                             base.head) {
8253                 if (!intel_encoder->base.crtc)
8254                         continue;
8255
8256                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8257
8258                 if (prepare_pipes & (1 << intel_crtc->pipe))
8259                         intel_encoder->connectors_active = false;
8260         }
8261
8262         intel_modeset_commit_output_state(dev);
8263
8264         /* Update computed state. */
8265         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8266                             base.head) {
8267                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8268         }
8269
8270         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8271                 if (!connector->encoder || !connector->encoder->crtc)
8272                         continue;
8273
8274                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8275
8276                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8277                         struct drm_property *dpms_property =
8278                                 dev->mode_config.dpms_property;
8279
8280                         connector->dpms = DRM_MODE_DPMS_ON;
8281                         drm_object_property_set_value(&connector->base,
8282                                                          dpms_property,
8283                                                          DRM_MODE_DPMS_ON);
8284
8285                         intel_encoder = to_intel_encoder(connector->encoder);
8286                         intel_encoder->connectors_active = true;
8287                 }
8288         }
8289
8290 }
8291
8292 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8293                                     struct intel_crtc_config *new)
8294 {
8295         int clock1, clock2, diff;
8296
8297         clock1 = cur->adjusted_mode.clock;
8298         clock2 = new->adjusted_mode.clock;
8299
8300         if (clock1 == clock2)
8301                 return true;
8302
8303         if (!clock1 || !clock2)
8304                 return false;
8305
8306         diff = abs(clock1 - clock2);
8307
8308         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8309                 return true;
8310
8311         return false;
8312 }
8313
8314 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8315         list_for_each_entry((intel_crtc), \
8316                             &(dev)->mode_config.crtc_list, \
8317                             base.head) \
8318                 if (mask & (1 <<(intel_crtc)->pipe))
8319
8320 static bool
8321 intel_pipe_config_compare(struct drm_device *dev,
8322                           struct intel_crtc_config *current_config,
8323                           struct intel_crtc_config *pipe_config)
8324 {
8325 #define PIPE_CONF_CHECK_X(name) \
8326         if (current_config->name != pipe_config->name) { \
8327                 DRM_ERROR("mismatch in " #name " " \
8328                           "(expected 0x%08x, found 0x%08x)\n", \
8329                           current_config->name, \
8330                           pipe_config->name); \
8331                 return false; \
8332         }
8333
8334 #define PIPE_CONF_CHECK_I(name) \
8335         if (current_config->name != pipe_config->name) { \
8336                 DRM_ERROR("mismatch in " #name " " \
8337                           "(expected %i, found %i)\n", \
8338                           current_config->name, \
8339                           pipe_config->name); \
8340                 return false; \
8341         }
8342
8343 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8344         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8345                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8346                           "(expected %i, found %i)\n", \
8347                           current_config->name & (mask), \
8348                           pipe_config->name & (mask)); \
8349                 return false; \
8350         }
8351
8352 #define PIPE_CONF_QUIRK(quirk)  \
8353         ((current_config->quirks | pipe_config->quirks) & (quirk))
8354
8355         PIPE_CONF_CHECK_I(cpu_transcoder);
8356
8357         PIPE_CONF_CHECK_I(has_pch_encoder);
8358         PIPE_CONF_CHECK_I(fdi_lanes);
8359         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8360         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8361         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8362         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8363         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8364
8365         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8366         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8367         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8368         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8369         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8370         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8371
8372         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8373         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8374         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8375         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8376         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8377         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8378
8379         PIPE_CONF_CHECK_I(pixel_multiplier);
8380
8381         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8382                               DRM_MODE_FLAG_INTERLACE);
8383
8384         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8385                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8386                                       DRM_MODE_FLAG_PHSYNC);
8387                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8388                                       DRM_MODE_FLAG_NHSYNC);
8389                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8390                                       DRM_MODE_FLAG_PVSYNC);
8391                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8392                                       DRM_MODE_FLAG_NVSYNC);
8393         }
8394
8395         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8396         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8397
8398         PIPE_CONF_CHECK_I(gmch_pfit.control);
8399         /* pfit ratios are autocomputed by the hw on gen4+ */
8400         if (INTEL_INFO(dev)->gen < 4)
8401                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8402         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8403         PIPE_CONF_CHECK_I(pch_pfit.pos);
8404         PIPE_CONF_CHECK_I(pch_pfit.size);
8405
8406         PIPE_CONF_CHECK_I(ips_enabled);
8407
8408         PIPE_CONF_CHECK_I(shared_dpll);
8409         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8410         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8411         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8412         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8413
8414 #undef PIPE_CONF_CHECK_X
8415 #undef PIPE_CONF_CHECK_I
8416 #undef PIPE_CONF_CHECK_FLAGS
8417 #undef PIPE_CONF_QUIRK
8418
8419         if (!IS_HASWELL(dev)) {
8420                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8421                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8422                                   current_config->adjusted_mode.clock,
8423                                   pipe_config->adjusted_mode.clock);
8424                         return false;
8425                 }
8426         }
8427
8428         return true;
8429 }
8430
8431 static void
8432 check_connector_state(struct drm_device *dev)
8433 {
8434         struct intel_connector *connector;
8435
8436         list_for_each_entry(connector, &dev->mode_config.connector_list,
8437                             base.head) {
8438                 /* This also checks the encoder/connector hw state with the
8439                  * ->get_hw_state callbacks. */
8440                 intel_connector_check_state(connector);
8441
8442                 WARN(&connector->new_encoder->base != connector->base.encoder,
8443                      "connector's staged encoder doesn't match current encoder\n");
8444         }
8445 }
8446
8447 static void
8448 check_encoder_state(struct drm_device *dev)
8449 {
8450         struct intel_encoder *encoder;
8451         struct intel_connector *connector;
8452
8453         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8454                             base.head) {
8455                 bool enabled = false;
8456                 bool active = false;
8457                 enum pipe pipe, tracked_pipe;
8458
8459                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8460                               encoder->base.base.id,
8461                               drm_get_encoder_name(&encoder->base));
8462
8463                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8464                      "encoder's stage crtc doesn't match current crtc\n");
8465                 WARN(encoder->connectors_active && !encoder->base.crtc,
8466                      "encoder's active_connectors set, but no crtc\n");
8467
8468                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8469                                     base.head) {
8470                         if (connector->base.encoder != &encoder->base)
8471                                 continue;
8472                         enabled = true;
8473                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8474                                 active = true;
8475                 }
8476                 WARN(!!encoder->base.crtc != enabled,
8477                      "encoder's enabled state mismatch "
8478                      "(expected %i, found %i)\n",
8479                      !!encoder->base.crtc, enabled);
8480                 WARN(active && !encoder->base.crtc,
8481                      "active encoder with no crtc\n");
8482
8483                 WARN(encoder->connectors_active != active,
8484                      "encoder's computed active state doesn't match tracked active state "
8485                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8486
8487                 active = encoder->get_hw_state(encoder, &pipe);
8488                 WARN(active != encoder->connectors_active,
8489                      "encoder's hw state doesn't match sw tracking "
8490                      "(expected %i, found %i)\n",
8491                      encoder->connectors_active, active);
8492
8493                 if (!encoder->base.crtc)
8494                         continue;
8495
8496                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8497                 WARN(active && pipe != tracked_pipe,
8498                      "active encoder's pipe doesn't match"
8499                      "(expected %i, found %i)\n",
8500                      tracked_pipe, pipe);
8501
8502         }
8503 }
8504
8505 static void
8506 check_crtc_state(struct drm_device *dev)
8507 {
8508         drm_i915_private_t *dev_priv = dev->dev_private;
8509         struct intel_crtc *crtc;
8510         struct intel_encoder *encoder;
8511         struct intel_crtc_config pipe_config;
8512
8513         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8514                             base.head) {
8515                 bool enabled = false;
8516                 bool active = false;
8517
8518                 memset(&pipe_config, 0, sizeof(pipe_config));
8519
8520                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8521                               crtc->base.base.id);
8522
8523                 WARN(crtc->active && !crtc->base.enabled,
8524                      "active crtc, but not enabled in sw tracking\n");
8525
8526                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8527                                     base.head) {
8528                         if (encoder->base.crtc != &crtc->base)
8529                                 continue;
8530                         enabled = true;
8531                         if (encoder->connectors_active)
8532                                 active = true;
8533                 }
8534
8535                 WARN(active != crtc->active,
8536                      "crtc's computed active state doesn't match tracked active state "
8537                      "(expected %i, found %i)\n", active, crtc->active);
8538                 WARN(enabled != crtc->base.enabled,
8539                      "crtc's computed enabled state doesn't match tracked enabled state "
8540                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8541
8542                 active = dev_priv->display.get_pipe_config(crtc,
8543                                                            &pipe_config);
8544
8545                 /* hw state is inconsistent with the pipe A quirk */
8546                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8547                         active = crtc->active;
8548
8549                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8550                                     base.head) {
8551                         if (encoder->base.crtc != &crtc->base)
8552                                 continue;
8553                         if (encoder->get_config)
8554                                 encoder->get_config(encoder, &pipe_config);
8555                 }
8556
8557                 if (dev_priv->display.get_clock)
8558                         dev_priv->display.get_clock(crtc, &pipe_config);
8559
8560                 WARN(crtc->active != active,
8561                      "crtc active state doesn't match with hw state "
8562                      "(expected %i, found %i)\n", crtc->active, active);
8563
8564                 if (active &&
8565                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8566                         WARN(1, "pipe state doesn't match!\n");
8567                         intel_dump_pipe_config(crtc, &pipe_config,
8568                                                "[hw state]");
8569                         intel_dump_pipe_config(crtc, &crtc->config,
8570                                                "[sw state]");
8571                 }
8572         }
8573 }
8574
8575 static void
8576 check_shared_dpll_state(struct drm_device *dev)
8577 {
8578         drm_i915_private_t *dev_priv = dev->dev_private;
8579         struct intel_crtc *crtc;
8580         struct intel_dpll_hw_state dpll_hw_state;
8581         int i;
8582
8583         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8584                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8585                 int enabled_crtcs = 0, active_crtcs = 0;
8586                 bool active;
8587
8588                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8589
8590                 DRM_DEBUG_KMS("%s\n", pll->name);
8591
8592                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8593
8594                 WARN(pll->active > pll->refcount,
8595                      "more active pll users than references: %i vs %i\n",
8596                      pll->active, pll->refcount);
8597                 WARN(pll->active && !pll->on,
8598                      "pll in active use but not on in sw tracking\n");
8599                 WARN(pll->on && !pll->active,
8600                      "pll in on but not on in use in sw tracking\n");
8601                 WARN(pll->on != active,
8602                      "pll on state mismatch (expected %i, found %i)\n",
8603                      pll->on, active);
8604
8605                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8606                                     base.head) {
8607                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8608                                 enabled_crtcs++;
8609                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8610                                 active_crtcs++;
8611                 }
8612                 WARN(pll->active != active_crtcs,
8613                      "pll active crtcs mismatch (expected %i, found %i)\n",
8614                      pll->active, active_crtcs);
8615                 WARN(pll->refcount != enabled_crtcs,
8616                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8617                      pll->refcount, enabled_crtcs);
8618
8619                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8620                                        sizeof(dpll_hw_state)),
8621                      "pll hw state mismatch\n");
8622         }
8623 }
8624
8625 void
8626 intel_modeset_check_state(struct drm_device *dev)
8627 {
8628         check_connector_state(dev);
8629         check_encoder_state(dev);
8630         check_crtc_state(dev);
8631         check_shared_dpll_state(dev);
8632 }
8633
8634 static int __intel_set_mode(struct drm_crtc *crtc,
8635                             struct drm_display_mode *mode,
8636                             int x, int y, struct drm_framebuffer *fb)
8637 {
8638         struct drm_device *dev = crtc->dev;
8639         drm_i915_private_t *dev_priv = dev->dev_private;
8640         struct drm_display_mode *saved_mode, *saved_hwmode;
8641         struct intel_crtc_config *pipe_config = NULL;
8642         struct intel_crtc *intel_crtc;
8643         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8644         int ret = 0;
8645
8646         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8647         if (!saved_mode)
8648                 return -ENOMEM;
8649         saved_hwmode = saved_mode + 1;
8650
8651         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8652                                      &prepare_pipes, &disable_pipes);
8653
8654         *saved_hwmode = crtc->hwmode;
8655         *saved_mode = crtc->mode;
8656
8657         /* Hack: Because we don't (yet) support global modeset on multiple
8658          * crtcs, we don't keep track of the new mode for more than one crtc.
8659          * Hence simply check whether any bit is set in modeset_pipes in all the
8660          * pieces of code that are not yet converted to deal with mutliple crtcs
8661          * changing their mode at the same time. */
8662         if (modeset_pipes) {
8663                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8664                 if (IS_ERR(pipe_config)) {
8665                         ret = PTR_ERR(pipe_config);
8666                         pipe_config = NULL;
8667
8668                         goto out;
8669                 }
8670                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8671                                        "[modeset]");
8672         }
8673
8674         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8675                 intel_crtc_disable(&intel_crtc->base);
8676
8677         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8678                 if (intel_crtc->base.enabled)
8679                         dev_priv->display.crtc_disable(&intel_crtc->base);
8680         }
8681
8682         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8683          * to set it here already despite that we pass it down the callchain.
8684          */
8685         if (modeset_pipes) {
8686                 crtc->mode = *mode;
8687                 /* mode_set/enable/disable functions rely on a correct pipe
8688                  * config. */
8689                 to_intel_crtc(crtc)->config = *pipe_config;
8690         }
8691
8692         /* Only after disabling all output pipelines that will be changed can we
8693          * update the the output configuration. */
8694         intel_modeset_update_state(dev, prepare_pipes);
8695
8696         if (dev_priv->display.modeset_global_resources)
8697                 dev_priv->display.modeset_global_resources(dev);
8698
8699         /* Set up the DPLL and any encoders state that needs to adjust or depend
8700          * on the DPLL.
8701          */
8702         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8703                 ret = intel_crtc_mode_set(&intel_crtc->base,
8704                                           x, y, fb);
8705                 if (ret)
8706                         goto done;
8707         }
8708
8709         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8710         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8711                 dev_priv->display.crtc_enable(&intel_crtc->base);
8712
8713         if (modeset_pipes) {
8714                 /* Store real post-adjustment hardware mode. */
8715                 crtc->hwmode = pipe_config->adjusted_mode;
8716
8717                 /* Calculate and store various constants which
8718                  * are later needed by vblank and swap-completion
8719                  * timestamping. They are derived from true hwmode.
8720                  */
8721                 drm_calc_timestamping_constants(crtc);
8722         }
8723
8724         /* FIXME: add subpixel order */
8725 done:
8726         if (ret && crtc->enabled) {
8727                 crtc->hwmode = *saved_hwmode;
8728                 crtc->mode = *saved_mode;
8729         }
8730
8731 out:
8732         kfree(pipe_config);
8733         kfree(saved_mode);
8734         return ret;
8735 }
8736
8737 int intel_set_mode(struct drm_crtc *crtc,
8738                      struct drm_display_mode *mode,
8739                      int x, int y, struct drm_framebuffer *fb)
8740 {
8741         int ret;
8742
8743         ret = __intel_set_mode(crtc, mode, x, y, fb);
8744
8745         if (ret == 0)
8746                 intel_modeset_check_state(crtc->dev);
8747
8748         return ret;
8749 }
8750
8751 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8752 {
8753         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8754 }
8755
8756 #undef for_each_intel_crtc_masked
8757
8758 static void intel_set_config_free(struct intel_set_config *config)
8759 {
8760         if (!config)
8761                 return;
8762
8763         kfree(config->save_connector_encoders);
8764         kfree(config->save_encoder_crtcs);
8765         kfree(config);
8766 }
8767
8768 static int intel_set_config_save_state(struct drm_device *dev,
8769                                        struct intel_set_config *config)
8770 {
8771         struct drm_encoder *encoder;
8772         struct drm_connector *connector;
8773         int count;
8774
8775         config->save_encoder_crtcs =
8776                 kcalloc(dev->mode_config.num_encoder,
8777                         sizeof(struct drm_crtc *), GFP_KERNEL);
8778         if (!config->save_encoder_crtcs)
8779                 return -ENOMEM;
8780
8781         config->save_connector_encoders =
8782                 kcalloc(dev->mode_config.num_connector,
8783                         sizeof(struct drm_encoder *), GFP_KERNEL);
8784         if (!config->save_connector_encoders)
8785                 return -ENOMEM;
8786
8787         /* Copy data. Note that driver private data is not affected.
8788          * Should anything bad happen only the expected state is
8789          * restored, not the drivers personal bookkeeping.
8790          */
8791         count = 0;
8792         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8793                 config->save_encoder_crtcs[count++] = encoder->crtc;
8794         }
8795
8796         count = 0;
8797         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8798                 config->save_connector_encoders[count++] = connector->encoder;
8799         }
8800
8801         return 0;
8802 }
8803
8804 static void intel_set_config_restore_state(struct drm_device *dev,
8805                                            struct intel_set_config *config)
8806 {
8807         struct intel_encoder *encoder;
8808         struct intel_connector *connector;
8809         int count;
8810
8811         count = 0;
8812         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8813                 encoder->new_crtc =
8814                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8815         }
8816
8817         count = 0;
8818         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8819                 connector->new_encoder =
8820                         to_intel_encoder(config->save_connector_encoders[count++]);
8821         }
8822 }
8823
8824 static bool
8825 is_crtc_connector_off(struct drm_mode_set *set)
8826 {
8827         int i;
8828
8829         if (set->num_connectors == 0)
8830                 return false;
8831
8832         if (WARN_ON(set->connectors == NULL))
8833                 return false;
8834
8835         for (i = 0; i < set->num_connectors; i++)
8836                 if (set->connectors[i]->encoder &&
8837                     set->connectors[i]->encoder->crtc == set->crtc &&
8838                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8839                         return true;
8840
8841         return false;
8842 }
8843
8844 static void
8845 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8846                                       struct intel_set_config *config)
8847 {
8848
8849         /* We should be able to check here if the fb has the same properties
8850          * and then just flip_or_move it */
8851         if (is_crtc_connector_off(set)) {
8852                 config->mode_changed = true;
8853         } else if (set->crtc->fb != set->fb) {
8854                 /* If we have no fb then treat it as a full mode set */
8855                 if (set->crtc->fb == NULL) {
8856                         struct intel_crtc *intel_crtc =
8857                                 to_intel_crtc(set->crtc);
8858
8859                         if (intel_crtc->active && i915_fastboot) {
8860                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8861                                 config->fb_changed = true;
8862                         } else {
8863                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8864                                 config->mode_changed = true;
8865                         }
8866                 } else if (set->fb == NULL) {
8867                         config->mode_changed = true;
8868                 } else if (set->fb->pixel_format !=
8869                            set->crtc->fb->pixel_format) {
8870                         config->mode_changed = true;
8871                 } else {
8872                         config->fb_changed = true;
8873                 }
8874         }
8875
8876         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8877                 config->fb_changed = true;
8878
8879         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8880                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8881                 drm_mode_debug_printmodeline(&set->crtc->mode);
8882                 drm_mode_debug_printmodeline(set->mode);
8883                 config->mode_changed = true;
8884         }
8885 }
8886
8887 static int
8888 intel_modeset_stage_output_state(struct drm_device *dev,
8889                                  struct drm_mode_set *set,
8890                                  struct intel_set_config *config)
8891 {
8892         struct drm_crtc *new_crtc;
8893         struct intel_connector *connector;
8894         struct intel_encoder *encoder;
8895         int count, ro;
8896
8897         /* The upper layers ensure that we either disable a crtc or have a list
8898          * of connectors. For paranoia, double-check this. */
8899         WARN_ON(!set->fb && (set->num_connectors != 0));
8900         WARN_ON(set->fb && (set->num_connectors == 0));
8901
8902         count = 0;
8903         list_for_each_entry(connector, &dev->mode_config.connector_list,
8904                             base.head) {
8905                 /* Otherwise traverse passed in connector list and get encoders
8906                  * for them. */
8907                 for (ro = 0; ro < set->num_connectors; ro++) {
8908                         if (set->connectors[ro] == &connector->base) {
8909                                 connector->new_encoder = connector->encoder;
8910                                 break;
8911                         }
8912                 }
8913
8914                 /* If we disable the crtc, disable all its connectors. Also, if
8915                  * the connector is on the changing crtc but not on the new
8916                  * connector list, disable it. */
8917                 if ((!set->fb || ro == set->num_connectors) &&
8918                     connector->base.encoder &&
8919                     connector->base.encoder->crtc == set->crtc) {
8920                         connector->new_encoder = NULL;
8921
8922                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8923                                 connector->base.base.id,
8924                                 drm_get_connector_name(&connector->base));
8925                 }
8926
8927
8928                 if (&connector->new_encoder->base != connector->base.encoder) {
8929                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8930                         config->mode_changed = true;
8931                 }
8932         }
8933         /* connector->new_encoder is now updated for all connectors. */
8934
8935         /* Update crtc of enabled connectors. */
8936         count = 0;
8937         list_for_each_entry(connector, &dev->mode_config.connector_list,
8938                             base.head) {
8939                 if (!connector->new_encoder)
8940                         continue;
8941
8942                 new_crtc = connector->new_encoder->base.crtc;
8943
8944                 for (ro = 0; ro < set->num_connectors; ro++) {
8945                         if (set->connectors[ro] == &connector->base)
8946                                 new_crtc = set->crtc;
8947                 }
8948
8949                 /* Make sure the new CRTC will work with the encoder */
8950                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8951                                            new_crtc)) {
8952                         return -EINVAL;
8953                 }
8954                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8955
8956                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8957                         connector->base.base.id,
8958                         drm_get_connector_name(&connector->base),
8959                         new_crtc->base.id);
8960         }
8961
8962         /* Check for any encoders that needs to be disabled. */
8963         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8964                             base.head) {
8965                 list_for_each_entry(connector,
8966                                     &dev->mode_config.connector_list,
8967                                     base.head) {
8968                         if (connector->new_encoder == encoder) {
8969                                 WARN_ON(!connector->new_encoder->new_crtc);
8970
8971                                 goto next_encoder;
8972                         }
8973                 }
8974                 encoder->new_crtc = NULL;
8975 next_encoder:
8976                 /* Only now check for crtc changes so we don't miss encoders
8977                  * that will be disabled. */
8978                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8979                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8980                         config->mode_changed = true;
8981                 }
8982         }
8983         /* Now we've also updated encoder->new_crtc for all encoders. */
8984
8985         return 0;
8986 }
8987
8988 static int intel_crtc_set_config(struct drm_mode_set *set)
8989 {
8990         struct drm_device *dev;
8991         struct drm_mode_set save_set;
8992         struct intel_set_config *config;
8993         int ret;
8994
8995         BUG_ON(!set);
8996         BUG_ON(!set->crtc);
8997         BUG_ON(!set->crtc->helper_private);
8998
8999         /* Enforce sane interface api - has been abused by the fb helper. */
9000         BUG_ON(!set->mode && set->fb);
9001         BUG_ON(set->fb && set->num_connectors == 0);
9002
9003         if (set->fb) {
9004                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9005                                 set->crtc->base.id, set->fb->base.id,
9006                                 (int)set->num_connectors, set->x, set->y);
9007         } else {
9008                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9009         }
9010
9011         dev = set->crtc->dev;
9012
9013         ret = -ENOMEM;
9014         config = kzalloc(sizeof(*config), GFP_KERNEL);
9015         if (!config)
9016                 goto out_config;
9017
9018         ret = intel_set_config_save_state(dev, config);
9019         if (ret)
9020                 goto out_config;
9021
9022         save_set.crtc = set->crtc;
9023         save_set.mode = &set->crtc->mode;
9024         save_set.x = set->crtc->x;
9025         save_set.y = set->crtc->y;
9026         save_set.fb = set->crtc->fb;
9027
9028         /* Compute whether we need a full modeset, only an fb base update or no
9029          * change at all. In the future we might also check whether only the
9030          * mode changed, e.g. for LVDS where we only change the panel fitter in
9031          * such cases. */
9032         intel_set_config_compute_mode_changes(set, config);
9033
9034         ret = intel_modeset_stage_output_state(dev, set, config);
9035         if (ret)
9036                 goto fail;
9037
9038         if (config->mode_changed) {
9039                 ret = intel_set_mode(set->crtc, set->mode,
9040                                      set->x, set->y, set->fb);
9041         } else if (config->fb_changed) {
9042                 intel_crtc_wait_for_pending_flips(set->crtc);
9043
9044                 ret = intel_pipe_set_base(set->crtc,
9045                                           set->x, set->y, set->fb);
9046         }
9047
9048         if (ret) {
9049                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9050                               set->crtc->base.id, ret);
9051 fail:
9052                 intel_set_config_restore_state(dev, config);
9053
9054                 /* Try to restore the config */
9055                 if (config->mode_changed &&
9056                     intel_set_mode(save_set.crtc, save_set.mode,
9057                                    save_set.x, save_set.y, save_set.fb))
9058                         DRM_ERROR("failed to restore config after modeset failure\n");
9059         }
9060
9061 out_config:
9062         intel_set_config_free(config);
9063         return ret;
9064 }
9065
9066 static const struct drm_crtc_funcs intel_crtc_funcs = {
9067         .cursor_set = intel_crtc_cursor_set,
9068         .cursor_move = intel_crtc_cursor_move,
9069         .gamma_set = intel_crtc_gamma_set,
9070         .set_config = intel_crtc_set_config,
9071         .destroy = intel_crtc_destroy,
9072         .page_flip = intel_crtc_page_flip,
9073 };
9074
9075 static void intel_cpu_pll_init(struct drm_device *dev)
9076 {
9077         if (HAS_DDI(dev))
9078                 intel_ddi_pll_init(dev);
9079 }
9080
9081 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9082                                       struct intel_shared_dpll *pll,
9083                                       struct intel_dpll_hw_state *hw_state)
9084 {
9085         uint32_t val;
9086
9087         val = I915_READ(PCH_DPLL(pll->id));
9088         hw_state->dpll = val;
9089         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9090         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9091
9092         return val & DPLL_VCO_ENABLE;
9093 }
9094
9095 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9096                                   struct intel_shared_dpll *pll)
9097 {
9098         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9099         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9100 }
9101
9102 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9103                                 struct intel_shared_dpll *pll)
9104 {
9105         /* PCH refclock must be enabled first */
9106         assert_pch_refclk_enabled(dev_priv);
9107
9108         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9109
9110         /* Wait for the clocks to stabilize. */
9111         POSTING_READ(PCH_DPLL(pll->id));
9112         udelay(150);
9113
9114         /* The pixel multiplier can only be updated once the
9115          * DPLL is enabled and the clocks are stable.
9116          *
9117          * So write it again.
9118          */
9119         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9120         POSTING_READ(PCH_DPLL(pll->id));
9121         udelay(200);
9122 }
9123
9124 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9125                                  struct intel_shared_dpll *pll)
9126 {
9127         struct drm_device *dev = dev_priv->dev;
9128         struct intel_crtc *crtc;
9129
9130         /* Make sure no transcoder isn't still depending on us. */
9131         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9132                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9133                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9134         }
9135
9136         I915_WRITE(PCH_DPLL(pll->id), 0);
9137         POSTING_READ(PCH_DPLL(pll->id));
9138         udelay(200);
9139 }
9140
9141 static char *ibx_pch_dpll_names[] = {
9142         "PCH DPLL A",
9143         "PCH DPLL B",
9144 };
9145
9146 static void ibx_pch_dpll_init(struct drm_device *dev)
9147 {
9148         struct drm_i915_private *dev_priv = dev->dev_private;
9149         int i;
9150
9151         dev_priv->num_shared_dpll = 2;
9152
9153         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9154                 dev_priv->shared_dplls[i].id = i;
9155                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9156                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9157                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9158                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9159                 dev_priv->shared_dplls[i].get_hw_state =
9160                         ibx_pch_dpll_get_hw_state;
9161         }
9162 }
9163
9164 static void intel_shared_dpll_init(struct drm_device *dev)
9165 {
9166         struct drm_i915_private *dev_priv = dev->dev_private;
9167
9168         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9169                 ibx_pch_dpll_init(dev);
9170         else
9171                 dev_priv->num_shared_dpll = 0;
9172
9173         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9174         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9175                       dev_priv->num_shared_dpll);
9176 }
9177
9178 static void intel_crtc_init(struct drm_device *dev, int pipe)
9179 {
9180         drm_i915_private_t *dev_priv = dev->dev_private;
9181         struct intel_crtc *intel_crtc;
9182         int i;
9183
9184         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9185         if (intel_crtc == NULL)
9186                 return;
9187
9188         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9189
9190         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9191         for (i = 0; i < 256; i++) {
9192                 intel_crtc->lut_r[i] = i;
9193                 intel_crtc->lut_g[i] = i;
9194                 intel_crtc->lut_b[i] = i;
9195         }
9196
9197         /* Swap pipes & planes for FBC on pre-965 */
9198         intel_crtc->pipe = pipe;
9199         intel_crtc->plane = pipe;
9200         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9201                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9202                 intel_crtc->plane = !pipe;
9203         }
9204
9205         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9206                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9207         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9208         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9209
9210         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9211 }
9212
9213 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9214                                 struct drm_file *file)
9215 {
9216         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9217         struct drm_mode_object *drmmode_obj;
9218         struct intel_crtc *crtc;
9219
9220         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9221                 return -ENODEV;
9222
9223         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9224                         DRM_MODE_OBJECT_CRTC);
9225
9226         if (!drmmode_obj) {
9227                 DRM_ERROR("no such CRTC id\n");
9228                 return -EINVAL;
9229         }
9230
9231         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9232         pipe_from_crtc_id->pipe = crtc->pipe;
9233
9234         return 0;
9235 }
9236
9237 static int intel_encoder_clones(struct intel_encoder *encoder)
9238 {
9239         struct drm_device *dev = encoder->base.dev;
9240         struct intel_encoder *source_encoder;
9241         int index_mask = 0;
9242         int entry = 0;
9243
9244         list_for_each_entry(source_encoder,
9245                             &dev->mode_config.encoder_list, base.head) {
9246
9247                 if (encoder == source_encoder)
9248                         index_mask |= (1 << entry);
9249
9250                 /* Intel hw has only one MUX where enocoders could be cloned. */
9251                 if (encoder->cloneable && source_encoder->cloneable)
9252                         index_mask |= (1 << entry);
9253
9254                 entry++;
9255         }
9256
9257         return index_mask;
9258 }
9259
9260 static bool has_edp_a(struct drm_device *dev)
9261 {
9262         struct drm_i915_private *dev_priv = dev->dev_private;
9263
9264         if (!IS_MOBILE(dev))
9265                 return false;
9266
9267         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9268                 return false;
9269
9270         if (IS_GEN5(dev) &&
9271             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9272                 return false;
9273
9274         return true;
9275 }
9276
9277 static void intel_setup_outputs(struct drm_device *dev)
9278 {
9279         struct drm_i915_private *dev_priv = dev->dev_private;
9280         struct intel_encoder *encoder;
9281         bool dpd_is_edp = false;
9282
9283         intel_lvds_init(dev);
9284
9285         if (!IS_ULT(dev))
9286                 intel_crt_init(dev);
9287
9288         if (HAS_DDI(dev)) {
9289                 int found;
9290
9291                 /* Haswell uses DDI functions to detect digital outputs */
9292                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9293                 /* DDI A only supports eDP */
9294                 if (found)
9295                         intel_ddi_init(dev, PORT_A);
9296
9297                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9298                  * register */
9299                 found = I915_READ(SFUSE_STRAP);
9300
9301                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9302                         intel_ddi_init(dev, PORT_B);
9303                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9304                         intel_ddi_init(dev, PORT_C);
9305                 if (found & SFUSE_STRAP_DDID_DETECTED)
9306                         intel_ddi_init(dev, PORT_D);
9307         } else if (HAS_PCH_SPLIT(dev)) {
9308                 int found;
9309                 dpd_is_edp = intel_dpd_is_edp(dev);
9310
9311                 if (has_edp_a(dev))
9312                         intel_dp_init(dev, DP_A, PORT_A);
9313
9314                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9315                         /* PCH SDVOB multiplex with HDMIB */
9316                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9317                         if (!found)
9318                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9319                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9320                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9321                 }
9322
9323                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9324                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9325
9326                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9327                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9328
9329                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9330                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9331
9332                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9333                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9334         } else if (IS_VALLEYVIEW(dev)) {
9335                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9336                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9337                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9338
9339                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9340                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9341                                         PORT_B);
9342                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9343                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9344                 }
9345         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9346                 bool found = false;
9347
9348                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9349                         DRM_DEBUG_KMS("probing SDVOB\n");
9350                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9351                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9352                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9353                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9354                         }
9355
9356                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9357                                 intel_dp_init(dev, DP_B, PORT_B);
9358                 }
9359
9360                 /* Before G4X SDVOC doesn't have its own detect register */
9361
9362                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9363                         DRM_DEBUG_KMS("probing SDVOC\n");
9364                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9365                 }
9366
9367                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9368
9369                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9370                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9371                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9372                         }
9373                         if (SUPPORTS_INTEGRATED_DP(dev))
9374                                 intel_dp_init(dev, DP_C, PORT_C);
9375                 }
9376
9377                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9378                     (I915_READ(DP_D) & DP_DETECTED))
9379                         intel_dp_init(dev, DP_D, PORT_D);
9380         } else if (IS_GEN2(dev))
9381                 intel_dvo_init(dev);
9382
9383         if (SUPPORTS_TV(dev))
9384                 intel_tv_init(dev);
9385
9386         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9387                 encoder->base.possible_crtcs = encoder->crtc_mask;
9388                 encoder->base.possible_clones =
9389                         intel_encoder_clones(encoder);
9390         }
9391
9392         intel_init_pch_refclk(dev);
9393
9394         drm_helper_move_panel_connectors_to_head(dev);
9395 }
9396
9397 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9398 {
9399         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9400
9401         drm_framebuffer_cleanup(fb);
9402         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9403
9404         kfree(intel_fb);
9405 }
9406
9407 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9408                                                 struct drm_file *file,
9409                                                 unsigned int *handle)
9410 {
9411         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9412         struct drm_i915_gem_object *obj = intel_fb->obj;
9413
9414         return drm_gem_handle_create(file, &obj->base, handle);
9415 }
9416
9417 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9418         .destroy = intel_user_framebuffer_destroy,
9419         .create_handle = intel_user_framebuffer_create_handle,
9420 };
9421
9422 int intel_framebuffer_init(struct drm_device *dev,
9423                            struct intel_framebuffer *intel_fb,
9424                            struct drm_mode_fb_cmd2 *mode_cmd,
9425                            struct drm_i915_gem_object *obj)
9426 {
9427         int pitch_limit;
9428         int ret;
9429
9430         if (obj->tiling_mode == I915_TILING_Y) {
9431                 DRM_DEBUG("hardware does not support tiling Y\n");
9432                 return -EINVAL;
9433         }
9434
9435         if (mode_cmd->pitches[0] & 63) {
9436                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9437                           mode_cmd->pitches[0]);
9438                 return -EINVAL;
9439         }
9440
9441         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9442                 pitch_limit = 32*1024;
9443         } else if (INTEL_INFO(dev)->gen >= 4) {
9444                 if (obj->tiling_mode)
9445                         pitch_limit = 16*1024;
9446                 else
9447                         pitch_limit = 32*1024;
9448         } else if (INTEL_INFO(dev)->gen >= 3) {
9449                 if (obj->tiling_mode)
9450                         pitch_limit = 8*1024;
9451                 else
9452                         pitch_limit = 16*1024;
9453         } else
9454                 /* XXX DSPC is limited to 4k tiled */
9455                 pitch_limit = 8*1024;
9456
9457         if (mode_cmd->pitches[0] > pitch_limit) {
9458                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9459                           obj->tiling_mode ? "tiled" : "linear",
9460                           mode_cmd->pitches[0], pitch_limit);
9461                 return -EINVAL;
9462         }
9463
9464         if (obj->tiling_mode != I915_TILING_NONE &&
9465             mode_cmd->pitches[0] != obj->stride) {
9466                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9467                           mode_cmd->pitches[0], obj->stride);
9468                 return -EINVAL;
9469         }
9470
9471         /* Reject formats not supported by any plane early. */
9472         switch (mode_cmd->pixel_format) {
9473         case DRM_FORMAT_C8:
9474         case DRM_FORMAT_RGB565:
9475         case DRM_FORMAT_XRGB8888:
9476         case DRM_FORMAT_ARGB8888:
9477                 break;
9478         case DRM_FORMAT_XRGB1555:
9479         case DRM_FORMAT_ARGB1555:
9480                 if (INTEL_INFO(dev)->gen > 3) {
9481                         DRM_DEBUG("unsupported pixel format: %s\n",
9482                                   drm_get_format_name(mode_cmd->pixel_format));
9483                         return -EINVAL;
9484                 }
9485                 break;
9486         case DRM_FORMAT_XBGR8888:
9487         case DRM_FORMAT_ABGR8888:
9488         case DRM_FORMAT_XRGB2101010:
9489         case DRM_FORMAT_ARGB2101010:
9490         case DRM_FORMAT_XBGR2101010:
9491         case DRM_FORMAT_ABGR2101010:
9492                 if (INTEL_INFO(dev)->gen < 4) {
9493                         DRM_DEBUG("unsupported pixel format: %s\n",
9494                                   drm_get_format_name(mode_cmd->pixel_format));
9495                         return -EINVAL;
9496                 }
9497                 break;
9498         case DRM_FORMAT_YUYV:
9499         case DRM_FORMAT_UYVY:
9500         case DRM_FORMAT_YVYU:
9501         case DRM_FORMAT_VYUY:
9502                 if (INTEL_INFO(dev)->gen < 5) {
9503                         DRM_DEBUG("unsupported pixel format: %s\n",
9504                                   drm_get_format_name(mode_cmd->pixel_format));
9505                         return -EINVAL;
9506                 }
9507                 break;
9508         default:
9509                 DRM_DEBUG("unsupported pixel format: %s\n",
9510                           drm_get_format_name(mode_cmd->pixel_format));
9511                 return -EINVAL;
9512         }
9513
9514         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9515         if (mode_cmd->offsets[0] != 0)
9516                 return -EINVAL;
9517
9518         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9519         intel_fb->obj = obj;
9520
9521         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9522         if (ret) {
9523                 DRM_ERROR("framebuffer init failed %d\n", ret);
9524                 return ret;
9525         }
9526
9527         return 0;
9528 }
9529
9530 static struct drm_framebuffer *
9531 intel_user_framebuffer_create(struct drm_device *dev,
9532                               struct drm_file *filp,
9533                               struct drm_mode_fb_cmd2 *mode_cmd)
9534 {
9535         struct drm_i915_gem_object *obj;
9536
9537         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9538                                                 mode_cmd->handles[0]));
9539         if (&obj->base == NULL)
9540                 return ERR_PTR(-ENOENT);
9541
9542         return intel_framebuffer_create(dev, mode_cmd, obj);
9543 }
9544
9545 static const struct drm_mode_config_funcs intel_mode_funcs = {
9546         .fb_create = intel_user_framebuffer_create,
9547         .output_poll_changed = intel_fb_output_poll_changed,
9548 };
9549
9550 /* Set up chip specific display functions */
9551 static void intel_init_display(struct drm_device *dev)
9552 {
9553         struct drm_i915_private *dev_priv = dev->dev_private;
9554
9555         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9556                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9557         else if (IS_VALLEYVIEW(dev))
9558                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9559         else if (IS_PINEVIEW(dev))
9560                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9561         else
9562                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9563
9564         if (HAS_DDI(dev)) {
9565                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9566                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9567                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9568                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9569                 dev_priv->display.off = haswell_crtc_off;
9570                 dev_priv->display.update_plane = ironlake_update_plane;
9571         } else if (HAS_PCH_SPLIT(dev)) {
9572                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9573                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9574                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9575                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9576                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9577                 dev_priv->display.off = ironlake_crtc_off;
9578                 dev_priv->display.update_plane = ironlake_update_plane;
9579         } else if (IS_VALLEYVIEW(dev)) {
9580                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9581                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9582                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9583                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9584                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9585                 dev_priv->display.off = i9xx_crtc_off;
9586                 dev_priv->display.update_plane = i9xx_update_plane;
9587         } else {
9588                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9589                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9590                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9591                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9592                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9593                 dev_priv->display.off = i9xx_crtc_off;
9594                 dev_priv->display.update_plane = i9xx_update_plane;
9595         }
9596
9597         /* Returns the core display clock speed */
9598         if (IS_VALLEYVIEW(dev))
9599                 dev_priv->display.get_display_clock_speed =
9600                         valleyview_get_display_clock_speed;
9601         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9602                 dev_priv->display.get_display_clock_speed =
9603                         i945_get_display_clock_speed;
9604         else if (IS_I915G(dev))
9605                 dev_priv->display.get_display_clock_speed =
9606                         i915_get_display_clock_speed;
9607         else if (IS_I945GM(dev) || IS_845G(dev))
9608                 dev_priv->display.get_display_clock_speed =
9609                         i9xx_misc_get_display_clock_speed;
9610         else if (IS_PINEVIEW(dev))
9611                 dev_priv->display.get_display_clock_speed =
9612                         pnv_get_display_clock_speed;
9613         else if (IS_I915GM(dev))
9614                 dev_priv->display.get_display_clock_speed =
9615                         i915gm_get_display_clock_speed;
9616         else if (IS_I865G(dev))
9617                 dev_priv->display.get_display_clock_speed =
9618                         i865_get_display_clock_speed;
9619         else if (IS_I85X(dev))
9620                 dev_priv->display.get_display_clock_speed =
9621                         i855_get_display_clock_speed;
9622         else /* 852, 830 */
9623                 dev_priv->display.get_display_clock_speed =
9624                         i830_get_display_clock_speed;
9625
9626         if (HAS_PCH_SPLIT(dev)) {
9627                 if (IS_GEN5(dev)) {
9628                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9629                         dev_priv->display.write_eld = ironlake_write_eld;
9630                 } else if (IS_GEN6(dev)) {
9631                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9632                         dev_priv->display.write_eld = ironlake_write_eld;
9633                 } else if (IS_IVYBRIDGE(dev)) {
9634                         /* FIXME: detect B0+ stepping and use auto training */
9635                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9636                         dev_priv->display.write_eld = ironlake_write_eld;
9637                         dev_priv->display.modeset_global_resources =
9638                                 ivb_modeset_global_resources;
9639                 } else if (IS_HASWELL(dev)) {
9640                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9641                         dev_priv->display.write_eld = haswell_write_eld;
9642                         dev_priv->display.modeset_global_resources =
9643                                 haswell_modeset_global_resources;
9644                 }
9645         } else if (IS_G4X(dev)) {
9646                 dev_priv->display.write_eld = g4x_write_eld;
9647         }
9648
9649         /* Default just returns -ENODEV to indicate unsupported */
9650         dev_priv->display.queue_flip = intel_default_queue_flip;
9651
9652         switch (INTEL_INFO(dev)->gen) {
9653         case 2:
9654                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9655                 break;
9656
9657         case 3:
9658                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9659                 break;
9660
9661         case 4:
9662         case 5:
9663                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9664                 break;
9665
9666         case 6:
9667                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9668                 break;
9669         case 7:
9670                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9671                 break;
9672         }
9673 }
9674
9675 /*
9676  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9677  * resume, or other times.  This quirk makes sure that's the case for
9678  * affected systems.
9679  */
9680 static void quirk_pipea_force(struct drm_device *dev)
9681 {
9682         struct drm_i915_private *dev_priv = dev->dev_private;
9683
9684         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9685         DRM_INFO("applying pipe a force quirk\n");
9686 }
9687
9688 /*
9689  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9690  */
9691 static void quirk_ssc_force_disable(struct drm_device *dev)
9692 {
9693         struct drm_i915_private *dev_priv = dev->dev_private;
9694         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9695         DRM_INFO("applying lvds SSC disable quirk\n");
9696 }
9697
9698 /*
9699  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9700  * brightness value
9701  */
9702 static void quirk_invert_brightness(struct drm_device *dev)
9703 {
9704         struct drm_i915_private *dev_priv = dev->dev_private;
9705         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9706         DRM_INFO("applying inverted panel brightness quirk\n");
9707 }
9708
9709 /*
9710  * Some machines (Dell XPS13) suffer broken backlight controls if
9711  * BLM_PCH_PWM_ENABLE is set.
9712  */
9713 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9714 {
9715         struct drm_i915_private *dev_priv = dev->dev_private;
9716         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9717         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9718 }
9719
9720 struct intel_quirk {
9721         int device;
9722         int subsystem_vendor;
9723         int subsystem_device;
9724         void (*hook)(struct drm_device *dev);
9725 };
9726
9727 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9728 struct intel_dmi_quirk {
9729         void (*hook)(struct drm_device *dev);
9730         const struct dmi_system_id (*dmi_id_list)[];
9731 };
9732
9733 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9734 {
9735         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9736         return 1;
9737 }
9738
9739 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9740         {
9741                 .dmi_id_list = &(const struct dmi_system_id[]) {
9742                         {
9743                                 .callback = intel_dmi_reverse_brightness,
9744                                 .ident = "NCR Corporation",
9745                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9746                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9747                                 },
9748                         },
9749                         { }  /* terminating entry */
9750                 },
9751                 .hook = quirk_invert_brightness,
9752         },
9753 };
9754
9755 static struct intel_quirk intel_quirks[] = {
9756         /* HP Mini needs pipe A force quirk (LP: #322104) */
9757         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9758
9759         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9760         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9761
9762         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9763         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9764
9765         /* 830/845 need to leave pipe A & dpll A up */
9766         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9767         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9768
9769         /* Lenovo U160 cannot use SSC on LVDS */
9770         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9771
9772         /* Sony Vaio Y cannot use SSC on LVDS */
9773         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9774
9775         /* Acer Aspire 5734Z must invert backlight brightness */
9776         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9777
9778         /* Acer/eMachines G725 */
9779         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9780
9781         /* Acer/eMachines e725 */
9782         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9783
9784         /* Acer/Packard Bell NCL20 */
9785         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9786
9787         /* Acer Aspire 4736Z */
9788         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9789
9790         /* Dell XPS13 HD Sandy Bridge */
9791         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9792         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9793         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9794 };
9795
9796 static void intel_init_quirks(struct drm_device *dev)
9797 {
9798         struct pci_dev *d = dev->pdev;
9799         int i;
9800
9801         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9802                 struct intel_quirk *q = &intel_quirks[i];
9803
9804                 if (d->device == q->device &&
9805                     (d->subsystem_vendor == q->subsystem_vendor ||
9806                      q->subsystem_vendor == PCI_ANY_ID) &&
9807                     (d->subsystem_device == q->subsystem_device ||
9808                      q->subsystem_device == PCI_ANY_ID))
9809                         q->hook(dev);
9810         }
9811         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9812                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9813                         intel_dmi_quirks[i].hook(dev);
9814         }
9815 }
9816
9817 /* Disable the VGA plane that we never use */
9818 static void i915_disable_vga(struct drm_device *dev)
9819 {
9820         struct drm_i915_private *dev_priv = dev->dev_private;
9821         u8 sr1;
9822         u32 vga_reg = i915_vgacntrl_reg(dev);
9823
9824         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9825         outb(SR01, VGA_SR_INDEX);
9826         sr1 = inb(VGA_SR_DATA);
9827         outb(sr1 | 1<<5, VGA_SR_DATA);
9828         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9829         udelay(300);
9830
9831         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9832         POSTING_READ(vga_reg);
9833 }
9834
9835 void intel_modeset_init_hw(struct drm_device *dev)
9836 {
9837         intel_init_power_well(dev);
9838
9839         intel_prepare_ddi(dev);
9840
9841         intel_init_clock_gating(dev);
9842
9843         mutex_lock(&dev->struct_mutex);
9844         intel_enable_gt_powersave(dev);
9845         mutex_unlock(&dev->struct_mutex);
9846 }
9847
9848 void intel_modeset_suspend_hw(struct drm_device *dev)
9849 {
9850         intel_suspend_hw(dev);
9851 }
9852
9853 void intel_modeset_init(struct drm_device *dev)
9854 {
9855         struct drm_i915_private *dev_priv = dev->dev_private;
9856         int i, j, ret;
9857
9858         drm_mode_config_init(dev);
9859
9860         dev->mode_config.min_width = 0;
9861         dev->mode_config.min_height = 0;
9862
9863         dev->mode_config.preferred_depth = 24;
9864         dev->mode_config.prefer_shadow = 1;
9865
9866         dev->mode_config.funcs = &intel_mode_funcs;
9867
9868         intel_init_quirks(dev);
9869
9870         intel_init_pm(dev);
9871
9872         if (INTEL_INFO(dev)->num_pipes == 0)
9873                 return;
9874
9875         intel_init_display(dev);
9876
9877         if (IS_GEN2(dev)) {
9878                 dev->mode_config.max_width = 2048;
9879                 dev->mode_config.max_height = 2048;
9880         } else if (IS_GEN3(dev)) {
9881                 dev->mode_config.max_width = 4096;
9882                 dev->mode_config.max_height = 4096;
9883         } else {
9884                 dev->mode_config.max_width = 8192;
9885                 dev->mode_config.max_height = 8192;
9886         }
9887         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9888
9889         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9890                       INTEL_INFO(dev)->num_pipes,
9891                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9892
9893         for_each_pipe(i) {
9894                 intel_crtc_init(dev, i);
9895                 for (j = 0; j < dev_priv->num_plane; j++) {
9896                         ret = intel_plane_init(dev, i, j);
9897                         if (ret)
9898                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9899                                               pipe_name(i), sprite_name(i, j), ret);
9900                 }
9901         }
9902
9903         intel_cpu_pll_init(dev);
9904         intel_shared_dpll_init(dev);
9905
9906         /* Just disable it once at startup */
9907         i915_disable_vga(dev);
9908         intel_setup_outputs(dev);
9909
9910         /* Just in case the BIOS is doing something questionable. */
9911         intel_disable_fbc(dev);
9912 }
9913
9914 static void
9915 intel_connector_break_all_links(struct intel_connector *connector)
9916 {
9917         connector->base.dpms = DRM_MODE_DPMS_OFF;
9918         connector->base.encoder = NULL;
9919         connector->encoder->connectors_active = false;
9920         connector->encoder->base.crtc = NULL;
9921 }
9922
9923 static void intel_enable_pipe_a(struct drm_device *dev)
9924 {
9925         struct intel_connector *connector;
9926         struct drm_connector *crt = NULL;
9927         struct intel_load_detect_pipe load_detect_temp;
9928
9929         /* We can't just switch on the pipe A, we need to set things up with a
9930          * proper mode and output configuration. As a gross hack, enable pipe A
9931          * by enabling the load detect pipe once. */
9932         list_for_each_entry(connector,
9933                             &dev->mode_config.connector_list,
9934                             base.head) {
9935                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9936                         crt = &connector->base;
9937                         break;
9938                 }
9939         }
9940
9941         if (!crt)
9942                 return;
9943
9944         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9945                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9946
9947
9948 }
9949
9950 static bool
9951 intel_check_plane_mapping(struct intel_crtc *crtc)
9952 {
9953         struct drm_device *dev = crtc->base.dev;
9954         struct drm_i915_private *dev_priv = dev->dev_private;
9955         u32 reg, val;
9956
9957         if (INTEL_INFO(dev)->num_pipes == 1)
9958                 return true;
9959
9960         reg = DSPCNTR(!crtc->plane);
9961         val = I915_READ(reg);
9962
9963         if ((val & DISPLAY_PLANE_ENABLE) &&
9964             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9965                 return false;
9966
9967         return true;
9968 }
9969
9970 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9971 {
9972         struct drm_device *dev = crtc->base.dev;
9973         struct drm_i915_private *dev_priv = dev->dev_private;
9974         u32 reg;
9975
9976         /* Clear any frame start delays used for debugging left by the BIOS */
9977         reg = PIPECONF(crtc->config.cpu_transcoder);
9978         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9979
9980         /* We need to sanitize the plane -> pipe mapping first because this will
9981          * disable the crtc (and hence change the state) if it is wrong. Note
9982          * that gen4+ has a fixed plane -> pipe mapping.  */
9983         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9984                 struct intel_connector *connector;
9985                 bool plane;
9986
9987                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9988                               crtc->base.base.id);
9989
9990                 /* Pipe has the wrong plane attached and the plane is active.
9991                  * Temporarily change the plane mapping and disable everything
9992                  * ...  */
9993                 plane = crtc->plane;
9994                 crtc->plane = !plane;
9995                 dev_priv->display.crtc_disable(&crtc->base);
9996                 crtc->plane = plane;
9997
9998                 /* ... and break all links. */
9999                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10000                                     base.head) {
10001                         if (connector->encoder->base.crtc != &crtc->base)
10002                                 continue;
10003
10004                         intel_connector_break_all_links(connector);
10005                 }
10006
10007                 WARN_ON(crtc->active);
10008                 crtc->base.enabled = false;
10009         }
10010
10011         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10012             crtc->pipe == PIPE_A && !crtc->active) {
10013                 /* BIOS forgot to enable pipe A, this mostly happens after
10014                  * resume. Force-enable the pipe to fix this, the update_dpms
10015                  * call below we restore the pipe to the right state, but leave
10016                  * the required bits on. */
10017                 intel_enable_pipe_a(dev);
10018         }
10019
10020         /* Adjust the state of the output pipe according to whether we
10021          * have active connectors/encoders. */
10022         intel_crtc_update_dpms(&crtc->base);
10023
10024         if (crtc->active != crtc->base.enabled) {
10025                 struct intel_encoder *encoder;
10026
10027                 /* This can happen either due to bugs in the get_hw_state
10028                  * functions or because the pipe is force-enabled due to the
10029                  * pipe A quirk. */
10030                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10031                               crtc->base.base.id,
10032                               crtc->base.enabled ? "enabled" : "disabled",
10033                               crtc->active ? "enabled" : "disabled");
10034
10035                 crtc->base.enabled = crtc->active;
10036
10037                 /* Because we only establish the connector -> encoder ->
10038                  * crtc links if something is active, this means the
10039                  * crtc is now deactivated. Break the links. connector
10040                  * -> encoder links are only establish when things are
10041                  *  actually up, hence no need to break them. */
10042                 WARN_ON(crtc->active);
10043
10044                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10045                         WARN_ON(encoder->connectors_active);
10046                         encoder->base.crtc = NULL;
10047                 }
10048         }
10049 }
10050
10051 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10052 {
10053         struct intel_connector *connector;
10054         struct drm_device *dev = encoder->base.dev;
10055
10056         /* We need to check both for a crtc link (meaning that the
10057          * encoder is active and trying to read from a pipe) and the
10058          * pipe itself being active. */
10059         bool has_active_crtc = encoder->base.crtc &&
10060                 to_intel_crtc(encoder->base.crtc)->active;
10061
10062         if (encoder->connectors_active && !has_active_crtc) {
10063                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10064                               encoder->base.base.id,
10065                               drm_get_encoder_name(&encoder->base));
10066
10067                 /* Connector is active, but has no active pipe. This is
10068                  * fallout from our resume register restoring. Disable
10069                  * the encoder manually again. */
10070                 if (encoder->base.crtc) {
10071                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10072                                       encoder->base.base.id,
10073                                       drm_get_encoder_name(&encoder->base));
10074                         encoder->disable(encoder);
10075                 }
10076
10077                 /* Inconsistent output/port/pipe state happens presumably due to
10078                  * a bug in one of the get_hw_state functions. Or someplace else
10079                  * in our code, like the register restore mess on resume. Clamp
10080                  * things to off as a safer default. */
10081                 list_for_each_entry(connector,
10082                                     &dev->mode_config.connector_list,
10083                                     base.head) {
10084                         if (connector->encoder != encoder)
10085                                 continue;
10086
10087                         intel_connector_break_all_links(connector);
10088                 }
10089         }
10090         /* Enabled encoders without active connectors will be fixed in
10091          * the crtc fixup. */
10092 }
10093
10094 void i915_redisable_vga(struct drm_device *dev)
10095 {
10096         struct drm_i915_private *dev_priv = dev->dev_private;
10097         u32 vga_reg = i915_vgacntrl_reg(dev);
10098
10099         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10100                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10101                 i915_disable_vga(dev);
10102         }
10103 }
10104
10105 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10106 {
10107         struct drm_i915_private *dev_priv = dev->dev_private;
10108         enum pipe pipe;
10109         struct intel_crtc *crtc;
10110         struct intel_encoder *encoder;
10111         struct intel_connector *connector;
10112         int i;
10113
10114         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10115                             base.head) {
10116                 memset(&crtc->config, 0, sizeof(crtc->config));
10117
10118                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10119                                                                  &crtc->config);
10120
10121                 crtc->base.enabled = crtc->active;
10122
10123                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10124                               crtc->base.base.id,
10125                               crtc->active ? "enabled" : "disabled");
10126         }
10127
10128         /* FIXME: Smash this into the new shared dpll infrastructure. */
10129         if (HAS_DDI(dev))
10130                 intel_ddi_setup_hw_pll_state(dev);
10131
10132         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10133                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10134
10135                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10136                 pll->active = 0;
10137                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10138                                     base.head) {
10139                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10140                                 pll->active++;
10141                 }
10142                 pll->refcount = pll->active;
10143
10144                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10145                               pll->name, pll->refcount, pll->on);
10146         }
10147
10148         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10149                             base.head) {
10150                 pipe = 0;
10151
10152                 if (encoder->get_hw_state(encoder, &pipe)) {
10153                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10154                         encoder->base.crtc = &crtc->base;
10155                         if (encoder->get_config)
10156                                 encoder->get_config(encoder, &crtc->config);
10157                 } else {
10158                         encoder->base.crtc = NULL;
10159                 }
10160
10161                 encoder->connectors_active = false;
10162                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10163                               encoder->base.base.id,
10164                               drm_get_encoder_name(&encoder->base),
10165                               encoder->base.crtc ? "enabled" : "disabled",
10166                               pipe);
10167         }
10168
10169         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10170                             base.head) {
10171                 if (!crtc->active)
10172                         continue;
10173                 if (dev_priv->display.get_clock)
10174                         dev_priv->display.get_clock(crtc,
10175                                                     &crtc->config);
10176         }
10177
10178         list_for_each_entry(connector, &dev->mode_config.connector_list,
10179                             base.head) {
10180                 if (connector->get_hw_state(connector)) {
10181                         connector->base.dpms = DRM_MODE_DPMS_ON;
10182                         connector->encoder->connectors_active = true;
10183                         connector->base.encoder = &connector->encoder->base;
10184                 } else {
10185                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10186                         connector->base.encoder = NULL;
10187                 }
10188                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10189                               connector->base.base.id,
10190                               drm_get_connector_name(&connector->base),
10191                               connector->base.encoder ? "enabled" : "disabled");
10192         }
10193 }
10194
10195 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10196  * and i915 state tracking structures. */
10197 void intel_modeset_setup_hw_state(struct drm_device *dev,
10198                                   bool force_restore)
10199 {
10200         struct drm_i915_private *dev_priv = dev->dev_private;
10201         enum pipe pipe;
10202         struct drm_plane *plane;
10203         struct intel_crtc *crtc;
10204         struct intel_encoder *encoder;
10205         int i;
10206
10207         intel_modeset_readout_hw_state(dev);
10208
10209         /*
10210          * Now that we have the config, copy it to each CRTC struct
10211          * Note that this could go away if we move to using crtc_config
10212          * checking everywhere.
10213          */
10214         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10215                             base.head) {
10216                 if (crtc->active && i915_fastboot) {
10217                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10218
10219                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10220                                       crtc->base.base.id);
10221                         drm_mode_debug_printmodeline(&crtc->base.mode);
10222                 }
10223         }
10224
10225         /* HW state is read out, now we need to sanitize this mess. */
10226         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10227                             base.head) {
10228                 intel_sanitize_encoder(encoder);
10229         }
10230
10231         for_each_pipe(pipe) {
10232                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10233                 intel_sanitize_crtc(crtc);
10234                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10235         }
10236
10237         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10238                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10239
10240                 if (!pll->on || pll->active)
10241                         continue;
10242
10243                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10244
10245                 pll->disable(dev_priv, pll);
10246                 pll->on = false;
10247         }
10248
10249         if (force_restore) {
10250                 /*
10251                  * We need to use raw interfaces for restoring state to avoid
10252                  * checking (bogus) intermediate states.
10253                  */
10254                 for_each_pipe(pipe) {
10255                         struct drm_crtc *crtc =
10256                                 dev_priv->pipe_to_crtc_mapping[pipe];
10257
10258                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10259                                          crtc->fb);
10260                 }
10261                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10262                         intel_plane_restore(plane);
10263
10264                 i915_redisable_vga(dev);
10265         } else {
10266                 intel_modeset_update_staged_output_state(dev);
10267         }
10268
10269         intel_modeset_check_state(dev);
10270
10271         drm_mode_config_reset(dev);
10272 }
10273
10274 void intel_modeset_gem_init(struct drm_device *dev)
10275 {
10276         intel_modeset_init_hw(dev);
10277
10278         intel_setup_overlay(dev);
10279
10280         intel_modeset_setup_hw_state(dev, false);
10281 }
10282
10283 void intel_modeset_cleanup(struct drm_device *dev)
10284 {
10285         struct drm_i915_private *dev_priv = dev->dev_private;
10286         struct drm_crtc *crtc;
10287         struct intel_crtc *intel_crtc;
10288
10289         /*
10290          * Interrupts and polling as the first thing to avoid creating havoc.
10291          * Too much stuff here (turning of rps, connectors, ...) would
10292          * experience fancy races otherwise.
10293          */
10294         drm_irq_uninstall(dev);
10295         cancel_work_sync(&dev_priv->hotplug_work);
10296         /*
10297          * Due to the hpd irq storm handling the hotplug work can re-arm the
10298          * poll handlers. Hence disable polling after hpd handling is shut down.
10299          */
10300         drm_kms_helper_poll_fini(dev);
10301
10302         mutex_lock(&dev->struct_mutex);
10303
10304         intel_unregister_dsm_handler();
10305
10306         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10307                 /* Skip inactive CRTCs */
10308                 if (!crtc->fb)
10309                         continue;
10310
10311                 intel_crtc = to_intel_crtc(crtc);
10312                 intel_increase_pllclock(crtc);
10313         }
10314
10315         intel_disable_fbc(dev);
10316
10317         intel_disable_gt_powersave(dev);
10318
10319         ironlake_teardown_rc6(dev);
10320
10321         mutex_unlock(&dev->struct_mutex);
10322
10323         /* flush any delayed tasks or pending work */
10324         flush_scheduled_work();
10325
10326         /* destroy backlight, if any, before the connectors */
10327         intel_panel_destroy_backlight(dev);
10328
10329         drm_mode_config_cleanup(dev);
10330
10331         intel_cleanup_overlay(dev);
10332 }
10333
10334 /*
10335  * Return which encoder is currently attached for connector.
10336  */
10337 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10338 {
10339         return &intel_attached_encoder(connector)->base;
10340 }
10341
10342 void intel_connector_attach_encoder(struct intel_connector *connector,
10343                                     struct intel_encoder *encoder)
10344 {
10345         connector->encoder = encoder;
10346         drm_mode_connector_attach_encoder(&connector->base,
10347                                           &encoder->base);
10348 }
10349
10350 /*
10351  * set vga decode state - true == enable VGA decode
10352  */
10353 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10354 {
10355         struct drm_i915_private *dev_priv = dev->dev_private;
10356         u16 gmch_ctrl;
10357
10358         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10359         if (state)
10360                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10361         else
10362                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10363         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10364         return 0;
10365 }
10366
10367 struct intel_display_error_state {
10368
10369         u32 power_well_driver;
10370
10371         struct intel_cursor_error_state {
10372                 u32 control;
10373                 u32 position;
10374                 u32 base;
10375                 u32 size;
10376         } cursor[I915_MAX_PIPES];
10377
10378         struct intel_pipe_error_state {
10379                 enum transcoder cpu_transcoder;
10380                 u32 conf;
10381                 u32 source;
10382
10383                 u32 htotal;
10384                 u32 hblank;
10385                 u32 hsync;
10386                 u32 vtotal;
10387                 u32 vblank;
10388                 u32 vsync;
10389         } pipe[I915_MAX_PIPES];
10390
10391         struct intel_plane_error_state {
10392                 u32 control;
10393                 u32 stride;
10394                 u32 size;
10395                 u32 pos;
10396                 u32 addr;
10397                 u32 surface;
10398                 u32 tile_offset;
10399         } plane[I915_MAX_PIPES];
10400 };
10401
10402 struct intel_display_error_state *
10403 intel_display_capture_error_state(struct drm_device *dev)
10404 {
10405         drm_i915_private_t *dev_priv = dev->dev_private;
10406         struct intel_display_error_state *error;
10407         enum transcoder cpu_transcoder;
10408         int i;
10409
10410         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10411         if (error == NULL)
10412                 return NULL;
10413
10414         if (HAS_POWER_WELL(dev))
10415                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10416
10417         for_each_pipe(i) {
10418                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10419                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10420
10421                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10422                         error->cursor[i].control = I915_READ(CURCNTR(i));
10423                         error->cursor[i].position = I915_READ(CURPOS(i));
10424                         error->cursor[i].base = I915_READ(CURBASE(i));
10425                 } else {
10426                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10427                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10428                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10429                 }
10430
10431                 error->plane[i].control = I915_READ(DSPCNTR(i));
10432                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10433                 if (INTEL_INFO(dev)->gen <= 3) {
10434                         error->plane[i].size = I915_READ(DSPSIZE(i));
10435                         error->plane[i].pos = I915_READ(DSPPOS(i));
10436                 }
10437                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10438                         error->plane[i].addr = I915_READ(DSPADDR(i));
10439                 if (INTEL_INFO(dev)->gen >= 4) {
10440                         error->plane[i].surface = I915_READ(DSPSURF(i));
10441                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10442                 }
10443
10444                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10445                 error->pipe[i].source = I915_READ(PIPESRC(i));
10446                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10447                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10448                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10449                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10450                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10451                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10452         }
10453
10454         /* In the code above we read the registers without checking if the power
10455          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10456          * prevent the next I915_WRITE from detecting it and printing an error
10457          * message. */
10458         intel_uncore_clear_errors(dev);
10459
10460         return error;
10461 }
10462
10463 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10464
10465 void
10466 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10467                                 struct drm_device *dev,
10468                                 struct intel_display_error_state *error)
10469 {
10470         int i;
10471
10472         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10473         if (HAS_POWER_WELL(dev))
10474                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10475                            error->power_well_driver);
10476         for_each_pipe(i) {
10477                 err_printf(m, "Pipe [%d]:\n", i);
10478                 err_printf(m, "  CPU transcoder: %c\n",
10479                            transcoder_name(error->pipe[i].cpu_transcoder));
10480                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10481                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10482                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10483                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10484                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10485                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10486                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10487                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10488
10489                 err_printf(m, "Plane [%d]:\n", i);
10490                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10491                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10492                 if (INTEL_INFO(dev)->gen <= 3) {
10493                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10494                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10495                 }
10496                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10497                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10498                 if (INTEL_INFO(dev)->gen >= 4) {
10499                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10500                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10501                 }
10502
10503                 err_printf(m, "Cursor [%d]:\n", i);
10504                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10505                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10506                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10507         }
10508 }