drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_increase_pllclock(struct drm_device *dev,
  77                                     enum pipe pipe);
  78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  79
  80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  81                                 struct intel_crtc_config *pipe_config);
  82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  83                                    struct intel_crtc_config *pipe_config);
  84
  85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  86                           int x, int y, struct drm_framebuffer *old_fb);
  87 static int intel_framebuffer_init(struct drm_device *dev,
  88                                   struct intel_framebuffer *ifb,
  89                                   struct drm_mode_fb_cmd2 *mode_cmd,
  90                                   struct drm_i915_gem_object *obj);
  91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  94                                          struct intel_link_m_n *m_n,
  95                                          struct intel_link_m_n *m2_n2);
  96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  99 static void vlv_prepare_pll(struct intel_crtc *crtc);
 100 static void chv_prepare_pll(struct intel_crtc *crtc);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 412 {
 413         struct drm_device *dev = crtc->dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, crtc, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 424                                                 int refclk)
 425 {
 426         struct drm_device *dev = crtc->dev;
 427         const intel_limit_t *limit;
 428
 429         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 430                 if (intel_is_dual_link_lvds(dev)) {
 431                         if (refclk == 100000)
 432                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 433                         else
 434                                 limit = &intel_limits_ironlake_dual_lvds;
 435                 } else {
 436                         if (refclk == 100000)
 437                                 limit = &intel_limits_ironlake_single_lvds_100m;
 438                         else
 439                                 limit = &intel_limits_ironlake_single_lvds;
 440                 }
 441         } else
 442                 limit = &intel_limits_ironlake_dac;
 443
 444         return limit;
 445 }
 446
 447 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 448 {
 449         struct drm_device *dev = crtc->dev;
 450         const intel_limit_t *limit;
 451
 452         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 453                 if (intel_is_dual_link_lvds(dev))
 454                         limit = &intel_limits_g4x_dual_channel_lvds;
 455                 else
 456                         limit = &intel_limits_g4x_single_channel_lvds;
 457         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 458                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 459                 limit = &intel_limits_g4x_hdmi;
 460         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 461                 limit = &intel_limits_g4x_sdvo;
 462         } else /* The option is for other outputs */
 463                 limit = &intel_limits_i9xx_sdvo;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 469 {
 470         struct drm_device *dev = crtc->dev;
 471         const intel_limit_t *limit;
 472
 473         if (HAS_PCH_SPLIT(dev))
 474                 limit = intel_ironlake_limit(crtc, refclk);
 475         else if (IS_G4X(dev)) {
 476                 limit = intel_g4x_limit(crtc);
 477         } else if (IS_PINEVIEW(dev)) {
 478                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 479                         limit = &intel_limits_pineview_lvds;
 480                 else
 481                         limit = &intel_limits_pineview_sdvo;
 482         } else if (IS_CHERRYVIEW(dev)) {
 483                 limit = &intel_limits_chv;
 484         } else if (IS_VALLEYVIEW(dev)) {
 485                 limit = &intel_limits_vlv;
 486         } else if (!IS_GEN2(dev)) {
 487                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 488                         limit = &intel_limits_i9xx_lvds;
 489                 else
 490                         limit = &intel_limits_i9xx_sdvo;
 491         } else {
 492                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 493                         limit = &intel_limits_i8xx_lvds;
 494                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 495                         limit = &intel_limits_i8xx_dvo;
 496                 else
 497                         limit = &intel_limits_i8xx_dac;
 498         }
 499         return limit;
 500 }
 501
 502 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 503 static void pineview_clock(int refclk, intel_clock_t *clock)
 504 {
 505         clock->m = clock->m2 + 2;
 506         clock->p = clock->p1 * clock->p2;
 507         if (WARN_ON(clock->n == 0 || clock->p == 0))
 508                 return;
 509         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 510         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 511 }
 512
 513 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 514 {
 515         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 516 }
 517
 518 static void i9xx_clock(int refclk, intel_clock_t *clock)
 519 {
 520         clock->m = i9xx_dpll_compute_m(clock);
 521         clock->p = clock->p1 * clock->p2;
 522         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 523                 return;
 524         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 525         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 526 }
 527
 528 static void chv_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m1 * clock->m2;
 531         clock->p = clock->p1 * clock->p2;
 532         if (WARN_ON(clock->n == 0 || clock->p == 0))
 533                 return;
 534         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 535                         clock->n << 22);
 536         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 537 }
 538
 539 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 540 /**
 541  * Returns whether the given set of divisors are valid for a given refclk with
 542  * the given connectors.
 543  */
 544
 545 static bool intel_PLL_is_valid(struct drm_device *dev,
 546                                const intel_limit_t *limit,
 547                                const intel_clock_t *clock)
 548 {
 549         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 550                 INTELPllInvalid("n out of range\n");
 551         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 552                 INTELPllInvalid("p1 out of range\n");
 553         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 554                 INTELPllInvalid("m2 out of range\n");
 555         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 556                 INTELPllInvalid("m1 out of range\n");
 557
 558         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 559                 if (clock->m1 <= clock->m2)
 560                         INTELPllInvalid("m1 <= m2\n");
 561
 562         if (!IS_VALLEYVIEW(dev)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static bool
 581 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 582                     int target, int refclk, intel_clock_t *match_clock,
 583                     intel_clock_t *best_clock)
 584 {
 585         struct drm_device *dev = crtc->dev;
 586         intel_clock_t clock;
 587         int err = target;
 588
 589         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 590                 /*
 591                  * For LVDS just rely on its current settings for dual-channel.
 592                  * We haven't figured out how to reliably set up different
 593                  * single/dual channel state, if we even can.
 594                  */
 595                 if (intel_is_dual_link_lvds(dev))
 596                         clock.p2 = limit->p2.p2_fast;
 597                 else
 598                         clock.p2 = limit->p2.p2_slow;
 599         } else {
 600                 if (target < limit->p2.dot_limit)
 601                         clock.p2 = limit->p2.p2_slow;
 602                 else
 603                         clock.p2 = limit->p2.p2_fast;
 604         }
 605
 606         memset(best_clock, 0, sizeof(*best_clock));
 607
 608         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 609              clock.m1++) {
 610                 for (clock.m2 = limit->m2.min;
 611                      clock.m2 <= limit->m2.max; clock.m2++) {
 612                         if (clock.m2 >= clock.m1)
 613                                 break;
 614                         for (clock.n = limit->n.min;
 615                              clock.n <= limit->n.max; clock.n++) {
 616                                 for (clock.p1 = limit->p1.min;
 617                                         clock.p1 <= limit->p1.max; clock.p1++) {
 618                                         int this_err;
 619
 620                                         i9xx_clock(refclk, &clock);
 621                                         if (!intel_PLL_is_valid(dev, limit,
 622                                                                 &clock))
 623                                                 continue;
 624                                         if (match_clock &&
 625                                             clock.p != match_clock->p)
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err) {
 630                                                 *best_clock = clock;
 631                                                 err = this_err;
 632                                         }
 633                                 }
 634                         }
 635                 }
 636         }
 637
 638         return (err != target);
 639 }
 640
 641 static bool
 642 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                    int target, int refclk, intel_clock_t *match_clock,
 644                    intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648         int err = target;
 649
 650         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 651                 /*
 652                  * For LVDS just rely on its current settings for dual-channel.
 653                  * We haven't figured out how to reliably set up different
 654                  * single/dual channel state, if we even can.
 655                  */
 656                 if (intel_is_dual_link_lvds(dev))
 657                         clock.p2 = limit->p2.p2_fast;
 658                 else
 659                         clock.p2 = limit->p2.p2_slow;
 660         } else {
 661                 if (target < limit->p2.dot_limit)
 662                         clock.p2 = limit->p2.p2_slow;
 663                 else
 664                         clock.p2 = limit->p2.p2_fast;
 665         }
 666
 667         memset(best_clock, 0, sizeof(*best_clock));
 668
 669         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 670              clock.m1++) {
 671                 for (clock.m2 = limit->m2.min;
 672                      clock.m2 <= limit->m2.max; clock.m2++) {
 673                         for (clock.n = limit->n.min;
 674                              clock.n <= limit->n.max; clock.n++) {
 675                                 for (clock.p1 = limit->p1.min;
 676                                         clock.p1 <= limit->p1.max; clock.p1++) {
 677                                         int this_err;
 678
 679                                         pineview_clock(refclk, &clock);
 680                                         if (!intel_PLL_is_valid(dev, limit,
 681                                                                 &clock))
 682                                                 continue;
 683                                         if (match_clock &&
 684                                             clock.p != match_clock->p)
 685                                                 continue;
 686
 687                                         this_err = abs(clock.dot - target);
 688                                         if (this_err < err) {
 689                                                 *best_clock = clock;
 690                                                 err = this_err;
 691                                         }
 692                                 }
 693                         }
 694                 }
 695         }
 696
 697         return (err != target);
 698 }
 699
 700 static bool
 701 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 702                    int target, int refclk, intel_clock_t *match_clock,
 703                    intel_clock_t *best_clock)
 704 {
 705         struct drm_device *dev = crtc->dev;
 706         intel_clock_t clock;
 707         int max_n;
 708         bool found;
 709         /* approximately equals target * 0.00585 */
 710         int err_most = (target >> 8) + (target >> 9);
 711         found = false;
 712
 713         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 714                 if (intel_is_dual_link_lvds(dev))
 715                         clock.p2 = limit->p2.p2_fast;
 716                 else
 717                         clock.p2 = limit->p2.p2_slow;
 718         } else {
 719                 if (target < limit->p2.dot_limit)
 720                         clock.p2 = limit->p2.p2_slow;
 721                 else
 722                         clock.p2 = limit->p2.p2_fast;
 723         }
 724
 725         memset(best_clock, 0, sizeof(*best_clock));
 726         max_n = limit->n.max;
 727         /* based on hardware requirement, prefer smaller n to precision */
 728         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 729                 /* based on hardware requirement, prefere larger m1,m2 */
 730                 for (clock.m1 = limit->m1.max;
 731                      clock.m1 >= limit->m1.min; clock.m1--) {
 732                         for (clock.m2 = limit->m2.max;
 733                              clock.m2 >= limit->m2.min; clock.m2--) {
 734                                 for (clock.p1 = limit->p1.max;
 735                                      clock.p1 >= limit->p1.min; clock.p1--) {
 736                                         int this_err;
 737
 738                                         i9xx_clock(refclk, &clock);
 739                                         if (!intel_PLL_is_valid(dev, limit,
 740                                                                 &clock))
 741                                                 continue;
 742
 743                                         this_err = abs(clock.dot - target);
 744                                         if (this_err < err_most) {
 745                                                 *best_clock = clock;
 746                                                 err_most = this_err;
 747                                                 max_n = clock.n;
 748                                                 found = true;
 749                                         }
 750                                 }
 751                         }
 752                 }
 753         }
 754         return found;
 755 }
 756
 757 static bool
 758 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 759                    int target, int refclk, intel_clock_t *match_clock,
 760                    intel_clock_t *best_clock)
 761 {
 762         struct drm_device *dev = crtc->dev;
 763         intel_clock_t clock;
 764         unsigned int bestppm = 1000000;
 765         /* min update 19.2 MHz */
 766         int max_n = min(limit->n.max, refclk / 19200);
 767         bool found = false;
 768
 769         target *= 5; /* fast clock */
 770
 771         memset(best_clock, 0, sizeof(*best_clock));
 772
 773         /* based on hardware requirement, prefer smaller n to precision */
 774         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 775                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 776                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 777                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 778                                 clock.p = clock.p1 * clock.p2;
 779                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 780                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 781                                         unsigned int ppm, diff;
 782
 783                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 784                                                                      refclk * clock.m1);
 785
 786                                         vlv_clock(refclk, &clock);
 787
 788                                         if (!intel_PLL_is_valid(dev, limit,
 789                                                                 &clock))
 790                                                 continue;
 791
 792                                         diff = abs(clock.dot - target);
 793                                         ppm = div_u64(1000000ULL * diff, target);
 794
 795                                         if (ppm < 100 && clock.p > best_clock->p) {
 796                                                 bestppm = 0;
 797                                                 *best_clock = clock;
 798                                                 found = true;
 799                                         }
 800
 801                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 802                                                 bestppm = ppm;
 803                                                 *best_clock = clock;
 804                                                 found = true;
 805                                         }
 806                                 }
 807                         }
 808                 }
 809         }
 810
 811         return found;
 812 }
 813
 814 static bool
 815 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc->dev;
 820         intel_clock_t clock;
 821         uint64_t m2;
 822         int found = false;
 823
 824         memset(best_clock, 0, sizeof(*best_clock));
 825
 826         /*
 827          * Based on hardware doc, the n always set to 1, and m1 always
 828          * set to 2.  If requires to support 200Mhz refclk, we need to
 829          * revisit this because n may not 1 anymore.
 830          */
 831         clock.n = 1, clock.m1 = 2;
 832         target *= 5;    /* fast clock */
 833
 834         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 835                 for (clock.p2 = limit->p2.p2_fast;
 836                                 clock.p2 >= limit->p2.p2_slow;
 837                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 838
 839                         clock.p = clock.p1 * clock.p2;
 840
 841                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 842                                         clock.n) << 22, refclk * clock.m1);
 843
 844                         if (m2 > INT_MAX/clock.m1)
 845                                 continue;
 846
 847                         clock.m2 = m2;
 848
 849                         chv_clock(refclk, &clock);
 850
 851                         if (!intel_PLL_is_valid(dev, limit, &clock))
 852                                 continue;
 853
 854                         /* based on hardware requirement, prefer bigger p
 855                          */
 856                         if (clock.p > best_clock->p) {
 857                                 *best_clock = clock;
 858                                 found = true;
 859                         }
 860                 }
 861         }
 862
 863         return found;
 864 }
 865
 866 bool intel_crtc_active(struct drm_crtc *crtc)
 867 {
 868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 869
 870         /* Be paranoid as we can arrive here with only partial
 871          * state retrieved from the hardware during setup.
 872          *
 873          * We can ditch the adjusted_mode.crtc_clock check as soon
 874          * as Haswell has gained clock readout/fastboot support.
 875          *
 876          * We can ditch the crtc->primary->fb check as soon as we can
 877          * properly reconstruct framebuffers.
 878          */
 879         return intel_crtc->active && crtc->primary->fb &&
 880                 intel_crtc->config.adjusted_mode.crtc_clock;
 881 }
 882
 883 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 884                                              enum pipe pipe)
 885 {
 886         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 888
 889         return intel_crtc->config.cpu_transcoder;
 890 }
 891
 892 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 893 {
 894         struct drm_i915_private *dev_priv = dev->dev_private;
 895         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 896
 897         frame = I915_READ(frame_reg);
 898
 899         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 900                 WARN(1, "vblank wait on pipe %c timed out\n",
 901                      pipe_name(pipe));
 902 }
 903
 904 /**
 905  * intel_wait_for_vblank - wait for vblank on a given pipe
 906  * @dev: drm device
 907  * @pipe: pipe to wait for
 908  *
 909  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 910  * mode setting code.
 911  */
 912 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 913 {
 914         struct drm_i915_private *dev_priv = dev->dev_private;
 915         int pipestat_reg = PIPESTAT(pipe);
 916
 917         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 918                 g4x_wait_for_vblank(dev, pipe);
 919                 return;
 920         }
 921
 922         /* Clear existing vblank status. Note this will clear any other
 923          * sticky status fields as well.
 924          *
 925          * This races with i915_driver_irq_handler() with the result
 926          * that either function could miss a vblank event.  Here it is not
 927          * fatal, as we will either wait upon the next vblank interrupt or
 928          * timeout.  Generally speaking intel_wait_for_vblank() is only
 929          * called during modeset at which time the GPU should be idle and
 930          * should *not* be performing page flips and thus not waiting on
 931          * vblanks...
 932          * Currently, the result of us stealing a vblank from the irq
 933          * handler is that a single frame will be skipped during swapbuffers.
 934          */
 935         I915_WRITE(pipestat_reg,
 936                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 937
 938         /* Wait for vblank interrupt bit to set */
 939         if (wait_for(I915_READ(pipestat_reg) &
 940                      PIPE_VBLANK_INTERRUPT_STATUS,
 941                      50))
 942                 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
 943                               pipe_name(pipe));
 944 }
 945
 946 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 947 {
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         u32 reg = PIPEDSL(pipe);
 950         u32 line1, line2;
 951         u32 line_mask;
 952
 953         if (IS_GEN2(dev))
 954                 line_mask = DSL_LINEMASK_GEN2;
 955         else
 956                 line_mask = DSL_LINEMASK_GEN3;
 957
 958         line1 = I915_READ(reg) & line_mask;
 959         mdelay(5);
 960         line2 = I915_READ(reg) & line_mask;
 961
 962         return line1 == line2;
 963 }
 964
 965 /*
 966  * intel_wait_for_pipe_off - wait for pipe to turn off
 967  * @crtc: crtc whose pipe to wait for
 968  *
 969  * After disabling a pipe, we can't wait for vblank in the usual way,
 970  * spinning on the vblank interrupt status bit, since we won't actually
 971  * see an interrupt when the pipe is disabled.
 972  *
 973  * On Gen4 and above:
 974  *   wait for the pipe register state bit to turn off
 975  *
 976  * Otherwise:
 977  *   wait for the display line value to settle (it usually
 978  *   ends up stopping at the start of the next frame).
 979  *
 980  */
 981 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 982 {
 983         struct drm_device *dev = crtc->base.dev;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 986         enum pipe pipe = crtc->pipe;
 987
 988         if (INTEL_INFO(dev)->gen >= 4) {
 989                 int reg = PIPECONF(cpu_transcoder);
 990
 991                 /* Wait for the Pipe State to go off */
 992                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 993                              100))
 994                         WARN(1, "pipe_off wait timed out\n");
 995         } else {
 996                 /* Wait for the display line to settle */
 997                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 998                         WARN(1, "pipe_off wait timed out\n");
 999         }
1000 }
1001
1002 /*
1003  * ibx_digital_port_connected - is the specified port connected?
1004  * @dev_priv: i915 private structure
1005  * @port: the port to test
1006  *
1007  * Returns true if @port is connected, false otherwise.
1008  */
1009 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010                                 struct intel_digital_port *port)
1011 {
1012         u32 bit;
1013
1014         if (HAS_PCH_IBX(dev_priv->dev)) {
1015                 switch (port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         } else {
1029                 switch (port->port) {
1030                 case PORT_B:
1031                         bit = SDE_PORTB_HOTPLUG_CPT;
1032                         break;
1033                 case PORT_C:
1034                         bit = SDE_PORTC_HOTPLUG_CPT;
1035                         break;
1036                 case PORT_D:
1037                         bit = SDE_PORTD_HOTPLUG_CPT;
1038                         break;
1039                 default:
1040                         return true;
1041                 }
1042         }
1043
1044         return I915_READ(SDEISR) & bit;
1045 }
1046
1047 static const char *state_string(bool enabled)
1048 {
1049         return enabled ? "on" : "off";
1050 }
1051
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054                 enum pipe pipe, bool state)
1055 {
1056         int reg;
1057         u32 val;
1058         bool cur_state;
1059
1060         reg = DPLL(pipe);
1061         val = I915_READ(reg);
1062         cur_state = !!(val & DPLL_VCO_ENABLE);
1063         WARN(cur_state != state,
1064              "PLL state assertion failure (expected %s, current %s)\n",
1065              state_string(state), state_string(cur_state));
1066 }
1067
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1070 {
1071         u32 val;
1072         bool cur_state;
1073
1074         mutex_lock(&dev_priv->dpio_lock);
1075         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076         mutex_unlock(&dev_priv->dpio_lock);
1077
1078         cur_state = val & DSI_PLL_VCO_EN;
1079         WARN(cur_state != state,
1080              "DSI PLL state assertion failure (expected %s, current %s)\n",
1081              state_string(state), state_string(cur_state));
1082 }
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1085
1086 struct intel_shared_dpll *
1087 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1088 {
1089         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1090
1091         if (crtc->config.shared_dpll < 0)
1092                 return NULL;
1093
1094         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1095 }
1096
1097 /* For ILK+ */
1098 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099                         struct intel_shared_dpll *pll,
1100                         bool state)
1101 {
1102         bool cur_state;
1103         struct intel_dpll_hw_state hw_state;
1104
1105         if (WARN (!pll,
1106                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1107                 return;
1108
1109         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110         WARN(cur_state != state,
1111              "%s assertion failure (expected %s, current %s)\n",
1112              pll->name, state_string(state), state_string(cur_state));
1113 }
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116                           enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123
1124         if (HAS_DDI(dev_priv->dev)) {
1125                 /* DDI does not have a specific FDI_TX register */
1126                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129         } else {
1130                 reg = FDI_TX_CTL(pipe);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & FDI_TX_ENABLE);
1133         }
1134         WARN(cur_state != state,
1135              "FDI TX state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142                           enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX state assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159                                       enum pipe pipe)
1160 {
1161         int reg;
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv->dev))
1170                 return;
1171
1172         reg = FDI_TX_CTL(pipe);
1173         val = I915_READ(reg);
1174         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183
1184         reg = FDI_RX_CTL(pipe);
1185         val = I915_READ(reg);
1186         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187         WARN(cur_state != state,
1188              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189              state_string(state), state_string(cur_state));
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         struct drm_device *dev = dev_priv->dev;
1196         int pp_reg;
1197         u32 val;
1198         enum pipe panel_pipe = PIPE_A;
1199         bool locked = true;
1200
1201         if (WARN_ON(HAS_DDI(dev)))
1202                 return;
1203
1204         if (HAS_PCH_SPLIT(dev)) {
1205                 u32 port_sel;
1206
1207                 pp_reg = PCH_PP_CONTROL;
1208                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1209
1210                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1211                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1212                         panel_pipe = PIPE_B;
1213                 /* XXX: else fix for eDP */
1214         } else if (IS_VALLEYVIEW(dev)) {
1215                 /* presumably write lock depends on pipe, not port select */
1216                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1217                 panel_pipe = pipe;
1218         } else {
1219                 pp_reg = PP_CONTROL;
1220                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1221                         panel_pipe = PIPE_B;
1222         }
1223
1224         val = I915_READ(pp_reg);
1225         if (!(val & PANEL_POWER_ON) ||
1226             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1227                 locked = false;
1228
1229         WARN(panel_pipe == pipe && locked,
1230              "panel assertion failure, pipe %c regs locked\n",
1231              pipe_name(pipe));
1232 }
1233
1234 static void assert_cursor(struct drm_i915_private *dev_priv,
1235                           enum pipe pipe, bool state)
1236 {
1237         struct drm_device *dev = dev_priv->dev;
1238         bool cur_state;
1239
1240         if (IS_845G(dev) || IS_I865G(dev))
1241                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1242         else
1243                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1244
1245         WARN(cur_state != state,
1246              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1247              pipe_name(pipe), state_string(state), state_string(cur_state));
1248 }
1249 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1250 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1251
1252 void assert_pipe(struct drm_i915_private *dev_priv,
1253                  enum pipe pipe, bool state)
1254 {
1255         int reg;
1256         u32 val;
1257         bool cur_state;
1258         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1259                                                                       pipe);
1260
1261         /* if we need the pipe quirk it must be always on */
1262         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1263             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1264                 state = true;
1265
1266         if (!intel_display_power_enabled(dev_priv,
1267                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1268                 cur_state = false;
1269         } else {
1270                 reg = PIPECONF(cpu_transcoder);
1271                 val = I915_READ(reg);
1272                 cur_state = !!(val & PIPECONF_ENABLE);
1273         }
1274
1275         WARN(cur_state != state,
1276              "pipe %c assertion failure (expected %s, current %s)\n",
1277              pipe_name(pipe), state_string(state), state_string(cur_state));
1278 }
1279
1280 static void assert_plane(struct drm_i915_private *dev_priv,
1281                          enum plane plane, bool state)
1282 {
1283         int reg;
1284         u32 val;
1285         bool cur_state;
1286
1287         reg = DSPCNTR(plane);
1288         val = I915_READ(reg);
1289         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1290         WARN(cur_state != state,
1291              "plane %c assertion failure (expected %s, current %s)\n",
1292              plane_name(plane), state_string(state), state_string(cur_state));
1293 }
1294
1295 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1296 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1297
1298 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1299                                    enum pipe pipe)
1300 {
1301         struct drm_device *dev = dev_priv->dev;
1302         int reg, i;
1303         u32 val;
1304         int cur_pipe;
1305
1306         /* Primary planes are fixed to pipes on gen4+ */
1307         if (INTEL_INFO(dev)->gen >= 4) {
1308                 reg = DSPCNTR(pipe);
1309                 val = I915_READ(reg);
1310                 WARN(val & DISPLAY_PLANE_ENABLE,
1311                      "plane %c assertion failure, should be disabled but not\n",
1312                      plane_name(pipe));
1313                 return;
1314         }
1315
1316         /* Need to check both planes against the pipe */
1317         for_each_pipe(dev_priv, i) {
1318                 reg = DSPCNTR(i);
1319                 val = I915_READ(reg);
1320                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1321                         DISPPLANE_SEL_PIPE_SHIFT;
1322                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1323                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1324                      plane_name(i), pipe_name(pipe));
1325         }
1326 }
1327
1328 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1329                                     enum pipe pipe)
1330 {
1331         struct drm_device *dev = dev_priv->dev;
1332         int reg, sprite;
1333         u32 val;
1334
1335         if (IS_VALLEYVIEW(dev)) {
1336                 for_each_sprite(pipe, sprite) {
1337                         reg = SPCNTR(pipe, sprite);
1338                         val = I915_READ(reg);
1339                         WARN(val & SP_ENABLE,
1340                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341                              sprite_name(pipe, sprite), pipe_name(pipe));
1342                 }
1343         } else if (INTEL_INFO(dev)->gen >= 7) {
1344                 reg = SPRCTL(pipe);
1345                 val = I915_READ(reg);
1346                 WARN(val & SPRITE_ENABLE,
1347                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348                      plane_name(pipe), pipe_name(pipe));
1349         } else if (INTEL_INFO(dev)->gen >= 5) {
1350                 reg = DVSCNTR(pipe);
1351                 val = I915_READ(reg);
1352                 WARN(val & DVS_ENABLE,
1353                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1354                      plane_name(pipe), pipe_name(pipe));
1355         }
1356 }
1357
1358 static void assert_vblank_disabled(struct drm_crtc *crtc)
1359 {
1360         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1361                 drm_crtc_vblank_put(crtc);
1362 }
1363
1364 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1365 {
1366         u32 val;
1367         bool enabled;
1368
1369         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1370
1371         val = I915_READ(PCH_DREF_CONTROL);
1372         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1373                             DREF_SUPERSPREAD_SOURCE_MASK));
1374         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1375 }
1376
1377 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1378                                            enum pipe pipe)
1379 {
1380         int reg;
1381         u32 val;
1382         bool enabled;
1383
1384         reg = PCH_TRANSCONF(pipe);
1385         val = I915_READ(reg);
1386         enabled = !!(val & TRANS_ENABLE);
1387         WARN(enabled,
1388              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1389              pipe_name(pipe));
1390 }
1391
1392 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1393                             enum pipe pipe, u32 port_sel, u32 val)
1394 {
1395         if ((val & DP_PORT_EN) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv->dev)) {
1399                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1400                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1401                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1402                         return false;
1403         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1404                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1405                         return false;
1406         } else {
1407                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1408                         return false;
1409         }
1410         return true;
1411 }
1412
1413 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1414                               enum pipe pipe, u32 val)
1415 {
1416         if ((val & SDVO_ENABLE) == 0)
1417                 return false;
1418
1419         if (HAS_PCH_CPT(dev_priv->dev)) {
1420                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1421                         return false;
1422         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1423                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1424                         return false;
1425         } else {
1426                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1427                         return false;
1428         }
1429         return true;
1430 }
1431
1432 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1433                               enum pipe pipe, u32 val)
1434 {
1435         if ((val & LVDS_PORT_EN) == 0)
1436                 return false;
1437
1438         if (HAS_PCH_CPT(dev_priv->dev)) {
1439                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1440                         return false;
1441         } else {
1442                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1443                         return false;
1444         }
1445         return true;
1446 }
1447
1448 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1449                               enum pipe pipe, u32 val)
1450 {
1451         if ((val & ADPA_DAC_ENABLE) == 0)
1452                 return false;
1453         if (HAS_PCH_CPT(dev_priv->dev)) {
1454                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1455                         return false;
1456         } else {
1457                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1458                         return false;
1459         }
1460         return true;
1461 }
1462
1463 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1464                                    enum pipe pipe, int reg, u32 port_sel)
1465 {
1466         u32 val = I915_READ(reg);
1467         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1468              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1469              reg, pipe_name(pipe));
1470
1471         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1472              && (val & DP_PIPEB_SELECT),
1473              "IBX PCH dp port still using transcoder B\n");
1474 }
1475
1476 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1477                                      enum pipe pipe, int reg)
1478 {
1479         u32 val = I915_READ(reg);
1480         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1481              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1482              reg, pipe_name(pipe));
1483
1484         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1485              && (val & SDVO_PIPE_B_SELECT),
1486              "IBX PCH hdmi port still using transcoder B\n");
1487 }
1488
1489 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1490                                       enum pipe pipe)
1491 {
1492         int reg;
1493         u32 val;
1494
1495         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1496         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1497         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1498
1499         reg = PCH_ADPA;
1500         val = I915_READ(reg);
1501         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1502              "PCH VGA enabled on transcoder %c, should be disabled\n",
1503              pipe_name(pipe));
1504
1505         reg = PCH_LVDS;
1506         val = I915_READ(reg);
1507         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1508              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1509              pipe_name(pipe));
1510
1511         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1512         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1513         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1514 }
1515
1516 static void intel_init_dpio(struct drm_device *dev)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520         if (!IS_VALLEYVIEW(dev))
1521                 return;
1522
1523         /*
1524          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1525          * CHV x1 PHY (DP/HDMI D)
1526          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1527          */
1528         if (IS_CHERRYVIEW(dev)) {
1529                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1530                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1531         } else {
1532                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1533         }
1534 }
1535
1536 static void vlv_enable_pll(struct intel_crtc *crtc)
1537 {
1538         struct drm_device *dev = crtc->base.dev;
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         int reg = DPLL(crtc->pipe);
1541         u32 dpll = crtc->config.dpll_hw_state.dpll;
1542
1543         assert_pipe_disabled(dev_priv, crtc->pipe);
1544
1545         /* No really, not for ILK+ */
1546         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1547
1548         /* PLL is protected by panel, make sure we can write it */
1549         if (IS_MOBILE(dev_priv->dev))
1550                 assert_panel_unlocked(dev_priv, crtc->pipe);
1551
1552         I915_WRITE(reg, dpll);
1553         POSTING_READ(reg);
1554         udelay(150);
1555
1556         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1557                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1558
1559         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1560         POSTING_READ(DPLL_MD(crtc->pipe));
1561
1562         /* We do this three times for luck */
1563         I915_WRITE(reg, dpll);
1564         POSTING_READ(reg);
1565         udelay(150); /* wait for warmup */
1566         I915_WRITE(reg, dpll);
1567         POSTING_READ(reg);
1568         udelay(150); /* wait for warmup */
1569         I915_WRITE(reg, dpll);
1570         POSTING_READ(reg);
1571         udelay(150); /* wait for warmup */
1572 }
1573
1574 static void chv_enable_pll(struct intel_crtc *crtc)
1575 {
1576         struct drm_device *dev = crtc->base.dev;
1577         struct drm_i915_private *dev_priv = dev->dev_private;
1578         int pipe = crtc->pipe;
1579         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1580         u32 tmp;
1581
1582         assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1585
1586         mutex_lock(&dev_priv->dpio_lock);
1587
1588         /* Enable back the 10bit clock to display controller */
1589         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1590         tmp |= DPIO_DCLKP_EN;
1591         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1592
1593         /*
1594          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595          */
1596         udelay(1);
1597
1598         /* Enable PLL */
1599         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1600
1601         /* Check PLL is locked */
1602         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1603                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1604
1605         /* not sure when this should be written */
1606         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1607         POSTING_READ(DPLL_MD(pipe));
1608
1609         mutex_unlock(&dev_priv->dpio_lock);
1610 }
1611
1612 static int intel_num_dvo_pipes(struct drm_device *dev)
1613 {
1614         struct intel_crtc *crtc;
1615         int count = 0;
1616
1617         for_each_intel_crtc(dev, crtc)
1618                 count += crtc->active &&
1619                         intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1620
1621         return count;
1622 }
1623
1624 static void i9xx_enable_pll(struct intel_crtc *crtc)
1625 {
1626         struct drm_device *dev = crtc->base.dev;
1627         struct drm_i915_private *dev_priv = dev->dev_private;
1628         int reg = DPLL(crtc->pipe);
1629         u32 dpll = crtc->config.dpll_hw_state.dpll;
1630
1631         assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633         /* No really, not for ILK+ */
1634         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1635
1636         /* PLL is protected by panel, make sure we can write it */
1637         if (IS_MOBILE(dev) && !IS_I830(dev))
1638                 assert_panel_unlocked(dev_priv, crtc->pipe);
1639
1640         /* Enable DVO 2x clock on both PLLs if necessary */
1641         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1642                 /*
1643                  * It appears to be important that we don't enable this
1644                  * for the current pipe before otherwise configuring the
1645                  * PLL. No idea how this should be handled if multiple
1646                  * DVO outputs are enabled simultaneosly.
1647                  */
1648                 dpll |= DPLL_DVO_2X_MODE;
1649                 I915_WRITE(DPLL(!crtc->pipe),
1650                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1651         }
1652
1653         /* Wait for the clocks to stabilize. */
1654         POSTING_READ(reg);
1655         udelay(150);
1656
1657         if (INTEL_INFO(dev)->gen >= 4) {
1658                 I915_WRITE(DPLL_MD(crtc->pipe),
1659                            crtc->config.dpll_hw_state.dpll_md);
1660         } else {
1661                 /* The pixel multiplier can only be updated once the
1662                  * DPLL is enabled and the clocks are stable.
1663                  *
1664                  * So write it again.
1665                  */
1666                 I915_WRITE(reg, dpll);
1667         }
1668
1669         /* We do this three times for luck */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673         I915_WRITE(reg, dpll);
1674         POSTING_READ(reg);
1675         udelay(150); /* wait for warmup */
1676         I915_WRITE(reg, dpll);
1677         POSTING_READ(reg);
1678         udelay(150); /* wait for warmup */
1679 }
1680
1681 /**
1682  * i9xx_disable_pll - disable a PLL
1683  * @dev_priv: i915 private structure
1684  * @pipe: pipe PLL to disable
1685  *
1686  * Disable the PLL for @pipe, making sure the pipe is off first.
1687  *
1688  * Note!  This is for pre-ILK only.
1689  */
1690 static void i9xx_disable_pll(struct intel_crtc *crtc)
1691 {
1692         struct drm_device *dev = crtc->base.dev;
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694         enum pipe pipe = crtc->pipe;
1695
1696         /* Disable DVO 2x clock on both PLLs if necessary */
1697         if (IS_I830(dev) &&
1698             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1699             intel_num_dvo_pipes(dev) == 1) {
1700                 I915_WRITE(DPLL(PIPE_B),
1701                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1702                 I915_WRITE(DPLL(PIPE_A),
1703                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1704         }
1705
1706         /* Don't disable pipe or pipe PLLs if needed */
1707         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1708             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1709                 return;
1710
1711         /* Make sure the pipe isn't still relying on us */
1712         assert_pipe_disabled(dev_priv, pipe);
1713
1714         I915_WRITE(DPLL(pipe), 0);
1715         POSTING_READ(DPLL(pipe));
1716 }
1717
1718 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1719 {
1720         u32 val = 0;
1721
1722         /* Make sure the pipe isn't still relying on us */
1723         assert_pipe_disabled(dev_priv, pipe);
1724
1725         /*
1726          * Leave integrated clock source and reference clock enabled for pipe B.
1727          * The latter is needed for VGA hotplug / manual detection.
1728          */
1729         if (pipe == PIPE_B)
1730                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1731         I915_WRITE(DPLL(pipe), val);
1732         POSTING_READ(DPLL(pipe));
1733
1734 }
1735
1736 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1737 {
1738         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1739         u32 val;
1740
1741         /* Make sure the pipe isn't still relying on us */
1742         assert_pipe_disabled(dev_priv, pipe);
1743
1744         /* Set PLL en = 0 */
1745         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1746         if (pipe != PIPE_A)
1747                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1748         I915_WRITE(DPLL(pipe), val);
1749         POSTING_READ(DPLL(pipe));
1750
1751         mutex_lock(&dev_priv->dpio_lock);
1752
1753         /* Disable 10bit clock to display controller */
1754         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1755         val &= ~DPIO_DCLKP_EN;
1756         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1757
1758         /* disable left/right clock distribution */
1759         if (pipe != PIPE_B) {
1760                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1761                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1762                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1763         } else {
1764                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1765                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1766                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1767         }
1768
1769         mutex_unlock(&dev_priv->dpio_lock);
1770 }
1771
1772 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1773                 struct intel_digital_port *dport)
1774 {
1775         u32 port_mask;
1776         int dpll_reg;
1777
1778         switch (dport->port) {
1779         case PORT_B:
1780                 port_mask = DPLL_PORTB_READY_MASK;
1781                 dpll_reg = DPLL(0);
1782                 break;
1783         case PORT_C:
1784                 port_mask = DPLL_PORTC_READY_MASK;
1785                 dpll_reg = DPLL(0);
1786                 break;
1787         case PORT_D:
1788                 port_mask = DPLL_PORTD_READY_MASK;
1789                 dpll_reg = DPIO_PHY_STATUS;
1790                 break;
1791         default:
1792                 BUG();
1793         }
1794
1795         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1796                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1797                      port_name(dport->port), I915_READ(dpll_reg));
1798 }
1799
1800 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         WARN_ON(!pll->refcount);
1810         if (pll->active == 0) {
1811                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1812                 WARN_ON(pll->on);
1813                 assert_shared_dpll_disabled(dev_priv, pll);
1814
1815                 pll->mode_set(dev_priv, pll);
1816         }
1817 }
1818
1819 /**
1820  * intel_enable_shared_dpll - enable PCH PLL
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe PLL to enable
1823  *
1824  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1825  * drives the transcoder clock.
1826  */
1827 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1828 {
1829         struct drm_device *dev = crtc->base.dev;
1830         struct drm_i915_private *dev_priv = dev->dev_private;
1831         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1832
1833         if (WARN_ON(pll == NULL))
1834                 return;
1835
1836         if (WARN_ON(pll->refcount == 0))
1837                 return;
1838
1839         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1840                       pll->name, pll->active, pll->on,
1841                       crtc->base.base.id);
1842
1843         if (pll->active++) {
1844                 WARN_ON(!pll->on);
1845                 assert_shared_dpll_enabled(dev_priv, pll);
1846                 return;
1847         }
1848         WARN_ON(pll->on);
1849
1850         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1851
1852         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1853         pll->enable(dev_priv, pll);
1854         pll->on = true;
1855 }
1856
1857 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1858 {
1859         struct drm_device *dev = crtc->base.dev;
1860         struct drm_i915_private *dev_priv = dev->dev_private;
1861         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1862
1863         /* PCH only available on ILK+ */
1864         BUG_ON(INTEL_INFO(dev)->gen < 5);
1865         if (WARN_ON(pll == NULL))
1866                return;
1867
1868         if (WARN_ON(pll->refcount == 0))
1869                 return;
1870
1871         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1872                       pll->name, pll->active, pll->on,
1873                       crtc->base.base.id);
1874
1875         if (WARN_ON(pll->active == 0)) {
1876                 assert_shared_dpll_disabled(dev_priv, pll);
1877                 return;
1878         }
1879
1880         assert_shared_dpll_enabled(dev_priv, pll);
1881         WARN_ON(!pll->on);
1882         if (--pll->active)
1883                 return;
1884
1885         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1886         pll->disable(dev_priv, pll);
1887         pll->on = false;
1888
1889         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1890 }
1891
1892 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1893                                            enum pipe pipe)
1894 {
1895         struct drm_device *dev = dev_priv->dev;
1896         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1898         uint32_t reg, val, pipeconf_val;
1899
1900         /* PCH only available on ILK+ */
1901         BUG_ON(!HAS_PCH_SPLIT(dev));
1902
1903         /* Make sure PCH DPLL is enabled */
1904         assert_shared_dpll_enabled(dev_priv,
1905                                    intel_crtc_to_shared_dpll(intel_crtc));
1906
1907         /* FDI must be feeding us bits for PCH ports */
1908         assert_fdi_tx_enabled(dev_priv, pipe);
1909         assert_fdi_rx_enabled(dev_priv, pipe);
1910
1911         if (HAS_PCH_CPT(dev)) {
1912                 /* Workaround: Set the timing override bit before enabling the
1913                  * pch transcoder. */
1914                 reg = TRANS_CHICKEN2(pipe);
1915                 val = I915_READ(reg);
1916                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1917                 I915_WRITE(reg, val);
1918         }
1919
1920         reg = PCH_TRANSCONF(pipe);
1921         val = I915_READ(reg);
1922         pipeconf_val = I915_READ(PIPECONF(pipe));
1923
1924         if (HAS_PCH_IBX(dev_priv->dev)) {
1925                 /*
1926                  * make the BPC in transcoder be consistent with
1927                  * that in pipeconf reg.
1928                  */
1929                 val &= ~PIPECONF_BPC_MASK;
1930                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1931         }
1932
1933         val &= ~TRANS_INTERLACE_MASK;
1934         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1935                 if (HAS_PCH_IBX(dev_priv->dev) &&
1936                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1937                         val |= TRANS_LEGACY_INTERLACED_ILK;
1938                 else
1939                         val |= TRANS_INTERLACED;
1940         else
1941                 val |= TRANS_PROGRESSIVE;
1942
1943         I915_WRITE(reg, val | TRANS_ENABLE);
1944         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1945                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1946 }
1947
1948 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1949                                       enum transcoder cpu_transcoder)
1950 {
1951         u32 val, pipeconf_val;
1952
1953         /* PCH only available on ILK+ */
1954         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1955
1956         /* FDI must be feeding us bits for PCH ports */
1957         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1958         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1959
1960         /* Workaround: set timing override bit. */
1961         val = I915_READ(_TRANSA_CHICKEN2);
1962         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1963         I915_WRITE(_TRANSA_CHICKEN2, val);
1964
1965         val = TRANS_ENABLE;
1966         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1967
1968         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1969             PIPECONF_INTERLACED_ILK)
1970                 val |= TRANS_INTERLACED;
1971         else
1972                 val |= TRANS_PROGRESSIVE;
1973
1974         I915_WRITE(LPT_TRANSCONF, val);
1975         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1976                 DRM_ERROR("Failed to enable PCH transcoder\n");
1977 }
1978
1979 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1980                                             enum pipe pipe)
1981 {
1982         struct drm_device *dev = dev_priv->dev;
1983         uint32_t reg, val;
1984
1985         /* FDI relies on the transcoder */
1986         assert_fdi_tx_disabled(dev_priv, pipe);
1987         assert_fdi_rx_disabled(dev_priv, pipe);
1988
1989         /* Ports must be off as well */
1990         assert_pch_ports_disabled(dev_priv, pipe);
1991
1992         reg = PCH_TRANSCONF(pipe);
1993         val = I915_READ(reg);
1994         val &= ~TRANS_ENABLE;
1995         I915_WRITE(reg, val);
1996         /* wait for PCH transcoder off, transcoder state */
1997         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1998                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1999
2000         if (!HAS_PCH_IBX(dev)) {
2001                 /* Workaround: Clear the timing override chicken bit again. */
2002                 reg = TRANS_CHICKEN2(pipe);
2003                 val = I915_READ(reg);
2004                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2005                 I915_WRITE(reg, val);
2006         }
2007 }
2008
2009 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2010 {
2011         u32 val;
2012
2013         val = I915_READ(LPT_TRANSCONF);
2014         val &= ~TRANS_ENABLE;
2015         I915_WRITE(LPT_TRANSCONF, val);
2016         /* wait for PCH transcoder off, transcoder state */
2017         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2018                 DRM_ERROR("Failed to disable PCH transcoder\n");
2019
2020         /* Workaround: clear timing override bit. */
2021         val = I915_READ(_TRANSA_CHICKEN2);
2022         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2023         I915_WRITE(_TRANSA_CHICKEN2, val);
2024 }
2025
2026 /**
2027  * intel_enable_pipe - enable a pipe, asserting requirements
2028  * @crtc: crtc responsible for the pipe
2029  *
2030  * Enable @crtc's pipe, making sure that various hardware specific requirements
2031  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2032  */
2033 static void intel_enable_pipe(struct intel_crtc *crtc)
2034 {
2035         struct drm_device *dev = crtc->base.dev;
2036         struct drm_i915_private *dev_priv = dev->dev_private;
2037         enum pipe pipe = crtc->pipe;
2038         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2039                                                                       pipe);
2040         enum pipe pch_transcoder;
2041         int reg;
2042         u32 val;
2043
2044         assert_planes_disabled(dev_priv, pipe);
2045         assert_cursor_disabled(dev_priv, pipe);
2046         assert_sprites_disabled(dev_priv, pipe);
2047
2048         if (HAS_PCH_LPT(dev_priv->dev))
2049                 pch_transcoder = TRANSCODER_A;
2050         else
2051                 pch_transcoder = pipe;
2052
2053         /*
2054          * A pipe without a PLL won't actually be able to drive bits from
2055          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2056          * need the check.
2057          */
2058         if (!HAS_PCH_SPLIT(dev_priv->dev))
2059                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2060                         assert_dsi_pll_enabled(dev_priv);
2061                 else
2062                         assert_pll_enabled(dev_priv, pipe);
2063         else {
2064                 if (crtc->config.has_pch_encoder) {
2065                         /* if driving the PCH, we need FDI enabled */
2066                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2067                         assert_fdi_tx_pll_enabled(dev_priv,
2068                                                   (enum pipe) cpu_transcoder);
2069                 }
2070                 /* FIXME: assert CPU port conditions for SNB+ */
2071         }
2072
2073         reg = PIPECONF(cpu_transcoder);
2074         val = I915_READ(reg);
2075         if (val & PIPECONF_ENABLE) {
2076                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2077                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2078                 return;
2079         }
2080
2081         I915_WRITE(reg, val | PIPECONF_ENABLE);
2082         POSTING_READ(reg);
2083 }
2084
2085 /**
2086  * intel_disable_pipe - disable a pipe, asserting requirements
2087  * @crtc: crtc whose pipes is to be disabled
2088  *
2089  * Disable the pipe of @crtc, making sure that various hardware
2090  * specific requirements are met, if applicable, e.g. plane
2091  * disabled, panel fitter off, etc.
2092  *
2093  * Will wait until the pipe has shut down before returning.
2094  */
2095 static void intel_disable_pipe(struct intel_crtc *crtc)
2096 {
2097         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2098         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2099         enum pipe pipe = crtc->pipe;
2100         int reg;
2101         u32 val;
2102
2103         /*
2104          * Make sure planes won't keep trying to pump pixels to us,
2105          * or we might hang the display.
2106          */
2107         assert_planes_disabled(dev_priv, pipe);
2108         assert_cursor_disabled(dev_priv, pipe);
2109         assert_sprites_disabled(dev_priv, pipe);
2110
2111         reg = PIPECONF(cpu_transcoder);
2112         val = I915_READ(reg);
2113         if ((val & PIPECONF_ENABLE) == 0)
2114                 return;
2115
2116         /*
2117          * Double wide has implications for planes
2118          * so best keep it disabled when not needed.
2119          */
2120         if (crtc->config.double_wide)
2121                 val &= ~PIPECONF_DOUBLE_WIDE;
2122
2123         /* Don't disable pipe or pipe PLLs if needed */
2124         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2125             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2126                 val &= ~PIPECONF_ENABLE;
2127
2128         I915_WRITE(reg, val);
2129         if ((val & PIPECONF_ENABLE) == 0)
2130                 intel_wait_for_pipe_off(crtc);
2131 }
2132
2133 /*
2134  * Plane regs are double buffered, going from enabled->disabled needs a
2135  * trigger in order to latch.  The display address reg provides this.
2136  */
2137 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2138                                enum plane plane)
2139 {
2140         struct drm_device *dev = dev_priv->dev;
2141         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2142
2143         I915_WRITE(reg, I915_READ(reg));
2144         POSTING_READ(reg);
2145 }
2146
2147 /**
2148  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2149  * @plane:  plane to be enabled
2150  * @crtc: crtc for the plane
2151  *
2152  * Enable @plane on @crtc, making sure that the pipe is running first.
2153  */
2154 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2155                                           struct drm_crtc *crtc)
2156 {
2157         struct drm_device *dev = plane->dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160
2161         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2162         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2163
2164         if (intel_crtc->primary_enabled)
2165                 return;
2166
2167         intel_crtc->primary_enabled = true;
2168
2169         dev_priv->display.update_primary_plane(crtc, plane->fb,
2170                                                crtc->x, crtc->y);
2171
2172         /*
2173          * BDW signals flip done immediately if the plane
2174          * is disabled, even if the plane enable is already
2175          * armed to occur at the next vblank :(
2176          */
2177         if (IS_BROADWELL(dev))
2178                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2179 }
2180
2181 /**
2182  * intel_disable_primary_hw_plane - disable the primary hardware plane
2183  * @plane: plane to be disabled
2184  * @crtc: crtc for the plane
2185  *
2186  * Disable @plane on @crtc, making sure that the pipe is running first.
2187  */
2188 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2189                                            struct drm_crtc *crtc)
2190 {
2191         struct drm_device *dev = plane->dev;
2192         struct drm_i915_private *dev_priv = dev->dev_private;
2193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2194
2195         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2196
2197         if (!intel_crtc->primary_enabled)
2198                 return;
2199
2200         intel_crtc->primary_enabled = false;
2201
2202         dev_priv->display.update_primary_plane(crtc, plane->fb,
2203                                                crtc->x, crtc->y);
2204 }
2205
2206 static bool need_vtd_wa(struct drm_device *dev)
2207 {
2208 #ifdef CONFIG_INTEL_IOMMU
2209         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2210                 return true;
2211 #endif
2212         return false;
2213 }
2214
2215 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2216 {
2217         int tile_height;
2218
2219         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2220         return ALIGN(height, tile_height);
2221 }
2222
2223 int
2224 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2225                            struct drm_i915_gem_object *obj,
2226                            struct intel_engine_cs *pipelined)
2227 {
2228         struct drm_i915_private *dev_priv = dev->dev_private;
2229         u32 alignment;
2230         int ret;
2231
2232         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2233
2234         switch (obj->tiling_mode) {
2235         case I915_TILING_NONE:
2236                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2237                         alignment = 128 * 1024;
2238                 else if (INTEL_INFO(dev)->gen >= 4)
2239                         alignment = 4 * 1024;
2240                 else
2241                         alignment = 64 * 1024;
2242                 break;
2243         case I915_TILING_X:
2244                 /* pin() will align the object as required by fence */
2245                 alignment = 0;
2246                 break;
2247         case I915_TILING_Y:
2248                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2249                 return -EINVAL;
2250         default:
2251                 BUG();
2252         }
2253
2254         /* Note that the w/a also requires 64 PTE of padding following the
2255          * bo. We currently fill all unused PTE with the shadow page and so
2256          * we should always have valid PTE following the scanout preventing
2257          * the VT-d warning.
2258          */
2259         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2260                 alignment = 256 * 1024;
2261
2262         /*
2263          * Global gtt pte registers are special registers which actually forward
2264          * writes to a chunk of system memory. Which means that there is no risk
2265          * that the register values disappear as soon as we call
2266          * intel_runtime_pm_put(), so it is correct to wrap only the
2267          * pin/unpin/fence and not more.
2268          */
2269         intel_runtime_pm_get(dev_priv);
2270
2271         dev_priv->mm.interruptible = false;
2272         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2273         if (ret)
2274                 goto err_interruptible;
2275
2276         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2277          * fence, whereas 965+ only requires a fence if using
2278          * framebuffer compression.  For simplicity, we always install
2279          * a fence as the cost is not that onerous.
2280          */
2281         ret = i915_gem_object_get_fence(obj);
2282         if (ret)
2283                 goto err_unpin;
2284
2285         i915_gem_object_pin_fence(obj);
2286
2287         dev_priv->mm.interruptible = true;
2288         intel_runtime_pm_put(dev_priv);
2289         return 0;
2290
2291 err_unpin:
2292         i915_gem_object_unpin_from_display_plane(obj);
2293 err_interruptible:
2294         dev_priv->mm.interruptible = true;
2295         intel_runtime_pm_put(dev_priv);
2296         return ret;
2297 }
2298
2299 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2300 {
2301         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2302
2303         i915_gem_object_unpin_fence(obj);
2304         i915_gem_object_unpin_from_display_plane(obj);
2305 }
2306
2307 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2308  * is assumed to be a power-of-two. */
2309 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2310                                              unsigned int tiling_mode,
2311                                              unsigned int cpp,
2312                                              unsigned int pitch)
2313 {
2314         if (tiling_mode != I915_TILING_NONE) {
2315                 unsigned int tile_rows, tiles;
2316
2317                 tile_rows = *y / 8;
2318                 *y %= 8;
2319
2320                 tiles = *x / (512/cpp);
2321                 *x %= 512/cpp;
2322
2323                 return tile_rows * pitch * 8 + tiles * 4096;
2324         } else {
2325                 unsigned int offset;
2326
2327                 offset = *y * pitch + *x * cpp;
2328                 *y = 0;
2329                 *x = (offset & 4095) / cpp;
2330                 return offset & -4096;
2331         }
2332 }
2333
2334 int intel_format_to_fourcc(int format)
2335 {
2336         switch (format) {
2337         case DISPPLANE_8BPP:
2338                 return DRM_FORMAT_C8;
2339         case DISPPLANE_BGRX555:
2340                 return DRM_FORMAT_XRGB1555;
2341         case DISPPLANE_BGRX565:
2342                 return DRM_FORMAT_RGB565;
2343         default:
2344         case DISPPLANE_BGRX888:
2345                 return DRM_FORMAT_XRGB8888;
2346         case DISPPLANE_RGBX888:
2347                 return DRM_FORMAT_XBGR8888;
2348         case DISPPLANE_BGRX101010:
2349                 return DRM_FORMAT_XRGB2101010;
2350         case DISPPLANE_RGBX101010:
2351                 return DRM_FORMAT_XBGR2101010;
2352         }
2353 }
2354
2355 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2356                                   struct intel_plane_config *plane_config)
2357 {
2358         struct drm_device *dev = crtc->base.dev;
2359         struct drm_i915_gem_object *obj = NULL;
2360         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2361         u32 base = plane_config->base;
2362
2363         if (plane_config->size == 0)
2364                 return false;
2365
2366         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2367                                                              plane_config->size);
2368         if (!obj)
2369                 return false;
2370
2371         if (plane_config->tiled) {
2372                 obj->tiling_mode = I915_TILING_X;
2373                 obj->stride = crtc->base.primary->fb->pitches[0];
2374         }
2375
2376         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2377         mode_cmd.width = crtc->base.primary->fb->width;
2378         mode_cmd.height = crtc->base.primary->fb->height;
2379         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2380
2381         mutex_lock(&dev->struct_mutex);
2382
2383         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2384                                    &mode_cmd, obj)) {
2385                 DRM_DEBUG_KMS("intel fb init failed\n");
2386                 goto out_unref_obj;
2387         }
2388
2389         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2390         mutex_unlock(&dev->struct_mutex);
2391
2392         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2393         return true;
2394
2395 out_unref_obj:
2396         drm_gem_object_unreference(&obj->base);
2397         mutex_unlock(&dev->struct_mutex);
2398         return false;
2399 }
2400
2401 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2402                                  struct intel_plane_config *plane_config)
2403 {
2404         struct drm_device *dev = intel_crtc->base.dev;
2405         struct drm_crtc *c;
2406         struct intel_crtc *i;
2407         struct drm_i915_gem_object *obj;
2408
2409         if (!intel_crtc->base.primary->fb)
2410                 return;
2411
2412         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2413                 return;
2414
2415         kfree(intel_crtc->base.primary->fb);
2416         intel_crtc->base.primary->fb = NULL;
2417
2418         /*
2419          * Failed to alloc the obj, check to see if we should share
2420          * an fb with another CRTC instead
2421          */
2422         for_each_crtc(dev, c) {
2423                 i = to_intel_crtc(c);
2424
2425                 if (c == &intel_crtc->base)
2426                         continue;
2427
2428                 if (!i->active)
2429                         continue;
2430
2431                 obj = intel_fb_obj(c->primary->fb);
2432                 if (obj == NULL)
2433                         continue;
2434
2435                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2436                         drm_framebuffer_reference(c->primary->fb);
2437                         intel_crtc->base.primary->fb = c->primary->fb;
2438                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2439                         break;
2440                 }
2441         }
2442 }
2443
2444 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2445                                       struct drm_framebuffer *fb,
2446                                       int x, int y)
2447 {
2448         struct drm_device *dev = crtc->dev;
2449         struct drm_i915_private *dev_priv = dev->dev_private;
2450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451         struct drm_i915_gem_object *obj;
2452         int plane = intel_crtc->plane;
2453         unsigned long linear_offset;
2454         u32 dspcntr;
2455         u32 reg = DSPCNTR(plane);
2456         int pixel_size;
2457
2458         if (!intel_crtc->primary_enabled) {
2459                 I915_WRITE(reg, 0);
2460                 if (INTEL_INFO(dev)->gen >= 4)
2461                         I915_WRITE(DSPSURF(plane), 0);
2462                 else
2463                         I915_WRITE(DSPADDR(plane), 0);
2464                 POSTING_READ(reg);
2465                 return;
2466         }
2467
2468         obj = intel_fb_obj(fb);
2469         if (WARN_ON(obj == NULL))
2470                 return;
2471
2472         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2473
2474         dspcntr = DISPPLANE_GAMMA_ENABLE;
2475
2476         dspcntr |= DISPLAY_PLANE_ENABLE;
2477
2478         if (INTEL_INFO(dev)->gen < 4) {
2479                 if (intel_crtc->pipe == PIPE_B)
2480                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2481
2482                 /* pipesrc and dspsize control the size that is scaled from,
2483                  * which should always be the user's requested size.
2484                  */
2485                 I915_WRITE(DSPSIZE(plane),
2486                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2487                            (intel_crtc->config.pipe_src_w - 1));
2488                 I915_WRITE(DSPPOS(plane), 0);
2489         }
2490
2491         switch (fb->pixel_format) {
2492         case DRM_FORMAT_C8:
2493                 dspcntr |= DISPPLANE_8BPP;
2494                 break;
2495         case DRM_FORMAT_XRGB1555:
2496         case DRM_FORMAT_ARGB1555:
2497                 dspcntr |= DISPPLANE_BGRX555;
2498                 break;
2499         case DRM_FORMAT_RGB565:
2500                 dspcntr |= DISPPLANE_BGRX565;
2501                 break;
2502         case DRM_FORMAT_XRGB8888:
2503         case DRM_FORMAT_ARGB8888:
2504                 dspcntr |= DISPPLANE_BGRX888;
2505                 break;
2506         case DRM_FORMAT_XBGR8888:
2507         case DRM_FORMAT_ABGR8888:
2508                 dspcntr |= DISPPLANE_RGBX888;
2509                 break;
2510         case DRM_FORMAT_XRGB2101010:
2511         case DRM_FORMAT_ARGB2101010:
2512                 dspcntr |= DISPPLANE_BGRX101010;
2513                 break;
2514         case DRM_FORMAT_XBGR2101010:
2515         case DRM_FORMAT_ABGR2101010:
2516                 dspcntr |= DISPPLANE_RGBX101010;
2517                 break;
2518         default:
2519                 BUG();
2520         }
2521
2522         if (INTEL_INFO(dev)->gen >= 4 &&
2523             obj->tiling_mode != I915_TILING_NONE)
2524                 dspcntr |= DISPPLANE_TILED;
2525
2526         if (IS_G4X(dev))
2527                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2528
2529         linear_offset = y * fb->pitches[0] + x * pixel_size;
2530
2531         if (INTEL_INFO(dev)->gen >= 4) {
2532                 intel_crtc->dspaddr_offset =
2533                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2534                                                        pixel_size,
2535                                                        fb->pitches[0]);
2536                 linear_offset -= intel_crtc->dspaddr_offset;
2537         } else {
2538                 intel_crtc->dspaddr_offset = linear_offset;
2539         }
2540
2541         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2542                 dspcntr |= DISPPLANE_ROTATE_180;
2543
2544                 x += (intel_crtc->config.pipe_src_w - 1);
2545                 y += (intel_crtc->config.pipe_src_h - 1);
2546
2547                 /* Finding the last pixel of the last line of the display
2548                 data and adding to linear_offset*/
2549                 linear_offset +=
2550                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2551                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2552         }
2553
2554         I915_WRITE(reg, dspcntr);
2555
2556         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2557                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2558                       fb->pitches[0]);
2559         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2560         if (INTEL_INFO(dev)->gen >= 4) {
2561                 I915_WRITE(DSPSURF(plane),
2562                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2563                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2564                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2565         } else
2566                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2567         POSTING_READ(reg);
2568 }
2569
2570 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2571                                           struct drm_framebuffer *fb,
2572                                           int x, int y)
2573 {
2574         struct drm_device *dev = crtc->dev;
2575         struct drm_i915_private *dev_priv = dev->dev_private;
2576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577         struct drm_i915_gem_object *obj;
2578         int plane = intel_crtc->plane;
2579         unsigned long linear_offset;
2580         u32 dspcntr;
2581         u32 reg = DSPCNTR(plane);
2582         int pixel_size;
2583
2584         if (!intel_crtc->primary_enabled) {
2585                 I915_WRITE(reg, 0);
2586                 I915_WRITE(DSPSURF(plane), 0);
2587                 POSTING_READ(reg);
2588                 return;
2589         }
2590
2591         obj = intel_fb_obj(fb);
2592         if (WARN_ON(obj == NULL))
2593                 return;
2594
2595         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2596
2597         dspcntr = DISPPLANE_GAMMA_ENABLE;
2598
2599         dspcntr |= DISPLAY_PLANE_ENABLE;
2600
2601         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2602                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2603
2604         switch (fb->pixel_format) {
2605         case DRM_FORMAT_C8:
2606                 dspcntr |= DISPPLANE_8BPP;
2607                 break;
2608         case DRM_FORMAT_RGB565:
2609                 dspcntr |= DISPPLANE_BGRX565;
2610                 break;
2611         case DRM_FORMAT_XRGB8888:
2612         case DRM_FORMAT_ARGB8888:
2613                 dspcntr |= DISPPLANE_BGRX888;
2614                 break;
2615         case DRM_FORMAT_XBGR8888:
2616         case DRM_FORMAT_ABGR8888:
2617                 dspcntr |= DISPPLANE_RGBX888;
2618                 break;
2619         case DRM_FORMAT_XRGB2101010:
2620         case DRM_FORMAT_ARGB2101010:
2621                 dspcntr |= DISPPLANE_BGRX101010;
2622                 break;
2623         case DRM_FORMAT_XBGR2101010:
2624         case DRM_FORMAT_ABGR2101010:
2625                 dspcntr |= DISPPLANE_RGBX101010;
2626                 break;
2627         default:
2628                 BUG();
2629         }
2630
2631         if (obj->tiling_mode != I915_TILING_NONE)
2632                 dspcntr |= DISPPLANE_TILED;
2633
2634         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2635                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2636
2637         linear_offset = y * fb->pitches[0] + x * pixel_size;
2638         intel_crtc->dspaddr_offset =
2639                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2640                                                pixel_size,
2641                                                fb->pitches[0]);
2642         linear_offset -= intel_crtc->dspaddr_offset;
2643         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2644                 dspcntr |= DISPPLANE_ROTATE_180;
2645
2646                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2647                         x += (intel_crtc->config.pipe_src_w - 1);
2648                         y += (intel_crtc->config.pipe_src_h - 1);
2649
2650                         /* Finding the last pixel of the last line of the display
2651                         data and adding to linear_offset*/
2652                         linear_offset +=
2653                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2654                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2655                 }
2656         }
2657
2658         I915_WRITE(reg, dspcntr);
2659
2660         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2661                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2662                       fb->pitches[0]);
2663         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2664         I915_WRITE(DSPSURF(plane),
2665                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2666         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2667                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2668         } else {
2669                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2670                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2671         }
2672         POSTING_READ(reg);
2673 }
2674
2675 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2676 static int
2677 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2678                            int x, int y, enum mode_set_atomic state)
2679 {
2680         struct drm_device *dev = crtc->dev;
2681         struct drm_i915_private *dev_priv = dev->dev_private;
2682
2683         if (dev_priv->display.disable_fbc)
2684                 dev_priv->display.disable_fbc(dev);
2685         intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2686
2687         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2688
2689         return 0;
2690 }
2691
2692 void intel_display_handle_reset(struct drm_device *dev)
2693 {
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         struct drm_crtc *crtc;
2696
2697         /*
2698          * Flips in the rings have been nuked by the reset,
2699          * so complete all pending flips so that user space
2700          * will get its events and not get stuck.
2701          *
2702          * Also update the base address of all primary
2703          * planes to the the last fb to make sure we're
2704          * showing the correct fb after a reset.
2705          *
2706          * Need to make two loops over the crtcs so that we
2707          * don't try to grab a crtc mutex before the
2708          * pending_flip_queue really got woken up.
2709          */
2710
2711         for_each_crtc(dev, crtc) {
2712                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2713                 enum plane plane = intel_crtc->plane;
2714
2715                 intel_prepare_page_flip(dev, plane);
2716                 intel_finish_page_flip_plane(dev, plane);
2717         }
2718
2719         for_each_crtc(dev, crtc) {
2720                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2721
2722                 drm_modeset_lock(&crtc->mutex, NULL);
2723                 /*
2724                  * FIXME: Once we have proper support for primary planes (and
2725                  * disabling them without disabling the entire crtc) allow again
2726                  * a NULL crtc->primary->fb.
2727                  */
2728                 if (intel_crtc->active && crtc->primary->fb)
2729                         dev_priv->display.update_primary_plane(crtc,
2730                                                                crtc->primary->fb,
2731                                                                crtc->x,
2732                                                                crtc->y);
2733                 drm_modeset_unlock(&crtc->mutex);
2734         }
2735 }
2736
2737 static int
2738 intel_finish_fb(struct drm_framebuffer *old_fb)
2739 {
2740         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2741         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2742         bool was_interruptible = dev_priv->mm.interruptible;
2743         int ret;
2744
2745         /* Big Hammer, we also need to ensure that any pending
2746          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2747          * current scanout is retired before unpinning the old
2748          * framebuffer.
2749          *
2750          * This should only fail upon a hung GPU, in which case we
2751          * can safely continue.
2752          */
2753         dev_priv->mm.interruptible = false;
2754         ret = i915_gem_object_finish_gpu(obj);
2755         dev_priv->mm.interruptible = was_interruptible;
2756
2757         return ret;
2758 }
2759
2760 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2761 {
2762         struct drm_device *dev = crtc->dev;
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765         unsigned long flags;
2766         bool pending;
2767
2768         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2769             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2770                 return false;
2771
2772         spin_lock_irqsave(&dev->event_lock, flags);
2773         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2774         spin_unlock_irqrestore(&dev->event_lock, flags);
2775
2776         return pending;
2777 }
2778
2779 static int
2780 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2781                     struct drm_framebuffer *fb)
2782 {
2783         struct drm_device *dev = crtc->dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786         enum pipe pipe = intel_crtc->pipe;
2787         struct drm_framebuffer *old_fb = crtc->primary->fb;
2788         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2789         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2790         int ret;
2791
2792         if (intel_crtc_has_pending_flip(crtc)) {
2793                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2794                 return -EBUSY;
2795         }
2796
2797         /* no fb bound */
2798         if (!fb) {
2799                 DRM_ERROR("No FB bound\n");
2800                 return 0;
2801         }
2802
2803         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2804                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2805                           plane_name(intel_crtc->plane),
2806                           INTEL_INFO(dev)->num_pipes);
2807                 return -EINVAL;
2808         }
2809
2810         mutex_lock(&dev->struct_mutex);
2811         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2812         if (ret == 0)
2813                 i915_gem_track_fb(old_obj, obj,
2814                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2815         mutex_unlock(&dev->struct_mutex);
2816         if (ret != 0) {
2817                 DRM_ERROR("pin & fence failed\n");
2818                 return ret;
2819         }
2820
2821         /*
2822          * Update pipe size and adjust fitter if needed: the reason for this is
2823          * that in compute_mode_changes we check the native mode (not the pfit
2824          * mode) to see if we can flip rather than do a full mode set. In the
2825          * fastboot case, we'll flip, but if we don't update the pipesrc and
2826          * pfit state, we'll end up with a big fb scanned out into the wrong
2827          * sized surface.
2828          *
2829          * To fix this properly, we need to hoist the checks up into
2830          * compute_mode_changes (or above), check the actual pfit state and
2831          * whether the platform allows pfit disable with pipe active, and only
2832          * then update the pipesrc and pfit state, even on the flip path.
2833          */
2834         if (i915.fastboot) {
2835                 const struct drm_display_mode *adjusted_mode =
2836                         &intel_crtc->config.adjusted_mode;
2837
2838                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2839                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2840                            (adjusted_mode->crtc_vdisplay - 1));
2841                 if (!intel_crtc->config.pch_pfit.enabled &&
2842                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2843                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2844                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2845                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2846                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2847                 }
2848                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2849                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2850         }
2851
2852         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2853
2854         if (intel_crtc->active)
2855                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2856
2857         crtc->primary->fb = fb;
2858         crtc->x = x;
2859         crtc->y = y;
2860
2861         if (old_fb) {
2862                 if (intel_crtc->active && old_fb != fb)
2863                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2864                 mutex_lock(&dev->struct_mutex);
2865                 intel_unpin_fb_obj(old_obj);
2866                 mutex_unlock(&dev->struct_mutex);
2867         }
2868
2869         mutex_lock(&dev->struct_mutex);
2870         intel_update_fbc(dev);
2871         mutex_unlock(&dev->struct_mutex);
2872
2873         return 0;
2874 }
2875
2876 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2877 {
2878         struct drm_device *dev = crtc->dev;
2879         struct drm_i915_private *dev_priv = dev->dev_private;
2880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2881         int pipe = intel_crtc->pipe;
2882         u32 reg, temp;
2883
2884         /* enable normal train */
2885         reg = FDI_TX_CTL(pipe);
2886         temp = I915_READ(reg);
2887         if (IS_IVYBRIDGE(dev)) {
2888                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2889                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2890         } else {
2891                 temp &= ~FDI_LINK_TRAIN_NONE;
2892                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2893         }
2894         I915_WRITE(reg, temp);
2895
2896         reg = FDI_RX_CTL(pipe);
2897         temp = I915_READ(reg);
2898         if (HAS_PCH_CPT(dev)) {
2899                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2900                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2901         } else {
2902                 temp &= ~FDI_LINK_TRAIN_NONE;
2903                 temp |= FDI_LINK_TRAIN_NONE;
2904         }
2905         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2906
2907         /* wait one idle pattern time */
2908         POSTING_READ(reg);
2909         udelay(1000);
2910
2911         /* IVB wants error correction enabled */
2912         if (IS_IVYBRIDGE(dev))
2913                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2914                            FDI_FE_ERRC_ENABLE);
2915 }
2916
2917 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2918 {
2919         return crtc->base.enabled && crtc->active &&
2920                 crtc->config.has_pch_encoder;
2921 }
2922
2923 static void ivb_modeset_global_resources(struct drm_device *dev)
2924 {
2925         struct drm_i915_private *dev_priv = dev->dev_private;
2926         struct intel_crtc *pipe_B_crtc =
2927                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2928         struct intel_crtc *pipe_C_crtc =
2929                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2930         uint32_t temp;
2931
2932         /*
2933          * When everything is off disable fdi C so that we could enable fdi B
2934          * with all lanes. Note that we don't care about enabled pipes without
2935          * an enabled pch encoder.
2936          */
2937         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2938             !pipe_has_enabled_pch(pipe_C_crtc)) {
2939                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2940                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2941
2942                 temp = I915_READ(SOUTH_CHICKEN1);
2943                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2944                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2945                 I915_WRITE(SOUTH_CHICKEN1, temp);
2946         }
2947 }
2948
2949 /* The FDI link training functions for ILK/Ibexpeak. */
2950 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2951 {
2952         struct drm_device *dev = crtc->dev;
2953         struct drm_i915_private *dev_priv = dev->dev_private;
2954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2955         int pipe = intel_crtc->pipe;
2956         u32 reg, temp, tries;
2957
2958         /* FDI needs bits from pipe first */
2959         assert_pipe_enabled(dev_priv, pipe);
2960
2961         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2962            for train result */
2963         reg = FDI_RX_IMR(pipe);
2964         temp = I915_READ(reg);
2965         temp &= ~FDI_RX_SYMBOL_LOCK;
2966         temp &= ~FDI_RX_BIT_LOCK;
2967         I915_WRITE(reg, temp);
2968         I915_READ(reg);
2969         udelay(150);
2970
2971         /* enable CPU FDI TX and PCH FDI RX */
2972         reg = FDI_TX_CTL(pipe);
2973         temp = I915_READ(reg);
2974         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2975         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2976         temp &= ~FDI_LINK_TRAIN_NONE;
2977         temp |= FDI_LINK_TRAIN_PATTERN_1;
2978         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2979
2980         reg = FDI_RX_CTL(pipe);
2981         temp = I915_READ(reg);
2982         temp &= ~FDI_LINK_TRAIN_NONE;
2983         temp |= FDI_LINK_TRAIN_PATTERN_1;
2984         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2985
2986         POSTING_READ(reg);
2987         udelay(150);
2988
2989         /* Ironlake workaround, enable clock pointer after FDI enable*/
2990         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2991         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2992                    FDI_RX_PHASE_SYNC_POINTER_EN);
2993
2994         reg = FDI_RX_IIR(pipe);
2995         for (tries = 0; tries < 5; tries++) {
2996                 temp = I915_READ(reg);
2997                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2998
2999                 if ((temp & FDI_RX_BIT_LOCK)) {
3000                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3001                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3002                         break;
3003                 }
3004         }
3005         if (tries == 5)
3006                 DRM_ERROR("FDI train 1 fail!\n");
3007
3008         /* Train 2 */
3009         reg = FDI_TX_CTL(pipe);
3010         temp = I915_READ(reg);
3011         temp &= ~FDI_LINK_TRAIN_NONE;
3012         temp |= FDI_LINK_TRAIN_PATTERN_2;
3013         I915_WRITE(reg, temp);
3014
3015         reg = FDI_RX_CTL(pipe);
3016         temp = I915_READ(reg);
3017         temp &= ~FDI_LINK_TRAIN_NONE;
3018         temp |= FDI_LINK_TRAIN_PATTERN_2;
3019         I915_WRITE(reg, temp);
3020
3021         POSTING_READ(reg);
3022         udelay(150);
3023
3024         reg = FDI_RX_IIR(pipe);
3025         for (tries = 0; tries < 5; tries++) {
3026                 temp = I915_READ(reg);
3027                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3028
3029                 if (temp & FDI_RX_SYMBOL_LOCK) {
3030                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3031                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3032                         break;
3033                 }
3034         }
3035         if (tries == 5)
3036                 DRM_ERROR("FDI train 2 fail!\n");
3037
3038         DRM_DEBUG_KMS("FDI train done\n");
3039
3040 }
3041
3042 static const int snb_b_fdi_train_param[] = {
3043         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3044         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3045         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3046         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3047 };
3048
3049 /* The FDI link training functions for SNB/Cougarpoint. */
3050 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3051 {
3052         struct drm_device *dev = crtc->dev;
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3055         int pipe = intel_crtc->pipe;
3056         u32 reg, temp, i, retry;
3057
3058         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3059            for train result */
3060         reg = FDI_RX_IMR(pipe);
3061         temp = I915_READ(reg);
3062         temp &= ~FDI_RX_SYMBOL_LOCK;
3063         temp &= ~FDI_RX_BIT_LOCK;
3064         I915_WRITE(reg, temp);
3065
3066         POSTING_READ(reg);
3067         udelay(150);
3068
3069         /* enable CPU FDI TX and PCH FDI RX */
3070         reg = FDI_TX_CTL(pipe);
3071         temp = I915_READ(reg);
3072         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3073         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3074         temp &= ~FDI_LINK_TRAIN_NONE;
3075         temp |= FDI_LINK_TRAIN_PATTERN_1;
3076         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3077         /* SNB-B */
3078         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3079         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3080
3081         I915_WRITE(FDI_RX_MISC(pipe),
3082                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3083
3084         reg = FDI_RX_CTL(pipe);
3085         temp = I915_READ(reg);
3086         if (HAS_PCH_CPT(dev)) {
3087                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3088                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3089         } else {
3090                 temp &= ~FDI_LINK_TRAIN_NONE;
3091                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3092         }
3093         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3094
3095         POSTING_READ(reg);
3096         udelay(150);
3097
3098         for (i = 0; i < 4; i++) {
3099                 reg = FDI_TX_CTL(pipe);
3100                 temp = I915_READ(reg);
3101                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3102                 temp |= snb_b_fdi_train_param[i];
3103                 I915_WRITE(reg, temp);
3104
3105                 POSTING_READ(reg);
3106                 udelay(500);
3107
3108                 for (retry = 0; retry < 5; retry++) {
3109                         reg = FDI_RX_IIR(pipe);
3110                         temp = I915_READ(reg);
3111                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112                         if (temp & FDI_RX_BIT_LOCK) {
3113                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3114                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3115                                 break;
3116                         }
3117                         udelay(50);
3118                 }
3119                 if (retry < 5)
3120                         break;
3121         }
3122         if (i == 4)
3123                 DRM_ERROR("FDI train 1 fail!\n");
3124
3125         /* Train 2 */
3126         reg = FDI_TX_CTL(pipe);
3127         temp = I915_READ(reg);
3128         temp &= ~FDI_LINK_TRAIN_NONE;
3129         temp |= FDI_LINK_TRAIN_PATTERN_2;
3130         if (IS_GEN6(dev)) {
3131                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3132                 /* SNB-B */
3133                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3134         }
3135         I915_WRITE(reg, temp);
3136
3137         reg = FDI_RX_CTL(pipe);
3138         temp = I915_READ(reg);
3139         if (HAS_PCH_CPT(dev)) {
3140                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3141                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3142         } else {
3143                 temp &= ~FDI_LINK_TRAIN_NONE;
3144                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3145         }
3146         I915_WRITE(reg, temp);
3147
3148         POSTING_READ(reg);
3149         udelay(150);
3150
3151         for (i = 0; i < 4; i++) {
3152                 reg = FDI_TX_CTL(pipe);
3153                 temp = I915_READ(reg);
3154                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3155                 temp |= snb_b_fdi_train_param[i];
3156                 I915_WRITE(reg, temp);
3157
3158                 POSTING_READ(reg);
3159                 udelay(500);
3160
3161                 for (retry = 0; retry < 5; retry++) {
3162                         reg = FDI_RX_IIR(pipe);
3163                         temp = I915_READ(reg);
3164                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3165                         if (temp & FDI_RX_SYMBOL_LOCK) {
3166                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3167                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3168                                 break;
3169                         }
3170                         udelay(50);
3171                 }
3172                 if (retry < 5)
3173                         break;
3174         }
3175         if (i == 4)
3176                 DRM_ERROR("FDI train 2 fail!\n");
3177
3178         DRM_DEBUG_KMS("FDI train done.\n");
3179 }
3180
3181 /* Manual link training for Ivy Bridge A0 parts */
3182 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3183 {
3184         struct drm_device *dev = crtc->dev;
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187         int pipe = intel_crtc->pipe;
3188         u32 reg, temp, i, j;
3189
3190         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3191            for train result */
3192         reg = FDI_RX_IMR(pipe);
3193         temp = I915_READ(reg);
3194         temp &= ~FDI_RX_SYMBOL_LOCK;
3195         temp &= ~FDI_RX_BIT_LOCK;
3196         I915_WRITE(reg, temp);
3197
3198         POSTING_READ(reg);
3199         udelay(150);
3200
3201         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3202                       I915_READ(FDI_RX_IIR(pipe)));
3203
3204         /* Try each vswing and preemphasis setting twice before moving on */
3205         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3206                 /* disable first in case we need to retry */
3207                 reg = FDI_TX_CTL(pipe);
3208                 temp = I915_READ(reg);
3209                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3210                 temp &= ~FDI_TX_ENABLE;
3211                 I915_WRITE(reg, temp);
3212
3213                 reg = FDI_RX_CTL(pipe);
3214                 temp = I915_READ(reg);
3215                 temp &= ~FDI_LINK_TRAIN_AUTO;
3216                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3217                 temp &= ~FDI_RX_ENABLE;
3218                 I915_WRITE(reg, temp);
3219
3220                 /* enable CPU FDI TX and PCH FDI RX */
3221                 reg = FDI_TX_CTL(pipe);
3222                 temp = I915_READ(reg);
3223                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3224                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3225                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3226                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3227                 temp |= snb_b_fdi_train_param[j/2];
3228                 temp |= FDI_COMPOSITE_SYNC;
3229                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3230
3231                 I915_WRITE(FDI_RX_MISC(pipe),
3232                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3233
3234                 reg = FDI_RX_CTL(pipe);
3235                 temp = I915_READ(reg);
3236                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3237                 temp |= FDI_COMPOSITE_SYNC;
3238                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3239
3240                 POSTING_READ(reg);
3241                 udelay(1); /* should be 0.5us */
3242
3243                 for (i = 0; i < 4; i++) {
3244                         reg = FDI_RX_IIR(pipe);
3245                         temp = I915_READ(reg);
3246                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247
3248                         if (temp & FDI_RX_BIT_LOCK ||
3249                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3250                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3251                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3252                                               i);
3253                                 break;
3254                         }
3255                         udelay(1); /* should be 0.5us */
3256                 }
3257                 if (i == 4) {
3258                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3259                         continue;
3260                 }
3261
3262                 /* Train 2 */
3263                 reg = FDI_TX_CTL(pipe);
3264                 temp = I915_READ(reg);
3265                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3266                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3267                 I915_WRITE(reg, temp);
3268
3269                 reg = FDI_RX_CTL(pipe);
3270                 temp = I915_READ(reg);
3271                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3272                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3273                 I915_WRITE(reg, temp);
3274
3275                 POSTING_READ(reg);
3276                 udelay(2); /* should be 1.5us */
3277
3278                 for (i = 0; i < 4; i++) {
3279                         reg = FDI_RX_IIR(pipe);
3280                         temp = I915_READ(reg);
3281                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3282
3283                         if (temp & FDI_RX_SYMBOL_LOCK ||
3284                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3285                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3286                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3287                                               i);
3288                                 goto train_done;
3289                         }
3290                         udelay(2); /* should be 1.5us */
3291                 }
3292                 if (i == 4)
3293                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3294         }
3295
3296 train_done:
3297         DRM_DEBUG_KMS("FDI train done.\n");
3298 }
3299
3300 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3301 {
3302         struct drm_device *dev = intel_crtc->base.dev;
3303         struct drm_i915_private *dev_priv = dev->dev_private;
3304         int pipe = intel_crtc->pipe;
3305         u32 reg, temp;
3306
3307
3308         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3309         reg = FDI_RX_CTL(pipe);
3310         temp = I915_READ(reg);
3311         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3312         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3313         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3314         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3315
3316         POSTING_READ(reg);
3317         udelay(200);
3318
3319         /* Switch from Rawclk to PCDclk */
3320         temp = I915_READ(reg);
3321         I915_WRITE(reg, temp | FDI_PCDCLK);
3322
3323         POSTING_READ(reg);
3324         udelay(200);
3325
3326         /* Enable CPU FDI TX PLL, always on for Ironlake */
3327         reg = FDI_TX_CTL(pipe);
3328         temp = I915_READ(reg);
3329         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3330                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3331
3332                 POSTING_READ(reg);
3333                 udelay(100);
3334         }
3335 }
3336
3337 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3338 {
3339         struct drm_device *dev = intel_crtc->base.dev;
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341         int pipe = intel_crtc->pipe;
3342         u32 reg, temp;
3343
3344         /* Switch from PCDclk to Rawclk */
3345         reg = FDI_RX_CTL(pipe);
3346         temp = I915_READ(reg);
3347         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3348
3349         /* Disable CPU FDI TX PLL */
3350         reg = FDI_TX_CTL(pipe);
3351         temp = I915_READ(reg);
3352         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3353
3354         POSTING_READ(reg);
3355         udelay(100);
3356
3357         reg = FDI_RX_CTL(pipe);
3358         temp = I915_READ(reg);
3359         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3360
3361         /* Wait for the clocks to turn off. */
3362         POSTING_READ(reg);
3363         udelay(100);
3364 }
3365
3366 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3367 {
3368         struct drm_device *dev = crtc->dev;
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3371         int pipe = intel_crtc->pipe;
3372         u32 reg, temp;
3373
3374         /* disable CPU FDI tx and PCH FDI rx */
3375         reg = FDI_TX_CTL(pipe);
3376         temp = I915_READ(reg);
3377         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3378         POSTING_READ(reg);
3379
3380         reg = FDI_RX_CTL(pipe);
3381         temp = I915_READ(reg);
3382         temp &= ~(0x7 << 16);
3383         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3384         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3385
3386         POSTING_READ(reg);
3387         udelay(100);
3388
3389         /* Ironlake workaround, disable clock pointer after downing FDI */
3390         if (HAS_PCH_IBX(dev))
3391                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3392
3393         /* still set train pattern 1 */
3394         reg = FDI_TX_CTL(pipe);
3395         temp = I915_READ(reg);
3396         temp &= ~FDI_LINK_TRAIN_NONE;
3397         temp |= FDI_LINK_TRAIN_PATTERN_1;
3398         I915_WRITE(reg, temp);
3399
3400         reg = FDI_RX_CTL(pipe);
3401         temp = I915_READ(reg);
3402         if (HAS_PCH_CPT(dev)) {
3403                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3404                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3405         } else {
3406                 temp &= ~FDI_LINK_TRAIN_NONE;
3407                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408         }
3409         /* BPC in FDI rx is consistent with that in PIPECONF */
3410         temp &= ~(0x07 << 16);
3411         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3412         I915_WRITE(reg, temp);
3413
3414         POSTING_READ(reg);
3415         udelay(100);
3416 }
3417
3418 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3419 {
3420         struct intel_crtc *crtc;
3421
3422         /* Note that we don't need to be called with mode_config.lock here
3423          * as our list of CRTC objects is static for the lifetime of the
3424          * device and so cannot disappear as we iterate. Similarly, we can
3425          * happily treat the predicates as racy, atomic checks as userspace
3426          * cannot claim and pin a new fb without at least acquring the
3427          * struct_mutex and so serialising with us.
3428          */
3429         for_each_intel_crtc(dev, crtc) {
3430                 if (atomic_read(&crtc->unpin_work_count) == 0)
3431                         continue;
3432
3433                 if (crtc->unpin_work)
3434                         intel_wait_for_vblank(dev, crtc->pipe);
3435
3436                 return true;
3437         }
3438
3439         return false;
3440 }
3441
3442 static void page_flip_completed(struct intel_crtc *intel_crtc)
3443 {
3444         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3445         struct intel_unpin_work *work = intel_crtc->unpin_work;
3446
3447         /* ensure that the unpin work is consistent wrt ->pending. */
3448         smp_rmb();
3449         intel_crtc->unpin_work = NULL;
3450
3451         if (work->event)
3452                 drm_send_vblank_event(intel_crtc->base.dev,
3453                                       intel_crtc->pipe,
3454                                       work->event);
3455
3456         drm_crtc_vblank_put(&intel_crtc->base);
3457
3458         wake_up_all(&dev_priv->pending_flip_queue);
3459         queue_work(dev_priv->wq, &work->work);
3460
3461         trace_i915_flip_complete(intel_crtc->plane,
3462                                  work->pending_flip_obj);
3463 }
3464
3465 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3466 {
3467         struct drm_device *dev = crtc->dev;
3468         struct drm_i915_private *dev_priv = dev->dev_private;
3469
3470         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3471         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3472                                        !intel_crtc_has_pending_flip(crtc),
3473                                        60*HZ) == 0)) {
3474                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3475                 unsigned long flags;
3476
3477                 spin_lock_irqsave(&dev->event_lock, flags);
3478                 if (intel_crtc->unpin_work) {
3479                         WARN_ONCE(1, "Removing stuck page flip\n");
3480                         page_flip_completed(intel_crtc);
3481                 }
3482                 spin_unlock_irqrestore(&dev->event_lock, flags);
3483         }
3484
3485         if (crtc->primary->fb) {
3486                 mutex_lock(&dev->struct_mutex);
3487                 intel_finish_fb(crtc->primary->fb);
3488                 mutex_unlock(&dev->struct_mutex);
3489         }
3490 }
3491
3492 /* Program iCLKIP clock to the desired frequency */
3493 static void lpt_program_iclkip(struct drm_crtc *crtc)
3494 {
3495         struct drm_device *dev = crtc->dev;
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3498         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3499         u32 temp;
3500
3501         mutex_lock(&dev_priv->dpio_lock);
3502
3503         /* It is necessary to ungate the pixclk gate prior to programming
3504          * the divisors, and gate it back when it is done.
3505          */
3506         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3507
3508         /* Disable SSCCTL */
3509         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3510                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3511                                 SBI_SSCCTL_DISABLE,
3512                         SBI_ICLK);
3513
3514         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3515         if (clock == 20000) {
3516                 auxdiv = 1;
3517                 divsel = 0x41;
3518                 phaseinc = 0x20;
3519         } else {
3520                 /* The iCLK virtual clock root frequency is in MHz,
3521                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3522                  * divisors, it is necessary to divide one by another, so we
3523                  * convert the virtual clock precision to KHz here for higher
3524                  * precision.
3525                  */
3526                 u32 iclk_virtual_root_freq = 172800 * 1000;
3527                 u32 iclk_pi_range = 64;
3528                 u32 desired_divisor, msb_divisor_value, pi_value;
3529
3530                 desired_divisor = (iclk_virtual_root_freq / clock);
3531                 msb_divisor_value = desired_divisor / iclk_pi_range;
3532                 pi_value = desired_divisor % iclk_pi_range;
3533
3534                 auxdiv = 0;
3535                 divsel = msb_divisor_value - 2;
3536                 phaseinc = pi_value;
3537         }
3538
3539         /* This should not happen with any sane values */
3540         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3541                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3542         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3543                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3544
3545         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3546                         clock,
3547                         auxdiv,
3548                         divsel,
3549                         phasedir,
3550                         phaseinc);
3551
3552         /* Program SSCDIVINTPHASE6 */
3553         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3554         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3555         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3556         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3557         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3558         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3559         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3560         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3561
3562         /* Program SSCAUXDIV */
3563         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3564         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3565         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3566         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3567
3568         /* Enable modulator and associated divider */
3569         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3570         temp &= ~SBI_SSCCTL_DISABLE;
3571         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3572
3573         /* Wait for initialization time */
3574         udelay(24);
3575
3576         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3577
3578         mutex_unlock(&dev_priv->dpio_lock);
3579 }
3580
3581 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3582                                                 enum pipe pch_transcoder)
3583 {
3584         struct drm_device *dev = crtc->base.dev;
3585         struct drm_i915_private *dev_priv = dev->dev_private;
3586         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3587
3588         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3589                    I915_READ(HTOTAL(cpu_transcoder)));
3590         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3591                    I915_READ(HBLANK(cpu_transcoder)));
3592         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3593                    I915_READ(HSYNC(cpu_transcoder)));
3594
3595         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3596                    I915_READ(VTOTAL(cpu_transcoder)));
3597         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3598                    I915_READ(VBLANK(cpu_transcoder)));
3599         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3600                    I915_READ(VSYNC(cpu_transcoder)));
3601         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3602                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3603 }
3604
3605 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3606 {
3607         struct drm_i915_private *dev_priv = dev->dev_private;
3608         uint32_t temp;
3609
3610         temp = I915_READ(SOUTH_CHICKEN1);
3611         if (temp & FDI_BC_BIFURCATION_SELECT)
3612                 return;
3613
3614         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3615         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3616
3617         temp |= FDI_BC_BIFURCATION_SELECT;
3618         DRM_DEBUG_KMS("enabling fdi C rx\n");
3619         I915_WRITE(SOUTH_CHICKEN1, temp);
3620         POSTING_READ(SOUTH_CHICKEN1);
3621 }
3622
3623 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3624 {
3625         struct drm_device *dev = intel_crtc->base.dev;
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627
3628         switch (intel_crtc->pipe) {
3629         case PIPE_A:
3630                 break;
3631         case PIPE_B:
3632                 if (intel_crtc->config.fdi_lanes > 2)
3633                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3634                 else
3635                         cpt_enable_fdi_bc_bifurcation(dev);
3636
3637                 break;
3638         case PIPE_C:
3639                 cpt_enable_fdi_bc_bifurcation(dev);
3640
3641                 break;
3642         default:
3643                 BUG();
3644         }
3645 }
3646
3647 /*
3648  * Enable PCH resources required for PCH ports:
3649  *   - PCH PLLs
3650  *   - FDI training & RX/TX
3651  *   - update transcoder timings
3652  *   - DP transcoding bits
3653  *   - transcoder
3654  */
3655 static void ironlake_pch_enable(struct drm_crtc *crtc)
3656 {
3657         struct drm_device *dev = crtc->dev;
3658         struct drm_i915_private *dev_priv = dev->dev_private;
3659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660         int pipe = intel_crtc->pipe;
3661         u32 reg, temp;
3662
3663         assert_pch_transcoder_disabled(dev_priv, pipe);
3664
3665         if (IS_IVYBRIDGE(dev))
3666                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3667
3668         /* Write the TU size bits before fdi link training, so that error
3669          * detection works. */
3670         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3671                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3672
3673         /* For PCH output, training FDI link */
3674         dev_priv->display.fdi_link_train(crtc);
3675
3676         /* We need to program the right clock selection before writing the pixel
3677          * mutliplier into the DPLL. */
3678         if (HAS_PCH_CPT(dev)) {
3679                 u32 sel;
3680
3681                 temp = I915_READ(PCH_DPLL_SEL);
3682                 temp |= TRANS_DPLL_ENABLE(pipe);
3683                 sel = TRANS_DPLLB_SEL(pipe);
3684                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3685                         temp |= sel;
3686                 else
3687                         temp &= ~sel;
3688                 I915_WRITE(PCH_DPLL_SEL, temp);
3689         }
3690
3691         /* XXX: pch pll's can be enabled any time before we enable the PCH
3692          * transcoder, and we actually should do this to not upset any PCH
3693          * transcoder that already use the clock when we share it.
3694          *
3695          * Note that enable_shared_dpll tries to do the right thing, but
3696          * get_shared_dpll unconditionally resets the pll - we need that to have
3697          * the right LVDS enable sequence. */
3698         intel_enable_shared_dpll(intel_crtc);
3699
3700         /* set transcoder timing, panel must allow it */
3701         assert_panel_unlocked(dev_priv, pipe);
3702         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3703
3704         intel_fdi_normal_train(crtc);
3705
3706         /* For PCH DP, enable TRANS_DP_CTL */
3707         if (HAS_PCH_CPT(dev) &&
3708             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3709              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3710                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3711                 reg = TRANS_DP_CTL(pipe);
3712                 temp = I915_READ(reg);
3713                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3714                           TRANS_DP_SYNC_MASK |
3715                           TRANS_DP_BPC_MASK);
3716                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3717                          TRANS_DP_ENH_FRAMING);
3718                 temp |= bpc << 9; /* same format but at 11:9 */
3719
3720                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3721                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3722                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3723                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3724
3725                 switch (intel_trans_dp_port_sel(crtc)) {
3726                 case PCH_DP_B:
3727                         temp |= TRANS_DP_PORT_SEL_B;
3728                         break;
3729                 case PCH_DP_C:
3730                         temp |= TRANS_DP_PORT_SEL_C;
3731                         break;
3732                 case PCH_DP_D:
3733                         temp |= TRANS_DP_PORT_SEL_D;
3734                         break;
3735                 default:
3736                         BUG();
3737                 }
3738
3739                 I915_WRITE(reg, temp);
3740         }
3741
3742         ironlake_enable_pch_transcoder(dev_priv, pipe);
3743 }
3744
3745 static void lpt_pch_enable(struct drm_crtc *crtc)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3751
3752         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3753
3754         lpt_program_iclkip(crtc);
3755
3756         /* Set transcoder timing. */
3757         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3758
3759         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3760 }
3761
3762 void intel_put_shared_dpll(struct intel_crtc *crtc)
3763 {
3764         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3765
3766         if (pll == NULL)
3767                 return;
3768
3769         if (pll->refcount == 0) {
3770                 WARN(1, "bad %s refcount\n", pll->name);
3771                 return;
3772         }
3773
3774         if (--pll->refcount == 0) {
3775                 WARN_ON(pll->on);
3776                 WARN_ON(pll->active);
3777         }
3778
3779         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3780 }
3781
3782 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3783 {
3784         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3785         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3786         enum intel_dpll_id i;
3787
3788         if (pll) {
3789                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3790                               crtc->base.base.id, pll->name);
3791                 intel_put_shared_dpll(crtc);
3792         }
3793
3794         if (HAS_PCH_IBX(dev_priv->dev)) {
3795                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3796                 i = (enum intel_dpll_id) crtc->pipe;
3797                 pll = &dev_priv->shared_dplls[i];
3798
3799                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3800                               crtc->base.base.id, pll->name);
3801
3802                 WARN_ON(pll->refcount);
3803
3804                 goto found;
3805         }
3806
3807         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3808                 pll = &dev_priv->shared_dplls[i];
3809
3810                 /* Only want to check enabled timings first */
3811                 if (pll->refcount == 0)
3812                         continue;
3813
3814                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3815                            sizeof(pll->hw_state)) == 0) {
3816                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3817                                       crtc->base.base.id,
3818                                       pll->name, pll->refcount, pll->active);
3819
3820                         goto found;
3821                 }
3822         }
3823
3824         /* Ok no matching timings, maybe there's a free one? */
3825         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3826                 pll = &dev_priv->shared_dplls[i];
3827                 if (pll->refcount == 0) {
3828                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3829                                       crtc->base.base.id, pll->name);
3830                         goto found;
3831                 }
3832         }
3833
3834         return NULL;
3835
3836 found:
3837         if (pll->refcount == 0)
3838                 pll->hw_state = crtc->config.dpll_hw_state;
3839
3840         crtc->config.shared_dpll = i;
3841         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3842                          pipe_name(crtc->pipe));
3843
3844         pll->refcount++;
3845
3846         return pll;
3847 }
3848
3849 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3850 {
3851         struct drm_i915_private *dev_priv = dev->dev_private;
3852         int dslreg = PIPEDSL(pipe);
3853         u32 temp;
3854
3855         temp = I915_READ(dslreg);
3856         udelay(500);
3857         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3858                 if (wait_for(I915_READ(dslreg) != temp, 5))
3859                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3860         }
3861 }
3862
3863 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3864 {
3865         struct drm_device *dev = crtc->base.dev;
3866         struct drm_i915_private *dev_priv = dev->dev_private;
3867         int pipe = crtc->pipe;
3868
3869         if (crtc->config.pch_pfit.enabled) {
3870                 /* Force use of hard-coded filter coefficients
3871                  * as some pre-programmed values are broken,
3872                  * e.g. x201.
3873                  */
3874                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3875                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3876                                                  PF_PIPE_SEL_IVB(pipe));
3877                 else
3878                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3879                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3880                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3881         }
3882 }
3883
3884 static void intel_enable_planes(struct drm_crtc *crtc)
3885 {
3886         struct drm_device *dev = crtc->dev;
3887         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3888         struct drm_plane *plane;
3889         struct intel_plane *intel_plane;
3890
3891         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3892                 intel_plane = to_intel_plane(plane);
3893                 if (intel_plane->pipe == pipe)
3894                         intel_plane_restore(&intel_plane->base);
3895         }
3896 }
3897
3898 static void intel_disable_planes(struct drm_crtc *crtc)
3899 {
3900         struct drm_device *dev = crtc->dev;
3901         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3902         struct drm_plane *plane;
3903         struct intel_plane *intel_plane;
3904
3905         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3906                 intel_plane = to_intel_plane(plane);
3907                 if (intel_plane->pipe == pipe)
3908                         intel_plane_disable(&intel_plane->base);
3909         }
3910 }
3911
3912 void hsw_enable_ips(struct intel_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->base.dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916
3917         if (!crtc->config.ips_enabled)
3918                 return;
3919
3920         /* We can only enable IPS after we enable a plane and wait for a vblank */
3921         intel_wait_for_vblank(dev, crtc->pipe);
3922
3923         assert_plane_enabled(dev_priv, crtc->plane);
3924         if (IS_BROADWELL(dev)) {
3925                 mutex_lock(&dev_priv->rps.hw_lock);
3926                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3927                 mutex_unlock(&dev_priv->rps.hw_lock);
3928                 /* Quoting Art Runyan: "its not safe to expect any particular
3929                  * value in IPS_CTL bit 31 after enabling IPS through the
3930                  * mailbox." Moreover, the mailbox may return a bogus state,
3931                  * so we need to just enable it and continue on.
3932                  */
3933         } else {
3934                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3935                 /* The bit only becomes 1 in the next vblank, so this wait here
3936                  * is essentially intel_wait_for_vblank. If we don't have this
3937                  * and don't wait for vblanks until the end of crtc_enable, then
3938                  * the HW state readout code will complain that the expected
3939                  * IPS_CTL value is not the one we read. */
3940                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3941                         DRM_ERROR("Timed out waiting for IPS enable\n");
3942         }
3943 }
3944
3945 void hsw_disable_ips(struct intel_crtc *crtc)
3946 {
3947         struct drm_device *dev = crtc->base.dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949
3950         if (!crtc->config.ips_enabled)
3951                 return;
3952
3953         assert_plane_enabled(dev_priv, crtc->plane);
3954         if (IS_BROADWELL(dev)) {
3955                 mutex_lock(&dev_priv->rps.hw_lock);
3956                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3957                 mutex_unlock(&dev_priv->rps.hw_lock);
3958                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3959                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3960                         DRM_ERROR("Timed out waiting for IPS disable\n");
3961         } else {
3962                 I915_WRITE(IPS_CTL, 0);
3963                 POSTING_READ(IPS_CTL);
3964         }
3965
3966         /* We need to wait for a vblank before we can disable the plane. */
3967         intel_wait_for_vblank(dev, crtc->pipe);
3968 }
3969
3970 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3971 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3972 {
3973         struct drm_device *dev = crtc->dev;
3974         struct drm_i915_private *dev_priv = dev->dev_private;
3975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976         enum pipe pipe = intel_crtc->pipe;
3977         int palreg = PALETTE(pipe);
3978         int i;
3979         bool reenable_ips = false;
3980
3981         /* The clocks have to be on to load the palette. */
3982         if (!crtc->enabled || !intel_crtc->active)
3983                 return;
3984
3985         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3986                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3987                         assert_dsi_pll_enabled(dev_priv);
3988                 else
3989                         assert_pll_enabled(dev_priv, pipe);
3990         }
3991
3992         /* use legacy palette for Ironlake */
3993         if (!HAS_GMCH_DISPLAY(dev))
3994                 palreg = LGC_PALETTE(pipe);
3995
3996         /* Workaround : Do not read or write the pipe palette/gamma data while
3997          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3998          */
3999         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4000             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4001              GAMMA_MODE_MODE_SPLIT)) {
4002                 hsw_disable_ips(intel_crtc);
4003                 reenable_ips = true;
4004         }
4005
4006         for (i = 0; i < 256; i++) {
4007                 I915_WRITE(palreg + 4 * i,
4008                            (intel_crtc->lut_r[i] << 16) |
4009                            (intel_crtc->lut_g[i] << 8) |
4010                            intel_crtc->lut_b[i]);
4011         }
4012
4013         if (reenable_ips)
4014                 hsw_enable_ips(intel_crtc);
4015 }
4016
4017 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4018 {
4019         if (!enable && intel_crtc->overlay) {
4020                 struct drm_device *dev = intel_crtc->base.dev;
4021                 struct drm_i915_private *dev_priv = dev->dev_private;
4022
4023                 mutex_lock(&dev->struct_mutex);
4024                 dev_priv->mm.interruptible = false;
4025                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4026                 dev_priv->mm.interruptible = true;
4027                 mutex_unlock(&dev->struct_mutex);
4028         }
4029
4030         /* Let userspace switch the overlay on again. In most cases userspace
4031          * has to recompute where to put it anyway.
4032          */
4033 }
4034
4035 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4036 {
4037         struct drm_device *dev = crtc->dev;
4038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039         int pipe = intel_crtc->pipe;
4040
4041         assert_vblank_disabled(crtc);
4042
4043         drm_vblank_on(dev, pipe);
4044
4045         intel_enable_primary_hw_plane(crtc->primary, crtc);
4046         intel_enable_planes(crtc);
4047         intel_crtc_update_cursor(crtc, true);
4048         intel_crtc_dpms_overlay(intel_crtc, true);
4049
4050         hsw_enable_ips(intel_crtc);
4051
4052         mutex_lock(&dev->struct_mutex);
4053         intel_update_fbc(dev);
4054         mutex_unlock(&dev->struct_mutex);
4055
4056         /*
4057          * FIXME: Once we grow proper nuclear flip support out of this we need
4058          * to compute the mask of flip planes precisely. For the time being
4059          * consider this a flip from a NULL plane.
4060          */
4061         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4062 }
4063
4064 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4065 {
4066         struct drm_device *dev = crtc->dev;
4067         struct drm_i915_private *dev_priv = dev->dev_private;
4068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069         int pipe = intel_crtc->pipe;
4070         int plane = intel_crtc->plane;
4071
4072         intel_crtc_wait_for_pending_flips(crtc);
4073
4074         if (dev_priv->fbc.plane == plane)
4075                 intel_disable_fbc(dev);
4076
4077         hsw_disable_ips(intel_crtc);
4078
4079         intel_crtc_dpms_overlay(intel_crtc, false);
4080         intel_crtc_update_cursor(crtc, false);
4081         intel_disable_planes(crtc);
4082         intel_disable_primary_hw_plane(crtc->primary, crtc);
4083
4084         /*
4085          * FIXME: Once we grow proper nuclear flip support out of this we need
4086          * to compute the mask of flip planes precisely. For the time being
4087          * consider this a flip to a NULL plane.
4088          */
4089         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4090
4091         drm_vblank_off(dev, pipe);
4092
4093         assert_vblank_disabled(crtc);
4094 }
4095
4096 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4097 {
4098         struct drm_device *dev = crtc->dev;
4099         struct drm_i915_private *dev_priv = dev->dev_private;
4100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4101         struct intel_encoder *encoder;
4102         int pipe = intel_crtc->pipe;
4103
4104         WARN_ON(!crtc->enabled);
4105
4106         if (intel_crtc->active)
4107                 return;
4108
4109         if (intel_crtc->config.has_pch_encoder)
4110                 intel_prepare_shared_dpll(intel_crtc);
4111
4112         if (intel_crtc->config.has_dp_encoder)
4113                 intel_dp_set_m_n(intel_crtc);
4114
4115         intel_set_pipe_timings(intel_crtc);
4116
4117         if (intel_crtc->config.has_pch_encoder) {
4118                 intel_cpu_transcoder_set_m_n(intel_crtc,
4119                                      &intel_crtc->config.fdi_m_n, NULL);
4120         }
4121
4122         ironlake_set_pipeconf(crtc);
4123
4124         intel_crtc->active = true;
4125
4126         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4127         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4128
4129         for_each_encoder_on_crtc(dev, crtc, encoder)
4130                 if (encoder->pre_enable)
4131                         encoder->pre_enable(encoder);
4132
4133         if (intel_crtc->config.has_pch_encoder) {
4134                 /* Note: FDI PLL enabling _must_ be done before we enable the
4135                  * cpu pipes, hence this is separate from all the other fdi/pch
4136                  * enabling. */
4137                 ironlake_fdi_pll_enable(intel_crtc);
4138         } else {
4139                 assert_fdi_tx_disabled(dev_priv, pipe);
4140                 assert_fdi_rx_disabled(dev_priv, pipe);
4141         }
4142
4143         ironlake_pfit_enable(intel_crtc);
4144
4145         /*
4146          * On ILK+ LUT must be loaded before the pipe is running but with
4147          * clocks enabled
4148          */
4149         intel_crtc_load_lut(crtc);
4150
4151         intel_update_watermarks(crtc);
4152         intel_enable_pipe(intel_crtc);
4153
4154         if (intel_crtc->config.has_pch_encoder)
4155                 ironlake_pch_enable(crtc);
4156
4157         for_each_encoder_on_crtc(dev, crtc, encoder)
4158                 encoder->enable(encoder);
4159
4160         if (HAS_PCH_CPT(dev))
4161                 cpt_verify_modeset(dev, intel_crtc->pipe);
4162
4163         intel_crtc_enable_planes(crtc);
4164 }
4165
4166 /* IPS only exists on ULT machines and is tied to pipe A. */
4167 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4168 {
4169         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4170 }
4171
4172 /*
4173  * This implements the workaround described in the "notes" section of the mode
4174  * set sequence documentation. When going from no pipes or single pipe to
4175  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4176  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4177  */
4178 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4179 {
4180         struct drm_device *dev = crtc->base.dev;
4181         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4182
4183         /* We want to get the other_active_crtc only if there's only 1 other
4184          * active crtc. */
4185         for_each_intel_crtc(dev, crtc_it) {
4186                 if (!crtc_it->active || crtc_it == crtc)
4187                         continue;
4188
4189                 if (other_active_crtc)
4190                         return;
4191
4192                 other_active_crtc = crtc_it;
4193         }
4194         if (!other_active_crtc)
4195                 return;
4196
4197         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4198         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4199 }
4200
4201 static void haswell_crtc_enable(struct drm_crtc *crtc)
4202 {
4203         struct drm_device *dev = crtc->dev;
4204         struct drm_i915_private *dev_priv = dev->dev_private;
4205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4206         struct intel_encoder *encoder;
4207         int pipe = intel_crtc->pipe;
4208
4209         WARN_ON(!crtc->enabled);
4210
4211         if (intel_crtc->active)
4212                 return;
4213
4214         if (intel_crtc_to_shared_dpll(intel_crtc))
4215                 intel_enable_shared_dpll(intel_crtc);
4216
4217         if (intel_crtc->config.has_dp_encoder)
4218                 intel_dp_set_m_n(intel_crtc);
4219
4220         intel_set_pipe_timings(intel_crtc);
4221
4222         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4223                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4224                            intel_crtc->config.pixel_multiplier - 1);
4225         }
4226
4227         if (intel_crtc->config.has_pch_encoder) {
4228                 intel_cpu_transcoder_set_m_n(intel_crtc,
4229                                      &intel_crtc->config.fdi_m_n, NULL);
4230         }
4231
4232         haswell_set_pipeconf(crtc);
4233
4234         intel_set_pipe_csc(crtc);
4235
4236         intel_crtc->active = true;
4237
4238         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4239         for_each_encoder_on_crtc(dev, crtc, encoder)
4240                 if (encoder->pre_enable)
4241                         encoder->pre_enable(encoder);
4242
4243         if (intel_crtc->config.has_pch_encoder) {
4244                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4245                 dev_priv->display.fdi_link_train(crtc);
4246         }
4247
4248         intel_ddi_enable_pipe_clock(intel_crtc);
4249
4250         ironlake_pfit_enable(intel_crtc);
4251
4252         /*
4253          * On ILK+ LUT must be loaded before the pipe is running but with
4254          * clocks enabled
4255          */
4256         intel_crtc_load_lut(crtc);
4257
4258         intel_ddi_set_pipe_settings(crtc);
4259         intel_ddi_enable_transcoder_func(crtc);
4260
4261         intel_update_watermarks(crtc);
4262         intel_enable_pipe(intel_crtc);
4263
4264         if (intel_crtc->config.has_pch_encoder)
4265                 lpt_pch_enable(crtc);
4266
4267         if (intel_crtc->config.dp_encoder_is_mst)
4268                 intel_ddi_set_vc_payload_alloc(crtc, true);
4269
4270         for_each_encoder_on_crtc(dev, crtc, encoder) {
4271                 encoder->enable(encoder);
4272                 intel_opregion_notify_encoder(encoder, true);
4273         }
4274
4275         /* If we change the relative order between pipe/planes enabling, we need
4276          * to change the workaround. */
4277         haswell_mode_set_planes_workaround(intel_crtc);
4278         intel_crtc_enable_planes(crtc);
4279 }
4280
4281 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4282 {
4283         struct drm_device *dev = crtc->base.dev;
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         int pipe = crtc->pipe;
4286
4287         /* To avoid upsetting the power well on haswell only disable the pfit if
4288          * it's in use. The hw state code will make sure we get this right. */
4289         if (crtc->config.pch_pfit.enabled) {
4290                 I915_WRITE(PF_CTL(pipe), 0);
4291                 I915_WRITE(PF_WIN_POS(pipe), 0);
4292                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4293         }
4294 }
4295
4296 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4297 {
4298         struct drm_device *dev = crtc->dev;
4299         struct drm_i915_private *dev_priv = dev->dev_private;
4300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301         struct intel_encoder *encoder;
4302         int pipe = intel_crtc->pipe;
4303         u32 reg, temp;
4304
4305         if (!intel_crtc->active)
4306                 return;
4307
4308         intel_crtc_disable_planes(crtc);
4309
4310         for_each_encoder_on_crtc(dev, crtc, encoder)
4311                 encoder->disable(encoder);
4312
4313         if (intel_crtc->config.has_pch_encoder)
4314                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4315
4316         intel_disable_pipe(intel_crtc);
4317
4318         ironlake_pfit_disable(intel_crtc);
4319
4320         for_each_encoder_on_crtc(dev, crtc, encoder)
4321                 if (encoder->post_disable)
4322                         encoder->post_disable(encoder);
4323
4324         if (intel_crtc->config.has_pch_encoder) {
4325                 ironlake_fdi_disable(crtc);
4326
4327                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4328
4329                 if (HAS_PCH_CPT(dev)) {
4330                         /* disable TRANS_DP_CTL */
4331                         reg = TRANS_DP_CTL(pipe);
4332                         temp = I915_READ(reg);
4333                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4334                                   TRANS_DP_PORT_SEL_MASK);
4335                         temp |= TRANS_DP_PORT_SEL_NONE;
4336                         I915_WRITE(reg, temp);
4337
4338                         /* disable DPLL_SEL */
4339                         temp = I915_READ(PCH_DPLL_SEL);
4340                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4341                         I915_WRITE(PCH_DPLL_SEL, temp);
4342                 }
4343
4344                 /* disable PCH DPLL */
4345                 intel_disable_shared_dpll(intel_crtc);
4346
4347                 ironlake_fdi_pll_disable(intel_crtc);
4348         }
4349
4350         intel_crtc->active = false;
4351         intel_update_watermarks(crtc);
4352
4353         mutex_lock(&dev->struct_mutex);
4354         intel_update_fbc(dev);
4355         mutex_unlock(&dev->struct_mutex);
4356 }
4357
4358 static void haswell_crtc_disable(struct drm_crtc *crtc)
4359 {
4360         struct drm_device *dev = crtc->dev;
4361         struct drm_i915_private *dev_priv = dev->dev_private;
4362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363         struct intel_encoder *encoder;
4364         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4365
4366         if (!intel_crtc->active)
4367                 return;
4368
4369         intel_crtc_disable_planes(crtc);
4370
4371         for_each_encoder_on_crtc(dev, crtc, encoder) {
4372                 intel_opregion_notify_encoder(encoder, false);
4373                 encoder->disable(encoder);
4374         }
4375
4376         if (intel_crtc->config.has_pch_encoder)
4377                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4378         intel_disable_pipe(intel_crtc);
4379
4380         if (intel_crtc->config.dp_encoder_is_mst)
4381                 intel_ddi_set_vc_payload_alloc(crtc, false);
4382
4383         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4384
4385         ironlake_pfit_disable(intel_crtc);
4386
4387         intel_ddi_disable_pipe_clock(intel_crtc);
4388
4389         if (intel_crtc->config.has_pch_encoder) {
4390                 lpt_disable_pch_transcoder(dev_priv);
4391                 intel_ddi_fdi_disable(crtc);
4392         }
4393
4394         for_each_encoder_on_crtc(dev, crtc, encoder)
4395                 if (encoder->post_disable)
4396                         encoder->post_disable(encoder);
4397
4398         intel_crtc->active = false;
4399         intel_update_watermarks(crtc);
4400
4401         mutex_lock(&dev->struct_mutex);
4402         intel_update_fbc(dev);
4403         mutex_unlock(&dev->struct_mutex);
4404
4405         if (intel_crtc_to_shared_dpll(intel_crtc))
4406                 intel_disable_shared_dpll(intel_crtc);
4407 }
4408
4409 static void ironlake_crtc_off(struct drm_crtc *crtc)
4410 {
4411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412         intel_put_shared_dpll(intel_crtc);
4413 }
4414
4415
4416 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4417 {
4418         struct drm_device *dev = crtc->base.dev;
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420         struct intel_crtc_config *pipe_config = &crtc->config;
4421
4422         if (!crtc->config.gmch_pfit.control)
4423                 return;
4424
4425         /*
4426          * The panel fitter should only be adjusted whilst the pipe is disabled,
4427          * according to register description and PRM.
4428          */
4429         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4430         assert_pipe_disabled(dev_priv, crtc->pipe);
4431
4432         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4433         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4434
4435         /* Border color in case we don't scale up to the full screen. Black by
4436          * default, change to something else for debugging. */
4437         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4438 }
4439
4440 static enum intel_display_power_domain port_to_power_domain(enum port port)
4441 {
4442         switch (port) {
4443         case PORT_A:
4444                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4445         case PORT_B:
4446                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4447         case PORT_C:
4448                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4449         case PORT_D:
4450                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4451         default:
4452                 WARN_ON_ONCE(1);
4453                 return POWER_DOMAIN_PORT_OTHER;
4454         }
4455 }
4456
4457 #define for_each_power_domain(domain, mask)                             \
4458         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4459                 if ((1 << (domain)) & (mask))
4460
4461 enum intel_display_power_domain
4462 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4463 {
4464         struct drm_device *dev = intel_encoder->base.dev;
4465         struct intel_digital_port *intel_dig_port;
4466
4467         switch (intel_encoder->type) {
4468         case INTEL_OUTPUT_UNKNOWN:
4469                 /* Only DDI platforms should ever use this output type */
4470                 WARN_ON_ONCE(!HAS_DDI(dev));
4471         case INTEL_OUTPUT_DISPLAYPORT:
4472         case INTEL_OUTPUT_HDMI:
4473         case INTEL_OUTPUT_EDP:
4474                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4475                 return port_to_power_domain(intel_dig_port->port);
4476         case INTEL_OUTPUT_DP_MST:
4477                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4478                 return port_to_power_domain(intel_dig_port->port);
4479         case INTEL_OUTPUT_ANALOG:
4480                 return POWER_DOMAIN_PORT_CRT;
4481         case INTEL_OUTPUT_DSI:
4482                 return POWER_DOMAIN_PORT_DSI;
4483         default:
4484                 return POWER_DOMAIN_PORT_OTHER;
4485         }
4486 }
4487
4488 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4489 {
4490         struct drm_device *dev = crtc->dev;
4491         struct intel_encoder *intel_encoder;
4492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4493         enum pipe pipe = intel_crtc->pipe;
4494         unsigned long mask;
4495         enum transcoder transcoder;
4496
4497         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4498
4499         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4500         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4501         if (intel_crtc->config.pch_pfit.enabled ||
4502             intel_crtc->config.pch_pfit.force_thru)
4503                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4504
4505         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4506                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4507
4508         return mask;
4509 }
4510
4511 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4512                                   bool enable)
4513 {
4514         if (dev_priv->power_domains.init_power_on == enable)
4515                 return;
4516
4517         if (enable)
4518                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4519         else
4520                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4521
4522         dev_priv->power_domains.init_power_on = enable;
4523 }
4524
4525 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4526 {
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4529         struct intel_crtc *crtc;
4530
4531         /*
4532          * First get all needed power domains, then put all unneeded, to avoid
4533          * any unnecessary toggling of the power wells.
4534          */
4535         for_each_intel_crtc(dev, crtc) {
4536                 enum intel_display_power_domain domain;
4537
4538                 if (!crtc->base.enabled)
4539                         continue;
4540
4541                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4542
4543                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4544                         intel_display_power_get(dev_priv, domain);
4545         }
4546
4547         for_each_intel_crtc(dev, crtc) {
4548                 enum intel_display_power_domain domain;
4549
4550                 for_each_power_domain(domain, crtc->enabled_power_domains)
4551                         intel_display_power_put(dev_priv, domain);
4552
4553                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4554         }
4555
4556         intel_display_set_init_power(dev_priv, false);
4557 }
4558
4559 /* returns HPLL frequency in kHz */
4560 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4561 {
4562         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4563
4564         /* Obtain SKU information */
4565         mutex_lock(&dev_priv->dpio_lock);
4566         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4567                 CCK_FUSE_HPLL_FREQ_MASK;
4568         mutex_unlock(&dev_priv->dpio_lock);
4569
4570         return vco_freq[hpll_freq] * 1000;
4571 }
4572
4573 static void vlv_update_cdclk(struct drm_device *dev)
4574 {
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576
4577         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4578         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4579                          dev_priv->vlv_cdclk_freq);
4580
4581         /*
4582          * Program the gmbus_freq based on the cdclk frequency.
4583          * BSpec erroneously claims we should aim for 4MHz, but
4584          * in fact 1MHz is the correct frequency.
4585          */
4586         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4587 }
4588
4589 /* Adjust CDclk dividers to allow high res or save power if possible */
4590 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4591 {
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593         u32 val, cmd;
4594
4595         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4596
4597         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4598                 cmd = 2;
4599         else if (cdclk == 266667)
4600                 cmd = 1;
4601         else
4602                 cmd = 0;
4603
4604         mutex_lock(&dev_priv->rps.hw_lock);
4605         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4606         val &= ~DSPFREQGUAR_MASK;
4607         val |= (cmd << DSPFREQGUAR_SHIFT);
4608         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4609         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4610                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4611                      50)) {
4612                 DRM_ERROR("timed out waiting for CDclk change\n");
4613         }
4614         mutex_unlock(&dev_priv->rps.hw_lock);
4615
4616         if (cdclk == 400000) {
4617                 u32 divider, vco;
4618
4619                 vco = valleyview_get_vco(dev_priv);
4620                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4621
4622                 mutex_lock(&dev_priv->dpio_lock);
4623                 /* adjust cdclk divider */
4624                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4625                 val &= ~DISPLAY_FREQUENCY_VALUES;
4626                 val |= divider;
4627                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4628
4629                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4630                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4631                              50))
4632                         DRM_ERROR("timed out waiting for CDclk change\n");
4633                 mutex_unlock(&dev_priv->dpio_lock);
4634         }
4635
4636         mutex_lock(&dev_priv->dpio_lock);
4637         /* adjust self-refresh exit latency value */
4638         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4639         val &= ~0x7f;
4640
4641         /*
4642          * For high bandwidth configs, we set a higher latency in the bunit
4643          * so that the core display fetch happens in time to avoid underruns.
4644          */
4645         if (cdclk == 400000)
4646                 val |= 4500 / 250; /* 4.5 usec */
4647         else
4648                 val |= 3000 / 250; /* 3.0 usec */
4649         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4650         mutex_unlock(&dev_priv->dpio_lock);
4651
4652         vlv_update_cdclk(dev);
4653 }
4654
4655 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4656 {
4657         struct drm_i915_private *dev_priv = dev->dev_private;
4658         u32 val, cmd;
4659
4660         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4661
4662         switch (cdclk) {
4663         case 400000:
4664                 cmd = 3;
4665                 break;
4666         case 333333:
4667         case 320000:
4668                 cmd = 2;
4669                 break;
4670         case 266667:
4671                 cmd = 1;
4672                 break;
4673         case 200000:
4674                 cmd = 0;
4675                 break;
4676         default:
4677                 WARN_ON(1);
4678                 return;
4679         }
4680
4681         mutex_lock(&dev_priv->rps.hw_lock);
4682         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4683         val &= ~DSPFREQGUAR_MASK_CHV;
4684         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4685         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4686         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4687                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4688                      50)) {
4689                 DRM_ERROR("timed out waiting for CDclk change\n");
4690         }
4691         mutex_unlock(&dev_priv->rps.hw_lock);
4692
4693         vlv_update_cdclk(dev);
4694 }
4695
4696 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4697                                  int max_pixclk)
4698 {
4699         int vco = valleyview_get_vco(dev_priv);
4700         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4701
4702         /* FIXME: Punit isn't quite ready yet */
4703         if (IS_CHERRYVIEW(dev_priv->dev))
4704                 return 400000;
4705
4706         /*
4707          * Really only a few cases to deal with, as only 4 CDclks are supported:
4708          *   200MHz
4709          *   267MHz
4710          *   320/333MHz (depends on HPLL freq)
4711          *   400MHz
4712          * So we check to see whether we're above 90% of the lower bin and
4713          * adjust if needed.
4714          *
4715          * We seem to get an unstable or solid color picture at 200MHz.
4716          * Not sure what's wrong. For now use 200MHz only when all pipes
4717          * are off.
4718          */
4719         if (max_pixclk > freq_320*9/10)
4720                 return 400000;
4721         else if (max_pixclk > 266667*9/10)
4722                 return freq_320;
4723         else if (max_pixclk > 0)
4724                 return 266667;
4725         else
4726                 return 200000;
4727 }
4728
4729 /* compute the max pixel clock for new configuration */
4730 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4731 {
4732         struct drm_device *dev = dev_priv->dev;
4733         struct intel_crtc *intel_crtc;
4734         int max_pixclk = 0;
4735
4736         for_each_intel_crtc(dev, intel_crtc) {
4737                 if (intel_crtc->new_enabled)
4738                         max_pixclk = max(max_pixclk,
4739                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4740         }
4741
4742         return max_pixclk;
4743 }
4744
4745 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4746                                             unsigned *prepare_pipes)
4747 {
4748         struct drm_i915_private *dev_priv = dev->dev_private;
4749         struct intel_crtc *intel_crtc;
4750         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4751
4752         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4753             dev_priv->vlv_cdclk_freq)
4754                 return;
4755
4756         /* disable/enable all currently active pipes while we change cdclk */
4757         for_each_intel_crtc(dev, intel_crtc)
4758                 if (intel_crtc->base.enabled)
4759                         *prepare_pipes |= (1 << intel_crtc->pipe);
4760 }
4761
4762 static void valleyview_modeset_global_resources(struct drm_device *dev)
4763 {
4764         struct drm_i915_private *dev_priv = dev->dev_private;
4765         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4766         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4767
4768         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4769                 if (IS_CHERRYVIEW(dev))
4770                         cherryview_set_cdclk(dev, req_cdclk);
4771                 else
4772                         valleyview_set_cdclk(dev, req_cdclk);
4773         }
4774
4775         modeset_update_crtc_power_domains(dev);
4776 }
4777
4778 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4779 {
4780         struct drm_device *dev = crtc->dev;
4781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782         struct intel_encoder *encoder;
4783         int pipe = intel_crtc->pipe;
4784         bool is_dsi;
4785
4786         WARN_ON(!crtc->enabled);
4787
4788         if (intel_crtc->active)
4789                 return;
4790
4791         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4792
4793         if (!is_dsi) {
4794                 if (IS_CHERRYVIEW(dev))
4795                         chv_prepare_pll(intel_crtc);
4796                 else
4797                         vlv_prepare_pll(intel_crtc);
4798         }
4799
4800         if (intel_crtc->config.has_dp_encoder)
4801                 intel_dp_set_m_n(intel_crtc);
4802
4803         intel_set_pipe_timings(intel_crtc);
4804
4805         i9xx_set_pipeconf(intel_crtc);
4806
4807         intel_crtc->active = true;
4808
4809         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4810
4811         for_each_encoder_on_crtc(dev, crtc, encoder)
4812                 if (encoder->pre_pll_enable)
4813                         encoder->pre_pll_enable(encoder);
4814
4815         if (!is_dsi) {
4816                 if (IS_CHERRYVIEW(dev))
4817                         chv_enable_pll(intel_crtc);
4818                 else
4819                         vlv_enable_pll(intel_crtc);
4820         }
4821
4822         for_each_encoder_on_crtc(dev, crtc, encoder)
4823                 if (encoder->pre_enable)
4824                         encoder->pre_enable(encoder);
4825
4826         i9xx_pfit_enable(intel_crtc);
4827
4828         intel_crtc_load_lut(crtc);
4829
4830         intel_update_watermarks(crtc);
4831         intel_enable_pipe(intel_crtc);
4832
4833         for_each_encoder_on_crtc(dev, crtc, encoder)
4834                 encoder->enable(encoder);
4835
4836         intel_crtc_enable_planes(crtc);
4837
4838         /* Underruns don't raise interrupts, so check manually. */
4839         i9xx_check_fifo_underruns(dev);
4840 }
4841
4842 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4843 {
4844         struct drm_device *dev = crtc->base.dev;
4845         struct drm_i915_private *dev_priv = dev->dev_private;
4846
4847         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4848         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4849 }
4850
4851 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4852 {
4853         struct drm_device *dev = crtc->dev;
4854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855         struct intel_encoder *encoder;
4856         int pipe = intel_crtc->pipe;
4857
4858         WARN_ON(!crtc->enabled);
4859
4860         if (intel_crtc->active)
4861                 return;
4862
4863         i9xx_set_pll_dividers(intel_crtc);
4864
4865         if (intel_crtc->config.has_dp_encoder)
4866                 intel_dp_set_m_n(intel_crtc);
4867
4868         intel_set_pipe_timings(intel_crtc);
4869
4870         i9xx_set_pipeconf(intel_crtc);
4871
4872         intel_crtc->active = true;
4873
4874         if (!IS_GEN2(dev))
4875                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4876
4877         for_each_encoder_on_crtc(dev, crtc, encoder)
4878                 if (encoder->pre_enable)
4879                         encoder->pre_enable(encoder);
4880
4881         i9xx_enable_pll(intel_crtc);
4882
4883         i9xx_pfit_enable(intel_crtc);
4884
4885         intel_crtc_load_lut(crtc);
4886
4887         intel_update_watermarks(crtc);
4888         intel_enable_pipe(intel_crtc);
4889
4890         for_each_encoder_on_crtc(dev, crtc, encoder)
4891                 encoder->enable(encoder);
4892
4893         intel_crtc_enable_planes(crtc);
4894
4895         /*
4896          * Gen2 reports pipe underruns whenever all planes are disabled.
4897          * So don't enable underrun reporting before at least some planes
4898          * are enabled.
4899          * FIXME: Need to fix the logic to work when we turn off all planes
4900          * but leave the pipe running.
4901          */
4902         if (IS_GEN2(dev))
4903                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4904
4905         /* Underruns don't raise interrupts, so check manually. */
4906         i9xx_check_fifo_underruns(dev);
4907 }
4908
4909 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4910 {
4911         struct drm_device *dev = crtc->base.dev;
4912         struct drm_i915_private *dev_priv = dev->dev_private;
4913
4914         if (!crtc->config.gmch_pfit.control)
4915                 return;
4916
4917         assert_pipe_disabled(dev_priv, crtc->pipe);
4918
4919         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4920                          I915_READ(PFIT_CONTROL));
4921         I915_WRITE(PFIT_CONTROL, 0);
4922 }
4923
4924 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4925 {
4926         struct drm_device *dev = crtc->dev;
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4929         struct intel_encoder *encoder;
4930         int pipe = intel_crtc->pipe;
4931
4932         if (!intel_crtc->active)
4933                 return;
4934
4935         /*
4936          * Gen2 reports pipe underruns whenever all planes are disabled.
4937          * So diasble underrun reporting before all the planes get disabled.
4938          * FIXME: Need to fix the logic to work when we turn off all planes
4939          * but leave the pipe running.
4940          */
4941         if (IS_GEN2(dev))
4942                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4943
4944         /*
4945          * Vblank time updates from the shadow to live plane control register
4946          * are blocked if the memory self-refresh mode is active at that
4947          * moment. So to make sure the plane gets truly disabled, disable
4948          * first the self-refresh mode. The self-refresh enable bit in turn
4949          * will be checked/applied by the HW only at the next frame start
4950          * event which is after the vblank start event, so we need to have a
4951          * wait-for-vblank between disabling the plane and the pipe.
4952          */
4953         intel_set_memory_cxsr(dev_priv, false);
4954         intel_crtc_disable_planes(crtc);
4955
4956         for_each_encoder_on_crtc(dev, crtc, encoder)
4957                 encoder->disable(encoder);
4958
4959         /*
4960          * On gen2 planes are double buffered but the pipe isn't, so we must
4961          * wait for planes to fully turn off before disabling the pipe.
4962          * We also need to wait on all gmch platforms because of the
4963          * self-refresh mode constraint explained above.
4964          */
4965         intel_wait_for_vblank(dev, pipe);
4966
4967         intel_disable_pipe(intel_crtc);
4968
4969         i9xx_pfit_disable(intel_crtc);
4970
4971         for_each_encoder_on_crtc(dev, crtc, encoder)
4972                 if (encoder->post_disable)
4973                         encoder->post_disable(encoder);
4974
4975         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4976                 if (IS_CHERRYVIEW(dev))
4977                         chv_disable_pll(dev_priv, pipe);
4978                 else if (IS_VALLEYVIEW(dev))
4979                         vlv_disable_pll(dev_priv, pipe);
4980                 else
4981                         i9xx_disable_pll(intel_crtc);
4982         }
4983
4984         if (!IS_GEN2(dev))
4985                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4986
4987         intel_crtc->active = false;
4988         intel_update_watermarks(crtc);
4989
4990         mutex_lock(&dev->struct_mutex);
4991         intel_update_fbc(dev);
4992         mutex_unlock(&dev->struct_mutex);
4993 }
4994
4995 static void i9xx_crtc_off(struct drm_crtc *crtc)
4996 {
4997 }
4998
4999 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5000                                     bool enabled)
5001 {
5002         struct drm_device *dev = crtc->dev;
5003         struct drm_i915_master_private *master_priv;
5004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005         int pipe = intel_crtc->pipe;
5006
5007         if (!dev->primary->master)
5008                 return;
5009
5010         master_priv = dev->primary->master->driver_priv;
5011         if (!master_priv->sarea_priv)
5012                 return;
5013
5014         switch (pipe) {
5015         case 0:
5016                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5017                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5018                 break;
5019         case 1:
5020                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5021                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5022                 break;
5023         default:
5024                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5025                 break;
5026         }
5027 }
5028
5029 /* Master function to enable/disable CRTC and corresponding power wells */
5030 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5031 {
5032         struct drm_device *dev = crtc->dev;
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5035         enum intel_display_power_domain domain;
5036         unsigned long domains;
5037
5038         if (enable) {
5039                 if (!intel_crtc->active) {
5040                         domains = get_crtc_power_domains(crtc);
5041                         for_each_power_domain(domain, domains)
5042                                 intel_display_power_get(dev_priv, domain);
5043                         intel_crtc->enabled_power_domains = domains;
5044
5045                         dev_priv->display.crtc_enable(crtc);
5046                 }
5047         } else {
5048                 if (intel_crtc->active) {
5049                         dev_priv->display.crtc_disable(crtc);
5050
5051                         domains = intel_crtc->enabled_power_domains;
5052                         for_each_power_domain(domain, domains)
5053                                 intel_display_power_put(dev_priv, domain);
5054                         intel_crtc->enabled_power_domains = 0;
5055                 }
5056         }
5057 }
5058
5059 /**
5060  * Sets the power management mode of the pipe and plane.
5061  */
5062 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5063 {
5064         struct drm_device *dev = crtc->dev;
5065         struct intel_encoder *intel_encoder;
5066         bool enable = false;
5067
5068         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5069                 enable |= intel_encoder->connectors_active;
5070
5071         intel_crtc_control(crtc, enable);
5072
5073         intel_crtc_update_sarea(crtc, enable);
5074 }
5075
5076 static void intel_crtc_disable(struct drm_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->dev;
5079         struct drm_connector *connector;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5082         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5083
5084         /* crtc should still be enabled when we disable it. */
5085         WARN_ON(!crtc->enabled);
5086
5087         dev_priv->display.crtc_disable(crtc);
5088         intel_crtc_update_sarea(crtc, false);
5089         dev_priv->display.off(crtc);
5090
5091         if (crtc->primary->fb) {
5092                 mutex_lock(&dev->struct_mutex);
5093                 intel_unpin_fb_obj(old_obj);
5094                 i915_gem_track_fb(old_obj, NULL,
5095                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5096                 mutex_unlock(&dev->struct_mutex);
5097                 crtc->primary->fb = NULL;
5098         }
5099
5100         /* Update computed state. */
5101         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5102                 if (!connector->encoder || !connector->encoder->crtc)
5103                         continue;
5104
5105                 if (connector->encoder->crtc != crtc)
5106                         continue;
5107
5108                 connector->dpms = DRM_MODE_DPMS_OFF;
5109                 to_intel_encoder(connector->encoder)->connectors_active = false;
5110         }
5111 }
5112
5113 void intel_encoder_destroy(struct drm_encoder *encoder)
5114 {
5115         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5116
5117         drm_encoder_cleanup(encoder);
5118         kfree(intel_encoder);
5119 }
5120
5121 /* Simple dpms helper for encoders with just one connector, no cloning and only
5122  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5123  * state of the entire output pipe. */
5124 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5125 {
5126         if (mode == DRM_MODE_DPMS_ON) {
5127                 encoder->connectors_active = true;
5128
5129                 intel_crtc_update_dpms(encoder->base.crtc);
5130         } else {
5131                 encoder->connectors_active = false;
5132
5133                 intel_crtc_update_dpms(encoder->base.crtc);
5134         }
5135 }
5136
5137 /* Cross check the actual hw state with our own modeset state tracking (and it's
5138  * internal consistency). */
5139 static void intel_connector_check_state(struct intel_connector *connector)
5140 {
5141         if (connector->get_hw_state(connector)) {
5142                 struct intel_encoder *encoder = connector->encoder;
5143                 struct drm_crtc *crtc;
5144                 bool encoder_enabled;
5145                 enum pipe pipe;
5146
5147                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5148                               connector->base.base.id,
5149                               connector->base.name);
5150
5151                 /* there is no real hw state for MST connectors */
5152                 if (connector->mst_port)
5153                         return;
5154
5155                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5156                      "wrong connector dpms state\n");
5157                 WARN(connector->base.encoder != &encoder->base,
5158                      "active connector not linked to encoder\n");
5159
5160                 if (encoder) {
5161                         WARN(!encoder->connectors_active,
5162                              "encoder->connectors_active not set\n");
5163
5164                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5165                         WARN(!encoder_enabled, "encoder not enabled\n");
5166                         if (WARN_ON(!encoder->base.crtc))
5167                                 return;
5168
5169                         crtc = encoder->base.crtc;
5170
5171                         WARN(!crtc->enabled, "crtc not enabled\n");
5172                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5173                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5174                              "encoder active on the wrong pipe\n");
5175                 }
5176         }
5177 }
5178
5179 /* Even simpler default implementation, if there's really no special case to
5180  * consider. */
5181 void intel_connector_dpms(struct drm_connector *connector, int mode)
5182 {
5183         /* All the simple cases only support two dpms states. */
5184         if (mode != DRM_MODE_DPMS_ON)
5185                 mode = DRM_MODE_DPMS_OFF;
5186
5187         if (mode == connector->dpms)
5188                 return;
5189
5190         connector->dpms = mode;
5191
5192         /* Only need to change hw state when actually enabled */
5193         if (connector->encoder)
5194                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5195
5196         intel_modeset_check_state(connector->dev);
5197 }
5198
5199 /* Simple connector->get_hw_state implementation for encoders that support only
5200  * one connector and no cloning and hence the encoder state determines the state
5201  * of the connector. */
5202 bool intel_connector_get_hw_state(struct intel_connector *connector)
5203 {
5204         enum pipe pipe = 0;
5205         struct intel_encoder *encoder = connector->encoder;
5206
5207         return encoder->get_hw_state(encoder, &pipe);
5208 }
5209
5210 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5211                                      struct intel_crtc_config *pipe_config)
5212 {
5213         struct drm_i915_private *dev_priv = dev->dev_private;
5214         struct intel_crtc *pipe_B_crtc =
5215                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5216
5217         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5218                       pipe_name(pipe), pipe_config->fdi_lanes);
5219         if (pipe_config->fdi_lanes > 4) {
5220                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5221                               pipe_name(pipe), pipe_config->fdi_lanes);
5222                 return false;
5223         }
5224
5225         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5226                 if (pipe_config->fdi_lanes > 2) {
5227                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5228                                       pipe_config->fdi_lanes);
5229                         return false;
5230                 } else {
5231                         return true;
5232                 }
5233         }
5234
5235         if (INTEL_INFO(dev)->num_pipes == 2)
5236                 return true;
5237
5238         /* Ivybridge 3 pipe is really complicated */
5239         switch (pipe) {
5240         case PIPE_A:
5241                 return true;
5242         case PIPE_B:
5243                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5244                     pipe_config->fdi_lanes > 2) {
5245                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5246                                       pipe_name(pipe), pipe_config->fdi_lanes);
5247                         return false;
5248                 }
5249                 return true;
5250         case PIPE_C:
5251                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5252                     pipe_B_crtc->config.fdi_lanes <= 2) {
5253                         if (pipe_config->fdi_lanes > 2) {
5254                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5255                                               pipe_name(pipe), pipe_config->fdi_lanes);
5256                                 return false;
5257                         }
5258                 } else {
5259                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5260                         return false;
5261                 }
5262                 return true;
5263         default:
5264                 BUG();
5265         }
5266 }
5267
5268 #define RETRY 1
5269 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5270                                        struct intel_crtc_config *pipe_config)
5271 {
5272         struct drm_device *dev = intel_crtc->base.dev;
5273         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5274         int lane, link_bw, fdi_dotclock;
5275         bool setup_ok, needs_recompute = false;
5276
5277 retry:
5278         /* FDI is a binary signal running at ~2.7GHz, encoding
5279          * each output octet as 10 bits. The actual frequency
5280          * is stored as a divider into a 100MHz clock, and the
5281          * mode pixel clock is stored in units of 1KHz.
5282          * Hence the bw of each lane in terms of the mode signal
5283          * is:
5284          */
5285         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5286
5287         fdi_dotclock = adjusted_mode->crtc_clock;
5288
5289         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5290                                            pipe_config->pipe_bpp);
5291
5292         pipe_config->fdi_lanes = lane;
5293
5294         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5295                                link_bw, &pipe_config->fdi_m_n);
5296
5297         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5298                                             intel_crtc->pipe, pipe_config);
5299         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5300                 pipe_config->pipe_bpp -= 2*3;
5301                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5302                               pipe_config->pipe_bpp);
5303                 needs_recompute = true;
5304                 pipe_config->bw_constrained = true;
5305
5306                 goto retry;
5307         }
5308
5309         if (needs_recompute)
5310                 return RETRY;
5311
5312         return setup_ok ? 0 : -EINVAL;
5313 }
5314
5315 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5316                                    struct intel_crtc_config *pipe_config)
5317 {
5318         pipe_config->ips_enabled = i915.enable_ips &&
5319                                    hsw_crtc_supports_ips(crtc) &&
5320                                    pipe_config->pipe_bpp <= 24;
5321 }
5322
5323 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5324                                      struct intel_crtc_config *pipe_config)
5325 {
5326         struct drm_device *dev = crtc->base.dev;
5327         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5328
5329         /* FIXME should check pixel clock limits on all platforms */
5330         if (INTEL_INFO(dev)->gen < 4) {
5331                 struct drm_i915_private *dev_priv = dev->dev_private;
5332                 int clock_limit =
5333                         dev_priv->display.get_display_clock_speed(dev);
5334
5335                 /*
5336                  * Enable pixel doubling when the dot clock
5337                  * is > 90% of the (display) core speed.
5338                  *
5339                  * GDG double wide on either pipe,
5340                  * otherwise pipe A only.
5341                  */
5342                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5343                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5344                         clock_limit *= 2;
5345                         pipe_config->double_wide = true;
5346                 }
5347
5348                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5349                         return -EINVAL;
5350         }
5351
5352         /*
5353          * Pipe horizontal size must be even in:
5354          * - DVO ganged mode
5355          * - LVDS dual channel mode
5356          * - Double wide pipe
5357          */
5358         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5359              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5360                 pipe_config->pipe_src_w &= ~1;
5361
5362         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5363          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5364          */
5365         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5366                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5367                 return -EINVAL;
5368
5369         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5370                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5371         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5372                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5373                  * for lvds. */
5374                 pipe_config->pipe_bpp = 8*3;
5375         }
5376
5377         if (HAS_IPS(dev))
5378                 hsw_compute_ips_config(crtc, pipe_config);
5379
5380         /*
5381          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5382          * old clock survives for now.
5383          */
5384         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5385                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5386
5387         if (pipe_config->has_pch_encoder)
5388                 return ironlake_fdi_compute_config(crtc, pipe_config);
5389
5390         return 0;
5391 }
5392
5393 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5394 {
5395         struct drm_i915_private *dev_priv = dev->dev_private;
5396         int vco = valleyview_get_vco(dev_priv);
5397         u32 val;
5398         int divider;
5399
5400         /* FIXME: Punit isn't quite ready yet */
5401         if (IS_CHERRYVIEW(dev))
5402                 return 400000;
5403
5404         mutex_lock(&dev_priv->dpio_lock);
5405         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5406         mutex_unlock(&dev_priv->dpio_lock);
5407
5408         divider = val & DISPLAY_FREQUENCY_VALUES;
5409
5410         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5411              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5412              "cdclk change in progress\n");
5413
5414         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5415 }
5416
5417 static int i945_get_display_clock_speed(struct drm_device *dev)
5418 {
5419         return 400000;
5420 }
5421
5422 static int i915_get_display_clock_speed(struct drm_device *dev)
5423 {
5424         return 333000;
5425 }
5426
5427 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5428 {
5429         return 200000;
5430 }
5431
5432 static int pnv_get_display_clock_speed(struct drm_device *dev)
5433 {
5434         u16 gcfgc = 0;
5435
5436         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5437
5438         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5439         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5440                 return 267000;
5441         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5442                 return 333000;
5443         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5444                 return 444000;
5445         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5446                 return 200000;
5447         default:
5448                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5449         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5450                 return 133000;
5451         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5452                 return 167000;
5453         }
5454 }
5455
5456 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5457 {
5458         u16 gcfgc = 0;
5459
5460         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5461
5462         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5463                 return 133000;
5464         else {
5465                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5466                 case GC_DISPLAY_CLOCK_333_MHZ:
5467                         return 333000;
5468                 default:
5469                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5470                         return 190000;
5471                 }
5472         }
5473 }
5474
5475 static int i865_get_display_clock_speed(struct drm_device *dev)
5476 {
5477         return 266000;
5478 }
5479
5480 static int i855_get_display_clock_speed(struct drm_device *dev)
5481 {
5482         u16 hpllcc = 0;
5483         /* Assume that the hardware is in the high speed state.  This
5484          * should be the default.
5485          */
5486         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5487         case GC_CLOCK_133_200:
5488         case GC_CLOCK_100_200:
5489                 return 200000;
5490         case GC_CLOCK_166_250:
5491                 return 250000;
5492         case GC_CLOCK_100_133:
5493                 return 133000;
5494         }
5495
5496         /* Shouldn't happen */
5497         return 0;
5498 }
5499
5500 static int i830_get_display_clock_speed(struct drm_device *dev)
5501 {
5502         return 133000;
5503 }
5504
5505 static void
5506 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5507 {
5508         while (*num > DATA_LINK_M_N_MASK ||
5509                *den > DATA_LINK_M_N_MASK) {
5510                 *num >>= 1;
5511                 *den >>= 1;
5512         }
5513 }
5514
5515 static void compute_m_n(unsigned int m, unsigned int n,
5516                         uint32_t *ret_m, uint32_t *ret_n)
5517 {
5518         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5519         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5520         intel_reduce_m_n_ratio(ret_m, ret_n);
5521 }
5522
5523 void
5524 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5525                        int pixel_clock, int link_clock,
5526                        struct intel_link_m_n *m_n)
5527 {
5528         m_n->tu = 64;
5529
5530         compute_m_n(bits_per_pixel * pixel_clock,
5531                     link_clock * nlanes * 8,
5532                     &m_n->gmch_m, &m_n->gmch_n);
5533
5534         compute_m_n(pixel_clock, link_clock,
5535                     &m_n->link_m, &m_n->link_n);
5536 }
5537
5538 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5539 {
5540         if (i915.panel_use_ssc >= 0)
5541                 return i915.panel_use_ssc != 0;
5542         return dev_priv->vbt.lvds_use_ssc
5543                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5544 }
5545
5546 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5547 {
5548         struct drm_device *dev = crtc->dev;
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         int refclk;
5551
5552         if (IS_VALLEYVIEW(dev)) {
5553                 refclk = 100000;
5554         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5555             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5556                 refclk = dev_priv->vbt.lvds_ssc_freq;
5557                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5558         } else if (!IS_GEN2(dev)) {
5559                 refclk = 96000;
5560         } else {
5561                 refclk = 48000;
5562         }
5563
5564         return refclk;
5565 }
5566
5567 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5568 {
5569         return (1 << dpll->n) << 16 | dpll->m2;
5570 }
5571
5572 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5573 {
5574         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5575 }
5576
5577 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5578                                      intel_clock_t *reduced_clock)
5579 {
5580         struct drm_device *dev = crtc->base.dev;
5581         u32 fp, fp2 = 0;
5582
5583         if (IS_PINEVIEW(dev)) {
5584                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5585                 if (reduced_clock)
5586                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5587         } else {
5588                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5589                 if (reduced_clock)
5590                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5591         }
5592
5593         crtc->config.dpll_hw_state.fp0 = fp;
5594
5595         crtc->lowfreq_avail = false;
5596         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5597             reduced_clock && i915.powersave) {
5598                 crtc->config.dpll_hw_state.fp1 = fp2;
5599                 crtc->lowfreq_avail = true;
5600         } else {
5601                 crtc->config.dpll_hw_state.fp1 = fp;
5602         }
5603 }
5604
5605 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5606                 pipe)
5607 {
5608         u32 reg_val;
5609
5610         /*
5611          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5612          * and set it to a reasonable value instead.
5613          */
5614         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5615         reg_val &= 0xffffff00;
5616         reg_val |= 0x00000030;
5617         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5618
5619         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5620         reg_val &= 0x8cffffff;
5621         reg_val = 0x8c000000;
5622         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5623
5624         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5625         reg_val &= 0xffffff00;
5626         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5627
5628         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5629         reg_val &= 0x00ffffff;
5630         reg_val |= 0xb0000000;
5631         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5632 }
5633
5634 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5635                                          struct intel_link_m_n *m_n)
5636 {
5637         struct drm_device *dev = crtc->base.dev;
5638         struct drm_i915_private *dev_priv = dev->dev_private;
5639         int pipe = crtc->pipe;
5640
5641         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5642         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5643         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5644         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5645 }
5646
5647 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5648                                          struct intel_link_m_n *m_n,
5649                                          struct intel_link_m_n *m2_n2)
5650 {
5651         struct drm_device *dev = crtc->base.dev;
5652         struct drm_i915_private *dev_priv = dev->dev_private;
5653         int pipe = crtc->pipe;
5654         enum transcoder transcoder = crtc->config.cpu_transcoder;
5655
5656         if (INTEL_INFO(dev)->gen >= 5) {
5657                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5658                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5659                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5660                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5661                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5662                  * for gen < 8) and if DRRS is supported (to make sure the
5663                  * registers are not unnecessarily accessed).
5664                  */
5665                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5666                         crtc->config.has_drrs) {
5667                         I915_WRITE(PIPE_DATA_M2(transcoder),
5668                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5669                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5670                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5671                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5672                 }
5673         } else {
5674                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5675                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5676                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5677                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5678         }
5679 }
5680
5681 void intel_dp_set_m_n(struct intel_crtc *crtc)
5682 {
5683         if (crtc->config.has_pch_encoder)
5684                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5685         else
5686                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5687                                                    &crtc->config.dp_m2_n2);
5688 }
5689
5690 static void vlv_update_pll(struct intel_crtc *crtc)
5691 {
5692         u32 dpll, dpll_md;
5693
5694         /*
5695          * Enable DPIO clock input. We should never disable the reference
5696          * clock for pipe B, since VGA hotplug / manual detection depends
5697          * on it.
5698          */
5699         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5700                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5701         /* We should never disable this, set it here for state tracking */
5702         if (crtc->pipe == PIPE_B)
5703                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5704         dpll |= DPLL_VCO_ENABLE;
5705         crtc->config.dpll_hw_state.dpll = dpll;
5706
5707         dpll_md = (crtc->config.pixel_multiplier - 1)
5708                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5709         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5710 }
5711
5712 static void vlv_prepare_pll(struct intel_crtc *crtc)
5713 {
5714         struct drm_device *dev = crtc->base.dev;
5715         struct drm_i915_private *dev_priv = dev->dev_private;
5716         int pipe = crtc->pipe;
5717         u32 mdiv;
5718         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5719         u32 coreclk, reg_val;
5720
5721         mutex_lock(&dev_priv->dpio_lock);
5722
5723         bestn = crtc->config.dpll.n;
5724         bestm1 = crtc->config.dpll.m1;
5725         bestm2 = crtc->config.dpll.m2;
5726         bestp1 = crtc->config.dpll.p1;
5727         bestp2 = crtc->config.dpll.p2;
5728
5729         /* See eDP HDMI DPIO driver vbios notes doc */
5730
5731         /* PLL B needs special handling */
5732         if (pipe == PIPE_B)
5733                 vlv_pllb_recal_opamp(dev_priv, pipe);
5734
5735         /* Set up Tx target for periodic Rcomp update */
5736         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5737
5738         /* Disable target IRef on PLL */
5739         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5740         reg_val &= 0x00ffffff;
5741         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5742
5743         /* Disable fast lock */
5744         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5745
5746         /* Set idtafcrecal before PLL is enabled */
5747         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5748         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5749         mdiv |= ((bestn << DPIO_N_SHIFT));
5750         mdiv |= (1 << DPIO_K_SHIFT);
5751
5752         /*
5753          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5754          * but we don't support that).
5755          * Note: don't use the DAC post divider as it seems unstable.
5756          */
5757         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5758         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5759
5760         mdiv |= DPIO_ENABLE_CALIBRATION;
5761         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5762
5763         /* Set HBR and RBR LPF coefficients */
5764         if (crtc->config.port_clock == 162000 ||
5765             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5766             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5767                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5768                                  0x009f0003);
5769         else
5770                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5771                                  0x00d0000f);
5772
5773         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5774             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5775                 /* Use SSC source */
5776                 if (pipe == PIPE_A)
5777                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5778                                          0x0df40000);
5779                 else
5780                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5781                                          0x0df70000);
5782         } else { /* HDMI or VGA */
5783                 /* Use bend source */
5784                 if (pipe == PIPE_A)
5785                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5786                                          0x0df70000);
5787                 else
5788                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5789                                          0x0df40000);
5790         }
5791
5792         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5793         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5794         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5795             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5796                 coreclk |= 0x01000000;
5797         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5798
5799         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5800         mutex_unlock(&dev_priv->dpio_lock);
5801 }
5802
5803 static void chv_update_pll(struct intel_crtc *crtc)
5804 {
5805         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5806                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5807                 DPLL_VCO_ENABLE;
5808         if (crtc->pipe != PIPE_A)
5809                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5810
5811         crtc->config.dpll_hw_state.dpll_md =
5812                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5813 }
5814
5815 static void chv_prepare_pll(struct intel_crtc *crtc)
5816 {
5817         struct drm_device *dev = crtc->base.dev;
5818         struct drm_i915_private *dev_priv = dev->dev_private;
5819         int pipe = crtc->pipe;
5820         int dpll_reg = DPLL(crtc->pipe);
5821         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5822         u32 loopfilter, intcoeff;
5823         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5824         int refclk;
5825
5826         bestn = crtc->config.dpll.n;
5827         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5828         bestm1 = crtc->config.dpll.m1;
5829         bestm2 = crtc->config.dpll.m2 >> 22;
5830         bestp1 = crtc->config.dpll.p1;
5831         bestp2 = crtc->config.dpll.p2;
5832
5833         /*
5834          * Enable Refclk and SSC
5835          */
5836         I915_WRITE(dpll_reg,
5837                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5838
5839         mutex_lock(&dev_priv->dpio_lock);
5840
5841         /* p1 and p2 divider */
5842         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5843                         5 << DPIO_CHV_S1_DIV_SHIFT |
5844                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5845                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5846                         1 << DPIO_CHV_K_DIV_SHIFT);
5847
5848         /* Feedback post-divider - m2 */
5849         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5850
5851         /* Feedback refclk divider - n and m1 */
5852         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5853                         DPIO_CHV_M1_DIV_BY_2 |
5854                         1 << DPIO_CHV_N_DIV_SHIFT);
5855
5856         /* M2 fraction division */
5857         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5858
5859         /* M2 fraction division enable */
5860         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5861                        DPIO_CHV_FRAC_DIV_EN |
5862                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5863
5864         /* Loop filter */
5865         refclk = i9xx_get_refclk(&crtc->base, 0);
5866         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5867                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5868         if (refclk == 100000)
5869                 intcoeff = 11;
5870         else if (refclk == 38400)
5871                 intcoeff = 10;
5872         else
5873                 intcoeff = 9;
5874         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5875         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5876
5877         /* AFC Recal */
5878         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5879                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5880                         DPIO_AFC_RECAL);
5881
5882         mutex_unlock(&dev_priv->dpio_lock);
5883 }
5884
5885 static void i9xx_update_pll(struct intel_crtc *crtc,
5886                             intel_clock_t *reduced_clock,
5887                             int num_connectors)
5888 {
5889         struct drm_device *dev = crtc->base.dev;
5890         struct drm_i915_private *dev_priv = dev->dev_private;
5891         u32 dpll;
5892         bool is_sdvo;
5893         struct dpll *clock = &crtc->config.dpll;
5894
5895         i9xx_update_pll_dividers(crtc, reduced_clock);
5896
5897         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5898                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5899
5900         dpll = DPLL_VGA_MODE_DIS;
5901
5902         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5903                 dpll |= DPLLB_MODE_LVDS;
5904         else
5905                 dpll |= DPLLB_MODE_DAC_SERIAL;
5906
5907         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5908                 dpll |= (crtc->config.pixel_multiplier - 1)
5909                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5910         }
5911
5912         if (is_sdvo)
5913                 dpll |= DPLL_SDVO_HIGH_SPEED;
5914
5915         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5916                 dpll |= DPLL_SDVO_HIGH_SPEED;
5917
5918         /* compute bitmask from p1 value */
5919         if (IS_PINEVIEW(dev))
5920                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5921         else {
5922                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5923                 if (IS_G4X(dev) && reduced_clock)
5924                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5925         }
5926         switch (clock->p2) {
5927         case 5:
5928                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5929                 break;
5930         case 7:
5931                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5932                 break;
5933         case 10:
5934                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5935                 break;
5936         case 14:
5937                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5938                 break;
5939         }
5940         if (INTEL_INFO(dev)->gen >= 4)
5941                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5942
5943         if (crtc->config.sdvo_tv_clock)
5944                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5945         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5946                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5947                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5948         else
5949                 dpll |= PLL_REF_INPUT_DREFCLK;
5950
5951         dpll |= DPLL_VCO_ENABLE;
5952         crtc->config.dpll_hw_state.dpll = dpll;
5953
5954         if (INTEL_INFO(dev)->gen >= 4) {
5955                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5956                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5957                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5958         }
5959 }
5960
5961 static void i8xx_update_pll(struct intel_crtc *crtc,
5962                             intel_clock_t *reduced_clock,
5963                             int num_connectors)
5964 {
5965         struct drm_device *dev = crtc->base.dev;
5966         struct drm_i915_private *dev_priv = dev->dev_private;
5967         u32 dpll;
5968         struct dpll *clock = &crtc->config.dpll;
5969
5970         i9xx_update_pll_dividers(crtc, reduced_clock);
5971
5972         dpll = DPLL_VGA_MODE_DIS;
5973
5974         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5975                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5976         } else {
5977                 if (clock->p1 == 2)
5978                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5979                 else
5980                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5981                 if (clock->p2 == 4)
5982                         dpll |= PLL_P2_DIVIDE_BY_4;
5983         }
5984
5985         if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5986                 dpll |= DPLL_DVO_2X_MODE;
5987
5988         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5989                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5990                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5991         else
5992                 dpll |= PLL_REF_INPUT_DREFCLK;
5993
5994         dpll |= DPLL_VCO_ENABLE;
5995         crtc->config.dpll_hw_state.dpll = dpll;
5996 }
5997
5998 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5999 {
6000         struct drm_device *dev = intel_crtc->base.dev;
6001         struct drm_i915_private *dev_priv = dev->dev_private;
6002         enum pipe pipe = intel_crtc->pipe;
6003         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6004         struct drm_display_mode *adjusted_mode =
6005                 &intel_crtc->config.adjusted_mode;
6006         uint32_t crtc_vtotal, crtc_vblank_end;
6007         int vsyncshift = 0;
6008
6009         /* We need to be careful not to changed the adjusted mode, for otherwise
6010          * the hw state checker will get angry at the mismatch. */
6011         crtc_vtotal = adjusted_mode->crtc_vtotal;
6012         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6013
6014         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6015                 /* the chip adds 2 halflines automatically */
6016                 crtc_vtotal -= 1;
6017                 crtc_vblank_end -= 1;
6018
6019                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6020                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6021                 else
6022                         vsyncshift = adjusted_mode->crtc_hsync_start -
6023                                 adjusted_mode->crtc_htotal / 2;
6024                 if (vsyncshift < 0)
6025                         vsyncshift += adjusted_mode->crtc_htotal;
6026         }
6027
6028         if (INTEL_INFO(dev)->gen > 3)
6029                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6030
6031         I915_WRITE(HTOTAL(cpu_transcoder),
6032                    (adjusted_mode->crtc_hdisplay - 1) |
6033                    ((adjusted_mode->crtc_htotal - 1) << 16));
6034         I915_WRITE(HBLANK(cpu_transcoder),
6035                    (adjusted_mode->crtc_hblank_start - 1) |
6036                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6037         I915_WRITE(HSYNC(cpu_transcoder),
6038                    (adjusted_mode->crtc_hsync_start - 1) |
6039                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6040
6041         I915_WRITE(VTOTAL(cpu_transcoder),
6042                    (adjusted_mode->crtc_vdisplay - 1) |
6043                    ((crtc_vtotal - 1) << 16));
6044         I915_WRITE(VBLANK(cpu_transcoder),
6045                    (adjusted_mode->crtc_vblank_start - 1) |
6046                    ((crtc_vblank_end - 1) << 16));
6047         I915_WRITE(VSYNC(cpu_transcoder),
6048                    (adjusted_mode->crtc_vsync_start - 1) |
6049                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6050
6051         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6052          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6053          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6054          * bits. */
6055         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6056             (pipe == PIPE_B || pipe == PIPE_C))
6057                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6058
6059         /* pipesrc controls the size that is scaled from, which should
6060          * always be the user's requested size.
6061          */
6062         I915_WRITE(PIPESRC(pipe),
6063                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6064                    (intel_crtc->config.pipe_src_h - 1));
6065 }
6066
6067 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6068                                    struct intel_crtc_config *pipe_config)
6069 {
6070         struct drm_device *dev = crtc->base.dev;
6071         struct drm_i915_private *dev_priv = dev->dev_private;
6072         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6073         uint32_t tmp;
6074
6075         tmp = I915_READ(HTOTAL(cpu_transcoder));
6076         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6077         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6078         tmp = I915_READ(HBLANK(cpu_transcoder));
6079         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6080         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6081         tmp = I915_READ(HSYNC(cpu_transcoder));
6082         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6083         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6084
6085         tmp = I915_READ(VTOTAL(cpu_transcoder));
6086         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6087         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6088         tmp = I915_READ(VBLANK(cpu_transcoder));
6089         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6090         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6091         tmp = I915_READ(VSYNC(cpu_transcoder));
6092         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6093         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6094
6095         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6096                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6097                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6098                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6099         }
6100
6101         tmp = I915_READ(PIPESRC(crtc->pipe));
6102         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6103         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6104
6105         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6106         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6107 }
6108
6109 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6110                                  struct intel_crtc_config *pipe_config)
6111 {
6112         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6113         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6114         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6115         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6116
6117         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6118         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6119         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6120         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6121
6122         mode->flags = pipe_config->adjusted_mode.flags;
6123
6124         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6125         mode->flags |= pipe_config->adjusted_mode.flags;
6126 }
6127
6128 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6129 {
6130         struct drm_device *dev = intel_crtc->base.dev;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132         uint32_t pipeconf;
6133
6134         pipeconf = 0;
6135
6136         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6137             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6138                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6139
6140         if (intel_crtc->config.double_wide)
6141                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6142
6143         /* only g4x and later have fancy bpc/dither controls */
6144         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6145                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6146                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6147                         pipeconf |= PIPECONF_DITHER_EN |
6148                                     PIPECONF_DITHER_TYPE_SP;
6149
6150                 switch (intel_crtc->config.pipe_bpp) {
6151                 case 18:
6152                         pipeconf |= PIPECONF_6BPC;
6153                         break;
6154                 case 24:
6155                         pipeconf |= PIPECONF_8BPC;
6156                         break;
6157                 case 30:
6158                         pipeconf |= PIPECONF_10BPC;
6159                         break;
6160                 default:
6161                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6162                         BUG();
6163                 }
6164         }
6165
6166         if (HAS_PIPE_CXSR(dev)) {
6167                 if (intel_crtc->lowfreq_avail) {
6168                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6169                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6170                 } else {
6171                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6172                 }
6173         }
6174
6175         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6176                 if (INTEL_INFO(dev)->gen < 4 ||
6177                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6178                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6179                 else
6180                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6181         } else
6182                 pipeconf |= PIPECONF_PROGRESSIVE;
6183
6184         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6185                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6186
6187         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6188         POSTING_READ(PIPECONF(intel_crtc->pipe));
6189 }
6190
6191 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6192                               int x, int y,
6193                               struct drm_framebuffer *fb)
6194 {
6195         struct drm_device *dev = crtc->dev;
6196         struct drm_i915_private *dev_priv = dev->dev_private;
6197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198         int refclk, num_connectors = 0;
6199         intel_clock_t clock, reduced_clock;
6200         bool ok, has_reduced_clock = false;
6201         bool is_lvds = false, is_dsi = false;
6202         struct intel_encoder *encoder;
6203         const intel_limit_t *limit;
6204
6205         for_each_encoder_on_crtc(dev, crtc, encoder) {
6206                 switch (encoder->type) {
6207                 case INTEL_OUTPUT_LVDS:
6208                         is_lvds = true;
6209                         break;
6210                 case INTEL_OUTPUT_DSI:
6211                         is_dsi = true;
6212                         break;
6213                 }
6214
6215                 num_connectors++;
6216         }
6217
6218         if (is_dsi)
6219                 return 0;
6220
6221         if (!intel_crtc->config.clock_set) {
6222                 refclk = i9xx_get_refclk(crtc, num_connectors);
6223
6224                 /*
6225                  * Returns a set of divisors for the desired target clock with
6226                  * the given refclk, or FALSE.  The returned values represent
6227                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6228                  * 2) / p1 / p2.
6229                  */
6230                 limit = intel_limit(crtc, refclk);
6231                 ok = dev_priv->display.find_dpll(limit, crtc,
6232                                                  intel_crtc->config.port_clock,
6233                                                  refclk, NULL, &clock);
6234                 if (!ok) {
6235                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6236                         return -EINVAL;
6237                 }
6238
6239                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6240                         /*
6241                          * Ensure we match the reduced clock's P to the target
6242                          * clock.  If the clocks don't match, we can't switch
6243                          * the display clock by using the FP0/FP1. In such case
6244                          * we will disable the LVDS downclock feature.
6245                          */
6246                         has_reduced_clock =
6247                                 dev_priv->display.find_dpll(limit, crtc,
6248                                                             dev_priv->lvds_downclock,
6249                                                             refclk, &clock,
6250                                                             &reduced_clock);
6251                 }
6252                 /* Compat-code for transition, will disappear. */
6253                 intel_crtc->config.dpll.n = clock.n;
6254                 intel_crtc->config.dpll.m1 = clock.m1;
6255                 intel_crtc->config.dpll.m2 = clock.m2;
6256                 intel_crtc->config.dpll.p1 = clock.p1;
6257                 intel_crtc->config.dpll.p2 = clock.p2;
6258         }
6259
6260         if (IS_GEN2(dev)) {
6261                 i8xx_update_pll(intel_crtc,
6262                                 has_reduced_clock ? &reduced_clock : NULL,
6263                                 num_connectors);
6264         } else if (IS_CHERRYVIEW(dev)) {
6265                 chv_update_pll(intel_crtc);
6266         } else if (IS_VALLEYVIEW(dev)) {
6267                 vlv_update_pll(intel_crtc);
6268         } else {
6269                 i9xx_update_pll(intel_crtc,
6270                                 has_reduced_clock ? &reduced_clock : NULL,
6271                                 num_connectors);
6272         }
6273
6274         return 0;
6275 }
6276
6277 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6278                                  struct intel_crtc_config *pipe_config)
6279 {
6280         struct drm_device *dev = crtc->base.dev;
6281         struct drm_i915_private *dev_priv = dev->dev_private;
6282         uint32_t tmp;
6283
6284         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6285                 return;
6286
6287         tmp = I915_READ(PFIT_CONTROL);
6288         if (!(tmp & PFIT_ENABLE))
6289                 return;
6290
6291         /* Check whether the pfit is attached to our pipe. */
6292         if (INTEL_INFO(dev)->gen < 4) {
6293                 if (crtc->pipe != PIPE_B)
6294                         return;
6295         } else {
6296                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6297                         return;
6298         }
6299
6300         pipe_config->gmch_pfit.control = tmp;
6301         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6302         if (INTEL_INFO(dev)->gen < 5)
6303                 pipe_config->gmch_pfit.lvds_border_bits =
6304                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6305 }
6306
6307 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6308                                struct intel_crtc_config *pipe_config)
6309 {
6310         struct drm_device *dev = crtc->base.dev;
6311         struct drm_i915_private *dev_priv = dev->dev_private;
6312         int pipe = pipe_config->cpu_transcoder;
6313         intel_clock_t clock;
6314         u32 mdiv;
6315         int refclk = 100000;
6316
6317         /* In case of MIPI DPLL will not even be used */
6318         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6319                 return;
6320
6321         mutex_lock(&dev_priv->dpio_lock);
6322         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6323         mutex_unlock(&dev_priv->dpio_lock);
6324
6325         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6326         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6327         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6328         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6329         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6330
6331         vlv_clock(refclk, &clock);
6332
6333         /* clock.dot is the fast clock */
6334         pipe_config->port_clock = clock.dot / 5;
6335 }
6336
6337 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6338                                   struct intel_plane_config *plane_config)
6339 {
6340         struct drm_device *dev = crtc->base.dev;
6341         struct drm_i915_private *dev_priv = dev->dev_private;
6342         u32 val, base, offset;
6343         int pipe = crtc->pipe, plane = crtc->plane;
6344         int fourcc, pixel_format;
6345         int aligned_height;
6346
6347         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6348         if (!crtc->base.primary->fb) {
6349                 DRM_DEBUG_KMS("failed to alloc fb\n");
6350                 return;
6351         }
6352
6353         val = I915_READ(DSPCNTR(plane));
6354
6355         if (INTEL_INFO(dev)->gen >= 4)
6356                 if (val & DISPPLANE_TILED)
6357                         plane_config->tiled = true;
6358
6359         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6360         fourcc = intel_format_to_fourcc(pixel_format);
6361         crtc->base.primary->fb->pixel_format = fourcc;
6362         crtc->base.primary->fb->bits_per_pixel =
6363                 drm_format_plane_cpp(fourcc, 0) * 8;
6364
6365         if (INTEL_INFO(dev)->gen >= 4) {
6366                 if (plane_config->tiled)
6367                         offset = I915_READ(DSPTILEOFF(plane));
6368                 else
6369                         offset = I915_READ(DSPLINOFF(plane));
6370                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6371         } else {
6372                 base = I915_READ(DSPADDR(plane));
6373         }
6374         plane_config->base = base;
6375
6376         val = I915_READ(PIPESRC(pipe));
6377         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6378         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6379
6380         val = I915_READ(DSPSTRIDE(pipe));
6381         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6382
6383         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6384                                             plane_config->tiled);
6385
6386         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6387                                         aligned_height);
6388
6389         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6390                       pipe, plane, crtc->base.primary->fb->width,
6391                       crtc->base.primary->fb->height,
6392                       crtc->base.primary->fb->bits_per_pixel, base,
6393                       crtc->base.primary->fb->pitches[0],
6394                       plane_config->size);
6395
6396 }
6397
6398 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6399                                struct intel_crtc_config *pipe_config)
6400 {
6401         struct drm_device *dev = crtc->base.dev;
6402         struct drm_i915_private *dev_priv = dev->dev_private;
6403         int pipe = pipe_config->cpu_transcoder;
6404         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6405         intel_clock_t clock;
6406         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6407         int refclk = 100000;
6408
6409         mutex_lock(&dev_priv->dpio_lock);
6410         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6411         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6412         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6413         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6414         mutex_unlock(&dev_priv->dpio_lock);
6415
6416         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6417         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6418         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6419         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6420         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6421
6422         chv_clock(refclk, &clock);
6423
6424         /* clock.dot is the fast clock */
6425         pipe_config->port_clock = clock.dot / 5;
6426 }
6427
6428 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6429                                  struct intel_crtc_config *pipe_config)
6430 {
6431         struct drm_device *dev = crtc->base.dev;
6432         struct drm_i915_private *dev_priv = dev->dev_private;
6433         uint32_t tmp;
6434
6435         if (!intel_display_power_enabled(dev_priv,
6436                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6437                 return false;
6438
6439         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6440         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6441
6442         tmp = I915_READ(PIPECONF(crtc->pipe));
6443         if (!(tmp & PIPECONF_ENABLE))
6444                 return false;
6445
6446         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6447                 switch (tmp & PIPECONF_BPC_MASK) {
6448                 case PIPECONF_6BPC:
6449                         pipe_config->pipe_bpp = 18;
6450                         break;
6451                 case PIPECONF_8BPC:
6452                         pipe_config->pipe_bpp = 24;
6453                         break;
6454                 case PIPECONF_10BPC:
6455                         pipe_config->pipe_bpp = 30;
6456                         break;
6457                 default:
6458                         break;
6459                 }
6460         }
6461
6462         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6463                 pipe_config->limited_color_range = true;
6464
6465         if (INTEL_INFO(dev)->gen < 4)
6466                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6467
6468         intel_get_pipe_timings(crtc, pipe_config);
6469
6470         i9xx_get_pfit_config(crtc, pipe_config);
6471
6472         if (INTEL_INFO(dev)->gen >= 4) {
6473                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6474                 pipe_config->pixel_multiplier =
6475                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6476                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6477                 pipe_config->dpll_hw_state.dpll_md = tmp;
6478         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6479                 tmp = I915_READ(DPLL(crtc->pipe));
6480                 pipe_config->pixel_multiplier =
6481                         ((tmp & SDVO_MULTIPLIER_MASK)
6482                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6483         } else {
6484                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6485                  * port and will be fixed up in the encoder->get_config
6486                  * function. */
6487                 pipe_config->pixel_multiplier = 1;
6488         }
6489         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6490         if (!IS_VALLEYVIEW(dev)) {
6491                 /*
6492                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6493                  * on 830. Filter it out here so that we don't
6494                  * report errors due to that.
6495                  */
6496                 if (IS_I830(dev))
6497                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6498
6499                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6500                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6501         } else {
6502                 /* Mask out read-only status bits. */
6503                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6504                                                      DPLL_PORTC_READY_MASK |
6505                                                      DPLL_PORTB_READY_MASK);
6506         }
6507
6508         if (IS_CHERRYVIEW(dev))
6509                 chv_crtc_clock_get(crtc, pipe_config);
6510         else if (IS_VALLEYVIEW(dev))
6511                 vlv_crtc_clock_get(crtc, pipe_config);
6512         else
6513                 i9xx_crtc_clock_get(crtc, pipe_config);
6514
6515         return true;
6516 }
6517
6518 static void ironlake_init_pch_refclk(struct drm_device *dev)
6519 {
6520         struct drm_i915_private *dev_priv = dev->dev_private;
6521         struct intel_encoder *encoder;
6522         u32 val, final;
6523         bool has_lvds = false;
6524         bool has_cpu_edp = false;
6525         bool has_panel = false;
6526         bool has_ck505 = false;
6527         bool can_ssc = false;
6528
6529         /* We need to take the global config into account */
6530         for_each_intel_encoder(dev, encoder) {
6531                 switch (encoder->type) {
6532                 case INTEL_OUTPUT_LVDS:
6533                         has_panel = true;
6534                         has_lvds = true;
6535                         break;
6536                 case INTEL_OUTPUT_EDP:
6537                         has_panel = true;
6538                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6539                                 has_cpu_edp = true;
6540                         break;
6541                 }
6542         }
6543
6544         if (HAS_PCH_IBX(dev)) {
6545                 has_ck505 = dev_priv->vbt.display_clock_mode;
6546                 can_ssc = has_ck505;
6547         } else {
6548                 has_ck505 = false;
6549                 can_ssc = true;
6550         }
6551
6552         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6553                       has_panel, has_lvds, has_ck505);
6554
6555         /* Ironlake: try to setup display ref clock before DPLL
6556          * enabling. This is only under driver's control after
6557          * PCH B stepping, previous chipset stepping should be
6558          * ignoring this setting.
6559          */
6560         val = I915_READ(PCH_DREF_CONTROL);
6561
6562         /* As we must carefully and slowly disable/enable each source in turn,
6563          * compute the final state we want first and check if we need to
6564          * make any changes at all.
6565          */
6566         final = val;
6567         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6568         if (has_ck505)
6569                 final |= DREF_NONSPREAD_CK505_ENABLE;
6570         else
6571                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6572
6573         final &= ~DREF_SSC_SOURCE_MASK;
6574         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6575         final &= ~DREF_SSC1_ENABLE;
6576
6577         if (has_panel) {
6578                 final |= DREF_SSC_SOURCE_ENABLE;
6579
6580                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6581                         final |= DREF_SSC1_ENABLE;
6582
6583                 if (has_cpu_edp) {
6584                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6585                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6586                         else
6587                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6588                 } else
6589                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6590         } else {
6591                 final |= DREF_SSC_SOURCE_DISABLE;
6592                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6593         }
6594
6595         if (final == val)
6596                 return;
6597
6598         /* Always enable nonspread source */
6599         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6600
6601         if (has_ck505)
6602                 val |= DREF_NONSPREAD_CK505_ENABLE;
6603         else
6604                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6605
6606         if (has_panel) {
6607                 val &= ~DREF_SSC_SOURCE_MASK;
6608                 val |= DREF_SSC_SOURCE_ENABLE;
6609
6610                 /* SSC must be turned on before enabling the CPU output  */
6611                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6612                         DRM_DEBUG_KMS("Using SSC on panel\n");
6613                         val |= DREF_SSC1_ENABLE;
6614                 } else
6615                         val &= ~DREF_SSC1_ENABLE;
6616
6617                 /* Get SSC going before enabling the outputs */
6618                 I915_WRITE(PCH_DREF_CONTROL, val);
6619                 POSTING_READ(PCH_DREF_CONTROL);
6620                 udelay(200);
6621
6622                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6623
6624                 /* Enable CPU source on CPU attached eDP */
6625                 if (has_cpu_edp) {
6626                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6627                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6628                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6629                         } else
6630                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6631                 } else
6632                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6633
6634                 I915_WRITE(PCH_DREF_CONTROL, val);
6635                 POSTING_READ(PCH_DREF_CONTROL);
6636                 udelay(200);
6637         } else {
6638                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6639
6640                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6641
6642                 /* Turn off CPU output */
6643                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6644
6645                 I915_WRITE(PCH_DREF_CONTROL, val);
6646                 POSTING_READ(PCH_DREF_CONTROL);
6647                 udelay(200);
6648
6649                 /* Turn off the SSC source */
6650                 val &= ~DREF_SSC_SOURCE_MASK;
6651                 val |= DREF_SSC_SOURCE_DISABLE;
6652
6653                 /* Turn off SSC1 */
6654                 val &= ~DREF_SSC1_ENABLE;
6655
6656                 I915_WRITE(PCH_DREF_CONTROL, val);
6657                 POSTING_READ(PCH_DREF_CONTROL);
6658                 udelay(200);
6659         }
6660
6661         BUG_ON(val != final);
6662 }
6663
6664 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6665 {
6666         uint32_t tmp;
6667
6668         tmp = I915_READ(SOUTH_CHICKEN2);
6669         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6670         I915_WRITE(SOUTH_CHICKEN2, tmp);
6671
6672         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6673                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6674                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6675
6676         tmp = I915_READ(SOUTH_CHICKEN2);
6677         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6678         I915_WRITE(SOUTH_CHICKEN2, tmp);
6679
6680         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6681                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6682                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6683 }
6684
6685 /* WaMPhyProgramming:hsw */
6686 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6687 {
6688         uint32_t tmp;
6689
6690         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6691         tmp &= ~(0xFF << 24);
6692         tmp |= (0x12 << 24);
6693         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6694
6695         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6696         tmp |= (1 << 11);
6697         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6698
6699         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6700         tmp |= (1 << 11);
6701         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6702
6703         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6704         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6705         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6706
6707         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6708         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6709         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6710
6711         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6712         tmp &= ~(7 << 13);
6713         tmp |= (5 << 13);
6714         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6715
6716         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6717         tmp &= ~(7 << 13);
6718         tmp |= (5 << 13);
6719         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6720
6721         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6722         tmp &= ~0xFF;
6723         tmp |= 0x1C;
6724         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6725
6726         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6727         tmp &= ~0xFF;
6728         tmp |= 0x1C;
6729         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6730
6731         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6732         tmp &= ~(0xFF << 16);
6733         tmp |= (0x1C << 16);
6734         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6735
6736         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6737         tmp &= ~(0xFF << 16);
6738         tmp |= (0x1C << 16);
6739         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6740
6741         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6742         tmp |= (1 << 27);
6743         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6744
6745         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6746         tmp |= (1 << 27);
6747         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6748
6749         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6750         tmp &= ~(0xF << 28);
6751         tmp |= (4 << 28);
6752         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6753
6754         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6755         tmp &= ~(0xF << 28);
6756         tmp |= (4 << 28);
6757         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6758 }
6759
6760 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6761  * Programming" based on the parameters passed:
6762  * - Sequence to enable CLKOUT_DP
6763  * - Sequence to enable CLKOUT_DP without spread
6764  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6765  */
6766 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6767                                  bool with_fdi)
6768 {
6769         struct drm_i915_private *dev_priv = dev->dev_private;
6770         uint32_t reg, tmp;
6771
6772         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6773                 with_spread = true;
6774         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6775                  with_fdi, "LP PCH doesn't have FDI\n"))
6776                 with_fdi = false;
6777
6778         mutex_lock(&dev_priv->dpio_lock);
6779
6780         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6781         tmp &= ~SBI_SSCCTL_DISABLE;
6782         tmp |= SBI_SSCCTL_PATHALT;
6783         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6784
6785         udelay(24);
6786
6787         if (with_spread) {
6788                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6789                 tmp &= ~SBI_SSCCTL_PATHALT;
6790                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6791
6792                 if (with_fdi) {
6793                         lpt_reset_fdi_mphy(dev_priv);
6794                         lpt_program_fdi_mphy(dev_priv);
6795                 }
6796         }
6797
6798         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6799                SBI_GEN0 : SBI_DBUFF0;
6800         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6801         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6802         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6803
6804         mutex_unlock(&dev_priv->dpio_lock);
6805 }
6806
6807 /* Sequence to disable CLKOUT_DP */
6808 static void lpt_disable_clkout_dp(struct drm_device *dev)
6809 {
6810         struct drm_i915_private *dev_priv = dev->dev_private;
6811         uint32_t reg, tmp;
6812
6813         mutex_lock(&dev_priv->dpio_lock);
6814
6815         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6816                SBI_GEN0 : SBI_DBUFF0;
6817         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6818         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6819         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6820
6821         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6822         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6823                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6824                         tmp |= SBI_SSCCTL_PATHALT;
6825                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6826                         udelay(32);
6827                 }
6828                 tmp |= SBI_SSCCTL_DISABLE;
6829                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6830         }
6831
6832         mutex_unlock(&dev_priv->dpio_lock);
6833 }
6834
6835 static void lpt_init_pch_refclk(struct drm_device *dev)
6836 {
6837         struct intel_encoder *encoder;
6838         bool has_vga = false;
6839
6840         for_each_intel_encoder(dev, encoder) {
6841                 switch (encoder->type) {
6842                 case INTEL_OUTPUT_ANALOG:
6843                         has_vga = true;
6844                         break;
6845                 }
6846         }
6847
6848         if (has_vga)
6849                 lpt_enable_clkout_dp(dev, true, true);
6850         else
6851                 lpt_disable_clkout_dp(dev);
6852 }
6853
6854 /*
6855  * Initialize reference clocks when the driver loads
6856  */
6857 void intel_init_pch_refclk(struct drm_device *dev)
6858 {
6859         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6860                 ironlake_init_pch_refclk(dev);
6861         else if (HAS_PCH_LPT(dev))
6862                 lpt_init_pch_refclk(dev);
6863 }
6864
6865 static int ironlake_get_refclk(struct drm_crtc *crtc)
6866 {
6867         struct drm_device *dev = crtc->dev;
6868         struct drm_i915_private *dev_priv = dev->dev_private;
6869         struct intel_encoder *encoder;
6870         int num_connectors = 0;
6871         bool is_lvds = false;
6872
6873         for_each_encoder_on_crtc(dev, crtc, encoder) {
6874                 switch (encoder->type) {
6875                 case INTEL_OUTPUT_LVDS:
6876                         is_lvds = true;
6877                         break;
6878                 }
6879                 num_connectors++;
6880         }
6881
6882         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6883                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6884                               dev_priv->vbt.lvds_ssc_freq);
6885                 return dev_priv->vbt.lvds_ssc_freq;
6886         }
6887
6888         return 120000;
6889 }
6890
6891 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6892 {
6893         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895         int pipe = intel_crtc->pipe;
6896         uint32_t val;
6897
6898         val = 0;
6899
6900         switch (intel_crtc->config.pipe_bpp) {
6901         case 18:
6902                 val |= PIPECONF_6BPC;
6903                 break;
6904         case 24:
6905                 val |= PIPECONF_8BPC;
6906                 break;
6907         case 30:
6908                 val |= PIPECONF_10BPC;
6909                 break;
6910         case 36:
6911                 val |= PIPECONF_12BPC;
6912                 break;
6913         default:
6914                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6915                 BUG();
6916         }
6917
6918         if (intel_crtc->config.dither)
6919                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6920
6921         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6922                 val |= PIPECONF_INTERLACED_ILK;
6923         else
6924                 val |= PIPECONF_PROGRESSIVE;
6925
6926         if (intel_crtc->config.limited_color_range)
6927                 val |= PIPECONF_COLOR_RANGE_SELECT;
6928
6929         I915_WRITE(PIPECONF(pipe), val);
6930         POSTING_READ(PIPECONF(pipe));
6931 }
6932
6933 /*
6934  * Set up the pipe CSC unit.
6935  *
6936  * Currently only full range RGB to limited range RGB conversion
6937  * is supported, but eventually this should handle various
6938  * RGB<->YCbCr scenarios as well.
6939  */
6940 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6941 {
6942         struct drm_device *dev = crtc->dev;
6943         struct drm_i915_private *dev_priv = dev->dev_private;
6944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6945         int pipe = intel_crtc->pipe;
6946         uint16_t coeff = 0x7800; /* 1.0 */
6947
6948         /*
6949          * TODO: Check what kind of values actually come out of the pipe
6950          * with these coeff/postoff values and adjust to get the best
6951          * accuracy. Perhaps we even need to take the bpc value into
6952          * consideration.
6953          */
6954
6955         if (intel_crtc->config.limited_color_range)
6956                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6957
6958         /*
6959          * GY/GU and RY/RU should be the other way around according
6960          * to BSpec, but reality doesn't agree. Just set them up in
6961          * a way that results in the correct picture.
6962          */
6963         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6964         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6965
6966         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6967         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6968
6969         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6970         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6971
6972         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6973         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6974         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6975
6976         if (INTEL_INFO(dev)->gen > 6) {
6977                 uint16_t postoff = 0;
6978
6979                 if (intel_crtc->config.limited_color_range)
6980                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6981
6982                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6983                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6984                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6985
6986                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6987         } else {
6988                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6989
6990                 if (intel_crtc->config.limited_color_range)
6991                         mode |= CSC_BLACK_SCREEN_OFFSET;
6992
6993                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6994         }
6995 }
6996
6997 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6998 {
6999         struct drm_device *dev = crtc->dev;
7000         struct drm_i915_private *dev_priv = dev->dev_private;
7001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002         enum pipe pipe = intel_crtc->pipe;
7003         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7004         uint32_t val;
7005
7006         val = 0;
7007
7008         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7009                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7010
7011         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7012                 val |= PIPECONF_INTERLACED_ILK;
7013         else
7014                 val |= PIPECONF_PROGRESSIVE;
7015
7016         I915_WRITE(PIPECONF(cpu_transcoder), val);
7017         POSTING_READ(PIPECONF(cpu_transcoder));
7018
7019         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7020         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7021
7022         if (IS_BROADWELL(dev)) {
7023                 val = 0;
7024
7025                 switch (intel_crtc->config.pipe_bpp) {
7026                 case 18:
7027                         val |= PIPEMISC_DITHER_6_BPC;
7028                         break;
7029                 case 24:
7030                         val |= PIPEMISC_DITHER_8_BPC;
7031                         break;
7032                 case 30:
7033                         val |= PIPEMISC_DITHER_10_BPC;
7034                         break;
7035                 case 36:
7036                         val |= PIPEMISC_DITHER_12_BPC;
7037                         break;
7038                 default:
7039                         /* Case prevented by pipe_config_set_bpp. */
7040                         BUG();
7041                 }
7042
7043                 if (intel_crtc->config.dither)
7044                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7045
7046                 I915_WRITE(PIPEMISC(pipe), val);
7047         }
7048 }
7049
7050 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7051                                     intel_clock_t *clock,
7052                                     bool *has_reduced_clock,
7053                                     intel_clock_t *reduced_clock)
7054 {
7055         struct drm_device *dev = crtc->dev;
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057         struct intel_encoder *intel_encoder;
7058         int refclk;
7059         const intel_limit_t *limit;
7060         bool ret, is_lvds = false;
7061
7062         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7063                 switch (intel_encoder->type) {
7064                 case INTEL_OUTPUT_LVDS:
7065                         is_lvds = true;
7066                         break;
7067                 }
7068         }
7069
7070         refclk = ironlake_get_refclk(crtc);
7071
7072         /*
7073          * Returns a set of divisors for the desired target clock with the given
7074          * refclk, or FALSE.  The returned values represent the clock equation:
7075          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7076          */
7077         limit = intel_limit(crtc, refclk);
7078         ret = dev_priv->display.find_dpll(limit, crtc,
7079                                           to_intel_crtc(crtc)->config.port_clock,
7080                                           refclk, NULL, clock);
7081         if (!ret)
7082                 return false;
7083
7084         if (is_lvds && dev_priv->lvds_downclock_avail) {
7085                 /*
7086                  * Ensure we match the reduced clock's P to the target clock.
7087                  * If the clocks don't match, we can't switch the display clock
7088                  * by using the FP0/FP1. In such case we will disable the LVDS
7089                  * downclock feature.
7090                 */
7091                 *has_reduced_clock =
7092                         dev_priv->display.find_dpll(limit, crtc,
7093                                                     dev_priv->lvds_downclock,
7094                                                     refclk, clock,
7095                                                     reduced_clock);
7096         }
7097
7098         return true;
7099 }
7100
7101 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7102 {
7103         /*
7104          * Account for spread spectrum to avoid
7105          * oversubscribing the link. Max center spread
7106          * is 2.5%; use 5% for safety's sake.
7107          */
7108         u32 bps = target_clock * bpp * 21 / 20;
7109         return DIV_ROUND_UP(bps, link_bw * 8);
7110 }
7111
7112 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7113 {
7114         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7115 }
7116
7117 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7118                                       u32 *fp,
7119                                       intel_clock_t *reduced_clock, u32 *fp2)
7120 {
7121         struct drm_crtc *crtc = &intel_crtc->base;
7122         struct drm_device *dev = crtc->dev;
7123         struct drm_i915_private *dev_priv = dev->dev_private;
7124         struct intel_encoder *intel_encoder;
7125         uint32_t dpll;
7126         int factor, num_connectors = 0;
7127         bool is_lvds = false, is_sdvo = false;
7128
7129         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7130                 switch (intel_encoder->type) {
7131                 case INTEL_OUTPUT_LVDS:
7132                         is_lvds = true;
7133                         break;
7134                 case INTEL_OUTPUT_SDVO:
7135                 case INTEL_OUTPUT_HDMI:
7136                         is_sdvo = true;
7137                         break;
7138                 }
7139
7140                 num_connectors++;
7141         }
7142
7143         /* Enable autotuning of the PLL clock (if permissible) */
7144         factor = 21;
7145         if (is_lvds) {
7146                 if ((intel_panel_use_ssc(dev_priv) &&
7147                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7148                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7149                         factor = 25;
7150         } else if (intel_crtc->config.sdvo_tv_clock)
7151                 factor = 20;
7152
7153         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7154                 *fp |= FP_CB_TUNE;
7155
7156         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7157                 *fp2 |= FP_CB_TUNE;
7158
7159         dpll = 0;
7160
7161         if (is_lvds)
7162                 dpll |= DPLLB_MODE_LVDS;
7163         else
7164                 dpll |= DPLLB_MODE_DAC_SERIAL;
7165
7166         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7167                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7168
7169         if (is_sdvo)
7170                 dpll |= DPLL_SDVO_HIGH_SPEED;
7171         if (intel_crtc->config.has_dp_encoder)
7172                 dpll |= DPLL_SDVO_HIGH_SPEED;
7173
7174         /* compute bitmask from p1 value */
7175         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7176         /* also FPA1 */
7177         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7178
7179         switch (intel_crtc->config.dpll.p2) {
7180         case 5:
7181                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7182                 break;
7183         case 7:
7184                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7185                 break;
7186         case 10:
7187                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7188                 break;
7189         case 14:
7190                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7191                 break;
7192         }
7193
7194         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7195                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7196         else
7197                 dpll |= PLL_REF_INPUT_DREFCLK;
7198
7199         return dpll | DPLL_VCO_ENABLE;
7200 }
7201
7202 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7203                                   int x, int y,
7204                                   struct drm_framebuffer *fb)
7205 {
7206         struct drm_device *dev = crtc->dev;
7207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7208         int num_connectors = 0;
7209         intel_clock_t clock, reduced_clock;
7210         u32 dpll = 0, fp = 0, fp2 = 0;
7211         bool ok, has_reduced_clock = false;
7212         bool is_lvds = false;
7213         struct intel_encoder *encoder;
7214         struct intel_shared_dpll *pll;
7215
7216         for_each_encoder_on_crtc(dev, crtc, encoder) {
7217                 switch (encoder->type) {
7218                 case INTEL_OUTPUT_LVDS:
7219                         is_lvds = true;
7220                         break;
7221                 }
7222
7223                 num_connectors++;
7224         }
7225
7226         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7227              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7228
7229         ok = ironlake_compute_clocks(crtc, &clock,
7230                                      &has_reduced_clock, &reduced_clock);
7231         if (!ok && !intel_crtc->config.clock_set) {
7232                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7233                 return -EINVAL;
7234         }
7235         /* Compat-code for transition, will disappear. */
7236         if (!intel_crtc->config.clock_set) {
7237                 intel_crtc->config.dpll.n = clock.n;
7238                 intel_crtc->config.dpll.m1 = clock.m1;
7239                 intel_crtc->config.dpll.m2 = clock.m2;
7240                 intel_crtc->config.dpll.p1 = clock.p1;
7241                 intel_crtc->config.dpll.p2 = clock.p2;
7242         }
7243
7244         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7245         if (intel_crtc->config.has_pch_encoder) {
7246                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7247                 if (has_reduced_clock)
7248                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7249
7250                 dpll = ironlake_compute_dpll(intel_crtc,
7251                                              &fp, &reduced_clock,
7252                                              has_reduced_clock ? &fp2 : NULL);
7253
7254                 intel_crtc->config.dpll_hw_state.dpll = dpll;
7255                 intel_crtc->config.dpll_hw_state.fp0 = fp;
7256                 if (has_reduced_clock)
7257                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
7258                 else
7259                         intel_crtc->config.dpll_hw_state.fp1 = fp;
7260
7261                 pll = intel_get_shared_dpll(intel_crtc);
7262                 if (pll == NULL) {
7263                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7264                                          pipe_name(intel_crtc->pipe));
7265                         return -EINVAL;
7266                 }
7267         } else
7268                 intel_put_shared_dpll(intel_crtc);
7269
7270         if (is_lvds && has_reduced_clock && i915.powersave)
7271                 intel_crtc->lowfreq_avail = true;
7272         else
7273                 intel_crtc->lowfreq_avail = false;
7274
7275         return 0;
7276 }
7277
7278 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7279                                          struct intel_link_m_n *m_n)
7280 {
7281         struct drm_device *dev = crtc->base.dev;
7282         struct drm_i915_private *dev_priv = dev->dev_private;
7283         enum pipe pipe = crtc->pipe;
7284
7285         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7286         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7287         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7288                 & ~TU_SIZE_MASK;
7289         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7290         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7291                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7292 }
7293
7294 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7295                                          enum transcoder transcoder,
7296                                          struct intel_link_m_n *m_n,
7297                                          struct intel_link_m_n *m2_n2)
7298 {
7299         struct drm_device *dev = crtc->base.dev;
7300         struct drm_i915_private *dev_priv = dev->dev_private;
7301         enum pipe pipe = crtc->pipe;
7302
7303         if (INTEL_INFO(dev)->gen >= 5) {
7304                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7305                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7306                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7307                         & ~TU_SIZE_MASK;
7308                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7309                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7310                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7311                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7312                  * gen < 8) and if DRRS is supported (to make sure the
7313                  * registers are not unnecessarily read).
7314                  */
7315                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7316                         crtc->config.has_drrs) {
7317                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7318                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7319                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7320                                         & ~TU_SIZE_MASK;
7321                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7322                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7323                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7324                 }
7325         } else {
7326                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7327                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7328                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7329                         & ~TU_SIZE_MASK;
7330                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7331                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7332                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7333         }
7334 }
7335
7336 void intel_dp_get_m_n(struct intel_crtc *crtc,
7337                       struct intel_crtc_config *pipe_config)
7338 {
7339         if (crtc->config.has_pch_encoder)
7340                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7341         else
7342                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7343                                              &pipe_config->dp_m_n,
7344                                              &pipe_config->dp_m2_n2);
7345 }
7346
7347 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7348                                         struct intel_crtc_config *pipe_config)
7349 {
7350         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7351                                      &pipe_config->fdi_m_n, NULL);
7352 }
7353
7354 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7355                                      struct intel_crtc_config *pipe_config)
7356 {
7357         struct drm_device *dev = crtc->base.dev;
7358         struct drm_i915_private *dev_priv = dev->dev_private;
7359         uint32_t tmp;
7360
7361         tmp = I915_READ(PF_CTL(crtc->pipe));
7362
7363         if (tmp & PF_ENABLE) {
7364                 pipe_config->pch_pfit.enabled = true;
7365                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7366                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7367
7368                 /* We currently do not free assignements of panel fitters on
7369                  * ivb/hsw (since we don't use the higher upscaling modes which
7370                  * differentiates them) so just WARN about this case for now. */
7371                 if (IS_GEN7(dev)) {
7372                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7373                                 PF_PIPE_SEL_IVB(crtc->pipe));
7374                 }
7375         }
7376 }
7377
7378 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7379                                       struct intel_plane_config *plane_config)
7380 {
7381         struct drm_device *dev = crtc->base.dev;
7382         struct drm_i915_private *dev_priv = dev->dev_private;
7383         u32 val, base, offset;
7384         int pipe = crtc->pipe, plane = crtc->plane;
7385         int fourcc, pixel_format;
7386         int aligned_height;
7387
7388         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7389         if (!crtc->base.primary->fb) {
7390                 DRM_DEBUG_KMS("failed to alloc fb\n");
7391                 return;
7392         }
7393
7394         val = I915_READ(DSPCNTR(plane));
7395
7396         if (INTEL_INFO(dev)->gen >= 4)
7397                 if (val & DISPPLANE_TILED)
7398                         plane_config->tiled = true;
7399
7400         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7401         fourcc = intel_format_to_fourcc(pixel_format);
7402         crtc->base.primary->fb->pixel_format = fourcc;
7403         crtc->base.primary->fb->bits_per_pixel =
7404                 drm_format_plane_cpp(fourcc, 0) * 8;
7405
7406         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7407         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7408                 offset = I915_READ(DSPOFFSET(plane));
7409         } else {
7410                 if (plane_config->tiled)
7411                         offset = I915_READ(DSPTILEOFF(plane));
7412                 else
7413                         offset = I915_READ(DSPLINOFF(plane));
7414         }
7415         plane_config->base = base;
7416
7417         val = I915_READ(PIPESRC(pipe));
7418         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7419         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7420
7421         val = I915_READ(DSPSTRIDE(pipe));
7422         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7423
7424         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7425                                             plane_config->tiled);
7426
7427         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7428                                         aligned_height);
7429
7430         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7431                       pipe, plane, crtc->base.primary->fb->width,
7432                       crtc->base.primary->fb->height,
7433                       crtc->base.primary->fb->bits_per_pixel, base,
7434                       crtc->base.primary->fb->pitches[0],
7435                       plane_config->size);
7436 }
7437
7438 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7439                                      struct intel_crtc_config *pipe_config)
7440 {
7441         struct drm_device *dev = crtc->base.dev;
7442         struct drm_i915_private *dev_priv = dev->dev_private;
7443         uint32_t tmp;
7444
7445         if (!intel_display_power_enabled(dev_priv,
7446                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7447                 return false;
7448
7449         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7450         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7451
7452         tmp = I915_READ(PIPECONF(crtc->pipe));
7453         if (!(tmp & PIPECONF_ENABLE))
7454                 return false;
7455
7456         switch (tmp & PIPECONF_BPC_MASK) {
7457         case PIPECONF_6BPC:
7458                 pipe_config->pipe_bpp = 18;
7459                 break;
7460         case PIPECONF_8BPC:
7461                 pipe_config->pipe_bpp = 24;
7462                 break;
7463         case PIPECONF_10BPC:
7464                 pipe_config->pipe_bpp = 30;
7465                 break;
7466         case PIPECONF_12BPC:
7467                 pipe_config->pipe_bpp = 36;
7468                 break;
7469         default:
7470                 break;
7471         }
7472
7473         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7474                 pipe_config->limited_color_range = true;
7475
7476         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7477                 struct intel_shared_dpll *pll;
7478
7479                 pipe_config->has_pch_encoder = true;
7480
7481                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7482                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7483                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7484
7485                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7486
7487                 if (HAS_PCH_IBX(dev_priv->dev)) {
7488                         pipe_config->shared_dpll =
7489                                 (enum intel_dpll_id) crtc->pipe;
7490                 } else {
7491                         tmp = I915_READ(PCH_DPLL_SEL);
7492                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7493                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7494                         else
7495                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7496                 }
7497
7498                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7499
7500                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7501                                            &pipe_config->dpll_hw_state));
7502
7503                 tmp = pipe_config->dpll_hw_state.dpll;
7504                 pipe_config->pixel_multiplier =
7505                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7506                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7507
7508                 ironlake_pch_clock_get(crtc, pipe_config);
7509         } else {
7510                 pipe_config->pixel_multiplier = 1;
7511         }
7512
7513         intel_get_pipe_timings(crtc, pipe_config);
7514
7515         ironlake_get_pfit_config(crtc, pipe_config);
7516
7517         return true;
7518 }
7519
7520 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7521 {
7522         struct drm_device *dev = dev_priv->dev;
7523         struct intel_crtc *crtc;
7524
7525         for_each_intel_crtc(dev, crtc)
7526                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7527                      pipe_name(crtc->pipe));
7528
7529         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7530         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7531         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7532         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7533         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7534         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7535              "CPU PWM1 enabled\n");
7536         if (IS_HASWELL(dev))
7537                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7538                      "CPU PWM2 enabled\n");
7539         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7540              "PCH PWM1 enabled\n");
7541         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7542              "Utility pin enabled\n");
7543         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7544
7545         /*
7546          * In theory we can still leave IRQs enabled, as long as only the HPD
7547          * interrupts remain enabled. We used to check for that, but since it's
7548          * gen-specific and since we only disable LCPLL after we fully disable
7549          * the interrupts, the check below should be enough.
7550          */
7551         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7552 }
7553
7554 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7555 {
7556         struct drm_device *dev = dev_priv->dev;
7557
7558         if (IS_HASWELL(dev))
7559                 return I915_READ(D_COMP_HSW);
7560         else
7561                 return I915_READ(D_COMP_BDW);
7562 }
7563
7564 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7565 {
7566         struct drm_device *dev = dev_priv->dev;
7567
7568         if (IS_HASWELL(dev)) {
7569                 mutex_lock(&dev_priv->rps.hw_lock);
7570                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7571                                             val))
7572                         DRM_ERROR("Failed to write to D_COMP\n");
7573                 mutex_unlock(&dev_priv->rps.hw_lock);
7574         } else {
7575                 I915_WRITE(D_COMP_BDW, val);
7576                 POSTING_READ(D_COMP_BDW);
7577         }
7578 }
7579
7580 /*
7581  * This function implements pieces of two sequences from BSpec:
7582  * - Sequence for display software to disable LCPLL
7583  * - Sequence for display software to allow package C8+
7584  * The steps implemented here are just the steps that actually touch the LCPLL
7585  * register. Callers should take care of disabling all the display engine
7586  * functions, doing the mode unset, fixing interrupts, etc.
7587  */
7588 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7589                               bool switch_to_fclk, bool allow_power_down)
7590 {
7591         uint32_t val;
7592
7593         assert_can_disable_lcpll(dev_priv);
7594
7595         val = I915_READ(LCPLL_CTL);
7596
7597         if (switch_to_fclk) {
7598                 val |= LCPLL_CD_SOURCE_FCLK;
7599                 I915_WRITE(LCPLL_CTL, val);
7600
7601                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7602                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7603                         DRM_ERROR("Switching to FCLK failed\n");
7604
7605                 val = I915_READ(LCPLL_CTL);
7606         }
7607
7608         val |= LCPLL_PLL_DISABLE;
7609         I915_WRITE(LCPLL_CTL, val);
7610         POSTING_READ(LCPLL_CTL);
7611
7612         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7613                 DRM_ERROR("LCPLL still locked\n");
7614
7615         val = hsw_read_dcomp(dev_priv);
7616         val |= D_COMP_COMP_DISABLE;
7617         hsw_write_dcomp(dev_priv, val);
7618         ndelay(100);
7619
7620         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7621                      1))
7622                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7623
7624         if (allow_power_down) {
7625                 val = I915_READ(LCPLL_CTL);
7626                 val |= LCPLL_POWER_DOWN_ALLOW;
7627                 I915_WRITE(LCPLL_CTL, val);
7628                 POSTING_READ(LCPLL_CTL);
7629         }
7630 }
7631
7632 /*
7633  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7634  * source.
7635  */
7636 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7637 {
7638         uint32_t val;
7639         unsigned long irqflags;
7640
7641         val = I915_READ(LCPLL_CTL);
7642
7643         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7644                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7645                 return;
7646
7647         /*
7648          * Make sure we're not on PC8 state before disabling PC8, otherwise
7649          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7650          *
7651          * The other problem is that hsw_restore_lcpll() is called as part of
7652          * the runtime PM resume sequence, so we can't just call
7653          * gen6_gt_force_wake_get() because that function calls
7654          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7655          * while we are on the resume sequence. So to solve this problem we have
7656          * to call special forcewake code that doesn't touch runtime PM and
7657          * doesn't enable the forcewake delayed work.
7658          */
7659         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7660         if (dev_priv->uncore.forcewake_count++ == 0)
7661                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7662         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7663
7664         if (val & LCPLL_POWER_DOWN_ALLOW) {
7665                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7666                 I915_WRITE(LCPLL_CTL, val);
7667                 POSTING_READ(LCPLL_CTL);
7668         }
7669
7670         val = hsw_read_dcomp(dev_priv);
7671         val |= D_COMP_COMP_FORCE;
7672         val &= ~D_COMP_COMP_DISABLE;
7673         hsw_write_dcomp(dev_priv, val);
7674
7675         val = I915_READ(LCPLL_CTL);
7676         val &= ~LCPLL_PLL_DISABLE;
7677         I915_WRITE(LCPLL_CTL, val);
7678
7679         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7680                 DRM_ERROR("LCPLL not locked yet\n");
7681
7682         if (val & LCPLL_CD_SOURCE_FCLK) {
7683                 val = I915_READ(LCPLL_CTL);
7684                 val &= ~LCPLL_CD_SOURCE_FCLK;
7685                 I915_WRITE(LCPLL_CTL, val);
7686
7687                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7688                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7689                         DRM_ERROR("Switching back to LCPLL failed\n");
7690         }
7691
7692         /* See the big comment above. */
7693         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7694         if (--dev_priv->uncore.forcewake_count == 0)
7695                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7696         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7697 }
7698
7699 /*
7700  * Package states C8 and deeper are really deep PC states that can only be
7701  * reached when all the devices on the system allow it, so even if the graphics
7702  * device allows PC8+, it doesn't mean the system will actually get to these
7703  * states. Our driver only allows PC8+ when going into runtime PM.
7704  *
7705  * The requirements for PC8+ are that all the outputs are disabled, the power
7706  * well is disabled and most interrupts are disabled, and these are also
7707  * requirements for runtime PM. When these conditions are met, we manually do
7708  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7709  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7710  * hang the machine.
7711  *
7712  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7713  * the state of some registers, so when we come back from PC8+ we need to
7714  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7715  * need to take care of the registers kept by RC6. Notice that this happens even
7716  * if we don't put the device in PCI D3 state (which is what currently happens
7717  * because of the runtime PM support).
7718  *
7719  * For more, read "Display Sequences for Package C8" on the hardware
7720  * documentation.
7721  */
7722 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7723 {
7724         struct drm_device *dev = dev_priv->dev;
7725         uint32_t val;
7726
7727         DRM_DEBUG_KMS("Enabling package C8+\n");
7728
7729         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7730                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7731                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7732                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7733         }
7734
7735         lpt_disable_clkout_dp(dev);
7736         hsw_disable_lcpll(dev_priv, true, true);
7737 }
7738
7739 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7740 {
7741         struct drm_device *dev = dev_priv->dev;
7742         uint32_t val;
7743
7744         DRM_DEBUG_KMS("Disabling package C8+\n");
7745
7746         hsw_restore_lcpll(dev_priv);
7747         lpt_init_pch_refclk(dev);
7748
7749         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7750                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7751                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7752                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7753         }
7754
7755         intel_prepare_ddi(dev);
7756 }
7757
7758 static void snb_modeset_global_resources(struct drm_device *dev)
7759 {
7760         modeset_update_crtc_power_domains(dev);
7761 }
7762
7763 static void haswell_modeset_global_resources(struct drm_device *dev)
7764 {
7765         modeset_update_crtc_power_domains(dev);
7766 }
7767
7768 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7769                                  int x, int y,
7770                                  struct drm_framebuffer *fb)
7771 {
7772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7773
7774         if (!intel_ddi_pll_select(intel_crtc))
7775                 return -EINVAL;
7776
7777         intel_crtc->lowfreq_avail = false;
7778
7779         return 0;
7780 }
7781
7782 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7783                                 enum port port,
7784                                 struct intel_crtc_config *pipe_config)
7785 {
7786         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7787
7788         switch (pipe_config->ddi_pll_sel) {
7789         case PORT_CLK_SEL_WRPLL1:
7790                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7791                 break;
7792         case PORT_CLK_SEL_WRPLL2:
7793                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7794                 break;
7795         }
7796 }
7797
7798 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7799                                        struct intel_crtc_config *pipe_config)
7800 {
7801         struct drm_device *dev = crtc->base.dev;
7802         struct drm_i915_private *dev_priv = dev->dev_private;
7803         struct intel_shared_dpll *pll;
7804         enum port port;
7805         uint32_t tmp;
7806
7807         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7808
7809         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7810
7811         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7812
7813         if (pipe_config->shared_dpll >= 0) {
7814                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7815
7816                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7817                                            &pipe_config->dpll_hw_state));
7818         }
7819
7820         /*
7821          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7822          * DDI E. So just check whether this pipe is wired to DDI E and whether
7823          * the PCH transcoder is on.
7824          */
7825         if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7826                 pipe_config->has_pch_encoder = true;
7827
7828                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7829                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7830                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7831
7832                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7833         }
7834 }
7835
7836 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7837                                     struct intel_crtc_config *pipe_config)
7838 {
7839         struct drm_device *dev = crtc->base.dev;
7840         struct drm_i915_private *dev_priv = dev->dev_private;
7841         enum intel_display_power_domain pfit_domain;
7842         uint32_t tmp;
7843
7844         if (!intel_display_power_enabled(dev_priv,
7845                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7846                 return false;
7847
7848         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7849         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7850
7851         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7852         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7853                 enum pipe trans_edp_pipe;
7854                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7855                 default:
7856                         WARN(1, "unknown pipe linked to edp transcoder\n");
7857                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7858                 case TRANS_DDI_EDP_INPUT_A_ON:
7859                         trans_edp_pipe = PIPE_A;
7860                         break;
7861                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7862                         trans_edp_pipe = PIPE_B;
7863                         break;
7864                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7865                         trans_edp_pipe = PIPE_C;
7866                         break;
7867                 }
7868
7869                 if (trans_edp_pipe == crtc->pipe)
7870                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7871         }
7872
7873         if (!intel_display_power_enabled(dev_priv,
7874                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7875                 return false;
7876
7877         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7878         if (!(tmp & PIPECONF_ENABLE))
7879                 return false;
7880
7881         haswell_get_ddi_port_state(crtc, pipe_config);
7882
7883         intel_get_pipe_timings(crtc, pipe_config);
7884
7885         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7886         if (intel_display_power_enabled(dev_priv, pfit_domain))
7887                 ironlake_get_pfit_config(crtc, pipe_config);
7888
7889         if (IS_HASWELL(dev))
7890                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7891                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7892
7893         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7894                 pipe_config->pixel_multiplier =
7895                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7896         } else {
7897                 pipe_config->pixel_multiplier = 1;
7898         }
7899
7900         return true;
7901 }
7902
7903 static struct {
7904         int clock;
7905         u32 config;
7906 } hdmi_audio_clock[] = {
7907         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7908         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7909         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7910         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7911         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7912         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7913         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7914         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7915         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7916         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7917 };
7918
7919 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7920 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7921 {
7922         int i;
7923
7924         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7925                 if (mode->clock == hdmi_audio_clock[i].clock)
7926                         break;
7927         }
7928
7929         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7930                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7931                 i = 1;
7932         }
7933
7934         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7935                       hdmi_audio_clock[i].clock,
7936                       hdmi_audio_clock[i].config);
7937
7938         return hdmi_audio_clock[i].config;
7939 }
7940
7941 static bool intel_eld_uptodate(struct drm_connector *connector,
7942                                int reg_eldv, uint32_t bits_eldv,
7943                                int reg_elda, uint32_t bits_elda,
7944                                int reg_edid)
7945 {
7946         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7947         uint8_t *eld = connector->eld;
7948         uint32_t i;
7949
7950         i = I915_READ(reg_eldv);
7951         i &= bits_eldv;
7952
7953         if (!eld[0])
7954                 return !i;
7955
7956         if (!i)
7957                 return false;
7958
7959         i = I915_READ(reg_elda);
7960         i &= ~bits_elda;
7961         I915_WRITE(reg_elda, i);
7962
7963         for (i = 0; i < eld[2]; i++)
7964                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7965                         return false;
7966
7967         return true;
7968 }
7969
7970 static void g4x_write_eld(struct drm_connector *connector,
7971                           struct drm_crtc *crtc,
7972                           struct drm_display_mode *mode)
7973 {
7974         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7975         uint8_t *eld = connector->eld;
7976         uint32_t eldv;
7977         uint32_t len;
7978         uint32_t i;
7979
7980         i = I915_READ(G4X_AUD_VID_DID);
7981
7982         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7983                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7984         else
7985                 eldv = G4X_ELDV_DEVCTG;
7986
7987         if (intel_eld_uptodate(connector,
7988                                G4X_AUD_CNTL_ST, eldv,
7989                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7990                                G4X_HDMIW_HDMIEDID))
7991                 return;
7992
7993         i = I915_READ(G4X_AUD_CNTL_ST);
7994         i &= ~(eldv | G4X_ELD_ADDR);
7995         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7996         I915_WRITE(G4X_AUD_CNTL_ST, i);
7997
7998         if (!eld[0])
7999                 return;
8000
8001         len = min_t(uint8_t, eld[2], len);
8002         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8003         for (i = 0; i < len; i++)
8004                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8005
8006         i = I915_READ(G4X_AUD_CNTL_ST);
8007         i |= eldv;
8008         I915_WRITE(G4X_AUD_CNTL_ST, i);
8009 }
8010
8011 static void haswell_write_eld(struct drm_connector *connector,
8012                               struct drm_crtc *crtc,
8013                               struct drm_display_mode *mode)
8014 {
8015         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8016         uint8_t *eld = connector->eld;
8017         uint32_t eldv;
8018         uint32_t i;
8019         int len;
8020         int pipe = to_intel_crtc(crtc)->pipe;
8021         int tmp;
8022
8023         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8024         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8025         int aud_config = HSW_AUD_CFG(pipe);
8026         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8027
8028         /* Audio output enable */
8029         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8030         tmp = I915_READ(aud_cntrl_st2);
8031         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8032         I915_WRITE(aud_cntrl_st2, tmp);
8033         POSTING_READ(aud_cntrl_st2);
8034
8035         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8036
8037         /* Set ELD valid state */
8038         tmp = I915_READ(aud_cntrl_st2);
8039         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8040         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8041         I915_WRITE(aud_cntrl_st2, tmp);
8042         tmp = I915_READ(aud_cntrl_st2);
8043         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8044
8045         /* Enable HDMI mode */
8046         tmp = I915_READ(aud_config);
8047         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8048         /* clear N_programing_enable and N_value_index */
8049         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8050         I915_WRITE(aud_config, tmp);
8051
8052         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8053
8054         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8055
8056         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8057                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8058                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8059                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8060         } else {
8061                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8062         }
8063
8064         if (intel_eld_uptodate(connector,
8065                                aud_cntrl_st2, eldv,
8066                                aud_cntl_st, IBX_ELD_ADDRESS,
8067                                hdmiw_hdmiedid))
8068                 return;
8069
8070         i = I915_READ(aud_cntrl_st2);
8071         i &= ~eldv;
8072         I915_WRITE(aud_cntrl_st2, i);
8073
8074         if (!eld[0])
8075                 return;
8076
8077         i = I915_READ(aud_cntl_st);
8078         i &= ~IBX_ELD_ADDRESS;
8079         I915_WRITE(aud_cntl_st, i);
8080         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
8081         DRM_DEBUG_DRIVER("port num:%d\n", i);
8082
8083         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8084         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8085         for (i = 0; i < len; i++)
8086                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8087
8088         i = I915_READ(aud_cntrl_st2);
8089         i |= eldv;
8090         I915_WRITE(aud_cntrl_st2, i);
8091
8092 }
8093
8094 static void ironlake_write_eld(struct drm_connector *connector,
8095                                struct drm_crtc *crtc,
8096                                struct drm_display_mode *mode)
8097 {
8098         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8099         uint8_t *eld = connector->eld;
8100         uint32_t eldv;
8101         uint32_t i;
8102         int len;
8103         int hdmiw_hdmiedid;
8104         int aud_config;
8105         int aud_cntl_st;
8106         int aud_cntrl_st2;
8107         int pipe = to_intel_crtc(crtc)->pipe;
8108
8109         if (HAS_PCH_IBX(connector->dev)) {
8110                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8111                 aud_config = IBX_AUD_CFG(pipe);
8112                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8113                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8114         } else if (IS_VALLEYVIEW(connector->dev)) {
8115                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8116                 aud_config = VLV_AUD_CFG(pipe);
8117                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8118                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8119         } else {
8120                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8121                 aud_config = CPT_AUD_CFG(pipe);
8122                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8123                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8124         }
8125
8126         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8127
8128         if (IS_VALLEYVIEW(connector->dev))  {
8129                 struct intel_encoder *intel_encoder;
8130                 struct intel_digital_port *intel_dig_port;
8131
8132                 intel_encoder = intel_attached_encoder(connector);
8133                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8134                 i = intel_dig_port->port;
8135         } else {
8136                 i = I915_READ(aud_cntl_st);
8137                 i = (i >> 29) & DIP_PORT_SEL_MASK;
8138                 /* DIP_Port_Select, 0x1 = PortB */
8139         }
8140
8141         if (!i) {
8142                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8143                 /* operate blindly on all ports */
8144                 eldv = IBX_ELD_VALIDB;
8145                 eldv |= IBX_ELD_VALIDB << 4;
8146                 eldv |= IBX_ELD_VALIDB << 8;
8147         } else {
8148                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8149                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8150         }
8151
8152         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8153                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8154                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8155                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8156         } else {
8157                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8158         }
8159
8160         if (intel_eld_uptodate(connector,
8161                                aud_cntrl_st2, eldv,
8162                                aud_cntl_st, IBX_ELD_ADDRESS,
8163                                hdmiw_hdmiedid))
8164                 return;
8165
8166         i = I915_READ(aud_cntrl_st2);
8167         i &= ~eldv;
8168         I915_WRITE(aud_cntrl_st2, i);
8169
8170         if (!eld[0])
8171                 return;
8172
8173         i = I915_READ(aud_cntl_st);
8174         i &= ~IBX_ELD_ADDRESS;
8175         I915_WRITE(aud_cntl_st, i);
8176
8177         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8178         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8179         for (i = 0; i < len; i++)
8180                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8181
8182         i = I915_READ(aud_cntrl_st2);
8183         i |= eldv;
8184         I915_WRITE(aud_cntrl_st2, i);
8185 }
8186
8187 void intel_write_eld(struct drm_encoder *encoder,
8188                      struct drm_display_mode *mode)
8189 {
8190         struct drm_crtc *crtc = encoder->crtc;
8191         struct drm_connector *connector;
8192         struct drm_device *dev = encoder->dev;
8193         struct drm_i915_private *dev_priv = dev->dev_private;
8194
8195         connector = drm_select_eld(encoder, mode);
8196         if (!connector)
8197                 return;
8198
8199         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8200                          connector->base.id,
8201                          connector->name,
8202                          connector->encoder->base.id,
8203                          connector->encoder->name);
8204
8205         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8206
8207         if (dev_priv->display.write_eld)
8208                 dev_priv->display.write_eld(connector, crtc, mode);
8209 }
8210
8211 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8212 {
8213         struct drm_device *dev = crtc->dev;
8214         struct drm_i915_private *dev_priv = dev->dev_private;
8215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8216         uint32_t cntl = 0, size = 0;
8217
8218         if (base) {
8219                 unsigned int width = intel_crtc->cursor_width;
8220                 unsigned int height = intel_crtc->cursor_height;
8221                 unsigned int stride = roundup_pow_of_two(width) * 4;
8222
8223                 switch (stride) {
8224                 default:
8225                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8226                                   width, stride);
8227                         stride = 256;
8228                         /* fallthrough */
8229                 case 256:
8230                 case 512:
8231                 case 1024:
8232                 case 2048:
8233                         break;
8234                 }
8235
8236                 cntl |= CURSOR_ENABLE |
8237                         CURSOR_GAMMA_ENABLE |
8238                         CURSOR_FORMAT_ARGB |
8239                         CURSOR_STRIDE(stride);
8240
8241                 size = (height << 12) | width;
8242         }
8243
8244         if (intel_crtc->cursor_cntl != 0 &&
8245             (intel_crtc->cursor_base != base ||
8246              intel_crtc->cursor_size != size ||
8247              intel_crtc->cursor_cntl != cntl)) {
8248                 /* On these chipsets we can only modify the base/size/stride
8249                  * whilst the cursor is disabled.
8250                  */
8251                 I915_WRITE(_CURACNTR, 0);
8252                 POSTING_READ(_CURACNTR);
8253                 intel_crtc->cursor_cntl = 0;
8254         }
8255
8256         if (intel_crtc->cursor_base != base)
8257                 I915_WRITE(_CURABASE, base);
8258
8259         if (intel_crtc->cursor_size != size) {
8260                 I915_WRITE(CURSIZE, size);
8261                 intel_crtc->cursor_size = size;
8262         }
8263
8264         if (intel_crtc->cursor_cntl != cntl) {
8265                 I915_WRITE(_CURACNTR, cntl);
8266                 POSTING_READ(_CURACNTR);
8267                 intel_crtc->cursor_cntl = cntl;
8268         }
8269 }
8270
8271 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8272 {
8273         struct drm_device *dev = crtc->dev;
8274         struct drm_i915_private *dev_priv = dev->dev_private;
8275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8276         int pipe = intel_crtc->pipe;
8277         uint32_t cntl;
8278
8279         cntl = 0;
8280         if (base) {
8281                 cntl = MCURSOR_GAMMA_ENABLE;
8282                 switch (intel_crtc->cursor_width) {
8283                         case 64:
8284                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8285                                 break;
8286                         case 128:
8287                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8288                                 break;
8289                         case 256:
8290                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8291                                 break;
8292                         default:
8293                                 WARN_ON(1);
8294                                 return;
8295                 }
8296                 cntl |= pipe << 28; /* Connect to correct pipe */
8297         }
8298         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8299                 cntl |= CURSOR_PIPE_CSC_ENABLE;
8300
8301         if (intel_crtc->cursor_cntl != cntl) {
8302                 I915_WRITE(CURCNTR(pipe), cntl);
8303                 POSTING_READ(CURCNTR(pipe));
8304                 intel_crtc->cursor_cntl = cntl;
8305         }
8306
8307         /* and commit changes on next vblank */
8308         I915_WRITE(CURBASE(pipe), base);
8309         POSTING_READ(CURBASE(pipe));
8310 }
8311
8312 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8313 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8314                                      bool on)
8315 {
8316         struct drm_device *dev = crtc->dev;
8317         struct drm_i915_private *dev_priv = dev->dev_private;
8318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8319         int pipe = intel_crtc->pipe;
8320         int x = crtc->cursor_x;
8321         int y = crtc->cursor_y;
8322         u32 base = 0, pos = 0;
8323
8324         if (on)
8325                 base = intel_crtc->cursor_addr;
8326
8327         if (x >= intel_crtc->config.pipe_src_w)
8328                 base = 0;
8329
8330         if (y >= intel_crtc->config.pipe_src_h)
8331                 base = 0;
8332
8333         if (x < 0) {
8334                 if (x + intel_crtc->cursor_width <= 0)
8335                         base = 0;
8336
8337                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8338                 x = -x;
8339         }
8340         pos |= x << CURSOR_X_SHIFT;
8341
8342         if (y < 0) {
8343                 if (y + intel_crtc->cursor_height <= 0)
8344                         base = 0;
8345
8346                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8347                 y = -y;
8348         }
8349         pos |= y << CURSOR_Y_SHIFT;
8350
8351         if (base == 0 && intel_crtc->cursor_base == 0)
8352                 return;
8353
8354         I915_WRITE(CURPOS(pipe), pos);
8355
8356         if (IS_845G(dev) || IS_I865G(dev))
8357                 i845_update_cursor(crtc, base);
8358         else
8359                 i9xx_update_cursor(crtc, base);
8360         intel_crtc->cursor_base = base;
8361 }
8362
8363 static bool cursor_size_ok(struct drm_device *dev,
8364                            uint32_t width, uint32_t height)
8365 {
8366         if (width == 0 || height == 0)
8367                 return false;
8368
8369         /*
8370          * 845g/865g are special in that they are only limited by
8371          * the width of their cursors, the height is arbitrary up to
8372          * the precision of the register. Everything else requires
8373          * square cursors, limited to a few power-of-two sizes.
8374          */
8375         if (IS_845G(dev) || IS_I865G(dev)) {
8376                 if ((width & 63) != 0)
8377                         return false;
8378
8379                 if (width > (IS_845G(dev) ? 64 : 512))
8380                         return false;
8381
8382                 if (height > 1023)
8383                         return false;
8384         } else {
8385                 switch (width | height) {
8386                 case 256:
8387                 case 128:
8388                         if (IS_GEN2(dev))
8389                                 return false;
8390                 case 64:
8391                         break;
8392                 default:
8393                         return false;
8394                 }
8395         }
8396
8397         return true;
8398 }
8399
8400 /*
8401  * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8402  *
8403  * Note that the object's reference will be consumed if the update fails.  If
8404  * the update succeeds, the reference of the old object (if any) will be
8405  * consumed.
8406  */
8407 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8408                                      struct drm_i915_gem_object *obj,
8409                                      uint32_t width, uint32_t height)
8410 {
8411         struct drm_device *dev = crtc->dev;
8412         struct drm_i915_private *dev_priv = dev->dev_private;
8413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8414         enum pipe pipe = intel_crtc->pipe;
8415         unsigned old_width, stride;
8416         uint32_t addr;
8417         int ret;
8418
8419         /* if we want to turn off the cursor ignore width and height */
8420         if (!obj) {
8421                 DRM_DEBUG_KMS("cursor off\n");
8422                 addr = 0;
8423                 mutex_lock(&dev->struct_mutex);
8424                 goto finish;
8425         }
8426
8427         /* Check for which cursor types we support */
8428         if (!cursor_size_ok(dev, width, height)) {
8429                 DRM_DEBUG("Cursor dimension not supported\n");
8430                 return -EINVAL;
8431         }
8432
8433         stride = roundup_pow_of_two(width) * 4;
8434         if (obj->base.size < stride * height) {
8435                 DRM_DEBUG_KMS("buffer is too small\n");
8436                 ret = -ENOMEM;
8437                 goto fail;
8438         }
8439
8440         /* we only need to pin inside GTT if cursor is non-phy */
8441         mutex_lock(&dev->struct_mutex);
8442         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8443                 unsigned alignment;
8444
8445                 if (obj->tiling_mode) {
8446                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8447                         ret = -EINVAL;
8448                         goto fail_locked;
8449                 }
8450
8451                 /*
8452                  * Global gtt pte registers are special registers which actually
8453                  * forward writes to a chunk of system memory. Which means that
8454                  * there is no risk that the register values disappear as soon
8455                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8456                  * only the pin/unpin/fence and not more.
8457                  */
8458                 intel_runtime_pm_get(dev_priv);
8459
8460                 /* Note that the w/a also requires 2 PTE of padding following
8461                  * the bo. We currently fill all unused PTE with the shadow
8462                  * page and so we should always have valid PTE following the
8463                  * cursor preventing the VT-d warning.
8464                  */
8465                 alignment = 0;
8466                 if (need_vtd_wa(dev))
8467                         alignment = 64*1024;
8468
8469                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8470                 if (ret) {
8471                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8472                         intel_runtime_pm_put(dev_priv);
8473                         goto fail_locked;
8474                 }
8475
8476                 ret = i915_gem_object_put_fence(obj);
8477                 if (ret) {
8478                         DRM_DEBUG_KMS("failed to release fence for cursor");
8479                         intel_runtime_pm_put(dev_priv);
8480                         goto fail_unpin;
8481                 }
8482
8483                 addr = i915_gem_obj_ggtt_offset(obj);
8484
8485                 intel_runtime_pm_put(dev_priv);
8486         } else {
8487                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8488                 ret = i915_gem_object_attach_phys(obj, align);
8489                 if (ret) {
8490                         DRM_DEBUG_KMS("failed to attach phys object\n");
8491                         goto fail_locked;
8492                 }
8493                 addr = obj->phys_handle->busaddr;
8494         }
8495
8496  finish:
8497         if (intel_crtc->cursor_bo) {
8498                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8499                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8500         }
8501
8502         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8503                           INTEL_FRONTBUFFER_CURSOR(pipe));
8504         mutex_unlock(&dev->struct_mutex);
8505
8506         old_width = intel_crtc->cursor_width;
8507
8508         intel_crtc->cursor_addr = addr;
8509         intel_crtc->cursor_bo = obj;
8510         intel_crtc->cursor_width = width;
8511         intel_crtc->cursor_height = height;
8512
8513         if (intel_crtc->active) {
8514                 if (old_width != width)
8515                         intel_update_watermarks(crtc);
8516                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8517         }
8518
8519         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8520
8521         return 0;
8522 fail_unpin:
8523         i915_gem_object_unpin_from_display_plane(obj);
8524 fail_locked:
8525         mutex_unlock(&dev->struct_mutex);
8526 fail:
8527         drm_gem_object_unreference_unlocked(&obj->base);
8528         return ret;
8529 }
8530
8531 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8532                                  u16 *blue, uint32_t start, uint32_t size)
8533 {
8534         int end = (start + size > 256) ? 256 : start + size, i;
8535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8536
8537         for (i = start; i < end; i++) {
8538                 intel_crtc->lut_r[i] = red[i] >> 8;
8539                 intel_crtc->lut_g[i] = green[i] >> 8;
8540                 intel_crtc->lut_b[i] = blue[i] >> 8;
8541         }
8542
8543         intel_crtc_load_lut(crtc);
8544 }
8545
8546 /* VESA 640x480x72Hz mode to set on the pipe */
8547 static struct drm_display_mode load_detect_mode = {
8548         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8549                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8550 };
8551
8552 struct drm_framebuffer *
8553 __intel_framebuffer_create(struct drm_device *dev,
8554                            struct drm_mode_fb_cmd2 *mode_cmd,
8555                            struct drm_i915_gem_object *obj)
8556 {
8557         struct intel_framebuffer *intel_fb;
8558         int ret;
8559
8560         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8561         if (!intel_fb) {
8562                 drm_gem_object_unreference_unlocked(&obj->base);
8563                 return ERR_PTR(-ENOMEM);
8564         }
8565
8566         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8567         if (ret)
8568                 goto err;
8569
8570         return &intel_fb->base;
8571 err:
8572         drm_gem_object_unreference_unlocked(&obj->base);
8573         kfree(intel_fb);
8574
8575         return ERR_PTR(ret);
8576 }
8577
8578 static struct drm_framebuffer *
8579 intel_framebuffer_create(struct drm_device *dev,
8580                          struct drm_mode_fb_cmd2 *mode_cmd,
8581                          struct drm_i915_gem_object *obj)
8582 {
8583         struct drm_framebuffer *fb;
8584         int ret;
8585
8586         ret = i915_mutex_lock_interruptible(dev);
8587         if (ret)
8588                 return ERR_PTR(ret);
8589         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8590         mutex_unlock(&dev->struct_mutex);
8591
8592         return fb;
8593 }
8594
8595 static u32
8596 intel_framebuffer_pitch_for_width(int width, int bpp)
8597 {
8598         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8599         return ALIGN(pitch, 64);
8600 }
8601
8602 static u32
8603 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8604 {
8605         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8606         return PAGE_ALIGN(pitch * mode->vdisplay);
8607 }
8608
8609 static struct drm_framebuffer *
8610 intel_framebuffer_create_for_mode(struct drm_device *dev,
8611                                   struct drm_display_mode *mode,
8612                                   int depth, int bpp)
8613 {
8614         struct drm_i915_gem_object *obj;
8615         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8616
8617         obj = i915_gem_alloc_object(dev,
8618                                     intel_framebuffer_size_for_mode(mode, bpp));
8619         if (obj == NULL)
8620                 return ERR_PTR(-ENOMEM);
8621
8622         mode_cmd.width = mode->hdisplay;
8623         mode_cmd.height = mode->vdisplay;
8624         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8625                                                                 bpp);
8626         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8627
8628         return intel_framebuffer_create(dev, &mode_cmd, obj);
8629 }
8630
8631 static struct drm_framebuffer *
8632 mode_fits_in_fbdev(struct drm_device *dev,
8633                    struct drm_display_mode *mode)
8634 {
8635 #ifdef CONFIG_DRM_I915_FBDEV
8636         struct drm_i915_private *dev_priv = dev->dev_private;
8637         struct drm_i915_gem_object *obj;
8638         struct drm_framebuffer *fb;
8639
8640         if (!dev_priv->fbdev)
8641                 return NULL;
8642
8643         if (!dev_priv->fbdev->fb)
8644                 return NULL;
8645
8646         obj = dev_priv->fbdev->fb->obj;
8647         BUG_ON(!obj);
8648
8649         fb = &dev_priv->fbdev->fb->base;
8650         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8651                                                                fb->bits_per_pixel))
8652                 return NULL;
8653
8654         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8655                 return NULL;
8656
8657         return fb;
8658 #else
8659         return NULL;
8660 #endif
8661 }
8662
8663 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8664                                 struct drm_display_mode *mode,
8665                                 struct intel_load_detect_pipe *old,
8666                                 struct drm_modeset_acquire_ctx *ctx)
8667 {
8668         struct intel_crtc *intel_crtc;
8669         struct intel_encoder *intel_encoder =
8670                 intel_attached_encoder(connector);
8671         struct drm_crtc *possible_crtc;
8672         struct drm_encoder *encoder = &intel_encoder->base;
8673         struct drm_crtc *crtc = NULL;
8674         struct drm_device *dev = encoder->dev;
8675         struct drm_framebuffer *fb;
8676         struct drm_mode_config *config = &dev->mode_config;
8677         int ret, i = -1;
8678
8679         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8680                       connector->base.id, connector->name,
8681                       encoder->base.id, encoder->name);
8682
8683 retry:
8684         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8685         if (ret)
8686                 goto fail_unlock;
8687
8688         /*
8689          * Algorithm gets a little messy:
8690          *
8691          *   - if the connector already has an assigned crtc, use it (but make
8692          *     sure it's on first)
8693          *
8694          *   - try to find the first unused crtc that can drive this connector,
8695          *     and use that if we find one
8696          */
8697
8698         /* See if we already have a CRTC for this connector */
8699         if (encoder->crtc) {
8700                 crtc = encoder->crtc;
8701
8702                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8703                 if (ret)
8704                         goto fail_unlock;
8705
8706                 old->dpms_mode = connector->dpms;
8707                 old->load_detect_temp = false;
8708
8709                 /* Make sure the crtc and connector are running */
8710                 if (connector->dpms != DRM_MODE_DPMS_ON)
8711                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8712
8713                 return true;
8714         }
8715
8716         /* Find an unused one (if possible) */
8717         for_each_crtc(dev, possible_crtc) {
8718                 i++;
8719                 if (!(encoder->possible_crtcs & (1 << i)))
8720                         continue;
8721                 if (possible_crtc->enabled)
8722                         continue;
8723                 /* This can occur when applying the pipe A quirk on resume. */
8724                 if (to_intel_crtc(possible_crtc)->new_enabled)
8725                         continue;
8726
8727                 crtc = possible_crtc;
8728                 break;
8729         }
8730
8731         /*
8732          * If we didn't find an unused CRTC, don't use any.
8733          */
8734         if (!crtc) {
8735                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8736                 goto fail_unlock;
8737         }
8738
8739         ret = drm_modeset_lock(&crtc->mutex, ctx);
8740         if (ret)
8741                 goto fail_unlock;
8742         intel_encoder->new_crtc = to_intel_crtc(crtc);
8743         to_intel_connector(connector)->new_encoder = intel_encoder;
8744
8745         intel_crtc = to_intel_crtc(crtc);
8746         intel_crtc->new_enabled = true;
8747         intel_crtc->new_config = &intel_crtc->config;
8748         old->dpms_mode = connector->dpms;
8749         old->load_detect_temp = true;
8750         old->release_fb = NULL;
8751
8752         if (!mode)
8753                 mode = &load_detect_mode;
8754
8755         /* We need a framebuffer large enough to accommodate all accesses
8756          * that the plane may generate whilst we perform load detection.
8757          * We can not rely on the fbcon either being present (we get called
8758          * during its initialisation to detect all boot displays, or it may
8759          * not even exist) or that it is large enough to satisfy the
8760          * requested mode.
8761          */
8762         fb = mode_fits_in_fbdev(dev, mode);
8763         if (fb == NULL) {
8764                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8765                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8766                 old->release_fb = fb;
8767         } else
8768                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8769         if (IS_ERR(fb)) {
8770                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8771                 goto fail;
8772         }
8773
8774         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8775                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8776                 if (old->release_fb)
8777                         old->release_fb->funcs->destroy(old->release_fb);
8778                 goto fail;
8779         }
8780
8781         /* let the connector get through one full cycle before testing */
8782         intel_wait_for_vblank(dev, intel_crtc->pipe);
8783         return true;
8784
8785  fail:
8786         intel_crtc->new_enabled = crtc->enabled;
8787         if (intel_crtc->new_enabled)
8788                 intel_crtc->new_config = &intel_crtc->config;
8789         else
8790                 intel_crtc->new_config = NULL;
8791 fail_unlock:
8792         if (ret == -EDEADLK) {
8793                 drm_modeset_backoff(ctx);
8794                 goto retry;
8795         }
8796
8797         return false;
8798 }
8799
8800 void intel_release_load_detect_pipe(struct drm_connector *connector,
8801                                     struct intel_load_detect_pipe *old)
8802 {
8803         struct intel_encoder *intel_encoder =
8804                 intel_attached_encoder(connector);
8805         struct drm_encoder *encoder = &intel_encoder->base;
8806         struct drm_crtc *crtc = encoder->crtc;
8807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8808
8809         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8810                       connector->base.id, connector->name,
8811                       encoder->base.id, encoder->name);
8812
8813         if (old->load_detect_temp) {
8814                 to_intel_connector(connector)->new_encoder = NULL;
8815                 intel_encoder->new_crtc = NULL;
8816                 intel_crtc->new_enabled = false;
8817                 intel_crtc->new_config = NULL;
8818                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8819
8820                 if (old->release_fb) {
8821                         drm_framebuffer_unregister_private(old->release_fb);
8822                         drm_framebuffer_unreference(old->release_fb);
8823                 }
8824
8825                 return;
8826         }
8827
8828         /* Switch crtc and encoder back off if necessary */
8829         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8830                 connector->funcs->dpms(connector, old->dpms_mode);
8831 }
8832
8833 static int i9xx_pll_refclk(struct drm_device *dev,
8834                            const struct intel_crtc_config *pipe_config)
8835 {
8836         struct drm_i915_private *dev_priv = dev->dev_private;
8837         u32 dpll = pipe_config->dpll_hw_state.dpll;
8838
8839         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8840                 return dev_priv->vbt.lvds_ssc_freq;
8841         else if (HAS_PCH_SPLIT(dev))
8842                 return 120000;
8843         else if (!IS_GEN2(dev))
8844                 return 96000;
8845         else
8846                 return 48000;
8847 }
8848
8849 /* Returns the clock of the currently programmed mode of the given pipe. */
8850 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8851                                 struct intel_crtc_config *pipe_config)
8852 {
8853         struct drm_device *dev = crtc->base.dev;
8854         struct drm_i915_private *dev_priv = dev->dev_private;
8855         int pipe = pipe_config->cpu_transcoder;
8856         u32 dpll = pipe_config->dpll_hw_state.dpll;
8857         u32 fp;
8858         intel_clock_t clock;
8859         int refclk = i9xx_pll_refclk(dev, pipe_config);
8860
8861         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8862                 fp = pipe_config->dpll_hw_state.fp0;
8863         else
8864                 fp = pipe_config->dpll_hw_state.fp1;
8865
8866         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8867         if (IS_PINEVIEW(dev)) {
8868                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8869                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8870         } else {
8871                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8872                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8873         }
8874
8875         if (!IS_GEN2(dev)) {
8876                 if (IS_PINEVIEW(dev))
8877                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8878                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8879                 else
8880                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8881                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8882
8883                 switch (dpll & DPLL_MODE_MASK) {
8884                 case DPLLB_MODE_DAC_SERIAL:
8885                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8886                                 5 : 10;
8887                         break;
8888                 case DPLLB_MODE_LVDS:
8889                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8890                                 7 : 14;
8891                         break;
8892                 default:
8893                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8894                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8895                         return;
8896                 }
8897
8898                 if (IS_PINEVIEW(dev))
8899                         pineview_clock(refclk, &clock);
8900                 else
8901                         i9xx_clock(refclk, &clock);
8902         } else {
8903                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8904                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8905
8906                 if (is_lvds) {
8907                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8908                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8909
8910                         if (lvds & LVDS_CLKB_POWER_UP)
8911                                 clock.p2 = 7;
8912                         else
8913                                 clock.p2 = 14;
8914                 } else {
8915                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8916                                 clock.p1 = 2;
8917                         else {
8918                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8919                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8920                         }
8921                         if (dpll & PLL_P2_DIVIDE_BY_4)
8922                                 clock.p2 = 4;
8923                         else
8924                                 clock.p2 = 2;
8925                 }
8926
8927                 i9xx_clock(refclk, &clock);
8928         }
8929
8930         /*
8931          * This value includes pixel_multiplier. We will use
8932          * port_clock to compute adjusted_mode.crtc_clock in the
8933          * encoder's get_config() function.
8934          */
8935         pipe_config->port_clock = clock.dot;
8936 }
8937
8938 int intel_dotclock_calculate(int link_freq,
8939                              const struct intel_link_m_n *m_n)
8940 {
8941         /*
8942          * The calculation for the data clock is:
8943          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8944          * But we want to avoid losing precison if possible, so:
8945          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8946          *
8947          * and the link clock is simpler:
8948          * link_clock = (m * link_clock) / n
8949          */
8950
8951         if (!m_n->link_n)
8952                 return 0;
8953
8954         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8955 }
8956
8957 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8958                                    struct intel_crtc_config *pipe_config)
8959 {
8960         struct drm_device *dev = crtc->base.dev;
8961
8962         /* read out port_clock from the DPLL */
8963         i9xx_crtc_clock_get(crtc, pipe_config);
8964
8965         /*
8966          * This value does not include pixel_multiplier.
8967          * We will check that port_clock and adjusted_mode.crtc_clock
8968          * agree once we know their relationship in the encoder's
8969          * get_config() function.
8970          */
8971         pipe_config->adjusted_mode.crtc_clock =
8972                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8973                                          &pipe_config->fdi_m_n);
8974 }
8975
8976 /** Returns the currently programmed mode of the given pipe. */
8977 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8978                                              struct drm_crtc *crtc)
8979 {
8980         struct drm_i915_private *dev_priv = dev->dev_private;
8981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8982         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8983         struct drm_display_mode *mode;
8984         struct intel_crtc_config pipe_config;
8985         int htot = I915_READ(HTOTAL(cpu_transcoder));
8986         int hsync = I915_READ(HSYNC(cpu_transcoder));
8987         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8988         int vsync = I915_READ(VSYNC(cpu_transcoder));
8989         enum pipe pipe = intel_crtc->pipe;
8990
8991         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8992         if (!mode)
8993                 return NULL;
8994
8995         /*
8996          * Construct a pipe_config sufficient for getting the clock info
8997          * back out of crtc_clock_get.
8998          *
8999          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9000          * to use a real value here instead.
9001          */
9002         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9003         pipe_config.pixel_multiplier = 1;
9004         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9005         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9006         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9007         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9008
9009         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9010         mode->hdisplay = (htot & 0xffff) + 1;
9011         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9012         mode->hsync_start = (hsync & 0xffff) + 1;
9013         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9014         mode->vdisplay = (vtot & 0xffff) + 1;
9015         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9016         mode->vsync_start = (vsync & 0xffff) + 1;
9017         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9018
9019         drm_mode_set_name(mode);
9020
9021         return mode;
9022 }
9023
9024 static void intel_increase_pllclock(struct drm_device *dev,
9025                                     enum pipe pipe)
9026 {
9027         struct drm_i915_private *dev_priv = dev->dev_private;
9028         int dpll_reg = DPLL(pipe);
9029         int dpll;
9030
9031         if (!HAS_GMCH_DISPLAY(dev))
9032                 return;
9033
9034         if (!dev_priv->lvds_downclock_avail)
9035                 return;
9036
9037         dpll = I915_READ(dpll_reg);
9038         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9039                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9040
9041                 assert_panel_unlocked(dev_priv, pipe);
9042
9043                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9044                 I915_WRITE(dpll_reg, dpll);
9045                 intel_wait_for_vblank(dev, pipe);
9046
9047                 dpll = I915_READ(dpll_reg);
9048                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9049                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9050         }
9051 }
9052
9053 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9054 {
9055         struct drm_device *dev = crtc->dev;
9056         struct drm_i915_private *dev_priv = dev->dev_private;
9057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9058
9059         if (!HAS_GMCH_DISPLAY(dev))
9060                 return;
9061
9062         if (!dev_priv->lvds_downclock_avail)
9063                 return;
9064
9065         /*
9066          * Since this is called by a timer, we should never get here in
9067          * the manual case.
9068          */
9069         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9070                 int pipe = intel_crtc->pipe;
9071                 int dpll_reg = DPLL(pipe);
9072                 int dpll;
9073
9074                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9075
9076                 assert_panel_unlocked(dev_priv, pipe);
9077
9078                 dpll = I915_READ(dpll_reg);
9079                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9080                 I915_WRITE(dpll_reg, dpll);
9081                 intel_wait_for_vblank(dev, pipe);
9082                 dpll = I915_READ(dpll_reg);
9083                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9084                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9085         }
9086
9087 }
9088
9089 void intel_mark_busy(struct drm_device *dev)
9090 {
9091         struct drm_i915_private *dev_priv = dev->dev_private;
9092
9093         if (dev_priv->mm.busy)
9094                 return;
9095
9096         intel_runtime_pm_get(dev_priv);
9097         i915_update_gfx_val(dev_priv);
9098         dev_priv->mm.busy = true;
9099 }
9100
9101 void intel_mark_idle(struct drm_device *dev)
9102 {
9103         struct drm_i915_private *dev_priv = dev->dev_private;
9104         struct drm_crtc *crtc;
9105
9106         if (!dev_priv->mm.busy)
9107                 return;
9108
9109         dev_priv->mm.busy = false;
9110
9111         if (!i915.powersave)
9112                 goto out;
9113
9114         for_each_crtc(dev, crtc) {
9115                 if (!crtc->primary->fb)
9116                         continue;
9117
9118                 intel_decrease_pllclock(crtc);
9119         }
9120
9121         if (INTEL_INFO(dev)->gen >= 6)
9122                 gen6_rps_idle(dev->dev_private);
9123
9124 out:
9125         intel_runtime_pm_put(dev_priv);
9126 }
9127
9128
9129 /**
9130  * intel_mark_fb_busy - mark given planes as busy
9131  * @dev: DRM device
9132  * @frontbuffer_bits: bits for the affected planes
9133  * @ring: optional ring for asynchronous commands
9134  *
9135  * This function gets called every time the screen contents change. It can be
9136  * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9137  */
9138 static void intel_mark_fb_busy(struct drm_device *dev,
9139                                unsigned frontbuffer_bits,
9140                                struct intel_engine_cs *ring)
9141 {
9142         struct drm_i915_private *dev_priv = dev->dev_private;
9143         enum pipe pipe;
9144
9145         if (!i915.powersave)
9146                 return;
9147
9148         for_each_pipe(dev_priv, pipe) {
9149                 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9150                         continue;
9151
9152                 intel_increase_pllclock(dev, pipe);
9153                 if (ring && intel_fbc_enabled(dev))
9154                         ring->fbc_dirty = true;
9155         }
9156 }
9157
9158 /**
9159  * intel_fb_obj_invalidate - invalidate frontbuffer object
9160  * @obj: GEM object to invalidate
9161  * @ring: set for asynchronous rendering
9162  *
9163  * This function gets called every time rendering on the given object starts and
9164  * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9165  * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9166  * until the rendering completes or a flip on this frontbuffer plane is
9167  * scheduled.
9168  */
9169 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9170                              struct intel_engine_cs *ring)
9171 {
9172         struct drm_device *dev = obj->base.dev;
9173         struct drm_i915_private *dev_priv = dev->dev_private;
9174
9175         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9176
9177         if (!obj->frontbuffer_bits)
9178                 return;
9179
9180         if (ring) {
9181                 mutex_lock(&dev_priv->fb_tracking.lock);
9182                 dev_priv->fb_tracking.busy_bits
9183                         |= obj->frontbuffer_bits;
9184                 dev_priv->fb_tracking.flip_bits
9185                         &= ~obj->frontbuffer_bits;
9186                 mutex_unlock(&dev_priv->fb_tracking.lock);
9187         }
9188
9189         intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9190
9191         intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9192 }
9193
9194 /**
9195  * intel_frontbuffer_flush - flush frontbuffer
9196  * @dev: DRM device
9197  * @frontbuffer_bits: frontbuffer plane tracking bits
9198  *
9199  * This function gets called every time rendering on the given planes has
9200  * completed and frontbuffer caching can be started again. Flushes will get
9201  * delayed if they're blocked by some oustanding asynchronous rendering.
9202  *
9203  * Can be called without any locks held.
9204  */
9205 void intel_frontbuffer_flush(struct drm_device *dev,
9206                              unsigned frontbuffer_bits)
9207 {
9208         struct drm_i915_private *dev_priv = dev->dev_private;
9209
9210         /* Delay flushing when rings are still busy.*/
9211         mutex_lock(&dev_priv->fb_tracking.lock);
9212         frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9213         mutex_unlock(&dev_priv->fb_tracking.lock);
9214
9215         intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9216
9217         intel_edp_psr_flush(dev, frontbuffer_bits);
9218
9219         /*
9220          * FIXME: Unconditional fbc flushing here is a rather gross hack and
9221          * needs to be reworked into a proper frontbuffer tracking scheme like
9222          * psr employs.
9223          */
9224         if (IS_BROADWELL(dev))
9225                 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9226 }
9227
9228 /**
9229  * intel_fb_obj_flush - flush frontbuffer object
9230  * @obj: GEM object to flush
9231  * @retire: set when retiring asynchronous rendering
9232  *
9233  * This function gets called every time rendering on the given object has
9234  * completed and frontbuffer caching can be started again. If @retire is true
9235  * then any delayed flushes will be unblocked.
9236  */
9237 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9238                         bool retire)
9239 {
9240         struct drm_device *dev = obj->base.dev;
9241         struct drm_i915_private *dev_priv = dev->dev_private;
9242         unsigned frontbuffer_bits;
9243
9244         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9245
9246         if (!obj->frontbuffer_bits)
9247                 return;
9248
9249         frontbuffer_bits = obj->frontbuffer_bits;
9250
9251         if (retire) {
9252                 mutex_lock(&dev_priv->fb_tracking.lock);
9253                 /* Filter out new bits since rendering started. */
9254                 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9255
9256                 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9257                 mutex_unlock(&dev_priv->fb_tracking.lock);
9258         }
9259
9260         intel_frontbuffer_flush(dev, frontbuffer_bits);
9261 }
9262
9263 /**
9264  * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9265  * @dev: DRM device
9266  * @frontbuffer_bits: frontbuffer plane tracking bits
9267  *
9268  * This function gets called after scheduling a flip on @obj. The actual
9269  * frontbuffer flushing will be delayed until completion is signalled with
9270  * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9271  * flush will be cancelled.
9272  *
9273  * Can be called without any locks held.
9274  */
9275 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9276                                     unsigned frontbuffer_bits)
9277 {
9278         struct drm_i915_private *dev_priv = dev->dev_private;
9279
9280         mutex_lock(&dev_priv->fb_tracking.lock);
9281         dev_priv->fb_tracking.flip_bits
9282                 |= frontbuffer_bits;
9283         mutex_unlock(&dev_priv->fb_tracking.lock);
9284 }
9285
9286 /**
9287  * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9288  * @dev: DRM device
9289  * @frontbuffer_bits: frontbuffer plane tracking bits
9290  *
9291  * This function gets called after the flip has been latched and will complete
9292  * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9293  *
9294  * Can be called without any locks held.
9295  */
9296 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9297                                      unsigned frontbuffer_bits)
9298 {
9299         struct drm_i915_private *dev_priv = dev->dev_private;
9300
9301         mutex_lock(&dev_priv->fb_tracking.lock);
9302         /* Mask any cancelled flips. */
9303         frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9304         dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9305         mutex_unlock(&dev_priv->fb_tracking.lock);
9306
9307         intel_frontbuffer_flush(dev, frontbuffer_bits);
9308 }
9309
9310 static void intel_crtc_destroy(struct drm_crtc *crtc)
9311 {
9312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9313         struct drm_device *dev = crtc->dev;
9314         struct intel_unpin_work *work;
9315         unsigned long flags;
9316
9317         spin_lock_irqsave(&dev->event_lock, flags);
9318         work = intel_crtc->unpin_work;
9319         intel_crtc->unpin_work = NULL;
9320         spin_unlock_irqrestore(&dev->event_lock, flags);
9321
9322         if (work) {
9323                 cancel_work_sync(&work->work);
9324                 kfree(work);
9325         }
9326
9327         drm_crtc_cleanup(crtc);
9328
9329         kfree(intel_crtc);
9330 }
9331
9332 static void intel_unpin_work_fn(struct work_struct *__work)
9333 {
9334         struct intel_unpin_work *work =
9335                 container_of(__work, struct intel_unpin_work, work);
9336         struct drm_device *dev = work->crtc->dev;
9337         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9338
9339         mutex_lock(&dev->struct_mutex);
9340         intel_unpin_fb_obj(work->old_fb_obj);
9341         drm_gem_object_unreference(&work->pending_flip_obj->base);
9342         drm_gem_object_unreference(&work->old_fb_obj->base);
9343
9344         intel_update_fbc(dev);
9345         mutex_unlock(&dev->struct_mutex);
9346
9347         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9348
9349         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9350         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9351
9352         kfree(work);
9353 }
9354
9355 static void do_intel_finish_page_flip(struct drm_device *dev,
9356                                       struct drm_crtc *crtc)
9357 {
9358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9359         struct intel_unpin_work *work;
9360         unsigned long flags;
9361
9362         /* Ignore early vblank irqs */
9363         if (intel_crtc == NULL)
9364                 return;
9365
9366         spin_lock_irqsave(&dev->event_lock, flags);
9367         work = intel_crtc->unpin_work;
9368
9369         /* Ensure we don't miss a work->pending update ... */
9370         smp_rmb();
9371
9372         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9373                 spin_unlock_irqrestore(&dev->event_lock, flags);
9374                 return;
9375         }
9376
9377         page_flip_completed(intel_crtc);
9378
9379         spin_unlock_irqrestore(&dev->event_lock, flags);
9380 }
9381
9382 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9383 {
9384         struct drm_i915_private *dev_priv = dev->dev_private;
9385         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9386
9387         do_intel_finish_page_flip(dev, crtc);
9388 }
9389
9390 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9391 {
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9394
9395         do_intel_finish_page_flip(dev, crtc);
9396 }
9397
9398 /* Is 'a' after or equal to 'b'? */
9399 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9400 {
9401         return !((a - b) & 0x80000000);
9402 }
9403
9404 static bool page_flip_finished(struct intel_crtc *crtc)
9405 {
9406         struct drm_device *dev = crtc->base.dev;
9407         struct drm_i915_private *dev_priv = dev->dev_private;
9408
9409         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9410             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9411                 return true;
9412
9413         /*
9414          * The relevant registers doen't exist on pre-ctg.
9415          * As the flip done interrupt doesn't trigger for mmio
9416          * flips on gmch platforms, a flip count check isn't
9417          * really needed there. But since ctg has the registers,
9418          * include it in the check anyway.
9419          */
9420         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9421                 return true;
9422
9423         /*
9424          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9425          * used the same base address. In that case the mmio flip might
9426          * have completed, but the CS hasn't even executed the flip yet.
9427          *
9428          * A flip count check isn't enough as the CS might have updated
9429          * the base address just after start of vblank, but before we
9430          * managed to process the interrupt. This means we'd complete the
9431          * CS flip too soon.
9432          *
9433          * Combining both checks should get us a good enough result. It may
9434          * still happen that the CS flip has been executed, but has not
9435          * yet actually completed. But in case the base address is the same
9436          * anyway, we don't really care.
9437          */
9438         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9439                 crtc->unpin_work->gtt_offset &&
9440                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9441                                     crtc->unpin_work->flip_count);
9442 }
9443
9444 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9445 {
9446         struct drm_i915_private *dev_priv = dev->dev_private;
9447         struct intel_crtc *intel_crtc =
9448                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9449         unsigned long flags;
9450
9451         /* NB: An MMIO update of the plane base pointer will also
9452          * generate a page-flip completion irq, i.e. every modeset
9453          * is also accompanied by a spurious intel_prepare_page_flip().
9454          */
9455         spin_lock_irqsave(&dev->event_lock, flags);
9456         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9457                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9458         spin_unlock_irqrestore(&dev->event_lock, flags);
9459 }
9460
9461 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9462 {
9463         /* Ensure that the work item is consistent when activating it ... */
9464         smp_wmb();
9465         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9466         /* and that it is marked active as soon as the irq could fire. */
9467         smp_wmb();
9468 }
9469
9470 static int intel_gen2_queue_flip(struct drm_device *dev,
9471                                  struct drm_crtc *crtc,
9472                                  struct drm_framebuffer *fb,
9473                                  struct drm_i915_gem_object *obj,
9474                                  struct intel_engine_cs *ring,
9475                                  uint32_t flags)
9476 {
9477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9478         u32 flip_mask;
9479         int ret;
9480
9481         ret = intel_ring_begin(ring, 6);
9482         if (ret)
9483                 return ret;
9484
9485         /* Can't queue multiple flips, so wait for the previous
9486          * one to finish before executing the next.
9487          */
9488         if (intel_crtc->plane)
9489                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9490         else
9491                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9492         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9493         intel_ring_emit(ring, MI_NOOP);
9494         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9495                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9496         intel_ring_emit(ring, fb->pitches[0]);
9497         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9498         intel_ring_emit(ring, 0); /* aux display base address, unused */
9499
9500         intel_mark_page_flip_active(intel_crtc);
9501         __intel_ring_advance(ring);
9502         return 0;
9503 }
9504
9505 static int intel_gen3_queue_flip(struct drm_device *dev,
9506                                  struct drm_crtc *crtc,
9507                                  struct drm_framebuffer *fb,
9508                                  struct drm_i915_gem_object *obj,
9509                                  struct intel_engine_cs *ring,
9510                                  uint32_t flags)
9511 {
9512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9513         u32 flip_mask;
9514         int ret;
9515
9516         ret = intel_ring_begin(ring, 6);
9517         if (ret)
9518                 return ret;
9519
9520         if (intel_crtc->plane)
9521                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9522         else
9523                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9524         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9525         intel_ring_emit(ring, MI_NOOP);
9526         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9527                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9528         intel_ring_emit(ring, fb->pitches[0]);
9529         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9530         intel_ring_emit(ring, MI_NOOP);
9531
9532         intel_mark_page_flip_active(intel_crtc);
9533         __intel_ring_advance(ring);
9534         return 0;
9535 }
9536
9537 static int intel_gen4_queue_flip(struct drm_device *dev,
9538                                  struct drm_crtc *crtc,
9539                                  struct drm_framebuffer *fb,
9540                                  struct drm_i915_gem_object *obj,
9541                                  struct intel_engine_cs *ring,
9542                                  uint32_t flags)
9543 {
9544         struct drm_i915_private *dev_priv = dev->dev_private;
9545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9546         uint32_t pf, pipesrc;
9547         int ret;
9548
9549         ret = intel_ring_begin(ring, 4);
9550         if (ret)
9551                 return ret;
9552
9553         /* i965+ uses the linear or tiled offsets from the
9554          * Display Registers (which do not change across a page-flip)
9555          * so we need only reprogram the base address.
9556          */
9557         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9558                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9559         intel_ring_emit(ring, fb->pitches[0]);
9560         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9561                         obj->tiling_mode);
9562
9563         /* XXX Enabling the panel-fitter across page-flip is so far
9564          * untested on non-native modes, so ignore it for now.
9565          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9566          */
9567         pf = 0;
9568         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9569         intel_ring_emit(ring, pf | pipesrc);
9570
9571         intel_mark_page_flip_active(intel_crtc);
9572         __intel_ring_advance(ring);
9573         return 0;
9574 }
9575
9576 static int intel_gen6_queue_flip(struct drm_device *dev,
9577                                  struct drm_crtc *crtc,
9578                                  struct drm_framebuffer *fb,
9579                                  struct drm_i915_gem_object *obj,
9580                                  struct intel_engine_cs *ring,
9581                                  uint32_t flags)
9582 {
9583         struct drm_i915_private *dev_priv = dev->dev_private;
9584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9585         uint32_t pf, pipesrc;
9586         int ret;
9587
9588         ret = intel_ring_begin(ring, 4);
9589         if (ret)
9590                 return ret;
9591
9592         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9593                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9594         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9595         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9596
9597         /* Contrary to the suggestions in the documentation,
9598          * "Enable Panel Fitter" does not seem to be required when page
9599          * flipping with a non-native mode, and worse causes a normal
9600          * modeset to fail.
9601          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9602          */
9603         pf = 0;
9604         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9605         intel_ring_emit(ring, pf | pipesrc);
9606
9607         intel_mark_page_flip_active(intel_crtc);
9608         __intel_ring_advance(ring);
9609         return 0;
9610 }
9611
9612 static int intel_gen7_queue_flip(struct drm_device *dev,
9613                                  struct drm_crtc *crtc,
9614                                  struct drm_framebuffer *fb,
9615                                  struct drm_i915_gem_object *obj,
9616                                  struct intel_engine_cs *ring,
9617                                  uint32_t flags)
9618 {
9619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9620         uint32_t plane_bit = 0;
9621         int len, ret;
9622
9623         switch (intel_crtc->plane) {
9624         case PLANE_A:
9625                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9626                 break;
9627         case PLANE_B:
9628                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9629                 break;
9630         case PLANE_C:
9631                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9632                 break;
9633         default:
9634                 WARN_ONCE(1, "unknown plane in flip command\n");
9635                 return -ENODEV;
9636         }
9637
9638         len = 4;
9639         if (ring->id == RCS) {
9640                 len += 6;
9641                 /*
9642                  * On Gen 8, SRM is now taking an extra dword to accommodate
9643                  * 48bits addresses, and we need a NOOP for the batch size to
9644                  * stay even.
9645                  */
9646                 if (IS_GEN8(dev))
9647                         len += 2;
9648         }
9649
9650         /*
9651          * BSpec MI_DISPLAY_FLIP for IVB:
9652          * "The full packet must be contained within the same cache line."
9653          *
9654          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9655          * cacheline, if we ever start emitting more commands before
9656          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9657          * then do the cacheline alignment, and finally emit the
9658          * MI_DISPLAY_FLIP.
9659          */
9660         ret = intel_ring_cacheline_align(ring);
9661         if (ret)
9662                 return ret;
9663
9664         ret = intel_ring_begin(ring, len);
9665         if (ret)
9666                 return ret;
9667
9668         /* Unmask the flip-done completion message. Note that the bspec says that
9669          * we should do this for both the BCS and RCS, and that we must not unmask
9670          * more than one flip event at any time (or ensure that one flip message
9671          * can be sent by waiting for flip-done prior to queueing new flips).
9672          * Experimentation says that BCS works despite DERRMR masking all
9673          * flip-done completion events and that unmasking all planes at once
9674          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9675          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9676          */
9677         if (ring->id == RCS) {
9678                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9679                 intel_ring_emit(ring, DERRMR);
9680                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9681                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9682                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9683                 if (IS_GEN8(dev))
9684                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9685                                               MI_SRM_LRM_GLOBAL_GTT);
9686                 else
9687                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9688                                               MI_SRM_LRM_GLOBAL_GTT);
9689                 intel_ring_emit(ring, DERRMR);
9690                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9691                 if (IS_GEN8(dev)) {
9692                         intel_ring_emit(ring, 0);
9693                         intel_ring_emit(ring, MI_NOOP);
9694                 }
9695         }
9696
9697         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9698         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9699         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9700         intel_ring_emit(ring, (MI_NOOP));
9701
9702         intel_mark_page_flip_active(intel_crtc);
9703         __intel_ring_advance(ring);
9704         return 0;
9705 }
9706
9707 static bool use_mmio_flip(struct intel_engine_cs *ring,
9708                           struct drm_i915_gem_object *obj)
9709 {
9710         /*
9711          * This is not being used for older platforms, because
9712          * non-availability of flip done interrupt forces us to use
9713          * CS flips. Older platforms derive flip done using some clever
9714          * tricks involving the flip_pending status bits and vblank irqs.
9715          * So using MMIO flips there would disrupt this mechanism.
9716          */
9717
9718         if (ring == NULL)
9719                 return true;
9720
9721         if (INTEL_INFO(ring->dev)->gen < 5)
9722                 return false;
9723
9724         if (i915.use_mmio_flip < 0)
9725                 return false;
9726         else if (i915.use_mmio_flip > 0)
9727                 return true;
9728         else if (i915.enable_execlists)
9729                 return true;
9730         else
9731                 return ring != obj->ring;
9732 }
9733
9734 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9735 {
9736         struct drm_device *dev = intel_crtc->base.dev;
9737         struct drm_i915_private *dev_priv = dev->dev_private;
9738         struct intel_framebuffer *intel_fb =
9739                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9740         struct drm_i915_gem_object *obj = intel_fb->obj;
9741         u32 dspcntr;
9742         u32 reg;
9743
9744         intel_mark_page_flip_active(intel_crtc);
9745
9746         reg = DSPCNTR(intel_crtc->plane);
9747         dspcntr = I915_READ(reg);
9748
9749         if (INTEL_INFO(dev)->gen >= 4) {
9750                 if (obj->tiling_mode != I915_TILING_NONE)
9751                         dspcntr |= DISPPLANE_TILED;
9752                 else
9753                         dspcntr &= ~DISPPLANE_TILED;
9754         }
9755         I915_WRITE(reg, dspcntr);
9756
9757         I915_WRITE(DSPSURF(intel_crtc->plane),
9758                    intel_crtc->unpin_work->gtt_offset);
9759         POSTING_READ(DSPSURF(intel_crtc->plane));
9760 }
9761
9762 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9763 {
9764         struct intel_engine_cs *ring;
9765         int ret;
9766
9767         lockdep_assert_held(&obj->base.dev->struct_mutex);
9768
9769         if (!obj->last_write_seqno)
9770                 return 0;
9771
9772         ring = obj->ring;
9773
9774         if (i915_seqno_passed(ring->get_seqno(ring, true),
9775                               obj->last_write_seqno))
9776                 return 0;
9777
9778         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9779         if (ret)
9780                 return ret;
9781
9782         if (WARN_ON(!ring->irq_get(ring)))
9783                 return 0;
9784
9785         return 1;
9786 }
9787
9788 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9789 {
9790         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9791         struct intel_crtc *intel_crtc;
9792         unsigned long irq_flags;
9793         u32 seqno;
9794
9795         seqno = ring->get_seqno(ring, false);
9796
9797         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9798         for_each_intel_crtc(ring->dev, intel_crtc) {
9799                 struct intel_mmio_flip *mmio_flip;
9800
9801                 mmio_flip = &intel_crtc->mmio_flip;
9802                 if (mmio_flip->seqno == 0)
9803                         continue;
9804
9805                 if (ring->id != mmio_flip->ring_id)
9806                         continue;
9807
9808                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9809                         intel_do_mmio_flip(intel_crtc);
9810                         mmio_flip->seqno = 0;
9811                         ring->irq_put(ring);
9812                 }
9813         }
9814         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9815 }
9816
9817 static int intel_queue_mmio_flip(struct drm_device *dev,
9818                                  struct drm_crtc *crtc,
9819                                  struct drm_framebuffer *fb,
9820                                  struct drm_i915_gem_object *obj,
9821                                  struct intel_engine_cs *ring,
9822                                  uint32_t flags)
9823 {
9824         struct drm_i915_private *dev_priv = dev->dev_private;
9825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9826         unsigned long irq_flags;
9827         int ret;
9828
9829         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9830                 return -EBUSY;
9831
9832         ret = intel_postpone_flip(obj);
9833         if (ret < 0)
9834                 return ret;
9835         if (ret == 0) {
9836                 intel_do_mmio_flip(intel_crtc);
9837                 return 0;
9838         }
9839
9840         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9841         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9842         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9843         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9844
9845         /*
9846          * Double check to catch cases where irq fired before
9847          * mmio flip data was ready
9848          */
9849         intel_notify_mmio_flip(obj->ring);
9850         return 0;
9851 }
9852
9853 static int intel_default_queue_flip(struct drm_device *dev,
9854                                     struct drm_crtc *crtc,
9855                                     struct drm_framebuffer *fb,
9856                                     struct drm_i915_gem_object *obj,
9857                                     struct intel_engine_cs *ring,
9858                                     uint32_t flags)
9859 {
9860         return -ENODEV;
9861 }
9862
9863 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9864                                          struct drm_crtc *crtc)
9865 {
9866         struct drm_i915_private *dev_priv = dev->dev_private;
9867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9868         struct intel_unpin_work *work = intel_crtc->unpin_work;
9869         u32 addr;
9870
9871         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9872                 return true;
9873
9874         if (!work->enable_stall_check)
9875                 return false;
9876
9877         if (work->flip_ready_vblank == 0) {
9878                 if (work->flip_queued_ring &&
9879                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9880                                        work->flip_queued_seqno))
9881                         return false;
9882
9883                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9884         }
9885
9886         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9887                 return false;
9888
9889         /* Potential stall - if we see that the flip has happened,
9890          * assume a missed interrupt. */
9891         if (INTEL_INFO(dev)->gen >= 4)
9892                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9893         else
9894                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9895
9896         /* There is a potential issue here with a false positive after a flip
9897          * to the same address. We could address this by checking for a
9898          * non-incrementing frame counter.
9899          */
9900         return addr == work->gtt_offset;
9901 }
9902
9903 void intel_check_page_flip(struct drm_device *dev, int pipe)
9904 {
9905         struct drm_i915_private *dev_priv = dev->dev_private;
9906         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9908         unsigned long flags;
9909
9910         if (crtc == NULL)
9911                 return;
9912
9913         spin_lock_irqsave(&dev->event_lock, flags);
9914         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9915                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9916                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9917                 page_flip_completed(intel_crtc);
9918         }
9919         spin_unlock_irqrestore(&dev->event_lock, flags);
9920 }
9921
9922 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9923                                 struct drm_framebuffer *fb,
9924                                 struct drm_pending_vblank_event *event,
9925                                 uint32_t page_flip_flags)
9926 {
9927         struct drm_device *dev = crtc->dev;
9928         struct drm_i915_private *dev_priv = dev->dev_private;
9929         struct drm_framebuffer *old_fb = crtc->primary->fb;
9930         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9932         enum pipe pipe = intel_crtc->pipe;
9933         struct intel_unpin_work *work;
9934         struct intel_engine_cs *ring;
9935         unsigned long flags;
9936         int ret;
9937
9938         /*
9939          * drm_mode_page_flip_ioctl() should already catch this, but double
9940          * check to be safe.  In the future we may enable pageflipping from
9941          * a disabled primary plane.
9942          */
9943         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9944                 return -EBUSY;
9945
9946         /* Can't change pixel format via MI display flips. */
9947         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9948                 return -EINVAL;
9949
9950         /*
9951          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9952          * Note that pitch changes could also affect these register.
9953          */
9954         if (INTEL_INFO(dev)->gen > 3 &&
9955             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9956              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9957                 return -EINVAL;
9958
9959         if (i915_terminally_wedged(&dev_priv->gpu_error))
9960                 goto out_hang;
9961
9962         work = kzalloc(sizeof(*work), GFP_KERNEL);
9963         if (work == NULL)
9964                 return -ENOMEM;
9965
9966         work->event = event;
9967         work->crtc = crtc;
9968         work->old_fb_obj = intel_fb_obj(old_fb);
9969         INIT_WORK(&work->work, intel_unpin_work_fn);
9970
9971         ret = drm_crtc_vblank_get(crtc);
9972         if (ret)
9973                 goto free_work;
9974
9975         /* We borrow the event spin lock for protecting unpin_work */
9976         spin_lock_irqsave(&dev->event_lock, flags);
9977         if (intel_crtc->unpin_work) {
9978                 /* Before declaring the flip queue wedged, check if
9979                  * the hardware completed the operation behind our backs.
9980                  */
9981                 if (__intel_pageflip_stall_check(dev, crtc)) {
9982                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9983                         page_flip_completed(intel_crtc);
9984                 } else {
9985                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9986                         spin_unlock_irqrestore(&dev->event_lock, flags);
9987
9988                         drm_crtc_vblank_put(crtc);
9989                         kfree(work);
9990                         return -EBUSY;
9991                 }
9992         }
9993         intel_crtc->unpin_work = work;
9994         spin_unlock_irqrestore(&dev->event_lock, flags);
9995
9996         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9997                 flush_workqueue(dev_priv->wq);
9998
9999         ret = i915_mutex_lock_interruptible(dev);
10000         if (ret)
10001                 goto cleanup;
10002
10003         /* Reference the objects for the scheduled work. */
10004         drm_gem_object_reference(&work->old_fb_obj->base);
10005         drm_gem_object_reference(&obj->base);
10006
10007         crtc->primary->fb = fb;
10008
10009         work->pending_flip_obj = obj;
10010
10011         atomic_inc(&intel_crtc->unpin_work_count);
10012         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10013
10014         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10015                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10016
10017         if (IS_VALLEYVIEW(dev)) {
10018                 ring = &dev_priv->ring[BCS];
10019                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
10020                         /* vlv: DISPLAY_FLIP fails to change tiling */
10021                         ring = NULL;
10022         } else if (IS_IVYBRIDGE(dev)) {
10023                 ring = &dev_priv->ring[BCS];
10024         } else if (INTEL_INFO(dev)->gen >= 7) {
10025                 ring = obj->ring;
10026                 if (ring == NULL || ring->id != RCS)
10027                         ring = &dev_priv->ring[BCS];
10028         } else {
10029                 ring = &dev_priv->ring[RCS];
10030         }
10031
10032         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10033         if (ret)
10034                 goto cleanup_pending;
10035
10036         work->gtt_offset =
10037                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10038
10039         if (use_mmio_flip(ring, obj)) {
10040                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10041                                             page_flip_flags);
10042                 if (ret)
10043                         goto cleanup_unpin;
10044
10045                 work->flip_queued_seqno = obj->last_write_seqno;
10046                 work->flip_queued_ring = obj->ring;
10047         } else {
10048                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10049                                                    page_flip_flags);
10050                 if (ret)
10051                         goto cleanup_unpin;
10052
10053                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10054                 work->flip_queued_ring = ring;
10055         }
10056
10057         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10058         work->enable_stall_check = true;
10059
10060         i915_gem_track_fb(work->old_fb_obj, obj,
10061                           INTEL_FRONTBUFFER_PRIMARY(pipe));
10062
10063         intel_disable_fbc(dev);
10064         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10065         mutex_unlock(&dev->struct_mutex);
10066
10067         trace_i915_flip_request(intel_crtc->plane, obj);
10068
10069         return 0;
10070
10071 cleanup_unpin:
10072         intel_unpin_fb_obj(obj);
10073 cleanup_pending:
10074         atomic_dec(&intel_crtc->unpin_work_count);
10075         crtc->primary->fb = old_fb;
10076         drm_gem_object_unreference(&work->old_fb_obj->base);
10077         drm_gem_object_unreference(&obj->base);
10078         mutex_unlock(&dev->struct_mutex);
10079
10080 cleanup:
10081         spin_lock_irqsave(&dev->event_lock, flags);
10082         intel_crtc->unpin_work = NULL;
10083         spin_unlock_irqrestore(&dev->event_lock, flags);
10084
10085         drm_crtc_vblank_put(crtc);
10086 free_work:
10087         kfree(work);
10088
10089         if (ret == -EIO) {
10090 out_hang:
10091                 intel_crtc_wait_for_pending_flips(crtc);
10092                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10093                 if (ret == 0 && event) {
10094                         spin_lock_irqsave(&dev->event_lock, flags);
10095                         drm_send_vblank_event(dev, pipe, event);
10096                         spin_unlock_irqrestore(&dev->event_lock, flags);
10097                 }
10098         }
10099         return ret;
10100 }
10101
10102 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10103         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10104         .load_lut = intel_crtc_load_lut,
10105 };
10106
10107 /**
10108  * intel_modeset_update_staged_output_state
10109  *
10110  * Updates the staged output configuration state, e.g. after we've read out the
10111  * current hw state.
10112  */
10113 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10114 {
10115         struct intel_crtc *crtc;
10116         struct intel_encoder *encoder;
10117         struct intel_connector *connector;
10118
10119         list_for_each_entry(connector, &dev->mode_config.connector_list,
10120                             base.head) {
10121                 connector->new_encoder =
10122                         to_intel_encoder(connector->base.encoder);
10123         }
10124
10125         for_each_intel_encoder(dev, encoder) {
10126                 encoder->new_crtc =
10127                         to_intel_crtc(encoder->base.crtc);
10128         }
10129
10130         for_each_intel_crtc(dev, crtc) {
10131                 crtc->new_enabled = crtc->base.enabled;
10132
10133                 if (crtc->new_enabled)
10134                         crtc->new_config = &crtc->config;
10135                 else
10136                         crtc->new_config = NULL;
10137         }
10138 }
10139
10140 /**
10141  * intel_modeset_commit_output_state
10142  *
10143  * This function copies the stage display pipe configuration to the real one.
10144  */
10145 static void intel_modeset_commit_output_state(struct drm_device *dev)
10146 {
10147         struct intel_crtc *crtc;
10148         struct intel_encoder *encoder;
10149         struct intel_connector *connector;
10150
10151         list_for_each_entry(connector, &dev->mode_config.connector_list,
10152                             base.head) {
10153                 connector->base.encoder = &connector->new_encoder->base;
10154         }
10155
10156         for_each_intel_encoder(dev, encoder) {
10157                 encoder->base.crtc = &encoder->new_crtc->base;
10158         }
10159
10160         for_each_intel_crtc(dev, crtc) {
10161                 crtc->base.enabled = crtc->new_enabled;
10162         }
10163 }
10164
10165 static void
10166 connected_sink_compute_bpp(struct intel_connector *connector,
10167                            struct intel_crtc_config *pipe_config)
10168 {
10169         int bpp = pipe_config->pipe_bpp;
10170
10171         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10172                 connector->base.base.id,
10173                 connector->base.name);
10174
10175         /* Don't use an invalid EDID bpc value */
10176         if (connector->base.display_info.bpc &&
10177             connector->base.display_info.bpc * 3 < bpp) {
10178                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10179                               bpp, connector->base.display_info.bpc*3);
10180                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10181         }
10182
10183         /* Clamp bpp to 8 on screens without EDID 1.4 */
10184         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10185                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10186                               bpp);
10187                 pipe_config->pipe_bpp = 24;
10188         }
10189 }
10190
10191 static int
10192 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10193                           struct drm_framebuffer *fb,
10194                           struct intel_crtc_config *pipe_config)
10195 {
10196         struct drm_device *dev = crtc->base.dev;
10197         struct intel_connector *connector;
10198         int bpp;
10199
10200         switch (fb->pixel_format) {
10201         case DRM_FORMAT_C8:
10202                 bpp = 8*3; /* since we go through a colormap */
10203                 break;
10204         case DRM_FORMAT_XRGB1555:
10205         case DRM_FORMAT_ARGB1555:
10206                 /* checked in intel_framebuffer_init already */
10207                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10208                         return -EINVAL;
10209         case DRM_FORMAT_RGB565:
10210                 bpp = 6*3; /* min is 18bpp */
10211                 break;
10212         case DRM_FORMAT_XBGR8888:
10213         case DRM_FORMAT_ABGR8888:
10214                 /* checked in intel_framebuffer_init already */
10215                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10216                         return -EINVAL;
10217         case DRM_FORMAT_XRGB8888:
10218         case DRM_FORMAT_ARGB8888:
10219                 bpp = 8*3;
10220                 break;
10221         case DRM_FORMAT_XRGB2101010:
10222         case DRM_FORMAT_ARGB2101010:
10223         case DRM_FORMAT_XBGR2101010:
10224         case DRM_FORMAT_ABGR2101010:
10225                 /* checked in intel_framebuffer_init already */
10226                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10227                         return -EINVAL;
10228                 bpp = 10*3;
10229                 break;
10230         /* TODO: gen4+ supports 16 bpc floating point, too. */
10231         default:
10232                 DRM_DEBUG_KMS("unsupported depth\n");
10233                 return -EINVAL;
10234         }
10235
10236         pipe_config->pipe_bpp = bpp;
10237
10238         /* Clamp display bpp to EDID value */
10239         list_for_each_entry(connector, &dev->mode_config.connector_list,
10240                             base.head) {
10241                 if (!connector->new_encoder ||
10242                     connector->new_encoder->new_crtc != crtc)
10243                         continue;
10244
10245                 connected_sink_compute_bpp(connector, pipe_config);
10246         }
10247
10248         return bpp;
10249 }
10250
10251 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10252 {
10253         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10254                         "type: 0x%x flags: 0x%x\n",
10255                 mode->crtc_clock,
10256                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10257                 mode->crtc_hsync_end, mode->crtc_htotal,
10258                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10259                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10260 }
10261
10262 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10263                                    struct intel_crtc_config *pipe_config,
10264                                    const char *context)
10265 {
10266         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10267                       context, pipe_name(crtc->pipe));
10268
10269         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10270         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10271                       pipe_config->pipe_bpp, pipe_config->dither);
10272         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10273                       pipe_config->has_pch_encoder,
10274                       pipe_config->fdi_lanes,
10275                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10276                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10277                       pipe_config->fdi_m_n.tu);
10278         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10279                       pipe_config->has_dp_encoder,
10280                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10281                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10282                       pipe_config->dp_m_n.tu);
10283
10284         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10285                       pipe_config->has_dp_encoder,
10286                       pipe_config->dp_m2_n2.gmch_m,
10287                       pipe_config->dp_m2_n2.gmch_n,
10288                       pipe_config->dp_m2_n2.link_m,
10289                       pipe_config->dp_m2_n2.link_n,
10290                       pipe_config->dp_m2_n2.tu);
10291
10292         DRM_DEBUG_KMS("requested mode:\n");
10293         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10294         DRM_DEBUG_KMS("adjusted mode:\n");
10295         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10296         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10297         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10298         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10299                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10300         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10301                       pipe_config->gmch_pfit.control,
10302                       pipe_config->gmch_pfit.pgm_ratios,
10303                       pipe_config->gmch_pfit.lvds_border_bits);
10304         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10305                       pipe_config->pch_pfit.pos,
10306                       pipe_config->pch_pfit.size,
10307                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10308         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10309         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10310 }
10311
10312 static bool encoders_cloneable(const struct intel_encoder *a,
10313                                const struct intel_encoder *b)
10314 {
10315         /* masks could be asymmetric, so check both ways */
10316         return a == b || (a->cloneable & (1 << b->type) &&
10317                           b->cloneable & (1 << a->type));
10318 }
10319
10320 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10321                                          struct intel_encoder *encoder)
10322 {
10323         struct drm_device *dev = crtc->base.dev;
10324         struct intel_encoder *source_encoder;
10325
10326         for_each_intel_encoder(dev, source_encoder) {
10327                 if (source_encoder->new_crtc != crtc)
10328                         continue;
10329
10330                 if (!encoders_cloneable(encoder, source_encoder))
10331                         return false;
10332         }
10333
10334         return true;
10335 }
10336
10337 static bool check_encoder_cloning(struct intel_crtc *crtc)
10338 {
10339         struct drm_device *dev = crtc->base.dev;
10340         struct intel_encoder *encoder;
10341
10342         for_each_intel_encoder(dev, encoder) {
10343                 if (encoder->new_crtc != crtc)
10344                         continue;
10345
10346                 if (!check_single_encoder_cloning(crtc, encoder))
10347                         return false;
10348         }
10349
10350         return true;
10351 }
10352
10353 static struct intel_crtc_config *
10354 intel_modeset_pipe_config(struct drm_crtc *crtc,
10355                           struct drm_framebuffer *fb,
10356                           struct drm_display_mode *mode)
10357 {
10358         struct drm_device *dev = crtc->dev;
10359         struct intel_encoder *encoder;
10360         struct intel_crtc_config *pipe_config;
10361         int plane_bpp, ret = -EINVAL;
10362         bool retry = true;
10363
10364         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10365                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10366                 return ERR_PTR(-EINVAL);
10367         }
10368
10369         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10370         if (!pipe_config)
10371                 return ERR_PTR(-ENOMEM);
10372
10373         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10374         drm_mode_copy(&pipe_config->requested_mode, mode);
10375
10376         pipe_config->cpu_transcoder =
10377                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10378         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10379
10380         /*
10381          * Sanitize sync polarity flags based on requested ones. If neither
10382          * positive or negative polarity is requested, treat this as meaning
10383          * negative polarity.
10384          */
10385         if (!(pipe_config->adjusted_mode.flags &
10386               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10387                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10388
10389         if (!(pipe_config->adjusted_mode.flags &
10390               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10391                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10392
10393         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10394          * plane pixel format and any sink constraints into account. Returns the
10395          * source plane bpp so that dithering can be selected on mismatches
10396          * after encoders and crtc also have had their say. */
10397         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10398                                               fb, pipe_config);
10399         if (plane_bpp < 0)
10400                 goto fail;
10401
10402         /*
10403          * Determine the real pipe dimensions. Note that stereo modes can
10404          * increase the actual pipe size due to the frame doubling and
10405          * insertion of additional space for blanks between the frame. This
10406          * is stored in the crtc timings. We use the requested mode to do this
10407          * computation to clearly distinguish it from the adjusted mode, which
10408          * can be changed by the connectors in the below retry loop.
10409          */
10410         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10411         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10412         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10413
10414 encoder_retry:
10415         /* Ensure the port clock defaults are reset when retrying. */
10416         pipe_config->port_clock = 0;
10417         pipe_config->pixel_multiplier = 1;
10418
10419         /* Fill in default crtc timings, allow encoders to overwrite them. */
10420         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10421
10422         /* Pass our mode to the connectors and the CRTC to give them a chance to
10423          * adjust it according to limitations or connector properties, and also
10424          * a chance to reject the mode entirely.
10425          */
10426         for_each_intel_encoder(dev, encoder) {
10427
10428                 if (&encoder->new_crtc->base != crtc)
10429                         continue;
10430
10431                 if (!(encoder->compute_config(encoder, pipe_config))) {
10432                         DRM_DEBUG_KMS("Encoder config failure\n");
10433                         goto fail;
10434                 }
10435         }
10436
10437         /* Set default port clock if not overwritten by the encoder. Needs to be
10438          * done afterwards in case the encoder adjusts the mode. */
10439         if (!pipe_config->port_clock)
10440                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10441                         * pipe_config->pixel_multiplier;
10442
10443         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10444         if (ret < 0) {
10445                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10446                 goto fail;
10447         }
10448
10449         if (ret == RETRY) {
10450                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10451                         ret = -EINVAL;
10452                         goto fail;
10453                 }
10454
10455                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10456                 retry = false;
10457                 goto encoder_retry;
10458         }
10459
10460         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10461         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10462                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10463
10464         return pipe_config;
10465 fail:
10466         kfree(pipe_config);
10467         return ERR_PTR(ret);
10468 }
10469
10470 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10471  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10472 static void
10473 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10474                              unsigned *prepare_pipes, unsigned *disable_pipes)
10475 {
10476         struct intel_crtc *intel_crtc;
10477         struct drm_device *dev = crtc->dev;
10478         struct intel_encoder *encoder;
10479         struct intel_connector *connector;
10480         struct drm_crtc *tmp_crtc;
10481
10482         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10483
10484         /* Check which crtcs have changed outputs connected to them, these need
10485          * to be part of the prepare_pipes mask. We don't (yet) support global
10486          * modeset across multiple crtcs, so modeset_pipes will only have one
10487          * bit set at most. */
10488         list_for_each_entry(connector, &dev->mode_config.connector_list,
10489                             base.head) {
10490                 if (connector->base.encoder == &connector->new_encoder->base)
10491                         continue;
10492
10493                 if (connector->base.encoder) {
10494                         tmp_crtc = connector->base.encoder->crtc;
10495
10496                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10497                 }
10498
10499                 if (connector->new_encoder)
10500                         *prepare_pipes |=
10501                                 1 << connector->new_encoder->new_crtc->pipe;
10502         }
10503
10504         for_each_intel_encoder(dev, encoder) {
10505                 if (encoder->base.crtc == &encoder->new_crtc->base)
10506                         continue;
10507
10508                 if (encoder->base.crtc) {
10509                         tmp_crtc = encoder->base.crtc;
10510
10511                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10512                 }
10513
10514                 if (encoder->new_crtc)
10515                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10516         }
10517
10518         /* Check for pipes that will be enabled/disabled ... */
10519         for_each_intel_crtc(dev, intel_crtc) {
10520                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10521                         continue;
10522
10523                 if (!intel_crtc->new_enabled)
10524                         *disable_pipes |= 1 << intel_crtc->pipe;
10525                 else
10526                         *prepare_pipes |= 1 << intel_crtc->pipe;
10527         }
10528
10529
10530         /* set_mode is also used to update properties on life display pipes. */
10531         intel_crtc = to_intel_crtc(crtc);
10532         if (intel_crtc->new_enabled)
10533                 *prepare_pipes |= 1 << intel_crtc->pipe;
10534
10535         /*
10536          * For simplicity do a full modeset on any pipe where the output routing
10537          * changed. We could be more clever, but that would require us to be
10538          * more careful with calling the relevant encoder->mode_set functions.
10539          */
10540         if (*prepare_pipes)
10541                 *modeset_pipes = *prepare_pipes;
10542
10543         /* ... and mask these out. */
10544         *modeset_pipes &= ~(*disable_pipes);
10545         *prepare_pipes &= ~(*disable_pipes);
10546
10547         /*
10548          * HACK: We don't (yet) fully support global modesets. intel_set_config
10549          * obies this rule, but the modeset restore mode of
10550          * intel_modeset_setup_hw_state does not.
10551          */
10552         *modeset_pipes &= 1 << intel_crtc->pipe;
10553         *prepare_pipes &= 1 << intel_crtc->pipe;
10554
10555         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10556                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10557 }
10558
10559 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10560 {
10561         struct drm_encoder *encoder;
10562         struct drm_device *dev = crtc->dev;
10563
10564         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10565                 if (encoder->crtc == crtc)
10566                         return true;
10567
10568         return false;
10569 }
10570
10571 static void
10572 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10573 {
10574         struct intel_encoder *intel_encoder;
10575         struct intel_crtc *intel_crtc;
10576         struct drm_connector *connector;
10577
10578         for_each_intel_encoder(dev, intel_encoder) {
10579                 if (!intel_encoder->base.crtc)
10580                         continue;
10581
10582                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10583
10584                 if (prepare_pipes & (1 << intel_crtc->pipe))
10585                         intel_encoder->connectors_active = false;
10586         }
10587
10588         intel_modeset_commit_output_state(dev);
10589
10590         /* Double check state. */
10591         for_each_intel_crtc(dev, intel_crtc) {
10592                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10593                 WARN_ON(intel_crtc->new_config &&
10594                         intel_crtc->new_config != &intel_crtc->config);
10595                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10596         }
10597
10598         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10599                 if (!connector->encoder || !connector->encoder->crtc)
10600                         continue;
10601
10602                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10603
10604                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10605                         struct drm_property *dpms_property =
10606                                 dev->mode_config.dpms_property;
10607
10608                         connector->dpms = DRM_MODE_DPMS_ON;
10609                         drm_object_property_set_value(&connector->base,
10610                                                          dpms_property,
10611                                                          DRM_MODE_DPMS_ON);
10612
10613                         intel_encoder = to_intel_encoder(connector->encoder);
10614                         intel_encoder->connectors_active = true;
10615                 }
10616         }
10617
10618 }
10619
10620 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10621 {
10622         int diff;
10623
10624         if (clock1 == clock2)
10625                 return true;
10626
10627         if (!clock1 || !clock2)
10628                 return false;
10629
10630         diff = abs(clock1 - clock2);
10631
10632         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10633                 return true;
10634
10635         return false;
10636 }
10637
10638 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10639         list_for_each_entry((intel_crtc), \
10640                             &(dev)->mode_config.crtc_list, \
10641                             base.head) \
10642                 if (mask & (1 <<(intel_crtc)->pipe))
10643
10644 static bool
10645 intel_pipe_config_compare(struct drm_device *dev,
10646                           struct intel_crtc_config *current_config,
10647                           struct intel_crtc_config *pipe_config)
10648 {
10649 #define PIPE_CONF_CHECK_X(name) \
10650         if (current_config->name != pipe_config->name) { \
10651                 DRM_ERROR("mismatch in " #name " " \
10652                           "(expected 0x%08x, found 0x%08x)\n", \
10653                           current_config->name, \
10654                           pipe_config->name); \
10655                 return false; \
10656         }
10657
10658 #define PIPE_CONF_CHECK_I(name) \
10659         if (current_config->name != pipe_config->name) { \
10660                 DRM_ERROR("mismatch in " #name " " \
10661                           "(expected %i, found %i)\n", \
10662                           current_config->name, \
10663                           pipe_config->name); \
10664                 return false; \
10665         }
10666
10667 /* This is required for BDW+ where there is only one set of registers for
10668  * switching between high and low RR.
10669  * This macro can be used whenever a comparison has to be made between one
10670  * hw state and multiple sw state variables.
10671  */
10672 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10673         if ((current_config->name != pipe_config->name) && \
10674                 (current_config->alt_name != pipe_config->name)) { \
10675                         DRM_ERROR("mismatch in " #name " " \
10676                                   "(expected %i or %i, found %i)\n", \
10677                                   current_config->name, \
10678                                   current_config->alt_name, \
10679                                   pipe_config->name); \
10680                         return false; \
10681         }
10682
10683 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10684         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10685                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10686                           "(expected %i, found %i)\n", \
10687                           current_config->name & (mask), \
10688                           pipe_config->name & (mask)); \
10689                 return false; \
10690         }
10691
10692 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10693         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10694                 DRM_ERROR("mismatch in " #name " " \
10695                           "(expected %i, found %i)\n", \
10696                           current_config->name, \
10697                           pipe_config->name); \
10698                 return false; \
10699         }
10700
10701 #define PIPE_CONF_QUIRK(quirk)  \
10702         ((current_config->quirks | pipe_config->quirks) & (quirk))
10703
10704         PIPE_CONF_CHECK_I(cpu_transcoder);
10705
10706         PIPE_CONF_CHECK_I(has_pch_encoder);
10707         PIPE_CONF_CHECK_I(fdi_lanes);
10708         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10709         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10710         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10711         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10712         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10713
10714         PIPE_CONF_CHECK_I(has_dp_encoder);
10715
10716         if (INTEL_INFO(dev)->gen < 8) {
10717                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10718                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10719                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10720                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10721                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10722
10723                 if (current_config->has_drrs) {
10724                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10725                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10726                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10727                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10728                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10729                 }
10730         } else {
10731                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10732                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10733                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10734                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10735                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10736         }
10737
10738         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10739         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10740         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10741         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10742         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10743         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10744
10745         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10746         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10747         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10748         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10749         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10750         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10751
10752         PIPE_CONF_CHECK_I(pixel_multiplier);
10753         PIPE_CONF_CHECK_I(has_hdmi_sink);
10754         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10755             IS_VALLEYVIEW(dev))
10756                 PIPE_CONF_CHECK_I(limited_color_range);
10757
10758         PIPE_CONF_CHECK_I(has_audio);
10759
10760         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10761                               DRM_MODE_FLAG_INTERLACE);
10762
10763         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10764                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10765                                       DRM_MODE_FLAG_PHSYNC);
10766                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10767                                       DRM_MODE_FLAG_NHSYNC);
10768                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10769                                       DRM_MODE_FLAG_PVSYNC);
10770                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10771                                       DRM_MODE_FLAG_NVSYNC);
10772         }
10773
10774         PIPE_CONF_CHECK_I(pipe_src_w);
10775         PIPE_CONF_CHECK_I(pipe_src_h);
10776
10777         /*
10778          * FIXME: BIOS likes to set up a cloned config with lvds+external
10779          * screen. Since we don't yet re-compute the pipe config when moving
10780          * just the lvds port away to another pipe the sw tracking won't match.
10781          *
10782          * Proper atomic modesets with recomputed global state will fix this.
10783          * Until then just don't check gmch state for inherited modes.
10784          */
10785         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10786                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10787                 /* pfit ratios are autocomputed by the hw on gen4+ */
10788                 if (INTEL_INFO(dev)->gen < 4)
10789                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10790                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10791         }
10792
10793         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10794         if (current_config->pch_pfit.enabled) {
10795                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10796                 PIPE_CONF_CHECK_I(pch_pfit.size);
10797         }
10798
10799         /* BDW+ don't expose a synchronous way to read the state */
10800         if (IS_HASWELL(dev))
10801                 PIPE_CONF_CHECK_I(ips_enabled);
10802
10803         PIPE_CONF_CHECK_I(double_wide);
10804
10805         PIPE_CONF_CHECK_X(ddi_pll_sel);
10806
10807         PIPE_CONF_CHECK_I(shared_dpll);
10808         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10809         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10810         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10811         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10812         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10813
10814         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10815                 PIPE_CONF_CHECK_I(pipe_bpp);
10816
10817         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10818         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10819
10820 #undef PIPE_CONF_CHECK_X
10821 #undef PIPE_CONF_CHECK_I
10822 #undef PIPE_CONF_CHECK_I_ALT
10823 #undef PIPE_CONF_CHECK_FLAGS
10824 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10825 #undef PIPE_CONF_QUIRK
10826
10827         return true;
10828 }
10829
10830 static void
10831 check_connector_state(struct drm_device *dev)
10832 {
10833         struct intel_connector *connector;
10834
10835         list_for_each_entry(connector, &dev->mode_config.connector_list,
10836                             base.head) {
10837                 /* This also checks the encoder/connector hw state with the
10838                  * ->get_hw_state callbacks. */
10839                 intel_connector_check_state(connector);
10840
10841                 WARN(&connector->new_encoder->base != connector->base.encoder,
10842                      "connector's staged encoder doesn't match current encoder\n");
10843         }
10844 }
10845
10846 static void
10847 check_encoder_state(struct drm_device *dev)
10848 {
10849         struct intel_encoder *encoder;
10850         struct intel_connector *connector;
10851
10852         for_each_intel_encoder(dev, encoder) {
10853                 bool enabled = false;
10854                 bool active = false;
10855                 enum pipe pipe, tracked_pipe;
10856
10857                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10858                               encoder->base.base.id,
10859                               encoder->base.name);
10860
10861                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10862                      "encoder's stage crtc doesn't match current crtc\n");
10863                 WARN(encoder->connectors_active && !encoder->base.crtc,
10864                      "encoder's active_connectors set, but no crtc\n");
10865
10866                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10867                                     base.head) {
10868                         if (connector->base.encoder != &encoder->base)
10869                                 continue;
10870                         enabled = true;
10871                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10872                                 active = true;
10873                 }
10874                 /*
10875                  * for MST connectors if we unplug the connector is gone
10876                  * away but the encoder is still connected to a crtc
10877                  * until a modeset happens in response to the hotplug.
10878                  */
10879                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10880                         continue;
10881
10882                 WARN(!!encoder->base.crtc != enabled,
10883                      "encoder's enabled state mismatch "
10884                      "(expected %i, found %i)\n",
10885                      !!encoder->base.crtc, enabled);
10886                 WARN(active && !encoder->base.crtc,
10887                      "active encoder with no crtc\n");
10888
10889                 WARN(encoder->connectors_active != active,
10890                      "encoder's computed active state doesn't match tracked active state "
10891                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10892
10893                 active = encoder->get_hw_state(encoder, &pipe);
10894                 WARN(active != encoder->connectors_active,
10895                      "encoder's hw state doesn't match sw tracking "
10896                      "(expected %i, found %i)\n",
10897                      encoder->connectors_active, active);
10898
10899                 if (!encoder->base.crtc)
10900                         continue;
10901
10902                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10903                 WARN(active && pipe != tracked_pipe,
10904                      "active encoder's pipe doesn't match"
10905                      "(expected %i, found %i)\n",
10906                      tracked_pipe, pipe);
10907
10908         }
10909 }
10910
10911 static void
10912 check_crtc_state(struct drm_device *dev)
10913 {
10914         struct drm_i915_private *dev_priv = dev->dev_private;
10915         struct intel_crtc *crtc;
10916         struct intel_encoder *encoder;
10917         struct intel_crtc_config pipe_config;
10918
10919         for_each_intel_crtc(dev, crtc) {
10920                 bool enabled = false;
10921                 bool active = false;
10922
10923                 memset(&pipe_config, 0, sizeof(pipe_config));
10924
10925                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10926                               crtc->base.base.id);
10927
10928                 WARN(crtc->active && !crtc->base.enabled,
10929                      "active crtc, but not enabled in sw tracking\n");
10930
10931                 for_each_intel_encoder(dev, encoder) {
10932                         if (encoder->base.crtc != &crtc->base)
10933                                 continue;
10934                         enabled = true;
10935                         if (encoder->connectors_active)
10936                                 active = true;
10937                 }
10938
10939                 WARN(active != crtc->active,
10940                      "crtc's computed active state doesn't match tracked active state "
10941                      "(expected %i, found %i)\n", active, crtc->active);
10942                 WARN(enabled != crtc->base.enabled,
10943                      "crtc's computed enabled state doesn't match tracked enabled state "
10944                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10945
10946                 active = dev_priv->display.get_pipe_config(crtc,
10947                                                            &pipe_config);
10948
10949                 /* hw state is inconsistent with the pipe quirk */
10950                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10951                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10952                         active = crtc->active;
10953
10954                 for_each_intel_encoder(dev, encoder) {
10955                         enum pipe pipe;
10956                         if (encoder->base.crtc != &crtc->base)
10957                                 continue;
10958                         if (encoder->get_hw_state(encoder, &pipe))
10959                                 encoder->get_config(encoder, &pipe_config);
10960                 }
10961
10962                 WARN(crtc->active != active,
10963                      "crtc active state doesn't match with hw state "
10964                      "(expected %i, found %i)\n", crtc->active, active);
10965
10966                 if (active &&
10967                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10968                         WARN(1, "pipe state doesn't match!\n");
10969                         intel_dump_pipe_config(crtc, &pipe_config,
10970                                                "[hw state]");
10971                         intel_dump_pipe_config(crtc, &crtc->config,
10972                                                "[sw state]");
10973                 }
10974         }
10975 }
10976
10977 static void
10978 check_shared_dpll_state(struct drm_device *dev)
10979 {
10980         struct drm_i915_private *dev_priv = dev->dev_private;
10981         struct intel_crtc *crtc;
10982         struct intel_dpll_hw_state dpll_hw_state;
10983         int i;
10984
10985         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10986                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10987                 int enabled_crtcs = 0, active_crtcs = 0;
10988                 bool active;
10989
10990                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10991
10992                 DRM_DEBUG_KMS("%s\n", pll->name);
10993
10994                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10995
10996                 WARN(pll->active > pll->refcount,
10997                      "more active pll users than references: %i vs %i\n",
10998                      pll->active, pll->refcount);
10999                 WARN(pll->active && !pll->on,
11000                      "pll in active use but not on in sw tracking\n");
11001                 WARN(pll->on && !pll->active,
11002                      "pll in on but not on in use in sw tracking\n");
11003                 WARN(pll->on != active,
11004                      "pll on state mismatch (expected %i, found %i)\n",
11005                      pll->on, active);
11006
11007                 for_each_intel_crtc(dev, crtc) {
11008                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
11009                                 enabled_crtcs++;
11010                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11011                                 active_crtcs++;
11012                 }
11013                 WARN(pll->active != active_crtcs,
11014                      "pll active crtcs mismatch (expected %i, found %i)\n",
11015                      pll->active, active_crtcs);
11016                 WARN(pll->refcount != enabled_crtcs,
11017                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
11018                      pll->refcount, enabled_crtcs);
11019
11020                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
11021                                        sizeof(dpll_hw_state)),
11022                      "pll hw state mismatch\n");
11023         }
11024 }
11025
11026 void
11027 intel_modeset_check_state(struct drm_device *dev)
11028 {
11029         check_connector_state(dev);
11030         check_encoder_state(dev);
11031         check_crtc_state(dev);
11032         check_shared_dpll_state(dev);
11033 }
11034
11035 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11036                                      int dotclock)
11037 {
11038         /*
11039          * FDI already provided one idea for the dotclock.
11040          * Yell if the encoder disagrees.
11041          */
11042         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11043              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11044              pipe_config->adjusted_mode.crtc_clock, dotclock);
11045 }
11046
11047 static void update_scanline_offset(struct intel_crtc *crtc)
11048 {
11049         struct drm_device *dev = crtc->base.dev;
11050
11051         /*
11052          * The scanline counter increments at the leading edge of hsync.
11053          *
11054          * On most platforms it starts counting from vtotal-1 on the
11055          * first active line. That means the scanline counter value is
11056          * always one less than what we would expect. Ie. just after
11057          * start of vblank, which also occurs at start of hsync (on the
11058          * last active line), the scanline counter will read vblank_start-1.
11059          *
11060          * On gen2 the scanline counter starts counting from 1 instead
11061          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11062          * to keep the value positive), instead of adding one.
11063          *
11064          * On HSW+ the behaviour of the scanline counter depends on the output
11065          * type. For DP ports it behaves like most other platforms, but on HDMI
11066          * there's an extra 1 line difference. So we need to add two instead of
11067          * one to the value.
11068          */
11069         if (IS_GEN2(dev)) {
11070                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11071                 int vtotal;
11072
11073                 vtotal = mode->crtc_vtotal;
11074                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11075                         vtotal /= 2;
11076
11077                 crtc->scanline_offset = vtotal - 1;
11078         } else if (HAS_DDI(dev) &&
11079                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11080                 crtc->scanline_offset = 2;
11081         } else
11082                 crtc->scanline_offset = 1;
11083 }
11084
11085 static int __intel_set_mode(struct drm_crtc *crtc,
11086                             struct drm_display_mode *mode,
11087                             int x, int y, struct drm_framebuffer *fb)
11088 {
11089         struct drm_device *dev = crtc->dev;
11090         struct drm_i915_private *dev_priv = dev->dev_private;
11091         struct drm_display_mode *saved_mode;
11092         struct intel_crtc_config *pipe_config = NULL;
11093         struct intel_crtc *intel_crtc;
11094         unsigned disable_pipes, prepare_pipes, modeset_pipes;
11095         int ret = 0;
11096
11097         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11098         if (!saved_mode)
11099                 return -ENOMEM;
11100
11101         intel_modeset_affected_pipes(crtc, &modeset_pipes,
11102                                      &prepare_pipes, &disable_pipes);
11103
11104         *saved_mode = crtc->mode;
11105
11106         /* Hack: Because we don't (yet) support global modeset on multiple
11107          * crtcs, we don't keep track of the new mode for more than one crtc.
11108          * Hence simply check whether any bit is set in modeset_pipes in all the
11109          * pieces of code that are not yet converted to deal with mutliple crtcs
11110          * changing their mode at the same time. */
11111         if (modeset_pipes) {
11112                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11113                 if (IS_ERR(pipe_config)) {
11114                         ret = PTR_ERR(pipe_config);
11115                         pipe_config = NULL;
11116
11117                         goto out;
11118                 }
11119                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11120                                        "[modeset]");
11121                 to_intel_crtc(crtc)->new_config = pipe_config;
11122         }
11123
11124         /*
11125          * See if the config requires any additional preparation, e.g.
11126          * to adjust global state with pipes off.  We need to do this
11127          * here so we can get the modeset_pipe updated config for the new
11128          * mode set on this crtc.  For other crtcs we need to use the
11129          * adjusted_mode bits in the crtc directly.
11130          */
11131         if (IS_VALLEYVIEW(dev)) {
11132                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11133
11134                 /* may have added more to prepare_pipes than we should */
11135                 prepare_pipes &= ~disable_pipes;
11136         }
11137
11138         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11139                 intel_crtc_disable(&intel_crtc->base);
11140
11141         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11142                 if (intel_crtc->base.enabled)
11143                         dev_priv->display.crtc_disable(&intel_crtc->base);
11144         }
11145
11146         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11147          * to set it here already despite that we pass it down the callchain.
11148          */
11149         if (modeset_pipes) {
11150                 crtc->mode = *mode;
11151                 /* mode_set/enable/disable functions rely on a correct pipe
11152                  * config. */
11153                 to_intel_crtc(crtc)->config = *pipe_config;
11154                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11155
11156                 /*
11157                  * Calculate and store various constants which
11158                  * are later needed by vblank and swap-completion
11159                  * timestamping. They are derived from true hwmode.
11160                  */
11161                 drm_calc_timestamping_constants(crtc,
11162                                                 &pipe_config->adjusted_mode);
11163         }
11164
11165         /* Only after disabling all output pipelines that will be changed can we
11166          * update the the output configuration. */
11167         intel_modeset_update_state(dev, prepare_pipes);
11168
11169         if (dev_priv->display.modeset_global_resources)
11170                 dev_priv->display.modeset_global_resources(dev);
11171
11172         /* Set up the DPLL and any encoders state that needs to adjust or depend
11173          * on the DPLL.
11174          */
11175         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11176                 struct drm_framebuffer *old_fb = crtc->primary->fb;
11177                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11178                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11179
11180                 mutex_lock(&dev->struct_mutex);
11181                 ret = intel_pin_and_fence_fb_obj(dev,
11182                                                  obj,
11183                                                  NULL);
11184                 if (ret != 0) {
11185                         DRM_ERROR("pin & fence failed\n");
11186                         mutex_unlock(&dev->struct_mutex);
11187                         goto done;
11188                 }
11189                 if (old_fb)
11190                         intel_unpin_fb_obj(old_obj);
11191                 i915_gem_track_fb(old_obj, obj,
11192                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11193                 mutex_unlock(&dev->struct_mutex);
11194
11195                 crtc->primary->fb = fb;
11196                 crtc->x = x;
11197                 crtc->y = y;
11198
11199                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11200                                                       x, y, fb);
11201                 if (ret)
11202                         goto done;
11203         }
11204
11205         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11206         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11207                 update_scanline_offset(intel_crtc);
11208
11209                 dev_priv->display.crtc_enable(&intel_crtc->base);
11210         }
11211
11212         /* FIXME: add subpixel order */
11213 done:
11214         if (ret && crtc->enabled)
11215                 crtc->mode = *saved_mode;
11216
11217 out:
11218         kfree(pipe_config);
11219         kfree(saved_mode);
11220         return ret;
11221 }
11222
11223 static int intel_set_mode(struct drm_crtc *crtc,
11224                           struct drm_display_mode *mode,
11225                           int x, int y, struct drm_framebuffer *fb)
11226 {
11227         int ret;
11228
11229         ret = __intel_set_mode(crtc, mode, x, y, fb);
11230
11231         if (ret == 0)
11232                 intel_modeset_check_state(crtc->dev);
11233
11234         return ret;
11235 }
11236
11237 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11238 {
11239         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11240 }
11241
11242 #undef for_each_intel_crtc_masked
11243
11244 static void intel_set_config_free(struct intel_set_config *config)
11245 {
11246         if (!config)
11247                 return;
11248
11249         kfree(config->save_connector_encoders);
11250         kfree(config->save_encoder_crtcs);
11251         kfree(config->save_crtc_enabled);
11252         kfree(config);
11253 }
11254
11255 static int intel_set_config_save_state(struct drm_device *dev,
11256                                        struct intel_set_config *config)
11257 {
11258         struct drm_crtc *crtc;
11259         struct drm_encoder *encoder;
11260         struct drm_connector *connector;
11261         int count;
11262
11263         config->save_crtc_enabled =
11264                 kcalloc(dev->mode_config.num_crtc,
11265                         sizeof(bool), GFP_KERNEL);
11266         if (!config->save_crtc_enabled)
11267                 return -ENOMEM;
11268
11269         config->save_encoder_crtcs =
11270                 kcalloc(dev->mode_config.num_encoder,
11271                         sizeof(struct drm_crtc *), GFP_KERNEL);
11272         if (!config->save_encoder_crtcs)
11273                 return -ENOMEM;
11274
11275         config->save_connector_encoders =
11276                 kcalloc(dev->mode_config.num_connector,
11277                         sizeof(struct drm_encoder *), GFP_KERNEL);
11278         if (!config->save_connector_encoders)
11279                 return -ENOMEM;
11280
11281         /* Copy data. Note that driver private data is not affected.
11282          * Should anything bad happen only the expected state is
11283          * restored, not the drivers personal bookkeeping.
11284          */
11285         count = 0;
11286         for_each_crtc(dev, crtc) {
11287                 config->save_crtc_enabled[count++] = crtc->enabled;
11288         }
11289
11290         count = 0;
11291         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11292                 config->save_encoder_crtcs[count++] = encoder->crtc;
11293         }
11294
11295         count = 0;
11296         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11297                 config->save_connector_encoders[count++] = connector->encoder;
11298         }
11299
11300         return 0;
11301 }
11302
11303 static void intel_set_config_restore_state(struct drm_device *dev,
11304                                            struct intel_set_config *config)
11305 {
11306         struct intel_crtc *crtc;
11307         struct intel_encoder *encoder;
11308         struct intel_connector *connector;
11309         int count;
11310
11311         count = 0;
11312         for_each_intel_crtc(dev, crtc) {
11313                 crtc->new_enabled = config->save_crtc_enabled[count++];
11314
11315                 if (crtc->new_enabled)
11316                         crtc->new_config = &crtc->config;
11317                 else
11318                         crtc->new_config = NULL;
11319         }
11320
11321         count = 0;
11322         for_each_intel_encoder(dev, encoder) {
11323                 encoder->new_crtc =
11324                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11325         }
11326
11327         count = 0;
11328         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11329                 connector->new_encoder =
11330                         to_intel_encoder(config->save_connector_encoders[count++]);
11331         }
11332 }
11333
11334 static bool
11335 is_crtc_connector_off(struct drm_mode_set *set)
11336 {
11337         int i;
11338
11339         if (set->num_connectors == 0)
11340                 return false;
11341
11342         if (WARN_ON(set->connectors == NULL))
11343                 return false;
11344
11345         for (i = 0; i < set->num_connectors; i++)
11346                 if (set->connectors[i]->encoder &&
11347                     set->connectors[i]->encoder->crtc == set->crtc &&
11348                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11349                         return true;
11350
11351         return false;
11352 }
11353
11354 static void
11355 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11356                                       struct intel_set_config *config)
11357 {
11358
11359         /* We should be able to check here if the fb has the same properties
11360          * and then just flip_or_move it */
11361         if (is_crtc_connector_off(set)) {
11362                 config->mode_changed = true;
11363         } else if (set->crtc->primary->fb != set->fb) {
11364                 /*
11365                  * If we have no fb, we can only flip as long as the crtc is
11366                  * active, otherwise we need a full mode set.  The crtc may
11367                  * be active if we've only disabled the primary plane, or
11368                  * in fastboot situations.
11369                  */
11370                 if (set->crtc->primary->fb == NULL) {
11371                         struct intel_crtc *intel_crtc =
11372                                 to_intel_crtc(set->crtc);
11373
11374                         if (intel_crtc->active) {
11375                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11376                                 config->fb_changed = true;
11377                         } else {
11378                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11379                                 config->mode_changed = true;
11380                         }
11381                 } else if (set->fb == NULL) {
11382                         config->mode_changed = true;
11383                 } else if (set->fb->pixel_format !=
11384                            set->crtc->primary->fb->pixel_format) {
11385                         config->mode_changed = true;
11386                 } else {
11387                         config->fb_changed = true;
11388                 }
11389         }
11390
11391         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11392                 config->fb_changed = true;
11393
11394         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11395                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11396                 drm_mode_debug_printmodeline(&set->crtc->mode);
11397                 drm_mode_debug_printmodeline(set->mode);
11398                 config->mode_changed = true;
11399         }
11400
11401         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11402                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11403 }
11404
11405 static int
11406 intel_modeset_stage_output_state(struct drm_device *dev,
11407                                  struct drm_mode_set *set,
11408                                  struct intel_set_config *config)
11409 {
11410         struct intel_connector *connector;
11411         struct intel_encoder *encoder;
11412         struct intel_crtc *crtc;
11413         int ro;
11414
11415         /* The upper layers ensure that we either disable a crtc or have a list
11416          * of connectors. For paranoia, double-check this. */
11417         WARN_ON(!set->fb && (set->num_connectors != 0));
11418         WARN_ON(set->fb && (set->num_connectors == 0));
11419
11420         list_for_each_entry(connector, &dev->mode_config.connector_list,
11421                             base.head) {
11422                 /* Otherwise traverse passed in connector list and get encoders
11423                  * for them. */
11424                 for (ro = 0; ro < set->num_connectors; ro++) {
11425                         if (set->connectors[ro] == &connector->base) {
11426                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11427                                 break;
11428                         }
11429                 }
11430
11431                 /* If we disable the crtc, disable all its connectors. Also, if
11432                  * the connector is on the changing crtc but not on the new
11433                  * connector list, disable it. */
11434                 if ((!set->fb || ro == set->num_connectors) &&
11435                     connector->base.encoder &&
11436                     connector->base.encoder->crtc == set->crtc) {
11437                         connector->new_encoder = NULL;
11438
11439                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11440                                 connector->base.base.id,
11441                                 connector->base.name);
11442                 }
11443
11444
11445                 if (&connector->new_encoder->base != connector->base.encoder) {
11446                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11447                         config->mode_changed = true;
11448                 }
11449         }
11450         /* connector->new_encoder is now updated for all connectors. */
11451
11452         /* Update crtc of enabled connectors. */
11453         list_for_each_entry(connector, &dev->mode_config.connector_list,
11454                             base.head) {
11455                 struct drm_crtc *new_crtc;
11456
11457                 if (!connector->new_encoder)
11458                         continue;
11459
11460                 new_crtc = connector->new_encoder->base.crtc;
11461
11462                 for (ro = 0; ro < set->num_connectors; ro++) {
11463                         if (set->connectors[ro] == &connector->base)
11464                                 new_crtc = set->crtc;
11465                 }
11466
11467                 /* Make sure the new CRTC will work with the encoder */
11468                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11469                                          new_crtc)) {
11470                         return -EINVAL;
11471                 }
11472                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11473
11474                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11475                         connector->base.base.id,
11476                         connector->base.name,
11477                         new_crtc->base.id);
11478         }
11479
11480         /* Check for any encoders that needs to be disabled. */
11481         for_each_intel_encoder(dev, encoder) {
11482                 int num_connectors = 0;
11483                 list_for_each_entry(connector,
11484                                     &dev->mode_config.connector_list,
11485                                     base.head) {
11486                         if (connector->new_encoder == encoder) {
11487                                 WARN_ON(!connector->new_encoder->new_crtc);
11488                                 num_connectors++;
11489                         }
11490                 }
11491
11492                 if (num_connectors == 0)
11493                         encoder->new_crtc = NULL;
11494                 else if (num_connectors > 1)
11495                         return -EINVAL;
11496
11497                 /* Only now check for crtc changes so we don't miss encoders
11498                  * that will be disabled. */
11499                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11500                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11501                         config->mode_changed = true;
11502                 }
11503         }
11504         /* Now we've also updated encoder->new_crtc for all encoders. */
11505         list_for_each_entry(connector, &dev->mode_config.connector_list,
11506                             base.head) {
11507                 if (connector->new_encoder)
11508                         if (connector->new_encoder != connector->encoder)
11509                                 connector->encoder = connector->new_encoder;
11510         }
11511         for_each_intel_crtc(dev, crtc) {
11512                 crtc->new_enabled = false;
11513
11514                 for_each_intel_encoder(dev, encoder) {
11515                         if (encoder->new_crtc == crtc) {
11516                                 crtc->new_enabled = true;
11517                                 break;
11518                         }
11519                 }
11520
11521                 if (crtc->new_enabled != crtc->base.enabled) {
11522                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11523                                       crtc->new_enabled ? "en" : "dis");
11524                         config->mode_changed = true;
11525                 }
11526
11527                 if (crtc->new_enabled)
11528                         crtc->new_config = &crtc->config;
11529                 else
11530                         crtc->new_config = NULL;
11531         }
11532
11533         return 0;
11534 }
11535
11536 static void disable_crtc_nofb(struct intel_crtc *crtc)
11537 {
11538         struct drm_device *dev = crtc->base.dev;
11539         struct intel_encoder *encoder;
11540         struct intel_connector *connector;
11541
11542         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11543                       pipe_name(crtc->pipe));
11544
11545         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11546                 if (connector->new_encoder &&
11547                     connector->new_encoder->new_crtc == crtc)
11548                         connector->new_encoder = NULL;
11549         }
11550
11551         for_each_intel_encoder(dev, encoder) {
11552                 if (encoder->new_crtc == crtc)
11553                         encoder->new_crtc = NULL;
11554         }
11555
11556         crtc->new_enabled = false;
11557         crtc->new_config = NULL;
11558 }
11559
11560 static int intel_crtc_set_config(struct drm_mode_set *set)
11561 {
11562         struct drm_device *dev;
11563         struct drm_mode_set save_set;
11564         struct intel_set_config *config;
11565         int ret;
11566
11567         BUG_ON(!set);
11568         BUG_ON(!set->crtc);
11569         BUG_ON(!set->crtc->helper_private);
11570
11571         /* Enforce sane interface api - has been abused by the fb helper. */
11572         BUG_ON(!set->mode && set->fb);
11573         BUG_ON(set->fb && set->num_connectors == 0);
11574
11575         if (set->fb) {
11576                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11577                                 set->crtc->base.id, set->fb->base.id,
11578                                 (int)set->num_connectors, set->x, set->y);
11579         } else {
11580                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11581         }
11582
11583         dev = set->crtc->dev;
11584
11585         ret = -ENOMEM;
11586         config = kzalloc(sizeof(*config), GFP_KERNEL);
11587         if (!config)
11588                 goto out_config;
11589
11590         ret = intel_set_config_save_state(dev, config);
11591         if (ret)
11592                 goto out_config;
11593
11594         save_set.crtc = set->crtc;
11595         save_set.mode = &set->crtc->mode;
11596         save_set.x = set->crtc->x;
11597         save_set.y = set->crtc->y;
11598         save_set.fb = set->crtc->primary->fb;
11599
11600         /* Compute whether we need a full modeset, only an fb base update or no
11601          * change at all. In the future we might also check whether only the
11602          * mode changed, e.g. for LVDS where we only change the panel fitter in
11603          * such cases. */
11604         intel_set_config_compute_mode_changes(set, config);
11605
11606         ret = intel_modeset_stage_output_state(dev, set, config);
11607         if (ret)
11608                 goto fail;
11609
11610         if (config->mode_changed) {
11611                 ret = intel_set_mode(set->crtc, set->mode,
11612                                      set->x, set->y, set->fb);
11613         } else if (config->fb_changed) {
11614                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11615
11616                 intel_crtc_wait_for_pending_flips(set->crtc);
11617
11618                 ret = intel_pipe_set_base(set->crtc,
11619                                           set->x, set->y, set->fb);
11620
11621                 /*
11622                  * We need to make sure the primary plane is re-enabled if it
11623                  * has previously been turned off.
11624                  */
11625                 if (!intel_crtc->primary_enabled && ret == 0) {
11626                         WARN_ON(!intel_crtc->active);
11627                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11628                 }
11629
11630                 /*
11631                  * In the fastboot case this may be our only check of the
11632                  * state after boot.  It would be better to only do it on
11633                  * the first update, but we don't have a nice way of doing that
11634                  * (and really, set_config isn't used much for high freq page
11635                  * flipping, so increasing its cost here shouldn't be a big
11636                  * deal).
11637                  */
11638                 if (i915.fastboot && ret == 0)
11639                         intel_modeset_check_state(set->crtc->dev);
11640         }
11641
11642         if (ret) {
11643                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11644                               set->crtc->base.id, ret);
11645 fail:
11646                 intel_set_config_restore_state(dev, config);
11647
11648                 /*
11649                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11650                  * force the pipe off to avoid oopsing in the modeset code
11651                  * due to fb==NULL. This should only happen during boot since
11652                  * we don't yet reconstruct the FB from the hardware state.
11653                  */
11654                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11655                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11656
11657                 /* Try to restore the config */
11658                 if (config->mode_changed &&
11659                     intel_set_mode(save_set.crtc, save_set.mode,
11660                                    save_set.x, save_set.y, save_set.fb))
11661                         DRM_ERROR("failed to restore config after modeset failure\n");
11662         }
11663
11664 out_config:
11665         intel_set_config_free(config);
11666         return ret;
11667 }
11668
11669 static const struct drm_crtc_funcs intel_crtc_funcs = {
11670         .gamma_set = intel_crtc_gamma_set,
11671         .set_config = intel_crtc_set_config,
11672         .destroy = intel_crtc_destroy,
11673         .page_flip = intel_crtc_page_flip,
11674 };
11675
11676 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11677                                       struct intel_shared_dpll *pll,
11678                                       struct intel_dpll_hw_state *hw_state)
11679 {
11680         uint32_t val;
11681
11682         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11683                 return false;
11684
11685         val = I915_READ(PCH_DPLL(pll->id));
11686         hw_state->dpll = val;
11687         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11688         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11689
11690         return val & DPLL_VCO_ENABLE;
11691 }
11692
11693 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11694                                   struct intel_shared_dpll *pll)
11695 {
11696         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11697         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11698 }
11699
11700 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11701                                 struct intel_shared_dpll *pll)
11702 {
11703         /* PCH refclock must be enabled first */
11704         ibx_assert_pch_refclk_enabled(dev_priv);
11705
11706         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11707
11708         /* Wait for the clocks to stabilize. */
11709         POSTING_READ(PCH_DPLL(pll->id));
11710         udelay(150);
11711
11712         /* The pixel multiplier can only be updated once the
11713          * DPLL is enabled and the clocks are stable.
11714          *
11715          * So write it again.
11716          */
11717         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11718         POSTING_READ(PCH_DPLL(pll->id));
11719         udelay(200);
11720 }
11721
11722 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11723                                  struct intel_shared_dpll *pll)
11724 {
11725         struct drm_device *dev = dev_priv->dev;
11726         struct intel_crtc *crtc;
11727
11728         /* Make sure no transcoder isn't still depending on us. */
11729         for_each_intel_crtc(dev, crtc) {
11730                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11731                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11732         }
11733
11734         I915_WRITE(PCH_DPLL(pll->id), 0);
11735         POSTING_READ(PCH_DPLL(pll->id));
11736         udelay(200);
11737 }
11738
11739 static char *ibx_pch_dpll_names[] = {
11740         "PCH DPLL A",
11741         "PCH DPLL B",
11742 };
11743
11744 static void ibx_pch_dpll_init(struct drm_device *dev)
11745 {
11746         struct drm_i915_private *dev_priv = dev->dev_private;
11747         int i;
11748
11749         dev_priv->num_shared_dpll = 2;
11750
11751         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11752                 dev_priv->shared_dplls[i].id = i;
11753                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11754                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11755                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11756                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11757                 dev_priv->shared_dplls[i].get_hw_state =
11758                         ibx_pch_dpll_get_hw_state;
11759         }
11760 }
11761
11762 static void intel_shared_dpll_init(struct drm_device *dev)
11763 {
11764         struct drm_i915_private *dev_priv = dev->dev_private;
11765
11766         if (HAS_DDI(dev))
11767                 intel_ddi_pll_init(dev);
11768         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11769                 ibx_pch_dpll_init(dev);
11770         else
11771                 dev_priv->num_shared_dpll = 0;
11772
11773         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11774 }
11775
11776 static int
11777 intel_primary_plane_disable(struct drm_plane *plane)
11778 {
11779         struct drm_device *dev = plane->dev;
11780         struct intel_crtc *intel_crtc;
11781
11782         if (!plane->fb)
11783                 return 0;
11784
11785         BUG_ON(!plane->crtc);
11786
11787         intel_crtc = to_intel_crtc(plane->crtc);
11788
11789         /*
11790          * Even though we checked plane->fb above, it's still possible that
11791          * the primary plane has been implicitly disabled because the crtc
11792          * coordinates given weren't visible, or because we detected
11793          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11794          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11795          * In either case, we need to unpin the FB and let the fb pointer get
11796          * updated, but otherwise we don't need to touch the hardware.
11797          */
11798         if (!intel_crtc->primary_enabled)
11799                 goto disable_unpin;
11800
11801         intel_crtc_wait_for_pending_flips(plane->crtc);
11802         intel_disable_primary_hw_plane(plane, plane->crtc);
11803
11804 disable_unpin:
11805         mutex_lock(&dev->struct_mutex);
11806         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11807                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11808         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11809         mutex_unlock(&dev->struct_mutex);
11810         plane->fb = NULL;
11811
11812         return 0;
11813 }
11814
11815 static int
11816 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11817                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11818                              unsigned int crtc_w, unsigned int crtc_h,
11819                              uint32_t src_x, uint32_t src_y,
11820                              uint32_t src_w, uint32_t src_h)
11821 {
11822         struct drm_device *dev = crtc->dev;
11823         struct drm_i915_private *dev_priv = dev->dev_private;
11824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11825         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11826         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11827         struct drm_rect dest = {
11828                 /* integer pixels */
11829                 .x1 = crtc_x,
11830                 .y1 = crtc_y,
11831                 .x2 = crtc_x + crtc_w,
11832                 .y2 = crtc_y + crtc_h,
11833         };
11834         struct drm_rect src = {
11835                 /* 16.16 fixed point */
11836                 .x1 = src_x,
11837                 .y1 = src_y,
11838                 .x2 = src_x + src_w,
11839                 .y2 = src_y + src_h,
11840         };
11841         const struct drm_rect clip = {
11842                 /* integer pixels */
11843                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11844                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11845         };
11846         const struct {
11847                 int crtc_x, crtc_y;
11848                 unsigned int crtc_w, crtc_h;
11849                 uint32_t src_x, src_y, src_w, src_h;
11850         } orig = {
11851                 .crtc_x = crtc_x,
11852                 .crtc_y = crtc_y,
11853                 .crtc_w = crtc_w,
11854                 .crtc_h = crtc_h,
11855                 .src_x = src_x,
11856                 .src_y = src_y,
11857                 .src_w = src_w,
11858                 .src_h = src_h,
11859         };
11860         struct intel_plane *intel_plane = to_intel_plane(plane);
11861         bool visible;
11862         int ret;
11863
11864         ret = drm_plane_helper_check_update(plane, crtc, fb,
11865                                             &src, &dest, &clip,
11866                                             DRM_PLANE_HELPER_NO_SCALING,
11867                                             DRM_PLANE_HELPER_NO_SCALING,
11868                                             false, true, &visible);
11869
11870         if (ret)
11871                 return ret;
11872
11873         /*
11874          * If the CRTC isn't enabled, we're just pinning the framebuffer,
11875          * updating the fb pointer, and returning without touching the
11876          * hardware.  This allows us to later do a drmModeSetCrtc with fb=-1 to
11877          * turn on the display with all planes setup as desired.
11878          */
11879         if (!crtc->enabled) {
11880                 mutex_lock(&dev->struct_mutex);
11881
11882                 /*
11883                  * If we already called setplane while the crtc was disabled,
11884                  * we may have an fb pinned; unpin it.
11885                  */
11886                 if (plane->fb)
11887                         intel_unpin_fb_obj(old_obj);
11888
11889                 i915_gem_track_fb(old_obj, obj,
11890                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11891
11892                 /* Pin and return without programming hardware */
11893                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11894                 mutex_unlock(&dev->struct_mutex);
11895
11896                 return ret;
11897         }
11898
11899         intel_crtc_wait_for_pending_flips(crtc);
11900
11901         /*
11902          * If clipping results in a non-visible primary plane, we'll disable
11903          * the primary plane.  Note that this is a bit different than what
11904          * happens if userspace explicitly disables the plane by passing fb=0
11905          * because plane->fb still gets set and pinned.
11906          */
11907         if (!visible) {
11908                 mutex_lock(&dev->struct_mutex);
11909
11910                 /*
11911                  * Try to pin the new fb first so that we can bail out if we
11912                  * fail.
11913                  */
11914                 if (plane->fb != fb) {
11915                         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11916                         if (ret) {
11917                                 mutex_unlock(&dev->struct_mutex);
11918                                 return ret;
11919                         }
11920                 }
11921
11922                 i915_gem_track_fb(old_obj, obj,
11923                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11924
11925                 if (intel_crtc->primary_enabled)
11926                         intel_disable_primary_hw_plane(plane, crtc);
11927
11928
11929                 if (plane->fb != fb)
11930                         if (plane->fb)
11931                                 intel_unpin_fb_obj(old_obj);
11932
11933                 mutex_unlock(&dev->struct_mutex);
11934
11935         } else {
11936                 if (intel_crtc && intel_crtc->active &&
11937                     intel_crtc->primary_enabled) {
11938                         /*
11939                          * FBC does not work on some platforms for rotated
11940                          * planes, so disable it when rotation is not 0 and
11941                          * update it when rotation is set back to 0.
11942                          *
11943                          * FIXME: This is redundant with the fbc update done in
11944                          * the primary plane enable function except that that
11945                          * one is done too late. We eventually need to unify
11946                          * this.
11947                          */
11948                         if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11949                             dev_priv->fbc.plane == intel_crtc->plane &&
11950                             intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11951                                 intel_disable_fbc(dev);
11952                         }
11953                 }
11954                 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11955                 if (ret)
11956                         return ret;
11957
11958                 if (!intel_crtc->primary_enabled)
11959                         intel_enable_primary_hw_plane(plane, crtc);
11960         }
11961
11962         intel_plane->crtc_x = orig.crtc_x;
11963         intel_plane->crtc_y = orig.crtc_y;
11964         intel_plane->crtc_w = orig.crtc_w;
11965         intel_plane->crtc_h = orig.crtc_h;
11966         intel_plane->src_x = orig.src_x;
11967         intel_plane->src_y = orig.src_y;
11968         intel_plane->src_w = orig.src_w;
11969         intel_plane->src_h = orig.src_h;
11970         intel_plane->obj = obj;
11971
11972         return 0;
11973 }
11974
11975 /* Common destruction function for both primary and cursor planes */
11976 static void intel_plane_destroy(struct drm_plane *plane)
11977 {
11978         struct intel_plane *intel_plane = to_intel_plane(plane);
11979         drm_plane_cleanup(plane);
11980         kfree(intel_plane);
11981 }
11982
11983 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11984         .update_plane = intel_primary_plane_setplane,
11985         .disable_plane = intel_primary_plane_disable,
11986         .destroy = intel_plane_destroy,
11987         .set_property = intel_plane_set_property
11988 };
11989
11990 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11991                                                     int pipe)
11992 {
11993         struct intel_plane *primary;
11994         const uint32_t *intel_primary_formats;
11995         int num_formats;
11996
11997         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11998         if (primary == NULL)
11999                 return NULL;
12000
12001         primary->can_scale = false;
12002         primary->max_downscale = 1;
12003         primary->pipe = pipe;
12004         primary->plane = pipe;
12005         primary->rotation = BIT(DRM_ROTATE_0);
12006         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12007                 primary->plane = !pipe;
12008
12009         if (INTEL_INFO(dev)->gen <= 3) {
12010                 intel_primary_formats = intel_primary_formats_gen2;
12011                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12012         } else {
12013                 intel_primary_formats = intel_primary_formats_gen4;
12014                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12015         }
12016
12017         drm_universal_plane_init(dev, &primary->base, 0,
12018                                  &intel_primary_plane_funcs,
12019                                  intel_primary_formats, num_formats,
12020                                  DRM_PLANE_TYPE_PRIMARY);
12021
12022         if (INTEL_INFO(dev)->gen >= 4) {
12023                 if (!dev->mode_config.rotation_property)
12024                         dev->mode_config.rotation_property =
12025                                 drm_mode_create_rotation_property(dev,
12026                                                         BIT(DRM_ROTATE_0) |
12027                                                         BIT(DRM_ROTATE_180));
12028                 if (dev->mode_config.rotation_property)
12029                         drm_object_attach_property(&primary->base.base,
12030                                 dev->mode_config.rotation_property,
12031                                 primary->rotation);
12032         }
12033
12034         return &primary->base;
12035 }
12036
12037 static int
12038 intel_cursor_plane_disable(struct drm_plane *plane)
12039 {
12040         if (!plane->fb)
12041                 return 0;
12042
12043         BUG_ON(!plane->crtc);
12044
12045         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12046 }
12047
12048 static int
12049 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12050                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12051                           unsigned int crtc_w, unsigned int crtc_h,
12052                           uint32_t src_x, uint32_t src_y,
12053                           uint32_t src_w, uint32_t src_h)
12054 {
12055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12056         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12057         struct drm_i915_gem_object *obj = intel_fb->obj;
12058         struct drm_rect dest = {
12059                 /* integer pixels */
12060                 .x1 = crtc_x,
12061                 .y1 = crtc_y,
12062                 .x2 = crtc_x + crtc_w,
12063                 .y2 = crtc_y + crtc_h,
12064         };
12065         struct drm_rect src = {
12066                 /* 16.16 fixed point */
12067                 .x1 = src_x,
12068                 .y1 = src_y,
12069                 .x2 = src_x + src_w,
12070                 .y2 = src_y + src_h,
12071         };
12072         const struct drm_rect clip = {
12073                 /* integer pixels */
12074                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
12075                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
12076         };
12077         bool visible;
12078         int ret;
12079
12080         ret = drm_plane_helper_check_update(plane, crtc, fb,
12081                                             &src, &dest, &clip,
12082                                             DRM_PLANE_HELPER_NO_SCALING,
12083                                             DRM_PLANE_HELPER_NO_SCALING,
12084                                             true, true, &visible);
12085         if (ret)
12086                 return ret;
12087
12088         crtc->cursor_x = crtc_x;
12089         crtc->cursor_y = crtc_y;
12090         if (fb != crtc->cursor->fb) {
12091                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12092         } else {
12093                 intel_crtc_update_cursor(crtc, visible);
12094
12095                 intel_frontbuffer_flip(crtc->dev,
12096                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12097
12098                 return 0;
12099         }
12100 }
12101 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12102         .update_plane = intel_cursor_plane_update,
12103         .disable_plane = intel_cursor_plane_disable,
12104         .destroy = intel_plane_destroy,
12105 };
12106
12107 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12108                                                    int pipe)
12109 {
12110         struct intel_plane *cursor;
12111
12112         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12113         if (cursor == NULL)
12114                 return NULL;
12115
12116         cursor->can_scale = false;
12117         cursor->max_downscale = 1;
12118         cursor->pipe = pipe;
12119         cursor->plane = pipe;
12120
12121         drm_universal_plane_init(dev, &cursor->base, 0,
12122                                  &intel_cursor_plane_funcs,
12123                                  intel_cursor_formats,
12124                                  ARRAY_SIZE(intel_cursor_formats),
12125                                  DRM_PLANE_TYPE_CURSOR);
12126         return &cursor->base;
12127 }
12128
12129 static void intel_crtc_init(struct drm_device *dev, int pipe)
12130 {
12131         struct drm_i915_private *dev_priv = dev->dev_private;
12132         struct intel_crtc *intel_crtc;
12133         struct drm_plane *primary = NULL;
12134         struct drm_plane *cursor = NULL;
12135         int i, ret;
12136
12137         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12138         if (intel_crtc == NULL)
12139                 return;
12140
12141         primary = intel_primary_plane_create(dev, pipe);
12142         if (!primary)
12143                 goto fail;
12144
12145         cursor = intel_cursor_plane_create(dev, pipe);
12146         if (!cursor)
12147                 goto fail;
12148
12149         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12150                                         cursor, &intel_crtc_funcs);
12151         if (ret)
12152                 goto fail;
12153
12154         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12155         for (i = 0; i < 256; i++) {
12156                 intel_crtc->lut_r[i] = i;
12157                 intel_crtc->lut_g[i] = i;
12158                 intel_crtc->lut_b[i] = i;
12159         }
12160
12161         /*
12162          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12163          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12164          */
12165         intel_crtc->pipe = pipe;
12166         intel_crtc->plane = pipe;
12167         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12168                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12169                 intel_crtc->plane = !pipe;
12170         }
12171
12172         intel_crtc->cursor_base = ~0;
12173         intel_crtc->cursor_cntl = ~0;
12174         intel_crtc->cursor_size = ~0;
12175
12176         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12177                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12178         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12179         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12180
12181         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12182
12183         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12184         return;
12185
12186 fail:
12187         if (primary)
12188                 drm_plane_cleanup(primary);
12189         if (cursor)
12190                 drm_plane_cleanup(cursor);
12191         kfree(intel_crtc);
12192 }
12193
12194 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12195 {
12196         struct drm_encoder *encoder = connector->base.encoder;
12197         struct drm_device *dev = connector->base.dev;
12198
12199         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12200
12201         if (!encoder)
12202                 return INVALID_PIPE;
12203
12204         return to_intel_crtc(encoder->crtc)->pipe;
12205 }
12206
12207 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12208                                 struct drm_file *file)
12209 {
12210         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12211         struct drm_crtc *drmmode_crtc;
12212         struct intel_crtc *crtc;
12213
12214         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12215                 return -ENODEV;
12216
12217         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12218
12219         if (!drmmode_crtc) {
12220                 DRM_ERROR("no such CRTC id\n");
12221                 return -ENOENT;
12222         }
12223
12224         crtc = to_intel_crtc(drmmode_crtc);
12225         pipe_from_crtc_id->pipe = crtc->pipe;
12226
12227         return 0;
12228 }
12229
12230 static int intel_encoder_clones(struct intel_encoder *encoder)
12231 {
12232         struct drm_device *dev = encoder->base.dev;
12233         struct intel_encoder *source_encoder;
12234         int index_mask = 0;
12235         int entry = 0;
12236
12237         for_each_intel_encoder(dev, source_encoder) {
12238                 if (encoders_cloneable(encoder, source_encoder))
12239                         index_mask |= (1 << entry);
12240
12241                 entry++;
12242         }
12243
12244         return index_mask;
12245 }
12246
12247 static bool has_edp_a(struct drm_device *dev)
12248 {
12249         struct drm_i915_private *dev_priv = dev->dev_private;
12250
12251         if (!IS_MOBILE(dev))
12252                 return false;
12253
12254         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12255                 return false;
12256
12257         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12258                 return false;
12259
12260         return true;
12261 }
12262
12263 const char *intel_output_name(int output)
12264 {
12265         static const char *names[] = {
12266                 [INTEL_OUTPUT_UNUSED] = "Unused",
12267                 [INTEL_OUTPUT_ANALOG] = "Analog",
12268                 [INTEL_OUTPUT_DVO] = "DVO",
12269                 [INTEL_OUTPUT_SDVO] = "SDVO",
12270                 [INTEL_OUTPUT_LVDS] = "LVDS",
12271                 [INTEL_OUTPUT_TVOUT] = "TV",
12272                 [INTEL_OUTPUT_HDMI] = "HDMI",
12273                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12274                 [INTEL_OUTPUT_EDP] = "eDP",
12275                 [INTEL_OUTPUT_DSI] = "DSI",
12276                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12277         };
12278
12279         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12280                 return "Invalid";
12281
12282         return names[output];
12283 }
12284
12285 static bool intel_crt_present(struct drm_device *dev)
12286 {
12287         struct drm_i915_private *dev_priv = dev->dev_private;
12288
12289         if (IS_ULT(dev))
12290                 return false;
12291
12292         if (IS_CHERRYVIEW(dev))
12293                 return false;
12294
12295         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12296                 return false;
12297
12298         return true;
12299 }
12300
12301 static void intel_setup_outputs(struct drm_device *dev)
12302 {
12303         struct drm_i915_private *dev_priv = dev->dev_private;
12304         struct intel_encoder *encoder;
12305         bool dpd_is_edp = false;
12306
12307         intel_lvds_init(dev);
12308
12309         if (intel_crt_present(dev))
12310                 intel_crt_init(dev);
12311
12312         if (HAS_DDI(dev)) {
12313                 int found;
12314
12315                 /* Haswell uses DDI functions to detect digital outputs */
12316                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12317                 /* DDI A only supports eDP */
12318                 if (found)
12319                         intel_ddi_init(dev, PORT_A);
12320
12321                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12322                  * register */
12323                 found = I915_READ(SFUSE_STRAP);
12324
12325                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12326                         intel_ddi_init(dev, PORT_B);
12327                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12328                         intel_ddi_init(dev, PORT_C);
12329                 if (found & SFUSE_STRAP_DDID_DETECTED)
12330                         intel_ddi_init(dev, PORT_D);
12331         } else if (HAS_PCH_SPLIT(dev)) {
12332                 int found;
12333                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12334
12335                 if (has_edp_a(dev))
12336                         intel_dp_init(dev, DP_A, PORT_A);
12337
12338                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12339                         /* PCH SDVOB multiplex with HDMIB */
12340                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12341                         if (!found)
12342                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12343                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12344                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12345                 }
12346
12347                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12348                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12349
12350                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12351                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12352
12353                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12354                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12355
12356                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12357                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12358         } else if (IS_VALLEYVIEW(dev)) {
12359                 /*
12360                  * The DP_DETECTED bit is the latched state of the DDC
12361                  * SDA pin at boot. However since eDP doesn't require DDC
12362                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12363                  * eDP ports may have been muxed to an alternate function.
12364                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12365                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12366                  * detect eDP ports.
12367                  */
12368                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12369                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12370                                         PORT_B);
12371                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12372                     intel_dp_is_edp(dev, PORT_B))
12373                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12374
12375                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12376                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12377                                         PORT_C);
12378                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12379                     intel_dp_is_edp(dev, PORT_C))
12380                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12381
12382                 if (IS_CHERRYVIEW(dev)) {
12383                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12384                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12385                                                 PORT_D);
12386                         /* eDP not supported on port D, so don't check VBT */
12387                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12388                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12389                 }
12390
12391                 intel_dsi_init(dev);
12392         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12393                 bool found = false;
12394
12395                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12396                         DRM_DEBUG_KMS("probing SDVOB\n");
12397                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12398                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12399                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12400                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12401                         }
12402
12403                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12404                                 intel_dp_init(dev, DP_B, PORT_B);
12405                 }
12406
12407                 /* Before G4X SDVOC doesn't have its own detect register */
12408
12409                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12410                         DRM_DEBUG_KMS("probing SDVOC\n");
12411                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12412                 }
12413
12414                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12415
12416                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12417                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12418                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12419                         }
12420                         if (SUPPORTS_INTEGRATED_DP(dev))
12421                                 intel_dp_init(dev, DP_C, PORT_C);
12422                 }
12423
12424                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12425                     (I915_READ(DP_D) & DP_DETECTED))
12426                         intel_dp_init(dev, DP_D, PORT_D);
12427         } else if (IS_GEN2(dev))
12428                 intel_dvo_init(dev);
12429
12430         if (SUPPORTS_TV(dev))
12431                 intel_tv_init(dev);
12432
12433         intel_edp_psr_init(dev);
12434
12435         for_each_intel_encoder(dev, encoder) {
12436                 encoder->base.possible_crtcs = encoder->crtc_mask;
12437                 encoder->base.possible_clones =
12438                         intel_encoder_clones(encoder);
12439         }
12440
12441         intel_init_pch_refclk(dev);
12442
12443         drm_helper_move_panel_connectors_to_head(dev);
12444 }
12445
12446 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12447 {
12448         struct drm_device *dev = fb->dev;
12449         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12450
12451         drm_framebuffer_cleanup(fb);
12452         mutex_lock(&dev->struct_mutex);
12453         WARN_ON(!intel_fb->obj->framebuffer_references--);
12454         drm_gem_object_unreference(&intel_fb->obj->base);
12455         mutex_unlock(&dev->struct_mutex);
12456         kfree(intel_fb);
12457 }
12458
12459 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12460                                                 struct drm_file *file,
12461                                                 unsigned int *handle)
12462 {
12463         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12464         struct drm_i915_gem_object *obj = intel_fb->obj;
12465
12466         return drm_gem_handle_create(file, &obj->base, handle);
12467 }
12468
12469 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12470         .destroy = intel_user_framebuffer_destroy,
12471         .create_handle = intel_user_framebuffer_create_handle,
12472 };
12473
12474 static int intel_framebuffer_init(struct drm_device *dev,
12475                                   struct intel_framebuffer *intel_fb,
12476                                   struct drm_mode_fb_cmd2 *mode_cmd,
12477                                   struct drm_i915_gem_object *obj)
12478 {
12479         int aligned_height;
12480         int pitch_limit;
12481         int ret;
12482
12483         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12484
12485         if (obj->tiling_mode == I915_TILING_Y) {
12486                 DRM_DEBUG("hardware does not support tiling Y\n");
12487                 return -EINVAL;
12488         }
12489
12490         if (mode_cmd->pitches[0] & 63) {
12491                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12492                           mode_cmd->pitches[0]);
12493                 return -EINVAL;
12494         }
12495
12496         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12497                 pitch_limit = 32*1024;
12498         } else if (INTEL_INFO(dev)->gen >= 4) {
12499                 if (obj->tiling_mode)
12500                         pitch_limit = 16*1024;
12501                 else
12502                         pitch_limit = 32*1024;
12503         } else if (INTEL_INFO(dev)->gen >= 3) {
12504                 if (obj->tiling_mode)
12505                         pitch_limit = 8*1024;
12506                 else
12507                         pitch_limit = 16*1024;
12508         } else
12509                 /* XXX DSPC is limited to 4k tiled */
12510                 pitch_limit = 8*1024;
12511
12512         if (mode_cmd->pitches[0] > pitch_limit) {
12513                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12514                           obj->tiling_mode ? "tiled" : "linear",
12515                           mode_cmd->pitches[0], pitch_limit);
12516                 return -EINVAL;
12517         }
12518
12519         if (obj->tiling_mode != I915_TILING_NONE &&
12520             mode_cmd->pitches[0] != obj->stride) {
12521                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12522                           mode_cmd->pitches[0], obj->stride);
12523                 return -EINVAL;
12524         }
12525
12526         /* Reject formats not supported by any plane early. */
12527         switch (mode_cmd->pixel_format) {
12528         case DRM_FORMAT_C8:
12529         case DRM_FORMAT_RGB565:
12530         case DRM_FORMAT_XRGB8888:
12531         case DRM_FORMAT_ARGB8888:
12532                 break;
12533         case DRM_FORMAT_XRGB1555:
12534         case DRM_FORMAT_ARGB1555:
12535                 if (INTEL_INFO(dev)->gen > 3) {
12536                         DRM_DEBUG("unsupported pixel format: %s\n",
12537                                   drm_get_format_name(mode_cmd->pixel_format));
12538                         return -EINVAL;
12539                 }
12540                 break;
12541         case DRM_FORMAT_XBGR8888:
12542         case DRM_FORMAT_ABGR8888:
12543         case DRM_FORMAT_XRGB2101010:
12544         case DRM_FORMAT_ARGB2101010:
12545         case DRM_FORMAT_XBGR2101010:
12546         case DRM_FORMAT_ABGR2101010:
12547                 if (INTEL_INFO(dev)->gen < 4) {
12548                         DRM_DEBUG("unsupported pixel format: %s\n",
12549                                   drm_get_format_name(mode_cmd->pixel_format));
12550                         return -EINVAL;
12551                 }
12552                 break;
12553         case DRM_FORMAT_YUYV:
12554         case DRM_FORMAT_UYVY:
12555         case DRM_FORMAT_YVYU:
12556         case DRM_FORMAT_VYUY:
12557                 if (INTEL_INFO(dev)->gen < 5) {
12558                         DRM_DEBUG("unsupported pixel format: %s\n",
12559                                   drm_get_format_name(mode_cmd->pixel_format));
12560                         return -EINVAL;
12561                 }
12562                 break;
12563         default:
12564                 DRM_DEBUG("unsupported pixel format: %s\n",
12565                           drm_get_format_name(mode_cmd->pixel_format));
12566                 return -EINVAL;
12567         }
12568
12569         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12570         if (mode_cmd->offsets[0] != 0)
12571                 return -EINVAL;
12572
12573         aligned_height = intel_align_height(dev, mode_cmd->height,
12574                                             obj->tiling_mode);
12575         /* FIXME drm helper for size checks (especially planar formats)? */
12576         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12577                 return -EINVAL;
12578
12579         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12580         intel_fb->obj = obj;
12581         intel_fb->obj->framebuffer_references++;
12582
12583         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12584         if (ret) {
12585                 DRM_ERROR("framebuffer init failed %d\n", ret);
12586                 return ret;
12587         }
12588
12589         return 0;
12590 }
12591
12592 static struct drm_framebuffer *
12593 intel_user_framebuffer_create(struct drm_device *dev,
12594                               struct drm_file *filp,
12595                               struct drm_mode_fb_cmd2 *mode_cmd)
12596 {
12597         struct drm_i915_gem_object *obj;
12598
12599         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12600                                                 mode_cmd->handles[0]));
12601         if (&obj->base == NULL)
12602                 return ERR_PTR(-ENOENT);
12603
12604         return intel_framebuffer_create(dev, mode_cmd, obj);
12605 }
12606
12607 #ifndef CONFIG_DRM_I915_FBDEV
12608 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12609 {
12610 }
12611 #endif
12612
12613 static const struct drm_mode_config_funcs intel_mode_funcs = {
12614         .fb_create = intel_user_framebuffer_create,
12615         .output_poll_changed = intel_fbdev_output_poll_changed,
12616 };
12617
12618 /* Set up chip specific display functions */
12619 static void intel_init_display(struct drm_device *dev)
12620 {
12621         struct drm_i915_private *dev_priv = dev->dev_private;
12622
12623         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12624                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12625         else if (IS_CHERRYVIEW(dev))
12626                 dev_priv->display.find_dpll = chv_find_best_dpll;
12627         else if (IS_VALLEYVIEW(dev))
12628                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12629         else if (IS_PINEVIEW(dev))
12630                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12631         else
12632                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12633
12634         if (HAS_DDI(dev)) {
12635                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12636                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12637                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12638                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12639                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12640                 dev_priv->display.off = ironlake_crtc_off;
12641                 dev_priv->display.update_primary_plane =
12642                         ironlake_update_primary_plane;
12643         } else if (HAS_PCH_SPLIT(dev)) {
12644                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12645                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12646                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12647                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12648                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12649                 dev_priv->display.off = ironlake_crtc_off;
12650                 dev_priv->display.update_primary_plane =
12651                         ironlake_update_primary_plane;
12652         } else if (IS_VALLEYVIEW(dev)) {
12653                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12654                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12655                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12656                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12657                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12658                 dev_priv->display.off = i9xx_crtc_off;
12659                 dev_priv->display.update_primary_plane =
12660                         i9xx_update_primary_plane;
12661         } else {
12662                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12663                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12664                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12665                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12666                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12667                 dev_priv->display.off = i9xx_crtc_off;
12668                 dev_priv->display.update_primary_plane =
12669                         i9xx_update_primary_plane;
12670         }
12671
12672         /* Returns the core display clock speed */
12673         if (IS_VALLEYVIEW(dev))
12674                 dev_priv->display.get_display_clock_speed =
12675                         valleyview_get_display_clock_speed;
12676         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12677                 dev_priv->display.get_display_clock_speed =
12678                         i945_get_display_clock_speed;
12679         else if (IS_I915G(dev))
12680                 dev_priv->display.get_display_clock_speed =
12681                         i915_get_display_clock_speed;
12682         else if (IS_I945GM(dev) || IS_845G(dev))
12683                 dev_priv->display.get_display_clock_speed =
12684                         i9xx_misc_get_display_clock_speed;
12685         else if (IS_PINEVIEW(dev))
12686                 dev_priv->display.get_display_clock_speed =
12687                         pnv_get_display_clock_speed;
12688         else if (IS_I915GM(dev))
12689                 dev_priv->display.get_display_clock_speed =
12690                         i915gm_get_display_clock_speed;
12691         else if (IS_I865G(dev))
12692                 dev_priv->display.get_display_clock_speed =
12693                         i865_get_display_clock_speed;
12694         else if (IS_I85X(dev))
12695                 dev_priv->display.get_display_clock_speed =
12696                         i855_get_display_clock_speed;
12697         else /* 852, 830 */
12698                 dev_priv->display.get_display_clock_speed =
12699                         i830_get_display_clock_speed;
12700
12701         if (IS_G4X(dev)) {
12702                 dev_priv->display.write_eld = g4x_write_eld;
12703         } else if (IS_GEN5(dev)) {
12704                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12705                 dev_priv->display.write_eld = ironlake_write_eld;
12706         } else if (IS_GEN6(dev)) {
12707                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12708                 dev_priv->display.write_eld = ironlake_write_eld;
12709                 dev_priv->display.modeset_global_resources =
12710                         snb_modeset_global_resources;
12711         } else if (IS_IVYBRIDGE(dev)) {
12712                 /* FIXME: detect B0+ stepping and use auto training */
12713                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12714                 dev_priv->display.write_eld = ironlake_write_eld;
12715                 dev_priv->display.modeset_global_resources =
12716                         ivb_modeset_global_resources;
12717         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12718                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12719                 dev_priv->display.write_eld = haswell_write_eld;
12720                 dev_priv->display.modeset_global_resources =
12721                         haswell_modeset_global_resources;
12722         } else if (IS_VALLEYVIEW(dev)) {
12723                 dev_priv->display.modeset_global_resources =
12724                         valleyview_modeset_global_resources;
12725                 dev_priv->display.write_eld = ironlake_write_eld;
12726         }
12727
12728         /* Default just returns -ENODEV to indicate unsupported */
12729         dev_priv->display.queue_flip = intel_default_queue_flip;
12730
12731         switch (INTEL_INFO(dev)->gen) {
12732         case 2:
12733                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12734                 break;
12735
12736         case 3:
12737                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12738                 break;
12739
12740         case 4:
12741         case 5:
12742                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12743                 break;
12744
12745         case 6:
12746                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12747                 break;
12748         case 7:
12749         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12750                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12751                 break;
12752         }
12753
12754         intel_panel_init_backlight_funcs(dev);
12755
12756         mutex_init(&dev_priv->pps_mutex);
12757 }
12758
12759 /*
12760  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12761  * resume, or other times.  This quirk makes sure that's the case for
12762  * affected systems.
12763  */
12764 static void quirk_pipea_force(struct drm_device *dev)
12765 {
12766         struct drm_i915_private *dev_priv = dev->dev_private;
12767
12768         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12769         DRM_INFO("applying pipe a force quirk\n");
12770 }
12771
12772 static void quirk_pipeb_force(struct drm_device *dev)
12773 {
12774         struct drm_i915_private *dev_priv = dev->dev_private;
12775
12776         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12777         DRM_INFO("applying pipe b force quirk\n");
12778 }
12779
12780 /*
12781  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12782  */
12783 static void quirk_ssc_force_disable(struct drm_device *dev)
12784 {
12785         struct drm_i915_private *dev_priv = dev->dev_private;
12786         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12787         DRM_INFO("applying lvds SSC disable quirk\n");
12788 }
12789
12790 /*
12791  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12792  * brightness value
12793  */
12794 static void quirk_invert_brightness(struct drm_device *dev)
12795 {
12796         struct drm_i915_private *dev_priv = dev->dev_private;
12797         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12798         DRM_INFO("applying inverted panel brightness quirk\n");
12799 }
12800
12801 /* Some VBT's incorrectly indicate no backlight is present */
12802 static void quirk_backlight_present(struct drm_device *dev)
12803 {
12804         struct drm_i915_private *dev_priv = dev->dev_private;
12805         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12806         DRM_INFO("applying backlight present quirk\n");
12807 }
12808
12809 struct intel_quirk {
12810         int device;
12811         int subsystem_vendor;
12812         int subsystem_device;
12813         void (*hook)(struct drm_device *dev);
12814 };
12815
12816 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12817 struct intel_dmi_quirk {
12818         void (*hook)(struct drm_device *dev);
12819         const struct dmi_system_id (*dmi_id_list)[];
12820 };
12821
12822 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12823 {
12824         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12825         return 1;
12826 }
12827
12828 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12829         {
12830                 .dmi_id_list = &(const struct dmi_system_id[]) {
12831                         {
12832                                 .callback = intel_dmi_reverse_brightness,
12833                                 .ident = "NCR Corporation",
12834                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12835                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12836                                 },
12837                         },
12838                         { }  /* terminating entry */
12839                 },
12840                 .hook = quirk_invert_brightness,
12841         },
12842 };
12843
12844 static struct intel_quirk intel_quirks[] = {
12845         /* HP Mini needs pipe A force quirk (LP: #322104) */
12846         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12847
12848         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12849         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12850
12851         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12852         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12853
12854         /* 830 needs to leave pipe A & dpll A up */
12855         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12856
12857         /* 830 needs to leave pipe B & dpll B up */
12858         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12859
12860         /* Lenovo U160 cannot use SSC on LVDS */
12861         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12862
12863         /* Sony Vaio Y cannot use SSC on LVDS */
12864         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12865
12866         /* Acer Aspire 5734Z must invert backlight brightness */
12867         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12868
12869         /* Acer/eMachines G725 */
12870         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12871
12872         /* Acer/eMachines e725 */
12873         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12874
12875         /* Acer/Packard Bell NCL20 */
12876         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12877
12878         /* Acer Aspire 4736Z */
12879         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12880
12881         /* Acer Aspire 5336 */
12882         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12883
12884         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12885         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12886
12887         /* Acer C720 Chromebook (Core i3 4005U) */
12888         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12889
12890         /* Apple Macbook 2,1 (Core 2 T7400) */
12891         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12892
12893         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12894         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12895
12896         /* HP Chromebook 14 (Celeron 2955U) */
12897         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12898 };
12899
12900 static void intel_init_quirks(struct drm_device *dev)
12901 {
12902         struct pci_dev *d = dev->pdev;
12903         int i;
12904
12905         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12906                 struct intel_quirk *q = &intel_quirks[i];
12907
12908                 if (d->device == q->device &&
12909                     (d->subsystem_vendor == q->subsystem_vendor ||
12910                      q->subsystem_vendor == PCI_ANY_ID) &&
12911                     (d->subsystem_device == q->subsystem_device ||
12912                      q->subsystem_device == PCI_ANY_ID))
12913                         q->hook(dev);
12914         }
12915         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12916                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12917                         intel_dmi_quirks[i].hook(dev);
12918         }
12919 }
12920
12921 /* Disable the VGA plane that we never use */
12922 static void i915_disable_vga(struct drm_device *dev)
12923 {
12924         struct drm_i915_private *dev_priv = dev->dev_private;
12925         u8 sr1;
12926         u32 vga_reg = i915_vgacntrl_reg(dev);
12927
12928         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12929         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12930         outb(SR01, VGA_SR_INDEX);
12931         sr1 = inb(VGA_SR_DATA);
12932         outb(sr1 | 1<<5, VGA_SR_DATA);
12933         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12934         udelay(300);
12935
12936         /*
12937          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12938          * from S3 without preserving (some of?) the other bits.
12939          */
12940         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12941         POSTING_READ(vga_reg);
12942 }
12943
12944 void intel_modeset_init_hw(struct drm_device *dev)
12945 {
12946         intel_prepare_ddi(dev);
12947
12948         if (IS_VALLEYVIEW(dev))
12949                 vlv_update_cdclk(dev);
12950
12951         intel_init_clock_gating(dev);
12952
12953         intel_enable_gt_powersave(dev);
12954 }
12955
12956 void intel_modeset_suspend_hw(struct drm_device *dev)
12957 {
12958         intel_suspend_hw(dev);
12959 }
12960
12961 void intel_modeset_init(struct drm_device *dev)
12962 {
12963         struct drm_i915_private *dev_priv = dev->dev_private;
12964         int sprite, ret;
12965         enum pipe pipe;
12966         struct intel_crtc *crtc;
12967
12968         drm_mode_config_init(dev);
12969
12970         dev->mode_config.min_width = 0;
12971         dev->mode_config.min_height = 0;
12972
12973         dev->mode_config.preferred_depth = 24;
12974         dev->mode_config.prefer_shadow = 1;
12975
12976         dev->mode_config.funcs = &intel_mode_funcs;
12977
12978         intel_init_quirks(dev);
12979
12980         intel_init_pm(dev);
12981
12982         if (INTEL_INFO(dev)->num_pipes == 0)
12983                 return;
12984
12985         intel_init_display(dev);
12986
12987         if (IS_GEN2(dev)) {
12988                 dev->mode_config.max_width = 2048;
12989                 dev->mode_config.max_height = 2048;
12990         } else if (IS_GEN3(dev)) {
12991                 dev->mode_config.max_width = 4096;
12992                 dev->mode_config.max_height = 4096;
12993         } else {
12994                 dev->mode_config.max_width = 8192;
12995                 dev->mode_config.max_height = 8192;
12996         }
12997
12998         if (IS_845G(dev) || IS_I865G(dev)) {
12999                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13000                 dev->mode_config.cursor_height = 1023;
13001         } else if (IS_GEN2(dev)) {
13002                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13003                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13004         } else {
13005                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13006                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13007         }
13008
13009         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13010
13011         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13012                       INTEL_INFO(dev)->num_pipes,
13013                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13014
13015         for_each_pipe(dev_priv, pipe) {
13016                 intel_crtc_init(dev, pipe);
13017                 for_each_sprite(pipe, sprite) {
13018                         ret = intel_plane_init(dev, pipe, sprite);
13019                         if (ret)
13020                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13021                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13022                 }
13023         }
13024
13025         intel_init_dpio(dev);
13026
13027         intel_shared_dpll_init(dev);
13028
13029         /* save the BIOS value before clobbering it */
13030         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13031         /* Just disable it once at startup */
13032         i915_disable_vga(dev);
13033         intel_setup_outputs(dev);
13034
13035         /* Just in case the BIOS is doing something questionable. */
13036         intel_disable_fbc(dev);
13037
13038         drm_modeset_lock_all(dev);
13039         intel_modeset_setup_hw_state(dev, false);
13040         drm_modeset_unlock_all(dev);
13041
13042         for_each_intel_crtc(dev, crtc) {
13043                 if (!crtc->active)
13044                         continue;
13045
13046                 /*
13047                  * Note that reserving the BIOS fb up front prevents us
13048                  * from stuffing other stolen allocations like the ring
13049                  * on top.  This prevents some ugliness at boot time, and
13050                  * can even allow for smooth boot transitions if the BIOS
13051                  * fb is large enough for the active pipe configuration.
13052                  */
13053                 if (dev_priv->display.get_plane_config) {
13054                         dev_priv->display.get_plane_config(crtc,
13055                                                            &crtc->plane_config);
13056                         /*
13057                          * If the fb is shared between multiple heads, we'll
13058                          * just get the first one.
13059                          */
13060                         intel_find_plane_obj(crtc, &crtc->plane_config);
13061                 }
13062         }
13063 }
13064
13065 static void intel_enable_pipe_a(struct drm_device *dev)
13066 {
13067         struct intel_connector *connector;
13068         struct drm_connector *crt = NULL;
13069         struct intel_load_detect_pipe load_detect_temp;
13070         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13071
13072         /* We can't just switch on the pipe A, we need to set things up with a
13073          * proper mode and output configuration. As a gross hack, enable pipe A
13074          * by enabling the load detect pipe once. */
13075         list_for_each_entry(connector,
13076                             &dev->mode_config.connector_list,
13077                             base.head) {
13078                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13079                         crt = &connector->base;
13080                         break;
13081                 }
13082         }
13083
13084         if (!crt)
13085                 return;
13086
13087         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13088                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13089 }
13090
13091 static bool
13092 intel_check_plane_mapping(struct intel_crtc *crtc)
13093 {
13094         struct drm_device *dev = crtc->base.dev;
13095         struct drm_i915_private *dev_priv = dev->dev_private;
13096         u32 reg, val;
13097
13098         if (INTEL_INFO(dev)->num_pipes == 1)
13099                 return true;
13100
13101         reg = DSPCNTR(!crtc->plane);
13102         val = I915_READ(reg);
13103
13104         if ((val & DISPLAY_PLANE_ENABLE) &&
13105             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13106                 return false;
13107
13108         return true;
13109 }
13110
13111 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13112 {
13113         struct drm_device *dev = crtc->base.dev;
13114         struct drm_i915_private *dev_priv = dev->dev_private;
13115         u32 reg;
13116
13117         /* Clear any frame start delays used for debugging left by the BIOS */
13118         reg = PIPECONF(crtc->config.cpu_transcoder);
13119         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13120
13121         /* restore vblank interrupts to correct state */
13122         if (crtc->active) {
13123                 update_scanline_offset(crtc);
13124                 drm_vblank_on(dev, crtc->pipe);
13125         } else
13126                 drm_vblank_off(dev, crtc->pipe);
13127
13128         /* We need to sanitize the plane -> pipe mapping first because this will
13129          * disable the crtc (and hence change the state) if it is wrong. Note
13130          * that gen4+ has a fixed plane -> pipe mapping.  */
13131         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13132                 struct intel_connector *connector;
13133                 bool plane;
13134
13135                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13136                               crtc->base.base.id);
13137
13138                 /* Pipe has the wrong plane attached and the plane is active.
13139                  * Temporarily change the plane mapping and disable everything
13140                  * ...  */
13141                 plane = crtc->plane;
13142                 crtc->plane = !plane;
13143                 crtc->primary_enabled = true;
13144                 dev_priv->display.crtc_disable(&crtc->base);
13145                 crtc->plane = plane;
13146
13147                 /* ... and break all links. */
13148                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13149                                     base.head) {
13150                         if (connector->encoder->base.crtc != &crtc->base)
13151                                 continue;
13152
13153                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13154                         connector->base.encoder = NULL;
13155                 }
13156                 /* multiple connectors may have the same encoder:
13157                  *  handle them and break crtc link separately */
13158                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13159                                     base.head)
13160                         if (connector->encoder->base.crtc == &crtc->base) {
13161                                 connector->encoder->base.crtc = NULL;
13162                                 connector->encoder->connectors_active = false;
13163                         }
13164
13165                 WARN_ON(crtc->active);
13166                 crtc->base.enabled = false;
13167         }
13168
13169         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13170             crtc->pipe == PIPE_A && !crtc->active) {
13171                 /* BIOS forgot to enable pipe A, this mostly happens after
13172                  * resume. Force-enable the pipe to fix this, the update_dpms
13173                  * call below we restore the pipe to the right state, but leave
13174                  * the required bits on. */
13175                 intel_enable_pipe_a(dev);
13176         }
13177
13178         /* Adjust the state of the output pipe according to whether we
13179          * have active connectors/encoders. */
13180         intel_crtc_update_dpms(&crtc->base);
13181
13182         if (crtc->active != crtc->base.enabled) {
13183                 struct intel_encoder *encoder;
13184
13185                 /* This can happen either due to bugs in the get_hw_state
13186                  * functions or because the pipe is force-enabled due to the
13187                  * pipe A quirk. */
13188                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13189                               crtc->base.base.id,
13190                               crtc->base.enabled ? "enabled" : "disabled",
13191                               crtc->active ? "enabled" : "disabled");
13192
13193                 crtc->base.enabled = crtc->active;
13194
13195                 /* Because we only establish the connector -> encoder ->
13196                  * crtc links if something is active, this means the
13197                  * crtc is now deactivated. Break the links. connector
13198                  * -> encoder links are only establish when things are
13199                  *  actually up, hence no need to break them. */
13200                 WARN_ON(crtc->active);
13201
13202                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13203                         WARN_ON(encoder->connectors_active);
13204                         encoder->base.crtc = NULL;
13205                 }
13206         }
13207
13208         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13209                 /*
13210                  * We start out with underrun reporting disabled to avoid races.
13211                  * For correct bookkeeping mark this on active crtcs.
13212                  *
13213                  * Also on gmch platforms we dont have any hardware bits to
13214                  * disable the underrun reporting. Which means we need to start
13215                  * out with underrun reporting disabled also on inactive pipes,
13216                  * since otherwise we'll complain about the garbage we read when
13217                  * e.g. coming up after runtime pm.
13218                  *
13219                  * No protection against concurrent access is required - at
13220                  * worst a fifo underrun happens which also sets this to false.
13221                  */
13222                 crtc->cpu_fifo_underrun_disabled = true;
13223                 crtc->pch_fifo_underrun_disabled = true;
13224         }
13225 }
13226
13227 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13228 {
13229         struct intel_connector *connector;
13230         struct drm_device *dev = encoder->base.dev;
13231
13232         /* We need to check both for a crtc link (meaning that the
13233          * encoder is active and trying to read from a pipe) and the
13234          * pipe itself being active. */
13235         bool has_active_crtc = encoder->base.crtc &&
13236                 to_intel_crtc(encoder->base.crtc)->active;
13237
13238         if (encoder->connectors_active && !has_active_crtc) {
13239                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13240                               encoder->base.base.id,
13241                               encoder->base.name);
13242
13243                 /* Connector is active, but has no active pipe. This is
13244                  * fallout from our resume register restoring. Disable
13245                  * the encoder manually again. */
13246                 if (encoder->base.crtc) {
13247                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13248                                       encoder->base.base.id,
13249                                       encoder->base.name);
13250                         encoder->disable(encoder);
13251                         if (encoder->post_disable)
13252                                 encoder->post_disable(encoder);
13253                 }
13254                 encoder->base.crtc = NULL;
13255                 encoder->connectors_active = false;
13256
13257                 /* Inconsistent output/port/pipe state happens presumably due to
13258                  * a bug in one of the get_hw_state functions. Or someplace else
13259                  * in our code, like the register restore mess on resume. Clamp
13260                  * things to off as a safer default. */
13261                 list_for_each_entry(connector,
13262                                     &dev->mode_config.connector_list,
13263                                     base.head) {
13264                         if (connector->encoder != encoder)
13265                                 continue;
13266                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13267                         connector->base.encoder = NULL;
13268                 }
13269         }
13270         /* Enabled encoders without active connectors will be fixed in
13271          * the crtc fixup. */
13272 }
13273
13274 void i915_redisable_vga_power_on(struct drm_device *dev)
13275 {
13276         struct drm_i915_private *dev_priv = dev->dev_private;
13277         u32 vga_reg = i915_vgacntrl_reg(dev);
13278
13279         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13280                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13281                 i915_disable_vga(dev);
13282         }
13283 }
13284
13285 void i915_redisable_vga(struct drm_device *dev)
13286 {
13287         struct drm_i915_private *dev_priv = dev->dev_private;
13288
13289         /* This function can be called both from intel_modeset_setup_hw_state or
13290          * at a very early point in our resume sequence, where the power well
13291          * structures are not yet restored. Since this function is at a very
13292          * paranoid "someone might have enabled VGA while we were not looking"
13293          * level, just check if the power well is enabled instead of trying to
13294          * follow the "don't touch the power well if we don't need it" policy
13295          * the rest of the driver uses. */
13296         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13297                 return;
13298
13299         i915_redisable_vga_power_on(dev);
13300 }
13301
13302 static bool primary_get_hw_state(struct intel_crtc *crtc)
13303 {
13304         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13305
13306         if (!crtc->active)
13307                 return false;
13308
13309         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13310 }
13311
13312 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13313 {
13314         struct drm_i915_private *dev_priv = dev->dev_private;
13315         enum pipe pipe;
13316         struct intel_crtc *crtc;
13317         struct intel_encoder *encoder;
13318         struct intel_connector *connector;
13319         int i;
13320
13321         for_each_intel_crtc(dev, crtc) {
13322                 memset(&crtc->config, 0, sizeof(crtc->config));
13323
13324                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13325
13326                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13327                                                                  &crtc->config);
13328
13329                 crtc->base.enabled = crtc->active;
13330                 crtc->primary_enabled = primary_get_hw_state(crtc);
13331
13332                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13333                               crtc->base.base.id,
13334                               crtc->active ? "enabled" : "disabled");
13335         }
13336
13337         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13338                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13339
13340                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13341                 pll->active = 0;
13342                 for_each_intel_crtc(dev, crtc) {
13343                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13344                                 pll->active++;
13345                 }
13346                 pll->refcount = pll->active;
13347
13348                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13349                               pll->name, pll->refcount, pll->on);
13350
13351                 if (pll->refcount)
13352                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13353         }
13354
13355         for_each_intel_encoder(dev, encoder) {
13356                 pipe = 0;
13357
13358                 if (encoder->get_hw_state(encoder, &pipe)) {
13359                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13360                         encoder->base.crtc = &crtc->base;
13361                         encoder->get_config(encoder, &crtc->config);
13362                 } else {
13363                         encoder->base.crtc = NULL;
13364                 }
13365
13366                 encoder->connectors_active = false;
13367                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13368                               encoder->base.base.id,
13369                               encoder->base.name,
13370                               encoder->base.crtc ? "enabled" : "disabled",
13371                               pipe_name(pipe));
13372         }
13373
13374         list_for_each_entry(connector, &dev->mode_config.connector_list,
13375                             base.head) {
13376                 if (connector->get_hw_state(connector)) {
13377                         connector->base.dpms = DRM_MODE_DPMS_ON;
13378                         connector->encoder->connectors_active = true;
13379                         connector->base.encoder = &connector->encoder->base;
13380                 } else {
13381                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13382                         connector->base.encoder = NULL;
13383                 }
13384                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13385                               connector->base.base.id,
13386                               connector->base.name,
13387                               connector->base.encoder ? "enabled" : "disabled");
13388         }
13389 }
13390
13391 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13392  * and i915 state tracking structures. */
13393 void intel_modeset_setup_hw_state(struct drm_device *dev,
13394                                   bool force_restore)
13395 {
13396         struct drm_i915_private *dev_priv = dev->dev_private;
13397         enum pipe pipe;
13398         struct intel_crtc *crtc;
13399         struct intel_encoder *encoder;
13400         int i;
13401
13402         intel_modeset_readout_hw_state(dev);
13403
13404         /*
13405          * Now that we have the config, copy it to each CRTC struct
13406          * Note that this could go away if we move to using crtc_config
13407          * checking everywhere.
13408          */
13409         for_each_intel_crtc(dev, crtc) {
13410                 if (crtc->active && i915.fastboot) {
13411                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13412                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13413                                       crtc->base.base.id);
13414                         drm_mode_debug_printmodeline(&crtc->base.mode);
13415                 }
13416         }
13417
13418         /* HW state is read out, now we need to sanitize this mess. */
13419         for_each_intel_encoder(dev, encoder) {
13420                 intel_sanitize_encoder(encoder);
13421         }
13422
13423         for_each_pipe(dev_priv, pipe) {
13424                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13425                 intel_sanitize_crtc(crtc);
13426                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13427         }
13428
13429         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13430                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13431
13432                 if (!pll->on || pll->active)
13433                         continue;
13434
13435                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13436
13437                 pll->disable(dev_priv, pll);
13438                 pll->on = false;
13439         }
13440
13441         if (HAS_PCH_SPLIT(dev))
13442                 ilk_wm_get_hw_state(dev);
13443
13444         if (force_restore) {
13445                 i915_redisable_vga(dev);
13446
13447                 /*
13448                  * We need to use raw interfaces for restoring state to avoid
13449                  * checking (bogus) intermediate states.
13450                  */
13451                 for_each_pipe(dev_priv, pipe) {
13452                         struct drm_crtc *crtc =
13453                                 dev_priv->pipe_to_crtc_mapping[pipe];
13454
13455                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13456                                          crtc->primary->fb);
13457                 }
13458         } else {
13459                 intel_modeset_update_staged_output_state(dev);
13460         }
13461
13462         intel_modeset_check_state(dev);
13463 }
13464
13465 void intel_modeset_gem_init(struct drm_device *dev)
13466 {
13467         struct drm_crtc *c;
13468         struct drm_i915_gem_object *obj;
13469
13470         mutex_lock(&dev->struct_mutex);
13471         intel_init_gt_powersave(dev);
13472         mutex_unlock(&dev->struct_mutex);
13473
13474         intel_modeset_init_hw(dev);
13475
13476         intel_setup_overlay(dev);
13477
13478         /*
13479          * Make sure any fbs we allocated at startup are properly
13480          * pinned & fenced.  When we do the allocation it's too early
13481          * for this.
13482          */
13483         mutex_lock(&dev->struct_mutex);
13484         for_each_crtc(dev, c) {
13485                 obj = intel_fb_obj(c->primary->fb);
13486                 if (obj == NULL)
13487                         continue;
13488
13489                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13490                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13491                                   to_intel_crtc(c)->pipe);
13492                         drm_framebuffer_unreference(c->primary->fb);
13493                         c->primary->fb = NULL;
13494                 }
13495         }
13496         mutex_unlock(&dev->struct_mutex);
13497 }
13498
13499 void intel_connector_unregister(struct intel_connector *intel_connector)
13500 {
13501         struct drm_connector *connector = &intel_connector->base;
13502
13503         intel_panel_destroy_backlight(connector);
13504         drm_connector_unregister(connector);
13505 }
13506
13507 void intel_modeset_cleanup(struct drm_device *dev)
13508 {
13509         struct drm_i915_private *dev_priv = dev->dev_private;
13510         struct drm_connector *connector;
13511
13512         /*
13513          * Interrupts and polling as the first thing to avoid creating havoc.
13514          * Too much stuff here (turning of rps, connectors, ...) would
13515          * experience fancy races otherwise.
13516          */
13517         drm_irq_uninstall(dev);
13518         intel_hpd_cancel_work(dev_priv);
13519         dev_priv->pm._irqs_disabled = true;
13520
13521         /*
13522          * Due to the hpd irq storm handling the hotplug work can re-arm the
13523          * poll handlers. Hence disable polling after hpd handling is shut down.
13524          */
13525         drm_kms_helper_poll_fini(dev);
13526
13527         mutex_lock(&dev->struct_mutex);
13528
13529         intel_unregister_dsm_handler();
13530
13531         intel_disable_fbc(dev);
13532
13533         intel_disable_gt_powersave(dev);
13534
13535         ironlake_teardown_rc6(dev);
13536
13537         mutex_unlock(&dev->struct_mutex);
13538
13539         /* flush any delayed tasks or pending work */
13540         flush_scheduled_work();
13541
13542         /* destroy the backlight and sysfs files before encoders/connectors */
13543         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13544                 struct intel_connector *intel_connector;
13545
13546                 intel_connector = to_intel_connector(connector);
13547                 intel_connector->unregister(intel_connector);
13548         }
13549
13550         drm_mode_config_cleanup(dev);
13551
13552         intel_cleanup_overlay(dev);
13553
13554         mutex_lock(&dev->struct_mutex);
13555         intel_cleanup_gt_powersave(dev);
13556         mutex_unlock(&dev->struct_mutex);
13557 }
13558
13559 /*
13560  * Return which encoder is currently attached for connector.
13561  */
13562 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13563 {
13564         return &intel_attached_encoder(connector)->base;
13565 }
13566
13567 void intel_connector_attach_encoder(struct intel_connector *connector,
13568                                     struct intel_encoder *encoder)
13569 {
13570         connector->encoder = encoder;
13571         drm_mode_connector_attach_encoder(&connector->base,
13572                                           &encoder->base);
13573 }
13574
13575 /*
13576  * set vga decode state - true == enable VGA decode
13577  */
13578 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13579 {
13580         struct drm_i915_private *dev_priv = dev->dev_private;
13581         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13582         u16 gmch_ctrl;
13583
13584         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13585                 DRM_ERROR("failed to read control word\n");
13586                 return -EIO;
13587         }
13588
13589         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13590                 return 0;
13591
13592         if (state)
13593                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13594         else
13595                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13596
13597         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13598                 DRM_ERROR("failed to write control word\n");
13599                 return -EIO;
13600         }
13601
13602         return 0;
13603 }
13604
13605 struct intel_display_error_state {
13606
13607         u32 power_well_driver;
13608
13609         int num_transcoders;
13610
13611         struct intel_cursor_error_state {
13612                 u32 control;
13613                 u32 position;
13614                 u32 base;
13615                 u32 size;
13616         } cursor[I915_MAX_PIPES];
13617
13618         struct intel_pipe_error_state {
13619                 bool power_domain_on;
13620                 u32 source;
13621                 u32 stat;
13622         } pipe[I915_MAX_PIPES];
13623
13624         struct intel_plane_error_state {
13625                 u32 control;
13626                 u32 stride;
13627                 u32 size;
13628                 u32 pos;
13629                 u32 addr;
13630                 u32 surface;
13631                 u32 tile_offset;
13632         } plane[I915_MAX_PIPES];
13633
13634         struct intel_transcoder_error_state {
13635                 bool power_domain_on;
13636                 enum transcoder cpu_transcoder;
13637
13638                 u32 conf;
13639
13640                 u32 htotal;
13641                 u32 hblank;
13642                 u32 hsync;
13643                 u32 vtotal;
13644                 u32 vblank;
13645                 u32 vsync;
13646         } transcoder[4];
13647 };
13648
13649 struct intel_display_error_state *
13650 intel_display_capture_error_state(struct drm_device *dev)
13651 {
13652         struct drm_i915_private *dev_priv = dev->dev_private;
13653         struct intel_display_error_state *error;
13654         int transcoders[] = {
13655                 TRANSCODER_A,
13656                 TRANSCODER_B,
13657                 TRANSCODER_C,
13658                 TRANSCODER_EDP,
13659         };
13660         int i;
13661
13662         if (INTEL_INFO(dev)->num_pipes == 0)
13663                 return NULL;
13664
13665         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13666         if (error == NULL)
13667                 return NULL;
13668
13669         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13670                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13671
13672         for_each_pipe(dev_priv, i) {
13673                 error->pipe[i].power_domain_on =
13674                         intel_display_power_enabled_unlocked(dev_priv,
13675                                                            POWER_DOMAIN_PIPE(i));
13676                 if (!error->pipe[i].power_domain_on)
13677                         continue;
13678
13679                 error->cursor[i].control = I915_READ(CURCNTR(i));
13680                 error->cursor[i].position = I915_READ(CURPOS(i));
13681                 error->cursor[i].base = I915_READ(CURBASE(i));
13682
13683                 error->plane[i].control = I915_READ(DSPCNTR(i));
13684                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13685                 if (INTEL_INFO(dev)->gen <= 3) {
13686                         error->plane[i].size = I915_READ(DSPSIZE(i));
13687                         error->plane[i].pos = I915_READ(DSPPOS(i));
13688                 }
13689                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13690                         error->plane[i].addr = I915_READ(DSPADDR(i));
13691                 if (INTEL_INFO(dev)->gen >= 4) {
13692                         error->plane[i].surface = I915_READ(DSPSURF(i));
13693                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13694                 }
13695
13696                 error->pipe[i].source = I915_READ(PIPESRC(i));
13697
13698                 if (HAS_GMCH_DISPLAY(dev))
13699                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13700         }
13701
13702         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13703         if (HAS_DDI(dev_priv->dev))
13704                 error->num_transcoders++; /* Account for eDP. */
13705
13706         for (i = 0; i < error->num_transcoders; i++) {
13707                 enum transcoder cpu_transcoder = transcoders[i];
13708
13709                 error->transcoder[i].power_domain_on =
13710                         intel_display_power_enabled_unlocked(dev_priv,
13711                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13712                 if (!error->transcoder[i].power_domain_on)
13713                         continue;
13714
13715                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13716
13717                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13718                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13719                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13720                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13721                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13722                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13723                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13724         }
13725
13726         return error;
13727 }
13728
13729 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13730
13731 void
13732 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13733                                 struct drm_device *dev,
13734                                 struct intel_display_error_state *error)
13735 {
13736         struct drm_i915_private *dev_priv = dev->dev_private;
13737         int i;
13738
13739         if (!error)
13740                 return;
13741
13742         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13743         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13744                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13745                            error->power_well_driver);
13746         for_each_pipe(dev_priv, i) {
13747                 err_printf(m, "Pipe [%d]:\n", i);
13748                 err_printf(m, "  Power: %s\n",
13749                            error->pipe[i].power_domain_on ? "on" : "off");
13750                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13751                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13752
13753                 err_printf(m, "Plane [%d]:\n", i);
13754                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13755                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13756                 if (INTEL_INFO(dev)->gen <= 3) {
13757                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13758                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13759                 }
13760                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13761                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13762                 if (INTEL_INFO(dev)->gen >= 4) {
13763                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13764                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13765                 }
13766
13767                 err_printf(m, "Cursor [%d]:\n", i);
13768                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13769                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13770                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13771         }
13772
13773         for (i = 0; i < error->num_transcoders; i++) {
13774                 err_printf(m, "CPU transcoder: %c\n",
13775                            transcoder_name(error->transcoder[i].cpu_transcoder));
13776                 err_printf(m, "  Power: %s\n",
13777                            error->transcoder[i].power_domain_on ? "on" : "off");
13778                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13779                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13780                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13781                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13782                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13783                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13784                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13785         }
13786 }
13787
13788 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13789 {
13790         struct intel_crtc *crtc;
13791
13792         for_each_intel_crtc(dev, crtc) {
13793                 struct intel_unpin_work *work;
13794                 unsigned long irqflags;
13795
13796                 spin_lock_irqsave(&dev->event_lock, irqflags);
13797
13798                 work = crtc->unpin_work;
13799
13800                 if (work && work->event &&
13801                     work->event->base.file_priv == file) {
13802                         kfree(work->event);
13803                         work->event = NULL;
13804                 }
13805
13806                 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13807         }
13808 }