drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/module.h>
  30 #include <linux/input.h>
  31 #include <linux/i2c.h>
  32 #include <linux/kernel.h>
  33 #include <linux/slab.h>
  34 #include <linux/vgaarb.h>
  35 #include <drm/drm_edid.h>
  36 #include "drmP.h"
  37 #include "intel_drv.h"
  38 #include "i915_drm.h"
  39 #include "i915_drv.h"
  40 #include "i915_trace.h"
  41 #include "drm_dp_helper.h"
  42 #include "drm_crtc_helper.h"
  43 #include <linux/dma_remapping.h>
  44
  45 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  46
  47 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 364 {
 365         unsigned long flags;
 366         u32 val = 0;
 367
 368         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 369         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 370                 DRM_ERROR("DPIO idle wait timed out\n");
 371                 goto out_unlock;
 372         }
 373
 374         I915_WRITE(DPIO_REG, reg);
 375         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 376                    DPIO_BYTE);
 377         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 378                 DRM_ERROR("DPIO read wait timed out\n");
 379                 goto out_unlock;
 380         }
 381         val = I915_READ(DPIO_DATA);
 382
 383 out_unlock:
 384         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 385         return val;
 386 }
 387
 388 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 389                              u32 val)
 390 {
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 394         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 395                 DRM_ERROR("DPIO idle wait timed out\n");
 396                 goto out_unlock;
 397         }
 398
 399         I915_WRITE(DPIO_DATA, val);
 400         I915_WRITE(DPIO_REG, reg);
 401         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 402                    DPIO_BYTE);
 403         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 404                 DRM_ERROR("DPIO write wait timed out\n");
 405
 406 out_unlock:
 407         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 408 }
 409
 410 static void vlv_init_dpio(struct drm_device *dev)
 411 {
 412         struct drm_i915_private *dev_priv = dev->dev_private;
 413
 414         /* Reset the DPIO config */
 415         I915_WRITE(DPIO_CTL, 0);
 416         POSTING_READ(DPIO_CTL);
 417         I915_WRITE(DPIO_CTL, 1);
 418         POSTING_READ(DPIO_CTL);
 419 }
 420
 421 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 422 {
 423         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 424         return 1;
 425 }
 426
 427 static const struct dmi_system_id intel_dual_link_lvds[] = {
 428         {
 429                 .callback = intel_dual_link_lvds_callback,
 430                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 431                 .matches = {
 432                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 433                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 434                 },
 435         },
 436         { }     /* terminating entry */
 437 };
 438
 439 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 440                               unsigned int reg)
 441 {
 442         unsigned int val;
 443
 444         /* use the module option value if specified */
 445         if (i915_lvds_channel_mode > 0)
 446                 return i915_lvds_channel_mode == 2;
 447
 448         if (dmi_check_system(intel_dual_link_lvds))
 449                 return true;
 450
 451         if (dev_priv->lvds_val)
 452                 val = dev_priv->lvds_val;
 453         else {
 454                 /* BIOS should set the proper LVDS register value at boot, but
 455                  * in reality, it doesn't set the value when the lid is closed;
 456                  * we need to check "the value to be set" in VBT when LVDS
 457                  * register is uninitialized.
 458                  */
 459                 val = I915_READ(reg);
 460                 if (!(val & ~LVDS_DETECTED))
 461                         val = dev_priv->bios_lvds_val;
 462                 dev_priv->lvds_val = val;
 463         }
 464         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 465 }
 466
 467 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 468                                                 int refclk)
 469 {
 470         struct drm_device *dev = crtc->dev;
 471         struct drm_i915_private *dev_priv = dev->dev_private;
 472         const intel_limit_t *limit;
 473
 474         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 475                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 476                         /* LVDS dual channel */
 477                         if (refclk == 100000)
 478                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 479                         else
 480                                 limit = &intel_limits_ironlake_dual_lvds;
 481                 } else {
 482                         if (refclk == 100000)
 483                                 limit = &intel_limits_ironlake_single_lvds_100m;
 484                         else
 485                                 limit = &intel_limits_ironlake_single_lvds;
 486                 }
 487         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 488                         HAS_eDP)
 489                 limit = &intel_limits_ironlake_display_port;
 490         else
 491                 limit = &intel_limits_ironlake_dac;
 492
 493         return limit;
 494 }
 495
 496 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 497 {
 498         struct drm_device *dev = crtc->dev;
 499         struct drm_i915_private *dev_priv = dev->dev_private;
 500         const intel_limit_t *limit;
 501
 502         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 503                 if (is_dual_link_lvds(dev_priv, LVDS))
 504                         /* LVDS with dual channel */
 505                         limit = &intel_limits_g4x_dual_channel_lvds;
 506                 else
 507                         /* LVDS with dual channel */
 508                         limit = &intel_limits_g4x_single_channel_lvds;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 510                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 511                 limit = &intel_limits_g4x_hdmi;
 512         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 513                 limit = &intel_limits_g4x_sdvo;
 514         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 515                 limit = &intel_limits_g4x_display_port;
 516         } else /* The option is for other outputs */
 517                 limit = &intel_limits_i9xx_sdvo;
 518
 519         return limit;
 520 }
 521
 522 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 523 {
 524         struct drm_device *dev = crtc->dev;
 525         const intel_limit_t *limit;
 526
 527         if (HAS_PCH_SPLIT(dev))
 528                 limit = intel_ironlake_limit(crtc, refclk);
 529         else if (IS_G4X(dev)) {
 530                 limit = intel_g4x_limit(crtc);
 531         } else if (IS_PINEVIEW(dev)) {
 532                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 533                         limit = &intel_limits_pineview_lvds;
 534                 else
 535                         limit = &intel_limits_pineview_sdvo;
 536         } else if (!IS_GEN2(dev)) {
 537                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 538                         limit = &intel_limits_i9xx_lvds;
 539                 else
 540                         limit = &intel_limits_i9xx_sdvo;
 541         } else {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_i8xx_lvds;
 544                 else
 545                         limit = &intel_limits_i8xx_dvo;
 546         }
 547         return limit;
 548 }
 549
 550 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 551 static void pineview_clock(int refclk, intel_clock_t *clock)
 552 {
 553         clock->m = clock->m2 + 2;
 554         clock->p = clock->p1 * clock->p2;
 555         clock->vco = refclk * clock->m / clock->n;
 556         clock->dot = clock->vco / clock->p;
 557 }
 558
 559 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 560 {
 561         if (IS_PINEVIEW(dev)) {
 562                 pineview_clock(refclk, clock);
 563                 return;
 564         }
 565         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 566         clock->p = clock->p1 * clock->p2;
 567         clock->vco = refclk * clock->m / (clock->n + 2);
 568         clock->dot = clock->vco / clock->p;
 569 }
 570
 571 /**
 572  * Returns whether any output on the specified pipe is of the specified type
 573  */
 574 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 575 {
 576         struct drm_device *dev = crtc->dev;
 577         struct drm_mode_config *mode_config = &dev->mode_config;
 578         struct intel_encoder *encoder;
 579
 580         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 581                 if (encoder->base.crtc == crtc && encoder->type == type)
 582                         return true;
 583
 584         return false;
 585 }
 586
 587 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 588 /**
 589  * Returns whether the given set of divisors are valid for a given refclk with
 590  * the given connectors.
 591  */
 592
 593 static bool intel_PLL_is_valid(struct drm_device *dev,
 594                                const intel_limit_t *limit,
 595                                const intel_clock_t *clock)
 596 {
 597         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 598                 INTELPllInvalid("p1 out of range\n");
 599         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 600                 INTELPllInvalid("p out of range\n");
 601         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 602                 INTELPllInvalid("m2 out of range\n");
 603         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 604                 INTELPllInvalid("m1 out of range\n");
 605         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 606                 INTELPllInvalid("m1 <= m2\n");
 607         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 608                 INTELPllInvalid("m out of range\n");
 609         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 610                 INTELPllInvalid("n out of range\n");
 611         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 612                 INTELPllInvalid("vco out of range\n");
 613         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 614          * connector, etc., rather than just a single range.
 615          */
 616         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 617                 INTELPllInvalid("dot out of range\n");
 618
 619         return true;
 620 }
 621
 622 static bool
 623 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 624                     int target, int refclk, intel_clock_t *match_clock,
 625                     intel_clock_t *best_clock)
 626
 627 {
 628         struct drm_device *dev = crtc->dev;
 629         struct drm_i915_private *dev_priv = dev->dev_private;
 630         intel_clock_t clock;
 631         int err = target;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 634             (I915_READ(LVDS)) != 0) {
 635                 /*
 636                  * For LVDS, if the panel is on, just rely on its current
 637                  * settings for dual-channel.  We haven't figured out how to
 638                  * reliably set up different single/dual channel state, if we
 639                  * even can.
 640                  */
 641                 if (is_dual_link_lvds(dev_priv, LVDS))
 642                         clock.p2 = limit->p2.p2_fast;
 643                 else
 644                         clock.p2 = limit->p2.p2_slow;
 645         } else {
 646                 if (target < limit->p2.dot_limit)
 647                         clock.p2 = limit->p2.p2_slow;
 648                 else
 649                         clock.p2 = limit->p2.p2_fast;
 650         }
 651
 652         memset(best_clock, 0, sizeof(*best_clock));
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         /* m1 is always 0 in Pineview */
 659                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 660                                 break;
 661                         for (clock.n = limit->n.min;
 662                              clock.n <= limit->n.max; clock.n++) {
 663                                 for (clock.p1 = limit->p1.min;
 664                                         clock.p1 <= limit->p1.max; clock.p1++) {
 665                                         int this_err;
 666
 667                                         intel_clock(dev, refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 static bool
 689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 690                         int target, int refclk, intel_clock_t *match_clock,
 691                         intel_clock_t *best_clock)
 692 {
 693         struct drm_device *dev = crtc->dev;
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695         intel_clock_t clock;
 696         int max_n;
 697         bool found;
 698         /* approximately equals target * 0.00585 */
 699         int err_most = (target >> 8) + (target >> 9);
 700         found = false;
 701
 702         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 703                 int lvds_reg;
 704
 705                 if (HAS_PCH_SPLIT(dev))
 706                         lvds_reg = PCH_LVDS;
 707                 else
 708                         lvds_reg = LVDS;
 709                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 710                     LVDS_CLKB_POWER_UP)
 711                         clock.p2 = limit->p2.p2_fast;
 712                 else
 713                         clock.p2 = limit->p2.p2_slow;
 714         } else {
 715                 if (target < limit->p2.dot_limit)
 716                         clock.p2 = limit->p2.p2_slow;
 717                 else
 718                         clock.p2 = limit->p2.p2_fast;
 719         }
 720
 721         memset(best_clock, 0, sizeof(*best_clock));
 722         max_n = limit->n.max;
 723         /* based on hardware requirement, prefer smaller n to precision */
 724         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 725                 /* based on hardware requirement, prefere larger m1,m2 */
 726                 for (clock.m1 = limit->m1.max;
 727                      clock.m1 >= limit->m1.min; clock.m1--) {
 728                         for (clock.m2 = limit->m2.max;
 729                              clock.m2 >= limit->m2.min; clock.m2--) {
 730                                 for (clock.p1 = limit->p1.max;
 731                                      clock.p1 >= limit->p1.min; clock.p1--) {
 732                                         int this_err;
 733
 734                                         intel_clock(dev, refclk, &clock);
 735                                         if (!intel_PLL_is_valid(dev, limit,
 736                                                                 &clock))
 737                                                 continue;
 738                                         if (match_clock &&
 739                                             clock.p != match_clock->p)
 740                                                 continue;
 741
 742                                         this_err = abs(clock.dot - target);
 743                                         if (this_err < err_most) {
 744                                                 *best_clock = clock;
 745                                                 err_most = this_err;
 746                                                 max_n = clock.n;
 747                                                 found = true;
 748                                         }
 749                                 }
 750                         }
 751                 }
 752         }
 753         return found;
 754 }
 755
 756 static bool
 757 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 758                            int target, int refclk, intel_clock_t *match_clock,
 759                            intel_clock_t *best_clock)
 760 {
 761         struct drm_device *dev = crtc->dev;
 762         intel_clock_t clock;
 763
 764         if (target < 200000) {
 765                 clock.n = 1;
 766                 clock.p1 = 2;
 767                 clock.p2 = 10;
 768                 clock.m1 = 12;
 769                 clock.m2 = 9;
 770         } else {
 771                 clock.n = 2;
 772                 clock.p1 = 1;
 773                 clock.p2 = 10;
 774                 clock.m1 = 14;
 775                 clock.m2 = 8;
 776         }
 777         intel_clock(dev, refclk, &clock);
 778         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 779         return true;
 780 }
 781
 782 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 783 static bool
 784 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 785                       int target, int refclk, intel_clock_t *match_clock,
 786                       intel_clock_t *best_clock)
 787 {
 788         intel_clock_t clock;
 789         if (target < 200000) {
 790                 clock.p1 = 2;
 791                 clock.p2 = 10;
 792                 clock.n = 2;
 793                 clock.m1 = 23;
 794                 clock.m2 = 8;
 795         } else {
 796                 clock.p1 = 1;
 797                 clock.p2 = 10;
 798                 clock.n = 1;
 799                 clock.m1 = 14;
 800                 clock.m2 = 2;
 801         }
 802         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 803         clock.p = (clock.p1 * clock.p2);
 804         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 805         clock.vco = 0;
 806         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 807         return true;
 808 }
 809
 810 /**
 811  * intel_wait_for_vblank - wait for vblank on a given pipe
 812  * @dev: drm device
 813  * @pipe: pipe to wait for
 814  *
 815  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 816  * mode setting code.
 817  */
 818 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 819 {
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         int pipestat_reg = PIPESTAT(pipe);
 822
 823         /* Clear existing vblank status. Note this will clear any other
 824          * sticky status fields as well.
 825          *
 826          * This races with i915_driver_irq_handler() with the result
 827          * that either function could miss a vblank event.  Here it is not
 828          * fatal, as we will either wait upon the next vblank interrupt or
 829          * timeout.  Generally speaking intel_wait_for_vblank() is only
 830          * called during modeset at which time the GPU should be idle and
 831          * should *not* be performing page flips and thus not waiting on
 832          * vblanks...
 833          * Currently, the result of us stealing a vblank from the irq
 834          * handler is that a single frame will be skipped during swapbuffers.
 835          */
 836         I915_WRITE(pipestat_reg,
 837                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 838
 839         /* Wait for vblank interrupt bit to set */
 840         if (wait_for(I915_READ(pipestat_reg) &
 841                      PIPE_VBLANK_INTERRUPT_STATUS,
 842                      50))
 843                 DRM_DEBUG_KMS("vblank wait timed out\n");
 844 }
 845
 846 /*
 847  * intel_wait_for_pipe_off - wait for pipe to turn off
 848  * @dev: drm device
 849  * @pipe: pipe to wait for
 850  *
 851  * After disabling a pipe, we can't wait for vblank in the usual way,
 852  * spinning on the vblank interrupt status bit, since we won't actually
 853  * see an interrupt when the pipe is disabled.
 854  *
 855  * On Gen4 and above:
 856  *   wait for the pipe register state bit to turn off
 857  *
 858  * Otherwise:
 859  *   wait for the display line value to settle (it usually
 860  *   ends up stopping at the start of the next frame).
 861  *
 862  */
 863 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866
 867         if (INTEL_INFO(dev)->gen >= 4) {
 868                 int reg = PIPECONF(pipe);
 869
 870                 /* Wait for the Pipe State to go off */
 871                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 872                              100))
 873                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 874         } else {
 875                 u32 last_line;
 876                 int reg = PIPEDSL(pipe);
 877                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 878
 879                 /* Wait for the display line to settle */
 880                 do {
 881                         last_line = I915_READ(reg) & DSL_LINEMASK;
 882                         mdelay(5);
 883                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 884                          time_after(timeout, jiffies));
 885                 if (time_after(jiffies, timeout))
 886                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 887         }
 888 }
 889
 890 static const char *state_string(bool enabled)
 891 {
 892         return enabled ? "on" : "off";
 893 }
 894
 895 /* Only for pre-ILK configs */
 896 static void assert_pll(struct drm_i915_private *dev_priv,
 897                        enum pipe pipe, bool state)
 898 {
 899         int reg;
 900         u32 val;
 901         bool cur_state;
 902
 903         reg = DPLL(pipe);
 904         val = I915_READ(reg);
 905         cur_state = !!(val & DPLL_VCO_ENABLE);
 906         WARN(cur_state != state,
 907              "PLL state assertion failure (expected %s, current %s)\n",
 908              state_string(state), state_string(cur_state));
 909 }
 910 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 911 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 912
 913 /* For ILK+ */
 914 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 915                            enum pipe pipe, bool state)
 916 {
 917         int reg;
 918         u32 val;
 919         bool cur_state;
 920
 921         if (HAS_PCH_CPT(dev_priv->dev)) {
 922                 u32 pch_dpll;
 923
 924                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 925
 926                 /* Make sure the selected PLL is enabled to the transcoder */
 927                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 928                      "transcoder %d PLL not enabled\n", pipe);
 929
 930                 /* Convert the transcoder pipe number to a pll pipe number */
 931                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 932         }
 933
 934         reg = PCH_DPLL(pipe);
 935         val = I915_READ(reg);
 936         cur_state = !!(val & DPLL_VCO_ENABLE);
 937         WARN(cur_state != state,
 938              "PCH PLL state assertion failure (expected %s, current %s)\n",
 939              state_string(state), state_string(cur_state));
 940 }
 941 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 942 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 943
 944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 945                           enum pipe pipe, bool state)
 946 {
 947         int reg;
 948         u32 val;
 949         bool cur_state;
 950
 951         reg = FDI_TX_CTL(pipe);
 952         val = I915_READ(reg);
 953         cur_state = !!(val & FDI_TX_ENABLE);
 954         WARN(cur_state != state,
 955              "FDI TX state assertion failure (expected %s, current %s)\n",
 956              state_string(state), state_string(cur_state));
 957 }
 958 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 959 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 960
 961 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 962                           enum pipe pipe, bool state)
 963 {
 964         int reg;
 965         u32 val;
 966         bool cur_state;
 967
 968         reg = FDI_RX_CTL(pipe);
 969         val = I915_READ(reg);
 970         cur_state = !!(val & FDI_RX_ENABLE);
 971         WARN(cur_state != state,
 972              "FDI RX state assertion failure (expected %s, current %s)\n",
 973              state_string(state), state_string(cur_state));
 974 }
 975 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 976 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 977
 978 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 979                                       enum pipe pipe)
 980 {
 981         int reg;
 982         u32 val;
 983
 984         /* ILK FDI PLL is always enabled */
 985         if (dev_priv->info->gen == 5)
 986                 return;
 987
 988         reg = FDI_TX_CTL(pipe);
 989         val = I915_READ(reg);
 990         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 991 }
 992
 993 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 994                                       enum pipe pipe)
 995 {
 996         int reg;
 997         u32 val;
 998
 999         reg = FDI_RX_CTL(pipe);
1000         val = I915_READ(reg);
1001         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002 }
1003
1004 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005                                   enum pipe pipe)
1006 {
1007         int pp_reg, lvds_reg;
1008         u32 val;
1009         enum pipe panel_pipe = PIPE_A;
1010         bool locked = true;
1011
1012         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013                 pp_reg = PCH_PP_CONTROL;
1014                 lvds_reg = PCH_LVDS;
1015         } else {
1016                 pp_reg = PP_CONTROL;
1017                 lvds_reg = LVDS;
1018         }
1019
1020         val = I915_READ(pp_reg);
1021         if (!(val & PANEL_POWER_ON) ||
1022             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023                 locked = false;
1024
1025         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026                 panel_pipe = PIPE_B;
1027
1028         WARN(panel_pipe == pipe && locked,
1029              "panel assertion failure, pipe %c regs locked\n",
1030              pipe_name(pipe));
1031 }
1032
1033 void assert_pipe(struct drm_i915_private *dev_priv,
1034                  enum pipe pipe, bool state)
1035 {
1036         int reg;
1037         u32 val;
1038         bool cur_state;
1039
1040         /* if we need the pipe A quirk it must be always on */
1041         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042                 state = true;
1043
1044         reg = PIPECONF(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & PIPECONF_ENABLE);
1047         WARN(cur_state != state,
1048              "pipe %c assertion failure (expected %s, current %s)\n",
1049              pipe_name(pipe), state_string(state), state_string(cur_state));
1050 }
1051
1052 static void assert_plane(struct drm_i915_private *dev_priv,
1053                          enum plane plane, bool state)
1054 {
1055         int reg;
1056         u32 val;
1057         bool cur_state;
1058
1059         reg = DSPCNTR(plane);
1060         val = I915_READ(reg);
1061         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062         WARN(cur_state != state,
1063              "plane %c assertion failure (expected %s, current %s)\n",
1064              plane_name(plane), state_string(state), state_string(cur_state));
1065 }
1066
1067 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
1070 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071                                    enum pipe pipe)
1072 {
1073         int reg, i;
1074         u32 val;
1075         int cur_pipe;
1076
1077         /* Planes are fixed to pipes on ILK+ */
1078         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079                 reg = DSPCNTR(pipe);
1080                 val = I915_READ(reg);
1081                 WARN((val & DISPLAY_PLANE_ENABLE),
1082                      "plane %c assertion failure, should be disabled but not\n",
1083                      plane_name(pipe));
1084                 return;
1085         }
1086
1087         /* Need to check both planes against the pipe */
1088         for (i = 0; i < 2; i++) {
1089                 reg = DSPCNTR(i);
1090                 val = I915_READ(reg);
1091                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092                         DISPPLANE_SEL_PIPE_SHIFT;
1093                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1094                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095                      plane_name(i), pipe_name(pipe));
1096         }
1097 }
1098
1099 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100 {
1101         u32 val;
1102         bool enabled;
1103
1104         val = I915_READ(PCH_DREF_CONTROL);
1105         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106                             DREF_SUPERSPREAD_SOURCE_MASK));
1107         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108 }
1109
1110 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111                                        enum pipe pipe)
1112 {
1113         int reg;
1114         u32 val;
1115         bool enabled;
1116
1117         reg = TRANSCONF(pipe);
1118         val = I915_READ(reg);
1119         enabled = !!(val & TRANS_ENABLE);
1120         WARN(enabled,
1121              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122              pipe_name(pipe));
1123 }
1124
1125 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126                             enum pipe pipe, u32 port_sel, u32 val)
1127 {
1128         if ((val & DP_PORT_EN) == 0)
1129                 return false;
1130
1131         if (HAS_PCH_CPT(dev_priv->dev)) {
1132                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135                         return false;
1136         } else {
1137                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138                         return false;
1139         }
1140         return true;
1141 }
1142
1143 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144                               enum pipe pipe, u32 val)
1145 {
1146         if ((val & PORT_ENABLE) == 0)
1147                 return false;
1148
1149         if (HAS_PCH_CPT(dev_priv->dev)) {
1150                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151                         return false;
1152         } else {
1153                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154                         return false;
1155         }
1156         return true;
1157 }
1158
1159 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160                               enum pipe pipe, u32 val)
1161 {
1162         if ((val & LVDS_PORT_EN) == 0)
1163                 return false;
1164
1165         if (HAS_PCH_CPT(dev_priv->dev)) {
1166                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167                         return false;
1168         } else {
1169                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170                         return false;
1171         }
1172         return true;
1173 }
1174
1175 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176                               enum pipe pipe, u32 val)
1177 {
1178         if ((val & ADPA_DAC_ENABLE) == 0)
1179                 return false;
1180         if (HAS_PCH_CPT(dev_priv->dev)) {
1181                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182                         return false;
1183         } else {
1184                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185                         return false;
1186         }
1187         return true;
1188 }
1189
1190 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1191                                    enum pipe pipe, int reg, u32 port_sel)
1192 {
1193         u32 val = I915_READ(reg);
1194         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1195              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1196              reg, pipe_name(pipe));
1197 }
1198
1199 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200                                      enum pipe pipe, int reg)
1201 {
1202         u32 val = I915_READ(reg);
1203         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1204              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1205              reg, pipe_name(pipe));
1206 }
1207
1208 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209                                       enum pipe pipe)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1217
1218         reg = PCH_ADPA;
1219         val = I915_READ(reg);
1220         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1221              "PCH VGA enabled on transcoder %c, should be disabled\n",
1222              pipe_name(pipe));
1223
1224         reg = PCH_LVDS;
1225         val = I915_READ(reg);
1226         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1227              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1228              pipe_name(pipe));
1229
1230         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233 }
1234
1235 /**
1236  * intel_enable_pll - enable a PLL
1237  * @dev_priv: i915 private structure
1238  * @pipe: pipe PLL to enable
1239  *
1240  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1241  * make sure the PLL reg is writable first though, since the panel write
1242  * protect mechanism may be enabled.
1243  *
1244  * Note!  This is for pre-ILK only.
1245  */
1246 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247 {
1248         int reg;
1249         u32 val;
1250
1251         /* No really, not for ILK+ */
1252         BUG_ON(dev_priv->info->gen >= 5);
1253
1254         /* PLL is protected by panel, make sure we can write it */
1255         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256                 assert_panel_unlocked(dev_priv, pipe);
1257
1258         reg = DPLL(pipe);
1259         val = I915_READ(reg);
1260         val |= DPLL_VCO_ENABLE;
1261
1262         /* We do this three times for luck */
1263         I915_WRITE(reg, val);
1264         POSTING_READ(reg);
1265         udelay(150); /* wait for warmup */
1266         I915_WRITE(reg, val);
1267         POSTING_READ(reg);
1268         udelay(150); /* wait for warmup */
1269         I915_WRITE(reg, val);
1270         POSTING_READ(reg);
1271         udelay(150); /* wait for warmup */
1272 }
1273
1274 /**
1275  * intel_disable_pll - disable a PLL
1276  * @dev_priv: i915 private structure
1277  * @pipe: pipe PLL to disable
1278  *
1279  * Disable the PLL for @pipe, making sure the pipe is off first.
1280  *
1281  * Note!  This is for pre-ILK only.
1282  */
1283 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284 {
1285         int reg;
1286         u32 val;
1287
1288         /* Don't disable pipe A or pipe A PLLs if needed */
1289         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290                 return;
1291
1292         /* Make sure the pipe isn't still relying on us */
1293         assert_pipe_disabled(dev_priv, pipe);
1294
1295         reg = DPLL(pipe);
1296         val = I915_READ(reg);
1297         val &= ~DPLL_VCO_ENABLE;
1298         I915_WRITE(reg, val);
1299         POSTING_READ(reg);
1300 }
1301
1302 /**
1303  * intel_enable_pch_pll - enable PCH PLL
1304  * @dev_priv: i915 private structure
1305  * @pipe: pipe PLL to enable
1306  *
1307  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1308  * drives the transcoder clock.
1309  */
1310 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1311                                  enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315
1316         if (pipe > 1)
1317                 return;
1318
1319         /* PCH only available on ILK+ */
1320         BUG_ON(dev_priv->info->gen < 5);
1321
1322         /* PCH refclock must be enabled first */
1323         assert_pch_refclk_enabled(dev_priv);
1324
1325         reg = PCH_DPLL(pipe);
1326         val = I915_READ(reg);
1327         val |= DPLL_VCO_ENABLE;
1328         I915_WRITE(reg, val);
1329         POSTING_READ(reg);
1330         udelay(200);
1331 }
1332
1333 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1334                                   enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1338                 pll_sel = TRANSC_DPLL_ENABLE;
1339
1340         if (pipe > 1)
1341                 return;
1342
1343         /* PCH only available on ILK+ */
1344         BUG_ON(dev_priv->info->gen < 5);
1345
1346         /* Make sure transcoder isn't still depending on us */
1347         assert_transcoder_disabled(dev_priv, pipe);
1348
1349         if (pipe == 0)
1350                 pll_sel |= TRANSC_DPLLA_SEL;
1351         else if (pipe == 1)
1352                 pll_sel |= TRANSC_DPLLB_SEL;
1353
1354
1355         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1356                 return;
1357
1358         reg = PCH_DPLL(pipe);
1359         val = I915_READ(reg);
1360         val &= ~DPLL_VCO_ENABLE;
1361         I915_WRITE(reg, val);
1362         POSTING_READ(reg);
1363         udelay(200);
1364 }
1365
1366 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1367                                     enum pipe pipe)
1368 {
1369         int reg;
1370         u32 val, pipeconf_val;
1371         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1372
1373         /* PCH only available on ILK+ */
1374         BUG_ON(dev_priv->info->gen < 5);
1375
1376         /* Make sure PCH DPLL is enabled */
1377         assert_pch_pll_enabled(dev_priv, pipe);
1378
1379         /* FDI must be feeding us bits for PCH ports */
1380         assert_fdi_tx_enabled(dev_priv, pipe);
1381         assert_fdi_rx_enabled(dev_priv, pipe);
1382
1383         reg = TRANSCONF(pipe);
1384         val = I915_READ(reg);
1385         pipeconf_val = I915_READ(PIPECONF(pipe));
1386
1387         if (HAS_PCH_IBX(dev_priv->dev)) {
1388                 /*
1389                  * make the BPC in transcoder be consistent with
1390                  * that in pipeconf reg.
1391                  */
1392                 val &= ~PIPE_BPC_MASK;
1393                 val |= pipeconf_val & PIPE_BPC_MASK;
1394         }
1395
1396         val &= ~TRANS_INTERLACE_MASK;
1397         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1398                 if (HAS_PCH_IBX(dev_priv->dev) &&
1399                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1400                         val |= TRANS_LEGACY_INTERLACED_ILK;
1401                 else
1402                         val |= TRANS_INTERLACED;
1403         else
1404                 val |= TRANS_PROGRESSIVE;
1405
1406         I915_WRITE(reg, val | TRANS_ENABLE);
1407         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1408                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1409 }
1410
1411 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1412                                      enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         /* FDI relies on the transcoder */
1418         assert_fdi_tx_disabled(dev_priv, pipe);
1419         assert_fdi_rx_disabled(dev_priv, pipe);
1420
1421         /* Ports must be off as well */
1422         assert_pch_ports_disabled(dev_priv, pipe);
1423
1424         reg = TRANSCONF(pipe);
1425         val = I915_READ(reg);
1426         val &= ~TRANS_ENABLE;
1427         I915_WRITE(reg, val);
1428         /* wait for PCH transcoder off, transcoder state */
1429         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1430                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1431 }
1432
1433 /**
1434  * intel_enable_pipe - enable a pipe, asserting requirements
1435  * @dev_priv: i915 private structure
1436  * @pipe: pipe to enable
1437  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1438  *
1439  * Enable @pipe, making sure that various hardware specific requirements
1440  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1441  *
1442  * @pipe should be %PIPE_A or %PIPE_B.
1443  *
1444  * Will wait until the pipe is actually running (i.e. first vblank) before
1445  * returning.
1446  */
1447 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1448                               bool pch_port)
1449 {
1450         int reg;
1451         u32 val;
1452
1453         /*
1454          * A pipe without a PLL won't actually be able to drive bits from
1455          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1456          * need the check.
1457          */
1458         if (!HAS_PCH_SPLIT(dev_priv->dev))
1459                 assert_pll_enabled(dev_priv, pipe);
1460         else {
1461                 if (pch_port) {
1462                         /* if driving the PCH, we need FDI enabled */
1463                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1464                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1465                 }
1466                 /* FIXME: assert CPU port conditions for SNB+ */
1467         }
1468
1469         reg = PIPECONF(pipe);
1470         val = I915_READ(reg);
1471         if (val & PIPECONF_ENABLE)
1472                 return;
1473
1474         I915_WRITE(reg, val | PIPECONF_ENABLE);
1475         intel_wait_for_vblank(dev_priv->dev, pipe);
1476 }
1477
1478 /**
1479  * intel_disable_pipe - disable a pipe, asserting requirements
1480  * @dev_priv: i915 private structure
1481  * @pipe: pipe to disable
1482  *
1483  * Disable @pipe, making sure that various hardware specific requirements
1484  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1485  *
1486  * @pipe should be %PIPE_A or %PIPE_B.
1487  *
1488  * Will wait until the pipe has shut down before returning.
1489  */
1490 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1491                                enum pipe pipe)
1492 {
1493         int reg;
1494         u32 val;
1495
1496         /*
1497          * Make sure planes won't keep trying to pump pixels to us,
1498          * or we might hang the display.
1499          */
1500         assert_planes_disabled(dev_priv, pipe);
1501
1502         /* Don't disable pipe A or pipe A PLLs if needed */
1503         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1504                 return;
1505
1506         reg = PIPECONF(pipe);
1507         val = I915_READ(reg);
1508         if ((val & PIPECONF_ENABLE) == 0)
1509                 return;
1510
1511         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1512         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1513 }
1514
1515 /*
1516  * Plane regs are double buffered, going from enabled->disabled needs a
1517  * trigger in order to latch.  The display address reg provides this.
1518  */
1519 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1520                                       enum plane plane)
1521 {
1522         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1523         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1524 }
1525
1526 /**
1527  * intel_enable_plane - enable a display plane on a given pipe
1528  * @dev_priv: i915 private structure
1529  * @plane: plane to enable
1530  * @pipe: pipe being fed
1531  *
1532  * Enable @plane on @pipe, making sure that @pipe is running first.
1533  */
1534 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1535                                enum plane plane, enum pipe pipe)
1536 {
1537         int reg;
1538         u32 val;
1539
1540         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1541         assert_pipe_enabled(dev_priv, pipe);
1542
1543         reg = DSPCNTR(plane);
1544         val = I915_READ(reg);
1545         if (val & DISPLAY_PLANE_ENABLE)
1546                 return;
1547
1548         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1549         intel_flush_display_plane(dev_priv, plane);
1550         intel_wait_for_vblank(dev_priv->dev, pipe);
1551 }
1552
1553 /**
1554  * intel_disable_plane - disable a display plane
1555  * @dev_priv: i915 private structure
1556  * @plane: plane to disable
1557  * @pipe: pipe consuming the data
1558  *
1559  * Disable @plane; should be an independent operation.
1560  */
1561 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1562                                 enum plane plane, enum pipe pipe)
1563 {
1564         int reg;
1565         u32 val;
1566
1567         reg = DSPCNTR(plane);
1568         val = I915_READ(reg);
1569         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1570                 return;
1571
1572         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1573         intel_flush_display_plane(dev_priv, plane);
1574         intel_wait_for_vblank(dev_priv->dev, pipe);
1575 }
1576
1577 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1578                            enum pipe pipe, int reg, u32 port_sel)
1579 {
1580         u32 val = I915_READ(reg);
1581         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1582                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1583                 I915_WRITE(reg, val & ~DP_PORT_EN);
1584         }
1585 }
1586
1587 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1588                              enum pipe pipe, int reg)
1589 {
1590         u32 val = I915_READ(reg);
1591         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1592                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1593                               reg, pipe);
1594                 I915_WRITE(reg, val & ~PORT_ENABLE);
1595         }
1596 }
1597
1598 /* Disable any ports connected to this transcoder */
1599 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1600                                     enum pipe pipe)
1601 {
1602         u32 reg, val;
1603
1604         val = I915_READ(PCH_PP_CONTROL);
1605         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1606
1607         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1608         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1609         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1610
1611         reg = PCH_ADPA;
1612         val = I915_READ(reg);
1613         if (adpa_pipe_enabled(dev_priv, val, pipe))
1614                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1615
1616         reg = PCH_LVDS;
1617         val = I915_READ(reg);
1618         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1619                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1620                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1621                 POSTING_READ(reg);
1622                 udelay(100);
1623         }
1624
1625         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1626         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1627         disable_pch_hdmi(dev_priv, pipe, HDMID);
1628 }
1629
1630 static void i8xx_disable_fbc(struct drm_device *dev)
1631 {
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633         u32 fbc_ctl;
1634
1635         /* Disable compression */
1636         fbc_ctl = I915_READ(FBC_CONTROL);
1637         if ((fbc_ctl & FBC_CTL_EN) == 0)
1638                 return;
1639
1640         fbc_ctl &= ~FBC_CTL_EN;
1641         I915_WRITE(FBC_CONTROL, fbc_ctl);
1642
1643         /* Wait for compressing bit to clear */
1644         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1645                 DRM_DEBUG_KMS("FBC idle timed out\n");
1646                 return;
1647         }
1648
1649         DRM_DEBUG_KMS("disabled FBC\n");
1650 }
1651
1652 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1653 {
1654         struct drm_device *dev = crtc->dev;
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         struct drm_framebuffer *fb = crtc->fb;
1657         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1658         struct drm_i915_gem_object *obj = intel_fb->obj;
1659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1660         int cfb_pitch;
1661         int plane, i;
1662         u32 fbc_ctl, fbc_ctl2;
1663
1664         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1665         if (fb->pitches[0] < cfb_pitch)
1666                 cfb_pitch = fb->pitches[0];
1667
1668         /* FBC_CTL wants 64B units */
1669         cfb_pitch = (cfb_pitch / 64) - 1;
1670         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1671
1672         /* Clear old tags */
1673         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1674                 I915_WRITE(FBC_TAG + (i * 4), 0);
1675
1676         /* Set it up... */
1677         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1678         fbc_ctl2 |= plane;
1679         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1680         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1681
1682         /* enable it... */
1683         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1684         if (IS_I945GM(dev))
1685                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1686         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1687         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1688         fbc_ctl |= obj->fence_reg;
1689         I915_WRITE(FBC_CONTROL, fbc_ctl);
1690
1691         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1692                       cfb_pitch, crtc->y, intel_crtc->plane);
1693 }
1694
1695 static bool i8xx_fbc_enabled(struct drm_device *dev)
1696 {
1697         struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1700 }
1701
1702 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1703 {
1704         struct drm_device *dev = crtc->dev;
1705         struct drm_i915_private *dev_priv = dev->dev_private;
1706         struct drm_framebuffer *fb = crtc->fb;
1707         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1708         struct drm_i915_gem_object *obj = intel_fb->obj;
1709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1710         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1711         unsigned long stall_watermark = 200;
1712         u32 dpfc_ctl;
1713
1714         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1715         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1716         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1717
1718         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1719                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1720                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1721         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1722
1723         /* enable it... */
1724         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1725
1726         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1727 }
1728
1729 static void g4x_disable_fbc(struct drm_device *dev)
1730 {
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         u32 dpfc_ctl;
1733
1734         /* Disable compression */
1735         dpfc_ctl = I915_READ(DPFC_CONTROL);
1736         if (dpfc_ctl & DPFC_CTL_EN) {
1737                 dpfc_ctl &= ~DPFC_CTL_EN;
1738                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1739
1740                 DRM_DEBUG_KMS("disabled FBC\n");
1741         }
1742 }
1743
1744 static bool g4x_fbc_enabled(struct drm_device *dev)
1745 {
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1749 }
1750
1751 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1752 {
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         u32 blt_ecoskpd;
1755
1756         /* Make sure blitter notifies FBC of writes */
1757         gen6_gt_force_wake_get(dev_priv);
1758         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1759         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1760                 GEN6_BLITTER_LOCK_SHIFT;
1761         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1762         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1763         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1764         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1765                          GEN6_BLITTER_LOCK_SHIFT);
1766         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1767         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1768         gen6_gt_force_wake_put(dev_priv);
1769 }
1770
1771 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1772 {
1773         struct drm_device *dev = crtc->dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct drm_framebuffer *fb = crtc->fb;
1776         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1777         struct drm_i915_gem_object *obj = intel_fb->obj;
1778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1779         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1780         unsigned long stall_watermark = 200;
1781         u32 dpfc_ctl;
1782
1783         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1784         dpfc_ctl &= DPFC_RESERVED;
1785         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1786         /* Set persistent mode for front-buffer rendering, ala X. */
1787         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1788         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1789         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1790
1791         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1792                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1793                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1794         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1795         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1796         /* enable it... */
1797         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1798
1799         if (IS_GEN6(dev)) {
1800                 I915_WRITE(SNB_DPFC_CTL_SA,
1801                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1802                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1803                 sandybridge_blit_fbc_update(dev);
1804         }
1805
1806         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1807 }
1808
1809 static void ironlake_disable_fbc(struct drm_device *dev)
1810 {
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         u32 dpfc_ctl;
1813
1814         /* Disable compression */
1815         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1816         if (dpfc_ctl & DPFC_CTL_EN) {
1817                 dpfc_ctl &= ~DPFC_CTL_EN;
1818                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1819
1820                 DRM_DEBUG_KMS("disabled FBC\n");
1821         }
1822 }
1823
1824 static bool ironlake_fbc_enabled(struct drm_device *dev)
1825 {
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827
1828         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1829 }
1830
1831 bool intel_fbc_enabled(struct drm_device *dev)
1832 {
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834
1835         if (!dev_priv->display.fbc_enabled)
1836                 return false;
1837
1838         return dev_priv->display.fbc_enabled(dev);
1839 }
1840
1841 static void intel_fbc_work_fn(struct work_struct *__work)
1842 {
1843         struct intel_fbc_work *work =
1844                 container_of(to_delayed_work(__work),
1845                              struct intel_fbc_work, work);
1846         struct drm_device *dev = work->crtc->dev;
1847         struct drm_i915_private *dev_priv = dev->dev_private;
1848
1849         mutex_lock(&dev->struct_mutex);
1850         if (work == dev_priv->fbc_work) {
1851                 /* Double check that we haven't switched fb without cancelling
1852                  * the prior work.
1853                  */
1854                 if (work->crtc->fb == work->fb) {
1855                         dev_priv->display.enable_fbc(work->crtc,
1856                                                      work->interval);
1857
1858                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1859                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1860                         dev_priv->cfb_y = work->crtc->y;
1861                 }
1862
1863                 dev_priv->fbc_work = NULL;
1864         }
1865         mutex_unlock(&dev->struct_mutex);
1866
1867         kfree(work);
1868 }
1869
1870 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1871 {
1872         if (dev_priv->fbc_work == NULL)
1873                 return;
1874
1875         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1876
1877         /* Synchronisation is provided by struct_mutex and checking of
1878          * dev_priv->fbc_work, so we can perform the cancellation
1879          * entirely asynchronously.
1880          */
1881         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1882                 /* tasklet was killed before being run, clean up */
1883                 kfree(dev_priv->fbc_work);
1884
1885         /* Mark the work as no longer wanted so that if it does
1886          * wake-up (because the work was already running and waiting
1887          * for our mutex), it will discover that is no longer
1888          * necessary to run.
1889          */
1890         dev_priv->fbc_work = NULL;
1891 }
1892
1893 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1894 {
1895         struct intel_fbc_work *work;
1896         struct drm_device *dev = crtc->dev;
1897         struct drm_i915_private *dev_priv = dev->dev_private;
1898
1899         if (!dev_priv->display.enable_fbc)
1900                 return;
1901
1902         intel_cancel_fbc_work(dev_priv);
1903
1904         work = kzalloc(sizeof *work, GFP_KERNEL);
1905         if (work == NULL) {
1906                 dev_priv->display.enable_fbc(crtc, interval);
1907                 return;
1908         }
1909
1910         work->crtc = crtc;
1911         work->fb = crtc->fb;
1912         work->interval = interval;
1913         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1914
1915         dev_priv->fbc_work = work;
1916
1917         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1918
1919         /* Delay the actual enabling to let pageflipping cease and the
1920          * display to settle before starting the compression. Note that
1921          * this delay also serves a second purpose: it allows for a
1922          * vblank to pass after disabling the FBC before we attempt
1923          * to modify the control registers.
1924          *
1925          * A more complicated solution would involve tracking vblanks
1926          * following the termination of the page-flipping sequence
1927          * and indeed performing the enable as a co-routine and not
1928          * waiting synchronously upon the vblank.
1929          */
1930         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1931 }
1932
1933 void intel_disable_fbc(struct drm_device *dev)
1934 {
1935         struct drm_i915_private *dev_priv = dev->dev_private;
1936
1937         intel_cancel_fbc_work(dev_priv);
1938
1939         if (!dev_priv->display.disable_fbc)
1940                 return;
1941
1942         dev_priv->display.disable_fbc(dev);
1943         dev_priv->cfb_plane = -1;
1944 }
1945
1946 /**
1947  * intel_update_fbc - enable/disable FBC as needed
1948  * @dev: the drm_device
1949  *
1950  * Set up the framebuffer compression hardware at mode set time.  We
1951  * enable it if possible:
1952  *   - plane A only (on pre-965)
1953  *   - no pixel mulitply/line duplication
1954  *   - no alpha buffer discard
1955  *   - no dual wide
1956  *   - framebuffer <= 2048 in width, 1536 in height
1957  *
1958  * We can't assume that any compression will take place (worst case),
1959  * so the compressed buffer has to be the same size as the uncompressed
1960  * one.  It also must reside (along with the line length buffer) in
1961  * stolen memory.
1962  *
1963  * We need to enable/disable FBC on a global basis.
1964  */
1965 static void intel_update_fbc(struct drm_device *dev)
1966 {
1967         struct drm_i915_private *dev_priv = dev->dev_private;
1968         struct drm_crtc *crtc = NULL, *tmp_crtc;
1969         struct intel_crtc *intel_crtc;
1970         struct drm_framebuffer *fb;
1971         struct intel_framebuffer *intel_fb;
1972         struct drm_i915_gem_object *obj;
1973         int enable_fbc;
1974
1975         DRM_DEBUG_KMS("\n");
1976
1977         if (!i915_powersave)
1978                 return;
1979
1980         if (!I915_HAS_FBC(dev))
1981                 return;
1982
1983         /*
1984          * If FBC is already on, we just have to verify that we can
1985          * keep it that way...
1986          * Need to disable if:
1987          *   - more than one pipe is active
1988          *   - changing FBC params (stride, fence, mode)
1989          *   - new fb is too large to fit in compressed buffer
1990          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1991          */
1992         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1993                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1994                         if (crtc) {
1995                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1996                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1997                                 goto out_disable;
1998                         }
1999                         crtc = tmp_crtc;
2000                 }
2001         }
2002
2003         if (!crtc || crtc->fb == NULL) {
2004                 DRM_DEBUG_KMS("no output, disabling\n");
2005                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2006                 goto out_disable;
2007         }
2008
2009         intel_crtc = to_intel_crtc(crtc);
2010         fb = crtc->fb;
2011         intel_fb = to_intel_framebuffer(fb);
2012         obj = intel_fb->obj;
2013
2014         enable_fbc = i915_enable_fbc;
2015         if (enable_fbc < 0) {
2016                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
2017                 enable_fbc = 1;
2018                 if (INTEL_INFO(dev)->gen <= 6)
2019                         enable_fbc = 0;
2020         }
2021         if (!enable_fbc) {
2022                 DRM_DEBUG_KMS("fbc disabled per module param\n");
2023                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
2024                 goto out_disable;
2025         }
2026         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2027                 DRM_DEBUG_KMS("framebuffer too large, disabling "
2028                               "compression\n");
2029                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2030                 goto out_disable;
2031         }
2032         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2033             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2034                 DRM_DEBUG_KMS("mode incompatible with compression, "
2035                               "disabling\n");
2036                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2037                 goto out_disable;
2038         }
2039         if ((crtc->mode.hdisplay > 2048) ||
2040             (crtc->mode.vdisplay > 1536)) {
2041                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2042                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2043                 goto out_disable;
2044         }
2045         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2046                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2047                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2048                 goto out_disable;
2049         }
2050
2051         /* The use of a CPU fence is mandatory in order to detect writes
2052          * by the CPU to the scanout and trigger updates to the FBC.
2053          */
2054         if (obj->tiling_mode != I915_TILING_X ||
2055             obj->fence_reg == I915_FENCE_REG_NONE) {
2056                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
2057                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2058                 goto out_disable;
2059         }
2060
2061         /* If the kernel debugger is active, always disable compression */
2062         if (in_dbg_master())
2063                 goto out_disable;
2064
2065         /* If the scanout has not changed, don't modify the FBC settings.
2066          * Note that we make the fundamental assumption that the fb->obj
2067          * cannot be unpinned (and have its GTT offset and fence revoked)
2068          * without first being decoupled from the scanout and FBC disabled.
2069          */
2070         if (dev_priv->cfb_plane == intel_crtc->plane &&
2071             dev_priv->cfb_fb == fb->base.id &&
2072             dev_priv->cfb_y == crtc->y)
2073                 return;
2074
2075         if (intel_fbc_enabled(dev)) {
2076                 /* We update FBC along two paths, after changing fb/crtc
2077                  * configuration (modeswitching) and after page-flipping
2078                  * finishes. For the latter, we know that not only did
2079                  * we disable the FBC at the start of the page-flip
2080                  * sequence, but also more than one vblank has passed.
2081                  *
2082                  * For the former case of modeswitching, it is possible
2083                  * to switch between two FBC valid configurations
2084                  * instantaneously so we do need to disable the FBC
2085                  * before we can modify its control registers. We also
2086                  * have to wait for the next vblank for that to take
2087                  * effect. However, since we delay enabling FBC we can
2088                  * assume that a vblank has passed since disabling and
2089                  * that we can safely alter the registers in the deferred
2090                  * callback.
2091                  *
2092                  * In the scenario that we go from a valid to invalid
2093                  * and then back to valid FBC configuration we have
2094                  * no strict enforcement that a vblank occurred since
2095                  * disabling the FBC. However, along all current pipe
2096                  * disabling paths we do need to wait for a vblank at
2097                  * some point. And we wait before enabling FBC anyway.
2098                  */
2099                 DRM_DEBUG_KMS("disabling active FBC for update\n");
2100                 intel_disable_fbc(dev);
2101         }
2102
2103         intel_enable_fbc(crtc, 500);
2104         return;
2105
2106 out_disable:
2107         /* Multiple disables should be harmless */
2108         if (intel_fbc_enabled(dev)) {
2109                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2110                 intel_disable_fbc(dev);
2111         }
2112 }
2113
2114 int
2115 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2116                            struct drm_i915_gem_object *obj,
2117                            struct intel_ring_buffer *pipelined)
2118 {
2119         struct drm_i915_private *dev_priv = dev->dev_private;
2120         u32 alignment;
2121         int ret;
2122
2123         switch (obj->tiling_mode) {
2124         case I915_TILING_NONE:
2125                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2126                         alignment = 128 * 1024;
2127                 else if (INTEL_INFO(dev)->gen >= 4)
2128                         alignment = 4 * 1024;
2129                 else
2130                         alignment = 64 * 1024;
2131                 break;
2132         case I915_TILING_X:
2133                 /* pin() will align the object as required by fence */
2134                 alignment = 0;
2135                 break;
2136         case I915_TILING_Y:
2137                 /* FIXME: Is this true? */
2138                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2139                 return -EINVAL;
2140         default:
2141                 BUG();
2142         }
2143
2144         dev_priv->mm.interruptible = false;
2145         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2146         if (ret)
2147                 goto err_interruptible;
2148
2149         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2150          * fence, whereas 965+ only requires a fence if using
2151          * framebuffer compression.  For simplicity, we always install
2152          * a fence as the cost is not that onerous.
2153          */
2154         ret = i915_gem_object_get_fence(obj, pipelined);
2155         if (ret)
2156                 goto err_unpin;
2157
2158         i915_gem_object_pin_fence(obj);
2159
2160         dev_priv->mm.interruptible = true;
2161         return 0;
2162
2163 err_unpin:
2164         i915_gem_object_unpin(obj);
2165 err_interruptible:
2166         dev_priv->mm.interruptible = true;
2167         return ret;
2168 }
2169
2170 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2171 {
2172         i915_gem_object_unpin_fence(obj);
2173         i915_gem_object_unpin(obj);
2174 }
2175
2176 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2177                              int x, int y)
2178 {
2179         struct drm_device *dev = crtc->dev;
2180         struct drm_i915_private *dev_priv = dev->dev_private;
2181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2182         struct intel_framebuffer *intel_fb;
2183         struct drm_i915_gem_object *obj;
2184         int plane = intel_crtc->plane;
2185         unsigned long Start, Offset;
2186         u32 dspcntr;
2187         u32 reg;
2188
2189         switch (plane) {
2190         case 0:
2191         case 1:
2192                 break;
2193         default:
2194                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195                 return -EINVAL;
2196         }
2197
2198         intel_fb = to_intel_framebuffer(fb);
2199         obj = intel_fb->obj;
2200
2201         reg = DSPCNTR(plane);
2202         dspcntr = I915_READ(reg);
2203         /* Mask out pixel format bits in case we change it */
2204         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2205         switch (fb->bits_per_pixel) {
2206         case 8:
2207                 dspcntr |= DISPPLANE_8BPP;
2208                 break;
2209         case 16:
2210                 if (fb->depth == 15)
2211                         dspcntr |= DISPPLANE_15_16BPP;
2212                 else
2213                         dspcntr |= DISPPLANE_16BPP;
2214                 break;
2215         case 24:
2216         case 32:
2217                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2218                 break;
2219         default:
2220                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2221                 return -EINVAL;
2222         }
2223         if (INTEL_INFO(dev)->gen >= 4) {
2224                 if (obj->tiling_mode != I915_TILING_NONE)
2225                         dspcntr |= DISPPLANE_TILED;
2226                 else
2227                         dspcntr &= ~DISPPLANE_TILED;
2228         }
2229
2230         I915_WRITE(reg, dspcntr);
2231
2232         Start = obj->gtt_offset;
2233         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2234
2235         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2236                       Start, Offset, x, y, fb->pitches[0]);
2237         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2238         if (INTEL_INFO(dev)->gen >= 4) {
2239                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
2240                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2241                 I915_WRITE(DSPADDR(plane), Offset);
2242         } else
2243                 I915_WRITE(DSPADDR(plane), Start + Offset);
2244         POSTING_READ(reg);
2245
2246         return 0;
2247 }
2248
2249 static int ironlake_update_plane(struct drm_crtc *crtc,
2250                                  struct drm_framebuffer *fb, int x, int y)
2251 {
2252         struct drm_device *dev = crtc->dev;
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2255         struct intel_framebuffer *intel_fb;
2256         struct drm_i915_gem_object *obj;
2257         int plane = intel_crtc->plane;
2258         unsigned long Start, Offset;
2259         u32 dspcntr;
2260         u32 reg;
2261
2262         switch (plane) {
2263         case 0:
2264         case 1:
2265         case 2:
2266                 break;
2267         default:
2268                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2269                 return -EINVAL;
2270         }
2271
2272         intel_fb = to_intel_framebuffer(fb);
2273         obj = intel_fb->obj;
2274
2275         reg = DSPCNTR(plane);
2276         dspcntr = I915_READ(reg);
2277         /* Mask out pixel format bits in case we change it */
2278         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2279         switch (fb->bits_per_pixel) {
2280         case 8:
2281                 dspcntr |= DISPPLANE_8BPP;
2282                 break;
2283         case 16:
2284                 if (fb->depth != 16)
2285                         return -EINVAL;
2286
2287                 dspcntr |= DISPPLANE_16BPP;
2288                 break;
2289         case 24:
2290         case 32:
2291                 if (fb->depth == 24)
2292                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2293                 else if (fb->depth == 30)
2294                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2295                 else
2296                         return -EINVAL;
2297                 break;
2298         default:
2299                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2300                 return -EINVAL;
2301         }
2302
2303         if (obj->tiling_mode != I915_TILING_NONE)
2304                 dspcntr |= DISPPLANE_TILED;
2305         else
2306                 dspcntr &= ~DISPPLANE_TILED;
2307
2308         /* must disable */
2309         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2310
2311         I915_WRITE(reg, dspcntr);
2312
2313         Start = obj->gtt_offset;
2314         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2315
2316         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2317                       Start, Offset, x, y, fb->pitches[0]);
2318         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2319         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
2320         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2321         I915_WRITE(DSPADDR(plane), Offset);
2322         POSTING_READ(reg);
2323
2324         return 0;
2325 }
2326
2327 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2328 static int
2329 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2330                            int x, int y, enum mode_set_atomic state)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         int ret;
2335
2336         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2337         if (ret)
2338                 return ret;
2339
2340         intel_update_fbc(dev);
2341         intel_increase_pllclock(crtc);
2342
2343         return 0;
2344 }
2345
2346 static int
2347 intel_finish_fb(struct drm_framebuffer *old_fb)
2348 {
2349         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2350         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2351         bool was_interruptible = dev_priv->mm.interruptible;
2352         int ret;
2353
2354         wait_event(dev_priv->pending_flip_queue,
2355                    atomic_read(&dev_priv->mm.wedged) ||
2356                    atomic_read(&obj->pending_flip) == 0);
2357
2358         /* Big Hammer, we also need to ensure that any pending
2359          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2360          * current scanout is retired before unpinning the old
2361          * framebuffer.
2362          *
2363          * This should only fail upon a hung GPU, in which case we
2364          * can safely continue.
2365          */
2366         dev_priv->mm.interruptible = false;
2367         ret = i915_gem_object_finish_gpu(obj);
2368         dev_priv->mm.interruptible = was_interruptible;
2369
2370         return ret;
2371 }
2372
2373 static int
2374 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2375                     struct drm_framebuffer *old_fb)
2376 {
2377         struct drm_device *dev = crtc->dev;
2378         struct drm_i915_master_private *master_priv;
2379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2380         int ret;
2381
2382         /* no fb bound */
2383         if (!crtc->fb) {
2384                 DRM_ERROR("No FB bound\n");
2385                 return 0;
2386         }
2387
2388         switch (intel_crtc->plane) {
2389         case 0:
2390         case 1:
2391                 break;
2392         case 2:
2393                 if (IS_IVYBRIDGE(dev))
2394                         break;
2395                 /* fall through otherwise */
2396         default:
2397                 DRM_ERROR("no plane for crtc\n");
2398                 return -EINVAL;
2399         }
2400
2401         mutex_lock(&dev->struct_mutex);
2402         ret = intel_pin_and_fence_fb_obj(dev,
2403                                          to_intel_framebuffer(crtc->fb)->obj,
2404                                          NULL);
2405         if (ret != 0) {
2406                 mutex_unlock(&dev->struct_mutex);
2407                 DRM_ERROR("pin & fence failed\n");
2408                 return ret;
2409         }
2410
2411         if (old_fb)
2412                 intel_finish_fb(old_fb);
2413
2414         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2415                                          LEAVE_ATOMIC_MODE_SET);
2416         if (ret) {
2417                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2418                 mutex_unlock(&dev->struct_mutex);
2419                 DRM_ERROR("failed to update base address\n");
2420                 return ret;
2421         }
2422
2423         if (old_fb) {
2424                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2425                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2426         }
2427
2428         mutex_unlock(&dev->struct_mutex);
2429
2430         if (!dev->primary->master)
2431                 return 0;
2432
2433         master_priv = dev->primary->master->driver_priv;
2434         if (!master_priv->sarea_priv)
2435                 return 0;
2436
2437         if (intel_crtc->pipe) {
2438                 master_priv->sarea_priv->pipeB_x = x;
2439                 master_priv->sarea_priv->pipeB_y = y;
2440         } else {
2441                 master_priv->sarea_priv->pipeA_x = x;
2442                 master_priv->sarea_priv->pipeA_y = y;
2443         }
2444
2445         return 0;
2446 }
2447
2448 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2449 {
2450         struct drm_device *dev = crtc->dev;
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452         u32 dpa_ctl;
2453
2454         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2455         dpa_ctl = I915_READ(DP_A);
2456         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2457
2458         if (clock < 200000) {
2459                 u32 temp;
2460                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2461                 /* workaround for 160Mhz:
2462                    1) program 0x4600c bits 15:0 = 0x8124
2463                    2) program 0x46010 bit 0 = 1
2464                    3) program 0x46034 bit 24 = 1
2465                    4) program 0x64000 bit 14 = 1
2466                    */
2467                 temp = I915_READ(0x4600c);
2468                 temp &= 0xffff0000;
2469                 I915_WRITE(0x4600c, temp | 0x8124);
2470
2471                 temp = I915_READ(0x46010);
2472                 I915_WRITE(0x46010, temp | 1);
2473
2474                 temp = I915_READ(0x46034);
2475                 I915_WRITE(0x46034, temp | (1 << 24));
2476         } else {
2477                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2478         }
2479         I915_WRITE(DP_A, dpa_ctl);
2480
2481         POSTING_READ(DP_A);
2482         udelay(500);
2483 }
2484
2485 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2486 {
2487         struct drm_device *dev = crtc->dev;
2488         struct drm_i915_private *dev_priv = dev->dev_private;
2489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490         int pipe = intel_crtc->pipe;
2491         u32 reg, temp;
2492
2493         /* enable normal train */
2494         reg = FDI_TX_CTL(pipe);
2495         temp = I915_READ(reg);
2496         if (IS_IVYBRIDGE(dev)) {
2497                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2498                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2499         } else {
2500                 temp &= ~FDI_LINK_TRAIN_NONE;
2501                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2502         }
2503         I915_WRITE(reg, temp);
2504
2505         reg = FDI_RX_CTL(pipe);
2506         temp = I915_READ(reg);
2507         if (HAS_PCH_CPT(dev)) {
2508                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2509                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2510         } else {
2511                 temp &= ~FDI_LINK_TRAIN_NONE;
2512                 temp |= FDI_LINK_TRAIN_NONE;
2513         }
2514         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2515
2516         /* wait one idle pattern time */
2517         POSTING_READ(reg);
2518         udelay(1000);
2519
2520         /* IVB wants error correction enabled */
2521         if (IS_IVYBRIDGE(dev))
2522                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2523                            FDI_FE_ERRC_ENABLE);
2524 }
2525
2526 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2527 {
2528         struct drm_i915_private *dev_priv = dev->dev_private;
2529         u32 flags = I915_READ(SOUTH_CHICKEN1);
2530
2531         flags |= FDI_PHASE_SYNC_OVR(pipe);
2532         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2533         flags |= FDI_PHASE_SYNC_EN(pipe);
2534         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2535         POSTING_READ(SOUTH_CHICKEN1);
2536 }
2537
2538 /* The FDI link training functions for ILK/Ibexpeak. */
2539 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2540 {
2541         struct drm_device *dev = crtc->dev;
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2544         int pipe = intel_crtc->pipe;
2545         int plane = intel_crtc->plane;
2546         u32 reg, temp, tries;
2547
2548         /* FDI needs bits from pipe & plane first */
2549         assert_pipe_enabled(dev_priv, pipe);
2550         assert_plane_enabled(dev_priv, plane);
2551
2552         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553            for train result */
2554         reg = FDI_RX_IMR(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~FDI_RX_SYMBOL_LOCK;
2557         temp &= ~FDI_RX_BIT_LOCK;
2558         I915_WRITE(reg, temp);
2559         I915_READ(reg);
2560         udelay(150);
2561
2562         /* enable CPU FDI TX and PCH FDI RX */
2563         reg = FDI_TX_CTL(pipe);
2564         temp = I915_READ(reg);
2565         temp &= ~(7 << 19);
2566         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2567         temp &= ~FDI_LINK_TRAIN_NONE;
2568         temp |= FDI_LINK_TRAIN_PATTERN_1;
2569         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2570
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~FDI_LINK_TRAIN_NONE;
2574         temp |= FDI_LINK_TRAIN_PATTERN_1;
2575         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2576
2577         POSTING_READ(reg);
2578         udelay(150);
2579
2580         /* Ironlake workaround, enable clock pointer after FDI enable*/
2581         if (HAS_PCH_IBX(dev)) {
2582                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2583                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2584                            FDI_RX_PHASE_SYNC_POINTER_EN);
2585         }
2586
2587         reg = FDI_RX_IIR(pipe);
2588         for (tries = 0; tries < 5; tries++) {
2589                 temp = I915_READ(reg);
2590                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2591
2592                 if ((temp & FDI_RX_BIT_LOCK)) {
2593                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2594                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2595                         break;
2596                 }
2597         }
2598         if (tries == 5)
2599                 DRM_ERROR("FDI train 1 fail!\n");
2600
2601         /* Train 2 */
2602         reg = FDI_TX_CTL(pipe);
2603         temp = I915_READ(reg);
2604         temp &= ~FDI_LINK_TRAIN_NONE;
2605         temp |= FDI_LINK_TRAIN_PATTERN_2;
2606         I915_WRITE(reg, temp);
2607
2608         reg = FDI_RX_CTL(pipe);
2609         temp = I915_READ(reg);
2610         temp &= ~FDI_LINK_TRAIN_NONE;
2611         temp |= FDI_LINK_TRAIN_PATTERN_2;
2612         I915_WRITE(reg, temp);
2613
2614         POSTING_READ(reg);
2615         udelay(150);
2616
2617         reg = FDI_RX_IIR(pipe);
2618         for (tries = 0; tries < 5; tries++) {
2619                 temp = I915_READ(reg);
2620                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621
2622                 if (temp & FDI_RX_SYMBOL_LOCK) {
2623                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2624                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2625                         break;
2626                 }
2627         }
2628         if (tries == 5)
2629                 DRM_ERROR("FDI train 2 fail!\n");
2630
2631         DRM_DEBUG_KMS("FDI train done\n");
2632
2633 }
2634
2635 static const int snb_b_fdi_train_param[] = {
2636         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2637         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2638         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2639         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2640 };
2641
2642 /* The FDI link training functions for SNB/Cougarpoint. */
2643 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2644 {
2645         struct drm_device *dev = crtc->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648         int pipe = intel_crtc->pipe;
2649         u32 reg, temp, i, retry;
2650
2651         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2652            for train result */
2653         reg = FDI_RX_IMR(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_RX_SYMBOL_LOCK;
2656         temp &= ~FDI_RX_BIT_LOCK;
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         /* enable CPU FDI TX and PCH FDI RX */
2663         reg = FDI_TX_CTL(pipe);
2664         temp = I915_READ(reg);
2665         temp &= ~(7 << 19);
2666         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2667         temp &= ~FDI_LINK_TRAIN_NONE;
2668         temp |= FDI_LINK_TRAIN_PATTERN_1;
2669         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2670         /* SNB-B */
2671         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2672         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2673
2674         reg = FDI_RX_CTL(pipe);
2675         temp = I915_READ(reg);
2676         if (HAS_PCH_CPT(dev)) {
2677                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2678                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2679         } else {
2680                 temp &= ~FDI_LINK_TRAIN_NONE;
2681                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2682         }
2683         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2684
2685         POSTING_READ(reg);
2686         udelay(150);
2687
2688         if (HAS_PCH_CPT(dev))
2689                 cpt_phase_pointer_enable(dev, pipe);
2690
2691         for (i = 0; i < 4; i++) {
2692                 reg = FDI_TX_CTL(pipe);
2693                 temp = I915_READ(reg);
2694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695                 temp |= snb_b_fdi_train_param[i];
2696                 I915_WRITE(reg, temp);
2697
2698                 POSTING_READ(reg);
2699                 udelay(500);
2700
2701                 for (retry = 0; retry < 5; retry++) {
2702                         reg = FDI_RX_IIR(pipe);
2703                         temp = I915_READ(reg);
2704                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705                         if (temp & FDI_RX_BIT_LOCK) {
2706                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2708                                 break;
2709                         }
2710                         udelay(50);
2711                 }
2712                 if (retry < 5)
2713                         break;
2714         }
2715         if (i == 4)
2716                 DRM_ERROR("FDI train 1 fail!\n");
2717
2718         /* Train 2 */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_NONE;
2722         temp |= FDI_LINK_TRAIN_PATTERN_2;
2723         if (IS_GEN6(dev)) {
2724                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725                 /* SNB-B */
2726                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727         }
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         if (HAS_PCH_CPT(dev)) {
2733                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2735         } else {
2736                 temp &= ~FDI_LINK_TRAIN_NONE;
2737                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2738         }
2739         I915_WRITE(reg, temp);
2740
2741         POSTING_READ(reg);
2742         udelay(150);
2743
2744         for (i = 0; i < 4; i++) {
2745                 reg = FDI_TX_CTL(pipe);
2746                 temp = I915_READ(reg);
2747                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2748                 temp |= snb_b_fdi_train_param[i];
2749                 I915_WRITE(reg, temp);
2750
2751                 POSTING_READ(reg);
2752                 udelay(500);
2753
2754                 for (retry = 0; retry < 5; retry++) {
2755                         reg = FDI_RX_IIR(pipe);
2756                         temp = I915_READ(reg);
2757                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758                         if (temp & FDI_RX_SYMBOL_LOCK) {
2759                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2760                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2761                                 break;
2762                         }
2763                         udelay(50);
2764                 }
2765                 if (retry < 5)
2766                         break;
2767         }
2768         if (i == 4)
2769                 DRM_ERROR("FDI train 2 fail!\n");
2770
2771         DRM_DEBUG_KMS("FDI train done.\n");
2772 }
2773
2774 /* Manual link training for Ivy Bridge A0 parts */
2775 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2776 {
2777         struct drm_device *dev = crtc->dev;
2778         struct drm_i915_private *dev_priv = dev->dev_private;
2779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780         int pipe = intel_crtc->pipe;
2781         u32 reg, temp, i;
2782
2783         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2784            for train result */
2785         reg = FDI_RX_IMR(pipe);
2786         temp = I915_READ(reg);
2787         temp &= ~FDI_RX_SYMBOL_LOCK;
2788         temp &= ~FDI_RX_BIT_LOCK;
2789         I915_WRITE(reg, temp);
2790
2791         POSTING_READ(reg);
2792         udelay(150);
2793
2794         /* enable CPU FDI TX and PCH FDI RX */
2795         reg = FDI_TX_CTL(pipe);
2796         temp = I915_READ(reg);
2797         temp &= ~(7 << 19);
2798         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2799         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2800         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2801         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2802         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2803         temp |= FDI_COMPOSITE_SYNC;
2804         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2805
2806         reg = FDI_RX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_LINK_TRAIN_AUTO;
2809         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2811         temp |= FDI_COMPOSITE_SYNC;
2812         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2813
2814         POSTING_READ(reg);
2815         udelay(150);
2816
2817         if (HAS_PCH_CPT(dev))
2818                 cpt_phase_pointer_enable(dev, pipe);
2819
2820         for (i = 0; i < 4; i++) {
2821                 reg = FDI_TX_CTL(pipe);
2822                 temp = I915_READ(reg);
2823                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2824                 temp |= snb_b_fdi_train_param[i];
2825                 I915_WRITE(reg, temp);
2826
2827                 POSTING_READ(reg);
2828                 udelay(500);
2829
2830                 reg = FDI_RX_IIR(pipe);
2831                 temp = I915_READ(reg);
2832                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2833
2834                 if (temp & FDI_RX_BIT_LOCK ||
2835                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2836                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2837                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2838                         break;
2839                 }
2840         }
2841         if (i == 4)
2842                 DRM_ERROR("FDI train 1 fail!\n");
2843
2844         /* Train 2 */
2845         reg = FDI_TX_CTL(pipe);
2846         temp = I915_READ(reg);
2847         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2848         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2849         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2850         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2851         I915_WRITE(reg, temp);
2852
2853         reg = FDI_RX_CTL(pipe);
2854         temp = I915_READ(reg);
2855         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2856         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2857         I915_WRITE(reg, temp);
2858
2859         POSTING_READ(reg);
2860         udelay(150);
2861
2862         for (i = 0; i < 4; i++) {
2863                 reg = FDI_TX_CTL(pipe);
2864                 temp = I915_READ(reg);
2865                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2866                 temp |= snb_b_fdi_train_param[i];
2867                 I915_WRITE(reg, temp);
2868
2869                 POSTING_READ(reg);
2870                 udelay(500);
2871
2872                 reg = FDI_RX_IIR(pipe);
2873                 temp = I915_READ(reg);
2874                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2875
2876                 if (temp & FDI_RX_SYMBOL_LOCK) {
2877                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2878                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2879                         break;
2880                 }
2881         }
2882         if (i == 4)
2883                 DRM_ERROR("FDI train 2 fail!\n");
2884
2885         DRM_DEBUG_KMS("FDI train done.\n");
2886 }
2887
2888 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2889 {
2890         struct drm_device *dev = crtc->dev;
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893         int pipe = intel_crtc->pipe;
2894         u32 reg, temp;
2895
2896         /* Write the TU size bits so error detection works */
2897         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2898                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2899
2900         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2901         reg = FDI_RX_CTL(pipe);
2902         temp = I915_READ(reg);
2903         temp &= ~((0x7 << 19) | (0x7 << 16));
2904         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2905         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2906         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2907
2908         POSTING_READ(reg);
2909         udelay(200);
2910
2911         /* Switch from Rawclk to PCDclk */
2912         temp = I915_READ(reg);
2913         I915_WRITE(reg, temp | FDI_PCDCLK);
2914
2915         POSTING_READ(reg);
2916         udelay(200);
2917
2918         /* Enable CPU FDI TX PLL, always on for Ironlake */
2919         reg = FDI_TX_CTL(pipe);
2920         temp = I915_READ(reg);
2921         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2922                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2923
2924                 POSTING_READ(reg);
2925                 udelay(100);
2926         }
2927 }
2928
2929 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2930 {
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932         u32 flags = I915_READ(SOUTH_CHICKEN1);
2933
2934         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2935         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2936         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2937         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2938         POSTING_READ(SOUTH_CHICKEN1);
2939 }
2940 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2941 {
2942         struct drm_device *dev = crtc->dev;
2943         struct drm_i915_private *dev_priv = dev->dev_private;
2944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945         int pipe = intel_crtc->pipe;
2946         u32 reg, temp;
2947
2948         /* disable CPU FDI tx and PCH FDI rx */
2949         reg = FDI_TX_CTL(pipe);
2950         temp = I915_READ(reg);
2951         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2952         POSTING_READ(reg);
2953
2954         reg = FDI_RX_CTL(pipe);
2955         temp = I915_READ(reg);
2956         temp &= ~(0x7 << 16);
2957         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2958         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2959
2960         POSTING_READ(reg);
2961         udelay(100);
2962
2963         /* Ironlake workaround, disable clock pointer after downing FDI */
2964         if (HAS_PCH_IBX(dev)) {
2965                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2966                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2967                            I915_READ(FDI_RX_CHICKEN(pipe) &
2968                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2969         } else if (HAS_PCH_CPT(dev)) {
2970                 cpt_phase_pointer_disable(dev, pipe);
2971         }
2972
2973         /* still set train pattern 1 */
2974         reg = FDI_TX_CTL(pipe);
2975         temp = I915_READ(reg);
2976         temp &= ~FDI_LINK_TRAIN_NONE;
2977         temp |= FDI_LINK_TRAIN_PATTERN_1;
2978         I915_WRITE(reg, temp);
2979
2980         reg = FDI_RX_CTL(pipe);
2981         temp = I915_READ(reg);
2982         if (HAS_PCH_CPT(dev)) {
2983                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2985         } else {
2986                 temp &= ~FDI_LINK_TRAIN_NONE;
2987                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2988         }
2989         /* BPC in FDI rx is consistent with that in PIPECONF */
2990         temp &= ~(0x07 << 16);
2991         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2992         I915_WRITE(reg, temp);
2993
2994         POSTING_READ(reg);
2995         udelay(100);
2996 }
2997
2998 /*
2999  * When we disable a pipe, we need to clear any pending scanline wait events
3000  * to avoid hanging the ring, which we assume we are waiting on.
3001  */
3002 static void intel_clear_scanline_wait(struct drm_device *dev)
3003 {
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         struct intel_ring_buffer *ring;
3006         u32 tmp;
3007
3008         if (IS_GEN2(dev))
3009                 /* Can't break the hang on i8xx */
3010                 return;
3011
3012         ring = LP_RING(dev_priv);
3013         tmp = I915_READ_CTL(ring);
3014         if (tmp & RING_WAIT)
3015                 I915_WRITE_CTL(ring, tmp);
3016 }
3017
3018 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3019 {
3020         struct drm_i915_gem_object *obj;
3021         struct drm_i915_private *dev_priv;
3022
3023         if (crtc->fb == NULL)
3024                 return;
3025
3026         obj = to_intel_framebuffer(crtc->fb)->obj;
3027         dev_priv = crtc->dev->dev_private;
3028         wait_event(dev_priv->pending_flip_queue,
3029                    atomic_read(&obj->pending_flip) == 0);
3030 }
3031
3032 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
3033 {
3034         struct drm_device *dev = crtc->dev;
3035         struct drm_mode_config *mode_config = &dev->mode_config;
3036         struct intel_encoder *encoder;
3037
3038         /*
3039          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3040          * must be driven by its own crtc; no sharing is possible.
3041          */
3042         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3043                 if (encoder->base.crtc != crtc)
3044                         continue;
3045
3046                 switch (encoder->type) {
3047                 case INTEL_OUTPUT_EDP:
3048                         if (!intel_encoder_is_pch_edp(&encoder->base))
3049                                 return false;
3050                         continue;
3051                 }
3052         }
3053
3054         return true;
3055 }
3056
3057 /*
3058  * Enable PCH resources required for PCH ports:
3059  *   - PCH PLLs
3060  *   - FDI training & RX/TX
3061  *   - update transcoder timings
3062  *   - DP transcoding bits
3063  *   - transcoder
3064  */
3065 static void ironlake_pch_enable(struct drm_crtc *crtc)
3066 {
3067         struct drm_device *dev = crtc->dev;
3068         struct drm_i915_private *dev_priv = dev->dev_private;
3069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3070         int pipe = intel_crtc->pipe;
3071         u32 reg, temp, transc_sel;
3072
3073         /* For PCH output, training FDI link */
3074         dev_priv->display.fdi_link_train(crtc);
3075
3076         intel_enable_pch_pll(dev_priv, pipe);
3077
3078         if (HAS_PCH_CPT(dev)) {
3079                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
3080                         TRANSC_DPLLB_SEL;
3081
3082                 /* Be sure PCH DPLL SEL is set */
3083                 temp = I915_READ(PCH_DPLL_SEL);
3084                 if (pipe == 0) {
3085                         temp &= ~(TRANSA_DPLLB_SEL);
3086                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3087                 } else if (pipe == 1) {
3088                         temp &= ~(TRANSB_DPLLB_SEL);
3089                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3090                 } else if (pipe == 2) {
3091                         temp &= ~(TRANSC_DPLLB_SEL);
3092                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
3093                 }
3094                 I915_WRITE(PCH_DPLL_SEL, temp);
3095         }
3096
3097         /* set transcoder timing, panel must allow it */
3098         assert_panel_unlocked(dev_priv, pipe);
3099         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3100         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3101         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3102
3103         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3104         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3105         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3106         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3107
3108         intel_fdi_normal_train(crtc);
3109
3110         /* For PCH DP, enable TRANS_DP_CTL */
3111         if (HAS_PCH_CPT(dev) &&
3112             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3113              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3114                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3115                 reg = TRANS_DP_CTL(pipe);
3116                 temp = I915_READ(reg);
3117                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3118                           TRANS_DP_SYNC_MASK |
3119                           TRANS_DP_BPC_MASK);
3120                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3121                          TRANS_DP_ENH_FRAMING);
3122                 temp |= bpc << 9; /* same format but at 11:9 */
3123
3124                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3125                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3126                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3127                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3128
3129                 switch (intel_trans_dp_port_sel(crtc)) {
3130                 case PCH_DP_B:
3131                         temp |= TRANS_DP_PORT_SEL_B;
3132                         break;
3133                 case PCH_DP_C:
3134                         temp |= TRANS_DP_PORT_SEL_C;
3135                         break;
3136                 case PCH_DP_D:
3137                         temp |= TRANS_DP_PORT_SEL_D;
3138                         break;
3139                 default:
3140                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3141                         temp |= TRANS_DP_PORT_SEL_B;
3142                         break;
3143                 }
3144
3145                 I915_WRITE(reg, temp);
3146         }
3147
3148         intel_enable_transcoder(dev_priv, pipe);
3149 }
3150
3151 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3152 {
3153         struct drm_i915_private *dev_priv = dev->dev_private;
3154         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3155         u32 temp;
3156
3157         temp = I915_READ(dslreg);
3158         udelay(500);
3159         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3160                 /* Without this, mode sets may fail silently on FDI */
3161                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3162                 udelay(250);
3163                 I915_WRITE(tc2reg, 0);
3164                 if (wait_for(I915_READ(dslreg) != temp, 5))
3165                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3166         }
3167 }
3168
3169 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174         int pipe = intel_crtc->pipe;
3175         int plane = intel_crtc->plane;
3176         u32 temp;
3177         bool is_pch_port;
3178
3179         if (intel_crtc->active)
3180                 return;
3181
3182         intel_crtc->active = true;
3183         intel_update_watermarks(dev);
3184
3185         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3186                 temp = I915_READ(PCH_LVDS);
3187                 if ((temp & LVDS_PORT_EN) == 0)
3188                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3189         }
3190
3191         is_pch_port = intel_crtc_driving_pch(crtc);
3192
3193         if (is_pch_port)
3194                 ironlake_fdi_pll_enable(crtc);
3195         else
3196                 ironlake_fdi_disable(crtc);
3197
3198         /* Enable panel fitting for LVDS */
3199         if (dev_priv->pch_pf_size &&
3200             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3201                 /* Force use of hard-coded filter coefficients
3202                  * as some pre-programmed values are broken,
3203                  * e.g. x201.
3204                  */
3205                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3206                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3207                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3208         }
3209
3210         /*
3211          * On ILK+ LUT must be loaded before the pipe is running but with
3212          * clocks enabled
3213          */
3214         intel_crtc_load_lut(crtc);
3215
3216         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3217         intel_enable_plane(dev_priv, plane, pipe);
3218
3219         if (is_pch_port)
3220                 ironlake_pch_enable(crtc);
3221
3222         mutex_lock(&dev->struct_mutex);
3223         intel_update_fbc(dev);
3224         mutex_unlock(&dev->struct_mutex);
3225
3226         intel_crtc_update_cursor(crtc, true);
3227 }
3228
3229 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3230 {
3231         struct drm_device *dev = crtc->dev;
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3234         int pipe = intel_crtc->pipe;
3235         int plane = intel_crtc->plane;
3236         u32 reg, temp;
3237
3238         if (!intel_crtc->active)
3239                 return;
3240
3241         intel_crtc_wait_for_pending_flips(crtc);
3242         drm_vblank_off(dev, pipe);
3243         intel_crtc_update_cursor(crtc, false);
3244
3245         intel_disable_plane(dev_priv, plane, pipe);
3246
3247         if (dev_priv->cfb_plane == plane)
3248                 intel_disable_fbc(dev);
3249
3250         intel_disable_pipe(dev_priv, pipe);
3251
3252         /* Disable PF */
3253         I915_WRITE(PF_CTL(pipe), 0);
3254         I915_WRITE(PF_WIN_SZ(pipe), 0);
3255
3256         ironlake_fdi_disable(crtc);
3257
3258         /* This is a horrible layering violation; we should be doing this in
3259          * the connector/encoder ->prepare instead, but we don't always have
3260          * enough information there about the config to know whether it will
3261          * actually be necessary or just cause undesired flicker.
3262          */
3263         intel_disable_pch_ports(dev_priv, pipe);
3264
3265         intel_disable_transcoder(dev_priv, pipe);
3266
3267         if (HAS_PCH_CPT(dev)) {
3268                 /* disable TRANS_DP_CTL */
3269                 reg = TRANS_DP_CTL(pipe);
3270                 temp = I915_READ(reg);
3271                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3272                 temp |= TRANS_DP_PORT_SEL_NONE;
3273                 I915_WRITE(reg, temp);
3274
3275                 /* disable DPLL_SEL */
3276                 temp = I915_READ(PCH_DPLL_SEL);
3277                 switch (pipe) {
3278                 case 0:
3279                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3280                         break;
3281                 case 1:
3282                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3283                         break;
3284                 case 2:
3285                         /* C shares PLL A or B */
3286                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3287                         break;
3288                 default:
3289                         BUG(); /* wtf */
3290                 }
3291                 I915_WRITE(PCH_DPLL_SEL, temp);
3292         }
3293
3294         /* disable PCH DPLL */
3295         if (!intel_crtc->no_pll)
3296                 intel_disable_pch_pll(dev_priv, pipe);
3297
3298         /* Switch from PCDclk to Rawclk */
3299         reg = FDI_RX_CTL(pipe);
3300         temp = I915_READ(reg);
3301         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3302
3303         /* Disable CPU FDI TX PLL */
3304         reg = FDI_TX_CTL(pipe);
3305         temp = I915_READ(reg);
3306         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3307
3308         POSTING_READ(reg);
3309         udelay(100);
3310
3311         reg = FDI_RX_CTL(pipe);
3312         temp = I915_READ(reg);
3313         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3314
3315         /* Wait for the clocks to turn off. */
3316         POSTING_READ(reg);
3317         udelay(100);
3318
3319         intel_crtc->active = false;
3320         intel_update_watermarks(dev);
3321
3322         mutex_lock(&dev->struct_mutex);
3323         intel_update_fbc(dev);
3324         intel_clear_scanline_wait(dev);
3325         mutex_unlock(&dev->struct_mutex);
3326 }
3327
3328 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3329 {
3330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331         int pipe = intel_crtc->pipe;
3332         int plane = intel_crtc->plane;
3333
3334         /* XXX: When our outputs are all unaware of DPMS modes other than off
3335          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3336          */
3337         switch (mode) {
3338         case DRM_MODE_DPMS_ON:
3339         case DRM_MODE_DPMS_STANDBY:
3340         case DRM_MODE_DPMS_SUSPEND:
3341                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3342                 ironlake_crtc_enable(crtc);
3343                 break;
3344
3345         case DRM_MODE_DPMS_OFF:
3346                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3347                 ironlake_crtc_disable(crtc);
3348                 break;
3349         }
3350 }
3351
3352 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3353 {
3354         if (!enable && intel_crtc->overlay) {
3355                 struct drm_device *dev = intel_crtc->base.dev;
3356                 struct drm_i915_private *dev_priv = dev->dev_private;
3357
3358                 mutex_lock(&dev->struct_mutex);
3359                 dev_priv->mm.interruptible = false;
3360                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3361                 dev_priv->mm.interruptible = true;
3362                 mutex_unlock(&dev->struct_mutex);
3363         }
3364
3365         /* Let userspace switch the overlay on again. In most cases userspace
3366          * has to recompute where to put it anyway.
3367          */
3368 }
3369
3370 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3371 {
3372         struct drm_device *dev = crtc->dev;
3373         struct drm_i915_private *dev_priv = dev->dev_private;
3374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375         int pipe = intel_crtc->pipe;
3376         int plane = intel_crtc->plane;
3377
3378         if (intel_crtc->active)
3379                 return;
3380
3381         intel_crtc->active = true;
3382         intel_update_watermarks(dev);
3383
3384         intel_enable_pll(dev_priv, pipe);
3385         intel_enable_pipe(dev_priv, pipe, false);
3386         intel_enable_plane(dev_priv, plane, pipe);
3387
3388         intel_crtc_load_lut(crtc);
3389         intel_update_fbc(dev);
3390
3391         /* Give the overlay scaler a chance to enable if it's on this pipe */
3392         intel_crtc_dpms_overlay(intel_crtc, true);
3393         intel_crtc_update_cursor(crtc, true);
3394 }
3395
3396 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3397 {
3398         struct drm_device *dev = crtc->dev;
3399         struct drm_i915_private *dev_priv = dev->dev_private;
3400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3401         int pipe = intel_crtc->pipe;
3402         int plane = intel_crtc->plane;
3403
3404         if (!intel_crtc->active)
3405                 return;
3406
3407         /* Give the overlay scaler a chance to disable if it's on this pipe */
3408         intel_crtc_wait_for_pending_flips(crtc);
3409         drm_vblank_off(dev, pipe);
3410         intel_crtc_dpms_overlay(intel_crtc, false);
3411         intel_crtc_update_cursor(crtc, false);
3412
3413         if (dev_priv->cfb_plane == plane)
3414                 intel_disable_fbc(dev);
3415
3416         intel_disable_plane(dev_priv, plane, pipe);
3417         intel_disable_pipe(dev_priv, pipe);
3418         intel_disable_pll(dev_priv, pipe);
3419
3420         intel_crtc->active = false;
3421         intel_update_fbc(dev);
3422         intel_update_watermarks(dev);
3423         intel_clear_scanline_wait(dev);
3424 }
3425
3426 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3427 {
3428         /* XXX: When our outputs are all unaware of DPMS modes other than off
3429          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3430          */
3431         switch (mode) {
3432         case DRM_MODE_DPMS_ON:
3433         case DRM_MODE_DPMS_STANDBY:
3434         case DRM_MODE_DPMS_SUSPEND:
3435                 i9xx_crtc_enable(crtc);
3436                 break;
3437         case DRM_MODE_DPMS_OFF:
3438                 i9xx_crtc_disable(crtc);
3439                 break;
3440         }
3441 }
3442
3443 /**
3444  * Sets the power management mode of the pipe and plane.
3445  */
3446 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3447 {
3448         struct drm_device *dev = crtc->dev;
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450         struct drm_i915_master_private *master_priv;
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         int pipe = intel_crtc->pipe;
3453         bool enabled;
3454
3455         if (intel_crtc->dpms_mode == mode)
3456                 return;
3457
3458         intel_crtc->dpms_mode = mode;
3459
3460         dev_priv->display.dpms(crtc, mode);
3461
3462         if (!dev->primary->master)
3463                 return;
3464
3465         master_priv = dev->primary->master->driver_priv;
3466         if (!master_priv->sarea_priv)
3467                 return;
3468
3469         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3470
3471         switch (pipe) {
3472         case 0:
3473                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3474                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3475                 break;
3476         case 1:
3477                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3478                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3479                 break;
3480         default:
3481                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3482                 break;
3483         }
3484 }
3485
3486 static void intel_crtc_disable(struct drm_crtc *crtc)
3487 {
3488         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3489         struct drm_device *dev = crtc->dev;
3490
3491         /* Flush any pending WAITs before we disable the pipe. Note that
3492          * we need to drop the struct_mutex in order to acquire it again
3493          * during the lowlevel dpms routines around a couple of the
3494          * operations. It does not look trivial nor desirable to move
3495          * that locking higher. So instead we leave a window for the
3496          * submission of further commands on the fb before we can actually
3497          * disable it. This race with userspace exists anyway, and we can
3498          * only rely on the pipe being disabled by userspace after it
3499          * receives the hotplug notification and has flushed any pending
3500          * batches.
3501          */
3502         if (crtc->fb) {
3503                 mutex_lock(&dev->struct_mutex);
3504                 intel_finish_fb(crtc->fb);
3505                 mutex_unlock(&dev->struct_mutex);
3506         }
3507
3508         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3509         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3510         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3511
3512         if (crtc->fb) {
3513                 mutex_lock(&dev->struct_mutex);
3514                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3515                 mutex_unlock(&dev->struct_mutex);
3516         }
3517 }
3518
3519 /* Prepare for a mode set.
3520  *
3521  * Note we could be a lot smarter here.  We need to figure out which outputs
3522  * will be enabled, which disabled (in short, how the config will changes)
3523  * and perform the minimum necessary steps to accomplish that, e.g. updating
3524  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3525  * panel fitting is in the proper state, etc.
3526  */
3527 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3528 {
3529         i9xx_crtc_disable(crtc);
3530 }
3531
3532 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3533 {
3534         i9xx_crtc_enable(crtc);
3535 }
3536
3537 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3538 {
3539         ironlake_crtc_disable(crtc);
3540 }
3541
3542 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3543 {
3544         ironlake_crtc_enable(crtc);
3545 }
3546
3547 void intel_encoder_prepare(struct drm_encoder *encoder)
3548 {
3549         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3550         /* lvds has its own version of prepare see intel_lvds_prepare */
3551         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3552 }
3553
3554 void intel_encoder_commit(struct drm_encoder *encoder)
3555 {
3556         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3557         struct drm_device *dev = encoder->dev;
3558         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3559         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3560
3561         /* lvds has its own version of commit see intel_lvds_commit */
3562         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3563
3564         if (HAS_PCH_CPT(dev))
3565                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3566 }
3567
3568 void intel_encoder_destroy(struct drm_encoder *encoder)
3569 {
3570         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3571
3572         drm_encoder_cleanup(encoder);
3573         kfree(intel_encoder);
3574 }
3575
3576 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3577                                   struct drm_display_mode *mode,
3578                                   struct drm_display_mode *adjusted_mode)
3579 {
3580         struct drm_device *dev = crtc->dev;
3581
3582         if (HAS_PCH_SPLIT(dev)) {
3583                 /* FDI link clock is fixed at 2.7G */
3584                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3585                         return false;
3586         }
3587
3588         /* All interlaced capable intel hw wants timings in frames. */
3589         drm_mode_set_crtcinfo(adjusted_mode, 0);
3590
3591         return true;
3592 }
3593
3594 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3595 {
3596         return 400000; /* FIXME */
3597 }
3598
3599 static int i945_get_display_clock_speed(struct drm_device *dev)
3600 {
3601         return 400000;
3602 }
3603
3604 static int i915_get_display_clock_speed(struct drm_device *dev)
3605 {
3606         return 333000;
3607 }
3608
3609 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3610 {
3611         return 200000;
3612 }
3613
3614 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3615 {
3616         u16 gcfgc = 0;
3617
3618         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3619
3620         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3621                 return 133000;
3622         else {
3623                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3624                 case GC_DISPLAY_CLOCK_333_MHZ:
3625                         return 333000;
3626                 default:
3627                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3628                         return 190000;
3629                 }
3630         }
3631 }
3632
3633 static int i865_get_display_clock_speed(struct drm_device *dev)
3634 {
3635         return 266000;
3636 }
3637
3638 static int i855_get_display_clock_speed(struct drm_device *dev)
3639 {
3640         u16 hpllcc = 0;
3641         /* Assume that the hardware is in the high speed state.  This
3642          * should be the default.
3643          */
3644         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3645         case GC_CLOCK_133_200:
3646         case GC_CLOCK_100_200:
3647                 return 200000;
3648         case GC_CLOCK_166_250:
3649                 return 250000;
3650         case GC_CLOCK_100_133:
3651                 return 133000;
3652         }
3653
3654         /* Shouldn't happen */
3655         return 0;
3656 }
3657
3658 static int i830_get_display_clock_speed(struct drm_device *dev)
3659 {
3660         return 133000;
3661 }
3662
3663 struct fdi_m_n {
3664         u32        tu;
3665         u32        gmch_m;
3666         u32        gmch_n;
3667         u32        link_m;
3668         u32        link_n;
3669 };
3670
3671 static void
3672 fdi_reduce_ratio(u32 *num, u32 *den)
3673 {
3674         while (*num > 0xffffff || *den > 0xffffff) {
3675                 *num >>= 1;
3676                 *den >>= 1;
3677         }
3678 }
3679
3680 static void
3681 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3682                      int link_clock, struct fdi_m_n *m_n)
3683 {
3684         m_n->tu = 64; /* default size */
3685
3686         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3687         m_n->gmch_m = bits_per_pixel * pixel_clock;
3688         m_n->gmch_n = link_clock * nlanes * 8;
3689         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3690
3691         m_n->link_m = pixel_clock;
3692         m_n->link_n = link_clock;
3693         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3694 }
3695
3696
3697 struct intel_watermark_params {
3698         unsigned long fifo_size;
3699         unsigned long max_wm;
3700         unsigned long default_wm;
3701         unsigned long guard_size;
3702         unsigned long cacheline_size;
3703 };
3704
3705 /* Pineview has different values for various configs */
3706 static const struct intel_watermark_params pineview_display_wm = {
3707         PINEVIEW_DISPLAY_FIFO,
3708         PINEVIEW_MAX_WM,
3709         PINEVIEW_DFT_WM,
3710         PINEVIEW_GUARD_WM,
3711         PINEVIEW_FIFO_LINE_SIZE
3712 };
3713 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3714         PINEVIEW_DISPLAY_FIFO,
3715         PINEVIEW_MAX_WM,
3716         PINEVIEW_DFT_HPLLOFF_WM,
3717         PINEVIEW_GUARD_WM,
3718         PINEVIEW_FIFO_LINE_SIZE
3719 };
3720 static const struct intel_watermark_params pineview_cursor_wm = {
3721         PINEVIEW_CURSOR_FIFO,
3722         PINEVIEW_CURSOR_MAX_WM,
3723         PINEVIEW_CURSOR_DFT_WM,
3724         PINEVIEW_CURSOR_GUARD_WM,
3725         PINEVIEW_FIFO_LINE_SIZE,
3726 };
3727 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3728         PINEVIEW_CURSOR_FIFO,
3729         PINEVIEW_CURSOR_MAX_WM,
3730         PINEVIEW_CURSOR_DFT_WM,
3731         PINEVIEW_CURSOR_GUARD_WM,
3732         PINEVIEW_FIFO_LINE_SIZE
3733 };
3734 static const struct intel_watermark_params g4x_wm_info = {
3735         G4X_FIFO_SIZE,
3736         G4X_MAX_WM,
3737         G4X_MAX_WM,
3738         2,
3739         G4X_FIFO_LINE_SIZE,
3740 };
3741 static const struct intel_watermark_params g4x_cursor_wm_info = {
3742         I965_CURSOR_FIFO,
3743         I965_CURSOR_MAX_WM,
3744         I965_CURSOR_DFT_WM,
3745         2,
3746         G4X_FIFO_LINE_SIZE,
3747 };
3748 static const struct intel_watermark_params valleyview_wm_info = {
3749         VALLEYVIEW_FIFO_SIZE,
3750         VALLEYVIEW_MAX_WM,
3751         VALLEYVIEW_MAX_WM,
3752         2,
3753         G4X_FIFO_LINE_SIZE,
3754 };
3755 static const struct intel_watermark_params valleyview_cursor_wm_info = {
3756         I965_CURSOR_FIFO,
3757         VALLEYVIEW_CURSOR_MAX_WM,
3758         I965_CURSOR_DFT_WM,
3759         2,
3760         G4X_FIFO_LINE_SIZE,
3761 };
3762 static const struct intel_watermark_params i965_cursor_wm_info = {
3763         I965_CURSOR_FIFO,
3764         I965_CURSOR_MAX_WM,
3765         I965_CURSOR_DFT_WM,
3766         2,
3767         I915_FIFO_LINE_SIZE,
3768 };
3769 static const struct intel_watermark_params i945_wm_info = {
3770         I945_FIFO_SIZE,
3771         I915_MAX_WM,
3772         1,
3773         2,
3774         I915_FIFO_LINE_SIZE
3775 };
3776 static const struct intel_watermark_params i915_wm_info = {
3777         I915_FIFO_SIZE,
3778         I915_MAX_WM,
3779         1,
3780         2,
3781         I915_FIFO_LINE_SIZE
3782 };
3783 static const struct intel_watermark_params i855_wm_info = {
3784         I855GM_FIFO_SIZE,
3785         I915_MAX_WM,
3786         1,
3787         2,
3788         I830_FIFO_LINE_SIZE
3789 };
3790 static const struct intel_watermark_params i830_wm_info = {
3791         I830_FIFO_SIZE,
3792         I915_MAX_WM,
3793         1,
3794         2,
3795         I830_FIFO_LINE_SIZE
3796 };
3797
3798 static const struct intel_watermark_params ironlake_display_wm_info = {
3799         ILK_DISPLAY_FIFO,
3800         ILK_DISPLAY_MAXWM,
3801         ILK_DISPLAY_DFTWM,
3802         2,
3803         ILK_FIFO_LINE_SIZE
3804 };
3805 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3806         ILK_CURSOR_FIFO,
3807         ILK_CURSOR_MAXWM,
3808         ILK_CURSOR_DFTWM,
3809         2,
3810         ILK_FIFO_LINE_SIZE
3811 };
3812 static const struct intel_watermark_params ironlake_display_srwm_info = {
3813         ILK_DISPLAY_SR_FIFO,
3814         ILK_DISPLAY_MAX_SRWM,
3815         ILK_DISPLAY_DFT_SRWM,
3816         2,
3817         ILK_FIFO_LINE_SIZE
3818 };
3819 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3820         ILK_CURSOR_SR_FIFO,
3821         ILK_CURSOR_MAX_SRWM,
3822         ILK_CURSOR_DFT_SRWM,
3823         2,
3824         ILK_FIFO_LINE_SIZE
3825 };
3826
3827 static const struct intel_watermark_params sandybridge_display_wm_info = {
3828         SNB_DISPLAY_FIFO,
3829         SNB_DISPLAY_MAXWM,
3830         SNB_DISPLAY_DFTWM,
3831         2,
3832         SNB_FIFO_LINE_SIZE
3833 };
3834 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3835         SNB_CURSOR_FIFO,
3836         SNB_CURSOR_MAXWM,
3837         SNB_CURSOR_DFTWM,
3838         2,
3839         SNB_FIFO_LINE_SIZE
3840 };
3841 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3842         SNB_DISPLAY_SR_FIFO,
3843         SNB_DISPLAY_MAX_SRWM,
3844         SNB_DISPLAY_DFT_SRWM,
3845         2,
3846         SNB_FIFO_LINE_SIZE
3847 };
3848 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3849         SNB_CURSOR_SR_FIFO,
3850         SNB_CURSOR_MAX_SRWM,
3851         SNB_CURSOR_DFT_SRWM,
3852         2,
3853         SNB_FIFO_LINE_SIZE
3854 };
3855
3856
3857 /**
3858  * intel_calculate_wm - calculate watermark level
3859  * @clock_in_khz: pixel clock
3860  * @wm: chip FIFO params
3861  * @pixel_size: display pixel size
3862  * @latency_ns: memory latency for the platform
3863  *
3864  * Calculate the watermark level (the level at which the display plane will
3865  * start fetching from memory again).  Each chip has a different display
3866  * FIFO size and allocation, so the caller needs to figure that out and pass
3867  * in the correct intel_watermark_params structure.
3868  *
3869  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3870  * on the pixel size.  When it reaches the watermark level, it'll start
3871  * fetching FIFO line sized based chunks from memory until the FIFO fills
3872  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3873  * will occur, and a display engine hang could result.
3874  */
3875 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3876                                         const struct intel_watermark_params *wm,
3877                                         int fifo_size,
3878                                         int pixel_size,
3879                                         unsigned long latency_ns)
3880 {
3881         long entries_required, wm_size;
3882
3883         /*
3884          * Note: we need to make sure we don't overflow for various clock &
3885          * latency values.
3886          * clocks go from a few thousand to several hundred thousand.
3887          * latency is usually a few thousand
3888          */
3889         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3890                 1000;
3891         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3892
3893         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3894
3895         wm_size = fifo_size - (entries_required + wm->guard_size);
3896
3897         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3898
3899         /* Don't promote wm_size to unsigned... */
3900         if (wm_size > (long)wm->max_wm)
3901                 wm_size = wm->max_wm;
3902         if (wm_size <= 0)
3903                 wm_size = wm->default_wm;
3904         return wm_size;
3905 }
3906
3907 struct cxsr_latency {
3908         int is_desktop;
3909         int is_ddr3;
3910         unsigned long fsb_freq;
3911         unsigned long mem_freq;
3912         unsigned long display_sr;
3913         unsigned long display_hpll_disable;
3914         unsigned long cursor_sr;
3915         unsigned long cursor_hpll_disable;
3916 };
3917
3918 static const struct cxsr_latency cxsr_latency_table[] = {
3919         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3920         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3921         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3922         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3923         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3924
3925         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3926         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3927         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3928         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3929         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3930
3931         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3932         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3933         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3934         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3935         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3936
3937         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3938         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3939         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3940         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3941         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3942
3943         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3944         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3945         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3946         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3947         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3948
3949         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3950         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3951         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3952         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3953         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3954 };
3955
3956 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3957                                                          int is_ddr3,
3958                                                          int fsb,
3959                                                          int mem)
3960 {
3961         const struct cxsr_latency *latency;
3962         int i;
3963
3964         if (fsb == 0 || mem == 0)
3965                 return NULL;
3966
3967         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3968                 latency = &cxsr_latency_table[i];
3969                 if (is_desktop == latency->is_desktop &&
3970                     is_ddr3 == latency->is_ddr3 &&
3971                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3972                         return latency;
3973         }
3974
3975         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3976
3977         return NULL;
3978 }
3979
3980 static void pineview_disable_cxsr(struct drm_device *dev)
3981 {
3982         struct drm_i915_private *dev_priv = dev->dev_private;
3983
3984         /* deactivate cxsr */
3985         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3986 }
3987
3988 /*
3989  * Latency for FIFO fetches is dependent on several factors:
3990  *   - memory configuration (speed, channels)
3991  *   - chipset
3992  *   - current MCH state
3993  * It can be fairly high in some situations, so here we assume a fairly
3994  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3995  * set this value too high, the FIFO will fetch frequently to stay full)
3996  * and power consumption (set it too low to save power and we might see
3997  * FIFO underruns and display "flicker").
3998  *
3999  * A value of 5us seems to be a good balance; safe for very low end
4000  * platforms but not overly aggressive on lower latency configs.
4001  */
4002 static const int latency_ns = 5000;
4003
4004 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
4005 {
4006         struct drm_i915_private *dev_priv = dev->dev_private;
4007         uint32_t dsparb = I915_READ(DSPARB);
4008         int size;
4009
4010         size = dsparb & 0x7f;
4011         if (plane)
4012                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
4013
4014         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4015                       plane ? "B" : "A", size);
4016
4017         return size;
4018 }
4019
4020 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
4021 {
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         uint32_t dsparb = I915_READ(DSPARB);
4024         int size;
4025
4026         size = dsparb & 0x1ff;
4027         if (plane)
4028                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
4029         size >>= 1; /* Convert to cachelines */
4030
4031         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4032                       plane ? "B" : "A", size);
4033
4034         return size;
4035 }
4036
4037 static int i845_get_fifo_size(struct drm_device *dev, int plane)
4038 {
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         uint32_t dsparb = I915_READ(DSPARB);
4041         int size;
4042
4043         size = dsparb & 0x7f;
4044         size >>= 2; /* Convert to cachelines */
4045
4046         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4047                       plane ? "B" : "A",
4048                       size);
4049
4050         return size;
4051 }
4052
4053 static int i830_get_fifo_size(struct drm_device *dev, int plane)
4054 {
4055         struct drm_i915_private *dev_priv = dev->dev_private;
4056         uint32_t dsparb = I915_READ(DSPARB);
4057         int size;
4058
4059         size = dsparb & 0x7f;
4060         size >>= 1; /* Convert to cachelines */
4061
4062         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
4063                       plane ? "B" : "A", size);
4064
4065         return size;
4066 }
4067
4068 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
4069 {
4070         struct drm_crtc *crtc, *enabled = NULL;
4071
4072         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4073                 if (crtc->enabled && crtc->fb) {
4074                         if (enabled)
4075                                 return NULL;
4076                         enabled = crtc;
4077                 }
4078         }
4079
4080         return enabled;
4081 }
4082
4083 static void pineview_update_wm(struct drm_device *dev)
4084 {
4085         struct drm_i915_private *dev_priv = dev->dev_private;
4086         struct drm_crtc *crtc;
4087         const struct cxsr_latency *latency;
4088         u32 reg;
4089         unsigned long wm;
4090
4091         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
4092                                          dev_priv->fsb_freq, dev_priv->mem_freq);
4093         if (!latency) {
4094                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
4095                 pineview_disable_cxsr(dev);
4096                 return;
4097         }
4098
4099         crtc = single_enabled_crtc(dev);
4100         if (crtc) {
4101                 int clock = crtc->mode.clock;
4102                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4103
4104                 /* Display SR */
4105                 wm = intel_calculate_wm(clock, &pineview_display_wm,
4106                                         pineview_display_wm.fifo_size,
4107                                         pixel_size, latency->display_sr);
4108                 reg = I915_READ(DSPFW1);
4109                 reg &= ~DSPFW_SR_MASK;
4110                 reg |= wm << DSPFW_SR_SHIFT;
4111                 I915_WRITE(DSPFW1, reg);
4112                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
4113
4114                 /* cursor SR */
4115                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
4116                                         pineview_display_wm.fifo_size,
4117                                         pixel_size, latency->cursor_sr);
4118                 reg = I915_READ(DSPFW3);
4119                 reg &= ~DSPFW_CURSOR_SR_MASK;
4120                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4121                 I915_WRITE(DSPFW3, reg);
4122
4123                 /* Display HPLL off SR */
4124                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4125                                         pineview_display_hplloff_wm.fifo_size,
4126                                         pixel_size, latency->display_hpll_disable);
4127                 reg = I915_READ(DSPFW3);
4128                 reg &= ~DSPFW_HPLL_SR_MASK;
4129                 reg |= wm & DSPFW_HPLL_SR_MASK;
4130                 I915_WRITE(DSPFW3, reg);
4131
4132                 /* cursor HPLL off SR */
4133                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4134                                         pineview_display_hplloff_wm.fifo_size,
4135                                         pixel_size, latency->cursor_hpll_disable);
4136                 reg = I915_READ(DSPFW3);
4137                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4138                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4139                 I915_WRITE(DSPFW3, reg);
4140                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4141
4142                 /* activate cxsr */
4143                 I915_WRITE(DSPFW3,
4144                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4145                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4146         } else {
4147                 pineview_disable_cxsr(dev);
4148                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4149         }
4150 }
4151
4152 static bool g4x_compute_wm0(struct drm_device *dev,
4153                             int plane,
4154                             const struct intel_watermark_params *display,
4155                             int display_latency_ns,
4156                             const struct intel_watermark_params *cursor,
4157                             int cursor_latency_ns,
4158                             int *plane_wm,
4159                             int *cursor_wm)
4160 {
4161         struct drm_crtc *crtc;
4162         int htotal, hdisplay, clock, pixel_size;
4163         int line_time_us, line_count;
4164         int entries, tlb_miss;
4165
4166         crtc = intel_get_crtc_for_plane(dev, plane);
4167         if (crtc->fb == NULL || !crtc->enabled) {
4168                 *cursor_wm = cursor->guard_size;
4169                 *plane_wm = display->guard_size;
4170                 return false;
4171         }
4172
4173         htotal = crtc->mode.htotal;
4174         hdisplay = crtc->mode.hdisplay;
4175         clock = crtc->mode.clock;
4176         pixel_size = crtc->fb->bits_per_pixel / 8;
4177
4178         /* Use the small buffer method to calculate plane watermark */
4179         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4180         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4181         if (tlb_miss > 0)
4182                 entries += tlb_miss;
4183         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4184         *plane_wm = entries + display->guard_size;
4185         if (*plane_wm > (int)display->max_wm)
4186                 *plane_wm = display->max_wm;
4187
4188         /* Use the large buffer method to calculate cursor watermark */
4189         line_time_us = ((htotal * 1000) / clock);
4190         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4191         entries = line_count * 64 * pixel_size;
4192         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4193         if (tlb_miss > 0)
4194                 entries += tlb_miss;
4195         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4196         *cursor_wm = entries + cursor->guard_size;
4197         if (*cursor_wm > (int)cursor->max_wm)
4198                 *cursor_wm = (int)cursor->max_wm;
4199
4200         return true;
4201 }
4202
4203 /*
4204  * Check the wm result.
4205  *
4206  * If any calculated watermark values is larger than the maximum value that
4207  * can be programmed into the associated watermark register, that watermark
4208  * must be disabled.
4209  */
4210 static bool g4x_check_srwm(struct drm_device *dev,
4211                            int display_wm, int cursor_wm,
4212                            const struct intel_watermark_params *display,
4213                            const struct intel_watermark_params *cursor)
4214 {
4215         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4216                       display_wm, cursor_wm);
4217
4218         if (display_wm > display->max_wm) {
4219                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4220                               display_wm, display->max_wm);
4221                 return false;
4222         }
4223
4224         if (cursor_wm > cursor->max_wm) {
4225                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4226                               cursor_wm, cursor->max_wm);
4227                 return false;
4228         }
4229
4230         if (!(display_wm || cursor_wm)) {
4231                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4232                 return false;
4233         }
4234
4235         return true;
4236 }
4237
4238 static bool g4x_compute_srwm(struct drm_device *dev,
4239                              int plane,
4240                              int latency_ns,
4241                              const struct intel_watermark_params *display,
4242                              const struct intel_watermark_params *cursor,
4243                              int *display_wm, int *cursor_wm)
4244 {
4245         struct drm_crtc *crtc;
4246         int hdisplay, htotal, pixel_size, clock;
4247         unsigned long line_time_us;
4248         int line_count, line_size;
4249         int small, large;
4250         int entries;
4251
4252         if (!latency_ns) {
4253                 *display_wm = *cursor_wm = 0;
4254                 return false;
4255         }
4256
4257         crtc = intel_get_crtc_for_plane(dev, plane);
4258         hdisplay = crtc->mode.hdisplay;
4259         htotal = crtc->mode.htotal;
4260         clock = crtc->mode.clock;
4261         pixel_size = crtc->fb->bits_per_pixel / 8;
4262
4263         line_time_us = (htotal * 1000) / clock;
4264         line_count = (latency_ns / line_time_us + 1000) / 1000;
4265         line_size = hdisplay * pixel_size;
4266
4267         /* Use the minimum of the small and large buffer method for primary */
4268         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4269         large = line_count * line_size;
4270
4271         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4272         *display_wm = entries + display->guard_size;
4273
4274         /* calculate the self-refresh watermark for display cursor */
4275         entries = line_count * pixel_size * 64;
4276         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4277         *cursor_wm = entries + cursor->guard_size;
4278
4279         return g4x_check_srwm(dev,
4280                               *display_wm, *cursor_wm,
4281                               display, cursor);
4282 }
4283
4284 static bool vlv_compute_drain_latency(struct drm_device *dev,
4285                                      int plane,
4286                                      int *plane_prec_mult,
4287                                      int *plane_dl,
4288                                      int *cursor_prec_mult,
4289                                      int *cursor_dl)
4290 {
4291         struct drm_crtc *crtc;
4292         int clock, pixel_size;
4293         int entries;
4294
4295         crtc = intel_get_crtc_for_plane(dev, plane);
4296         if (crtc->fb == NULL || !crtc->enabled)
4297                 return false;
4298
4299         clock = crtc->mode.clock;       /* VESA DOT Clock */
4300         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
4301
4302         entries = (clock / 1000) * pixel_size;
4303         *plane_prec_mult = (entries > 256) ?
4304                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4305         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
4306                                                      pixel_size);
4307
4308         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
4309         *cursor_prec_mult = (entries > 256) ?
4310                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
4311         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
4312
4313         return true;
4314 }
4315
4316 /*
4317  * Update drain latency registers of memory arbiter
4318  *
4319  * Valleyview SoC has a new memory arbiter and needs drain latency registers
4320  * to be programmed. Each plane has a drain latency multiplier and a drain
4321  * latency value.
4322  */
4323
4324 static void vlv_update_drain_latency(struct drm_device *dev)
4325 {
4326         struct drm_i915_private *dev_priv = dev->dev_private;
4327         int planea_prec, planea_dl, planeb_prec, planeb_dl;
4328         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
4329         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
4330                                                         either 16 or 32 */
4331
4332         /* For plane A, Cursor A */
4333         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
4334                                       &cursor_prec_mult, &cursora_dl)) {
4335                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4336                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
4337                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4338                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
4339
4340                 I915_WRITE(VLV_DDL1, cursora_prec |
4341                                 (cursora_dl << DDL_CURSORA_SHIFT) |
4342                                 planea_prec | planea_dl);
4343         }
4344
4345         /* For plane B, Cursor B */
4346         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
4347                                       &cursor_prec_mult, &cursorb_dl)) {
4348                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4349                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
4350                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
4351                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
4352
4353                 I915_WRITE(VLV_DDL2, cursorb_prec |
4354                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
4355                                 planeb_prec | planeb_dl);
4356         }
4357 }
4358
4359 #define single_plane_enabled(mask) is_power_of_2(mask)
4360
4361 static void valleyview_update_wm(struct drm_device *dev)
4362 {
4363         static const int sr_latency_ns = 12000;
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4366         int plane_sr, cursor_sr;
4367         unsigned int enabled = 0;
4368
4369         vlv_update_drain_latency(dev);
4370
4371         if (g4x_compute_wm0(dev, 0,
4372                             &valleyview_wm_info, latency_ns,
4373                             &valleyview_cursor_wm_info, latency_ns,
4374                             &planea_wm, &cursora_wm))
4375                 enabled |= 1;
4376
4377         if (g4x_compute_wm0(dev, 1,
4378                             &valleyview_wm_info, latency_ns,
4379                             &valleyview_cursor_wm_info, latency_ns,
4380                             &planeb_wm, &cursorb_wm))
4381                 enabled |= 2;
4382
4383         plane_sr = cursor_sr = 0;
4384         if (single_plane_enabled(enabled) &&
4385             g4x_compute_srwm(dev, ffs(enabled) - 1,
4386                              sr_latency_ns,
4387                              &valleyview_wm_info,
4388                              &valleyview_cursor_wm_info,
4389                              &plane_sr, &cursor_sr))
4390                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
4391         else
4392                 I915_WRITE(FW_BLC_SELF_VLV,
4393                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
4394
4395         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4396                       planea_wm, cursora_wm,
4397                       planeb_wm, cursorb_wm,
4398                       plane_sr, cursor_sr);
4399
4400         I915_WRITE(DSPFW1,
4401                    (plane_sr << DSPFW_SR_SHIFT) |
4402                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4403                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4404                    planea_wm);
4405         I915_WRITE(DSPFW2,
4406                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4407                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4408         I915_WRITE(DSPFW3,
4409                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
4410 }
4411
4412 static void g4x_update_wm(struct drm_device *dev)
4413 {
4414         static const int sr_latency_ns = 12000;
4415         struct drm_i915_private *dev_priv = dev->dev_private;
4416         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4417         int plane_sr, cursor_sr;
4418         unsigned int enabled = 0;
4419
4420         if (g4x_compute_wm0(dev, 0,
4421                             &g4x_wm_info, latency_ns,
4422                             &g4x_cursor_wm_info, latency_ns,
4423                             &planea_wm, &cursora_wm))
4424                 enabled |= 1;
4425
4426         if (g4x_compute_wm0(dev, 1,
4427                             &g4x_wm_info, latency_ns,
4428                             &g4x_cursor_wm_info, latency_ns,
4429                             &planeb_wm, &cursorb_wm))
4430                 enabled |= 2;
4431
4432         plane_sr = cursor_sr = 0;
4433         if (single_plane_enabled(enabled) &&
4434             g4x_compute_srwm(dev, ffs(enabled) - 1,
4435                              sr_latency_ns,
4436                              &g4x_wm_info,
4437                              &g4x_cursor_wm_info,
4438                              &plane_sr, &cursor_sr))
4439                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4440         else
4441                 I915_WRITE(FW_BLC_SELF,
4442                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4443
4444         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4445                       planea_wm, cursora_wm,
4446                       planeb_wm, cursorb_wm,
4447                       plane_sr, cursor_sr);
4448
4449         I915_WRITE(DSPFW1,
4450                    (plane_sr << DSPFW_SR_SHIFT) |
4451                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4452                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4453                    planea_wm);
4454         I915_WRITE(DSPFW2,
4455                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4456                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4457         /* HPLL off in SR has some issues on G4x... disable it */
4458         I915_WRITE(DSPFW3,
4459                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4460                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4461 }
4462
4463 static void i965_update_wm(struct drm_device *dev)
4464 {
4465         struct drm_i915_private *dev_priv = dev->dev_private;
4466         struct drm_crtc *crtc;
4467         int srwm = 1;
4468         int cursor_sr = 16;
4469
4470         /* Calc sr entries for one plane configs */
4471         crtc = single_enabled_crtc(dev);
4472         if (crtc) {
4473                 /* self-refresh has much higher latency */
4474                 static const int sr_latency_ns = 12000;
4475                 int clock = crtc->mode.clock;
4476                 int htotal = crtc->mode.htotal;
4477                 int hdisplay = crtc->mode.hdisplay;
4478                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4479                 unsigned long line_time_us;
4480                 int entries;
4481
4482                 line_time_us = ((htotal * 1000) / clock);
4483
4484                 /* Use ns/us then divide to preserve precision */
4485                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4486                         pixel_size * hdisplay;
4487                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4488                 srwm = I965_FIFO_SIZE - entries;
4489                 if (srwm < 0)
4490                         srwm = 1;
4491                 srwm &= 0x1ff;
4492                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4493                               entries, srwm);
4494
4495                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4496                         pixel_size * 64;
4497                 entries = DIV_ROUND_UP(entries,
4498                                           i965_cursor_wm_info.cacheline_size);
4499                 cursor_sr = i965_cursor_wm_info.fifo_size -
4500                         (entries + i965_cursor_wm_info.guard_size);
4501
4502                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4503                         cursor_sr = i965_cursor_wm_info.max_wm;
4504
4505                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4506                               "cursor %d\n", srwm, cursor_sr);
4507
4508                 if (IS_CRESTLINE(dev))
4509                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4510         } else {
4511                 /* Turn off self refresh if both pipes are enabled */
4512                 if (IS_CRESTLINE(dev))
4513                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4514                                    & ~FW_BLC_SELF_EN);
4515         }
4516
4517         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4518                       srwm);
4519
4520         /* 965 has limitations... */
4521         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4522                    (8 << 16) | (8 << 8) | (8 << 0));
4523         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4524         /* update cursor SR watermark */
4525         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4526 }
4527
4528 static void i9xx_update_wm(struct drm_device *dev)
4529 {
4530         struct drm_i915_private *dev_priv = dev->dev_private;
4531         const struct intel_watermark_params *wm_info;
4532         uint32_t fwater_lo;
4533         uint32_t fwater_hi;
4534         int cwm, srwm = 1;
4535         int fifo_size;
4536         int planea_wm, planeb_wm;
4537         struct drm_crtc *crtc, *enabled = NULL;
4538
4539         if (IS_I945GM(dev))
4540                 wm_info = &i945_wm_info;
4541         else if (!IS_GEN2(dev))
4542                 wm_info = &i915_wm_info;
4543         else
4544                 wm_info = &i855_wm_info;
4545
4546         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4547         crtc = intel_get_crtc_for_plane(dev, 0);
4548         if (crtc->enabled && crtc->fb) {
4549                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4550                                                wm_info, fifo_size,
4551                                                crtc->fb->bits_per_pixel / 8,
4552                                                latency_ns);
4553                 enabled = crtc;
4554         } else
4555                 planea_wm = fifo_size - wm_info->guard_size;
4556
4557         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4558         crtc = intel_get_crtc_for_plane(dev, 1);
4559         if (crtc->enabled && crtc->fb) {
4560                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4561                                                wm_info, fifo_size,
4562                                                crtc->fb->bits_per_pixel / 8,
4563                                                latency_ns);
4564                 if (enabled == NULL)
4565                         enabled = crtc;
4566                 else
4567                         enabled = NULL;
4568         } else
4569                 planeb_wm = fifo_size - wm_info->guard_size;
4570
4571         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4572
4573         /*
4574          * Overlay gets an aggressive default since video jitter is bad.
4575          */
4576         cwm = 2;
4577
4578         /* Play safe and disable self-refresh before adjusting watermarks. */
4579         if (IS_I945G(dev) || IS_I945GM(dev))
4580                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4581         else if (IS_I915GM(dev))
4582                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4583
4584         /* Calc sr entries for one plane configs */
4585         if (HAS_FW_BLC(dev) && enabled) {
4586                 /* self-refresh has much higher latency */
4587                 static const int sr_latency_ns = 6000;
4588                 int clock = enabled->mode.clock;
4589                 int htotal = enabled->mode.htotal;
4590                 int hdisplay = enabled->mode.hdisplay;
4591                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4592                 unsigned long line_time_us;
4593                 int entries;
4594
4595                 line_time_us = (htotal * 1000) / clock;
4596
4597                 /* Use ns/us then divide to preserve precision */
4598                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4599                         pixel_size * hdisplay;
4600                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4601                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4602                 srwm = wm_info->fifo_size - entries;
4603                 if (srwm < 0)
4604                         srwm = 1;
4605
4606                 if (IS_I945G(dev) || IS_I945GM(dev))
4607                         I915_WRITE(FW_BLC_SELF,
4608                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4609                 else if (IS_I915GM(dev))
4610                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4611         }
4612
4613         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4614                       planea_wm, planeb_wm, cwm, srwm);
4615
4616         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4617         fwater_hi = (cwm & 0x1f);
4618
4619         /* Set request length to 8 cachelines per fetch */
4620         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4621         fwater_hi = fwater_hi | (1 << 8);
4622
4623         I915_WRITE(FW_BLC, fwater_lo);
4624         I915_WRITE(FW_BLC2, fwater_hi);
4625
4626         if (HAS_FW_BLC(dev)) {
4627                 if (enabled) {
4628                         if (IS_I945G(dev) || IS_I945GM(dev))
4629                                 I915_WRITE(FW_BLC_SELF,
4630                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4631                         else if (IS_I915GM(dev))
4632                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4633                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4634                 } else
4635                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4636         }
4637 }
4638
4639 static void i830_update_wm(struct drm_device *dev)
4640 {
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         struct drm_crtc *crtc;
4643         uint32_t fwater_lo;
4644         int planea_wm;
4645
4646         crtc = single_enabled_crtc(dev);
4647         if (crtc == NULL)
4648                 return;
4649
4650         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4651                                        dev_priv->display.get_fifo_size(dev, 0),
4652                                        crtc->fb->bits_per_pixel / 8,
4653                                        latency_ns);
4654         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4655         fwater_lo |= (3<<8) | planea_wm;
4656
4657         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4658
4659         I915_WRITE(FW_BLC, fwater_lo);
4660 }
4661
4662 #define ILK_LP0_PLANE_LATENCY           700
4663 #define ILK_LP0_CURSOR_LATENCY          1300
4664
4665 /*
4666  * Check the wm result.
4667  *
4668  * If any calculated watermark values is larger than the maximum value that
4669  * can be programmed into the associated watermark register, that watermark
4670  * must be disabled.
4671  */
4672 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4673                                 int fbc_wm, int display_wm, int cursor_wm,
4674                                 const struct intel_watermark_params *display,
4675                                 const struct intel_watermark_params *cursor)
4676 {
4677         struct drm_i915_private *dev_priv = dev->dev_private;
4678
4679         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4680                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4681
4682         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4683                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4684                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4685
4686                 /* fbc has it's own way to disable FBC WM */
4687                 I915_WRITE(DISP_ARB_CTL,
4688                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4689                 return false;
4690         }
4691
4692         if (display_wm > display->max_wm) {
4693                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4694                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4695                 return false;
4696         }
4697
4698         if (cursor_wm > cursor->max_wm) {
4699                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4700                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4701                 return false;
4702         }
4703
4704         if (!(fbc_wm || display_wm || cursor_wm)) {
4705                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4706                 return false;
4707         }
4708
4709         return true;
4710 }
4711
4712 /*
4713  * Compute watermark values of WM[1-3],
4714  */
4715 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4716                                   int latency_ns,
4717                                   const struct intel_watermark_params *display,
4718                                   const struct intel_watermark_params *cursor,
4719                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4720 {
4721         struct drm_crtc *crtc;
4722         unsigned long line_time_us;
4723         int hdisplay, htotal, pixel_size, clock;
4724         int line_count, line_size;
4725         int small, large;
4726         int entries;
4727
4728         if (!latency_ns) {
4729                 *fbc_wm = *display_wm = *cursor_wm = 0;
4730                 return false;
4731         }
4732
4733         crtc = intel_get_crtc_for_plane(dev, plane);
4734         hdisplay = crtc->mode.hdisplay;
4735         htotal = crtc->mode.htotal;
4736         clock = crtc->mode.clock;
4737         pixel_size = crtc->fb->bits_per_pixel / 8;
4738
4739         line_time_us = (htotal * 1000) / clock;
4740         line_count = (latency_ns / line_time_us + 1000) / 1000;
4741         line_size = hdisplay * pixel_size;
4742
4743         /* Use the minimum of the small and large buffer method for primary */
4744         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4745         large = line_count * line_size;
4746
4747         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4748         *display_wm = entries + display->guard_size;
4749
4750         /*
4751          * Spec says:
4752          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4753          */
4754         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4755
4756         /* calculate the self-refresh watermark for display cursor */
4757         entries = line_count * pixel_size * 64;
4758         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4759         *cursor_wm = entries + cursor->guard_size;
4760
4761         return ironlake_check_srwm(dev, level,
4762                                    *fbc_wm, *display_wm, *cursor_wm,
4763                                    display, cursor);
4764 }
4765
4766 static void ironlake_update_wm(struct drm_device *dev)
4767 {
4768         struct drm_i915_private *dev_priv = dev->dev_private;
4769         int fbc_wm, plane_wm, cursor_wm;
4770         unsigned int enabled;
4771
4772         enabled = 0;
4773         if (g4x_compute_wm0(dev, 0,
4774                             &ironlake_display_wm_info,
4775                             ILK_LP0_PLANE_LATENCY,
4776                             &ironlake_cursor_wm_info,
4777                             ILK_LP0_CURSOR_LATENCY,
4778                             &plane_wm, &cursor_wm)) {
4779                 I915_WRITE(WM0_PIPEA_ILK,
4780                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4781                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4782                               " plane %d, " "cursor: %d\n",
4783                               plane_wm, cursor_wm);
4784                 enabled |= 1;
4785         }
4786
4787         if (g4x_compute_wm0(dev, 1,
4788                             &ironlake_display_wm_info,
4789                             ILK_LP0_PLANE_LATENCY,
4790                             &ironlake_cursor_wm_info,
4791                             ILK_LP0_CURSOR_LATENCY,
4792                             &plane_wm, &cursor_wm)) {
4793                 I915_WRITE(WM0_PIPEB_ILK,
4794                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4795                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4796                               " plane %d, cursor: %d\n",
4797                               plane_wm, cursor_wm);
4798                 enabled |= 2;
4799         }
4800
4801         /*
4802          * Calculate and update the self-refresh watermark only when one
4803          * display plane is used.
4804          */
4805         I915_WRITE(WM3_LP_ILK, 0);
4806         I915_WRITE(WM2_LP_ILK, 0);
4807         I915_WRITE(WM1_LP_ILK, 0);
4808
4809         if (!single_plane_enabled(enabled))
4810                 return;
4811         enabled = ffs(enabled) - 1;
4812
4813         /* WM1 */
4814         if (!ironlake_compute_srwm(dev, 1, enabled,
4815                                    ILK_READ_WM1_LATENCY() * 500,
4816                                    &ironlake_display_srwm_info,
4817                                    &ironlake_cursor_srwm_info,
4818                                    &fbc_wm, &plane_wm, &cursor_wm))
4819                 return;
4820
4821         I915_WRITE(WM1_LP_ILK,
4822                    WM1_LP_SR_EN |
4823                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4824                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4825                    (plane_wm << WM1_LP_SR_SHIFT) |
4826                    cursor_wm);
4827
4828         /* WM2 */
4829         if (!ironlake_compute_srwm(dev, 2, enabled,
4830                                    ILK_READ_WM2_LATENCY() * 500,
4831                                    &ironlake_display_srwm_info,
4832                                    &ironlake_cursor_srwm_info,
4833                                    &fbc_wm, &plane_wm, &cursor_wm))
4834                 return;
4835
4836         I915_WRITE(WM2_LP_ILK,
4837                    WM2_LP_EN |
4838                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4839                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4840                    (plane_wm << WM1_LP_SR_SHIFT) |
4841                    cursor_wm);
4842
4843         /*
4844          * WM3 is unsupported on ILK, probably because we don't have latency
4845          * data for that power state
4846          */
4847 }
4848
4849 static void sandybridge_update_wm(struct drm_device *dev)
4850 {
4851         struct drm_i915_private *dev_priv = dev->dev_private;
4852         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4853         u32 val;
4854         int fbc_wm, plane_wm, cursor_wm;
4855         unsigned int enabled;
4856
4857         enabled = 0;
4858         if (g4x_compute_wm0(dev, 0,
4859                             &sandybridge_display_wm_info, latency,
4860                             &sandybridge_cursor_wm_info, latency,
4861                             &plane_wm, &cursor_wm)) {
4862                 val = I915_READ(WM0_PIPEA_ILK);
4863                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4864                 I915_WRITE(WM0_PIPEA_ILK, val |
4865                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4866                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4867                               " plane %d, " "cursor: %d\n",
4868                               plane_wm, cursor_wm);
4869                 enabled |= 1;
4870         }
4871
4872         if (g4x_compute_wm0(dev, 1,
4873                             &sandybridge_display_wm_info, latency,
4874                             &sandybridge_cursor_wm_info, latency,
4875                             &plane_wm, &cursor_wm)) {
4876                 val = I915_READ(WM0_PIPEB_ILK);
4877                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4878                 I915_WRITE(WM0_PIPEB_ILK, val |
4879                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4880                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4881                               " plane %d, cursor: %d\n",
4882                               plane_wm, cursor_wm);
4883                 enabled |= 2;
4884         }
4885
4886         /* IVB has 3 pipes */
4887         if (IS_IVYBRIDGE(dev) &&
4888             g4x_compute_wm0(dev, 2,
4889                             &sandybridge_display_wm_info, latency,
4890                             &sandybridge_cursor_wm_info, latency,
4891                             &plane_wm, &cursor_wm)) {
4892                 val = I915_READ(WM0_PIPEC_IVB);
4893                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4894                 I915_WRITE(WM0_PIPEC_IVB, val |
4895                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4896                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4897                               " plane %d, cursor: %d\n",
4898                               plane_wm, cursor_wm);
4899                 enabled |= 3;
4900         }
4901
4902         /*
4903          * Calculate and update the self-refresh watermark only when one
4904          * display plane is used.
4905          *
4906          * SNB support 3 levels of watermark.
4907          *
4908          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4909          * and disabled in the descending order
4910          *
4911          */
4912         I915_WRITE(WM3_LP_ILK, 0);
4913         I915_WRITE(WM2_LP_ILK, 0);
4914         I915_WRITE(WM1_LP_ILK, 0);
4915
4916         if (!single_plane_enabled(enabled) ||
4917             dev_priv->sprite_scaling_enabled)
4918                 return;
4919         enabled = ffs(enabled) - 1;
4920
4921         /* WM1 */
4922         if (!ironlake_compute_srwm(dev, 1, enabled,
4923                                    SNB_READ_WM1_LATENCY() * 500,
4924                                    &sandybridge_display_srwm_info,
4925                                    &sandybridge_cursor_srwm_info,
4926                                    &fbc_wm, &plane_wm, &cursor_wm))
4927                 return;
4928
4929         I915_WRITE(WM1_LP_ILK,
4930                    WM1_LP_SR_EN |
4931                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4932                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4933                    (plane_wm << WM1_LP_SR_SHIFT) |
4934                    cursor_wm);
4935
4936         /* WM2 */
4937         if (!ironlake_compute_srwm(dev, 2, enabled,
4938                                    SNB_READ_WM2_LATENCY() * 500,
4939                                    &sandybridge_display_srwm_info,
4940                                    &sandybridge_cursor_srwm_info,
4941                                    &fbc_wm, &plane_wm, &cursor_wm))
4942                 return;
4943
4944         I915_WRITE(WM2_LP_ILK,
4945                    WM2_LP_EN |
4946                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4947                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4948                    (plane_wm << WM1_LP_SR_SHIFT) |
4949                    cursor_wm);
4950
4951         /* WM3 */
4952         if (!ironlake_compute_srwm(dev, 3, enabled,
4953                                    SNB_READ_WM3_LATENCY() * 500,
4954                                    &sandybridge_display_srwm_info,
4955                                    &sandybridge_cursor_srwm_info,
4956                                    &fbc_wm, &plane_wm, &cursor_wm))
4957                 return;
4958
4959         I915_WRITE(WM3_LP_ILK,
4960                    WM3_LP_EN |
4961                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4962                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4963                    (plane_wm << WM1_LP_SR_SHIFT) |
4964                    cursor_wm);
4965 }
4966
4967 static bool
4968 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4969                               uint32_t sprite_width, int pixel_size,
4970                               const struct intel_watermark_params *display,
4971                               int display_latency_ns, int *sprite_wm)
4972 {
4973         struct drm_crtc *crtc;
4974         int clock;
4975         int entries, tlb_miss;
4976
4977         crtc = intel_get_crtc_for_plane(dev, plane);
4978         if (crtc->fb == NULL || !crtc->enabled) {
4979                 *sprite_wm = display->guard_size;
4980                 return false;
4981         }
4982
4983         clock = crtc->mode.clock;
4984
4985         /* Use the small buffer method to calculate the sprite watermark */
4986         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4987         tlb_miss = display->fifo_size*display->cacheline_size -
4988                 sprite_width * 8;
4989         if (tlb_miss > 0)
4990                 entries += tlb_miss;
4991         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4992         *sprite_wm = entries + display->guard_size;
4993         if (*sprite_wm > (int)display->max_wm)
4994                 *sprite_wm = display->max_wm;
4995
4996         return true;
4997 }
4998
4999 static bool
5000 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
5001                                 uint32_t sprite_width, int pixel_size,
5002                                 const struct intel_watermark_params *display,
5003                                 int latency_ns, int *sprite_wm)
5004 {
5005         struct drm_crtc *crtc;
5006         unsigned long line_time_us;
5007         int clock;
5008         int line_count, line_size;
5009         int small, large;
5010         int entries;
5011
5012         if (!latency_ns) {
5013                 *sprite_wm = 0;
5014                 return false;
5015         }
5016
5017         crtc = intel_get_crtc_for_plane(dev, plane);
5018         clock = crtc->mode.clock;
5019         if (!clock) {
5020                 *sprite_wm = 0;
5021                 return false;
5022         }
5023
5024         line_time_us = (sprite_width * 1000) / clock;
5025         if (!line_time_us) {
5026                 *sprite_wm = 0;
5027                 return false;
5028         }
5029
5030         line_count = (latency_ns / line_time_us + 1000) / 1000;
5031         line_size = sprite_width * pixel_size;
5032
5033         /* Use the minimum of the small and large buffer method for primary */
5034         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
5035         large = line_count * line_size;
5036
5037         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
5038         *sprite_wm = entries + display->guard_size;
5039
5040         return *sprite_wm > 0x3ff ? false : true;
5041 }
5042
5043 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
5044                                          uint32_t sprite_width, int pixel_size)
5045 {
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
5048         u32 val;
5049         int sprite_wm, reg;
5050         int ret;
5051
5052         switch (pipe) {
5053         case 0:
5054                 reg = WM0_PIPEA_ILK;
5055                 break;
5056         case 1:
5057                 reg = WM0_PIPEB_ILK;
5058                 break;
5059         case 2:
5060                 reg = WM0_PIPEC_IVB;
5061                 break;
5062         default:
5063                 return; /* bad pipe */
5064         }
5065
5066         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
5067                                             &sandybridge_display_wm_info,
5068                                             latency, &sprite_wm);
5069         if (!ret) {
5070                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
5071                               pipe);
5072                 return;
5073         }
5074
5075         val = I915_READ(reg);
5076         val &= ~WM0_PIPE_SPRITE_MASK;
5077         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
5078         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
5079
5080
5081         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5082                                               pixel_size,
5083                                               &sandybridge_display_srwm_info,
5084                                               SNB_READ_WM1_LATENCY() * 500,
5085                                               &sprite_wm);
5086         if (!ret) {
5087                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
5088                               pipe);
5089                 return;
5090         }
5091         I915_WRITE(WM1S_LP_ILK, sprite_wm);
5092
5093         /* Only IVB has two more LP watermarks for sprite */
5094         if (!IS_IVYBRIDGE(dev))
5095                 return;
5096
5097         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5098                                               pixel_size,
5099                                               &sandybridge_display_srwm_info,
5100                                               SNB_READ_WM2_LATENCY() * 500,
5101                                               &sprite_wm);
5102         if (!ret) {
5103                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
5104                               pipe);
5105                 return;
5106         }
5107         I915_WRITE(WM2S_LP_IVB, sprite_wm);
5108
5109         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
5110                                               pixel_size,
5111                                               &sandybridge_display_srwm_info,
5112                                               SNB_READ_WM3_LATENCY() * 500,
5113                                               &sprite_wm);
5114         if (!ret) {
5115                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
5116                               pipe);
5117                 return;
5118         }
5119         I915_WRITE(WM3S_LP_IVB, sprite_wm);
5120 }
5121
5122 /**
5123  * intel_update_watermarks - update FIFO watermark values based on current modes
5124  *
5125  * Calculate watermark values for the various WM regs based on current mode
5126  * and plane configuration.
5127  *
5128  * There are several cases to deal with here:
5129  *   - normal (i.e. non-self-refresh)
5130  *   - self-refresh (SR) mode
5131  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5132  *   - lines are small relative to FIFO size (buffer can hold more than 2
5133  *     lines), so need to account for TLB latency
5134  *
5135  *   The normal calculation is:
5136  *     watermark = dotclock * bytes per pixel * latency
5137  *   where latency is platform & configuration dependent (we assume pessimal
5138  *   values here).
5139  *
5140  *   The SR calculation is:
5141  *     watermark = (trunc(latency/line time)+1) * surface width *
5142  *       bytes per pixel
5143  *   where
5144  *     line time = htotal / dotclock
5145  *     surface width = hdisplay for normal plane and 64 for cursor
5146  *   and latency is assumed to be high, as above.
5147  *
5148  * The final value programmed to the register should always be rounded up,
5149  * and include an extra 2 entries to account for clock crossings.
5150  *
5151  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5152  * to set the non-SR watermarks to 8.
5153  */
5154 void intel_update_watermarks(struct drm_device *dev)
5155 {
5156         struct drm_i915_private *dev_priv = dev->dev_private;
5157
5158         if (dev_priv->display.update_wm)
5159                 dev_priv->display.update_wm(dev);
5160 }
5161
5162 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
5163                                     uint32_t sprite_width, int pixel_size)
5164 {
5165         struct drm_i915_private *dev_priv = dev->dev_private;
5166
5167         if (dev_priv->display.update_sprite_wm)
5168                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
5169                                                    pixel_size);
5170 }
5171
5172 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5173 {
5174         if (i915_panel_use_ssc >= 0)
5175                 return i915_panel_use_ssc != 0;
5176         return dev_priv->lvds_use_ssc
5177                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5178 }
5179
5180 /**
5181  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
5182  * @crtc: CRTC structure
5183  * @mode: requested mode
5184  *
5185  * A pipe may be connected to one or more outputs.  Based on the depth of the
5186  * attached framebuffer, choose a good color depth to use on the pipe.
5187  *
5188  * If possible, match the pipe depth to the fb depth.  In some cases, this
5189  * isn't ideal, because the connected output supports a lesser or restricted
5190  * set of depths.  Resolve that here:
5191  *    LVDS typically supports only 6bpc, so clamp down in that case
5192  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
5193  *    Displays may support a restricted set as well, check EDID and clamp as
5194  *      appropriate.
5195  *    DP may want to dither down to 6bpc to fit larger modes
5196  *
5197  * RETURNS:
5198  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
5199  * true if they don't match).
5200  */
5201 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
5202                                          unsigned int *pipe_bpp,
5203                                          struct drm_display_mode *mode)
5204 {
5205         struct drm_device *dev = crtc->dev;
5206         struct drm_i915_private *dev_priv = dev->dev_private;
5207         struct drm_encoder *encoder;
5208         struct drm_connector *connector;
5209         unsigned int display_bpc = UINT_MAX, bpc;
5210
5211         /* Walk the encoders & connectors on this crtc, get min bpc */
5212         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5213                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5214
5215                 if (encoder->crtc != crtc)
5216                         continue;
5217
5218                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
5219                         unsigned int lvds_bpc;
5220
5221                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
5222                             LVDS_A3_POWER_UP)
5223                                 lvds_bpc = 8;
5224                         else
5225                                 lvds_bpc = 6;
5226
5227                         if (lvds_bpc < display_bpc) {
5228                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5229                                 display_bpc = lvds_bpc;
5230                         }
5231                         continue;
5232                 }
5233
5234                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5235                         /* Use VBT settings if we have an eDP panel */
5236                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5237
5238                         if (edp_bpc < display_bpc) {
5239                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5240                                 display_bpc = edp_bpc;
5241                         }
5242                         continue;
5243                 }
5244
5245                 /* Not one of the known troublemakers, check the EDID */
5246                 list_for_each_entry(connector, &dev->mode_config.connector_list,
5247                                     head) {
5248                         if (connector->encoder != encoder)
5249                                 continue;
5250
5251                         /* Don't use an invalid EDID bpc value */
5252                         if (connector->display_info.bpc &&
5253                             connector->display_info.bpc < display_bpc) {
5254                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5255                                 display_bpc = connector->display_info.bpc;
5256                         }
5257                 }
5258
5259                 /*
5260                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5261                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5262                  */
5263                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5264                         if (display_bpc > 8 && display_bpc < 12) {
5265                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5266                                 display_bpc = 12;
5267                         } else {
5268                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5269                                 display_bpc = 8;
5270                         }
5271                 }
5272         }
5273
5274         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5275                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5276                 display_bpc = 6;
5277         }
5278
5279         /*
5280          * We could just drive the pipe at the highest bpc all the time and
5281          * enable dithering as needed, but that costs bandwidth.  So choose
5282          * the minimum value that expresses the full color range of the fb but
5283          * also stays within the max display bpc discovered above.
5284          */
5285
5286         switch (crtc->fb->depth) {
5287         case 8:
5288                 bpc = 8; /* since we go through a colormap */
5289                 break;
5290         case 15:
5291         case 16:
5292                 bpc = 6; /* min is 18bpp */
5293                 break;
5294         case 24:
5295                 bpc = 8;
5296                 break;
5297         case 30:
5298                 bpc = 10;
5299                 break;
5300         case 48:
5301                 bpc = 12;
5302                 break;
5303         default:
5304                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5305                 bpc = min((unsigned int)8, display_bpc);
5306                 break;
5307         }
5308
5309         display_bpc = min(display_bpc, bpc);
5310
5311         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5312                       bpc, display_bpc);
5313
5314         *pipe_bpp = display_bpc * 3;
5315
5316         return display_bpc != bpc;
5317 }
5318
5319 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5320 {
5321         struct drm_device *dev = crtc->dev;
5322         struct drm_i915_private *dev_priv = dev->dev_private;
5323         int refclk;
5324
5325         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5326             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5327                 refclk = dev_priv->lvds_ssc_freq * 1000;
5328                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5329                               refclk / 1000);
5330         } else if (!IS_GEN2(dev)) {
5331                 refclk = 96000;
5332         } else {
5333                 refclk = 48000;
5334         }
5335
5336         return refclk;
5337 }
5338
5339 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5340                                       intel_clock_t *clock)
5341 {
5342         /* SDVO TV has fixed PLL values depend on its clock range,
5343            this mirrors vbios setting. */
5344         if (adjusted_mode->clock >= 100000
5345             && adjusted_mode->clock < 140500) {
5346                 clock->p1 = 2;
5347                 clock->p2 = 10;
5348                 clock->n = 3;
5349                 clock->m1 = 16;
5350                 clock->m2 = 8;
5351         } else if (adjusted_mode->clock >= 140500
5352                    && adjusted_mode->clock <= 200000) {
5353                 clock->p1 = 1;
5354                 clock->p2 = 10;
5355                 clock->n = 6;
5356                 clock->m1 = 12;
5357                 clock->m2 = 8;
5358         }
5359 }
5360
5361 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5362                                      intel_clock_t *clock,
5363                                      intel_clock_t *reduced_clock)
5364 {
5365         struct drm_device *dev = crtc->dev;
5366         struct drm_i915_private *dev_priv = dev->dev_private;
5367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5368         int pipe = intel_crtc->pipe;
5369         u32 fp, fp2 = 0;
5370
5371         if (IS_PINEVIEW(dev)) {
5372                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5373                 if (reduced_clock)
5374                         fp2 = (1 << reduced_clock->n) << 16 |
5375                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5376         } else {
5377                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5378                 if (reduced_clock)
5379                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5380                                 reduced_clock->m2;
5381         }
5382
5383         I915_WRITE(FP0(pipe), fp);
5384
5385         intel_crtc->lowfreq_avail = false;
5386         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5387             reduced_clock && i915_powersave) {
5388                 I915_WRITE(FP1(pipe), fp2);
5389                 intel_crtc->lowfreq_avail = true;
5390         } else {
5391                 I915_WRITE(FP1(pipe), fp);
5392         }
5393 }
5394
5395 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
5396                               struct drm_display_mode *adjusted_mode)
5397 {
5398         struct drm_device *dev = crtc->dev;
5399         struct drm_i915_private *dev_priv = dev->dev_private;
5400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401         int pipe = intel_crtc->pipe;
5402         u32 temp, lvds_sync = 0;
5403
5404         temp = I915_READ(LVDS);
5405         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5406         if (pipe == 1) {
5407                 temp |= LVDS_PIPEB_SELECT;
5408         } else {
5409                 temp &= ~LVDS_PIPEB_SELECT;
5410         }
5411         /* set the corresponsding LVDS_BORDER bit */
5412         temp |= dev_priv->lvds_border_bits;
5413         /* Set the B0-B3 data pairs corresponding to whether we're going to
5414          * set the DPLLs for dual-channel mode or not.
5415          */
5416         if (clock->p2 == 7)
5417                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5418         else
5419                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5420
5421         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5422          * appropriately here, but we need to look more thoroughly into how
5423          * panels behave in the two modes.
5424          */
5425         /* set the dithering flag on LVDS as needed */
5426         if (INTEL_INFO(dev)->gen >= 4) {
5427                 if (dev_priv->lvds_dither)
5428                         temp |= LVDS_ENABLE_DITHER;
5429                 else
5430                         temp &= ~LVDS_ENABLE_DITHER;
5431         }
5432         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5433                 lvds_sync |= LVDS_HSYNC_POLARITY;
5434         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5435                 lvds_sync |= LVDS_VSYNC_POLARITY;
5436         if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5437             != lvds_sync) {
5438                 char flags[2] = "-+";
5439                 DRM_INFO("Changing LVDS panel from "
5440                          "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5441                          flags[!(temp & LVDS_HSYNC_POLARITY)],
5442                          flags[!(temp & LVDS_VSYNC_POLARITY)],
5443                          flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5444                          flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5445                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5446                 temp |= lvds_sync;
5447         }
5448         I915_WRITE(LVDS, temp);
5449 }
5450
5451 static void i9xx_update_pll(struct drm_crtc *crtc,
5452                             struct drm_display_mode *mode,
5453                             struct drm_display_mode *adjusted_mode,
5454                             intel_clock_t *clock, intel_clock_t *reduced_clock,
5455                             int num_connectors)
5456 {
5457         struct drm_device *dev = crtc->dev;
5458         struct drm_i915_private *dev_priv = dev->dev_private;
5459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5460         int pipe = intel_crtc->pipe;
5461         u32 dpll;
5462         bool is_sdvo;
5463
5464         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5465                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5466
5467         dpll = DPLL_VGA_MODE_DIS;
5468
5469         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5470                 dpll |= DPLLB_MODE_LVDS;
5471         else
5472                 dpll |= DPLLB_MODE_DAC_SERIAL;
5473         if (is_sdvo) {
5474                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5475                 if (pixel_multiplier > 1) {
5476                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5477                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5478                 }
5479                 dpll |= DPLL_DVO_HIGH_SPEED;
5480         }
5481         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5482                 dpll |= DPLL_DVO_HIGH_SPEED;
5483
5484         /* compute bitmask from p1 value */
5485         if (IS_PINEVIEW(dev))
5486                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5487         else {
5488                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5489                 if (IS_G4X(dev) && reduced_clock)
5490                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5491         }
5492         switch (clock->p2) {
5493         case 5:
5494                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5495                 break;
5496         case 7:
5497                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5498                 break;
5499         case 10:
5500                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5501                 break;
5502         case 14:
5503                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5504                 break;
5505         }
5506         if (INTEL_INFO(dev)->gen >= 4)
5507                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5508
5509         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5510                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5511         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5512                 /* XXX: just matching BIOS for now */
5513                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5514                 dpll |= 3;
5515         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5516                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5517                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5518         else
5519                 dpll |= PLL_REF_INPUT_DREFCLK;
5520
5521         dpll |= DPLL_VCO_ENABLE;
5522         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5523         POSTING_READ(DPLL(pipe));
5524         udelay(150);
5525
5526         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5527          * This is an exception to the general rule that mode_set doesn't turn
5528          * things on.
5529          */
5530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5531                 intel_update_lvds(crtc, clock, adjusted_mode);
5532
5533         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5534                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5535
5536         I915_WRITE(DPLL(pipe), dpll);
5537
5538         /* Wait for the clocks to stabilize. */
5539         POSTING_READ(DPLL(pipe));
5540         udelay(150);
5541
5542         if (INTEL_INFO(dev)->gen >= 4) {
5543                 u32 temp = 0;
5544                 if (is_sdvo) {
5545                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5546                         if (temp > 1)
5547                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5548                         else
5549                                 temp = 0;
5550                 }
5551                 I915_WRITE(DPLL_MD(pipe), temp);
5552         } else {
5553                 /* The pixel multiplier can only be updated once the
5554                  * DPLL is enabled and the clocks are stable.
5555                  *
5556                  * So write it again.
5557                  */
5558                 I915_WRITE(DPLL(pipe), dpll);
5559         }
5560 }
5561
5562 static void i8xx_update_pll(struct drm_crtc *crtc,
5563                             struct drm_display_mode *adjusted_mode,
5564                             intel_clock_t *clock,
5565                             int num_connectors)
5566 {
5567         struct drm_device *dev = crtc->dev;
5568         struct drm_i915_private *dev_priv = dev->dev_private;
5569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5570         int pipe = intel_crtc->pipe;
5571         u32 dpll;
5572
5573         dpll = DPLL_VGA_MODE_DIS;
5574
5575         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
5576                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5577         } else {
5578                 if (clock->p1 == 2)
5579                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5580                 else
5581                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5582                 if (clock->p2 == 4)
5583                         dpll |= PLL_P2_DIVIDE_BY_4;
5584         }
5585
5586         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
5587                 /* XXX: just matching BIOS for now */
5588                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5589                 dpll |= 3;
5590         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5591                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5592                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5593         else
5594                 dpll |= PLL_REF_INPUT_DREFCLK;
5595
5596         dpll |= DPLL_VCO_ENABLE;
5597         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5598         POSTING_READ(DPLL(pipe));
5599         udelay(150);
5600
5601         I915_WRITE(DPLL(pipe), dpll);
5602
5603         /* Wait for the clocks to stabilize. */
5604         POSTING_READ(DPLL(pipe));
5605         udelay(150);
5606
5607         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5608          * This is an exception to the general rule that mode_set doesn't turn
5609          * things on.
5610          */
5611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5612                 intel_update_lvds(crtc, clock, adjusted_mode);
5613
5614         /* The pixel multiplier can only be updated once the
5615          * DPLL is enabled and the clocks are stable.
5616          *
5617          * So write it again.
5618          */
5619         I915_WRITE(DPLL(pipe), dpll);
5620 }
5621
5622 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5623                               struct drm_display_mode *mode,
5624                               struct drm_display_mode *adjusted_mode,
5625                               int x, int y,
5626                               struct drm_framebuffer *old_fb)
5627 {
5628         struct drm_device *dev = crtc->dev;
5629         struct drm_i915_private *dev_priv = dev->dev_private;
5630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5631         int pipe = intel_crtc->pipe;
5632         int plane = intel_crtc->plane;
5633         int refclk, num_connectors = 0;
5634         intel_clock_t clock, reduced_clock;
5635         u32 dspcntr, pipeconf, vsyncshift;
5636         bool ok, has_reduced_clock = false, is_sdvo = false;
5637         bool is_lvds = false, is_tv = false, is_dp = false;
5638         struct drm_mode_config *mode_config = &dev->mode_config;
5639         struct intel_encoder *encoder;
5640         const intel_limit_t *limit;
5641         int ret;
5642
5643         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5644                 if (encoder->base.crtc != crtc)
5645                         continue;
5646
5647                 switch (encoder->type) {
5648                 case INTEL_OUTPUT_LVDS:
5649                         is_lvds = true;
5650                         break;
5651                 case INTEL_OUTPUT_SDVO:
5652                 case INTEL_OUTPUT_HDMI:
5653                         is_sdvo = true;
5654                         if (encoder->needs_tv_clock)
5655                                 is_tv = true;
5656                         break;
5657                 case INTEL_OUTPUT_TVOUT:
5658                         is_tv = true;
5659                         break;
5660                 case INTEL_OUTPUT_DISPLAYPORT:
5661                         is_dp = true;
5662                         break;
5663                 }
5664
5665                 num_connectors++;
5666         }
5667
5668         refclk = i9xx_get_refclk(crtc, num_connectors);
5669
5670         /*
5671          * Returns a set of divisors for the desired target clock with the given
5672          * refclk, or FALSE.  The returned values represent the clock equation:
5673          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5674          */
5675         limit = intel_limit(crtc, refclk);
5676         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5677                              &clock);
5678         if (!ok) {
5679                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5680                 return -EINVAL;
5681         }
5682
5683         /* Ensure that the cursor is valid for the new mode before changing... */
5684         intel_crtc_update_cursor(crtc, true);
5685
5686         if (is_lvds && dev_priv->lvds_downclock_avail) {
5687                 /*
5688                  * Ensure we match the reduced clock's P to the target clock.
5689                  * If the clocks don't match, we can't switch the display clock
5690                  * by using the FP0/FP1. In such case we will disable the LVDS
5691                  * downclock feature.
5692                 */
5693                 has_reduced_clock = limit->find_pll(limit, crtc,
5694                                                     dev_priv->lvds_downclock,
5695                                                     refclk,
5696                                                     &clock,
5697                                                     &reduced_clock);
5698         }
5699
5700         if (is_sdvo && is_tv)
5701                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5702
5703         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5704                                  &reduced_clock : NULL);
5705
5706         if (IS_GEN2(dev))
5707                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
5708         else
5709                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
5710                                 has_reduced_clock ? &reduced_clock : NULL,
5711                                 num_connectors);
5712
5713         /* setup pipeconf */
5714         pipeconf = I915_READ(PIPECONF(pipe));
5715
5716         /* Set up the display plane register */
5717         dspcntr = DISPPLANE_GAMMA_ENABLE;
5718
5719         if (pipe == 0)
5720                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5721         else
5722                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5723
5724         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5725                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5726                  * core speed.
5727                  *
5728                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5729                  * pipe == 0 check?
5730                  */
5731                 if (mode->clock >
5732                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5733                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5734                 else
5735                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5736         }
5737
5738         /* default to 8bpc */
5739         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5740         if (is_dp) {
5741                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5742                         pipeconf |= PIPECONF_BPP_6 |
5743                                     PIPECONF_DITHER_EN |
5744                                     PIPECONF_DITHER_TYPE_SP;
5745                 }
5746         }
5747
5748         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5749         drm_mode_debug_printmodeline(mode);
5750
5751         if (HAS_PIPE_CXSR(dev)) {
5752                 if (intel_crtc->lowfreq_avail) {
5753                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5754                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5755                 } else {
5756                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5757                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5758                 }
5759         }
5760
5761         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5762         if (!IS_GEN2(dev) &&
5763             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5764                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5765                 /* the chip adds 2 halflines automatically */
5766                 adjusted_mode->crtc_vtotal -= 1;
5767                 adjusted_mode->crtc_vblank_end -= 1;
5768                 vsyncshift = adjusted_mode->crtc_hsync_start
5769                              - adjusted_mode->crtc_htotal/2;
5770         } else {
5771                 pipeconf |= PIPECONF_PROGRESSIVE;
5772                 vsyncshift = 0;
5773         }
5774
5775         if (!IS_GEN3(dev))
5776                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5777
5778         I915_WRITE(HTOTAL(pipe),
5779                    (adjusted_mode->crtc_hdisplay - 1) |
5780                    ((adjusted_mode->crtc_htotal - 1) << 16));
5781         I915_WRITE(HBLANK(pipe),
5782                    (adjusted_mode->crtc_hblank_start - 1) |
5783                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5784         I915_WRITE(HSYNC(pipe),
5785                    (adjusted_mode->crtc_hsync_start - 1) |
5786                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5787
5788         I915_WRITE(VTOTAL(pipe),
5789                    (adjusted_mode->crtc_vdisplay - 1) |
5790                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5791         I915_WRITE(VBLANK(pipe),
5792                    (adjusted_mode->crtc_vblank_start - 1) |
5793                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5794         I915_WRITE(VSYNC(pipe),
5795                    (adjusted_mode->crtc_vsync_start - 1) |
5796                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5797
5798         /* pipesrc and dspsize control the size that is scaled from,
5799          * which should always be the user's requested size.
5800          */
5801         I915_WRITE(DSPSIZE(plane),
5802                    ((mode->vdisplay - 1) << 16) |
5803                    (mode->hdisplay - 1));
5804         I915_WRITE(DSPPOS(plane), 0);
5805         I915_WRITE(PIPESRC(pipe),
5806                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5807
5808         I915_WRITE(PIPECONF(pipe), pipeconf);
5809         POSTING_READ(PIPECONF(pipe));
5810         intel_enable_pipe(dev_priv, pipe, false);
5811
5812         intel_wait_for_vblank(dev, pipe);
5813
5814         I915_WRITE(DSPCNTR(plane), dspcntr);
5815         POSTING_READ(DSPCNTR(plane));
5816         intel_enable_plane(dev_priv, plane, pipe);
5817
5818         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5819
5820         intel_update_watermarks(dev);
5821
5822         return ret;
5823 }
5824
5825 /*
5826  * Initialize reference clocks when the driver loads
5827  */
5828 void ironlake_init_pch_refclk(struct drm_device *dev)
5829 {
5830         struct drm_i915_private *dev_priv = dev->dev_private;
5831         struct drm_mode_config *mode_config = &dev->mode_config;
5832         struct intel_encoder *encoder;
5833         u32 temp;
5834         bool has_lvds = false;
5835         bool has_cpu_edp = false;
5836         bool has_pch_edp = false;
5837         bool has_panel = false;
5838         bool has_ck505 = false;
5839         bool can_ssc = false;
5840
5841         /* We need to take the global config into account */
5842         list_for_each_entry(encoder, &mode_config->encoder_list,
5843                             base.head) {
5844                 switch (encoder->type) {
5845                 case INTEL_OUTPUT_LVDS:
5846                         has_panel = true;
5847                         has_lvds = true;
5848                         break;
5849                 case INTEL_OUTPUT_EDP:
5850                         has_panel = true;
5851                         if (intel_encoder_is_pch_edp(&encoder->base))
5852                                 has_pch_edp = true;
5853                         else
5854                                 has_cpu_edp = true;
5855                         break;
5856                 }
5857         }
5858
5859         if (HAS_PCH_IBX(dev)) {
5860                 has_ck505 = dev_priv->display_clock_mode;
5861                 can_ssc = has_ck505;
5862         } else {
5863                 has_ck505 = false;
5864                 can_ssc = true;
5865         }
5866
5867         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5868                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5869                       has_ck505);
5870
5871         /* Ironlake: try to setup display ref clock before DPLL
5872          * enabling. This is only under driver's control after
5873          * PCH B stepping, previous chipset stepping should be
5874          * ignoring this setting.
5875          */
5876         temp = I915_READ(PCH_DREF_CONTROL);
5877         /* Always enable nonspread source */
5878         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5879
5880         if (has_ck505)
5881                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5882         else
5883                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5884
5885         if (has_panel) {
5886                 temp &= ~DREF_SSC_SOURCE_MASK;
5887                 temp |= DREF_SSC_SOURCE_ENABLE;
5888
5889                 /* SSC must be turned on before enabling the CPU output  */
5890                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5891                         DRM_DEBUG_KMS("Using SSC on panel\n");
5892                         temp |= DREF_SSC1_ENABLE;
5893                 } else
5894                         temp &= ~DREF_SSC1_ENABLE;
5895
5896                 /* Get SSC going before enabling the outputs */
5897                 I915_WRITE(PCH_DREF_CONTROL, temp);
5898                 POSTING_READ(PCH_DREF_CONTROL);
5899                 udelay(200);
5900
5901                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5902
5903                 /* Enable CPU source on CPU attached eDP */
5904                 if (has_cpu_edp) {
5905                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5906                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5907                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5908                         }
5909                         else
5910                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5911                 } else
5912                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5913
5914                 I915_WRITE(PCH_DREF_CONTROL, temp);
5915                 POSTING_READ(PCH_DREF_CONTROL);
5916                 udelay(200);
5917         } else {
5918                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5919
5920                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5921
5922                 /* Turn off CPU output */
5923                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5924
5925                 I915_WRITE(PCH_DREF_CONTROL, temp);
5926                 POSTING_READ(PCH_DREF_CONTROL);
5927                 udelay(200);
5928
5929                 /* Turn off the SSC source */
5930                 temp &= ~DREF_SSC_SOURCE_MASK;
5931                 temp |= DREF_SSC_SOURCE_DISABLE;
5932
5933                 /* Turn off SSC1 */
5934                 temp &= ~ DREF_SSC1_ENABLE;
5935
5936                 I915_WRITE(PCH_DREF_CONTROL, temp);
5937                 POSTING_READ(PCH_DREF_CONTROL);
5938                 udelay(200);
5939         }
5940 }
5941
5942 static int ironlake_get_refclk(struct drm_crtc *crtc)
5943 {
5944         struct drm_device *dev = crtc->dev;
5945         struct drm_i915_private *dev_priv = dev->dev_private;
5946         struct intel_encoder *encoder;
5947         struct drm_mode_config *mode_config = &dev->mode_config;
5948         struct intel_encoder *edp_encoder = NULL;
5949         int num_connectors = 0;
5950         bool is_lvds = false;
5951
5952         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5953                 if (encoder->base.crtc != crtc)
5954                         continue;
5955
5956                 switch (encoder->type) {
5957                 case INTEL_OUTPUT_LVDS:
5958                         is_lvds = true;
5959                         break;
5960                 case INTEL_OUTPUT_EDP:
5961                         edp_encoder = encoder;
5962                         break;
5963                 }
5964                 num_connectors++;
5965         }
5966
5967         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5968                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5969                               dev_priv->lvds_ssc_freq);
5970                 return dev_priv->lvds_ssc_freq * 1000;
5971         }
5972
5973         return 120000;
5974 }
5975
5976 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5977                                   struct drm_display_mode *mode,
5978                                   struct drm_display_mode *adjusted_mode,
5979                                   int x, int y,
5980                                   struct drm_framebuffer *old_fb)
5981 {
5982         struct drm_device *dev = crtc->dev;
5983         struct drm_i915_private *dev_priv = dev->dev_private;
5984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5985         int pipe = intel_crtc->pipe;
5986         int plane = intel_crtc->plane;
5987         int refclk, num_connectors = 0;
5988         intel_clock_t clock, reduced_clock;
5989         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5990         bool ok, has_reduced_clock = false, is_sdvo = false;
5991         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5992         struct drm_mode_config *mode_config = &dev->mode_config;
5993         struct intel_encoder *encoder, *edp_encoder = NULL;
5994         const intel_limit_t *limit;
5995         int ret;
5996         struct fdi_m_n m_n = {0};
5997         u32 temp;
5998         u32 lvds_sync = 0;
5999         int target_clock, pixel_multiplier, lane, link_bw, factor;
6000         unsigned int pipe_bpp;
6001         bool dither;
6002         bool is_cpu_edp = false, is_pch_edp = false;
6003
6004         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6005                 if (encoder->base.crtc != crtc)
6006                         continue;
6007
6008                 switch (encoder->type) {
6009                 case INTEL_OUTPUT_LVDS:
6010                         is_lvds = true;
6011                         break;
6012                 case INTEL_OUTPUT_SDVO:
6013                 case INTEL_OUTPUT_HDMI:
6014                         is_sdvo = true;
6015                         if (encoder->needs_tv_clock)
6016                                 is_tv = true;
6017                         break;
6018                 case INTEL_OUTPUT_TVOUT:
6019                         is_tv = true;
6020                         break;
6021                 case INTEL_OUTPUT_ANALOG:
6022                         is_crt = true;
6023                         break;
6024                 case INTEL_OUTPUT_DISPLAYPORT:
6025                         is_dp = true;
6026                         break;
6027                 case INTEL_OUTPUT_EDP:
6028                         is_dp = true;
6029                         if (intel_encoder_is_pch_edp(&encoder->base))
6030                                 is_pch_edp = true;
6031                         else
6032                                 is_cpu_edp = true;
6033                         edp_encoder = encoder;
6034                         break;
6035                 }
6036
6037                 num_connectors++;
6038         }
6039
6040         refclk = ironlake_get_refclk(crtc);
6041
6042         /*
6043          * Returns a set of divisors for the desired target clock with the given
6044          * refclk, or FALSE.  The returned values represent the clock equation:
6045          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6046          */
6047         limit = intel_limit(crtc, refclk);
6048         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
6049                              &clock);
6050         if (!ok) {
6051                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6052                 return -EINVAL;
6053         }
6054
6055         /* Ensure that the cursor is valid for the new mode before changing... */
6056         intel_crtc_update_cursor(crtc, true);
6057
6058         if (is_lvds && dev_priv->lvds_downclock_avail) {
6059                 /*
6060                  * Ensure we match the reduced clock's P to the target clock.
6061                  * If the clocks don't match, we can't switch the display clock
6062                  * by using the FP0/FP1. In such case we will disable the LVDS
6063                  * downclock feature.
6064                 */
6065                 has_reduced_clock = limit->find_pll(limit, crtc,
6066                                                     dev_priv->lvds_downclock,
6067                                                     refclk,
6068                                                     &clock,
6069                                                     &reduced_clock);
6070         }
6071         /* SDVO TV has fixed PLL values depend on its clock range,
6072            this mirrors vbios setting. */
6073         if (is_sdvo && is_tv) {
6074                 if (adjusted_mode->clock >= 100000
6075                     && adjusted_mode->clock < 140500) {
6076                         clock.p1 = 2;
6077                         clock.p2 = 10;
6078                         clock.n = 3;
6079                         clock.m1 = 16;
6080                         clock.m2 = 8;
6081                 } else if (adjusted_mode->clock >= 140500
6082                            && adjusted_mode->clock <= 200000) {
6083                         clock.p1 = 1;
6084                         clock.p2 = 10;
6085                         clock.n = 6;
6086                         clock.m1 = 12;
6087                         clock.m2 = 8;
6088                 }
6089         }
6090
6091         /* FDI link */
6092         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6093         lane = 0;
6094         /* CPU eDP doesn't require FDI link, so just set DP M/N
6095            according to current link config */
6096         if (is_cpu_edp) {
6097                 target_clock = mode->clock;
6098                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
6099         } else {
6100                 /* [e]DP over FDI requires target mode clock
6101                    instead of link clock */
6102                 if (is_dp)
6103                         target_clock = mode->clock;
6104                 else
6105                         target_clock = adjusted_mode->clock;
6106
6107                 /* FDI is a binary signal running at ~2.7GHz, encoding
6108                  * each output octet as 10 bits. The actual frequency
6109                  * is stored as a divider into a 100MHz clock, and the
6110                  * mode pixel clock is stored in units of 1KHz.
6111                  * Hence the bw of each lane in terms of the mode signal
6112                  * is:
6113                  */
6114                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6115         }
6116
6117         /* determine panel color depth */
6118         temp = I915_READ(PIPECONF(pipe));
6119         temp &= ~PIPE_BPC_MASK;
6120         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
6121         switch (pipe_bpp) {
6122         case 18:
6123                 temp |= PIPE_6BPC;
6124                 break;
6125         case 24:
6126                 temp |= PIPE_8BPC;
6127                 break;
6128         case 30:
6129                 temp |= PIPE_10BPC;
6130                 break;
6131         case 36:
6132                 temp |= PIPE_12BPC;
6133                 break;
6134         default:
6135                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
6136                         pipe_bpp);
6137                 temp |= PIPE_8BPC;
6138                 pipe_bpp = 24;
6139                 break;
6140         }
6141
6142         intel_crtc->bpp = pipe_bpp;
6143         I915_WRITE(PIPECONF(pipe), temp);
6144
6145         if (!lane) {
6146                 /*
6147                  * Account for spread spectrum to avoid
6148                  * oversubscribing the link. Max center spread
6149                  * is 2.5%; use 5% for safety's sake.
6150                  */
6151                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
6152                 lane = bps / (link_bw * 8) + 1;
6153         }
6154
6155         intel_crtc->fdi_lanes = lane;
6156
6157         if (pixel_multiplier > 1)
6158                 link_bw *= pixel_multiplier;
6159         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
6160                              &m_n);
6161
6162         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
6163         if (has_reduced_clock)
6164                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
6165                         reduced_clock.m2;
6166
6167         /* Enable autotuning of the PLL clock (if permissible) */
6168         factor = 21;
6169         if (is_lvds) {
6170                 if ((intel_panel_use_ssc(dev_priv) &&
6171                      dev_priv->lvds_ssc_freq == 100) ||
6172                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
6173                         factor = 25;
6174         } else if (is_sdvo && is_tv)
6175                 factor = 20;
6176
6177         if (clock.m < factor * clock.n)
6178                 fp |= FP_CB_TUNE;
6179
6180         dpll = 0;
6181
6182         if (is_lvds)
6183                 dpll |= DPLLB_MODE_LVDS;
6184         else
6185                 dpll |= DPLLB_MODE_DAC_SERIAL;
6186         if (is_sdvo) {
6187                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
6188                 if (pixel_multiplier > 1) {
6189                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6190                 }
6191                 dpll |= DPLL_DVO_HIGH_SPEED;
6192         }
6193         if (is_dp && !is_cpu_edp)
6194                 dpll |= DPLL_DVO_HIGH_SPEED;
6195
6196         /* compute bitmask from p1 value */
6197         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6198         /* also FPA1 */
6199         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6200
6201         switch (clock.p2) {
6202         case 5:
6203                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6204                 break;
6205         case 7:
6206                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6207                 break;
6208         case 10:
6209                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6210                 break;
6211         case 14:
6212                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6213                 break;
6214         }
6215
6216         if (is_sdvo && is_tv)
6217                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6218         else if (is_tv)
6219                 /* XXX: just matching BIOS for now */
6220                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
6221                 dpll |= 3;
6222         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6223                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6224         else
6225                 dpll |= PLL_REF_INPUT_DREFCLK;
6226
6227         /* setup pipeconf */
6228         pipeconf = I915_READ(PIPECONF(pipe));
6229
6230         /* Set up the display plane register */
6231         dspcntr = DISPPLANE_GAMMA_ENABLE;
6232
6233         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
6234         drm_mode_debug_printmodeline(mode);
6235
6236         /* PCH eDP needs FDI, but CPU eDP does not */
6237         if (!intel_crtc->no_pll) {
6238                 if (!is_cpu_edp) {
6239                         I915_WRITE(PCH_FP0(pipe), fp);
6240                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
6241
6242                         POSTING_READ(PCH_DPLL(pipe));
6243                         udelay(150);
6244                 }
6245         } else {
6246                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
6247                     fp == I915_READ(PCH_FP0(0))) {
6248                         intel_crtc->use_pll_a = true;
6249                         DRM_DEBUG_KMS("using pipe a dpll\n");
6250                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
6251                            fp == I915_READ(PCH_FP0(1))) {
6252                         intel_crtc->use_pll_a = false;
6253                         DRM_DEBUG_KMS("using pipe b dpll\n");
6254                 } else {
6255                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
6256                         return -EINVAL;
6257                 }
6258         }
6259
6260         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
6261          * This is an exception to the general rule that mode_set doesn't turn
6262          * things on.
6263          */
6264         if (is_lvds) {
6265                 temp = I915_READ(PCH_LVDS);
6266                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
6267                 if (HAS_PCH_CPT(dev)) {
6268                         temp &= ~PORT_TRANS_SEL_MASK;
6269                         temp |= PORT_TRANS_SEL_CPT(pipe);
6270                 } else {
6271                         if (pipe == 1)
6272                                 temp |= LVDS_PIPEB_SELECT;
6273                         else
6274                                 temp &= ~LVDS_PIPEB_SELECT;
6275                 }
6276
6277                 /* set the corresponsding LVDS_BORDER bit */
6278                 temp |= dev_priv->lvds_border_bits;
6279                 /* Set the B0-B3 data pairs corresponding to whether we're going to
6280                  * set the DPLLs for dual-channel mode or not.
6281                  */
6282                 if (clock.p2 == 7)
6283                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
6284                 else
6285                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
6286
6287                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
6288                  * appropriately here, but we need to look more thoroughly into how
6289                  * panels behave in the two modes.
6290                  */
6291                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
6292                         lvds_sync |= LVDS_HSYNC_POLARITY;
6293                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
6294                         lvds_sync |= LVDS_VSYNC_POLARITY;
6295                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
6296                     != lvds_sync) {
6297                         char flags[2] = "-+";
6298                         DRM_INFO("Changing LVDS panel from "
6299                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
6300                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
6301                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
6302                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
6303                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
6304                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
6305                         temp |= lvds_sync;
6306                 }
6307                 I915_WRITE(PCH_LVDS, temp);
6308         }
6309
6310         pipeconf &= ~PIPECONF_DITHER_EN;
6311         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
6312         if ((is_lvds && dev_priv->lvds_dither) || dither) {
6313                 pipeconf |= PIPECONF_DITHER_EN;
6314                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
6315         }
6316         if (is_dp && !is_cpu_edp) {
6317                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
6318         } else {
6319                 /* For non-DP output, clear any trans DP clock recovery setting.*/
6320                 I915_WRITE(TRANSDATA_M1(pipe), 0);
6321                 I915_WRITE(TRANSDATA_N1(pipe), 0);
6322                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
6323                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
6324         }
6325
6326         if (!intel_crtc->no_pll && (!edp_encoder || is_pch_edp)) {
6327                 I915_WRITE(PCH_DPLL(pipe), dpll);
6328
6329                 /* Wait for the clocks to stabilize. */
6330                 POSTING_READ(PCH_DPLL(pipe));
6331                 udelay(150);
6332
6333                 /* The pixel multiplier can only be updated once the
6334                  * DPLL is enabled and the clocks are stable.
6335                  *
6336                  * So write it again.
6337                  */
6338                 I915_WRITE(PCH_DPLL(pipe), dpll);
6339         }
6340
6341         intel_crtc->lowfreq_avail = false;
6342         if (!intel_crtc->no_pll) {
6343                 if (is_lvds && has_reduced_clock && i915_powersave) {
6344                         I915_WRITE(PCH_FP1(pipe), fp2);
6345                         intel_crtc->lowfreq_avail = true;
6346                         if (HAS_PIPE_CXSR(dev)) {
6347                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6348                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6349                         }
6350                 } else {
6351                         I915_WRITE(PCH_FP1(pipe), fp);
6352                         if (HAS_PIPE_CXSR(dev)) {
6353                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6354                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6355                         }
6356                 }
6357         }
6358
6359         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6360         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6361                 pipeconf |= PIPECONF_INTERLACED_ILK;
6362                 /* the chip adds 2 halflines automatically */
6363                 adjusted_mode->crtc_vtotal -= 1;
6364                 adjusted_mode->crtc_vblank_end -= 1;
6365                 I915_WRITE(VSYNCSHIFT(pipe),
6366                            adjusted_mode->crtc_hsync_start
6367                            - adjusted_mode->crtc_htotal/2);
6368         } else {
6369                 pipeconf |= PIPECONF_PROGRESSIVE;
6370                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6371         }
6372
6373         I915_WRITE(HTOTAL(pipe),
6374                    (adjusted_mode->crtc_hdisplay - 1) |
6375                    ((adjusted_mode->crtc_htotal - 1) << 16));
6376         I915_WRITE(HBLANK(pipe),
6377                    (adjusted_mode->crtc_hblank_start - 1) |
6378                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6379         I915_WRITE(HSYNC(pipe),
6380                    (adjusted_mode->crtc_hsync_start - 1) |
6381                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6382
6383         I915_WRITE(VTOTAL(pipe),
6384                    (adjusted_mode->crtc_vdisplay - 1) |
6385                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6386         I915_WRITE(VBLANK(pipe),
6387                    (adjusted_mode->crtc_vblank_start - 1) |
6388                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6389         I915_WRITE(VSYNC(pipe),
6390                    (adjusted_mode->crtc_vsync_start - 1) |
6391                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6392
6393         /* pipesrc controls the size that is scaled from, which should
6394          * always be the user's requested size.
6395          */
6396         I915_WRITE(PIPESRC(pipe),
6397                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6398
6399         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6400         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6401         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6402         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6403
6404         if (is_cpu_edp)
6405                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6406
6407         I915_WRITE(PIPECONF(pipe), pipeconf);
6408         POSTING_READ(PIPECONF(pipe));
6409
6410         intel_wait_for_vblank(dev, pipe);
6411
6412         I915_WRITE(DSPCNTR(plane), dspcntr);
6413         POSTING_READ(DSPCNTR(plane));
6414
6415         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6416
6417         intel_update_watermarks(dev);
6418
6419         return ret;
6420 }
6421
6422 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6423                                struct drm_display_mode *mode,
6424                                struct drm_display_mode *adjusted_mode,
6425                                int x, int y,
6426                                struct drm_framebuffer *old_fb)
6427 {
6428         struct drm_device *dev = crtc->dev;
6429         struct drm_i915_private *dev_priv = dev->dev_private;
6430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431         int pipe = intel_crtc->pipe;
6432         int ret;
6433
6434         drm_vblank_pre_modeset(dev, pipe);
6435
6436         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6437                                               x, y, old_fb);
6438         drm_vblank_post_modeset(dev, pipe);
6439
6440         if (ret)
6441                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6442         else
6443                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6444
6445         return ret;
6446 }
6447
6448 static bool intel_eld_uptodate(struct drm_connector *connector,
6449                                int reg_eldv, uint32_t bits_eldv,
6450                                int reg_elda, uint32_t bits_elda,
6451                                int reg_edid)
6452 {
6453         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6454         uint8_t *eld = connector->eld;
6455         uint32_t i;
6456
6457         i = I915_READ(reg_eldv);
6458         i &= bits_eldv;
6459
6460         if (!eld[0])
6461                 return !i;
6462
6463         if (!i)
6464                 return false;
6465
6466         i = I915_READ(reg_elda);
6467         i &= ~bits_elda;
6468         I915_WRITE(reg_elda, i);
6469
6470         for (i = 0; i < eld[2]; i++)
6471                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6472                         return false;
6473
6474         return true;
6475 }
6476
6477 static void g4x_write_eld(struct drm_connector *connector,
6478                           struct drm_crtc *crtc)
6479 {
6480         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6481         uint8_t *eld = connector->eld;
6482         uint32_t eldv;
6483         uint32_t len;
6484         uint32_t i;
6485
6486         i = I915_READ(G4X_AUD_VID_DID);
6487
6488         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6489                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6490         else
6491                 eldv = G4X_ELDV_DEVCTG;
6492
6493         if (intel_eld_uptodate(connector,
6494                                G4X_AUD_CNTL_ST, eldv,
6495                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6496                                G4X_HDMIW_HDMIEDID))
6497                 return;
6498
6499         i = I915_READ(G4X_AUD_CNTL_ST);
6500         i &= ~(eldv | G4X_ELD_ADDR);
6501         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6502         I915_WRITE(G4X_AUD_CNTL_ST, i);
6503
6504         if (!eld[0])
6505                 return;
6506
6507         len = min_t(uint8_t, eld[2], len);
6508         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6509         for (i = 0; i < len; i++)
6510                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6511
6512         i = I915_READ(G4X_AUD_CNTL_ST);
6513         i |= eldv;
6514         I915_WRITE(G4X_AUD_CNTL_ST, i);
6515 }
6516
6517 static void ironlake_write_eld(struct drm_connector *connector,
6518                                      struct drm_crtc *crtc)
6519 {
6520         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6521         uint8_t *eld = connector->eld;
6522         uint32_t eldv;
6523         uint32_t i;
6524         int len;
6525         int hdmiw_hdmiedid;
6526         int aud_config;
6527         int aud_cntl_st;
6528         int aud_cntrl_st2;
6529
6530         if (HAS_PCH_IBX(connector->dev)) {
6531                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6532                 aud_config = IBX_AUD_CONFIG_A;
6533                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6534                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6535         } else {
6536                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6537                 aud_config = CPT_AUD_CONFIG_A;
6538                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6539                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6540         }
6541
6542         i = to_intel_crtc(crtc)->pipe;
6543         hdmiw_hdmiedid += i * 0x100;
6544         aud_cntl_st += i * 0x100;
6545         aud_config += i * 0x100;
6546
6547         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6548
6549         i = I915_READ(aud_cntl_st);
6550         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6551         if (!i) {
6552                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6553                 /* operate blindly on all ports */
6554                 eldv = IBX_ELD_VALIDB;
6555                 eldv |= IBX_ELD_VALIDB << 4;
6556                 eldv |= IBX_ELD_VALIDB << 8;
6557         } else {
6558                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6559                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6560         }
6561
6562         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6563                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6564                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6565                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6566         } else
6567                 I915_WRITE(aud_config, 0);
6568
6569         if (intel_eld_uptodate(connector,
6570                                aud_cntrl_st2, eldv,
6571                                aud_cntl_st, IBX_ELD_ADDRESS,
6572                                hdmiw_hdmiedid))
6573                 return;
6574
6575         i = I915_READ(aud_cntrl_st2);
6576         i &= ~eldv;
6577         I915_WRITE(aud_cntrl_st2, i);
6578
6579         if (!eld[0])
6580                 return;
6581
6582         i = I915_READ(aud_cntl_st);
6583         i &= ~IBX_ELD_ADDRESS;
6584         I915_WRITE(aud_cntl_st, i);
6585
6586         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6587         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6588         for (i = 0; i < len; i++)
6589                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6590
6591         i = I915_READ(aud_cntrl_st2);
6592         i |= eldv;
6593         I915_WRITE(aud_cntrl_st2, i);
6594 }
6595
6596 void intel_write_eld(struct drm_encoder *encoder,
6597                      struct drm_display_mode *mode)
6598 {
6599         struct drm_crtc *crtc = encoder->crtc;
6600         struct drm_connector *connector;
6601         struct drm_device *dev = encoder->dev;
6602         struct drm_i915_private *dev_priv = dev->dev_private;
6603
6604         connector = drm_select_eld(encoder, mode);
6605         if (!connector)
6606                 return;
6607
6608         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6609                          connector->base.id,
6610                          drm_get_connector_name(connector),
6611                          connector->encoder->base.id,
6612                          drm_get_encoder_name(connector->encoder));
6613
6614         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6615
6616         if (dev_priv->display.write_eld)
6617                 dev_priv->display.write_eld(connector, crtc);
6618 }
6619
6620 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6621 void intel_crtc_load_lut(struct drm_crtc *crtc)
6622 {
6623         struct drm_device *dev = crtc->dev;
6624         struct drm_i915_private *dev_priv = dev->dev_private;
6625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6626         int palreg = PALETTE(intel_crtc->pipe);
6627         int i;
6628
6629         /* The clocks have to be on to load the palette. */
6630         if (!crtc->enabled || !intel_crtc->active)
6631                 return;
6632
6633         /* use legacy palette for Ironlake */
6634         if (HAS_PCH_SPLIT(dev))
6635                 palreg = LGC_PALETTE(intel_crtc->pipe);
6636
6637         for (i = 0; i < 256; i++) {
6638                 I915_WRITE(palreg + 4 * i,
6639                            (intel_crtc->lut_r[i] << 16) |
6640                            (intel_crtc->lut_g[i] << 8) |
6641                            intel_crtc->lut_b[i]);
6642         }
6643 }
6644
6645 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6646 {
6647         struct drm_device *dev = crtc->dev;
6648         struct drm_i915_private *dev_priv = dev->dev_private;
6649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650         bool visible = base != 0;
6651         u32 cntl;
6652
6653         if (intel_crtc->cursor_visible == visible)
6654                 return;
6655
6656         cntl = I915_READ(_CURACNTR);
6657         if (visible) {
6658                 /* On these chipsets we can only modify the base whilst
6659                  * the cursor is disabled.
6660                  */
6661                 I915_WRITE(_CURABASE, base);
6662
6663                 cntl &= ~(CURSOR_FORMAT_MASK);
6664                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6665                 cntl |= CURSOR_ENABLE |
6666                         CURSOR_GAMMA_ENABLE |
6667                         CURSOR_FORMAT_ARGB;
6668         } else
6669                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6670         I915_WRITE(_CURACNTR, cntl);
6671
6672         intel_crtc->cursor_visible = visible;
6673 }
6674
6675 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6676 {
6677         struct drm_device *dev = crtc->dev;
6678         struct drm_i915_private *dev_priv = dev->dev_private;
6679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6680         int pipe = intel_crtc->pipe;
6681         bool visible = base != 0;
6682
6683         if (intel_crtc->cursor_visible != visible) {
6684                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6685                 if (base) {
6686                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6687                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6688                         cntl |= pipe << 28; /* Connect to correct pipe */
6689                 } else {
6690                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6691                         cntl |= CURSOR_MODE_DISABLE;
6692                 }
6693                 I915_WRITE(CURCNTR(pipe), cntl);
6694
6695                 intel_crtc->cursor_visible = visible;
6696         }
6697         /* and commit changes on next vblank */
6698         I915_WRITE(CURBASE(pipe), base);
6699 }
6700
6701 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6702 {
6703         struct drm_device *dev = crtc->dev;
6704         struct drm_i915_private *dev_priv = dev->dev_private;
6705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6706         int pipe = intel_crtc->pipe;
6707         bool visible = base != 0;
6708
6709         if (intel_crtc->cursor_visible != visible) {
6710                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6711                 if (base) {
6712                         cntl &= ~CURSOR_MODE;
6713                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6714                 } else {
6715                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6716                         cntl |= CURSOR_MODE_DISABLE;
6717                 }
6718                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6719
6720                 intel_crtc->cursor_visible = visible;
6721         }
6722         /* and commit changes on next vblank */
6723         I915_WRITE(CURBASE_IVB(pipe), base);
6724 }
6725
6726 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6727 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6728                                      bool on)
6729 {
6730         struct drm_device *dev = crtc->dev;
6731         struct drm_i915_private *dev_priv = dev->dev_private;
6732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6733         int pipe = intel_crtc->pipe;
6734         int x = intel_crtc->cursor_x;
6735         int y = intel_crtc->cursor_y;
6736         u32 base, pos;
6737         bool visible;
6738
6739         pos = 0;
6740
6741         if (on && crtc->enabled && crtc->fb) {
6742                 base = intel_crtc->cursor_addr;
6743                 if (x > (int) crtc->fb->width)
6744                         base = 0;
6745
6746                 if (y > (int) crtc->fb->height)
6747                         base = 0;
6748         } else
6749                 base = 0;
6750
6751         if (x < 0) {
6752                 if (x + intel_crtc->cursor_width < 0)
6753                         base = 0;
6754
6755                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6756                 x = -x;
6757         }
6758         pos |= x << CURSOR_X_SHIFT;
6759
6760         if (y < 0) {
6761                 if (y + intel_crtc->cursor_height < 0)
6762                         base = 0;
6763
6764                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6765                 y = -y;
6766         }
6767         pos |= y << CURSOR_Y_SHIFT;
6768
6769         visible = base != 0;
6770         if (!visible && !intel_crtc->cursor_visible)
6771                 return;
6772
6773         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6774                 I915_WRITE(CURPOS_IVB(pipe), pos);
6775                 ivb_update_cursor(crtc, base);
6776         } else {
6777                 I915_WRITE(CURPOS(pipe), pos);
6778                 if (IS_845G(dev) || IS_I865G(dev))
6779                         i845_update_cursor(crtc, base);
6780                 else
6781                         i9xx_update_cursor(crtc, base);
6782         }
6783
6784         if (visible)
6785                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6786 }
6787
6788 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6789                                  struct drm_file *file,
6790                                  uint32_t handle,
6791                                  uint32_t width, uint32_t height)
6792 {
6793         struct drm_device *dev = crtc->dev;
6794         struct drm_i915_private *dev_priv = dev->dev_private;
6795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6796         struct drm_i915_gem_object *obj;
6797         uint32_t addr;
6798         int ret;
6799
6800         DRM_DEBUG_KMS("\n");
6801
6802         /* if we want to turn off the cursor ignore width and height */
6803         if (!handle) {
6804                 DRM_DEBUG_KMS("cursor off\n");
6805                 addr = 0;
6806                 obj = NULL;
6807                 mutex_lock(&dev->struct_mutex);
6808                 goto finish;
6809         }
6810
6811         /* Currently we only support 64x64 cursors */
6812         if (width != 64 || height != 64) {
6813                 DRM_ERROR("we currently only support 64x64 cursors\n");
6814                 return -EINVAL;
6815         }
6816
6817         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6818         if (&obj->base == NULL)
6819                 return -ENOENT;
6820
6821         if (obj->base.size < width * height * 4) {
6822                 DRM_ERROR("buffer is to small\n");
6823                 ret = -ENOMEM;
6824                 goto fail;
6825         }
6826
6827         /* we only need to pin inside GTT if cursor is non-phy */
6828         mutex_lock(&dev->struct_mutex);
6829         if (!dev_priv->info->cursor_needs_physical) {
6830                 if (obj->tiling_mode) {
6831                         DRM_ERROR("cursor cannot be tiled\n");
6832                         ret = -EINVAL;
6833                         goto fail_locked;
6834                 }
6835
6836                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6837                 if (ret) {
6838                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6839                         goto fail_locked;
6840                 }
6841
6842                 ret = i915_gem_object_put_fence(obj);
6843                 if (ret) {
6844                         DRM_ERROR("failed to release fence for cursor");
6845                         goto fail_unpin;
6846                 }
6847
6848                 addr = obj->gtt_offset;
6849         } else {
6850                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6851                 ret = i915_gem_attach_phys_object(dev, obj,
6852                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6853                                                   align);
6854                 if (ret) {
6855                         DRM_ERROR("failed to attach phys object\n");
6856                         goto fail_locked;
6857                 }
6858                 addr = obj->phys_obj->handle->busaddr;
6859         }
6860
6861         if (IS_GEN2(dev))
6862                 I915_WRITE(CURSIZE, (height << 12) | width);
6863
6864  finish:
6865         if (intel_crtc->cursor_bo) {
6866                 if (dev_priv->info->cursor_needs_physical) {
6867                         if (intel_crtc->cursor_bo != obj)
6868                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6869                 } else
6870                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6871                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6872         }
6873
6874         mutex_unlock(&dev->struct_mutex);
6875
6876         intel_crtc->cursor_addr = addr;
6877         intel_crtc->cursor_bo = obj;
6878         intel_crtc->cursor_width = width;
6879         intel_crtc->cursor_height = height;
6880
6881         intel_crtc_update_cursor(crtc, true);
6882
6883         return 0;
6884 fail_unpin:
6885         i915_gem_object_unpin(obj);
6886 fail_locked:
6887         mutex_unlock(&dev->struct_mutex);
6888 fail:
6889         drm_gem_object_unreference_unlocked(&obj->base);
6890         return ret;
6891 }
6892
6893 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6894 {
6895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6896
6897         intel_crtc->cursor_x = x;
6898         intel_crtc->cursor_y = y;
6899
6900         intel_crtc_update_cursor(crtc, true);
6901
6902         return 0;
6903 }
6904
6905 /** Sets the color ramps on behalf of RandR */
6906 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6907                                  u16 blue, int regno)
6908 {
6909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910
6911         intel_crtc->lut_r[regno] = red >> 8;
6912         intel_crtc->lut_g[regno] = green >> 8;
6913         intel_crtc->lut_b[regno] = blue >> 8;
6914 }
6915
6916 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6917                              u16 *blue, int regno)
6918 {
6919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920
6921         *red = intel_crtc->lut_r[regno] << 8;
6922         *green = intel_crtc->lut_g[regno] << 8;
6923         *blue = intel_crtc->lut_b[regno] << 8;
6924 }
6925
6926 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6927                                  u16 *blue, uint32_t start, uint32_t size)
6928 {
6929         int end = (start + size > 256) ? 256 : start + size, i;
6930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6931
6932         for (i = start; i < end; i++) {
6933                 intel_crtc->lut_r[i] = red[i] >> 8;
6934                 intel_crtc->lut_g[i] = green[i] >> 8;
6935                 intel_crtc->lut_b[i] = blue[i] >> 8;
6936         }
6937
6938         intel_crtc_load_lut(crtc);
6939 }
6940
6941 /**
6942  * Get a pipe with a simple mode set on it for doing load-based monitor
6943  * detection.
6944  *
6945  * It will be up to the load-detect code to adjust the pipe as appropriate for
6946  * its requirements.  The pipe will be connected to no other encoders.
6947  *
6948  * Currently this code will only succeed if there is a pipe with no encoders
6949  * configured for it.  In the future, it could choose to temporarily disable
6950  * some outputs to free up a pipe for its use.
6951  *
6952  * \return crtc, or NULL if no pipes are available.
6953  */
6954
6955 /* VESA 640x480x72Hz mode to set on the pipe */
6956 static struct drm_display_mode load_detect_mode = {
6957         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6958                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6959 };
6960
6961 static struct drm_framebuffer *
6962 intel_framebuffer_create(struct drm_device *dev,
6963                          struct drm_mode_fb_cmd2 *mode_cmd,
6964                          struct drm_i915_gem_object *obj)
6965 {
6966         struct intel_framebuffer *intel_fb;
6967         int ret;
6968
6969         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6970         if (!intel_fb) {
6971                 drm_gem_object_unreference_unlocked(&obj->base);
6972                 return ERR_PTR(-ENOMEM);
6973         }
6974
6975         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6976         if (ret) {
6977                 drm_gem_object_unreference_unlocked(&obj->base);
6978                 kfree(intel_fb);
6979                 return ERR_PTR(ret);
6980         }
6981
6982         return &intel_fb->base;
6983 }
6984
6985 static u32
6986 intel_framebuffer_pitch_for_width(int width, int bpp)
6987 {
6988         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6989         return ALIGN(pitch, 64);
6990 }
6991
6992 static u32
6993 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6994 {
6995         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6996         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6997 }
6998
6999 static struct drm_framebuffer *
7000 intel_framebuffer_create_for_mode(struct drm_device *dev,
7001                                   struct drm_display_mode *mode,
7002                                   int depth, int bpp)
7003 {
7004         struct drm_i915_gem_object *obj;
7005         struct drm_mode_fb_cmd2 mode_cmd;
7006
7007         obj = i915_gem_alloc_object(dev,
7008                                     intel_framebuffer_size_for_mode(mode, bpp));
7009         if (obj == NULL)
7010                 return ERR_PTR(-ENOMEM);
7011
7012         mode_cmd.width = mode->hdisplay;
7013         mode_cmd.height = mode->vdisplay;
7014         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7015                                                                 bpp);
7016         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7017
7018         return intel_framebuffer_create(dev, &mode_cmd, obj);
7019 }
7020
7021 static struct drm_framebuffer *
7022 mode_fits_in_fbdev(struct drm_device *dev,
7023                    struct drm_display_mode *mode)
7024 {
7025         struct drm_i915_private *dev_priv = dev->dev_private;
7026         struct drm_i915_gem_object *obj;
7027         struct drm_framebuffer *fb;
7028
7029         if (dev_priv->fbdev == NULL)
7030                 return NULL;
7031
7032         obj = dev_priv->fbdev->ifb.obj;
7033         if (obj == NULL)
7034                 return NULL;
7035
7036         fb = &dev_priv->fbdev->ifb.base;
7037         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7038                                                                fb->bits_per_pixel))
7039                 return NULL;
7040
7041         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7042                 return NULL;
7043
7044         return fb;
7045 }
7046
7047 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
7048                                 struct drm_connector *connector,
7049                                 struct drm_display_mode *mode,
7050                                 struct intel_load_detect_pipe *old)
7051 {
7052         struct intel_crtc *intel_crtc;
7053         struct drm_crtc *possible_crtc;
7054         struct drm_encoder *encoder = &intel_encoder->base;
7055         struct drm_crtc *crtc = NULL;
7056         struct drm_device *dev = encoder->dev;
7057         struct drm_framebuffer *old_fb;
7058         int i = -1;
7059
7060         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7061                       connector->base.id, drm_get_connector_name(connector),
7062                       encoder->base.id, drm_get_encoder_name(encoder));
7063
7064         /*
7065          * Algorithm gets a little messy:
7066          *
7067          *   - if the connector already has an assigned crtc, use it (but make
7068          *     sure it's on first)
7069          *
7070          *   - try to find the first unused crtc that can drive this connector,
7071          *     and use that if we find one
7072          */
7073
7074         /* See if we already have a CRTC for this connector */
7075         if (encoder->crtc) {
7076                 crtc = encoder->crtc;
7077
7078                 intel_crtc = to_intel_crtc(crtc);
7079                 old->dpms_mode = intel_crtc->dpms_mode;
7080                 old->load_detect_temp = false;
7081
7082                 /* Make sure the crtc and connector are running */
7083                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
7084                         struct drm_encoder_helper_funcs *encoder_funcs;
7085                         struct drm_crtc_helper_funcs *crtc_funcs;
7086
7087                         crtc_funcs = crtc->helper_private;
7088                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
7089
7090                         encoder_funcs = encoder->helper_private;
7091                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
7092                 }
7093
7094                 return true;
7095         }
7096
7097         /* Find an unused one (if possible) */
7098         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7099                 i++;
7100                 if (!(encoder->possible_crtcs & (1 << i)))
7101                         continue;
7102                 if (!possible_crtc->enabled) {
7103                         crtc = possible_crtc;
7104                         break;
7105                 }
7106         }
7107
7108         /*
7109          * If we didn't find an unused CRTC, don't use any.
7110          */
7111         if (!crtc) {
7112                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7113                 return false;
7114         }
7115
7116         encoder->crtc = crtc;
7117         connector->encoder = encoder;
7118
7119         intel_crtc = to_intel_crtc(crtc);
7120         old->dpms_mode = intel_crtc->dpms_mode;
7121         old->load_detect_temp = true;
7122         old->release_fb = NULL;
7123
7124         if (!mode)
7125                 mode = &load_detect_mode;
7126
7127         old_fb = crtc->fb;
7128
7129         /* We need a framebuffer large enough to accommodate all accesses
7130          * that the plane may generate whilst we perform load detection.
7131          * We can not rely on the fbcon either being present (we get called
7132          * during its initialisation to detect all boot displays, or it may
7133          * not even exist) or that it is large enough to satisfy the
7134          * requested mode.
7135          */
7136         crtc->fb = mode_fits_in_fbdev(dev, mode);
7137         if (crtc->fb == NULL) {
7138                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7139                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7140                 old->release_fb = crtc->fb;
7141         } else
7142                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7143         if (IS_ERR(crtc->fb)) {
7144                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7145                 crtc->fb = old_fb;
7146                 return false;
7147         }
7148
7149         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
7150                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7151                 if (old->release_fb)
7152                         old->release_fb->funcs->destroy(old->release_fb);
7153                 crtc->fb = old_fb;
7154                 return false;
7155         }
7156
7157         /* let the connector get through one full cycle before testing */
7158         intel_wait_for_vblank(dev, intel_crtc->pipe);
7159
7160         return true;
7161 }
7162
7163 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
7164                                     struct drm_connector *connector,
7165                                     struct intel_load_detect_pipe *old)
7166 {
7167         struct drm_encoder *encoder = &intel_encoder->base;
7168         struct drm_device *dev = encoder->dev;
7169         struct drm_crtc *crtc = encoder->crtc;
7170         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
7171         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
7172
7173         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7174                       connector->base.id, drm_get_connector_name(connector),
7175                       encoder->base.id, drm_get_encoder_name(encoder));
7176
7177         if (old->load_detect_temp) {
7178                 connector->encoder = NULL;
7179                 drm_helper_disable_unused_functions(dev);
7180
7181                 if (old->release_fb)
7182                         old->release_fb->funcs->destroy(old->release_fb);
7183
7184                 return;
7185         }
7186
7187         /* Switch crtc and encoder back off if necessary */
7188         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
7189                 encoder_funcs->dpms(encoder, old->dpms_mode);
7190                 crtc_funcs->dpms(crtc, old->dpms_mode);
7191         }
7192 }
7193
7194 /* Returns the clock of the currently programmed mode of the given pipe. */
7195 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
7196 {
7197         struct drm_i915_private *dev_priv = dev->dev_private;
7198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199         int pipe = intel_crtc->pipe;
7200         u32 dpll = I915_READ(DPLL(pipe));
7201         u32 fp;
7202         intel_clock_t clock;
7203
7204         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7205                 fp = I915_READ(FP0(pipe));
7206         else
7207                 fp = I915_READ(FP1(pipe));
7208
7209         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7210         if (IS_PINEVIEW(dev)) {
7211                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7212                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7213         } else {
7214                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7215                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7216         }
7217
7218         if (!IS_GEN2(dev)) {
7219                 if (IS_PINEVIEW(dev))
7220                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7221                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7222                 else
7223                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7224                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7225
7226                 switch (dpll & DPLL_MODE_MASK) {
7227                 case DPLLB_MODE_DAC_SERIAL:
7228                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7229                                 5 : 10;
7230                         break;
7231                 case DPLLB_MODE_LVDS:
7232                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7233                                 7 : 14;
7234                         break;
7235                 default:
7236                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7237                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7238                         return 0;
7239                 }
7240
7241                 /* XXX: Handle the 100Mhz refclk */
7242                 intel_clock(dev, 96000, &clock);
7243         } else {
7244                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7245
7246                 if (is_lvds) {
7247                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7248                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7249                         clock.p2 = 14;
7250
7251                         if ((dpll & PLL_REF_INPUT_MASK) ==
7252                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7253                                 /* XXX: might not be 66MHz */
7254                                 intel_clock(dev, 66000, &clock);
7255                         } else
7256                                 intel_clock(dev, 48000, &clock);
7257                 } else {
7258                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7259                                 clock.p1 = 2;
7260                         else {
7261                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7262                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7263                         }
7264                         if (dpll & PLL_P2_DIVIDE_BY_4)
7265                                 clock.p2 = 4;
7266                         else
7267                                 clock.p2 = 2;
7268
7269                         intel_clock(dev, 48000, &clock);
7270                 }
7271         }
7272
7273         /* XXX: It would be nice to validate the clocks, but we can't reuse
7274          * i830PllIsValid() because it relies on the xf86_config connector
7275          * configuration being accurate, which it isn't necessarily.
7276          */
7277
7278         return clock.dot;
7279 }
7280
7281 /** Returns the currently programmed mode of the given pipe. */
7282 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7283                                              struct drm_crtc *crtc)
7284 {
7285         struct drm_i915_private *dev_priv = dev->dev_private;
7286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7287         int pipe = intel_crtc->pipe;
7288         struct drm_display_mode *mode;
7289         int htot = I915_READ(HTOTAL(pipe));
7290         int hsync = I915_READ(HSYNC(pipe));
7291         int vtot = I915_READ(VTOTAL(pipe));
7292         int vsync = I915_READ(VSYNC(pipe));
7293
7294         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7295         if (!mode)
7296                 return NULL;
7297
7298         mode->clock = intel_crtc_clock_get(dev, crtc);
7299         mode->hdisplay = (htot & 0xffff) + 1;
7300         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7301         mode->hsync_start = (hsync & 0xffff) + 1;
7302         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7303         mode->vdisplay = (vtot & 0xffff) + 1;
7304         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7305         mode->vsync_start = (vsync & 0xffff) + 1;
7306         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7307
7308         drm_mode_set_name(mode);
7309         drm_mode_set_crtcinfo(mode, 0);
7310
7311         return mode;
7312 }
7313
7314 #define GPU_IDLE_TIMEOUT 500 /* ms */
7315
7316 /* When this timer fires, we've been idle for awhile */
7317 static void intel_gpu_idle_timer(unsigned long arg)
7318 {
7319         struct drm_device *dev = (struct drm_device *)arg;
7320         drm_i915_private_t *dev_priv = dev->dev_private;
7321
7322         if (!list_empty(&dev_priv->mm.active_list)) {
7323                 /* Still processing requests, so just re-arm the timer. */
7324                 mod_timer(&dev_priv->idle_timer, jiffies +
7325                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7326                 return;
7327         }
7328
7329         dev_priv->busy = false;
7330         queue_work(dev_priv->wq, &dev_priv->idle_work);
7331 }
7332
7333 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7334
7335 static void intel_crtc_idle_timer(unsigned long arg)
7336 {
7337         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7338         struct drm_crtc *crtc = &intel_crtc->base;
7339         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7340         struct intel_framebuffer *intel_fb;
7341
7342         intel_fb = to_intel_framebuffer(crtc->fb);
7343         if (intel_fb && intel_fb->obj->active) {
7344                 /* The framebuffer is still being accessed by the GPU. */
7345                 mod_timer(&intel_crtc->idle_timer, jiffies +
7346                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7347                 return;
7348         }
7349
7350         intel_crtc->busy = false;
7351         queue_work(dev_priv->wq, &dev_priv->idle_work);
7352 }
7353
7354 static void intel_increase_pllclock(struct drm_crtc *crtc)
7355 {
7356         struct drm_device *dev = crtc->dev;
7357         drm_i915_private_t *dev_priv = dev->dev_private;
7358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7359         int pipe = intel_crtc->pipe;
7360         int dpll_reg = DPLL(pipe);
7361         int dpll;
7362
7363         if (HAS_PCH_SPLIT(dev))
7364                 return;
7365
7366         if (!dev_priv->lvds_downclock_avail)
7367                 return;
7368
7369         dpll = I915_READ(dpll_reg);
7370         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7371                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7372
7373                 assert_panel_unlocked(dev_priv, pipe);
7374
7375                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7376                 I915_WRITE(dpll_reg, dpll);
7377                 intel_wait_for_vblank(dev, pipe);
7378
7379                 dpll = I915_READ(dpll_reg);
7380                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7381                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7382         }
7383
7384         /* Schedule downclock */
7385         mod_timer(&intel_crtc->idle_timer, jiffies +
7386                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7387 }
7388
7389 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7390 {
7391         struct drm_device *dev = crtc->dev;
7392         drm_i915_private_t *dev_priv = dev->dev_private;
7393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7394         int pipe = intel_crtc->pipe;
7395         int dpll_reg = DPLL(pipe);
7396         int dpll = I915_READ(dpll_reg);
7397
7398         if (HAS_PCH_SPLIT(dev))
7399                 return;
7400
7401         if (!dev_priv->lvds_downclock_avail)
7402                 return;
7403
7404         /*
7405          * Since this is called by a timer, we should never get here in
7406          * the manual case.
7407          */
7408         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7409                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7410
7411                 assert_panel_unlocked(dev_priv, pipe);
7412
7413                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7414                 I915_WRITE(dpll_reg, dpll);
7415                 intel_wait_for_vblank(dev, pipe);
7416                 dpll = I915_READ(dpll_reg);
7417                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7418                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7419         }
7420
7421 }
7422
7423 /**
7424  * intel_idle_update - adjust clocks for idleness
7425  * @work: work struct
7426  *
7427  * Either the GPU or display (or both) went idle.  Check the busy status
7428  * here and adjust the CRTC and GPU clocks as necessary.
7429  */
7430 static void intel_idle_update(struct work_struct *work)
7431 {
7432         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7433                                                     idle_work);
7434         struct drm_device *dev = dev_priv->dev;
7435         struct drm_crtc *crtc;
7436         struct intel_crtc *intel_crtc;
7437
7438         if (!i915_powersave)
7439                 return;
7440
7441         mutex_lock(&dev->struct_mutex);
7442
7443         i915_update_gfx_val(dev_priv);
7444
7445         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7446                 /* Skip inactive CRTCs */
7447                 if (!crtc->fb)
7448                         continue;
7449
7450                 intel_crtc = to_intel_crtc(crtc);
7451                 if (!intel_crtc->busy)
7452                         intel_decrease_pllclock(crtc);
7453         }
7454
7455
7456         mutex_unlock(&dev->struct_mutex);
7457 }
7458
7459 /**
7460  * intel_mark_busy - mark the GPU and possibly the display busy
7461  * @dev: drm device
7462  * @obj: object we're operating on
7463  *
7464  * Callers can use this function to indicate that the GPU is busy processing
7465  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7466  * buffer), we'll also mark the display as busy, so we know to increase its
7467  * clock frequency.
7468  */
7469 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7470 {
7471         drm_i915_private_t *dev_priv = dev->dev_private;
7472         struct drm_crtc *crtc = NULL;
7473         struct intel_framebuffer *intel_fb;
7474         struct intel_crtc *intel_crtc;
7475
7476         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7477                 return;
7478
7479         if (!dev_priv->busy)
7480                 dev_priv->busy = true;
7481         else
7482                 mod_timer(&dev_priv->idle_timer, jiffies +
7483                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7484
7485         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7486                 if (!crtc->fb)
7487                         continue;
7488
7489                 intel_crtc = to_intel_crtc(crtc);
7490                 intel_fb = to_intel_framebuffer(crtc->fb);
7491                 if (intel_fb->obj == obj) {
7492                         if (!intel_crtc->busy) {
7493                                 /* Non-busy -> busy, upclock */
7494                                 intel_increase_pllclock(crtc);
7495                                 intel_crtc->busy = true;
7496                         } else {
7497                                 /* Busy -> busy, put off timer */
7498                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7499                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7500                         }
7501                 }
7502         }
7503 }
7504
7505 static void intel_crtc_destroy(struct drm_crtc *crtc)
7506 {
7507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7508         struct drm_device *dev = crtc->dev;
7509         struct intel_unpin_work *work;
7510         unsigned long flags;
7511
7512         spin_lock_irqsave(&dev->event_lock, flags);
7513         work = intel_crtc->unpin_work;
7514         intel_crtc->unpin_work = NULL;
7515         spin_unlock_irqrestore(&dev->event_lock, flags);
7516
7517         if (work) {
7518                 cancel_work_sync(&work->work);
7519                 kfree(work);
7520         }
7521
7522         drm_crtc_cleanup(crtc);
7523
7524         kfree(intel_crtc);
7525 }
7526
7527 static void intel_unpin_work_fn(struct work_struct *__work)
7528 {
7529         struct intel_unpin_work *work =
7530                 container_of(__work, struct intel_unpin_work, work);
7531
7532         mutex_lock(&work->dev->struct_mutex);
7533         intel_unpin_fb_obj(work->old_fb_obj);
7534         drm_gem_object_unreference(&work->pending_flip_obj->base);
7535         drm_gem_object_unreference(&work->old_fb_obj->base);
7536
7537         intel_update_fbc(work->dev);
7538         mutex_unlock(&work->dev->struct_mutex);
7539         kfree(work);
7540 }
7541
7542 static void do_intel_finish_page_flip(struct drm_device *dev,
7543                                       struct drm_crtc *crtc)
7544 {
7545         drm_i915_private_t *dev_priv = dev->dev_private;
7546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7547         struct intel_unpin_work *work;
7548         struct drm_i915_gem_object *obj;
7549         struct drm_pending_vblank_event *e;
7550         struct timeval tnow, tvbl;
7551         unsigned long flags;
7552
7553         /* Ignore early vblank irqs */
7554         if (intel_crtc == NULL)
7555                 return;
7556
7557         do_gettimeofday(&tnow);
7558
7559         spin_lock_irqsave(&dev->event_lock, flags);
7560         work = intel_crtc->unpin_work;
7561         if (work == NULL || !work->pending) {
7562                 spin_unlock_irqrestore(&dev->event_lock, flags);
7563                 return;
7564         }
7565
7566         intel_crtc->unpin_work = NULL;
7567
7568         if (work->event) {
7569                 e = work->event;
7570                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7571
7572                 /* Called before vblank count and timestamps have
7573                  * been updated for the vblank interval of flip
7574                  * completion? Need to increment vblank count and
7575                  * add one videorefresh duration to returned timestamp
7576                  * to account for this. We assume this happened if we
7577                  * get called over 0.9 frame durations after the last
7578                  * timestamped vblank.
7579                  *
7580                  * This calculation can not be used with vrefresh rates
7581                  * below 5Hz (10Hz to be on the safe side) without
7582                  * promoting to 64 integers.
7583                  */
7584                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7585                     9 * crtc->framedur_ns) {
7586                         e->event.sequence++;
7587                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7588                                              crtc->framedur_ns);
7589                 }
7590
7591                 e->event.tv_sec = tvbl.tv_sec;
7592                 e->event.tv_usec = tvbl.tv_usec;
7593
7594                 list_add_tail(&e->base.link,
7595                               &e->base.file_priv->event_list);
7596                 wake_up_interruptible(&e->base.file_priv->event_wait);
7597         }
7598
7599         drm_vblank_put(dev, intel_crtc->pipe);
7600
7601         spin_unlock_irqrestore(&dev->event_lock, flags);
7602
7603         obj = work->old_fb_obj;
7604
7605         atomic_clear_mask(1 << intel_crtc->plane,
7606                           &obj->pending_flip.counter);
7607         if (atomic_read(&obj->pending_flip) == 0)
7608                 wake_up(&dev_priv->pending_flip_queue);
7609
7610         schedule_work(&work->work);
7611
7612         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7613 }
7614
7615 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7616 {
7617         drm_i915_private_t *dev_priv = dev->dev_private;
7618         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7619
7620         do_intel_finish_page_flip(dev, crtc);
7621 }
7622
7623 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7624 {
7625         drm_i915_private_t *dev_priv = dev->dev_private;
7626         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7627
7628         do_intel_finish_page_flip(dev, crtc);
7629 }
7630
7631 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7632 {
7633         drm_i915_private_t *dev_priv = dev->dev_private;
7634         struct intel_crtc *intel_crtc =
7635                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7636         unsigned long flags;
7637
7638         spin_lock_irqsave(&dev->event_lock, flags);
7639         if (intel_crtc->unpin_work) {
7640                 if ((++intel_crtc->unpin_work->pending) > 1)
7641                         DRM_ERROR("Prepared flip multiple times\n");
7642         } else {
7643                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7644         }
7645         spin_unlock_irqrestore(&dev->event_lock, flags);
7646 }
7647
7648 static int intel_gen2_queue_flip(struct drm_device *dev,
7649                                  struct drm_crtc *crtc,
7650                                  struct drm_framebuffer *fb,
7651                                  struct drm_i915_gem_object *obj)
7652 {
7653         struct drm_i915_private *dev_priv = dev->dev_private;
7654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7655         unsigned long offset;
7656         u32 flip_mask;
7657         int ret;
7658
7659         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7660         if (ret)
7661                 goto out;
7662
7663         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7664         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7665
7666         ret = BEGIN_LP_RING(6);
7667         if (ret)
7668                 goto out;
7669
7670         /* Can't queue multiple flips, so wait for the previous
7671          * one to finish before executing the next.
7672          */
7673         if (intel_crtc->plane)
7674                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7675         else
7676                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7677         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7678         OUT_RING(MI_NOOP);
7679         OUT_RING(MI_DISPLAY_FLIP |
7680                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7681         OUT_RING(fb->pitches[0]);
7682         OUT_RING(obj->gtt_offset + offset);
7683         OUT_RING(0); /* aux display base address, unused */
7684         ADVANCE_LP_RING();
7685 out:
7686         return ret;
7687 }
7688
7689 static int intel_gen3_queue_flip(struct drm_device *dev,
7690                                  struct drm_crtc *crtc,
7691                                  struct drm_framebuffer *fb,
7692                                  struct drm_i915_gem_object *obj)
7693 {
7694         struct drm_i915_private *dev_priv = dev->dev_private;
7695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7696         unsigned long offset;
7697         u32 flip_mask;
7698         int ret;
7699
7700         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7701         if (ret)
7702                 goto out;
7703
7704         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7705         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7706
7707         ret = BEGIN_LP_RING(6);
7708         if (ret)
7709                 goto out;
7710
7711         if (intel_crtc->plane)
7712                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7713         else
7714                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7715         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7716         OUT_RING(MI_NOOP);
7717         OUT_RING(MI_DISPLAY_FLIP_I915 |
7718                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7719         OUT_RING(fb->pitches[0]);
7720         OUT_RING(obj->gtt_offset + offset);
7721         OUT_RING(MI_NOOP);
7722
7723         ADVANCE_LP_RING();
7724 out:
7725         return ret;
7726 }
7727
7728 static int intel_gen4_queue_flip(struct drm_device *dev,
7729                                  struct drm_crtc *crtc,
7730                                  struct drm_framebuffer *fb,
7731                                  struct drm_i915_gem_object *obj)
7732 {
7733         struct drm_i915_private *dev_priv = dev->dev_private;
7734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7735         uint32_t pf, pipesrc;
7736         int ret;
7737
7738         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7739         if (ret)
7740                 goto out;
7741
7742         ret = BEGIN_LP_RING(4);
7743         if (ret)
7744                 goto out;
7745
7746         /* i965+ uses the linear or tiled offsets from the
7747          * Display Registers (which do not change across a page-flip)
7748          * so we need only reprogram the base address.
7749          */
7750         OUT_RING(MI_DISPLAY_FLIP |
7751                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7752         OUT_RING(fb->pitches[0]);
7753         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7754
7755         /* XXX Enabling the panel-fitter across page-flip is so far
7756          * untested on non-native modes, so ignore it for now.
7757          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7758          */
7759         pf = 0;
7760         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7761         OUT_RING(pf | pipesrc);
7762         ADVANCE_LP_RING();
7763 out:
7764         return ret;
7765 }
7766
7767 static int intel_gen6_queue_flip(struct drm_device *dev,
7768                                  struct drm_crtc *crtc,
7769                                  struct drm_framebuffer *fb,
7770                                  struct drm_i915_gem_object *obj)
7771 {
7772         struct drm_i915_private *dev_priv = dev->dev_private;
7773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7774         uint32_t pf, pipesrc;
7775         int ret;
7776
7777         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7778         if (ret)
7779                 goto out;
7780
7781         ret = BEGIN_LP_RING(4);
7782         if (ret)
7783                 goto out;
7784
7785         OUT_RING(MI_DISPLAY_FLIP |
7786                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7787         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7788         OUT_RING(obj->gtt_offset);
7789
7790         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7791         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7792         OUT_RING(pf | pipesrc);
7793         ADVANCE_LP_RING();
7794 out:
7795         return ret;
7796 }
7797
7798 /*
7799  * On gen7 we currently use the blit ring because (in early silicon at least)
7800  * the render ring doesn't give us interrpts for page flip completion, which
7801  * means clients will hang after the first flip is queued.  Fortunately the
7802  * blit ring generates interrupts properly, so use it instead.
7803  */
7804 static int intel_gen7_queue_flip(struct drm_device *dev,
7805                                  struct drm_crtc *crtc,
7806                                  struct drm_framebuffer *fb,
7807                                  struct drm_i915_gem_object *obj)
7808 {
7809         struct drm_i915_private *dev_priv = dev->dev_private;
7810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7811         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7812         int ret;
7813
7814         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7815         if (ret)
7816                 goto out;
7817
7818         ret = intel_ring_begin(ring, 4);
7819         if (ret)
7820                 goto out;
7821
7822         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7823         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7824         intel_ring_emit(ring, (obj->gtt_offset));
7825         intel_ring_emit(ring, (MI_NOOP));
7826         intel_ring_advance(ring);
7827 out:
7828         return ret;
7829 }
7830
7831 static int intel_default_queue_flip(struct drm_device *dev,
7832                                     struct drm_crtc *crtc,
7833                                     struct drm_framebuffer *fb,
7834                                     struct drm_i915_gem_object *obj)
7835 {
7836         return -ENODEV;
7837 }
7838
7839 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7840                                 struct drm_framebuffer *fb,
7841                                 struct drm_pending_vblank_event *event)
7842 {
7843         struct drm_device *dev = crtc->dev;
7844         struct drm_i915_private *dev_priv = dev->dev_private;
7845         struct intel_framebuffer *intel_fb;
7846         struct drm_i915_gem_object *obj;
7847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7848         struct intel_unpin_work *work;
7849         unsigned long flags;
7850         int ret;
7851
7852         work = kzalloc(sizeof *work, GFP_KERNEL);
7853         if (work == NULL)
7854                 return -ENOMEM;
7855
7856         work->event = event;
7857         work->dev = crtc->dev;
7858         intel_fb = to_intel_framebuffer(crtc->fb);
7859         work->old_fb_obj = intel_fb->obj;
7860         INIT_WORK(&work->work, intel_unpin_work_fn);
7861
7862         ret = drm_vblank_get(dev, intel_crtc->pipe);
7863         if (ret)
7864                 goto free_work;
7865
7866         /* We borrow the event spin lock for protecting unpin_work */
7867         spin_lock_irqsave(&dev->event_lock, flags);
7868         if (intel_crtc->unpin_work) {
7869                 spin_unlock_irqrestore(&dev->event_lock, flags);
7870                 kfree(work);
7871                 drm_vblank_put(dev, intel_crtc->pipe);
7872
7873                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7874                 return -EBUSY;
7875         }
7876         intel_crtc->unpin_work = work;
7877         spin_unlock_irqrestore(&dev->event_lock, flags);
7878
7879         intel_fb = to_intel_framebuffer(fb);
7880         obj = intel_fb->obj;
7881
7882         mutex_lock(&dev->struct_mutex);
7883
7884         /* Reference the objects for the scheduled work. */
7885         drm_gem_object_reference(&work->old_fb_obj->base);
7886         drm_gem_object_reference(&obj->base);
7887
7888         crtc->fb = fb;
7889
7890         work->pending_flip_obj = obj;
7891
7892         work->enable_stall_check = true;
7893
7894         /* Block clients from rendering to the new back buffer until
7895          * the flip occurs and the object is no longer visible.
7896          */
7897         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7898
7899         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7900         if (ret)
7901                 goto cleanup_pending;
7902
7903         intel_disable_fbc(dev);
7904         mutex_unlock(&dev->struct_mutex);
7905
7906         trace_i915_flip_request(intel_crtc->plane, obj);
7907
7908         return 0;
7909
7910 cleanup_pending:
7911         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7912         drm_gem_object_unreference(&work->old_fb_obj->base);
7913         drm_gem_object_unreference(&obj->base);
7914         mutex_unlock(&dev->struct_mutex);
7915
7916         spin_lock_irqsave(&dev->event_lock, flags);
7917         intel_crtc->unpin_work = NULL;
7918         spin_unlock_irqrestore(&dev->event_lock, flags);
7919
7920         drm_vblank_put(dev, intel_crtc->pipe);
7921 free_work:
7922         kfree(work);
7923
7924         return ret;
7925 }
7926
7927 static void intel_sanitize_modesetting(struct drm_device *dev,
7928                                        int pipe, int plane)
7929 {
7930         struct drm_i915_private *dev_priv = dev->dev_private;
7931         u32 reg, val;
7932
7933         /* Clear any frame start delays used for debugging left by the BIOS */
7934         for_each_pipe(pipe) {
7935                 reg = PIPECONF(pipe);
7936                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7937         }
7938
7939         if (HAS_PCH_SPLIT(dev))
7940                 return;
7941
7942         /* Who knows what state these registers were left in by the BIOS or
7943          * grub?
7944          *
7945          * If we leave the registers in a conflicting state (e.g. with the
7946          * display plane reading from the other pipe than the one we intend
7947          * to use) then when we attempt to teardown the active mode, we will
7948          * not disable the pipes and planes in the correct order -- leaving
7949          * a plane reading from a disabled pipe and possibly leading to
7950          * undefined behaviour.
7951          */
7952
7953         reg = DSPCNTR(plane);
7954         val = I915_READ(reg);
7955
7956         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7957                 return;
7958         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7959                 return;
7960
7961         /* This display plane is active and attached to the other CPU pipe. */
7962         pipe = !pipe;
7963
7964         /* Disable the plane and wait for it to stop reading from the pipe. */
7965         intel_disable_plane(dev_priv, plane, pipe);
7966         intel_disable_pipe(dev_priv, pipe);
7967 }
7968
7969 static void intel_crtc_reset(struct drm_crtc *crtc)
7970 {
7971         struct drm_device *dev = crtc->dev;
7972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7973
7974         /* Reset flags back to the 'unknown' status so that they
7975          * will be correctly set on the initial modeset.
7976          */
7977         intel_crtc->dpms_mode = -1;
7978
7979         /* We need to fix up any BIOS configuration that conflicts with
7980          * our expectations.
7981          */
7982         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7983 }
7984
7985 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7986         .dpms = intel_crtc_dpms,
7987         .mode_fixup = intel_crtc_mode_fixup,
7988         .mode_set = intel_crtc_mode_set,
7989         .mode_set_base = intel_pipe_set_base,
7990         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7991         .load_lut = intel_crtc_load_lut,
7992         .disable = intel_crtc_disable,
7993 };
7994
7995 static const struct drm_crtc_funcs intel_crtc_funcs = {
7996         .reset = intel_crtc_reset,
7997         .cursor_set = intel_crtc_cursor_set,
7998         .cursor_move = intel_crtc_cursor_move,
7999         .gamma_set = intel_crtc_gamma_set,
8000         .set_config = drm_crtc_helper_set_config,
8001         .destroy = intel_crtc_destroy,
8002         .page_flip = intel_crtc_page_flip,
8003 };
8004
8005 static void intel_crtc_init(struct drm_device *dev, int pipe)
8006 {
8007         drm_i915_private_t *dev_priv = dev->dev_private;
8008         struct intel_crtc *intel_crtc;
8009         int i;
8010
8011         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8012         if (intel_crtc == NULL)
8013                 return;
8014
8015         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8016
8017         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8018         for (i = 0; i < 256; i++) {
8019                 intel_crtc->lut_r[i] = i;
8020                 intel_crtc->lut_g[i] = i;
8021                 intel_crtc->lut_b[i] = i;
8022         }
8023
8024         /* Swap pipes & planes for FBC on pre-965 */
8025         intel_crtc->pipe = pipe;
8026         intel_crtc->plane = pipe;
8027         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8028                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8029                 intel_crtc->plane = !pipe;
8030         }
8031
8032         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8033                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8034         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8035         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8036
8037         intel_crtc_reset(&intel_crtc->base);
8038         intel_crtc->active = true; /* force the pipe off on setup_init_config */
8039         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8040
8041         if (HAS_PCH_SPLIT(dev)) {
8042                 if (pipe == 2 && IS_IVYBRIDGE(dev))
8043                         intel_crtc->no_pll = true;
8044                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
8045                 intel_helper_funcs.commit = ironlake_crtc_commit;
8046         } else {
8047                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
8048                 intel_helper_funcs.commit = i9xx_crtc_commit;
8049         }
8050
8051         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8052
8053         intel_crtc->busy = false;
8054
8055         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
8056                     (unsigned long)intel_crtc);
8057 }
8058
8059 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8060                                 struct drm_file *file)
8061 {
8062         drm_i915_private_t *dev_priv = dev->dev_private;
8063         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8064         struct drm_mode_object *drmmode_obj;
8065         struct intel_crtc *crtc;
8066
8067         if (!dev_priv) {
8068                 DRM_ERROR("called with no initialization\n");
8069                 return -EINVAL;
8070         }
8071
8072         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8073                         DRM_MODE_OBJECT_CRTC);
8074
8075         if (!drmmode_obj) {
8076                 DRM_ERROR("no such CRTC id\n");
8077                 return -EINVAL;
8078         }
8079
8080         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8081         pipe_from_crtc_id->pipe = crtc->pipe;
8082
8083         return 0;
8084 }
8085
8086 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
8087 {
8088         struct intel_encoder *encoder;
8089         int index_mask = 0;
8090         int entry = 0;
8091
8092         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8093                 if (type_mask & encoder->clone_mask)
8094                         index_mask |= (1 << entry);
8095                 entry++;
8096         }
8097
8098         return index_mask;
8099 }
8100
8101 static bool has_edp_a(struct drm_device *dev)
8102 {
8103         struct drm_i915_private *dev_priv = dev->dev_private;
8104
8105         if (!IS_MOBILE(dev))
8106                 return false;
8107
8108         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8109                 return false;
8110
8111         if (IS_GEN5(dev) &&
8112             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8113                 return false;
8114
8115         return true;
8116 }
8117
8118 static void intel_setup_outputs(struct drm_device *dev)
8119 {
8120         struct drm_i915_private *dev_priv = dev->dev_private;
8121         struct intel_encoder *encoder;
8122         bool dpd_is_edp = false;
8123         bool has_lvds;
8124
8125         has_lvds = intel_lvds_init(dev);
8126         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8127                 /* disable the panel fitter on everything but LVDS */
8128                 I915_WRITE(PFIT_CONTROL, 0);
8129         }
8130
8131         if (HAS_PCH_SPLIT(dev)) {
8132                 dpd_is_edp = intel_dpd_is_edp(dev);
8133
8134                 if (has_edp_a(dev))
8135                         intel_dp_init(dev, DP_A);
8136
8137                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8138                         intel_dp_init(dev, PCH_DP_D);
8139         }
8140
8141         intel_crt_init(dev);
8142
8143         if (HAS_PCH_SPLIT(dev)) {
8144                 int found;
8145
8146                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8147                         /* PCH SDVOB multiplex with HDMIB */
8148                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8149                         if (!found)
8150                                 intel_hdmi_init(dev, HDMIB);
8151                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8152                                 intel_dp_init(dev, PCH_DP_B);
8153                 }
8154
8155                 if (I915_READ(HDMIC) & PORT_DETECTED)
8156                         intel_hdmi_init(dev, HDMIC);
8157
8158                 if (I915_READ(HDMID) & PORT_DETECTED)
8159                         intel_hdmi_init(dev, HDMID);
8160
8161                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8162                         intel_dp_init(dev, PCH_DP_C);
8163
8164                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8165                         intel_dp_init(dev, PCH_DP_D);
8166
8167         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8168                 bool found = false;
8169
8170                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8171                         DRM_DEBUG_KMS("probing SDVOB\n");
8172                         found = intel_sdvo_init(dev, SDVOB, true);
8173                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8174                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8175                                 intel_hdmi_init(dev, SDVOB);
8176                         }
8177
8178                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8179                                 DRM_DEBUG_KMS("probing DP_B\n");
8180                                 intel_dp_init(dev, DP_B);
8181                         }
8182                 }
8183
8184                 /* Before G4X SDVOC doesn't have its own detect register */
8185
8186                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8187                         DRM_DEBUG_KMS("probing SDVOC\n");
8188                         found = intel_sdvo_init(dev, SDVOC, false);
8189                 }
8190
8191                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8192
8193                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8194                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8195                                 intel_hdmi_init(dev, SDVOC);
8196                         }
8197                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8198                                 DRM_DEBUG_KMS("probing DP_C\n");
8199                                 intel_dp_init(dev, DP_C);
8200                         }
8201                 }
8202
8203                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8204                     (I915_READ(DP_D) & DP_DETECTED)) {
8205                         DRM_DEBUG_KMS("probing DP_D\n");
8206                         intel_dp_init(dev, DP_D);
8207                 }
8208         } else if (IS_GEN2(dev))
8209                 intel_dvo_init(dev);
8210
8211         if (SUPPORTS_TV(dev))
8212                 intel_tv_init(dev);
8213
8214         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8215                 encoder->base.possible_crtcs = encoder->crtc_mask;
8216                 encoder->base.possible_clones =
8217                         intel_encoder_clones(dev, encoder->clone_mask);
8218         }
8219
8220         /* disable all the possible outputs/crtcs before entering KMS mode */
8221         drm_helper_disable_unused_functions(dev);
8222
8223         if (HAS_PCH_SPLIT(dev))
8224                 ironlake_init_pch_refclk(dev);
8225 }
8226
8227 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8228 {
8229         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8230
8231         drm_framebuffer_cleanup(fb);
8232         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8233
8234         kfree(intel_fb);
8235 }
8236
8237 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8238                                                 struct drm_file *file,
8239                                                 unsigned int *handle)
8240 {
8241         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8242         struct drm_i915_gem_object *obj = intel_fb->obj;
8243
8244         return drm_gem_handle_create(file, &obj->base, handle);
8245 }
8246
8247 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8248         .destroy = intel_user_framebuffer_destroy,
8249         .create_handle = intel_user_framebuffer_create_handle,
8250 };
8251
8252 int intel_framebuffer_init(struct drm_device *dev,
8253                            struct intel_framebuffer *intel_fb,
8254                            struct drm_mode_fb_cmd2 *mode_cmd,
8255                            struct drm_i915_gem_object *obj)
8256 {
8257         int ret;
8258
8259         if (obj->tiling_mode == I915_TILING_Y)
8260                 return -EINVAL;
8261
8262         if (mode_cmd->pitches[0] & 63)
8263                 return -EINVAL;
8264
8265         switch (mode_cmd->pixel_format) {
8266         case DRM_FORMAT_RGB332:
8267         case DRM_FORMAT_RGB565:
8268         case DRM_FORMAT_XRGB8888:
8269         case DRM_FORMAT_XBGR8888:
8270         case DRM_FORMAT_ARGB8888:
8271         case DRM_FORMAT_XRGB2101010:
8272         case DRM_FORMAT_ARGB2101010:
8273                 /* RGB formats are common across chipsets */
8274                 break;
8275         case DRM_FORMAT_YUYV:
8276         case DRM_FORMAT_UYVY:
8277         case DRM_FORMAT_YVYU:
8278         case DRM_FORMAT_VYUY:
8279                 break;
8280         default:
8281                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8282                                 mode_cmd->pixel_format);
8283                 return -EINVAL;
8284         }
8285
8286         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8287         if (ret) {
8288                 DRM_ERROR("framebuffer init failed %d\n", ret);
8289                 return ret;
8290         }
8291
8292         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8293         intel_fb->obj = obj;
8294         return 0;
8295 }
8296
8297 static struct drm_framebuffer *
8298 intel_user_framebuffer_create(struct drm_device *dev,
8299                               struct drm_file *filp,
8300                               struct drm_mode_fb_cmd2 *mode_cmd)
8301 {
8302         struct drm_i915_gem_object *obj;
8303
8304         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8305                                                 mode_cmd->handles[0]));
8306         if (&obj->base == NULL)
8307                 return ERR_PTR(-ENOENT);
8308
8309         return intel_framebuffer_create(dev, mode_cmd, obj);
8310 }
8311
8312 static const struct drm_mode_config_funcs intel_mode_funcs = {
8313         .fb_create = intel_user_framebuffer_create,
8314         .output_poll_changed = intel_fb_output_poll_changed,
8315 };
8316
8317 static struct drm_i915_gem_object *
8318 intel_alloc_context_page(struct drm_device *dev)
8319 {
8320         struct drm_i915_gem_object *ctx;
8321         int ret;
8322
8323         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8324
8325         ctx = i915_gem_alloc_object(dev, 4096);
8326         if (!ctx) {
8327                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8328                 return NULL;
8329         }
8330
8331         ret = i915_gem_object_pin(ctx, 4096, true);
8332         if (ret) {
8333                 DRM_ERROR("failed to pin power context: %d\n", ret);
8334                 goto err_unref;
8335         }
8336
8337         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8338         if (ret) {
8339                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8340                 goto err_unpin;
8341         }
8342
8343         return ctx;
8344
8345 err_unpin:
8346         i915_gem_object_unpin(ctx);
8347 err_unref:
8348         drm_gem_object_unreference(&ctx->base);
8349         mutex_unlock(&dev->struct_mutex);
8350         return NULL;
8351 }
8352
8353 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8354 {
8355         struct drm_i915_private *dev_priv = dev->dev_private;
8356         u16 rgvswctl;
8357
8358         rgvswctl = I915_READ16(MEMSWCTL);
8359         if (rgvswctl & MEMCTL_CMD_STS) {
8360                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8361                 return false; /* still busy with another command */
8362         }
8363
8364         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8365                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8366         I915_WRITE16(MEMSWCTL, rgvswctl);
8367         POSTING_READ16(MEMSWCTL);
8368
8369         rgvswctl |= MEMCTL_CMD_STS;
8370         I915_WRITE16(MEMSWCTL, rgvswctl);
8371
8372         return true;
8373 }
8374
8375 void ironlake_enable_drps(struct drm_device *dev)
8376 {
8377         struct drm_i915_private *dev_priv = dev->dev_private;
8378         u32 rgvmodectl = I915_READ(MEMMODECTL);
8379         u8 fmax, fmin, fstart, vstart;
8380
8381         /* Enable temp reporting */
8382         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8383         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8384
8385         /* 100ms RC evaluation intervals */
8386         I915_WRITE(RCUPEI, 100000);
8387         I915_WRITE(RCDNEI, 100000);
8388
8389         /* Set max/min thresholds to 90ms and 80ms respectively */
8390         I915_WRITE(RCBMAXAVG, 90000);
8391         I915_WRITE(RCBMINAVG, 80000);
8392
8393         I915_WRITE(MEMIHYST, 1);
8394
8395         /* Set up min, max, and cur for interrupt handling */
8396         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8397         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8398         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8399                 MEMMODE_FSTART_SHIFT;
8400
8401         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8402                 PXVFREQ_PX_SHIFT;
8403
8404         dev_priv->fmax = fmax; /* IPS callback will increase this */
8405         dev_priv->fstart = fstart;
8406
8407         dev_priv->max_delay = fstart;
8408         dev_priv->min_delay = fmin;
8409         dev_priv->cur_delay = fstart;
8410
8411         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8412                          fmax, fmin, fstart);
8413
8414         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8415
8416         /*
8417          * Interrupts will be enabled in ironlake_irq_postinstall
8418          */
8419
8420         I915_WRITE(VIDSTART, vstart);
8421         POSTING_READ(VIDSTART);
8422
8423         rgvmodectl |= MEMMODE_SWMODE_EN;
8424         I915_WRITE(MEMMODECTL, rgvmodectl);
8425
8426         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8427                 DRM_ERROR("stuck trying to change perf mode\n");
8428         msleep(1);
8429
8430         ironlake_set_drps(dev, fstart);
8431
8432         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8433                 I915_READ(0x112e0);
8434         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8435         dev_priv->last_count2 = I915_READ(0x112f4);
8436         getrawmonotonic(&dev_priv->last_time2);
8437 }
8438
8439 void ironlake_disable_drps(struct drm_device *dev)
8440 {
8441         struct drm_i915_private *dev_priv = dev->dev_private;
8442         u16 rgvswctl = I915_READ16(MEMSWCTL);
8443
8444         /* Ack interrupts, disable EFC interrupt */
8445         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8446         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8447         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8448         I915_WRITE(DEIIR, DE_PCU_EVENT);
8449         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8450
8451         /* Go back to the starting frequency */
8452         ironlake_set_drps(dev, dev_priv->fstart);
8453         msleep(1);
8454         rgvswctl |= MEMCTL_CMD_STS;
8455         I915_WRITE(MEMSWCTL, rgvswctl);
8456         msleep(1);
8457
8458 }
8459
8460 void gen6_set_rps(struct drm_device *dev, u8 val)
8461 {
8462         struct drm_i915_private *dev_priv = dev->dev_private;
8463         u32 swreq;
8464
8465         swreq = (val & 0x3ff) << 25;
8466         I915_WRITE(GEN6_RPNSWREQ, swreq);
8467 }
8468
8469 void gen6_disable_rps(struct drm_device *dev)
8470 {
8471         struct drm_i915_private *dev_priv = dev->dev_private;
8472
8473         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8474         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8475         I915_WRITE(GEN6_PMIER, 0);
8476         /* Complete PM interrupt masking here doesn't race with the rps work
8477          * item again unmasking PM interrupts because that is using a different
8478          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8479          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8480
8481         spin_lock_irq(&dev_priv->rps_lock);
8482         dev_priv->pm_iir = 0;
8483         spin_unlock_irq(&dev_priv->rps_lock);
8484
8485         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8486 }
8487
8488 static unsigned long intel_pxfreq(u32 vidfreq)
8489 {
8490         unsigned long freq;
8491         int div = (vidfreq & 0x3f0000) >> 16;
8492         int post = (vidfreq & 0x3000) >> 12;
8493         int pre = (vidfreq & 0x7);
8494
8495         if (!pre)
8496                 return 0;
8497
8498         freq = ((div * 133333) / ((1<<post) * pre));
8499
8500         return freq;
8501 }
8502
8503 void intel_init_emon(struct drm_device *dev)
8504 {
8505         struct drm_i915_private *dev_priv = dev->dev_private;
8506         u32 lcfuse;
8507         u8 pxw[16];
8508         int i;
8509
8510         /* Disable to program */
8511         I915_WRITE(ECR, 0);
8512         POSTING_READ(ECR);
8513
8514         /* Program energy weights for various events */
8515         I915_WRITE(SDEW, 0x15040d00);
8516         I915_WRITE(CSIEW0, 0x007f0000);
8517         I915_WRITE(CSIEW1, 0x1e220004);
8518         I915_WRITE(CSIEW2, 0x04000004);
8519
8520         for (i = 0; i < 5; i++)
8521                 I915_WRITE(PEW + (i * 4), 0);
8522         for (i = 0; i < 3; i++)
8523                 I915_WRITE(DEW + (i * 4), 0);
8524
8525         /* Program P-state weights to account for frequency power adjustment */
8526         for (i = 0; i < 16; i++) {
8527                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8528                 unsigned long freq = intel_pxfreq(pxvidfreq);
8529                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8530                         PXVFREQ_PX_SHIFT;
8531                 unsigned long val;
8532
8533                 val = vid * vid;
8534                 val *= (freq / 1000);
8535                 val *= 255;
8536                 val /= (127*127*900);
8537                 if (val > 0xff)
8538                         DRM_ERROR("bad pxval: %ld\n", val);
8539                 pxw[i] = val;
8540         }
8541         /* Render standby states get 0 weight */
8542         pxw[14] = 0;
8543         pxw[15] = 0;
8544
8545         for (i = 0; i < 4; i++) {
8546                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8547                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8548                 I915_WRITE(PXW + (i * 4), val);
8549         }
8550
8551         /* Adjust magic regs to magic values (more experimental results) */
8552         I915_WRITE(OGW0, 0);
8553         I915_WRITE(OGW1, 0);
8554         I915_WRITE(EG0, 0x00007f00);
8555         I915_WRITE(EG1, 0x0000000e);
8556         I915_WRITE(EG2, 0x000e0000);
8557         I915_WRITE(EG3, 0x68000300);
8558         I915_WRITE(EG4, 0x42000000);
8559         I915_WRITE(EG5, 0x00140031);
8560         I915_WRITE(EG6, 0);
8561         I915_WRITE(EG7, 0);
8562
8563         for (i = 0; i < 8; i++)
8564                 I915_WRITE(PXWL + (i * 4), 0);
8565
8566         /* Enable PMON + select events */
8567         I915_WRITE(ECR, 0x80000019);
8568
8569         lcfuse = I915_READ(LCFUSE02);
8570
8571         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8572 }
8573
8574 int intel_enable_rc6(const struct drm_device *dev)
8575 {
8576         /*
8577          * Respect the kernel parameter if it is set
8578          */
8579         if (i915_enable_rc6 >= 0)
8580                 return i915_enable_rc6;
8581
8582         /*
8583          * Disable RC6 on Ironlake
8584          */
8585         if (INTEL_INFO(dev)->gen == 5)
8586                 return 0;
8587
8588         /* Sorry Haswell, no RC6 for you for now. */
8589         if (IS_HASWELL(dev))
8590                 return 0;
8591
8592         /*
8593          * Disable rc6 on Sandybridge
8594          */
8595         if (INTEL_INFO(dev)->gen == 6) {
8596                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8597                 return INTEL_RC6_ENABLE;
8598         }
8599         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8600         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8601 }
8602
8603 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8604 {
8605         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8606         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8607         u32 pcu_mbox, rc6_mask = 0;
8608         u32 gtfifodbg;
8609         int cur_freq, min_freq, max_freq;
8610         int rc6_mode;
8611         int i;
8612
8613         /* Here begins a magic sequence of register writes to enable
8614          * auto-downclocking.
8615          *
8616          * Perhaps there might be some value in exposing these to
8617          * userspace...
8618          */
8619         I915_WRITE(GEN6_RC_STATE, 0);
8620         mutex_lock(&dev_priv->dev->struct_mutex);
8621
8622         /* Clear the DBG now so we don't confuse earlier errors */
8623         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8624                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8625                 I915_WRITE(GTFIFODBG, gtfifodbg);
8626         }
8627
8628         gen6_gt_force_wake_get(dev_priv);
8629
8630         /* disable the counters and set deterministic thresholds */
8631         I915_WRITE(GEN6_RC_CONTROL, 0);
8632
8633         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8634         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8635         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8636         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8637         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8638
8639         for (i = 0; i < I915_NUM_RINGS; i++)
8640                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8641
8642         I915_WRITE(GEN6_RC_SLEEP, 0);
8643         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8644         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8645         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8646         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8647
8648         rc6_mode = intel_enable_rc6(dev_priv->dev);
8649         if (rc6_mode & INTEL_RC6_ENABLE)
8650                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8651
8652         if (rc6_mode & INTEL_RC6p_ENABLE)
8653                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8654
8655         if (rc6_mode & INTEL_RC6pp_ENABLE)
8656                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8657
8658         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8659                         (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8660                         (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8661                         (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8662
8663         I915_WRITE(GEN6_RC_CONTROL,
8664                    rc6_mask |
8665                    GEN6_RC_CTL_EI_MODE(1) |
8666                    GEN6_RC_CTL_HW_ENABLE);
8667
8668         I915_WRITE(GEN6_RPNSWREQ,
8669                    GEN6_FREQUENCY(10) |
8670                    GEN6_OFFSET(0) |
8671                    GEN6_AGGRESSIVE_TURBO);
8672         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8673                    GEN6_FREQUENCY(12));
8674
8675         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8676         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8677                    18 << 24 |
8678                    6 << 16);
8679         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8680         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8681         I915_WRITE(GEN6_RP_UP_EI, 100000);
8682         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8683         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8684         I915_WRITE(GEN6_RP_CONTROL,
8685                    GEN6_RP_MEDIA_TURBO |
8686                    GEN6_RP_MEDIA_HW_MODE |
8687                    GEN6_RP_MEDIA_IS_GFX |
8688                    GEN6_RP_ENABLE |
8689                    GEN6_RP_UP_BUSY_AVG |
8690                    GEN6_RP_DOWN_IDLE_CONT);
8691
8692         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8693                      500))
8694                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8695
8696         I915_WRITE(GEN6_PCODE_DATA, 0);
8697         I915_WRITE(GEN6_PCODE_MAILBOX,
8698                    GEN6_PCODE_READY |
8699                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8700         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8701                      500))
8702                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8703
8704         min_freq = (rp_state_cap & 0xff0000) >> 16;
8705         max_freq = rp_state_cap & 0xff;
8706         cur_freq = (gt_perf_status & 0xff00) >> 8;
8707
8708         /* Check for overclock support */
8709         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8710                      500))
8711                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8712         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8713         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8714         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8715                      500))
8716                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8717         if (pcu_mbox & (1<<31)) { /* OC supported */
8718                 max_freq = pcu_mbox & 0xff;
8719                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8720         }
8721
8722         /* In units of 100MHz */
8723         dev_priv->max_delay = max_freq;
8724         dev_priv->min_delay = min_freq;
8725         dev_priv->cur_delay = cur_freq;
8726
8727         /* requires MSI enabled */
8728         I915_WRITE(GEN6_PMIER,
8729                    GEN6_PM_MBOX_EVENT |
8730                    GEN6_PM_THERMAL_EVENT |
8731                    GEN6_PM_RP_DOWN_TIMEOUT |
8732                    GEN6_PM_RP_UP_THRESHOLD |
8733                    GEN6_PM_RP_DOWN_THRESHOLD |
8734                    GEN6_PM_RP_UP_EI_EXPIRED |
8735                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8736         spin_lock_irq(&dev_priv->rps_lock);
8737         WARN_ON(dev_priv->pm_iir != 0);
8738         I915_WRITE(GEN6_PMIMR, 0);
8739         spin_unlock_irq(&dev_priv->rps_lock);
8740         /* enable all PM interrupts */
8741         I915_WRITE(GEN6_PMINTRMSK, 0);
8742
8743         gen6_gt_force_wake_put(dev_priv);
8744         mutex_unlock(&dev_priv->dev->struct_mutex);
8745 }
8746
8747 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8748 {
8749         int min_freq = 15;
8750         int gpu_freq, ia_freq, max_ia_freq;
8751         int scaling_factor = 180;
8752
8753         max_ia_freq = cpufreq_quick_get_max(0);
8754         /*
8755          * Default to measured freq if none found, PCU will ensure we don't go
8756          * over
8757          */
8758         if (!max_ia_freq)
8759                 max_ia_freq = tsc_khz;
8760
8761         /* Convert from kHz to MHz */
8762         max_ia_freq /= 1000;
8763
8764         mutex_lock(&dev_priv->dev->struct_mutex);
8765
8766         /*
8767          * For each potential GPU frequency, load a ring frequency we'd like
8768          * to use for memory access.  We do this by specifying the IA frequency
8769          * the PCU should use as a reference to determine the ring frequency.
8770          */
8771         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8772              gpu_freq--) {
8773                 int diff = dev_priv->max_delay - gpu_freq;
8774
8775                 /*
8776                  * For GPU frequencies less than 750MHz, just use the lowest
8777                  * ring freq.
8778                  */
8779                 if (gpu_freq < min_freq)
8780                         ia_freq = 800;
8781                 else
8782                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8783                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8784
8785                 I915_WRITE(GEN6_PCODE_DATA,
8786                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8787                            gpu_freq);
8788                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8789                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8790                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8791                               GEN6_PCODE_READY) == 0, 10)) {
8792                         DRM_ERROR("pcode write of freq table timed out\n");
8793                         continue;
8794                 }
8795         }
8796
8797         mutex_unlock(&dev_priv->dev->struct_mutex);
8798 }
8799
8800 static void ironlake_init_clock_gating(struct drm_device *dev)
8801 {
8802         struct drm_i915_private *dev_priv = dev->dev_private;
8803         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8804
8805         /* Required for FBC */
8806         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8807                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8808                 DPFDUNIT_CLOCK_GATE_DISABLE;
8809         /* Required for CxSR */
8810         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8811
8812         I915_WRITE(PCH_3DCGDIS0,
8813                    MARIUNIT_CLOCK_GATE_DISABLE |
8814                    SVSMUNIT_CLOCK_GATE_DISABLE);
8815         I915_WRITE(PCH_3DCGDIS1,
8816                    VFMUNIT_CLOCK_GATE_DISABLE);
8817
8818         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8819
8820         /*
8821          * According to the spec the following bits should be set in
8822          * order to enable memory self-refresh
8823          * The bit 22/21 of 0x42004
8824          * The bit 5 of 0x42020
8825          * The bit 15 of 0x45000
8826          */
8827         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8828                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8829                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8830         I915_WRITE(ILK_DSPCLK_GATE,
8831                    (I915_READ(ILK_DSPCLK_GATE) |
8832                     ILK_DPARB_CLK_GATE));
8833         I915_WRITE(DISP_ARB_CTL,
8834                    (I915_READ(DISP_ARB_CTL) |
8835                     DISP_FBC_WM_DIS));
8836         I915_WRITE(WM3_LP_ILK, 0);
8837         I915_WRITE(WM2_LP_ILK, 0);
8838         I915_WRITE(WM1_LP_ILK, 0);
8839
8840         /*
8841          * Based on the document from hardware guys the following bits
8842          * should be set unconditionally in order to enable FBC.
8843          * The bit 22 of 0x42000
8844          * The bit 22 of 0x42004
8845          * The bit 7,8,9 of 0x42020.
8846          */
8847         if (IS_IRONLAKE_M(dev)) {
8848                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8849                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8850                            ILK_FBCQ_DIS);
8851                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8852                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8853                            ILK_DPARB_GATE);
8854                 I915_WRITE(ILK_DSPCLK_GATE,
8855                            I915_READ(ILK_DSPCLK_GATE) |
8856                            ILK_DPFC_DIS1 |
8857                            ILK_DPFC_DIS2 |
8858                            ILK_CLK_FBC);
8859         }
8860
8861         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8862                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8863                    ILK_ELPIN_409_SELECT);
8864         I915_WRITE(_3D_CHICKEN2,
8865                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8866                    _3D_CHICKEN2_WM_READ_PIPELINED);
8867 }
8868
8869 static void gen6_init_clock_gating(struct drm_device *dev)
8870 {
8871         struct drm_i915_private *dev_priv = dev->dev_private;
8872         int pipe;
8873         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8874
8875         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8876
8877         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8878                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8879                    ILK_ELPIN_409_SELECT);
8880
8881         I915_WRITE(WM3_LP_ILK, 0);
8882         I915_WRITE(WM2_LP_ILK, 0);
8883         I915_WRITE(WM1_LP_ILK, 0);
8884
8885         /* clear masked bit */
8886         I915_WRITE(CACHE_MODE_0,
8887                    CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
8888
8889         I915_WRITE(GEN6_UCGCTL1,
8890                    I915_READ(GEN6_UCGCTL1) |
8891                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8892                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8893
8894         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8895          * gating disable must be set.  Failure to set it results in
8896          * flickering pixels due to Z write ordering failures after
8897          * some amount of runtime in the Mesa "fire" demo, and Unigine
8898          * Sanctuary and Tropics, and apparently anything else with
8899          * alpha test or pixel discard.
8900          *
8901          * According to the spec, bit 11 (RCCUNIT) must also be set,
8902          * but we didn't debug actual testcases to find it out.
8903          */
8904         I915_WRITE(GEN6_UCGCTL2,
8905                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8906                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8907
8908         /* Bspec says we need to always set all mask bits. */
8909         I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
8910                    _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
8911
8912         /*
8913          * According to the spec the following bits should be
8914          * set in order to enable memory self-refresh and fbc:
8915          * The bit21 and bit22 of 0x42000
8916          * The bit21 and bit22 of 0x42004
8917          * The bit5 and bit7 of 0x42020
8918          * The bit14 of 0x70180
8919          * The bit14 of 0x71180
8920          */
8921         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8922                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8923                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8924         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8925                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8926                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8927         I915_WRITE(ILK_DSPCLK_GATE,
8928                    I915_READ(ILK_DSPCLK_GATE) |
8929                    ILK_DPARB_CLK_GATE  |
8930                    ILK_DPFD_CLK_GATE);
8931
8932         for_each_pipe(pipe) {
8933                 I915_WRITE(DSPCNTR(pipe),
8934                            I915_READ(DSPCNTR(pipe)) |
8935                            DISPPLANE_TRICKLE_FEED_DISABLE);
8936                 intel_flush_display_plane(dev_priv, pipe);
8937         }
8938 }
8939
8940 static void ivybridge_init_clock_gating(struct drm_device *dev)
8941 {
8942         struct drm_i915_private *dev_priv = dev->dev_private;
8943         int pipe;
8944         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8945
8946         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8947
8948         I915_WRITE(WM3_LP_ILK, 0);
8949         I915_WRITE(WM2_LP_ILK, 0);
8950         I915_WRITE(WM1_LP_ILK, 0);
8951
8952         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8953          * This implements the WaDisableRCZUnitClockGating workaround.
8954          */
8955         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8956
8957         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8958
8959         I915_WRITE(IVB_CHICKEN3,
8960                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8961                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8962
8963         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8964         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8965                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8966
8967         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8968         I915_WRITE(GEN7_L3CNTLREG1,
8969                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8970         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8971                         GEN7_WA_L3_CHICKEN_MODE);
8972
8973         /* This is required by WaCatErrorRejectionIssue */
8974         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8975                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8976                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8977
8978         for_each_pipe(pipe) {
8979                 I915_WRITE(DSPCNTR(pipe),
8980                            I915_READ(DSPCNTR(pipe)) |
8981                            DISPPLANE_TRICKLE_FEED_DISABLE);
8982                 intel_flush_display_plane(dev_priv, pipe);
8983         }
8984 }
8985
8986 static void valleyview_init_clock_gating(struct drm_device *dev)
8987 {
8988         struct drm_i915_private *dev_priv = dev->dev_private;
8989         int pipe;
8990         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8991
8992         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8993
8994         I915_WRITE(WM3_LP_ILK, 0);
8995         I915_WRITE(WM2_LP_ILK, 0);
8996         I915_WRITE(WM1_LP_ILK, 0);
8997
8998         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8999          * This implements the WaDisableRCZUnitClockGating workaround.
9000          */
9001         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9002
9003         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
9004
9005         I915_WRITE(IVB_CHICKEN3,
9006                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
9007                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
9008
9009         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
9010         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
9011                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
9012
9013         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
9014         I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
9015         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
9016
9017         /* This is required by WaCatErrorRejectionIssue */
9018         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9019                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9020                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9021
9022         for_each_pipe(pipe) {
9023                 I915_WRITE(DSPCNTR(pipe),
9024                            I915_READ(DSPCNTR(pipe)) |
9025                            DISPPLANE_TRICKLE_FEED_DISABLE);
9026                 intel_flush_display_plane(dev_priv, pipe);
9027         }
9028
9029         I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |
9030                    (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |
9031                    PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
9032 }
9033
9034 static void g4x_init_clock_gating(struct drm_device *dev)
9035 {
9036         struct drm_i915_private *dev_priv = dev->dev_private;
9037         uint32_t dspclk_gate;
9038
9039         I915_WRITE(RENCLK_GATE_D1, 0);
9040         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
9041                    GS_UNIT_CLOCK_GATE_DISABLE |
9042                    CL_UNIT_CLOCK_GATE_DISABLE);
9043         I915_WRITE(RAMCLK_GATE_D, 0);
9044         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
9045                 OVRUNIT_CLOCK_GATE_DISABLE |
9046                 OVCUNIT_CLOCK_GATE_DISABLE;
9047         if (IS_GM45(dev))
9048                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
9049         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
9050 }
9051
9052 static void crestline_init_clock_gating(struct drm_device *dev)
9053 {
9054         struct drm_i915_private *dev_priv = dev->dev_private;
9055
9056         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
9057         I915_WRITE(RENCLK_GATE_D2, 0);
9058         I915_WRITE(DSPCLK_GATE_D, 0);
9059         I915_WRITE(RAMCLK_GATE_D, 0);
9060         I915_WRITE16(DEUC, 0);
9061 }
9062
9063 static void broadwater_init_clock_gating(struct drm_device *dev)
9064 {
9065         struct drm_i915_private *dev_priv = dev->dev_private;
9066
9067         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
9068                    I965_RCC_CLOCK_GATE_DISABLE |
9069                    I965_RCPB_CLOCK_GATE_DISABLE |
9070                    I965_ISC_CLOCK_GATE_DISABLE |
9071                    I965_FBC_CLOCK_GATE_DISABLE);
9072         I915_WRITE(RENCLK_GATE_D2, 0);
9073 }
9074
9075 static void gen3_init_clock_gating(struct drm_device *dev)
9076 {
9077         struct drm_i915_private *dev_priv = dev->dev_private;
9078         u32 dstate = I915_READ(D_STATE);
9079
9080         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
9081                 DSTATE_DOT_CLOCK_GATING;
9082         I915_WRITE(D_STATE, dstate);
9083 }
9084
9085 static void i85x_init_clock_gating(struct drm_device *dev)
9086 {
9087         struct drm_i915_private *dev_priv = dev->dev_private;
9088
9089         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
9090 }
9091
9092 static void i830_init_clock_gating(struct drm_device *dev)
9093 {
9094         struct drm_i915_private *dev_priv = dev->dev_private;
9095
9096         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
9097 }
9098
9099 static void ibx_init_clock_gating(struct drm_device *dev)
9100 {
9101         struct drm_i915_private *dev_priv = dev->dev_private;
9102
9103         /*
9104          * On Ibex Peak and Cougar Point, we need to disable clock
9105          * gating for the panel power sequencer or it will fail to
9106          * start up when no ports are active.
9107          */
9108         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
9109 }
9110
9111 static void cpt_init_clock_gating(struct drm_device *dev)
9112 {
9113         struct drm_i915_private *dev_priv = dev->dev_private;
9114         int pipe;
9115
9116         /*
9117          * On Ibex Peak and Cougar Point, we need to disable clock
9118          * gating for the panel power sequencer or it will fail to
9119          * start up when no ports are active.
9120          */
9121         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
9122         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
9123                    DPLS_EDP_PPS_FIX_DIS);
9124         /* Without this, mode sets may fail silently on FDI */
9125         for_each_pipe(pipe)
9126                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
9127 }
9128
9129 static void ironlake_teardown_rc6(struct drm_device *dev)
9130 {
9131         struct drm_i915_private *dev_priv = dev->dev_private;
9132
9133         if (dev_priv->renderctx) {
9134                 i915_gem_object_unpin(dev_priv->renderctx);
9135                 drm_gem_object_unreference(&dev_priv->renderctx->base);
9136                 dev_priv->renderctx = NULL;
9137         }
9138
9139         if (dev_priv->pwrctx) {
9140                 i915_gem_object_unpin(dev_priv->pwrctx);
9141                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
9142                 dev_priv->pwrctx = NULL;
9143         }
9144 }
9145
9146 static void ironlake_disable_rc6(struct drm_device *dev)
9147 {
9148         struct drm_i915_private *dev_priv = dev->dev_private;
9149
9150         if (I915_READ(PWRCTXA)) {
9151                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
9152                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
9153                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
9154                          50);
9155
9156                 I915_WRITE(PWRCTXA, 0);
9157                 POSTING_READ(PWRCTXA);
9158
9159                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
9160                 POSTING_READ(RSTDBYCTL);
9161         }
9162
9163         ironlake_teardown_rc6(dev);
9164 }
9165
9166 static int ironlake_setup_rc6(struct drm_device *dev)
9167 {
9168         struct drm_i915_private *dev_priv = dev->dev_private;
9169
9170         if (dev_priv->renderctx == NULL)
9171                 dev_priv->renderctx = intel_alloc_context_page(dev);
9172         if (!dev_priv->renderctx)
9173                 return -ENOMEM;
9174
9175         if (dev_priv->pwrctx == NULL)
9176                 dev_priv->pwrctx = intel_alloc_context_page(dev);
9177         if (!dev_priv->pwrctx) {
9178                 ironlake_teardown_rc6(dev);
9179                 return -ENOMEM;
9180         }
9181
9182         return 0;
9183 }
9184
9185 void ironlake_enable_rc6(struct drm_device *dev)
9186 {
9187         struct drm_i915_private *dev_priv = dev->dev_private;
9188         int ret;
9189
9190         /* rc6 disabled by default due to repeated reports of hanging during
9191          * boot and resume.
9192          */
9193         if (!intel_enable_rc6(dev))
9194                 return;
9195
9196         mutex_lock(&dev->struct_mutex);
9197         ret = ironlake_setup_rc6(dev);
9198         if (ret) {
9199                 mutex_unlock(&dev->struct_mutex);
9200                 return;
9201         }
9202
9203         /*
9204          * GPU can automatically power down the render unit if given a page
9205          * to save state.
9206          */
9207         ret = BEGIN_LP_RING(6);
9208         if (ret) {
9209                 ironlake_teardown_rc6(dev);
9210                 mutex_unlock(&dev->struct_mutex);
9211                 return;
9212         }
9213
9214         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
9215         OUT_RING(MI_SET_CONTEXT);
9216         OUT_RING(dev_priv->renderctx->gtt_offset |
9217                  MI_MM_SPACE_GTT |
9218                  MI_SAVE_EXT_STATE_EN |
9219                  MI_RESTORE_EXT_STATE_EN |
9220                  MI_RESTORE_INHIBIT);
9221         OUT_RING(MI_SUSPEND_FLUSH);
9222         OUT_RING(MI_NOOP);
9223         OUT_RING(MI_FLUSH);
9224         ADVANCE_LP_RING();
9225
9226         /*
9227          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
9228          * does an implicit flush, combined with MI_FLUSH above, it should be
9229          * safe to assume that renderctx is valid
9230          */
9231         ret = intel_wait_ring_idle(LP_RING(dev_priv));
9232         if (ret) {
9233                 DRM_ERROR("failed to enable ironlake power power savings\n");
9234                 ironlake_teardown_rc6(dev);
9235                 mutex_unlock(&dev->struct_mutex);
9236                 return;
9237         }
9238
9239         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
9240         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
9241         mutex_unlock(&dev->struct_mutex);
9242 }
9243
9244 void intel_init_clock_gating(struct drm_device *dev)
9245 {
9246         struct drm_i915_private *dev_priv = dev->dev_private;
9247
9248         dev_priv->display.init_clock_gating(dev);
9249
9250         if (dev_priv->display.init_pch_clock_gating)
9251                 dev_priv->display.init_pch_clock_gating(dev);
9252 }
9253
9254 /* Set up chip specific display functions */
9255 static void intel_init_display(struct drm_device *dev)
9256 {
9257         struct drm_i915_private *dev_priv = dev->dev_private;
9258
9259         /* We always want a DPMS function */
9260         if (HAS_PCH_SPLIT(dev)) {
9261                 dev_priv->display.dpms = ironlake_crtc_dpms;
9262                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9263                 dev_priv->display.update_plane = ironlake_update_plane;
9264         } else {
9265                 dev_priv->display.dpms = i9xx_crtc_dpms;
9266                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9267                 dev_priv->display.update_plane = i9xx_update_plane;
9268         }
9269
9270         if (I915_HAS_FBC(dev)) {
9271                 if (HAS_PCH_SPLIT(dev)) {
9272                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
9273                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
9274                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
9275                 } else if (IS_GM45(dev)) {
9276                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
9277                         dev_priv->display.enable_fbc = g4x_enable_fbc;
9278                         dev_priv->display.disable_fbc = g4x_disable_fbc;
9279                 } else if (IS_CRESTLINE(dev)) {
9280                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
9281                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
9282                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
9283                 }
9284                 /* 855GM needs testing */
9285         }
9286
9287         /* Returns the core display clock speed */
9288         if (IS_VALLEYVIEW(dev))
9289                 dev_priv->display.get_display_clock_speed =
9290                         valleyview_get_display_clock_speed;
9291         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9292                 dev_priv->display.get_display_clock_speed =
9293                         i945_get_display_clock_speed;
9294         else if (IS_I915G(dev))
9295                 dev_priv->display.get_display_clock_speed =
9296                         i915_get_display_clock_speed;
9297         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9298                 dev_priv->display.get_display_clock_speed =
9299                         i9xx_misc_get_display_clock_speed;
9300         else if (IS_I915GM(dev))
9301                 dev_priv->display.get_display_clock_speed =
9302                         i915gm_get_display_clock_speed;
9303         else if (IS_I865G(dev))
9304                 dev_priv->display.get_display_clock_speed =
9305                         i865_get_display_clock_speed;
9306         else if (IS_I85X(dev))
9307                 dev_priv->display.get_display_clock_speed =
9308                         i855_get_display_clock_speed;
9309         else /* 852, 830 */
9310                 dev_priv->display.get_display_clock_speed =
9311                         i830_get_display_clock_speed;
9312
9313         /* For FIFO watermark updates */
9314         if (HAS_PCH_SPLIT(dev)) {
9315                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
9316                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
9317
9318                 /* IVB configs may use multi-threaded forcewake */
9319                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9320                         u32     ecobus;
9321
9322                         /* A small trick here - if the bios hasn't configured MT forcewake,
9323                          * and if the device is in RC6, then force_wake_mt_get will not wake
9324                          * the device and the ECOBUS read will return zero. Which will be
9325                          * (correctly) interpreted by the test below as MT forcewake being
9326                          * disabled.
9327                          */
9328                         mutex_lock(&dev->struct_mutex);
9329                         __gen6_gt_force_wake_mt_get(dev_priv);
9330                         ecobus = I915_READ_NOTRACE(ECOBUS);
9331                         __gen6_gt_force_wake_mt_put(dev_priv);
9332                         mutex_unlock(&dev->struct_mutex);
9333
9334                         if (ecobus & FORCEWAKE_MT_ENABLE) {
9335                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
9336                                 dev_priv->display.force_wake_get =
9337                                         __gen6_gt_force_wake_mt_get;
9338                                 dev_priv->display.force_wake_put =
9339                                         __gen6_gt_force_wake_mt_put;
9340                         }
9341                 }
9342
9343                 if (HAS_PCH_IBX(dev))
9344                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
9345                 else if (HAS_PCH_CPT(dev))
9346                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
9347
9348                 if (IS_GEN5(dev)) {
9349                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
9350                                 dev_priv->display.update_wm = ironlake_update_wm;
9351                         else {
9352                                 DRM_DEBUG_KMS("Failed to get proper latency. "
9353                                               "Disable CxSR\n");
9354                                 dev_priv->display.update_wm = NULL;
9355                         }
9356                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9357                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
9358                         dev_priv->display.write_eld = ironlake_write_eld;
9359                 } else if (IS_GEN6(dev)) {
9360                         if (SNB_READ_WM0_LATENCY()) {
9361                                 dev_priv->display.update_wm = sandybridge_update_wm;
9362                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9363                         } else {
9364                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9365                                               "Disable CxSR\n");
9366                                 dev_priv->display.update_wm = NULL;
9367                         }
9368                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9369                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9370                         dev_priv->display.write_eld = ironlake_write_eld;
9371                 } else if (IS_IVYBRIDGE(dev)) {
9372                         /* FIXME: detect B0+ stepping and use auto training */
9373                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9374                         if (SNB_READ_WM0_LATENCY()) {
9375                                 dev_priv->display.update_wm = sandybridge_update_wm;
9376                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
9377                         } else {
9378                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
9379                                               "Disable CxSR\n");
9380                                 dev_priv->display.update_wm = NULL;
9381                         }
9382                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9383                         dev_priv->display.write_eld = ironlake_write_eld;
9384                 } else
9385                         dev_priv->display.update_wm = NULL;
9386         } else if (IS_VALLEYVIEW(dev)) {
9387                 dev_priv->display.update_wm = valleyview_update_wm;
9388                 dev_priv->display.init_clock_gating =
9389                         valleyview_init_clock_gating;
9390                 dev_priv->display.force_wake_get = vlv_force_wake_get;
9391                 dev_priv->display.force_wake_put = vlv_force_wake_put;
9392         } else if (IS_PINEVIEW(dev)) {
9393                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9394                                             dev_priv->is_ddr3,
9395                                             dev_priv->fsb_freq,
9396                                             dev_priv->mem_freq)) {
9397                         DRM_INFO("failed to find known CxSR latency "
9398                                  "(found ddr%s fsb freq %d, mem freq %d), "
9399                                  "disabling CxSR\n",
9400                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9401                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9402                         /* Disable CxSR and never update its watermark again */
9403                         pineview_disable_cxsr(dev);
9404                         dev_priv->display.update_wm = NULL;
9405                 } else
9406                         dev_priv->display.update_wm = pineview_update_wm;
9407                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9408         } else if (IS_G4X(dev)) {
9409                 dev_priv->display.write_eld = g4x_write_eld;
9410                 dev_priv->display.update_wm = g4x_update_wm;
9411                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9412         } else if (IS_GEN4(dev)) {
9413                 dev_priv->display.update_wm = i965_update_wm;
9414                 if (IS_CRESTLINE(dev))
9415                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9416                 else if (IS_BROADWATER(dev))
9417                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9418         } else if (IS_GEN3(dev)) {
9419                 dev_priv->display.update_wm = i9xx_update_wm;
9420                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9421                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9422         } else if (IS_I865G(dev)) {
9423                 dev_priv->display.update_wm = i830_update_wm;
9424                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9425                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9426         } else if (IS_I85X(dev)) {
9427                 dev_priv->display.update_wm = i9xx_update_wm;
9428                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9429                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9430         } else {
9431                 dev_priv->display.update_wm = i830_update_wm;
9432                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9433                 if (IS_845G(dev))
9434                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9435                 else
9436                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9437         }
9438
9439         /* Default just returns -ENODEV to indicate unsupported */
9440         dev_priv->display.queue_flip = intel_default_queue_flip;
9441
9442         switch (INTEL_INFO(dev)->gen) {
9443         case 2:
9444                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9445                 break;
9446
9447         case 3:
9448                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9449                 break;
9450
9451         case 4:
9452         case 5:
9453                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9454                 break;
9455
9456         case 6:
9457                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9458                 break;
9459         case 7:
9460                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9461                 break;
9462         }
9463 }
9464
9465 /*
9466  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9467  * resume, or other times.  This quirk makes sure that's the case for
9468  * affected systems.
9469  */
9470 static void quirk_pipea_force(struct drm_device *dev)
9471 {
9472         struct drm_i915_private *dev_priv = dev->dev_private;
9473
9474         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9475         DRM_INFO("applying pipe a force quirk\n");
9476 }
9477
9478 /*
9479  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9480  */
9481 static void quirk_ssc_force_disable(struct drm_device *dev)
9482 {
9483         struct drm_i915_private *dev_priv = dev->dev_private;
9484         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9485         DRM_INFO("applying lvds SSC disable quirk\n");
9486 }
9487
9488 /*
9489  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9490  * brightness value
9491  */
9492 static void quirk_invert_brightness(struct drm_device *dev)
9493 {
9494         struct drm_i915_private *dev_priv = dev->dev_private;
9495         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9496         DRM_INFO("applying inverted panel brightness quirk\n");
9497 }
9498
9499 struct intel_quirk {
9500         int device;
9501         int subsystem_vendor;
9502         int subsystem_device;
9503         void (*hook)(struct drm_device *dev);
9504 };
9505
9506 struct intel_quirk intel_quirks[] = {
9507         /* HP Mini needs pipe A force quirk (LP: #322104) */
9508         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9509
9510         /* Thinkpad R31 needs pipe A force quirk */
9511         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9512         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9513         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9514
9515         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9516         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9517         /* ThinkPad X40 needs pipe A force quirk */
9518
9519         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9520         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9521
9522         /* 855 & before need to leave pipe A & dpll A up */
9523         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9524         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9525
9526         /* Lenovo U160 cannot use SSC on LVDS */
9527         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9528
9529         /* Sony Vaio Y cannot use SSC on LVDS */
9530         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9531
9532         /* Acer Aspire 5734Z must invert backlight brightness */
9533         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9534 };
9535
9536 static void intel_init_quirks(struct drm_device *dev)
9537 {
9538         struct pci_dev *d = dev->pdev;
9539         int i;
9540
9541         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9542                 struct intel_quirk *q = &intel_quirks[i];
9543
9544                 if (d->device == q->device &&
9545                     (d->subsystem_vendor == q->subsystem_vendor ||
9546                      q->subsystem_vendor == PCI_ANY_ID) &&
9547                     (d->subsystem_device == q->subsystem_device ||
9548                      q->subsystem_device == PCI_ANY_ID))
9549                         q->hook(dev);
9550         }
9551 }
9552
9553 /* Disable the VGA plane that we never use */
9554 static void i915_disable_vga(struct drm_device *dev)
9555 {
9556         struct drm_i915_private *dev_priv = dev->dev_private;
9557         u8 sr1;
9558         u32 vga_reg;
9559
9560         if (HAS_PCH_SPLIT(dev))
9561                 vga_reg = CPU_VGACNTRL;
9562         else
9563                 vga_reg = VGACNTRL;
9564
9565         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9566         outb(SR01, VGA_SR_INDEX);
9567         sr1 = inb(VGA_SR_DATA);
9568         outb(sr1 | 1<<5, VGA_SR_DATA);
9569         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9570         udelay(300);
9571
9572         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9573         POSTING_READ(vga_reg);
9574 }
9575
9576 static void ivb_pch_pwm_override(struct drm_device *dev)
9577 {
9578         struct drm_i915_private *dev_priv = dev->dev_private;
9579
9580         /*
9581          * IVB has CPU eDP backlight regs too, set things up to let the
9582          * PCH regs control the backlight
9583          */
9584         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
9585         I915_WRITE(BLC_PWM_CPU_CTL, 0);
9586         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
9587 }
9588
9589 void intel_modeset_init_hw(struct drm_device *dev)
9590 {
9591         struct drm_i915_private *dev_priv = dev->dev_private;
9592
9593         intel_init_clock_gating(dev);
9594
9595         if (IS_IRONLAKE_M(dev)) {
9596                 ironlake_enable_drps(dev);
9597                 intel_init_emon(dev);
9598         }
9599
9600         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
9601                 gen6_enable_rps(dev_priv);
9602                 gen6_update_ring_freq(dev_priv);
9603         }
9604
9605         if (IS_IVYBRIDGE(dev))
9606                 ivb_pch_pwm_override(dev);
9607 }
9608
9609 void intel_modeset_init(struct drm_device *dev)
9610 {
9611         struct drm_i915_private *dev_priv = dev->dev_private;
9612         int i, ret;
9613
9614         drm_mode_config_init(dev);
9615
9616         dev->mode_config.min_width = 0;
9617         dev->mode_config.min_height = 0;
9618
9619         dev->mode_config.preferred_depth = 24;
9620         dev->mode_config.prefer_shadow = 1;
9621
9622         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9623
9624         intel_init_quirks(dev);
9625
9626         intel_init_display(dev);
9627
9628         if (IS_GEN2(dev)) {
9629                 dev->mode_config.max_width = 2048;
9630                 dev->mode_config.max_height = 2048;
9631         } else if (IS_GEN3(dev)) {
9632                 dev->mode_config.max_width = 4096;
9633                 dev->mode_config.max_height = 4096;
9634         } else {
9635                 dev->mode_config.max_width = 8192;
9636                 dev->mode_config.max_height = 8192;
9637         }
9638         dev->mode_config.fb_base = dev->agp->base;
9639
9640         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9641                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9642
9643         for (i = 0; i < dev_priv->num_pipe; i++) {
9644                 intel_crtc_init(dev, i);
9645                 ret = intel_plane_init(dev, i);
9646                 if (ret)
9647                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9648         }
9649
9650         /* Just disable it once at startup */
9651         i915_disable_vga(dev);
9652         intel_setup_outputs(dev);
9653
9654         intel_modeset_init_hw(dev);
9655
9656         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9657         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9658                     (unsigned long)dev);
9659 }
9660
9661 void intel_modeset_gem_init(struct drm_device *dev)
9662 {
9663         if (IS_IRONLAKE_M(dev))
9664                 ironlake_enable_rc6(dev);
9665
9666         intel_setup_overlay(dev);
9667 }
9668
9669 void intel_modeset_cleanup(struct drm_device *dev)
9670 {
9671         struct drm_i915_private *dev_priv = dev->dev_private;
9672         struct drm_crtc *crtc;
9673         struct intel_crtc *intel_crtc;
9674
9675         drm_kms_helper_poll_fini(dev);
9676         mutex_lock(&dev->struct_mutex);
9677
9678         intel_unregister_dsm_handler();
9679
9680
9681         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9682                 /* Skip inactive CRTCs */
9683                 if (!crtc->fb)
9684                         continue;
9685
9686                 intel_crtc = to_intel_crtc(crtc);
9687                 intel_increase_pllclock(crtc);
9688         }
9689
9690         intel_disable_fbc(dev);
9691
9692         if (IS_IRONLAKE_M(dev))
9693                 ironlake_disable_drps(dev);
9694         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
9695                 gen6_disable_rps(dev);
9696
9697         if (IS_IRONLAKE_M(dev))
9698                 ironlake_disable_rc6(dev);
9699
9700         if (IS_VALLEYVIEW(dev))
9701                 vlv_init_dpio(dev);
9702
9703         mutex_unlock(&dev->struct_mutex);
9704
9705         /* Disable the irq before mode object teardown, for the irq might
9706          * enqueue unpin/hotplug work. */
9707         drm_irq_uninstall(dev);
9708         cancel_work_sync(&dev_priv->hotplug_work);
9709         cancel_work_sync(&dev_priv->rps_work);
9710
9711         /* flush any delayed tasks or pending work */
9712         flush_scheduled_work();
9713
9714         /* Shut off idle work before the crtcs get freed. */
9715         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9716                 intel_crtc = to_intel_crtc(crtc);
9717                 del_timer_sync(&intel_crtc->idle_timer);
9718         }
9719         del_timer_sync(&dev_priv->idle_timer);
9720         cancel_work_sync(&dev_priv->idle_work);
9721
9722         drm_mode_config_cleanup(dev);
9723 }
9724
9725 /*
9726  * Return which encoder is currently attached for connector.
9727  */
9728 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9729 {
9730         return &intel_attached_encoder(connector)->base;
9731 }
9732
9733 void intel_connector_attach_encoder(struct intel_connector *connector,
9734                                     struct intel_encoder *encoder)
9735 {
9736         connector->encoder = encoder;
9737         drm_mode_connector_attach_encoder(&connector->base,
9738                                           &encoder->base);
9739 }
9740
9741 /*
9742  * set vga decode state - true == enable VGA decode
9743  */
9744 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9745 {
9746         struct drm_i915_private *dev_priv = dev->dev_private;
9747         u16 gmch_ctrl;
9748
9749         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9750         if (state)
9751                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9752         else
9753                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9754         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9755         return 0;
9756 }
9757
9758 #ifdef CONFIG_DEBUG_FS
9759 #include <linux/seq_file.h>
9760
9761 struct intel_display_error_state {
9762         struct intel_cursor_error_state {
9763                 u32 control;
9764                 u32 position;
9765                 u32 base;
9766                 u32 size;
9767         } cursor[2];
9768
9769         struct intel_pipe_error_state {
9770                 u32 conf;
9771                 u32 source;
9772
9773                 u32 htotal;
9774                 u32 hblank;
9775                 u32 hsync;
9776                 u32 vtotal;
9777                 u32 vblank;
9778                 u32 vsync;
9779         } pipe[2];
9780
9781         struct intel_plane_error_state {
9782                 u32 control;
9783                 u32 stride;
9784                 u32 size;
9785                 u32 pos;
9786                 u32 addr;
9787                 u32 surface;
9788                 u32 tile_offset;
9789         } plane[2];
9790 };
9791
9792 struct intel_display_error_state *
9793 intel_display_capture_error_state(struct drm_device *dev)
9794 {
9795         drm_i915_private_t *dev_priv = dev->dev_private;
9796         struct intel_display_error_state *error;
9797         int i;
9798
9799         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9800         if (error == NULL)
9801                 return NULL;
9802
9803         for (i = 0; i < 2; i++) {
9804                 error->cursor[i].control = I915_READ(CURCNTR(i));
9805                 error->cursor[i].position = I915_READ(CURPOS(i));
9806                 error->cursor[i].base = I915_READ(CURBASE(i));
9807
9808                 error->plane[i].control = I915_READ(DSPCNTR(i));
9809                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9810                 error->plane[i].size = I915_READ(DSPSIZE(i));
9811                 error->plane[i].pos = I915_READ(DSPPOS(i));
9812                 error->plane[i].addr = I915_READ(DSPADDR(i));
9813                 if (INTEL_INFO(dev)->gen >= 4) {
9814                         error->plane[i].surface = I915_READ(DSPSURF(i));
9815                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9816                 }
9817
9818                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9819                 error->pipe[i].source = I915_READ(PIPESRC(i));
9820                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9821                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9822                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9823                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9824                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9825                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9826         }
9827
9828         return error;
9829 }
9830
9831 void
9832 intel_display_print_error_state(struct seq_file *m,
9833                                 struct drm_device *dev,
9834                                 struct intel_display_error_state *error)
9835 {
9836         int i;
9837
9838         for (i = 0; i < 2; i++) {
9839                 seq_printf(m, "Pipe [%d]:\n", i);
9840                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9841                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9842                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9843                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9844                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9845                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9846                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9847                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9848
9849                 seq_printf(m, "Plane [%d]:\n", i);
9850                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9851                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9852                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9853                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9854                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9855                 if (INTEL_INFO(dev)->gen >= 4) {
9856                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9857                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9858                 }
9859
9860                 seq_printf(m, "Cursor [%d]:\n", i);
9861                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9862                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9863                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9864         }
9865 }
9866 #endif