2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
106 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 int p2_slow, p2_fast;
122 typedef struct intel_limit intel_limit_t;
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_pch_rawclk(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 WARN_ON(!HAS_PCH_SPLIT(dev));
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
369 static const intel_limit_t intel_limits_vlv = {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv = {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
414 needs_modeset(struct drm_crtc_state *state)
416 return state->mode_changed || state->active_changed;
420 * Returns whether any output on the specified pipe is of the specified type
422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
460 WARN_ON(num_connectors == 0);
465 static const intel_limit_t *
466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
476 limit = &intel_limits_ironlake_dual_lvds;
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
481 limit = &intel_limits_ironlake_single_lvds;
484 limit = &intel_limits_ironlake_dac;
489 static const intel_limit_t *
490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
511 static const intel_limit_t *
512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
536 limit = &intel_limits_i9xx_sdvo;
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
543 limit = &intel_limits_i8xx_dac;
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595 return clock->dot / 5;
598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
608 return clock->dot / 5;
611 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
617 static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
653 i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
657 struct drm_device *dev = crtc_state->base.crtc->dev;
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
668 return limit->p2.p2_slow;
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
673 return limit->p2.p2_fast;
678 i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
683 struct drm_device *dev = crtc_state->base.crtc->dev;
687 memset(best_clock, 0, sizeof(*best_clock));
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
708 clock.p != match_clock->p)
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
721 return (err != target);
725 pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
730 struct drm_device *dev = crtc_state->base.crtc->dev;
734 memset(best_clock, 0, sizeof(*best_clock));
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
753 clock.p != match_clock->p)
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
766 return (err != target);
770 g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
775 struct drm_device *dev = crtc_state->base.crtc->dev;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
782 memset(best_clock, 0, sizeof(*best_clock));
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
831 if (IS_CHERRYVIEW(dev)) {
834 return calculated_clock->p > best_clock->p;
837 if (WARN_ON_ONCE(!target_freq))
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 return *error_ppm + 10 < best_error_ppm;
858 vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
871 target *= 5; /* fast clock */
873 memset(best_clock, 0, sizeof(*best_clock));
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
888 vlv_calc_dpll_params(refclk, &clock);
890 if (!intel_PLL_is_valid(dev, limit,
894 if (!vlv_PLL_is_optimal(dev, target,
912 chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
941 clock.p = clock.p1 * clock.p2;
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
946 if (m2 > INT_MAX/clock.m1)
951 chv_calc_dpll_params(refclk, &clock);
953 if (!intel_PLL_is_valid(dev, limit, &clock))
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
961 best_error_ppm = error_ppm;
969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
972 int refclk = i9xx_get_refclk(crtc_state, 0);
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
978 bool intel_crtc_active(struct drm_crtc *crtc)
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1005 return intel_crtc->config->cpu_transcoder;
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 line1 = I915_READ(reg) & line_mask;
1022 line2 = I915_READ(reg) & line_mask;
1024 return line1 == line2;
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1056 WARN(1, "pipe_off wait timed out\n");
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1069 * Returns true if @port is connected, false otherwise.
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1079 bit = SDE_PORTB_HOTPLUG;
1082 bit = SDE_PORTC_HOTPLUG;
1085 bit = SDE_PORTD_HOTPLUG;
1091 switch (port->port) {
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1106 return I915_READ(SDEISR) & bit;
1109 static const char *state_string(bool enabled)
1111 return enabled ? "on" : "off";
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1136 mutex_lock(&dev_priv->sb_lock);
1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138 mutex_unlock(&dev_priv->sb_lock);
1140 cur_state = val & DSI_PLL_VCO_EN;
1141 I915_STATE_WARN(cur_state != state,
1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1153 if (crtc->config->shared_dpll < 0)
1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1165 struct intel_dpll_hw_state hw_state;
1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172 I915_STATE_WARN(cur_state != state,
1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
1213 I915_STATE_WARN(cur_state != state,
1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1226 /* ILK FDI PLL is always enabled */
1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231 if (HAS_DDI(dev_priv->dev))
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249 I915_STATE_WARN(cur_state != state,
1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1257 struct drm_device *dev = dev_priv->dev;
1260 enum pipe panel_pipe = PIPE_A;
1263 if (WARN_ON(HAS_DDI(dev)))
1266 if (HAS_PCH_SPLIT(dev)) {
1269 pp_reg = PCH_PP_CONTROL;
1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1281 pp_reg = PP_CONTROL;
1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1291 I915_STATE_WARN(panel_pipe == pipe && locked,
1292 "panel assertion failure, pipe %c regs locked\n",
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1299 struct drm_device *dev = dev_priv->dev;
1302 if (IS_845G(dev) || IS_I865G(dev))
1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1307 I915_STATE_WARN(cur_state != state,
1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1328 if (!intel_display_power_is_enabled(dev_priv,
1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1337 I915_STATE_WARN(cur_state != state,
1338 "pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352 I915_STATE_WARN(cur_state != state,
1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1363 struct drm_device *dev = dev_priv->dev;
1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373 "plane %c assertion failure, should be disabled but not\n",
1378 /* Need to check both planes against the pipe */
1379 for_each_pipe(dev_priv, i) {
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1393 struct drm_device *dev = dev_priv->dev;
1397 if (INTEL_INFO(dev)->gen >= 9) {
1398 for_each_sprite(dev_priv, pipe, sprite) {
1399 val = I915_READ(PLANE_CTL(pipe, sprite));
1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1404 } else if (IS_VALLEYVIEW(dev)) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 reg = SPCNTR(pipe, sprite);
1407 val = I915_READ(reg);
1408 I915_STATE_WARN(val & SP_ENABLE,
1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410 sprite_name(pipe, sprite), pipe_name(pipe));
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SPRITE_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
1420 val = I915_READ(reg);
1421 I915_STATE_WARN(val & DVS_ENABLE,
1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423 plane_name(pipe), pipe_name(pipe));
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430 drm_crtc_vblank_put(crtc);
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1453 reg = PCH_TRANSCONF(pipe);
1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
1456 I915_STATE_WARN(enabled,
1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
1464 if ((val & DP_PORT_EN) == 0)
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1485 if ((val & SDVO_ENABLE) == 0)
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1504 if ((val & LVDS_PORT_EN) == 0)
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, int reg, u32 port_sel)
1535 u32 val = I915_READ(reg);
1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538 reg, pipe_name(pipe));
1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541 && (val & DP_PIPEB_SELECT),
1542 "IBX PCH dp port still using transcoder B\n");
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1548 u32 val = I915_READ(reg);
1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551 reg, pipe_name(pipe));
1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554 && (val & SDVO_PIPE_B_SELECT),
1555 "IBX PCH hdmi port still using transcoder B\n");
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1569 val = I915_READ(reg);
1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 val = I915_READ(reg);
1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1585 static void intel_init_dpio(struct drm_device *dev)
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1589 if (!IS_VALLEYVIEW(dev))
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606 const struct intel_crtc_state *pipe_config)
1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1618 /* PLL is protected by panel, make sure we can write it */
1619 if (IS_MOBILE(dev_priv->dev))
1620 assert_panel_unlocked(dev_priv, crtc->pipe);
1622 I915_WRITE(reg, dpll);
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(crtc->pipe));
1632 /* We do this three times for luck */
1633 I915_WRITE(reg, dpll);
1635 udelay(150); /* wait for warmup */
1636 I915_WRITE(reg, dpll);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1641 udelay(150); /* wait for warmup */
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645 const struct intel_crtc_state *pipe_config)
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1657 mutex_lock(&dev_priv->sb_lock);
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1664 mutex_unlock(&dev_priv->sb_lock);
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674 /* Check PLL is locked */
1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678 /* not sure when this should be written */
1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680 POSTING_READ(DPLL_MD(pipe));
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1685 struct intel_crtc *crtc;
1688 for_each_intel_crtc(dev, crtc)
1689 count += crtc->base.state->active &&
1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
1702 assert_pipe_disabled(dev_priv, crtc->pipe);
1704 /* No really, not for ILK+ */
1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1707 /* PLL is protected by panel, make sure we can write it */
1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1724 /* Wait for the clocks to stabilize. */
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1735 * So write it again.
1737 I915_WRITE(reg, dpll);
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1749 udelay(150); /* wait for warmup */
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 * Note! This is for pre-ILK only.
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1800 val = DPLL_VGA_MODE_DIS;
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1824 mutex_lock(&dev_priv->sb_lock);
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1842 mutex_unlock(&dev_priv->sb_lock);
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
1852 switch (dport->port) {
1854 port_mask = DPLL_PORTB_READY_MASK;
1858 port_mask = DPLL_PORTC_READY_MASK;
1860 expected_mask <<= 4;
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881 if (WARN_ON(pll == NULL))
1884 WARN_ON(!pll->config.crtc_mask);
1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1890 pll->mode_set(dev_priv, pll);
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908 if (WARN_ON(pll == NULL))
1911 if (WARN_ON(pll->config.crtc_mask == 0))
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll->name, pll->active, pll->on,
1916 crtc->base.base.id);
1918 if (pll->active++) {
1920 assert_shared_dpll_enabled(dev_priv, pll);
1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928 pll->enable(dev_priv, pll);
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev)->gen < 5);
1943 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll->name, pll->active, pll->on,
1948 crtc->base.base.id);
1950 if (WARN_ON(pll->active == 0)) {
1951 assert_shared_dpll_disabled(dev_priv, pll);
1955 assert_shared_dpll_enabled(dev_priv, pll);
1960 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1961 pll->disable(dev_priv, pll);
1964 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 struct drm_device *dev = dev_priv->dev;
1971 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1973 uint32_t reg, val, pipeconf_val;
1975 /* PCH only available on ILK+ */
1976 BUG_ON(!HAS_PCH_SPLIT(dev));
1978 /* Make sure PCH DPLL is enabled */
1979 assert_shared_dpll_enabled(dev_priv,
1980 intel_crtc_to_shared_dpll(intel_crtc));
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv, pipe);
1984 assert_fdi_rx_enabled(dev_priv, pipe);
1986 if (HAS_PCH_CPT(dev)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg = TRANS_CHICKEN2(pipe);
1990 val = I915_READ(reg);
1991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992 I915_WRITE(reg, val);
1995 reg = PCH_TRANSCONF(pipe);
1996 val = I915_READ(reg);
1997 pipeconf_val = I915_READ(PIPECONF(pipe));
1999 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 * Make the BPC in transcoder be consistent with
2002 * that in pipeconf reg. For HDMI we must use 8bpc
2003 * here for both 8bpc and 12bpc.
2005 val &= ~PIPECONF_BPC_MASK;
2006 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2007 val |= PIPECONF_8BPC;
2009 val |= pipeconf_val & PIPECONF_BPC_MASK;
2012 val &= ~TRANS_INTERLACE_MASK;
2013 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2014 if (HAS_PCH_IBX(dev_priv->dev) &&
2015 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2016 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 val |= TRANS_INTERLACED;
2020 val |= TRANS_PROGRESSIVE;
2022 I915_WRITE(reg, val | TRANS_ENABLE);
2023 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2024 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2028 enum transcoder cpu_transcoder)
2030 u32 val, pipeconf_val;
2032 /* PCH only available on ILK+ */
2033 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035 /* FDI must be feeding us bits for PCH ports */
2036 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2037 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039 /* Workaround: set timing override bit. */
2040 val = I915_READ(_TRANSA_CHICKEN2);
2041 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2042 I915_WRITE(_TRANSA_CHICKEN2, val);
2045 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2048 PIPECONF_INTERLACED_ILK)
2049 val |= TRANS_INTERLACED;
2051 val |= TRANS_PROGRESSIVE;
2053 I915_WRITE(LPT_TRANSCONF, val);
2054 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2055 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 struct drm_device *dev = dev_priv->dev;
2064 /* FDI relies on the transcoder */
2065 assert_fdi_tx_disabled(dev_priv, pipe);
2066 assert_fdi_rx_disabled(dev_priv, pipe);
2068 /* Ports must be off as well */
2069 assert_pch_ports_disabled(dev_priv, pipe);
2071 reg = PCH_TRANSCONF(pipe);
2072 val = I915_READ(reg);
2073 val &= ~TRANS_ENABLE;
2074 I915_WRITE(reg, val);
2075 /* wait for PCH transcoder off, transcoder state */
2076 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2077 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079 if (!HAS_PCH_IBX(dev)) {
2080 /* Workaround: Clear the timing override chicken bit again. */
2081 reg = TRANS_CHICKEN2(pipe);
2082 val = I915_READ(reg);
2083 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2084 I915_WRITE(reg, val);
2088 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2092 val = I915_READ(LPT_TRANSCONF);
2093 val &= ~TRANS_ENABLE;
2094 I915_WRITE(LPT_TRANSCONF, val);
2095 /* wait for PCH transcoder off, transcoder state */
2096 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2097 DRM_ERROR("Failed to disable PCH transcoder\n");
2099 /* Workaround: clear timing override bit. */
2100 val = I915_READ(_TRANSA_CHICKEN2);
2101 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2102 I915_WRITE(_TRANSA_CHICKEN2, val);
2106 * intel_enable_pipe - enable a pipe, asserting requirements
2107 * @crtc: crtc responsible for the pipe
2109 * Enable @crtc's pipe, making sure that various hardware specific requirements
2110 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 struct drm_device *dev = crtc->base.dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 enum pipe pipe = crtc->pipe;
2117 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 enum pipe pch_transcoder;
2123 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2125 assert_planes_disabled(dev_priv, pipe);
2126 assert_cursor_disabled(dev_priv, pipe);
2127 assert_sprites_disabled(dev_priv, pipe);
2129 if (HAS_PCH_LPT(dev_priv->dev))
2130 pch_transcoder = TRANSCODER_A;
2132 pch_transcoder = pipe;
2135 * A pipe without a PLL won't actually be able to drive bits from
2136 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2140 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2141 assert_dsi_pll_enabled(dev_priv);
2143 assert_pll_enabled(dev_priv, pipe);
2145 if (crtc->config->has_pch_encoder) {
2146 /* if driving the PCH, we need FDI enabled */
2147 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2148 assert_fdi_tx_pll_enabled(dev_priv,
2149 (enum pipe) cpu_transcoder);
2151 /* FIXME: assert CPU port conditions for SNB+ */
2154 reg = PIPECONF(cpu_transcoder);
2155 val = I915_READ(reg);
2156 if (val & PIPECONF_ENABLE) {
2157 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2162 I915_WRITE(reg, val | PIPECONF_ENABLE);
2167 * intel_disable_pipe - disable a pipe, asserting requirements
2168 * @crtc: crtc whose pipes is to be disabled
2170 * Disable the pipe of @crtc, making sure that various hardware
2171 * specific requirements are met, if applicable, e.g. plane
2172 * disabled, panel fitter off, etc.
2174 * Will wait until the pipe has shut down before returning.
2176 static void intel_disable_pipe(struct intel_crtc *crtc)
2178 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2179 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2180 enum pipe pipe = crtc->pipe;
2184 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187 * Make sure planes won't keep trying to pump pixels to us,
2188 * or we might hang the display.
2190 assert_planes_disabled(dev_priv, pipe);
2191 assert_cursor_disabled(dev_priv, pipe);
2192 assert_sprites_disabled(dev_priv, pipe);
2194 reg = PIPECONF(cpu_transcoder);
2195 val = I915_READ(reg);
2196 if ((val & PIPECONF_ENABLE) == 0)
2200 * Double wide has implications for planes
2201 * so best keep it disabled when not needed.
2203 if (crtc->config->double_wide)
2204 val &= ~PIPECONF_DOUBLE_WIDE;
2206 /* Don't disable pipe or pipe PLLs if needed */
2207 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2208 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2209 val &= ~PIPECONF_ENABLE;
2211 I915_WRITE(reg, val);
2212 if ((val & PIPECONF_ENABLE) == 0)
2213 intel_wait_for_pipe_off(crtc);
2216 static bool need_vtd_wa(struct drm_device *dev)
2218 #ifdef CONFIG_INTEL_IOMMU
2219 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2226 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2227 uint64_t fb_format_modifier)
2229 unsigned int tile_height;
2230 uint32_t pixel_bytes;
2232 switch (fb_format_modifier) {
2233 case DRM_FORMAT_MOD_NONE:
2236 case I915_FORMAT_MOD_X_TILED:
2237 tile_height = IS_GEN2(dev) ? 16 : 8;
2239 case I915_FORMAT_MOD_Y_TILED:
2242 case I915_FORMAT_MOD_Yf_TILED:
2243 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2244 switch (pixel_bytes) {
2258 "128-bit pixels are not supported for display!");
2264 MISSING_CASE(fb_format_modifier);
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274 uint32_t pixel_format, uint64_t fb_format_modifier)
2276 return ALIGN(height, intel_tile_height(dev, pixel_format,
2277 fb_format_modifier));
2281 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2282 const struct drm_plane_state *plane_state)
2284 struct intel_rotation_info *info = &view->rotation_info;
2285 unsigned int tile_height, tile_pitch;
2287 *view = i915_ggtt_view_normal;
2292 if (!intel_rotation_90_or_270(plane_state->rotation))
2295 *view = i915_ggtt_view_rotated;
2297 info->height = fb->height;
2298 info->pixel_format = fb->pixel_format;
2299 info->pitch = fb->pitches[0];
2300 info->fb_modifier = fb->modifier[0];
2302 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 tile_pitch = PAGE_SIZE / tile_height;
2305 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2306 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2307 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2312 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2314 if (INTEL_INFO(dev_priv)->gen >= 9)
2316 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2317 IS_VALLEYVIEW(dev_priv))
2319 else if (INTEL_INFO(dev_priv)->gen >= 4)
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327 struct drm_framebuffer *fb,
2328 const struct drm_plane_state *plane_state,
2329 struct intel_engine_cs *pipelined,
2330 struct drm_i915_gem_request **pipelined_request)
2332 struct drm_device *dev = fb->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2335 struct i915_ggtt_view view;
2339 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341 switch (fb->modifier[0]) {
2342 case DRM_FORMAT_MOD_NONE:
2343 alignment = intel_linear_alignment(dev_priv);
2345 case I915_FORMAT_MOD_X_TILED:
2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2349 /* pin() will align the object as required by fence */
2353 case I915_FORMAT_MOD_Y_TILED:
2354 case I915_FORMAT_MOD_Yf_TILED:
2355 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356 "Y tiling bo slipped through, driver bug!\n"))
2358 alignment = 1 * 1024 * 1024;
2361 MISSING_CASE(fb->modifier[0]);
2365 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2369 /* Note that the w/a also requires 64 PTE of padding following the
2370 * bo. We currently fill all unused PTE with the shadow page and so
2371 * we should always have valid PTE following the scanout preventing
2374 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2375 alignment = 256 * 1024;
2378 * Global gtt pte registers are special registers which actually forward
2379 * writes to a chunk of system memory. Which means that there is no risk
2380 * that the register values disappear as soon as we call
2381 * intel_runtime_pm_put(), so it is correct to wrap only the
2382 * pin/unpin/fence and not more.
2384 intel_runtime_pm_get(dev_priv);
2386 dev_priv->mm.interruptible = false;
2387 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2388 pipelined_request, &view);
2390 goto err_interruptible;
2392 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393 * fence, whereas 965+ only requires a fence if using
2394 * framebuffer compression. For simplicity, we always install
2395 * a fence as the cost is not that onerous.
2397 ret = i915_gem_object_get_fence(obj);
2401 i915_gem_object_pin_fence(obj);
2403 dev_priv->mm.interruptible = true;
2404 intel_runtime_pm_put(dev_priv);
2408 i915_gem_object_unpin_from_display_plane(obj, &view);
2410 dev_priv->mm.interruptible = true;
2411 intel_runtime_pm_put(dev_priv);
2415 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2416 const struct drm_plane_state *plane_state)
2418 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2419 struct i915_ggtt_view view;
2422 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2424 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2425 WARN_ONCE(ret, "Couldn't get view from plane state!");
2427 i915_gem_object_unpin_fence(obj);
2428 i915_gem_object_unpin_from_display_plane(obj, &view);
2431 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2432 * is assumed to be a power-of-two. */
2433 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2435 unsigned int tiling_mode,
2439 if (tiling_mode != I915_TILING_NONE) {
2440 unsigned int tile_rows, tiles;
2445 tiles = *x / (512/cpp);
2448 return tile_rows * pitch * 8 + tiles * 4096;
2450 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2451 unsigned int offset;
2453 offset = *y * pitch + *x * cpp;
2454 *y = (offset & alignment) / pitch;
2455 *x = ((offset & alignment) - *y * pitch) / cpp;
2456 return offset & ~alignment;
2460 static int i9xx_format_to_fourcc(int format)
2463 case DISPPLANE_8BPP:
2464 return DRM_FORMAT_C8;
2465 case DISPPLANE_BGRX555:
2466 return DRM_FORMAT_XRGB1555;
2467 case DISPPLANE_BGRX565:
2468 return DRM_FORMAT_RGB565;
2470 case DISPPLANE_BGRX888:
2471 return DRM_FORMAT_XRGB8888;
2472 case DISPPLANE_RGBX888:
2473 return DRM_FORMAT_XBGR8888;
2474 case DISPPLANE_BGRX101010:
2475 return DRM_FORMAT_XRGB2101010;
2476 case DISPPLANE_RGBX101010:
2477 return DRM_FORMAT_XBGR2101010;
2481 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484 case PLANE_CTL_FORMAT_RGB_565:
2485 return DRM_FORMAT_RGB565;
2487 case PLANE_CTL_FORMAT_XRGB_8888:
2490 return DRM_FORMAT_ABGR8888;
2492 return DRM_FORMAT_XBGR8888;
2495 return DRM_FORMAT_ARGB8888;
2497 return DRM_FORMAT_XRGB8888;
2499 case PLANE_CTL_FORMAT_XRGB_2101010:
2501 return DRM_FORMAT_XBGR2101010;
2503 return DRM_FORMAT_XRGB2101010;
2508 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2509 struct intel_initial_plane_config *plane_config)
2511 struct drm_device *dev = crtc->base.dev;
2512 struct drm_i915_gem_object *obj = NULL;
2513 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2514 struct drm_framebuffer *fb = &plane_config->fb->base;
2515 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2516 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 size_aligned -= base_aligned;
2521 if (plane_config->size == 0)
2524 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2531 obj->tiling_mode = plane_config->tiling;
2532 if (obj->tiling_mode == I915_TILING_X)
2533 obj->stride = fb->pitches[0];
2535 mode_cmd.pixel_format = fb->pixel_format;
2536 mode_cmd.width = fb->width;
2537 mode_cmd.height = fb->height;
2538 mode_cmd.pitches[0] = fb->pitches[0];
2539 mode_cmd.modifier[0] = fb->modifier[0];
2540 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2542 mutex_lock(&dev->struct_mutex);
2543 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2545 DRM_DEBUG_KMS("intel fb init failed\n");
2548 mutex_unlock(&dev->struct_mutex);
2550 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2554 drm_gem_object_unreference(&obj->base);
2555 mutex_unlock(&dev->struct_mutex);
2559 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2561 update_state_fb(struct drm_plane *plane)
2563 if (plane->fb == plane->state->fb)
2566 if (plane->state->fb)
2567 drm_framebuffer_unreference(plane->state->fb);
2568 plane->state->fb = plane->fb;
2569 if (plane->state->fb)
2570 drm_framebuffer_reference(plane->state->fb);
2574 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2575 struct intel_initial_plane_config *plane_config)
2577 struct drm_device *dev = intel_crtc->base.dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *i;
2581 struct drm_i915_gem_object *obj;
2582 struct drm_plane *primary = intel_crtc->base.primary;
2583 struct drm_plane_state *plane_state = primary->state;
2584 struct drm_framebuffer *fb;
2586 if (!plane_config->fb)
2589 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2590 fb = &plane_config->fb->base;
2594 kfree(plane_config->fb);
2597 * Failed to alloc the obj, check to see if we should share
2598 * an fb with another CRTC instead
2600 for_each_crtc(dev, c) {
2601 i = to_intel_crtc(c);
2603 if (c == &intel_crtc->base)
2609 fb = c->primary->fb;
2613 obj = intel_fb_obj(fb);
2614 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2615 drm_framebuffer_reference(fb);
2623 plane_state->src_x = plane_state->src_y = 0;
2624 plane_state->src_w = fb->width << 16;
2625 plane_state->src_h = fb->height << 16;
2627 plane_state->crtc_x = plane_state->src_y = 0;
2628 plane_state->crtc_w = fb->width;
2629 plane_state->crtc_h = fb->height;
2631 obj = intel_fb_obj(fb);
2632 if (obj->tiling_mode != I915_TILING_NONE)
2633 dev_priv->preserve_bios_swizzle = true;
2635 drm_framebuffer_reference(fb);
2636 primary->fb = primary->state->fb = fb;
2637 primary->crtc = primary->state->crtc = &intel_crtc->base;
2638 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2639 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2642 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2643 struct drm_framebuffer *fb,
2646 struct drm_device *dev = crtc->dev;
2647 struct drm_i915_private *dev_priv = dev->dev_private;
2648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2649 struct drm_plane *primary = crtc->primary;
2650 bool visible = to_intel_plane_state(primary->state)->visible;
2651 struct drm_i915_gem_object *obj;
2652 int plane = intel_crtc->plane;
2653 unsigned long linear_offset;
2655 u32 reg = DSPCNTR(plane);
2658 if (!visible || !fb) {
2660 if (INTEL_INFO(dev)->gen >= 4)
2661 I915_WRITE(DSPSURF(plane), 0);
2663 I915_WRITE(DSPADDR(plane), 0);
2668 obj = intel_fb_obj(fb);
2669 if (WARN_ON(obj == NULL))
2672 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2674 dspcntr = DISPPLANE_GAMMA_ENABLE;
2676 dspcntr |= DISPLAY_PLANE_ENABLE;
2678 if (INTEL_INFO(dev)->gen < 4) {
2679 if (intel_crtc->pipe == PIPE_B)
2680 dspcntr |= DISPPLANE_SEL_PIPE_B;
2682 /* pipesrc and dspsize control the size that is scaled from,
2683 * which should always be the user's requested size.
2685 I915_WRITE(DSPSIZE(plane),
2686 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2687 (intel_crtc->config->pipe_src_w - 1));
2688 I915_WRITE(DSPPOS(plane), 0);
2689 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2690 I915_WRITE(PRIMSIZE(plane),
2691 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2692 (intel_crtc->config->pipe_src_w - 1));
2693 I915_WRITE(PRIMPOS(plane), 0);
2694 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697 switch (fb->pixel_format) {
2699 dspcntr |= DISPPLANE_8BPP;
2701 case DRM_FORMAT_XRGB1555:
2702 dspcntr |= DISPPLANE_BGRX555;
2704 case DRM_FORMAT_RGB565:
2705 dspcntr |= DISPPLANE_BGRX565;
2707 case DRM_FORMAT_XRGB8888:
2708 dspcntr |= DISPPLANE_BGRX888;
2710 case DRM_FORMAT_XBGR8888:
2711 dspcntr |= DISPPLANE_RGBX888;
2713 case DRM_FORMAT_XRGB2101010:
2714 dspcntr |= DISPPLANE_BGRX101010;
2716 case DRM_FORMAT_XBGR2101010:
2717 dspcntr |= DISPPLANE_RGBX101010;
2723 if (INTEL_INFO(dev)->gen >= 4 &&
2724 obj->tiling_mode != I915_TILING_NONE)
2725 dspcntr |= DISPPLANE_TILED;
2728 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2730 linear_offset = y * fb->pitches[0] + x * pixel_size;
2732 if (INTEL_INFO(dev)->gen >= 4) {
2733 intel_crtc->dspaddr_offset =
2734 intel_gen4_compute_page_offset(dev_priv,
2735 &x, &y, obj->tiling_mode,
2738 linear_offset -= intel_crtc->dspaddr_offset;
2740 intel_crtc->dspaddr_offset = linear_offset;
2743 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2744 dspcntr |= DISPPLANE_ROTATE_180;
2746 x += (intel_crtc->config->pipe_src_w - 1);
2747 y += (intel_crtc->config->pipe_src_h - 1);
2749 /* Finding the last pixel of the last line of the display
2750 data and adding to linear_offset*/
2752 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2753 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756 I915_WRITE(reg, dspcntr);
2758 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2759 if (INTEL_INFO(dev)->gen >= 4) {
2760 I915_WRITE(DSPSURF(plane),
2761 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2762 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2763 I915_WRITE(DSPLINOFF(plane), linear_offset);
2765 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2770 struct drm_framebuffer *fb,
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 struct drm_plane *primary = crtc->primary;
2777 bool visible = to_intel_plane_state(primary->state)->visible;
2778 struct drm_i915_gem_object *obj;
2779 int plane = intel_crtc->plane;
2780 unsigned long linear_offset;
2782 u32 reg = DSPCNTR(plane);
2785 if (!visible || !fb) {
2787 I915_WRITE(DSPSURF(plane), 0);
2792 obj = intel_fb_obj(fb);
2793 if (WARN_ON(obj == NULL))
2796 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2798 dspcntr = DISPPLANE_GAMMA_ENABLE;
2800 dspcntr |= DISPLAY_PLANE_ENABLE;
2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2805 switch (fb->pixel_format) {
2807 dspcntr |= DISPPLANE_8BPP;
2809 case DRM_FORMAT_RGB565:
2810 dspcntr |= DISPPLANE_BGRX565;
2812 case DRM_FORMAT_XRGB8888:
2813 dspcntr |= DISPPLANE_BGRX888;
2815 case DRM_FORMAT_XBGR8888:
2816 dspcntr |= DISPPLANE_RGBX888;
2818 case DRM_FORMAT_XRGB2101010:
2819 dspcntr |= DISPPLANE_BGRX101010;
2821 case DRM_FORMAT_XBGR2101010:
2822 dspcntr |= DISPPLANE_RGBX101010;
2828 if (obj->tiling_mode != I915_TILING_NONE)
2829 dspcntr |= DISPPLANE_TILED;
2831 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2832 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2834 linear_offset = y * fb->pitches[0] + x * pixel_size;
2835 intel_crtc->dspaddr_offset =
2836 intel_gen4_compute_page_offset(dev_priv,
2837 &x, &y, obj->tiling_mode,
2840 linear_offset -= intel_crtc->dspaddr_offset;
2841 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2842 dspcntr |= DISPPLANE_ROTATE_180;
2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2845 x += (intel_crtc->config->pipe_src_w - 1);
2846 y += (intel_crtc->config->pipe_src_h - 1);
2848 /* Finding the last pixel of the last line of the display
2849 data and adding to linear_offset*/
2851 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2852 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2856 I915_WRITE(reg, dspcntr);
2858 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2859 I915_WRITE(DSPSURF(plane),
2860 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2861 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2862 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2864 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2865 I915_WRITE(DSPLINOFF(plane), linear_offset);
2870 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2871 uint32_t pixel_format)
2873 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2876 * The stride is either expressed as a multiple of 64 bytes
2877 * chunks for linear buffers or in number of tiles for tiled
2880 switch (fb_modifier) {
2881 case DRM_FORMAT_MOD_NONE:
2883 case I915_FORMAT_MOD_X_TILED:
2884 if (INTEL_INFO(dev)->gen == 2)
2887 case I915_FORMAT_MOD_Y_TILED:
2888 /* No need to check for old gens and Y tiling since this is
2889 * about the display engine and those will be blocked before
2893 case I915_FORMAT_MOD_Yf_TILED:
2894 if (bits_per_pixel == 8)
2899 MISSING_CASE(fb_modifier);
2904 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2905 struct drm_i915_gem_object *obj)
2907 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2909 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2910 view = &i915_ggtt_view_rotated;
2912 return i915_gem_obj_ggtt_offset_view(obj, view);
2915 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2917 struct drm_device *dev = intel_crtc->base.dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2920 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2921 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2922 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2923 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2924 intel_crtc->base.base.id, intel_crtc->pipe, id);
2928 * This function detaches (aka. unbinds) unused scalers in hardware
2930 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 struct intel_crtc_scaler_state *scaler_state;
2935 scaler_state = &intel_crtc->config->scaler_state;
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use)
2940 skl_detach_scaler(intel_crtc, i);
2944 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 switch (pixel_format) {
2948 return PLANE_CTL_FORMAT_INDEXED;
2949 case DRM_FORMAT_RGB565:
2950 return PLANE_CTL_FORMAT_RGB_565;
2951 case DRM_FORMAT_XBGR8888:
2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2953 case DRM_FORMAT_XRGB8888:
2954 return PLANE_CTL_FORMAT_XRGB_8888;
2956 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2957 * to be already pre-multiplied. We need to add a knob (or a different
2958 * DRM_FORMAT) for user-space to configure that.
2960 case DRM_FORMAT_ABGR8888:
2961 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2962 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2963 case DRM_FORMAT_ARGB8888:
2964 return PLANE_CTL_FORMAT_XRGB_8888 |
2965 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966 case DRM_FORMAT_XRGB2101010:
2967 return PLANE_CTL_FORMAT_XRGB_2101010;
2968 case DRM_FORMAT_XBGR2101010:
2969 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2970 case DRM_FORMAT_YUYV:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2972 case DRM_FORMAT_YVYU:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2974 case DRM_FORMAT_UYVY:
2975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2976 case DRM_FORMAT_VYUY:
2977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979 MISSING_CASE(pixel_format);
2985 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 switch (fb_modifier) {
2988 case DRM_FORMAT_MOD_NONE:
2990 case I915_FORMAT_MOD_X_TILED:
2991 return PLANE_CTL_TILED_X;
2992 case I915_FORMAT_MOD_Y_TILED:
2993 return PLANE_CTL_TILED_Y;
2994 case I915_FORMAT_MOD_Yf_TILED:
2995 return PLANE_CTL_TILED_YF;
2997 MISSING_CASE(fb_modifier);
3003 u32 skl_plane_ctl_rotation(unsigned int rotation)
3006 case BIT(DRM_ROTATE_0):
3009 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3010 * while i915 HW rotation is clockwise, thats why this swapping.
3012 case BIT(DRM_ROTATE_90):
3013 return PLANE_CTL_ROTATE_270;
3014 case BIT(DRM_ROTATE_180):
3015 return PLANE_CTL_ROTATE_180;
3016 case BIT(DRM_ROTATE_270):
3017 return PLANE_CTL_ROTATE_90;
3019 MISSING_CASE(rotation);
3025 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3026 struct drm_framebuffer *fb,
3029 struct drm_device *dev = crtc->dev;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032 struct drm_plane *plane = crtc->primary;
3033 bool visible = to_intel_plane_state(plane->state)->visible;
3034 struct drm_i915_gem_object *obj;
3035 int pipe = intel_crtc->pipe;
3036 u32 plane_ctl, stride_div, stride;
3037 u32 tile_height, plane_offset, plane_size;
3038 unsigned int rotation;
3039 int x_offset, y_offset;
3040 unsigned long surf_addr;
3041 struct intel_crtc_state *crtc_state = intel_crtc->config;
3042 struct intel_plane_state *plane_state;
3043 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3044 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3047 plane_state = to_intel_plane_state(plane->state);
3049 if (!visible || !fb) {
3050 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3051 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3052 POSTING_READ(PLANE_CTL(pipe, 0));
3056 plane_ctl = PLANE_CTL_ENABLE |
3057 PLANE_CTL_PIPE_GAMMA_ENABLE |
3058 PLANE_CTL_PIPE_CSC_ENABLE;
3060 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3061 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3062 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3064 rotation = plane->state->rotation;
3065 plane_ctl |= skl_plane_ctl_rotation(rotation);
3067 obj = intel_fb_obj(fb);
3068 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3070 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3073 * FIXME: intel_plane_state->src, dst aren't set when transitional
3074 * update_plane helpers are called from legacy paths.
3075 * Once full atomic crtc is available, below check can be avoided.
3077 if (drm_rect_width(&plane_state->src)) {
3078 scaler_id = plane_state->scaler_id;
3079 src_x = plane_state->src.x1 >> 16;
3080 src_y = plane_state->src.y1 >> 16;
3081 src_w = drm_rect_width(&plane_state->src) >> 16;
3082 src_h = drm_rect_height(&plane_state->src) >> 16;
3083 dst_x = plane_state->dst.x1;
3084 dst_y = plane_state->dst.y1;
3085 dst_w = drm_rect_width(&plane_state->dst);
3086 dst_h = drm_rect_height(&plane_state->dst);
3088 WARN_ON(x != src_x || y != src_y);
3090 src_w = intel_crtc->config->pipe_src_w;
3091 src_h = intel_crtc->config->pipe_src_h;
3094 if (intel_rotation_90_or_270(rotation)) {
3095 /* stride = Surface height in tiles */
3096 tile_height = intel_tile_height(dev, fb->pixel_format,
3098 stride = DIV_ROUND_UP(fb->height, tile_height);
3099 x_offset = stride * tile_height - y - src_h;
3101 plane_size = (src_w - 1) << 16 | (src_h - 1);
3103 stride = fb->pitches[0] / stride_div;
3106 plane_size = (src_h - 1) << 16 | (src_w - 1);
3108 plane_offset = y_offset << 16 | x_offset;
3110 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3111 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3112 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3113 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3115 if (scaler_id >= 0) {
3116 uint32_t ps_ctrl = 0;
3118 WARN_ON(!dst_w || !dst_h);
3119 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3120 crtc_state->scaler_state.scalers[scaler_id].mode;
3121 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3122 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3123 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3124 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3125 I915_WRITE(PLANE_POS(pipe, 0), 0);
3127 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3130 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3132 POSTING_READ(PLANE_SURF(pipe, 0));
3135 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3137 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3138 int x, int y, enum mode_set_atomic state)
3140 struct drm_device *dev = crtc->dev;
3141 struct drm_i915_private *dev_priv = dev->dev_private;
3143 if (dev_priv->fbc.disable_fbc)
3144 dev_priv->fbc.disable_fbc(dev_priv);
3146 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3151 static void intel_complete_page_flips(struct drm_device *dev)
3153 struct drm_crtc *crtc;
3155 for_each_crtc(dev, crtc) {
3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3157 enum plane plane = intel_crtc->plane;
3159 intel_prepare_page_flip(dev, plane);
3160 intel_finish_page_flip_plane(dev, plane);
3164 static void intel_update_primary_planes(struct drm_device *dev)
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 struct drm_crtc *crtc;
3169 for_each_crtc(dev, crtc) {
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 drm_modeset_lock(&crtc->mutex, NULL);
3174 * FIXME: Once we have proper support for primary planes (and
3175 * disabling them without disabling the entire crtc) allow again
3176 * a NULL crtc->primary->fb.
3178 if (intel_crtc->active && crtc->primary->fb)
3179 dev_priv->display.update_primary_plane(crtc,
3183 drm_modeset_unlock(&crtc->mutex);
3187 void intel_prepare_reset(struct drm_device *dev)
3189 /* no reset support for gen2 */
3193 /* reset doesn't touch the display */
3194 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3197 drm_modeset_lock_all(dev);
3199 * Disabling the crtcs gracefully seems nicer. Also the
3200 * g33 docs say we should at least disable all the planes.
3202 intel_display_suspend(dev);
3205 void intel_finish_reset(struct drm_device *dev)
3207 struct drm_i915_private *dev_priv = to_i915(dev);
3210 * Flips in the rings will be nuked by the reset,
3211 * so complete all pending flips so that user space
3212 * will get its events and not get stuck.
3214 intel_complete_page_flips(dev);
3216 /* no reset support for gen2 */
3220 /* reset doesn't touch the display */
3221 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3223 * Flips in the rings have been nuked by the reset,
3224 * so update the base address of all primary
3225 * planes to the the last fb to make sure we're
3226 * showing the correct fb after a reset.
3228 intel_update_primary_planes(dev);
3233 * The display has been reset as well,
3234 * so need a full re-initialization.
3236 intel_runtime_pm_disable_interrupts(dev_priv);
3237 intel_runtime_pm_enable_interrupts(dev_priv);
3239 intel_modeset_init_hw(dev);
3241 spin_lock_irq(&dev_priv->irq_lock);
3242 if (dev_priv->display.hpd_irq_setup)
3243 dev_priv->display.hpd_irq_setup(dev);
3244 spin_unlock_irq(&dev_priv->irq_lock);
3246 intel_display_resume(dev);
3248 intel_hpd_init(dev_priv);
3250 drm_modeset_unlock_all(dev);
3254 intel_finish_fb(struct drm_framebuffer *old_fb)
3256 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3257 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3258 bool was_interruptible = dev_priv->mm.interruptible;
3261 /* Big Hammer, we also need to ensure that any pending
3262 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3263 * current scanout is retired before unpinning the old
3264 * framebuffer. Note that we rely on userspace rendering
3265 * into the buffer attached to the pipe they are waiting
3266 * on. If not, userspace generates a GPU hang with IPEHR
3267 * point to the MI_WAIT_FOR_EVENT.
3269 * This should only fail upon a hung GPU, in which case we
3270 * can safely continue.
3272 dev_priv->mm.interruptible = false;
3273 ret = i915_gem_object_wait_rendering(obj, true);
3274 dev_priv->mm.interruptible = was_interruptible;
3279 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3287 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3290 spin_lock_irq(&dev->event_lock);
3291 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3292 spin_unlock_irq(&dev->event_lock);
3297 static void intel_update_pipe_size(struct intel_crtc *crtc)
3299 struct drm_device *dev = crtc->base.dev;
3300 struct drm_i915_private *dev_priv = dev->dev_private;
3301 const struct drm_display_mode *adjusted_mode;
3307 * Update pipe size and adjust fitter if needed: the reason for this is
3308 * that in compute_mode_changes we check the native mode (not the pfit
3309 * mode) to see if we can flip rather than do a full mode set. In the
3310 * fastboot case, we'll flip, but if we don't update the pipesrc and
3311 * pfit state, we'll end up with a big fb scanned out into the wrong
3314 * To fix this properly, we need to hoist the checks up into
3315 * compute_mode_changes (or above), check the actual pfit state and
3316 * whether the platform allows pfit disable with pipe active, and only
3317 * then update the pipesrc and pfit state, even on the flip path.
3320 adjusted_mode = &crtc->config->base.adjusted_mode;
3322 I915_WRITE(PIPESRC(crtc->pipe),
3323 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3324 (adjusted_mode->crtc_vdisplay - 1));
3325 if (!crtc->config->pch_pfit.enabled &&
3326 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3327 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3328 I915_WRITE(PF_CTL(crtc->pipe), 0);
3329 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3330 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3332 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3333 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3336 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 int pipe = intel_crtc->pipe;
3344 /* enable normal train */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 if (IS_IVYBRIDGE(dev)) {
3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3351 temp &= ~FDI_LINK_TRAIN_NONE;
3352 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3354 I915_WRITE(reg, temp);
3356 reg = FDI_RX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (HAS_PCH_CPT(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE;
3365 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3367 /* wait one idle pattern time */
3371 /* IVB wants error correction enabled */
3372 if (IS_IVYBRIDGE(dev))
3373 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3374 FDI_FE_ERRC_ENABLE);
3377 /* The FDI link training functions for ILK/Ibexpeak. */
3378 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
3384 u32 reg, temp, tries;
3386 /* FDI needs bits from pipe first */
3387 assert_pipe_enabled(dev_priv, pipe);
3389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3391 reg = FDI_RX_IMR(pipe);
3392 temp = I915_READ(reg);
3393 temp &= ~FDI_RX_SYMBOL_LOCK;
3394 temp &= ~FDI_RX_BIT_LOCK;
3395 I915_WRITE(reg, temp);
3399 /* enable CPU FDI TX and PCH FDI RX */
3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3403 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3417 /* Ironlake workaround, enable clock pointer after FDI enable*/
3418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3420 FDI_RX_PHASE_SYNC_POINTER_EN);
3422 reg = FDI_RX_IIR(pipe);
3423 for (tries = 0; tries < 5; tries++) {
3424 temp = I915_READ(reg);
3425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427 if ((temp & FDI_RX_BIT_LOCK)) {
3428 DRM_DEBUG_KMS("FDI train 1 done.\n");
3429 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3434 DRM_ERROR("FDI train 1 fail!\n");
3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
3441 I915_WRITE(reg, temp);
3443 reg = FDI_RX_CTL(pipe);
3444 temp = I915_READ(reg);
3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2;
3447 I915_WRITE(reg, temp);
3452 reg = FDI_RX_IIR(pipe);
3453 for (tries = 0; tries < 5; tries++) {
3454 temp = I915_READ(reg);
3455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3457 if (temp & FDI_RX_SYMBOL_LOCK) {
3458 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3459 DRM_DEBUG_KMS("FDI train 2 done.\n");
3464 DRM_ERROR("FDI train 2 fail!\n");
3466 DRM_DEBUG_KMS("FDI train done\n");
3470 static const int snb_b_fdi_train_param[] = {
3471 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3472 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3473 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3474 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3477 /* The FDI link training functions for SNB/Cougarpoint. */
3478 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 int pipe = intel_crtc->pipe;
3484 u32 reg, temp, i, retry;
3486 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3488 reg = FDI_RX_IMR(pipe);
3489 temp = I915_READ(reg);
3490 temp &= ~FDI_RX_SYMBOL_LOCK;
3491 temp &= ~FDI_RX_BIT_LOCK;
3492 I915_WRITE(reg, temp);
3497 /* enable CPU FDI TX and PCH FDI RX */
3498 reg = FDI_TX_CTL(pipe);
3499 temp = I915_READ(reg);
3500 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3501 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_1;
3504 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3506 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3507 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3509 I915_WRITE(FDI_RX_MISC(pipe),
3510 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3512 reg = FDI_RX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 if (HAS_PCH_CPT(dev)) {
3515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3521 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3526 for (i = 0; i < 4; i++) {
3527 reg = FDI_TX_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530 temp |= snb_b_fdi_train_param[i];
3531 I915_WRITE(reg, temp);
3536 for (retry = 0; retry < 5; retry++) {
3537 reg = FDI_RX_IIR(pipe);
3538 temp = I915_READ(reg);
3539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540 if (temp & FDI_RX_BIT_LOCK) {
3541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542 DRM_DEBUG_KMS("FDI train 1 done.\n");
3551 DRM_ERROR("FDI train 1 fail!\n");
3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~FDI_LINK_TRAIN_NONE;
3557 temp |= FDI_LINK_TRAIN_PATTERN_2;
3559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3563 I915_WRITE(reg, temp);
3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
3567 if (HAS_PCH_CPT(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 I915_WRITE(reg, temp);
3579 for (i = 0; i < 4; i++) {
3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583 temp |= snb_b_fdi_train_param[i];
3584 I915_WRITE(reg, temp);
3589 for (retry = 0; retry < 5; retry++) {
3590 reg = FDI_RX_IIR(pipe);
3591 temp = I915_READ(reg);
3592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593 if (temp & FDI_RX_SYMBOL_LOCK) {
3594 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595 DRM_DEBUG_KMS("FDI train 2 done.\n");
3604 DRM_ERROR("FDI train 2 fail!\n");
3606 DRM_DEBUG_KMS("FDI train done.\n");
3609 /* Manual link training for Ivy Bridge A0 parts */
3610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 int pipe = intel_crtc->pipe;
3616 u32 reg, temp, i, j;
3618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3620 reg = FDI_RX_IMR(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_RX_SYMBOL_LOCK;
3623 temp &= ~FDI_RX_BIT_LOCK;
3624 I915_WRITE(reg, temp);
3629 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3630 I915_READ(FDI_RX_IIR(pipe)));
3632 /* Try each vswing and preemphasis setting twice before moving on */
3633 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3634 /* disable first in case we need to retry */
3635 reg = FDI_TX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3638 temp &= ~FDI_TX_ENABLE;
3639 I915_WRITE(reg, temp);
3641 reg = FDI_RX_CTL(pipe);
3642 temp = I915_READ(reg);
3643 temp &= ~FDI_LINK_TRAIN_AUTO;
3644 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3645 temp &= ~FDI_RX_ENABLE;
3646 I915_WRITE(reg, temp);
3648 /* enable CPU FDI TX and PCH FDI RX */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3652 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3653 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3655 temp |= snb_b_fdi_train_param[j/2];
3656 temp |= FDI_COMPOSITE_SYNC;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3659 I915_WRITE(FDI_RX_MISC(pipe),
3660 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3662 reg = FDI_RX_CTL(pipe);
3663 temp = I915_READ(reg);
3664 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3665 temp |= FDI_COMPOSITE_SYNC;
3666 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3669 udelay(1); /* should be 0.5us */
3671 for (i = 0; i < 4; i++) {
3672 reg = FDI_RX_IIR(pipe);
3673 temp = I915_READ(reg);
3674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3676 if (temp & FDI_RX_BIT_LOCK ||
3677 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3678 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3679 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3683 udelay(1); /* should be 0.5us */
3686 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3695 I915_WRITE(reg, temp);
3697 reg = FDI_RX_CTL(pipe);
3698 temp = I915_READ(reg);
3699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3701 I915_WRITE(reg, temp);
3704 udelay(2); /* should be 1.5us */
3706 for (i = 0; i < 4; i++) {
3707 reg = FDI_RX_IIR(pipe);
3708 temp = I915_READ(reg);
3709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3711 if (temp & FDI_RX_SYMBOL_LOCK ||
3712 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3714 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3718 udelay(2); /* should be 1.5us */
3721 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3725 DRM_DEBUG_KMS("FDI train done.\n");
3728 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3730 struct drm_device *dev = intel_crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe = intel_crtc->pipe;
3736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3740 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3741 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3747 /* Switch from Rawclk to PCDclk */
3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp | FDI_PCDCLK);
3754 /* Enable CPU FDI TX PLL, always on for Ironlake */
3755 reg = FDI_TX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3758 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3765 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3767 struct drm_device *dev = intel_crtc->base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 int pipe = intel_crtc->pipe;
3772 /* Switch from PCDclk to Rawclk */
3773 reg = FDI_RX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3777 /* Disable CPU FDI TX PLL */
3778 reg = FDI_TX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3789 /* Wait for the clocks to turn off. */
3794 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3802 /* disable CPU FDI tx and PCH FDI rx */
3803 reg = FDI_TX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3808 reg = FDI_RX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 temp &= ~(0x7 << 16);
3811 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3812 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3817 /* Ironlake workaround, disable clock pointer after downing FDI */
3818 if (HAS_PCH_IBX(dev))
3819 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3821 /* still set train pattern 1 */
3822 reg = FDI_TX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~FDI_LINK_TRAIN_NONE;
3825 temp |= FDI_LINK_TRAIN_PATTERN_1;
3826 I915_WRITE(reg, temp);
3828 reg = FDI_RX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 if (HAS_PCH_CPT(dev)) {
3831 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3837 /* BPC in FDI rx is consistent with that in PIPECONF */
3838 temp &= ~(0x07 << 16);
3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840 I915_WRITE(reg, temp);
3846 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3848 struct intel_crtc *crtc;
3850 /* Note that we don't need to be called with mode_config.lock here
3851 * as our list of CRTC objects is static for the lifetime of the
3852 * device and so cannot disappear as we iterate. Similarly, we can
3853 * happily treat the predicates as racy, atomic checks as userspace
3854 * cannot claim and pin a new fb without at least acquring the
3855 * struct_mutex and so serialising with us.
3857 for_each_intel_crtc(dev, crtc) {
3858 if (atomic_read(&crtc->unpin_work_count) == 0)
3861 if (crtc->unpin_work)
3862 intel_wait_for_vblank(dev, crtc->pipe);
3870 static void page_flip_completed(struct intel_crtc *intel_crtc)
3872 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3873 struct intel_unpin_work *work = intel_crtc->unpin_work;
3875 /* ensure that the unpin work is consistent wrt ->pending. */
3877 intel_crtc->unpin_work = NULL;
3880 drm_send_vblank_event(intel_crtc->base.dev,
3884 drm_crtc_vblank_put(&intel_crtc->base);
3886 wake_up_all(&dev_priv->pending_flip_queue);
3887 queue_work(dev_priv->wq, &work->work);
3889 trace_i915_flip_complete(intel_crtc->plane,
3890 work->pending_flip_obj);
3893 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3895 struct drm_device *dev = crtc->dev;
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3898 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3899 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3900 !intel_crtc_has_pending_flip(crtc),
3902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3904 spin_lock_irq(&dev->event_lock);
3905 if (intel_crtc->unpin_work) {
3906 WARN_ONCE(1, "Removing stuck page flip\n");
3907 page_flip_completed(intel_crtc);
3909 spin_unlock_irq(&dev->event_lock);
3912 if (crtc->primary->fb) {
3913 mutex_lock(&dev->struct_mutex);
3914 intel_finish_fb(crtc->primary->fb);
3915 mutex_unlock(&dev->struct_mutex);
3919 /* Program iCLKIP clock to the desired frequency */
3920 static void lpt_program_iclkip(struct drm_crtc *crtc)
3922 struct drm_device *dev = crtc->dev;
3923 struct drm_i915_private *dev_priv = dev->dev_private;
3924 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3925 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3928 mutex_lock(&dev_priv->sb_lock);
3930 /* It is necessary to ungate the pixclk gate prior to programming
3931 * the divisors, and gate it back when it is done.
3933 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3935 /* Disable SSCCTL */
3936 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3937 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3941 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3942 if (clock == 20000) {
3947 /* The iCLK virtual clock root frequency is in MHz,
3948 * but the adjusted_mode->crtc_clock in in KHz. To get the
3949 * divisors, it is necessary to divide one by another, so we
3950 * convert the virtual clock precision to KHz here for higher
3953 u32 iclk_virtual_root_freq = 172800 * 1000;
3954 u32 iclk_pi_range = 64;
3955 u32 desired_divisor, msb_divisor_value, pi_value;
3957 desired_divisor = (iclk_virtual_root_freq / clock);
3958 msb_divisor_value = desired_divisor / iclk_pi_range;
3959 pi_value = desired_divisor % iclk_pi_range;
3962 divsel = msb_divisor_value - 2;
3963 phaseinc = pi_value;
3966 /* This should not happen with any sane values */
3967 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3968 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3969 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3970 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3972 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3979 /* Program SSCDIVINTPHASE6 */
3980 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3981 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3982 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3983 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3984 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3985 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3986 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3987 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3989 /* Program SSCAUXDIV */
3990 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3991 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3992 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3993 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3995 /* Enable modulator and associated divider */
3996 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3997 temp &= ~SBI_SSCCTL_DISABLE;
3998 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4000 /* Wait for initialization time */
4003 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4005 mutex_unlock(&dev_priv->sb_lock);
4008 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4009 enum pipe pch_transcoder)
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4015 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4016 I915_READ(HTOTAL(cpu_transcoder)));
4017 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4018 I915_READ(HBLANK(cpu_transcoder)));
4019 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4020 I915_READ(HSYNC(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4023 I915_READ(VTOTAL(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4025 I915_READ(VBLANK(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4027 I915_READ(VSYNC(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4029 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4032 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4037 temp = I915_READ(SOUTH_CHICKEN1);
4038 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4041 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4042 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4044 temp &= ~FDI_BC_BIFURCATION_SELECT;
4046 temp |= FDI_BC_BIFURCATION_SELECT;
4048 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4049 I915_WRITE(SOUTH_CHICKEN1, temp);
4050 POSTING_READ(SOUTH_CHICKEN1);
4053 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4055 struct drm_device *dev = intel_crtc->base.dev;
4057 switch (intel_crtc->pipe) {
4061 if (intel_crtc->config->fdi_lanes > 2)
4062 cpt_set_fdi_bc_bifurcation(dev, false);
4064 cpt_set_fdi_bc_bifurcation(dev, true);
4068 cpt_set_fdi_bc_bifurcation(dev, true);
4077 * Enable PCH resources required for PCH ports:
4079 * - FDI training & RX/TX
4080 * - update transcoder timings
4081 * - DP transcoding bits
4084 static void ironlake_pch_enable(struct drm_crtc *crtc)
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
4092 assert_pch_transcoder_disabled(dev_priv, pipe);
4094 if (IS_IVYBRIDGE(dev))
4095 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4097 /* Write the TU size bits before fdi link training, so that error
4098 * detection works. */
4099 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4102 /* For PCH output, training FDI link */
4103 dev_priv->display.fdi_link_train(crtc);
4105 /* We need to program the right clock selection before writing the pixel
4106 * mutliplier into the DPLL. */
4107 if (HAS_PCH_CPT(dev)) {
4110 temp = I915_READ(PCH_DPLL_SEL);
4111 temp |= TRANS_DPLL_ENABLE(pipe);
4112 sel = TRANS_DPLLB_SEL(pipe);
4113 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4117 I915_WRITE(PCH_DPLL_SEL, temp);
4120 /* XXX: pch pll's can be enabled any time before we enable the PCH
4121 * transcoder, and we actually should do this to not upset any PCH
4122 * transcoder that already use the clock when we share it.
4124 * Note that enable_shared_dpll tries to do the right thing, but
4125 * get_shared_dpll unconditionally resets the pll - we need that to have
4126 * the right LVDS enable sequence. */
4127 intel_enable_shared_dpll(intel_crtc);
4129 /* set transcoder timing, panel must allow it */
4130 assert_panel_unlocked(dev_priv, pipe);
4131 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4133 intel_fdi_normal_train(crtc);
4135 /* For PCH DP, enable TRANS_DP_CTL */
4136 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4137 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4138 reg = TRANS_DP_CTL(pipe);
4139 temp = I915_READ(reg);
4140 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4141 TRANS_DP_SYNC_MASK |
4143 temp |= TRANS_DP_OUTPUT_ENABLE;
4144 temp |= bpc << 9; /* same format but at 11:9 */
4146 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4147 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4148 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4149 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4151 switch (intel_trans_dp_port_sel(crtc)) {
4153 temp |= TRANS_DP_PORT_SEL_B;
4156 temp |= TRANS_DP_PORT_SEL_C;
4159 temp |= TRANS_DP_PORT_SEL_D;
4165 I915_WRITE(reg, temp);
4168 ironlake_enable_pch_transcoder(dev_priv, pipe);
4171 static void lpt_pch_enable(struct drm_crtc *crtc)
4173 struct drm_device *dev = crtc->dev;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4178 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4180 lpt_program_iclkip(crtc);
4182 /* Set transcoder timing. */
4183 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4185 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4188 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4189 struct intel_crtc_state *crtc_state)
4191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4192 struct intel_shared_dpll *pll;
4193 struct intel_shared_dpll_config *shared_dpll;
4194 enum intel_dpll_id i;
4196 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4198 if (HAS_PCH_IBX(dev_priv->dev)) {
4199 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4200 i = (enum intel_dpll_id) crtc->pipe;
4201 pll = &dev_priv->shared_dplls[i];
4203 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4204 crtc->base.base.id, pll->name);
4206 WARN_ON(shared_dpll[i].crtc_mask);
4211 if (IS_BROXTON(dev_priv->dev)) {
4212 /* PLL is attached to port in bxt */
4213 struct intel_encoder *encoder;
4214 struct intel_digital_port *intel_dig_port;
4216 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4217 if (WARN_ON(!encoder))
4220 intel_dig_port = enc_to_dig_port(&encoder->base);
4221 /* 1:1 mapping between ports and PLLs */
4222 i = (enum intel_dpll_id)intel_dig_port->port;
4223 pll = &dev_priv->shared_dplls[i];
4224 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4225 crtc->base.base.id, pll->name);
4226 WARN_ON(shared_dpll[i].crtc_mask);
4231 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4232 pll = &dev_priv->shared_dplls[i];
4234 /* Only want to check enabled timings first */
4235 if (shared_dpll[i].crtc_mask == 0)
4238 if (memcmp(&crtc_state->dpll_hw_state,
4239 &shared_dpll[i].hw_state,
4240 sizeof(crtc_state->dpll_hw_state)) == 0) {
4241 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4242 crtc->base.base.id, pll->name,
4243 shared_dpll[i].crtc_mask,
4249 /* Ok no matching timings, maybe there's a free one? */
4250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4251 pll = &dev_priv->shared_dplls[i];
4252 if (shared_dpll[i].crtc_mask == 0) {
4253 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4254 crtc->base.base.id, pll->name);
4262 if (shared_dpll[i].crtc_mask == 0)
4263 shared_dpll[i].hw_state =
4264 crtc_state->dpll_hw_state;
4266 crtc_state->shared_dpll = i;
4267 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4268 pipe_name(crtc->pipe));
4270 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4275 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4277 struct drm_i915_private *dev_priv = to_i915(state->dev);
4278 struct intel_shared_dpll_config *shared_dpll;
4279 struct intel_shared_dpll *pll;
4280 enum intel_dpll_id i;
4282 if (!to_intel_atomic_state(state)->dpll_set)
4285 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4287 pll = &dev_priv->shared_dplls[i];
4288 pll->config = shared_dpll[i];
4292 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int dslreg = PIPEDSL(pipe);
4298 temp = I915_READ(dslreg);
4300 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4301 if (wait_for(I915_READ(dslreg) != temp, 5))
4302 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4307 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4308 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4309 int src_w, int src_h, int dst_w, int dst_h)
4311 struct intel_crtc_scaler_state *scaler_state =
4312 &crtc_state->scaler_state;
4313 struct intel_crtc *intel_crtc =
4314 to_intel_crtc(crtc_state->base.crtc);
4317 need_scaling = intel_rotation_90_or_270(rotation) ?
4318 (src_h != dst_w || src_w != dst_h):
4319 (src_w != dst_w || src_h != dst_h);
4322 * if plane is being disabled or scaler is no more required or force detach
4323 * - free scaler binded to this plane/crtc
4324 * - in order to do this, update crtc->scaler_usage
4326 * Here scaler state in crtc_state is set free so that
4327 * scaler can be assigned to other user. Actual register
4328 * update to free the scaler is done in plane/panel-fit programming.
4329 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4331 if (force_detach || !need_scaling) {
4332 if (*scaler_id >= 0) {
4333 scaler_state->scaler_users &= ~(1 << scaler_user);
4334 scaler_state->scalers[*scaler_id].in_use = 0;
4336 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4337 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4338 intel_crtc->pipe, scaler_user, *scaler_id,
4339 scaler_state->scaler_users);
4346 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4347 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4349 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4350 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4351 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4352 "size is out of scaler range\n",
4353 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4357 /* mark this plane as a scaler user in crtc_state */
4358 scaler_state->scaler_users |= (1 << scaler_user);
4359 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4360 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4361 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4362 scaler_state->scaler_users);
4368 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4370 * @state: crtc's scaler state
4373 * 0 - scaler_usage updated successfully
4374 * error - requested scaling cannot be supported or other error condition
4376 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4378 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4379 struct drm_display_mode *adjusted_mode =
4380 &state->base.adjusted_mode;
4382 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4383 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4385 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4386 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4387 state->pipe_src_w, state->pipe_src_h,
4388 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4392 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4394 * @state: crtc's scaler state
4395 * @plane_state: atomic plane state to update
4398 * 0 - scaler_usage updated successfully
4399 * error - requested scaling cannot be supported or other error condition
4401 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4402 struct intel_plane_state *plane_state)
4405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4406 struct intel_plane *intel_plane =
4407 to_intel_plane(plane_state->base.plane);
4408 struct drm_framebuffer *fb = plane_state->base.fb;
4411 bool force_detach = !fb || !plane_state->visible;
4413 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4414 intel_plane->base.base.id, intel_crtc->pipe,
4415 drm_plane_index(&intel_plane->base));
4417 ret = skl_update_scaler(crtc_state, force_detach,
4418 drm_plane_index(&intel_plane->base),
4419 &plane_state->scaler_id,
4420 plane_state->base.rotation,
4421 drm_rect_width(&plane_state->src) >> 16,
4422 drm_rect_height(&plane_state->src) >> 16,
4423 drm_rect_width(&plane_state->dst),
4424 drm_rect_height(&plane_state->dst));
4426 if (ret || plane_state->scaler_id < 0)
4429 /* check colorkey */
4430 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4431 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4432 intel_plane->base.base.id);
4436 /* Check src format */
4437 switch (fb->pixel_format) {
4438 case DRM_FORMAT_RGB565:
4439 case DRM_FORMAT_XBGR8888:
4440 case DRM_FORMAT_XRGB8888:
4441 case DRM_FORMAT_ABGR8888:
4442 case DRM_FORMAT_ARGB8888:
4443 case DRM_FORMAT_XRGB2101010:
4444 case DRM_FORMAT_XBGR2101010:
4445 case DRM_FORMAT_YUYV:
4446 case DRM_FORMAT_YVYU:
4447 case DRM_FORMAT_UYVY:
4448 case DRM_FORMAT_VYUY:
4451 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4452 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4459 static void skylake_scaler_disable(struct intel_crtc *crtc)
4463 for (i = 0; i < crtc->num_scalers; i++)
4464 skl_detach_scaler(crtc, i);
4467 static void skylake_pfit_enable(struct intel_crtc *crtc)
4469 struct drm_device *dev = crtc->base.dev;
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 int pipe = crtc->pipe;
4472 struct intel_crtc_scaler_state *scaler_state =
4473 &crtc->config->scaler_state;
4475 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4477 if (crtc->config->pch_pfit.enabled) {
4480 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4481 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4485 id = scaler_state->scaler_id;
4486 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4487 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4488 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4489 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4491 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4495 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4497 struct drm_device *dev = crtc->base.dev;
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499 int pipe = crtc->pipe;
4501 if (crtc->config->pch_pfit.enabled) {
4502 /* Force use of hard-coded filter coefficients
4503 * as some pre-programmed values are broken,
4506 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4507 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4508 PF_PIPE_SEL_IVB(pipe));
4510 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4511 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4512 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4516 void hsw_enable_ips(struct intel_crtc *crtc)
4518 struct drm_device *dev = crtc->base.dev;
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4521 if (!crtc->config->ips_enabled)
4524 /* We can only enable IPS after we enable a plane and wait for a vblank */
4525 intel_wait_for_vblank(dev, crtc->pipe);
4527 assert_plane_enabled(dev_priv, crtc->plane);
4528 if (IS_BROADWELL(dev)) {
4529 mutex_lock(&dev_priv->rps.hw_lock);
4530 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4531 mutex_unlock(&dev_priv->rps.hw_lock);
4532 /* Quoting Art Runyan: "its not safe to expect any particular
4533 * value in IPS_CTL bit 31 after enabling IPS through the
4534 * mailbox." Moreover, the mailbox may return a bogus state,
4535 * so we need to just enable it and continue on.
4538 I915_WRITE(IPS_CTL, IPS_ENABLE);
4539 /* The bit only becomes 1 in the next vblank, so this wait here
4540 * is essentially intel_wait_for_vblank. If we don't have this
4541 * and don't wait for vblanks until the end of crtc_enable, then
4542 * the HW state readout code will complain that the expected
4543 * IPS_CTL value is not the one we read. */
4544 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4545 DRM_ERROR("Timed out waiting for IPS enable\n");
4549 void hsw_disable_ips(struct intel_crtc *crtc)
4551 struct drm_device *dev = crtc->base.dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4554 if (!crtc->config->ips_enabled)
4557 assert_plane_enabled(dev_priv, crtc->plane);
4558 if (IS_BROADWELL(dev)) {
4559 mutex_lock(&dev_priv->rps.hw_lock);
4560 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4561 mutex_unlock(&dev_priv->rps.hw_lock);
4562 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4563 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4564 DRM_ERROR("Timed out waiting for IPS disable\n");
4566 I915_WRITE(IPS_CTL, 0);
4567 POSTING_READ(IPS_CTL);
4570 /* We need to wait for a vblank before we can disable the plane. */
4571 intel_wait_for_vblank(dev, crtc->pipe);
4574 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4575 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4577 struct drm_device *dev = crtc->dev;
4578 struct drm_i915_private *dev_priv = dev->dev_private;
4579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4580 enum pipe pipe = intel_crtc->pipe;
4581 int palreg = PALETTE(pipe);
4583 bool reenable_ips = false;
4585 /* The clocks have to be on to load the palette. */
4586 if (!crtc->state->active)
4589 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4590 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4591 assert_dsi_pll_enabled(dev_priv);
4593 assert_pll_enabled(dev_priv, pipe);
4596 /* use legacy palette for Ironlake */
4597 if (!HAS_GMCH_DISPLAY(dev))
4598 palreg = LGC_PALETTE(pipe);
4600 /* Workaround : Do not read or write the pipe palette/gamma data while
4601 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4603 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4604 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4605 GAMMA_MODE_MODE_SPLIT)) {
4606 hsw_disable_ips(intel_crtc);
4607 reenable_ips = true;
4610 for (i = 0; i < 256; i++) {
4611 I915_WRITE(palreg + 4 * i,
4612 (intel_crtc->lut_r[i] << 16) |
4613 (intel_crtc->lut_g[i] << 8) |
4614 intel_crtc->lut_b[i]);
4618 hsw_enable_ips(intel_crtc);
4621 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4623 if (intel_crtc->overlay) {
4624 struct drm_device *dev = intel_crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4627 mutex_lock(&dev->struct_mutex);
4628 dev_priv->mm.interruptible = false;
4629 (void) intel_overlay_switch_off(intel_crtc->overlay);
4630 dev_priv->mm.interruptible = true;
4631 mutex_unlock(&dev->struct_mutex);
4634 /* Let userspace switch the overlay on again. In most cases userspace
4635 * has to recompute where to put it anyway.
4640 * intel_post_enable_primary - Perform operations after enabling primary plane
4641 * @crtc: the CRTC whose primary plane was just enabled
4643 * Performs potentially sleeping operations that must be done after the primary
4644 * plane is enabled, such as updating FBC and IPS. Note that this may be
4645 * called due to an explicit primary plane update, or due to an implicit
4646 * re-enable that is caused when a sprite plane is updated to no longer
4647 * completely hide the primary plane.
4650 intel_post_enable_primary(struct drm_crtc *crtc)
4652 struct drm_device *dev = crtc->dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4655 int pipe = intel_crtc->pipe;
4658 * BDW signals flip done immediately if the plane
4659 * is disabled, even if the plane enable is already
4660 * armed to occur at the next vblank :(
4662 if (IS_BROADWELL(dev))
4663 intel_wait_for_vblank(dev, pipe);
4666 * FIXME IPS should be fine as long as one plane is
4667 * enabled, but in practice it seems to have problems
4668 * when going from primary only to sprite only and vice
4671 hsw_enable_ips(intel_crtc);
4674 * Gen2 reports pipe underruns whenever all planes are disabled.
4675 * So don't enable underrun reporting before at least some planes
4677 * FIXME: Need to fix the logic to work when we turn off all planes
4678 * but leave the pipe running.
4681 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4683 /* Underruns don't raise interrupts, so check manually. */
4684 if (HAS_GMCH_DISPLAY(dev))
4685 i9xx_check_fifo_underruns(dev_priv);
4689 * intel_pre_disable_primary - Perform operations before disabling primary plane
4690 * @crtc: the CRTC whose primary plane is to be disabled
4692 * Performs potentially sleeping operations that must be done before the
4693 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4694 * be called due to an explicit primary plane update, or due to an implicit
4695 * disable that is caused when a sprite plane completely hides the primary
4699 intel_pre_disable_primary(struct drm_crtc *crtc)
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 int pipe = intel_crtc->pipe;
4707 * Gen2 reports pipe underruns whenever all planes are disabled.
4708 * So diasble underrun reporting before all the planes get disabled.
4709 * FIXME: Need to fix the logic to work when we turn off all planes
4710 * but leave the pipe running.
4713 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4716 * Vblank time updates from the shadow to live plane control register
4717 * are blocked if the memory self-refresh mode is active at that
4718 * moment. So to make sure the plane gets truly disabled, disable
4719 * first the self-refresh mode. The self-refresh enable bit in turn
4720 * will be checked/applied by the HW only at the next frame start
4721 * event which is after the vblank start event, so we need to have a
4722 * wait-for-vblank between disabling the plane and the pipe.
4724 if (HAS_GMCH_DISPLAY(dev)) {
4725 intel_set_memory_cxsr(dev_priv, false);
4726 dev_priv->wm.vlv.cxsr = false;
4727 intel_wait_for_vblank(dev, pipe);
4731 * FIXME IPS should be fine as long as one plane is
4732 * enabled, but in practice it seems to have problems
4733 * when going from primary only to sprite only and vice
4736 hsw_disable_ips(intel_crtc);
4739 static void intel_post_plane_update(struct intel_crtc *crtc)
4741 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4742 struct drm_device *dev = crtc->base.dev;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 struct drm_plane *plane;
4746 if (atomic->wait_vblank)
4747 intel_wait_for_vblank(dev, crtc->pipe);
4749 intel_frontbuffer_flip(dev, atomic->fb_bits);
4751 if (atomic->disable_cxsr)
4752 crtc->wm.cxsr_allowed = true;
4754 if (crtc->atomic.update_wm_post)
4755 intel_update_watermarks(&crtc->base);
4757 if (atomic->update_fbc)
4758 intel_fbc_update(dev_priv);
4760 if (atomic->post_enable_primary)
4761 intel_post_enable_primary(&crtc->base);
4763 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4764 intel_update_sprite_watermarks(plane, &crtc->base,
4765 0, 0, 0, false, false);
4767 memset(atomic, 0, sizeof(*atomic));
4770 static void intel_pre_plane_update(struct intel_crtc *crtc)
4772 struct drm_device *dev = crtc->base.dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4775 struct drm_plane *p;
4777 /* Track fb's for any planes being disabled */
4778 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4779 struct intel_plane *plane = to_intel_plane(p);
4781 mutex_lock(&dev->struct_mutex);
4782 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4783 plane->frontbuffer_bit);
4784 mutex_unlock(&dev->struct_mutex);
4787 if (atomic->wait_for_flips)
4788 intel_crtc_wait_for_pending_flips(&crtc->base);
4790 if (atomic->disable_fbc)
4791 intel_fbc_disable_crtc(crtc);
4793 if (crtc->atomic.disable_ips)
4794 hsw_disable_ips(crtc);
4796 if (atomic->pre_disable_primary)
4797 intel_pre_disable_primary(&crtc->base);
4799 if (atomic->disable_cxsr) {
4800 crtc->wm.cxsr_allowed = false;
4801 intel_set_memory_cxsr(dev_priv, false);
4805 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4807 struct drm_device *dev = crtc->dev;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 struct drm_plane *p;
4810 int pipe = intel_crtc->pipe;
4812 intel_crtc_dpms_overlay_disable(intel_crtc);
4814 drm_for_each_plane_mask(p, dev, plane_mask)
4815 to_intel_plane(p)->disable_plane(p, crtc);
4818 * FIXME: Once we grow proper nuclear flip support out of this we need
4819 * to compute the mask of flip planes precisely. For the time being
4820 * consider this a flip to a NULL plane.
4822 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4825 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4830 struct intel_encoder *encoder;
4831 int pipe = intel_crtc->pipe;
4833 if (WARN_ON(intel_crtc->active))
4836 if (intel_crtc->config->has_pch_encoder)
4837 intel_prepare_shared_dpll(intel_crtc);
4839 if (intel_crtc->config->has_dp_encoder)
4840 intel_dp_set_m_n(intel_crtc, M1_N1);
4842 intel_set_pipe_timings(intel_crtc);
4844 if (intel_crtc->config->has_pch_encoder) {
4845 intel_cpu_transcoder_set_m_n(intel_crtc,
4846 &intel_crtc->config->fdi_m_n, NULL);
4849 ironlake_set_pipeconf(crtc);
4851 intel_crtc->active = true;
4853 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4854 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4856 for_each_encoder_on_crtc(dev, crtc, encoder)
4857 if (encoder->pre_enable)
4858 encoder->pre_enable(encoder);
4860 if (intel_crtc->config->has_pch_encoder) {
4861 /* Note: FDI PLL enabling _must_ be done before we enable the
4862 * cpu pipes, hence this is separate from all the other fdi/pch
4864 ironlake_fdi_pll_enable(intel_crtc);
4866 assert_fdi_tx_disabled(dev_priv, pipe);
4867 assert_fdi_rx_disabled(dev_priv, pipe);
4870 ironlake_pfit_enable(intel_crtc);
4873 * On ILK+ LUT must be loaded before the pipe is running but with
4876 intel_crtc_load_lut(crtc);
4878 intel_update_watermarks(crtc);
4879 intel_enable_pipe(intel_crtc);
4881 if (intel_crtc->config->has_pch_encoder)
4882 ironlake_pch_enable(crtc);
4884 assert_vblank_disabled(crtc);
4885 drm_crtc_vblank_on(crtc);
4887 for_each_encoder_on_crtc(dev, crtc, encoder)
4888 encoder->enable(encoder);
4890 if (HAS_PCH_CPT(dev))
4891 cpt_verify_modeset(dev, intel_crtc->pipe);
4894 /* IPS only exists on ULT machines and is tied to pipe A. */
4895 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4897 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4900 static void haswell_crtc_enable(struct drm_crtc *crtc)
4902 struct drm_device *dev = crtc->dev;
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905 struct intel_encoder *encoder;
4906 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4907 struct intel_crtc_state *pipe_config =
4908 to_intel_crtc_state(crtc->state);
4910 if (WARN_ON(intel_crtc->active))
4913 if (intel_crtc_to_shared_dpll(intel_crtc))
4914 intel_enable_shared_dpll(intel_crtc);
4916 if (intel_crtc->config->has_dp_encoder)
4917 intel_dp_set_m_n(intel_crtc, M1_N1);
4919 intel_set_pipe_timings(intel_crtc);
4921 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4922 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4923 intel_crtc->config->pixel_multiplier - 1);
4926 if (intel_crtc->config->has_pch_encoder) {
4927 intel_cpu_transcoder_set_m_n(intel_crtc,
4928 &intel_crtc->config->fdi_m_n, NULL);
4931 haswell_set_pipeconf(crtc);
4933 intel_set_pipe_csc(crtc);
4935 intel_crtc->active = true;
4937 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 if (encoder->pre_enable)
4940 encoder->pre_enable(encoder);
4942 if (intel_crtc->config->has_pch_encoder) {
4943 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4945 dev_priv->display.fdi_link_train(crtc);
4948 intel_ddi_enable_pipe_clock(intel_crtc);
4950 if (INTEL_INFO(dev)->gen == 9)
4951 skylake_pfit_enable(intel_crtc);
4952 else if (INTEL_INFO(dev)->gen < 9)
4953 ironlake_pfit_enable(intel_crtc);
4955 MISSING_CASE(INTEL_INFO(dev)->gen);
4958 * On ILK+ LUT must be loaded before the pipe is running but with
4961 intel_crtc_load_lut(crtc);
4963 intel_ddi_set_pipe_settings(crtc);
4964 intel_ddi_enable_transcoder_func(crtc);
4966 intel_update_watermarks(crtc);
4967 intel_enable_pipe(intel_crtc);
4969 if (intel_crtc->config->has_pch_encoder)
4970 lpt_pch_enable(crtc);
4972 if (intel_crtc->config->dp_encoder_is_mst)
4973 intel_ddi_set_vc_payload_alloc(crtc, true);
4975 assert_vblank_disabled(crtc);
4976 drm_crtc_vblank_on(crtc);
4978 for_each_encoder_on_crtc(dev, crtc, encoder) {
4979 encoder->enable(encoder);
4980 intel_opregion_notify_encoder(encoder, true);
4983 /* If we change the relative order between pipe/planes enabling, we need
4984 * to change the workaround. */
4985 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4986 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4987 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4988 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4992 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 int pipe = crtc->pipe;
4998 /* To avoid upsetting the power well on haswell only disable the pfit if
4999 * it's in use. The hw state code will make sure we get this right. */
5000 if (crtc->config->pch_pfit.enabled) {
5001 I915_WRITE(PF_CTL(pipe), 0);
5002 I915_WRITE(PF_WIN_POS(pipe), 0);
5003 I915_WRITE(PF_WIN_SZ(pipe), 0);
5007 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5009 struct drm_device *dev = crtc->dev;
5010 struct drm_i915_private *dev_priv = dev->dev_private;
5011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012 struct intel_encoder *encoder;
5013 int pipe = intel_crtc->pipe;
5016 for_each_encoder_on_crtc(dev, crtc, encoder)
5017 encoder->disable(encoder);
5019 drm_crtc_vblank_off(crtc);
5020 assert_vblank_disabled(crtc);
5022 if (intel_crtc->config->has_pch_encoder)
5023 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5025 intel_disable_pipe(intel_crtc);
5027 ironlake_pfit_disable(intel_crtc);
5029 if (intel_crtc->config->has_pch_encoder)
5030 ironlake_fdi_disable(crtc);
5032 for_each_encoder_on_crtc(dev, crtc, encoder)
5033 if (encoder->post_disable)
5034 encoder->post_disable(encoder);
5036 if (intel_crtc->config->has_pch_encoder) {
5037 ironlake_disable_pch_transcoder(dev_priv, pipe);
5039 if (HAS_PCH_CPT(dev)) {
5040 /* disable TRANS_DP_CTL */
5041 reg = TRANS_DP_CTL(pipe);
5042 temp = I915_READ(reg);
5043 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5044 TRANS_DP_PORT_SEL_MASK);
5045 temp |= TRANS_DP_PORT_SEL_NONE;
5046 I915_WRITE(reg, temp);
5048 /* disable DPLL_SEL */
5049 temp = I915_READ(PCH_DPLL_SEL);
5050 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5051 I915_WRITE(PCH_DPLL_SEL, temp);
5054 ironlake_fdi_pll_disable(intel_crtc);
5057 intel_crtc->active = false;
5058 intel_update_watermarks(crtc);
5061 static void haswell_crtc_disable(struct drm_crtc *crtc)
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 struct intel_encoder *encoder;
5067 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5069 for_each_encoder_on_crtc(dev, crtc, encoder) {
5070 intel_opregion_notify_encoder(encoder, false);
5071 encoder->disable(encoder);
5074 drm_crtc_vblank_off(crtc);
5075 assert_vblank_disabled(crtc);
5077 if (intel_crtc->config->has_pch_encoder)
5078 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5080 intel_disable_pipe(intel_crtc);
5082 if (intel_crtc->config->dp_encoder_is_mst)
5083 intel_ddi_set_vc_payload_alloc(crtc, false);
5085 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5087 if (INTEL_INFO(dev)->gen == 9)
5088 skylake_scaler_disable(intel_crtc);
5089 else if (INTEL_INFO(dev)->gen < 9)
5090 ironlake_pfit_disable(intel_crtc);
5092 MISSING_CASE(INTEL_INFO(dev)->gen);
5094 intel_ddi_disable_pipe_clock(intel_crtc);
5096 if (intel_crtc->config->has_pch_encoder) {
5097 lpt_disable_pch_transcoder(dev_priv);
5098 intel_ddi_fdi_disable(crtc);
5101 for_each_encoder_on_crtc(dev, crtc, encoder)
5102 if (encoder->post_disable)
5103 encoder->post_disable(encoder);
5105 intel_crtc->active = false;
5106 intel_update_watermarks(crtc);
5109 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5111 struct drm_device *dev = crtc->base.dev;
5112 struct drm_i915_private *dev_priv = dev->dev_private;
5113 struct intel_crtc_state *pipe_config = crtc->config;
5115 if (!pipe_config->gmch_pfit.control)
5119 * The panel fitter should only be adjusted whilst the pipe is disabled,
5120 * according to register description and PRM.
5122 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5123 assert_pipe_disabled(dev_priv, crtc->pipe);
5125 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5126 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5128 /* Border color in case we don't scale up to the full screen. Black by
5129 * default, change to something else for debugging. */
5130 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5133 static enum intel_display_power_domain port_to_power_domain(enum port port)
5137 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5139 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5141 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5143 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146 return POWER_DOMAIN_PORT_OTHER;
5150 #define for_each_power_domain(domain, mask) \
5151 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5152 if ((1 << (domain)) & (mask))
5154 enum intel_display_power_domain
5155 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5157 struct drm_device *dev = intel_encoder->base.dev;
5158 struct intel_digital_port *intel_dig_port;
5160 switch (intel_encoder->type) {
5161 case INTEL_OUTPUT_UNKNOWN:
5162 /* Only DDI platforms should ever use this output type */
5163 WARN_ON_ONCE(!HAS_DDI(dev));
5164 case INTEL_OUTPUT_DISPLAYPORT:
5165 case INTEL_OUTPUT_HDMI:
5166 case INTEL_OUTPUT_EDP:
5167 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5168 return port_to_power_domain(intel_dig_port->port);
5169 case INTEL_OUTPUT_DP_MST:
5170 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5171 return port_to_power_domain(intel_dig_port->port);
5172 case INTEL_OUTPUT_ANALOG:
5173 return POWER_DOMAIN_PORT_CRT;
5174 case INTEL_OUTPUT_DSI:
5175 return POWER_DOMAIN_PORT_DSI;
5177 return POWER_DOMAIN_PORT_OTHER;
5181 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5183 struct drm_device *dev = crtc->dev;
5184 struct intel_encoder *intel_encoder;
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 enum pipe pipe = intel_crtc->pipe;
5188 enum transcoder transcoder;
5190 if (!crtc->state->active)
5193 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5195 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5196 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5197 if (intel_crtc->config->pch_pfit.enabled ||
5198 intel_crtc->config->pch_pfit.force_thru)
5199 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5201 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5202 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5207 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5209 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5211 enum intel_display_power_domain domain;
5212 unsigned long domains, new_domains, old_domains;
5214 old_domains = intel_crtc->enabled_power_domains;
5215 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5217 domains = new_domains & ~old_domains;
5219 for_each_power_domain(domain, domains)
5220 intel_display_power_get(dev_priv, domain);
5222 return old_domains & ~new_domains;
5225 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5226 unsigned long domains)
5228 enum intel_display_power_domain domain;
5230 for_each_power_domain(domain, domains)
5231 intel_display_power_put(dev_priv, domain);
5234 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5236 struct drm_device *dev = state->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 unsigned long put_domains[I915_MAX_PIPES] = {};
5239 struct drm_crtc_state *crtc_state;
5240 struct drm_crtc *crtc;
5243 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5244 if (needs_modeset(crtc->state))
5245 put_domains[to_intel_crtc(crtc)->pipe] =
5246 modeset_get_crtc_power_domains(crtc);
5249 if (dev_priv->display.modeset_commit_cdclk) {
5250 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5252 if (cdclk != dev_priv->cdclk_freq &&
5253 !WARN_ON(!state->allow_modeset))
5254 dev_priv->display.modeset_commit_cdclk(state);
5257 for (i = 0; i < I915_MAX_PIPES; i++)
5259 modeset_put_power_domains(dev_priv, put_domains[i]);
5262 static void intel_update_max_cdclk(struct drm_device *dev)
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5266 if (IS_SKYLAKE(dev)) {
5267 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5269 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5270 dev_priv->max_cdclk_freq = 675000;
5271 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5272 dev_priv->max_cdclk_freq = 540000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5274 dev_priv->max_cdclk_freq = 450000;
5276 dev_priv->max_cdclk_freq = 337500;
5277 } else if (IS_BROADWELL(dev)) {
5279 * FIXME with extra cooling we can allow
5280 * 540 MHz for ULX and 675 Mhz for ULT.
5281 * How can we know if extra cooling is
5282 * available? PCI ID, VTB, something else?
5284 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5285 dev_priv->max_cdclk_freq = 450000;
5286 else if (IS_BDW_ULX(dev))
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULT(dev))
5289 dev_priv->max_cdclk_freq = 540000;
5291 dev_priv->max_cdclk_freq = 675000;
5292 } else if (IS_CHERRYVIEW(dev)) {
5293 dev_priv->max_cdclk_freq = 320000;
5294 } else if (IS_VALLEYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 400000;
5297 /* otherwise assume cdclk is fixed */
5298 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5301 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302 dev_priv->max_cdclk_freq);
5305 static void intel_update_cdclk(struct drm_device *dev)
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5309 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311 dev_priv->cdclk_freq);
5314 * Program the gmbus_freq based on the cdclk frequency.
5315 * BSpec erroneously claims we should aim for 4MHz, but
5316 * in fact 1MHz is the correct frequency.
5318 if (IS_VALLEYVIEW(dev)) {
5320 * Program the gmbus_freq based on the cdclk frequency.
5321 * BSpec erroneously claims we should aim for 4MHz, but
5322 * in fact 1MHz is the correct frequency.
5324 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5327 if (dev_priv->max_cdclk_freq == 0)
5328 intel_update_max_cdclk(dev);
5331 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5336 uint32_t current_freq;
5339 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5340 switch (frequency) {
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5343 ratio = BXT_DE_PLL_RATIO(60);
5346 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5347 ratio = BXT_DE_PLL_RATIO(60);
5350 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5351 ratio = BXT_DE_PLL_RATIO(60);
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5355 ratio = BXT_DE_PLL_RATIO(60);
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5359 ratio = BXT_DE_PLL_RATIO(65);
5363 * Bypass frequency with DE PLL disabled. Init ratio, divider
5364 * to suppress GCC warning.
5370 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5375 mutex_lock(&dev_priv->rps.hw_lock);
5376 /* Inform power controller of upcoming frequency change */
5377 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5379 mutex_unlock(&dev_priv->rps.hw_lock);
5382 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5387 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5388 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5389 current_freq = current_freq * 500 + 1000;
5392 * DE PLL has to be disabled when
5393 * - setting to 19.2MHz (bypass, PLL isn't used)
5394 * - before setting to 624MHz (PLL needs toggling)
5395 * - before setting to any frequency from 624MHz (PLL needs toggling)
5397 if (frequency == 19200 || frequency == 624000 ||
5398 current_freq == 624000) {
5399 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5401 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5403 DRM_ERROR("timout waiting for DE PLL unlock\n");
5406 if (frequency != 19200) {
5409 val = I915_READ(BXT_DE_PLL_CTL);
5410 val &= ~BXT_DE_PLL_RATIO_MASK;
5412 I915_WRITE(BXT_DE_PLL_CTL, val);
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5416 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5417 DRM_ERROR("timeout waiting for DE PLL lock\n");
5419 val = I915_READ(CDCLK_CTL);
5420 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5423 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5426 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427 if (frequency >= 500000)
5428 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5430 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5431 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5432 val |= (frequency - 1000) / 500;
5433 I915_WRITE(CDCLK_CTL, val);
5436 mutex_lock(&dev_priv->rps.hw_lock);
5437 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5438 DIV_ROUND_UP(frequency, 25000));
5439 mutex_unlock(&dev_priv->rps.hw_lock);
5442 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5447 intel_update_cdclk(dev);
5450 void broxton_init_cdclk(struct drm_device *dev)
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5456 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5457 * or else the reset will hang because there is no PCH to respond.
5458 * Move the handshake programming to initialization sequence.
5459 * Previously was left up to BIOS.
5461 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5462 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5463 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5465 /* Enable PG1 for cdclk */
5466 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5468 /* check if cd clock is enabled */
5469 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5470 DRM_DEBUG_KMS("Display already initialized\n");
5476 * - The initial CDCLK needs to be read from VBT.
5477 * Need to make this change after VBT has changes for BXT.
5478 * - check if setting the max (or any) cdclk freq is really necessary
5479 * here, it belongs to modeset time
5481 broxton_set_cdclk(dev, 624000);
5483 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5484 POSTING_READ(DBUF_CTL);
5488 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5489 DRM_ERROR("DBuf power enable timeout!\n");
5492 void broxton_uninit_cdclk(struct drm_device *dev)
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5496 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5497 POSTING_READ(DBUF_CTL);
5501 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5502 DRM_ERROR("DBuf power disable timeout!\n");
5504 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5505 broxton_set_cdclk(dev, 19200);
5507 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5510 static const struct skl_cdclk_entry {
5513 } skl_cdclk_frequencies[] = {
5514 { .freq = 308570, .vco = 8640 },
5515 { .freq = 337500, .vco = 8100 },
5516 { .freq = 432000, .vco = 8640 },
5517 { .freq = 450000, .vco = 8100 },
5518 { .freq = 540000, .vco = 8100 },
5519 { .freq = 617140, .vco = 8640 },
5520 { .freq = 675000, .vco = 8100 },
5523 static unsigned int skl_cdclk_decimal(unsigned int freq)
5525 return (freq - 1000) / 500;
5528 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5532 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5533 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5535 if (e->freq == freq)
5543 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5545 unsigned int min_freq;
5548 /* select the minimum CDCLK before enabling DPLL 0 */
5549 val = I915_READ(CDCLK_CTL);
5550 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5551 val |= CDCLK_FREQ_337_308;
5553 if (required_vco == 8640)
5558 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5560 I915_WRITE(CDCLK_CTL, val);
5561 POSTING_READ(CDCLK_CTL);
5564 * We always enable DPLL0 with the lowest link rate possible, but still
5565 * taking into account the VCO required to operate the eDP panel at the
5566 * desired frequency. The usual DP link rates operate with a VCO of
5567 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5568 * The modeset code is responsible for the selection of the exact link
5569 * rate later on, with the constraint of choosing a frequency that
5570 * works with required_vco.
5572 val = I915_READ(DPLL_CTRL1);
5574 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5575 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5576 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5577 if (required_vco == 8640)
5578 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5581 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5584 I915_WRITE(DPLL_CTRL1, val);
5585 POSTING_READ(DPLL_CTRL1);
5587 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5589 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5590 DRM_ERROR("DPLL0 not locked\n");
5593 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5598 /* inform PCU we want to change CDCLK */
5599 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5600 mutex_lock(&dev_priv->rps.hw_lock);
5601 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5602 mutex_unlock(&dev_priv->rps.hw_lock);
5604 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5607 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5611 for (i = 0; i < 15; i++) {
5612 if (skl_cdclk_pcu_ready(dev_priv))
5620 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5622 struct drm_device *dev = dev_priv->dev;
5623 u32 freq_select, pcu_ack;
5625 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5627 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5628 DRM_ERROR("failed to inform PCU about cdclk change\n");
5636 freq_select = CDCLK_FREQ_450_432;
5640 freq_select = CDCLK_FREQ_540;
5646 freq_select = CDCLK_FREQ_337_308;
5651 freq_select = CDCLK_FREQ_675_617;
5656 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5657 POSTING_READ(CDCLK_CTL);
5659 /* inform PCU of the change */
5660 mutex_lock(&dev_priv->rps.hw_lock);
5661 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5662 mutex_unlock(&dev_priv->rps.hw_lock);
5664 intel_update_cdclk(dev);
5667 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5669 /* disable DBUF power */
5670 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5671 POSTING_READ(DBUF_CTL);
5675 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5676 DRM_ERROR("DBuf power disable timeout\n");
5679 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5680 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5681 DRM_ERROR("Couldn't disable DPLL0\n");
5683 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5686 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5689 unsigned int required_vco;
5691 /* enable PCH reset handshake */
5692 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5693 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5695 /* enable PG1 and Misc I/O */
5696 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5698 /* DPLL0 already enabed !? */
5699 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5700 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5705 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5706 skl_dpll0_enable(dev_priv, required_vco);
5708 /* set CDCLK to the frequency the BIOS chose */
5709 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5711 /* enable DBUF power */
5712 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5713 POSTING_READ(DBUF_CTL);
5717 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5718 DRM_ERROR("DBuf power enable timeout\n");
5721 /* returns HPLL frequency in kHz */
5722 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5724 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5726 /* Obtain SKU information */
5727 mutex_lock(&dev_priv->sb_lock);
5728 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5729 CCK_FUSE_HPLL_FREQ_MASK;
5730 mutex_unlock(&dev_priv->sb_lock);
5732 return vco_freq[hpll_freq] * 1000;
5735 /* Adjust CDclk dividers to allow high res or save power if possible */
5736 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5741 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5742 != dev_priv->cdclk_freq);
5744 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5746 else if (cdclk == 266667)
5751 mutex_lock(&dev_priv->rps.hw_lock);
5752 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5753 val &= ~DSPFREQGUAR_MASK;
5754 val |= (cmd << DSPFREQGUAR_SHIFT);
5755 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5756 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5757 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5759 DRM_ERROR("timed out waiting for CDclk change\n");
5761 mutex_unlock(&dev_priv->rps.hw_lock);
5763 mutex_lock(&dev_priv->sb_lock);
5765 if (cdclk == 400000) {
5768 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5770 /* adjust cdclk divider */
5771 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5772 val &= ~DISPLAY_FREQUENCY_VALUES;
5774 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5776 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5777 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5779 DRM_ERROR("timed out waiting for CDclk change\n");
5782 /* adjust self-refresh exit latency value */
5783 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5787 * For high bandwidth configs, we set a higher latency in the bunit
5788 * so that the core display fetch happens in time to avoid underruns.
5790 if (cdclk == 400000)
5791 val |= 4500 / 250; /* 4.5 usec */
5793 val |= 3000 / 250; /* 3.0 usec */
5794 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5796 mutex_unlock(&dev_priv->sb_lock);
5798 intel_update_cdclk(dev);
5801 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5803 struct drm_i915_private *dev_priv = dev->dev_private;
5806 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5807 != dev_priv->cdclk_freq);
5816 MISSING_CASE(cdclk);
5821 * Specs are full of misinformation, but testing on actual
5822 * hardware has shown that we just need to write the desired
5823 * CCK divider into the Punit register.
5825 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5827 mutex_lock(&dev_priv->rps.hw_lock);
5828 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5829 val &= ~DSPFREQGUAR_MASK_CHV;
5830 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5831 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5832 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5833 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5835 DRM_ERROR("timed out waiting for CDclk change\n");
5837 mutex_unlock(&dev_priv->rps.hw_lock);
5839 intel_update_cdclk(dev);
5842 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5845 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5846 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5849 * Really only a few cases to deal with, as only 4 CDclks are supported:
5852 * 320/333MHz (depends on HPLL freq)
5854 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5855 * of the lower bin and adjust if needed.
5857 * We seem to get an unstable or solid color picture at 200MHz.
5858 * Not sure what's wrong. For now use 200MHz only when all pipes
5861 if (!IS_CHERRYVIEW(dev_priv) &&
5862 max_pixclk > freq_320*limit/100)
5864 else if (max_pixclk > 266667*limit/100)
5866 else if (max_pixclk > 0)
5872 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5877 * - remove the guardband, it's not needed on BXT
5878 * - set 19.2MHz bypass frequency if there are no active pipes
5880 if (max_pixclk > 576000*9/10)
5882 else if (max_pixclk > 384000*9/10)
5884 else if (max_pixclk > 288000*9/10)
5886 else if (max_pixclk > 144000*9/10)
5892 /* Compute the max pixel clock for new configuration. Uses atomic state if
5893 * that's non-NULL, look at current state otherwise. */
5894 static int intel_mode_max_pixclk(struct drm_device *dev,
5895 struct drm_atomic_state *state)
5897 struct intel_crtc *intel_crtc;
5898 struct intel_crtc_state *crtc_state;
5901 for_each_intel_crtc(dev, intel_crtc) {
5902 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5903 if (IS_ERR(crtc_state))
5904 return PTR_ERR(crtc_state);
5906 if (!crtc_state->base.enable)
5909 max_pixclk = max(max_pixclk,
5910 crtc_state->base.adjusted_mode.crtc_clock);
5916 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5918 struct drm_device *dev = state->dev;
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920 int max_pixclk = intel_mode_max_pixclk(dev, state);
5925 to_intel_atomic_state(state)->cdclk =
5926 valleyview_calc_cdclk(dev_priv, max_pixclk);
5931 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5933 struct drm_device *dev = state->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 int max_pixclk = intel_mode_max_pixclk(dev, state);
5940 to_intel_atomic_state(state)->cdclk =
5941 broxton_calc_cdclk(dev_priv, max_pixclk);
5946 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5948 unsigned int credits, default_credits;
5950 if (IS_CHERRYVIEW(dev_priv))
5951 default_credits = PFI_CREDIT(12);
5953 default_credits = PFI_CREDIT(8);
5955 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5956 /* CHV suggested value is 31 or 63 */
5957 if (IS_CHERRYVIEW(dev_priv))
5958 credits = PFI_CREDIT_63;
5960 credits = PFI_CREDIT(15);
5962 credits = default_credits;
5966 * WA - write default credits before re-programming
5967 * FIXME: should we also set the resend bit here?
5969 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5972 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5973 credits | PFI_CREDIT_RESEND);
5976 * FIXME is this guaranteed to clear
5977 * immediately or should we poll for it?
5979 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5982 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5984 struct drm_device *dev = old_state->dev;
5985 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5989 * FIXME: We can end up here with all power domains off, yet
5990 * with a CDCLK frequency other than the minimum. To account
5991 * for this take the PIPE-A power domain, which covers the HW
5992 * blocks needed for the following programming. This can be
5993 * removed once it's guaranteed that we get here either with
5994 * the minimum CDCLK set, or the required power domains
5997 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5999 if (IS_CHERRYVIEW(dev))
6000 cherryview_set_cdclk(dev, req_cdclk);
6002 valleyview_set_cdclk(dev, req_cdclk);
6004 vlv_program_pfi_credits(dev_priv);
6006 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6009 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6011 struct drm_device *dev = crtc->dev;
6012 struct drm_i915_private *dev_priv = to_i915(dev);
6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014 struct intel_encoder *encoder;
6015 int pipe = intel_crtc->pipe;
6018 if (WARN_ON(intel_crtc->active))
6021 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6024 if (IS_CHERRYVIEW(dev))
6025 chv_prepare_pll(intel_crtc, intel_crtc->config);
6027 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6030 if (intel_crtc->config->has_dp_encoder)
6031 intel_dp_set_m_n(intel_crtc, M1_N1);
6033 intel_set_pipe_timings(intel_crtc);
6035 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6038 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6039 I915_WRITE(CHV_CANVAS(pipe), 0);
6042 i9xx_set_pipeconf(intel_crtc);
6044 intel_crtc->active = true;
6046 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6048 for_each_encoder_on_crtc(dev, crtc, encoder)
6049 if (encoder->pre_pll_enable)
6050 encoder->pre_pll_enable(encoder);
6053 if (IS_CHERRYVIEW(dev))
6054 chv_enable_pll(intel_crtc, intel_crtc->config);
6056 vlv_enable_pll(intel_crtc, intel_crtc->config);
6059 for_each_encoder_on_crtc(dev, crtc, encoder)
6060 if (encoder->pre_enable)
6061 encoder->pre_enable(encoder);
6063 i9xx_pfit_enable(intel_crtc);
6065 intel_crtc_load_lut(crtc);
6067 intel_enable_pipe(intel_crtc);
6069 assert_vblank_disabled(crtc);
6070 drm_crtc_vblank_on(crtc);
6072 for_each_encoder_on_crtc(dev, crtc, encoder)
6073 encoder->enable(encoder);
6076 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6078 struct drm_device *dev = crtc->base.dev;
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6081 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6082 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6085 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6087 struct drm_device *dev = crtc->dev;
6088 struct drm_i915_private *dev_priv = to_i915(dev);
6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 struct intel_encoder *encoder;
6091 int pipe = intel_crtc->pipe;
6093 if (WARN_ON(intel_crtc->active))
6096 i9xx_set_pll_dividers(intel_crtc);
6098 if (intel_crtc->config->has_dp_encoder)
6099 intel_dp_set_m_n(intel_crtc, M1_N1);
6101 intel_set_pipe_timings(intel_crtc);
6103 i9xx_set_pipeconf(intel_crtc);
6105 intel_crtc->active = true;
6108 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6110 for_each_encoder_on_crtc(dev, crtc, encoder)
6111 if (encoder->pre_enable)
6112 encoder->pre_enable(encoder);
6114 i9xx_enable_pll(intel_crtc);
6116 i9xx_pfit_enable(intel_crtc);
6118 intel_crtc_load_lut(crtc);
6120 intel_update_watermarks(crtc);
6121 intel_enable_pipe(intel_crtc);
6123 assert_vblank_disabled(crtc);
6124 drm_crtc_vblank_on(crtc);
6126 for_each_encoder_on_crtc(dev, crtc, encoder)
6127 encoder->enable(encoder);
6130 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6132 struct drm_device *dev = crtc->base.dev;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
6135 if (!crtc->config->gmch_pfit.control)
6138 assert_pipe_disabled(dev_priv, crtc->pipe);
6140 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6141 I915_READ(PFIT_CONTROL));
6142 I915_WRITE(PFIT_CONTROL, 0);
6145 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 struct intel_encoder *encoder;
6151 int pipe = intel_crtc->pipe;
6154 * On gen2 planes are double buffered but the pipe isn't, so we must
6155 * wait for planes to fully turn off before disabling the pipe.
6156 * We also need to wait on all gmch platforms because of the
6157 * self-refresh mode constraint explained above.
6159 intel_wait_for_vblank(dev, pipe);
6161 for_each_encoder_on_crtc(dev, crtc, encoder)
6162 encoder->disable(encoder);
6164 drm_crtc_vblank_off(crtc);
6165 assert_vblank_disabled(crtc);
6167 intel_disable_pipe(intel_crtc);
6169 i9xx_pfit_disable(intel_crtc);
6171 for_each_encoder_on_crtc(dev, crtc, encoder)
6172 if (encoder->post_disable)
6173 encoder->post_disable(encoder);
6175 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6176 if (IS_CHERRYVIEW(dev))
6177 chv_disable_pll(dev_priv, pipe);
6178 else if (IS_VALLEYVIEW(dev))
6179 vlv_disable_pll(dev_priv, pipe);
6181 i9xx_disable_pll(intel_crtc);
6185 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6187 intel_crtc->active = false;
6188 intel_update_watermarks(crtc);
6191 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6194 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6195 enum intel_display_power_domain domain;
6196 unsigned long domains;
6198 if (!intel_crtc->active)
6201 if (to_intel_plane_state(crtc->primary->state)->visible) {
6202 intel_crtc_wait_for_pending_flips(crtc);
6203 intel_pre_disable_primary(crtc);
6206 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6207 dev_priv->display.crtc_disable(crtc);
6208 intel_disable_shared_dpll(intel_crtc);
6210 domains = intel_crtc->enabled_power_domains;
6211 for_each_power_domain(domain, domains)
6212 intel_display_power_put(dev_priv, domain);
6213 intel_crtc->enabled_power_domains = 0;
6217 * turn all crtc's off, but do not adjust state
6218 * This has to be paired with a call to intel_modeset_setup_hw_state.
6220 int intel_display_suspend(struct drm_device *dev)
6222 struct drm_mode_config *config = &dev->mode_config;
6223 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6224 struct drm_atomic_state *state;
6225 struct drm_crtc *crtc;
6226 unsigned crtc_mask = 0;
6232 lockdep_assert_held(&ctx->ww_ctx);
6233 state = drm_atomic_state_alloc(dev);
6234 if (WARN_ON(!state))
6237 state->acquire_ctx = ctx;
6238 state->allow_modeset = true;
6240 for_each_crtc(dev, crtc) {
6241 struct drm_crtc_state *crtc_state =
6242 drm_atomic_get_crtc_state(state, crtc);
6244 ret = PTR_ERR_OR_ZERO(crtc_state);
6248 if (!crtc_state->active)
6251 crtc_state->active = false;
6252 crtc_mask |= 1 << drm_crtc_index(crtc);
6256 ret = drm_atomic_commit(state);
6259 for_each_crtc(dev, crtc)
6260 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6261 crtc->state->active = true;
6269 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6270 drm_atomic_state_free(state);
6274 /* Master function to enable/disable CRTC and corresponding power wells */
6275 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6277 struct drm_device *dev = crtc->dev;
6278 struct drm_mode_config *config = &dev->mode_config;
6279 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281 struct intel_crtc_state *pipe_config;
6282 struct drm_atomic_state *state;
6285 if (enable == intel_crtc->active)
6288 if (enable && !crtc->state->enable)
6291 /* this function should be called with drm_modeset_lock_all for now */
6294 lockdep_assert_held(&ctx->ww_ctx);
6296 state = drm_atomic_state_alloc(dev);
6297 if (WARN_ON(!state))
6300 state->acquire_ctx = ctx;
6301 state->allow_modeset = true;
6303 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6304 if (IS_ERR(pipe_config)) {
6305 ret = PTR_ERR(pipe_config);
6308 pipe_config->base.active = enable;
6310 ret = drm_atomic_commit(state);
6315 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6316 drm_atomic_state_free(state);
6321 * Sets the power management mode of the pipe and plane.
6323 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6325 struct drm_device *dev = crtc->dev;
6326 struct intel_encoder *intel_encoder;
6327 bool enable = false;
6329 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6330 enable |= intel_encoder->connectors_active;
6332 intel_crtc_control(crtc, enable);
6335 void intel_encoder_destroy(struct drm_encoder *encoder)
6337 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6339 drm_encoder_cleanup(encoder);
6340 kfree(intel_encoder);
6343 /* Simple dpms helper for encoders with just one connector, no cloning and only
6344 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6345 * state of the entire output pipe. */
6346 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6348 if (mode == DRM_MODE_DPMS_ON) {
6349 encoder->connectors_active = true;
6351 intel_crtc_update_dpms(encoder->base.crtc);
6353 encoder->connectors_active = false;
6355 intel_crtc_update_dpms(encoder->base.crtc);
6359 /* Cross check the actual hw state with our own modeset state tracking (and it's
6360 * internal consistency). */
6361 static void intel_connector_check_state(struct intel_connector *connector)
6363 if (connector->get_hw_state(connector)) {
6364 struct intel_encoder *encoder = connector->encoder;
6365 struct drm_crtc *crtc;
6366 bool encoder_enabled;
6369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6370 connector->base.base.id,
6371 connector->base.name);
6373 /* there is no real hw state for MST connectors */
6374 if (connector->mst_port)
6377 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6378 "wrong connector dpms state\n");
6379 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6380 "active connector not linked to encoder\n");
6383 I915_STATE_WARN(!encoder->connectors_active,
6384 "encoder->connectors_active not set\n");
6386 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6387 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6388 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6391 crtc = encoder->base.crtc;
6393 I915_STATE_WARN(!crtc->state->enable,
6394 "crtc not enabled\n");
6395 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6396 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6397 "encoder active on the wrong pipe\n");
6402 int intel_connector_init(struct intel_connector *connector)
6404 struct drm_connector_state *connector_state;
6406 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6407 if (!connector_state)
6410 connector->base.state = connector_state;
6414 struct intel_connector *intel_connector_alloc(void)
6416 struct intel_connector *connector;
6418 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6422 if (intel_connector_init(connector) < 0) {
6430 /* Even simpler default implementation, if there's really no special case to
6432 void intel_connector_dpms(struct drm_connector *connector, int mode)
6434 /* All the simple cases only support two dpms states. */
6435 if (mode != DRM_MODE_DPMS_ON)
6436 mode = DRM_MODE_DPMS_OFF;
6438 if (mode == connector->dpms)
6441 connector->dpms = mode;
6443 /* Only need to change hw state when actually enabled */
6444 if (connector->encoder)
6445 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6447 intel_modeset_check_state(connector->dev);
6450 /* Simple connector->get_hw_state implementation for encoders that support only
6451 * one connector and no cloning and hence the encoder state determines the state
6452 * of the connector. */
6453 bool intel_connector_get_hw_state(struct intel_connector *connector)
6456 struct intel_encoder *encoder = connector->encoder;
6458 return encoder->get_hw_state(encoder, &pipe);
6461 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6463 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6464 return crtc_state->fdi_lanes;
6469 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6470 struct intel_crtc_state *pipe_config)
6472 struct drm_atomic_state *state = pipe_config->base.state;
6473 struct intel_crtc *other_crtc;
6474 struct intel_crtc_state *other_crtc_state;
6476 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6477 pipe_name(pipe), pipe_config->fdi_lanes);
6478 if (pipe_config->fdi_lanes > 4) {
6479 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6480 pipe_name(pipe), pipe_config->fdi_lanes);
6484 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6485 if (pipe_config->fdi_lanes > 2) {
6486 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6487 pipe_config->fdi_lanes);
6494 if (INTEL_INFO(dev)->num_pipes == 2)
6497 /* Ivybridge 3 pipe is really complicated */
6502 if (pipe_config->fdi_lanes <= 2)
6505 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6507 intel_atomic_get_crtc_state(state, other_crtc);
6508 if (IS_ERR(other_crtc_state))
6509 return PTR_ERR(other_crtc_state);
6511 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6512 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6513 pipe_name(pipe), pipe_config->fdi_lanes);
6518 if (pipe_config->fdi_lanes > 2) {
6519 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6520 pipe_name(pipe), pipe_config->fdi_lanes);
6524 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6526 intel_atomic_get_crtc_state(state, other_crtc);
6527 if (IS_ERR(other_crtc_state))
6528 return PTR_ERR(other_crtc_state);
6530 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6531 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6541 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6542 struct intel_crtc_state *pipe_config)
6544 struct drm_device *dev = intel_crtc->base.dev;
6545 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6546 int lane, link_bw, fdi_dotclock, ret;
6547 bool needs_recompute = false;
6550 /* FDI is a binary signal running at ~2.7GHz, encoding
6551 * each output octet as 10 bits. The actual frequency
6552 * is stored as a divider into a 100MHz clock, and the
6553 * mode pixel clock is stored in units of 1KHz.
6554 * Hence the bw of each lane in terms of the mode signal
6557 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6559 fdi_dotclock = adjusted_mode->crtc_clock;
6561 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6562 pipe_config->pipe_bpp);
6564 pipe_config->fdi_lanes = lane;
6566 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6567 link_bw, &pipe_config->fdi_m_n);
6569 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6570 intel_crtc->pipe, pipe_config);
6571 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6572 pipe_config->pipe_bpp -= 2*3;
6573 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6574 pipe_config->pipe_bpp);
6575 needs_recompute = true;
6576 pipe_config->bw_constrained = true;
6581 if (needs_recompute)
6587 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6588 struct intel_crtc_state *pipe_config)
6590 if (pipe_config->pipe_bpp > 24)
6593 /* HSW can handle pixel rate up to cdclk? */
6594 if (IS_HASWELL(dev_priv->dev))
6598 * We compare against max which means we must take
6599 * the increased cdclk requirement into account when
6600 * calculating the new cdclk.
6602 * Should measure whether using a lower cdclk w/o IPS
6604 return ilk_pipe_pixel_rate(pipe_config) <=
6605 dev_priv->max_cdclk_freq * 95 / 100;
6608 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6609 struct intel_crtc_state *pipe_config)
6611 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6614 pipe_config->ips_enabled = i915.enable_ips &&
6615 hsw_crtc_supports_ips(crtc) &&
6616 pipe_config_supports_ips(dev_priv, pipe_config);
6619 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6620 struct intel_crtc_state *pipe_config)
6622 struct drm_device *dev = crtc->base.dev;
6623 struct drm_i915_private *dev_priv = dev->dev_private;
6624 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6626 /* FIXME should check pixel clock limits on all platforms */
6627 if (INTEL_INFO(dev)->gen < 4) {
6628 int clock_limit = dev_priv->max_cdclk_freq;
6631 * Enable pixel doubling when the dot clock
6632 * is > 90% of the (display) core speed.
6634 * GDG double wide on either pipe,
6635 * otherwise pipe A only.
6637 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6638 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6640 pipe_config->double_wide = true;
6643 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6648 * Pipe horizontal size must be even in:
6650 * - LVDS dual channel mode
6651 * - Double wide pipe
6653 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6654 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6655 pipe_config->pipe_src_w &= ~1;
6657 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6658 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6660 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6661 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6665 hsw_compute_ips_config(crtc, pipe_config);
6667 if (pipe_config->has_pch_encoder)
6668 return ironlake_fdi_compute_config(crtc, pipe_config);
6673 static int skylake_get_display_clock_speed(struct drm_device *dev)
6675 struct drm_i915_private *dev_priv = to_i915(dev);
6676 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6677 uint32_t cdctl = I915_READ(CDCLK_CTL);
6680 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6681 return 24000; /* 24MHz is the cd freq with NSSC ref */
6683 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6686 linkrate = (I915_READ(DPLL_CTRL1) &
6687 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6689 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6690 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6692 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6693 case CDCLK_FREQ_450_432:
6695 case CDCLK_FREQ_337_308:
6697 case CDCLK_FREQ_675_617:
6700 WARN(1, "Unknown cd freq selection\n");
6704 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6705 case CDCLK_FREQ_450_432:
6707 case CDCLK_FREQ_337_308:
6709 case CDCLK_FREQ_675_617:
6712 WARN(1, "Unknown cd freq selection\n");
6716 /* error case, do as if DPLL0 isn't enabled */
6720 static int broxton_get_display_clock_speed(struct drm_device *dev)
6722 struct drm_i915_private *dev_priv = to_i915(dev);
6723 uint32_t cdctl = I915_READ(CDCLK_CTL);
6724 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6725 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6728 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6731 cdclk = 19200 * pll_ratio / 2;
6733 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6734 case BXT_CDCLK_CD2X_DIV_SEL_1:
6735 return cdclk; /* 576MHz or 624MHz */
6736 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6737 return cdclk * 2 / 3; /* 384MHz */
6738 case BXT_CDCLK_CD2X_DIV_SEL_2:
6739 return cdclk / 2; /* 288MHz */
6740 case BXT_CDCLK_CD2X_DIV_SEL_4:
6741 return cdclk / 4; /* 144MHz */
6744 /* error case, do as if DE PLL isn't enabled */
6748 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 uint32_t lcpll = I915_READ(LCPLL_CTL);
6752 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6754 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6756 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6758 else if (freq == LCPLL_CLK_FREQ_450)
6760 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6762 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6768 static int haswell_get_display_clock_speed(struct drm_device *dev)
6770 struct drm_i915_private *dev_priv = dev->dev_private;
6771 uint32_t lcpll = I915_READ(LCPLL_CTL);
6772 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6774 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6776 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6778 else if (freq == LCPLL_CLK_FREQ_450)
6780 else if (IS_HSW_ULT(dev))
6786 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6788 struct drm_i915_private *dev_priv = dev->dev_private;
6792 if (dev_priv->hpll_freq == 0)
6793 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6795 mutex_lock(&dev_priv->sb_lock);
6796 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6797 mutex_unlock(&dev_priv->sb_lock);
6799 divider = val & DISPLAY_FREQUENCY_VALUES;
6801 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6802 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6803 "cdclk change in progress\n");
6805 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6808 static int ilk_get_display_clock_speed(struct drm_device *dev)
6813 static int i945_get_display_clock_speed(struct drm_device *dev)
6818 static int i915_get_display_clock_speed(struct drm_device *dev)
6823 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6828 static int pnv_get_display_clock_speed(struct drm_device *dev)
6832 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6834 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6835 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6837 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6839 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6841 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6844 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6845 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6847 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6852 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6856 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6858 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6861 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6862 case GC_DISPLAY_CLOCK_333_MHZ:
6865 case GC_DISPLAY_CLOCK_190_200_MHZ:
6871 static int i865_get_display_clock_speed(struct drm_device *dev)
6876 static int i85x_get_display_clock_speed(struct drm_device *dev)
6881 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6882 * encoding is different :(
6883 * FIXME is this the right way to detect 852GM/852GMV?
6885 if (dev->pdev->revision == 0x1)
6888 pci_bus_read_config_word(dev->pdev->bus,
6889 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6891 /* Assume that the hardware is in the high speed state. This
6892 * should be the default.
6894 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6895 case GC_CLOCK_133_200:
6896 case GC_CLOCK_133_200_2:
6897 case GC_CLOCK_100_200:
6899 case GC_CLOCK_166_250:
6901 case GC_CLOCK_100_133:
6903 case GC_CLOCK_133_266:
6904 case GC_CLOCK_133_266_2:
6905 case GC_CLOCK_166_266:
6909 /* Shouldn't happen */
6913 static int i830_get_display_clock_speed(struct drm_device *dev)
6918 static unsigned int intel_hpll_vco(struct drm_device *dev)
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 static const unsigned int blb_vco[8] = {
6928 static const unsigned int pnv_vco[8] = {
6935 static const unsigned int cl_vco[8] = {
6944 static const unsigned int elk_vco[8] = {
6950 static const unsigned int ctg_vco[8] = {
6958 const unsigned int *vco_table;
6962 /* FIXME other chipsets? */
6964 vco_table = ctg_vco;
6965 else if (IS_G4X(dev))
6966 vco_table = elk_vco;
6967 else if (IS_CRESTLINE(dev))
6969 else if (IS_PINEVIEW(dev))
6970 vco_table = pnv_vco;
6971 else if (IS_G33(dev))
6972 vco_table = blb_vco;
6976 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6978 vco = vco_table[tmp & 0x7];
6980 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6982 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6987 static int gm45_get_display_clock_speed(struct drm_device *dev)
6989 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6992 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6994 cdclk_sel = (tmp >> 12) & 0x1;
7000 return cdclk_sel ? 333333 : 222222;
7002 return cdclk_sel ? 320000 : 228571;
7004 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7009 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7011 static const uint8_t div_3200[] = { 16, 10, 8 };
7012 static const uint8_t div_4000[] = { 20, 12, 10 };
7013 static const uint8_t div_5333[] = { 24, 16, 14 };
7014 const uint8_t *div_table;
7015 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7018 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7020 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7022 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7027 div_table = div_3200;
7030 div_table = div_4000;
7033 div_table = div_5333;
7039 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7042 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7046 static int g33_get_display_clock_speed(struct drm_device *dev)
7048 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7049 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7050 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7051 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7052 const uint8_t *div_table;
7053 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7056 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7058 cdclk_sel = (tmp >> 4) & 0x7;
7060 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7065 div_table = div_3200;
7068 div_table = div_4000;
7071 div_table = div_4800;
7074 div_table = div_5333;
7080 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7083 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7088 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7090 while (*num > DATA_LINK_M_N_MASK ||
7091 *den > DATA_LINK_M_N_MASK) {
7097 static void compute_m_n(unsigned int m, unsigned int n,
7098 uint32_t *ret_m, uint32_t *ret_n)
7100 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7101 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7102 intel_reduce_m_n_ratio(ret_m, ret_n);
7106 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7107 int pixel_clock, int link_clock,
7108 struct intel_link_m_n *m_n)
7112 compute_m_n(bits_per_pixel * pixel_clock,
7113 link_clock * nlanes * 8,
7114 &m_n->gmch_m, &m_n->gmch_n);
7116 compute_m_n(pixel_clock, link_clock,
7117 &m_n->link_m, &m_n->link_n);
7120 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7122 if (i915.panel_use_ssc >= 0)
7123 return i915.panel_use_ssc != 0;
7124 return dev_priv->vbt.lvds_use_ssc
7125 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7128 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7131 struct drm_device *dev = crtc_state->base.crtc->dev;
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7135 WARN_ON(!crtc_state->base.state);
7137 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7139 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7140 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7141 refclk = dev_priv->vbt.lvds_ssc_freq;
7142 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7143 } else if (!IS_GEN2(dev)) {
7152 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7154 return (1 << dpll->n) << 16 | dpll->m2;
7157 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7159 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7162 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7163 struct intel_crtc_state *crtc_state,
7164 intel_clock_t *reduced_clock)
7166 struct drm_device *dev = crtc->base.dev;
7169 if (IS_PINEVIEW(dev)) {
7170 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7172 fp2 = pnv_dpll_compute_fp(reduced_clock);
7174 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7176 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7179 crtc_state->dpll_hw_state.fp0 = fp;
7181 crtc->lowfreq_avail = false;
7182 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7184 crtc_state->dpll_hw_state.fp1 = fp2;
7185 crtc->lowfreq_avail = true;
7187 crtc_state->dpll_hw_state.fp1 = fp;
7191 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7197 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7198 * and set it to a reasonable value instead.
7200 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7201 reg_val &= 0xffffff00;
7202 reg_val |= 0x00000030;
7203 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7205 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7206 reg_val &= 0x8cffffff;
7207 reg_val = 0x8c000000;
7208 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7210 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7211 reg_val &= 0xffffff00;
7212 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7214 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7215 reg_val &= 0x00ffffff;
7216 reg_val |= 0xb0000000;
7217 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7220 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7221 struct intel_link_m_n *m_n)
7223 struct drm_device *dev = crtc->base.dev;
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 int pipe = crtc->pipe;
7227 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7228 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7229 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7230 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7233 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7234 struct intel_link_m_n *m_n,
7235 struct intel_link_m_n *m2_n2)
7237 struct drm_device *dev = crtc->base.dev;
7238 struct drm_i915_private *dev_priv = dev->dev_private;
7239 int pipe = crtc->pipe;
7240 enum transcoder transcoder = crtc->config->cpu_transcoder;
7242 if (INTEL_INFO(dev)->gen >= 5) {
7243 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7244 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7245 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7246 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7247 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7248 * for gen < 8) and if DRRS is supported (to make sure the
7249 * registers are not unnecessarily accessed).
7251 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7252 crtc->config->has_drrs) {
7253 I915_WRITE(PIPE_DATA_M2(transcoder),
7254 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7255 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7256 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7257 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7260 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7261 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7262 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7263 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7267 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7269 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7272 dp_m_n = &crtc->config->dp_m_n;
7273 dp_m2_n2 = &crtc->config->dp_m2_n2;
7274 } else if (m_n == M2_N2) {
7277 * M2_N2 registers are not supported. Hence m2_n2 divider value
7278 * needs to be programmed into M1_N1.
7280 dp_m_n = &crtc->config->dp_m2_n2;
7282 DRM_ERROR("Unsupported divider value\n");
7286 if (crtc->config->has_pch_encoder)
7287 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7289 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7292 static void vlv_compute_dpll(struct intel_crtc *crtc,
7293 struct intel_crtc_state *pipe_config)
7298 * Enable DPIO clock input. We should never disable the reference
7299 * clock for pipe B, since VGA hotplug / manual detection depends
7302 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7303 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7304 /* We should never disable this, set it here for state tracking */
7305 if (crtc->pipe == PIPE_B)
7306 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7307 dpll |= DPLL_VCO_ENABLE;
7308 pipe_config->dpll_hw_state.dpll = dpll;
7310 dpll_md = (pipe_config->pixel_multiplier - 1)
7311 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7312 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7315 static void vlv_prepare_pll(struct intel_crtc *crtc,
7316 const struct intel_crtc_state *pipe_config)
7318 struct drm_device *dev = crtc->base.dev;
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7320 int pipe = crtc->pipe;
7322 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7323 u32 coreclk, reg_val;
7325 mutex_lock(&dev_priv->sb_lock);
7327 bestn = pipe_config->dpll.n;
7328 bestm1 = pipe_config->dpll.m1;
7329 bestm2 = pipe_config->dpll.m2;
7330 bestp1 = pipe_config->dpll.p1;
7331 bestp2 = pipe_config->dpll.p2;
7333 /* See eDP HDMI DPIO driver vbios notes doc */
7335 /* PLL B needs special handling */
7337 vlv_pllb_recal_opamp(dev_priv, pipe);
7339 /* Set up Tx target for periodic Rcomp update */
7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7342 /* Disable target IRef on PLL */
7343 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7344 reg_val &= 0x00ffffff;
7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7347 /* Disable fast lock */
7348 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7350 /* Set idtafcrecal before PLL is enabled */
7351 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7352 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7353 mdiv |= ((bestn << DPIO_N_SHIFT));
7354 mdiv |= (1 << DPIO_K_SHIFT);
7357 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7358 * but we don't support that).
7359 * Note: don't use the DAC post divider as it seems unstable.
7361 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7362 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7364 mdiv |= DPIO_ENABLE_CALIBRATION;
7365 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7367 /* Set HBR and RBR LPF coefficients */
7368 if (pipe_config->port_clock == 162000 ||
7369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7370 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7371 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7374 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7377 if (pipe_config->has_dp_encoder) {
7378 /* Use SSC source */
7380 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7383 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7385 } else { /* HDMI or VGA */
7386 /* Use bend source */
7388 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7395 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7396 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7397 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7398 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7399 coreclk |= 0x01000000;
7400 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7403 mutex_unlock(&dev_priv->sb_lock);
7406 static void chv_compute_dpll(struct intel_crtc *crtc,
7407 struct intel_crtc_state *pipe_config)
7409 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7410 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7412 if (crtc->pipe != PIPE_A)
7413 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7415 pipe_config->dpll_hw_state.dpll_md =
7416 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7419 static void chv_prepare_pll(struct intel_crtc *crtc,
7420 const struct intel_crtc_state *pipe_config)
7422 struct drm_device *dev = crtc->base.dev;
7423 struct drm_i915_private *dev_priv = dev->dev_private;
7424 int pipe = crtc->pipe;
7425 int dpll_reg = DPLL(crtc->pipe);
7426 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7427 u32 loopfilter, tribuf_calcntr;
7428 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7432 bestn = pipe_config->dpll.n;
7433 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7434 bestm1 = pipe_config->dpll.m1;
7435 bestm2 = pipe_config->dpll.m2 >> 22;
7436 bestp1 = pipe_config->dpll.p1;
7437 bestp2 = pipe_config->dpll.p2;
7438 vco = pipe_config->dpll.vco;
7443 * Enable Refclk and SSC
7445 I915_WRITE(dpll_reg,
7446 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7448 mutex_lock(&dev_priv->sb_lock);
7450 /* p1 and p2 divider */
7451 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7452 5 << DPIO_CHV_S1_DIV_SHIFT |
7453 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7454 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7455 1 << DPIO_CHV_K_DIV_SHIFT);
7457 /* Feedback post-divider - m2 */
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7460 /* Feedback refclk divider - n and m1 */
7461 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7462 DPIO_CHV_M1_DIV_BY_2 |
7463 1 << DPIO_CHV_N_DIV_SHIFT);
7465 /* M2 fraction division */
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7469 /* M2 fraction division enable */
7470 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7471 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7472 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7474 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7475 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7477 /* Program digital lock detect threshold */
7478 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7479 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7480 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7481 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7483 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7487 if (vco == 5400000) {
7488 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7489 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7490 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7491 tribuf_calcntr = 0x9;
7492 } else if (vco <= 6200000) {
7493 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7494 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7495 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7496 tribuf_calcntr = 0x9;
7497 } else if (vco <= 6480000) {
7498 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7499 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7500 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7501 tribuf_calcntr = 0x8;
7503 /* Not supported. Apply the same limits as in the max case */
7504 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7505 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7506 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7509 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7511 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7512 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7513 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7514 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7517 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7518 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7521 mutex_unlock(&dev_priv->sb_lock);
7525 * vlv_force_pll_on - forcibly enable just the PLL
7526 * @dev_priv: i915 private structure
7527 * @pipe: pipe PLL to enable
7528 * @dpll: PLL configuration
7530 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7531 * in cases where we need the PLL enabled even when @pipe is not going to
7534 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7535 const struct dpll *dpll)
7537 struct intel_crtc *crtc =
7538 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7539 struct intel_crtc_state pipe_config = {
7540 .base.crtc = &crtc->base,
7541 .pixel_multiplier = 1,
7545 if (IS_CHERRYVIEW(dev)) {
7546 chv_compute_dpll(crtc, &pipe_config);
7547 chv_prepare_pll(crtc, &pipe_config);
7548 chv_enable_pll(crtc, &pipe_config);
7550 vlv_compute_dpll(crtc, &pipe_config);
7551 vlv_prepare_pll(crtc, &pipe_config);
7552 vlv_enable_pll(crtc, &pipe_config);
7557 * vlv_force_pll_off - forcibly disable just the PLL
7558 * @dev_priv: i915 private structure
7559 * @pipe: pipe PLL to disable
7561 * Disable the PLL for @pipe. To be used in cases where we need
7562 * the PLL enabled even when @pipe is not going to be enabled.
7564 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7566 if (IS_CHERRYVIEW(dev))
7567 chv_disable_pll(to_i915(dev), pipe);
7569 vlv_disable_pll(to_i915(dev), pipe);
7572 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7573 struct intel_crtc_state *crtc_state,
7574 intel_clock_t *reduced_clock,
7577 struct drm_device *dev = crtc->base.dev;
7578 struct drm_i915_private *dev_priv = dev->dev_private;
7581 struct dpll *clock = &crtc_state->dpll;
7583 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7585 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7586 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7588 dpll = DPLL_VGA_MODE_DIS;
7590 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7591 dpll |= DPLLB_MODE_LVDS;
7593 dpll |= DPLLB_MODE_DAC_SERIAL;
7595 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7596 dpll |= (crtc_state->pixel_multiplier - 1)
7597 << SDVO_MULTIPLIER_SHIFT_HIRES;
7601 dpll |= DPLL_SDVO_HIGH_SPEED;
7603 if (crtc_state->has_dp_encoder)
7604 dpll |= DPLL_SDVO_HIGH_SPEED;
7606 /* compute bitmask from p1 value */
7607 if (IS_PINEVIEW(dev))
7608 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611 if (IS_G4X(dev) && reduced_clock)
7612 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7614 switch (clock->p2) {
7616 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7619 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7622 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7625 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7628 if (INTEL_INFO(dev)->gen >= 4)
7629 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7631 if (crtc_state->sdvo_tv_clock)
7632 dpll |= PLL_REF_INPUT_TVCLKINBC;
7633 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7634 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7635 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7637 dpll |= PLL_REF_INPUT_DREFCLK;
7639 dpll |= DPLL_VCO_ENABLE;
7640 crtc_state->dpll_hw_state.dpll = dpll;
7642 if (INTEL_INFO(dev)->gen >= 4) {
7643 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7644 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7645 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7649 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7650 struct intel_crtc_state *crtc_state,
7651 intel_clock_t *reduced_clock,
7654 struct drm_device *dev = crtc->base.dev;
7655 struct drm_i915_private *dev_priv = dev->dev_private;
7657 struct dpll *clock = &crtc_state->dpll;
7659 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7661 dpll = DPLL_VGA_MODE_DIS;
7663 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7664 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7667 dpll |= PLL_P1_DIVIDE_BY_TWO;
7669 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7671 dpll |= PLL_P2_DIVIDE_BY_4;
7674 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7675 dpll |= DPLL_DVO_2X_MODE;
7677 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7678 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7679 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7681 dpll |= PLL_REF_INPUT_DREFCLK;
7683 dpll |= DPLL_VCO_ENABLE;
7684 crtc_state->dpll_hw_state.dpll = dpll;
7687 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7689 struct drm_device *dev = intel_crtc->base.dev;
7690 struct drm_i915_private *dev_priv = dev->dev_private;
7691 enum pipe pipe = intel_crtc->pipe;
7692 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7693 struct drm_display_mode *adjusted_mode =
7694 &intel_crtc->config->base.adjusted_mode;
7695 uint32_t crtc_vtotal, crtc_vblank_end;
7698 /* We need to be careful not to changed the adjusted mode, for otherwise
7699 * the hw state checker will get angry at the mismatch. */
7700 crtc_vtotal = adjusted_mode->crtc_vtotal;
7701 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7703 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7704 /* the chip adds 2 halflines automatically */
7706 crtc_vblank_end -= 1;
7708 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7709 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7711 vsyncshift = adjusted_mode->crtc_hsync_start -
7712 adjusted_mode->crtc_htotal / 2;
7714 vsyncshift += adjusted_mode->crtc_htotal;
7717 if (INTEL_INFO(dev)->gen > 3)
7718 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7720 I915_WRITE(HTOTAL(cpu_transcoder),
7721 (adjusted_mode->crtc_hdisplay - 1) |
7722 ((adjusted_mode->crtc_htotal - 1) << 16));
7723 I915_WRITE(HBLANK(cpu_transcoder),
7724 (adjusted_mode->crtc_hblank_start - 1) |
7725 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7726 I915_WRITE(HSYNC(cpu_transcoder),
7727 (adjusted_mode->crtc_hsync_start - 1) |
7728 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7730 I915_WRITE(VTOTAL(cpu_transcoder),
7731 (adjusted_mode->crtc_vdisplay - 1) |
7732 ((crtc_vtotal - 1) << 16));
7733 I915_WRITE(VBLANK(cpu_transcoder),
7734 (adjusted_mode->crtc_vblank_start - 1) |
7735 ((crtc_vblank_end - 1) << 16));
7736 I915_WRITE(VSYNC(cpu_transcoder),
7737 (adjusted_mode->crtc_vsync_start - 1) |
7738 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7740 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7741 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7742 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7744 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7745 (pipe == PIPE_B || pipe == PIPE_C))
7746 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7748 /* pipesrc controls the size that is scaled from, which should
7749 * always be the user's requested size.
7751 I915_WRITE(PIPESRC(pipe),
7752 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7753 (intel_crtc->config->pipe_src_h - 1));
7756 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7757 struct intel_crtc_state *pipe_config)
7759 struct drm_device *dev = crtc->base.dev;
7760 struct drm_i915_private *dev_priv = dev->dev_private;
7761 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7764 tmp = I915_READ(HTOTAL(cpu_transcoder));
7765 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7766 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7767 tmp = I915_READ(HBLANK(cpu_transcoder));
7768 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7769 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7770 tmp = I915_READ(HSYNC(cpu_transcoder));
7771 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7772 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7774 tmp = I915_READ(VTOTAL(cpu_transcoder));
7775 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7776 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7777 tmp = I915_READ(VBLANK(cpu_transcoder));
7778 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7779 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7780 tmp = I915_READ(VSYNC(cpu_transcoder));
7781 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7782 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7784 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7785 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7786 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7787 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7790 tmp = I915_READ(PIPESRC(crtc->pipe));
7791 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7792 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7794 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7795 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7798 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7799 struct intel_crtc_state *pipe_config)
7801 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7802 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7803 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7804 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7806 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7807 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7808 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7809 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7811 mode->flags = pipe_config->base.adjusted_mode.flags;
7812 mode->type = DRM_MODE_TYPE_DRIVER;
7814 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7815 mode->flags |= pipe_config->base.adjusted_mode.flags;
7817 mode->hsync = drm_mode_hsync(mode);
7818 mode->vrefresh = drm_mode_vrefresh(mode);
7819 drm_mode_set_name(mode);
7822 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7824 struct drm_device *dev = intel_crtc->base.dev;
7825 struct drm_i915_private *dev_priv = dev->dev_private;
7830 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7831 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7832 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7834 if (intel_crtc->config->double_wide)
7835 pipeconf |= PIPECONF_DOUBLE_WIDE;
7837 /* only g4x and later have fancy bpc/dither controls */
7838 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7839 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7840 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7841 pipeconf |= PIPECONF_DITHER_EN |
7842 PIPECONF_DITHER_TYPE_SP;
7844 switch (intel_crtc->config->pipe_bpp) {
7846 pipeconf |= PIPECONF_6BPC;
7849 pipeconf |= PIPECONF_8BPC;
7852 pipeconf |= PIPECONF_10BPC;
7855 /* Case prevented by intel_choose_pipe_bpp_dither. */
7860 if (HAS_PIPE_CXSR(dev)) {
7861 if (intel_crtc->lowfreq_avail) {
7862 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7863 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7865 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7869 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7870 if (INTEL_INFO(dev)->gen < 4 ||
7871 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7872 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7874 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7876 pipeconf |= PIPECONF_PROGRESSIVE;
7878 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7879 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7881 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7882 POSTING_READ(PIPECONF(intel_crtc->pipe));
7885 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7886 struct intel_crtc_state *crtc_state)
7888 struct drm_device *dev = crtc->base.dev;
7889 struct drm_i915_private *dev_priv = dev->dev_private;
7890 int refclk, num_connectors = 0;
7891 intel_clock_t clock;
7893 bool is_dsi = false;
7894 struct intel_encoder *encoder;
7895 const intel_limit_t *limit;
7896 struct drm_atomic_state *state = crtc_state->base.state;
7897 struct drm_connector *connector;
7898 struct drm_connector_state *connector_state;
7901 memset(&crtc_state->dpll_hw_state, 0,
7902 sizeof(crtc_state->dpll_hw_state));
7904 for_each_connector_in_state(state, connector, connector_state, i) {
7905 if (connector_state->crtc != &crtc->base)
7908 encoder = to_intel_encoder(connector_state->best_encoder);
7910 switch (encoder->type) {
7911 case INTEL_OUTPUT_DSI:
7924 if (!crtc_state->clock_set) {
7925 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7928 * Returns a set of divisors for the desired target clock with
7929 * the given refclk, or FALSE. The returned values represent
7930 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7933 limit = intel_limit(crtc_state, refclk);
7934 ok = dev_priv->display.find_dpll(limit, crtc_state,
7935 crtc_state->port_clock,
7936 refclk, NULL, &clock);
7938 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7942 /* Compat-code for transition, will disappear. */
7943 crtc_state->dpll.n = clock.n;
7944 crtc_state->dpll.m1 = clock.m1;
7945 crtc_state->dpll.m2 = clock.m2;
7946 crtc_state->dpll.p1 = clock.p1;
7947 crtc_state->dpll.p2 = clock.p2;
7951 i8xx_compute_dpll(crtc, crtc_state, NULL,
7953 } else if (IS_CHERRYVIEW(dev)) {
7954 chv_compute_dpll(crtc, crtc_state);
7955 } else if (IS_VALLEYVIEW(dev)) {
7956 vlv_compute_dpll(crtc, crtc_state);
7958 i9xx_compute_dpll(crtc, crtc_state, NULL,
7965 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7966 struct intel_crtc_state *pipe_config)
7968 struct drm_device *dev = crtc->base.dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7972 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7975 tmp = I915_READ(PFIT_CONTROL);
7976 if (!(tmp & PFIT_ENABLE))
7979 /* Check whether the pfit is attached to our pipe. */
7980 if (INTEL_INFO(dev)->gen < 4) {
7981 if (crtc->pipe != PIPE_B)
7984 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7988 pipe_config->gmch_pfit.control = tmp;
7989 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7990 if (INTEL_INFO(dev)->gen < 5)
7991 pipe_config->gmch_pfit.lvds_border_bits =
7992 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7995 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7996 struct intel_crtc_state *pipe_config)
7998 struct drm_device *dev = crtc->base.dev;
7999 struct drm_i915_private *dev_priv = dev->dev_private;
8000 int pipe = pipe_config->cpu_transcoder;
8001 intel_clock_t clock;
8003 int refclk = 100000;
8005 /* In case of MIPI DPLL will not even be used */
8006 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8009 mutex_lock(&dev_priv->sb_lock);
8010 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8011 mutex_unlock(&dev_priv->sb_lock);
8013 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8014 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8015 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8016 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8017 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8019 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8023 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8024 struct intel_initial_plane_config *plane_config)
8026 struct drm_device *dev = crtc->base.dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028 u32 val, base, offset;
8029 int pipe = crtc->pipe, plane = crtc->plane;
8030 int fourcc, pixel_format;
8031 unsigned int aligned_height;
8032 struct drm_framebuffer *fb;
8033 struct intel_framebuffer *intel_fb;
8035 val = I915_READ(DSPCNTR(plane));
8036 if (!(val & DISPLAY_PLANE_ENABLE))
8039 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8041 DRM_DEBUG_KMS("failed to alloc fb\n");
8045 fb = &intel_fb->base;
8047 if (INTEL_INFO(dev)->gen >= 4) {
8048 if (val & DISPPLANE_TILED) {
8049 plane_config->tiling = I915_TILING_X;
8050 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8054 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8055 fourcc = i9xx_format_to_fourcc(pixel_format);
8056 fb->pixel_format = fourcc;
8057 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8059 if (INTEL_INFO(dev)->gen >= 4) {
8060 if (plane_config->tiling)
8061 offset = I915_READ(DSPTILEOFF(plane));
8063 offset = I915_READ(DSPLINOFF(plane));
8064 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8066 base = I915_READ(DSPADDR(plane));
8068 plane_config->base = base;
8070 val = I915_READ(PIPESRC(pipe));
8071 fb->width = ((val >> 16) & 0xfff) + 1;
8072 fb->height = ((val >> 0) & 0xfff) + 1;
8074 val = I915_READ(DSPSTRIDE(pipe));
8075 fb->pitches[0] = val & 0xffffffc0;
8077 aligned_height = intel_fb_align_height(dev, fb->height,
8081 plane_config->size = fb->pitches[0] * aligned_height;
8083 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8084 pipe_name(pipe), plane, fb->width, fb->height,
8085 fb->bits_per_pixel, base, fb->pitches[0],
8086 plane_config->size);
8088 plane_config->fb = intel_fb;
8091 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8092 struct intel_crtc_state *pipe_config)
8094 struct drm_device *dev = crtc->base.dev;
8095 struct drm_i915_private *dev_priv = dev->dev_private;
8096 int pipe = pipe_config->cpu_transcoder;
8097 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8098 intel_clock_t clock;
8099 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8100 int refclk = 100000;
8102 mutex_lock(&dev_priv->sb_lock);
8103 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8104 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8105 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8106 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8107 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8108 mutex_unlock(&dev_priv->sb_lock);
8110 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8111 clock.m2 = (pll_dw0 & 0xff) << 22;
8112 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8113 clock.m2 |= pll_dw2 & 0x3fffff;
8114 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8115 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8116 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8118 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8121 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8122 struct intel_crtc_state *pipe_config)
8124 struct drm_device *dev = crtc->base.dev;
8125 struct drm_i915_private *dev_priv = dev->dev_private;
8128 if (!intel_display_power_is_enabled(dev_priv,
8129 POWER_DOMAIN_PIPE(crtc->pipe)))
8132 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8133 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8135 tmp = I915_READ(PIPECONF(crtc->pipe));
8136 if (!(tmp & PIPECONF_ENABLE))
8139 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8140 switch (tmp & PIPECONF_BPC_MASK) {
8142 pipe_config->pipe_bpp = 18;
8145 pipe_config->pipe_bpp = 24;
8147 case PIPECONF_10BPC:
8148 pipe_config->pipe_bpp = 30;
8155 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8156 pipe_config->limited_color_range = true;
8158 if (INTEL_INFO(dev)->gen < 4)
8159 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8161 intel_get_pipe_timings(crtc, pipe_config);
8163 i9xx_get_pfit_config(crtc, pipe_config);
8165 if (INTEL_INFO(dev)->gen >= 4) {
8166 tmp = I915_READ(DPLL_MD(crtc->pipe));
8167 pipe_config->pixel_multiplier =
8168 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8169 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8170 pipe_config->dpll_hw_state.dpll_md = tmp;
8171 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8172 tmp = I915_READ(DPLL(crtc->pipe));
8173 pipe_config->pixel_multiplier =
8174 ((tmp & SDVO_MULTIPLIER_MASK)
8175 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8177 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8178 * port and will be fixed up in the encoder->get_config
8180 pipe_config->pixel_multiplier = 1;
8182 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8183 if (!IS_VALLEYVIEW(dev)) {
8185 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8186 * on 830. Filter it out here so that we don't
8187 * report errors due to that.
8190 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8192 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8193 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8195 /* Mask out read-only status bits. */
8196 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8197 DPLL_PORTC_READY_MASK |
8198 DPLL_PORTB_READY_MASK);
8201 if (IS_CHERRYVIEW(dev))
8202 chv_crtc_clock_get(crtc, pipe_config);
8203 else if (IS_VALLEYVIEW(dev))
8204 vlv_crtc_clock_get(crtc, pipe_config);
8206 i9xx_crtc_clock_get(crtc, pipe_config);
8211 static void ironlake_init_pch_refclk(struct drm_device *dev)
8213 struct drm_i915_private *dev_priv = dev->dev_private;
8214 struct intel_encoder *encoder;
8216 bool has_lvds = false;
8217 bool has_cpu_edp = false;
8218 bool has_panel = false;
8219 bool has_ck505 = false;
8220 bool can_ssc = false;
8222 /* We need to take the global config into account */
8223 for_each_intel_encoder(dev, encoder) {
8224 switch (encoder->type) {
8225 case INTEL_OUTPUT_LVDS:
8229 case INTEL_OUTPUT_EDP:
8231 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8239 if (HAS_PCH_IBX(dev)) {
8240 has_ck505 = dev_priv->vbt.display_clock_mode;
8241 can_ssc = has_ck505;
8247 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8248 has_panel, has_lvds, has_ck505);
8250 /* Ironlake: try to setup display ref clock before DPLL
8251 * enabling. This is only under driver's control after
8252 * PCH B stepping, previous chipset stepping should be
8253 * ignoring this setting.
8255 val = I915_READ(PCH_DREF_CONTROL);
8257 /* As we must carefully and slowly disable/enable each source in turn,
8258 * compute the final state we want first and check if we need to
8259 * make any changes at all.
8262 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8264 final |= DREF_NONSPREAD_CK505_ENABLE;
8266 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8268 final &= ~DREF_SSC_SOURCE_MASK;
8269 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8270 final &= ~DREF_SSC1_ENABLE;
8273 final |= DREF_SSC_SOURCE_ENABLE;
8275 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8276 final |= DREF_SSC1_ENABLE;
8279 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8280 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8282 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8284 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8286 final |= DREF_SSC_SOURCE_DISABLE;
8287 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8293 /* Always enable nonspread source */
8294 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8297 val |= DREF_NONSPREAD_CK505_ENABLE;
8299 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8302 val &= ~DREF_SSC_SOURCE_MASK;
8303 val |= DREF_SSC_SOURCE_ENABLE;
8305 /* SSC must be turned on before enabling the CPU output */
8306 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8307 DRM_DEBUG_KMS("Using SSC on panel\n");
8308 val |= DREF_SSC1_ENABLE;
8310 val &= ~DREF_SSC1_ENABLE;
8312 /* Get SSC going before enabling the outputs */
8313 I915_WRITE(PCH_DREF_CONTROL, val);
8314 POSTING_READ(PCH_DREF_CONTROL);
8317 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8319 /* Enable CPU source on CPU attached eDP */
8321 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8322 DRM_DEBUG_KMS("Using SSC on eDP\n");
8323 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8325 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8327 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8329 I915_WRITE(PCH_DREF_CONTROL, val);
8330 POSTING_READ(PCH_DREF_CONTROL);
8333 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8335 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8337 /* Turn off CPU output */
8338 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8340 I915_WRITE(PCH_DREF_CONTROL, val);
8341 POSTING_READ(PCH_DREF_CONTROL);
8344 /* Turn off the SSC source */
8345 val &= ~DREF_SSC_SOURCE_MASK;
8346 val |= DREF_SSC_SOURCE_DISABLE;
8349 val &= ~DREF_SSC1_ENABLE;
8351 I915_WRITE(PCH_DREF_CONTROL, val);
8352 POSTING_READ(PCH_DREF_CONTROL);
8356 BUG_ON(val != final);
8359 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8363 tmp = I915_READ(SOUTH_CHICKEN2);
8364 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8365 I915_WRITE(SOUTH_CHICKEN2, tmp);
8367 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8368 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8369 DRM_ERROR("FDI mPHY reset assert timeout\n");
8371 tmp = I915_READ(SOUTH_CHICKEN2);
8372 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8373 I915_WRITE(SOUTH_CHICKEN2, tmp);
8375 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8376 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8377 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8380 /* WaMPhyProgramming:hsw */
8381 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8385 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8386 tmp &= ~(0xFF << 24);
8387 tmp |= (0x12 << 24);
8388 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8390 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8392 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8394 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8396 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8398 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8399 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8400 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8402 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8403 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8404 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8406 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8409 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8411 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8414 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8416 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8419 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8421 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8424 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8426 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8427 tmp &= ~(0xFF << 16);
8428 tmp |= (0x1C << 16);
8429 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8431 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8432 tmp &= ~(0xFF << 16);
8433 tmp |= (0x1C << 16);
8434 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8436 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8438 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8440 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8442 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8444 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8445 tmp &= ~(0xF << 28);
8447 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8449 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8450 tmp &= ~(0xF << 28);
8452 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8455 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8456 * Programming" based on the parameters passed:
8457 * - Sequence to enable CLKOUT_DP
8458 * - Sequence to enable CLKOUT_DP without spread
8459 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8461 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8464 struct drm_i915_private *dev_priv = dev->dev_private;
8467 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8469 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8470 with_fdi, "LP PCH doesn't have FDI\n"))
8473 mutex_lock(&dev_priv->sb_lock);
8475 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8476 tmp &= ~SBI_SSCCTL_DISABLE;
8477 tmp |= SBI_SSCCTL_PATHALT;
8478 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8483 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8484 tmp &= ~SBI_SSCCTL_PATHALT;
8485 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8488 lpt_reset_fdi_mphy(dev_priv);
8489 lpt_program_fdi_mphy(dev_priv);
8493 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8494 SBI_GEN0 : SBI_DBUFF0;
8495 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8496 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8497 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8499 mutex_unlock(&dev_priv->sb_lock);
8502 /* Sequence to disable CLKOUT_DP */
8503 static void lpt_disable_clkout_dp(struct drm_device *dev)
8505 struct drm_i915_private *dev_priv = dev->dev_private;
8508 mutex_lock(&dev_priv->sb_lock);
8510 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8511 SBI_GEN0 : SBI_DBUFF0;
8512 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8513 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8514 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8516 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8517 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8518 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8519 tmp |= SBI_SSCCTL_PATHALT;
8520 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8523 tmp |= SBI_SSCCTL_DISABLE;
8524 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8527 mutex_unlock(&dev_priv->sb_lock);
8530 static void lpt_init_pch_refclk(struct drm_device *dev)
8532 struct intel_encoder *encoder;
8533 bool has_vga = false;
8535 for_each_intel_encoder(dev, encoder) {
8536 switch (encoder->type) {
8537 case INTEL_OUTPUT_ANALOG:
8546 lpt_enable_clkout_dp(dev, true, true);
8548 lpt_disable_clkout_dp(dev);
8552 * Initialize reference clocks when the driver loads
8554 void intel_init_pch_refclk(struct drm_device *dev)
8556 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8557 ironlake_init_pch_refclk(dev);
8558 else if (HAS_PCH_LPT(dev))
8559 lpt_init_pch_refclk(dev);
8562 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8564 struct drm_device *dev = crtc_state->base.crtc->dev;
8565 struct drm_i915_private *dev_priv = dev->dev_private;
8566 struct drm_atomic_state *state = crtc_state->base.state;
8567 struct drm_connector *connector;
8568 struct drm_connector_state *connector_state;
8569 struct intel_encoder *encoder;
8570 int num_connectors = 0, i;
8571 bool is_lvds = false;
8573 for_each_connector_in_state(state, connector, connector_state, i) {
8574 if (connector_state->crtc != crtc_state->base.crtc)
8577 encoder = to_intel_encoder(connector_state->best_encoder);
8579 switch (encoder->type) {
8580 case INTEL_OUTPUT_LVDS:
8589 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8590 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8591 dev_priv->vbt.lvds_ssc_freq);
8592 return dev_priv->vbt.lvds_ssc_freq;
8598 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8600 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8602 int pipe = intel_crtc->pipe;
8607 switch (intel_crtc->config->pipe_bpp) {
8609 val |= PIPECONF_6BPC;
8612 val |= PIPECONF_8BPC;
8615 val |= PIPECONF_10BPC;
8618 val |= PIPECONF_12BPC;
8621 /* Case prevented by intel_choose_pipe_bpp_dither. */
8625 if (intel_crtc->config->dither)
8626 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8628 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8629 val |= PIPECONF_INTERLACED_ILK;
8631 val |= PIPECONF_PROGRESSIVE;
8633 if (intel_crtc->config->limited_color_range)
8634 val |= PIPECONF_COLOR_RANGE_SELECT;
8636 I915_WRITE(PIPECONF(pipe), val);
8637 POSTING_READ(PIPECONF(pipe));
8641 * Set up the pipe CSC unit.
8643 * Currently only full range RGB to limited range RGB conversion
8644 * is supported, but eventually this should handle various
8645 * RGB<->YCbCr scenarios as well.
8647 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8649 struct drm_device *dev = crtc->dev;
8650 struct drm_i915_private *dev_priv = dev->dev_private;
8651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8652 int pipe = intel_crtc->pipe;
8653 uint16_t coeff = 0x7800; /* 1.0 */
8656 * TODO: Check what kind of values actually come out of the pipe
8657 * with these coeff/postoff values and adjust to get the best
8658 * accuracy. Perhaps we even need to take the bpc value into
8662 if (intel_crtc->config->limited_color_range)
8663 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8666 * GY/GU and RY/RU should be the other way around according
8667 * to BSpec, but reality doesn't agree. Just set them up in
8668 * a way that results in the correct picture.
8670 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8671 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8673 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8674 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8676 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8677 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8679 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8680 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8681 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8683 if (INTEL_INFO(dev)->gen > 6) {
8684 uint16_t postoff = 0;
8686 if (intel_crtc->config->limited_color_range)
8687 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8689 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8690 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8691 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8693 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8695 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8697 if (intel_crtc->config->limited_color_range)
8698 mode |= CSC_BLACK_SCREEN_OFFSET;
8700 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8704 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8706 struct drm_device *dev = crtc->dev;
8707 struct drm_i915_private *dev_priv = dev->dev_private;
8708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8709 enum pipe pipe = intel_crtc->pipe;
8710 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8715 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8716 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8718 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8719 val |= PIPECONF_INTERLACED_ILK;
8721 val |= PIPECONF_PROGRESSIVE;
8723 I915_WRITE(PIPECONF(cpu_transcoder), val);
8724 POSTING_READ(PIPECONF(cpu_transcoder));
8726 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8727 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8729 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8732 switch (intel_crtc->config->pipe_bpp) {
8734 val |= PIPEMISC_DITHER_6_BPC;
8737 val |= PIPEMISC_DITHER_8_BPC;
8740 val |= PIPEMISC_DITHER_10_BPC;
8743 val |= PIPEMISC_DITHER_12_BPC;
8746 /* Case prevented by pipe_config_set_bpp. */
8750 if (intel_crtc->config->dither)
8751 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8753 I915_WRITE(PIPEMISC(pipe), val);
8757 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8758 struct intel_crtc_state *crtc_state,
8759 intel_clock_t *clock,
8760 bool *has_reduced_clock,
8761 intel_clock_t *reduced_clock)
8763 struct drm_device *dev = crtc->dev;
8764 struct drm_i915_private *dev_priv = dev->dev_private;
8766 const intel_limit_t *limit;
8769 refclk = ironlake_get_refclk(crtc_state);
8772 * Returns a set of divisors for the desired target clock with the given
8773 * refclk, or FALSE. The returned values represent the clock equation:
8774 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8776 limit = intel_limit(crtc_state, refclk);
8777 ret = dev_priv->display.find_dpll(limit, crtc_state,
8778 crtc_state->port_clock,
8779 refclk, NULL, clock);
8786 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8789 * Account for spread spectrum to avoid
8790 * oversubscribing the link. Max center spread
8791 * is 2.5%; use 5% for safety's sake.
8793 u32 bps = target_clock * bpp * 21 / 20;
8794 return DIV_ROUND_UP(bps, link_bw * 8);
8797 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8799 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8802 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8803 struct intel_crtc_state *crtc_state,
8805 intel_clock_t *reduced_clock, u32 *fp2)
8807 struct drm_crtc *crtc = &intel_crtc->base;
8808 struct drm_device *dev = crtc->dev;
8809 struct drm_i915_private *dev_priv = dev->dev_private;
8810 struct drm_atomic_state *state = crtc_state->base.state;
8811 struct drm_connector *connector;
8812 struct drm_connector_state *connector_state;
8813 struct intel_encoder *encoder;
8815 int factor, num_connectors = 0, i;
8816 bool is_lvds = false, is_sdvo = false;
8818 for_each_connector_in_state(state, connector, connector_state, i) {
8819 if (connector_state->crtc != crtc_state->base.crtc)
8822 encoder = to_intel_encoder(connector_state->best_encoder);
8824 switch (encoder->type) {
8825 case INTEL_OUTPUT_LVDS:
8828 case INTEL_OUTPUT_SDVO:
8829 case INTEL_OUTPUT_HDMI:
8839 /* Enable autotuning of the PLL clock (if permissible) */
8842 if ((intel_panel_use_ssc(dev_priv) &&
8843 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8844 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8846 } else if (crtc_state->sdvo_tv_clock)
8849 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8852 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8858 dpll |= DPLLB_MODE_LVDS;
8860 dpll |= DPLLB_MODE_DAC_SERIAL;
8862 dpll |= (crtc_state->pixel_multiplier - 1)
8863 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8866 dpll |= DPLL_SDVO_HIGH_SPEED;
8867 if (crtc_state->has_dp_encoder)
8868 dpll |= DPLL_SDVO_HIGH_SPEED;
8870 /* compute bitmask from p1 value */
8871 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8873 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8875 switch (crtc_state->dpll.p2) {
8877 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8880 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8883 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8886 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8890 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8891 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8893 dpll |= PLL_REF_INPUT_DREFCLK;
8895 return dpll | DPLL_VCO_ENABLE;
8898 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8899 struct intel_crtc_state *crtc_state)
8901 struct drm_device *dev = crtc->base.dev;
8902 intel_clock_t clock, reduced_clock;
8903 u32 dpll = 0, fp = 0, fp2 = 0;
8904 bool ok, has_reduced_clock = false;
8905 bool is_lvds = false;
8906 struct intel_shared_dpll *pll;
8908 memset(&crtc_state->dpll_hw_state, 0,
8909 sizeof(crtc_state->dpll_hw_state));
8911 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8913 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8914 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8916 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8917 &has_reduced_clock, &reduced_clock);
8918 if (!ok && !crtc_state->clock_set) {
8919 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8922 /* Compat-code for transition, will disappear. */
8923 if (!crtc_state->clock_set) {
8924 crtc_state->dpll.n = clock.n;
8925 crtc_state->dpll.m1 = clock.m1;
8926 crtc_state->dpll.m2 = clock.m2;
8927 crtc_state->dpll.p1 = clock.p1;
8928 crtc_state->dpll.p2 = clock.p2;
8931 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8932 if (crtc_state->has_pch_encoder) {
8933 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8934 if (has_reduced_clock)
8935 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8937 dpll = ironlake_compute_dpll(crtc, crtc_state,
8938 &fp, &reduced_clock,
8939 has_reduced_clock ? &fp2 : NULL);
8941 crtc_state->dpll_hw_state.dpll = dpll;
8942 crtc_state->dpll_hw_state.fp0 = fp;
8943 if (has_reduced_clock)
8944 crtc_state->dpll_hw_state.fp1 = fp2;
8946 crtc_state->dpll_hw_state.fp1 = fp;
8948 pll = intel_get_shared_dpll(crtc, crtc_state);
8950 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8951 pipe_name(crtc->pipe));
8956 if (is_lvds && has_reduced_clock)
8957 crtc->lowfreq_avail = true;
8959 crtc->lowfreq_avail = false;
8964 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8965 struct intel_link_m_n *m_n)
8967 struct drm_device *dev = crtc->base.dev;
8968 struct drm_i915_private *dev_priv = dev->dev_private;
8969 enum pipe pipe = crtc->pipe;
8971 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8972 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8973 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8975 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8976 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8977 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8980 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8981 enum transcoder transcoder,
8982 struct intel_link_m_n *m_n,
8983 struct intel_link_m_n *m2_n2)
8985 struct drm_device *dev = crtc->base.dev;
8986 struct drm_i915_private *dev_priv = dev->dev_private;
8987 enum pipe pipe = crtc->pipe;
8989 if (INTEL_INFO(dev)->gen >= 5) {
8990 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8991 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8992 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8994 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8995 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8996 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8997 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8998 * gen < 8) and if DRRS is supported (to make sure the
8999 * registers are not unnecessarily read).
9001 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9002 crtc->config->has_drrs) {
9003 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9004 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9005 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9007 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9008 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9009 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9012 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9013 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9014 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9016 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9017 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9018 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9022 void intel_dp_get_m_n(struct intel_crtc *crtc,
9023 struct intel_crtc_state *pipe_config)
9025 if (pipe_config->has_pch_encoder)
9026 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9028 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9029 &pipe_config->dp_m_n,
9030 &pipe_config->dp_m2_n2);
9033 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9034 struct intel_crtc_state *pipe_config)
9036 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9037 &pipe_config->fdi_m_n, NULL);
9040 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9041 struct intel_crtc_state *pipe_config)
9043 struct drm_device *dev = crtc->base.dev;
9044 struct drm_i915_private *dev_priv = dev->dev_private;
9045 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9046 uint32_t ps_ctrl = 0;
9050 /* find scaler attached to this pipe */
9051 for (i = 0; i < crtc->num_scalers; i++) {
9052 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9053 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9055 pipe_config->pch_pfit.enabled = true;
9056 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9057 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9062 scaler_state->scaler_id = id;
9064 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9066 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9071 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9072 struct intel_initial_plane_config *plane_config)
9074 struct drm_device *dev = crtc->base.dev;
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 u32 val, base, offset, stride_mult, tiling;
9077 int pipe = crtc->pipe;
9078 int fourcc, pixel_format;
9079 unsigned int aligned_height;
9080 struct drm_framebuffer *fb;
9081 struct intel_framebuffer *intel_fb;
9083 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9085 DRM_DEBUG_KMS("failed to alloc fb\n");
9089 fb = &intel_fb->base;
9091 val = I915_READ(PLANE_CTL(pipe, 0));
9092 if (!(val & PLANE_CTL_ENABLE))
9095 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9096 fourcc = skl_format_to_fourcc(pixel_format,
9097 val & PLANE_CTL_ORDER_RGBX,
9098 val & PLANE_CTL_ALPHA_MASK);
9099 fb->pixel_format = fourcc;
9100 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9102 tiling = val & PLANE_CTL_TILED_MASK;
9104 case PLANE_CTL_TILED_LINEAR:
9105 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9107 case PLANE_CTL_TILED_X:
9108 plane_config->tiling = I915_TILING_X;
9109 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9111 case PLANE_CTL_TILED_Y:
9112 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9114 case PLANE_CTL_TILED_YF:
9115 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9118 MISSING_CASE(tiling);
9122 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9123 plane_config->base = base;
9125 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9127 val = I915_READ(PLANE_SIZE(pipe, 0));
9128 fb->height = ((val >> 16) & 0xfff) + 1;
9129 fb->width = ((val >> 0) & 0x1fff) + 1;
9131 val = I915_READ(PLANE_STRIDE(pipe, 0));
9132 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9134 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9136 aligned_height = intel_fb_align_height(dev, fb->height,
9140 plane_config->size = fb->pitches[0] * aligned_height;
9142 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9143 pipe_name(pipe), fb->width, fb->height,
9144 fb->bits_per_pixel, base, fb->pitches[0],
9145 plane_config->size);
9147 plane_config->fb = intel_fb;
9154 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9155 struct intel_crtc_state *pipe_config)
9157 struct drm_device *dev = crtc->base.dev;
9158 struct drm_i915_private *dev_priv = dev->dev_private;
9161 tmp = I915_READ(PF_CTL(crtc->pipe));
9163 if (tmp & PF_ENABLE) {
9164 pipe_config->pch_pfit.enabled = true;
9165 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9166 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9168 /* We currently do not free assignements of panel fitters on
9169 * ivb/hsw (since we don't use the higher upscaling modes which
9170 * differentiates them) so just WARN about this case for now. */
9172 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9173 PF_PIPE_SEL_IVB(crtc->pipe));
9179 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9180 struct intel_initial_plane_config *plane_config)
9182 struct drm_device *dev = crtc->base.dev;
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184 u32 val, base, offset;
9185 int pipe = crtc->pipe;
9186 int fourcc, pixel_format;
9187 unsigned int aligned_height;
9188 struct drm_framebuffer *fb;
9189 struct intel_framebuffer *intel_fb;
9191 val = I915_READ(DSPCNTR(pipe));
9192 if (!(val & DISPLAY_PLANE_ENABLE))
9195 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9197 DRM_DEBUG_KMS("failed to alloc fb\n");
9201 fb = &intel_fb->base;
9203 if (INTEL_INFO(dev)->gen >= 4) {
9204 if (val & DISPPLANE_TILED) {
9205 plane_config->tiling = I915_TILING_X;
9206 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9210 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9211 fourcc = i9xx_format_to_fourcc(pixel_format);
9212 fb->pixel_format = fourcc;
9213 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9215 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9216 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9217 offset = I915_READ(DSPOFFSET(pipe));
9219 if (plane_config->tiling)
9220 offset = I915_READ(DSPTILEOFF(pipe));
9222 offset = I915_READ(DSPLINOFF(pipe));
9224 plane_config->base = base;
9226 val = I915_READ(PIPESRC(pipe));
9227 fb->width = ((val >> 16) & 0xfff) + 1;
9228 fb->height = ((val >> 0) & 0xfff) + 1;
9230 val = I915_READ(DSPSTRIDE(pipe));
9231 fb->pitches[0] = val & 0xffffffc0;
9233 aligned_height = intel_fb_align_height(dev, fb->height,
9237 plane_config->size = fb->pitches[0] * aligned_height;
9239 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9240 pipe_name(pipe), fb->width, fb->height,
9241 fb->bits_per_pixel, base, fb->pitches[0],
9242 plane_config->size);
9244 plane_config->fb = intel_fb;
9247 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9248 struct intel_crtc_state *pipe_config)
9250 struct drm_device *dev = crtc->base.dev;
9251 struct drm_i915_private *dev_priv = dev->dev_private;
9254 if (!intel_display_power_is_enabled(dev_priv,
9255 POWER_DOMAIN_PIPE(crtc->pipe)))
9258 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9259 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9261 tmp = I915_READ(PIPECONF(crtc->pipe));
9262 if (!(tmp & PIPECONF_ENABLE))
9265 switch (tmp & PIPECONF_BPC_MASK) {
9267 pipe_config->pipe_bpp = 18;
9270 pipe_config->pipe_bpp = 24;
9272 case PIPECONF_10BPC:
9273 pipe_config->pipe_bpp = 30;
9275 case PIPECONF_12BPC:
9276 pipe_config->pipe_bpp = 36;
9282 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9283 pipe_config->limited_color_range = true;
9285 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9286 struct intel_shared_dpll *pll;
9288 pipe_config->has_pch_encoder = true;
9290 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9291 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9292 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9294 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9296 if (HAS_PCH_IBX(dev_priv->dev)) {
9297 pipe_config->shared_dpll =
9298 (enum intel_dpll_id) crtc->pipe;
9300 tmp = I915_READ(PCH_DPLL_SEL);
9301 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9302 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9304 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9307 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9309 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9310 &pipe_config->dpll_hw_state));
9312 tmp = pipe_config->dpll_hw_state.dpll;
9313 pipe_config->pixel_multiplier =
9314 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9315 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9317 ironlake_pch_clock_get(crtc, pipe_config);
9319 pipe_config->pixel_multiplier = 1;
9322 intel_get_pipe_timings(crtc, pipe_config);
9324 ironlake_get_pfit_config(crtc, pipe_config);
9329 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9331 struct drm_device *dev = dev_priv->dev;
9332 struct intel_crtc *crtc;
9334 for_each_intel_crtc(dev, crtc)
9335 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9336 pipe_name(crtc->pipe));
9338 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9339 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9340 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9341 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9342 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9343 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9344 "CPU PWM1 enabled\n");
9345 if (IS_HASWELL(dev))
9346 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9347 "CPU PWM2 enabled\n");
9348 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9349 "PCH PWM1 enabled\n");
9350 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9351 "Utility pin enabled\n");
9352 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9355 * In theory we can still leave IRQs enabled, as long as only the HPD
9356 * interrupts remain enabled. We used to check for that, but since it's
9357 * gen-specific and since we only disable LCPLL after we fully disable
9358 * the interrupts, the check below should be enough.
9360 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9363 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9365 struct drm_device *dev = dev_priv->dev;
9367 if (IS_HASWELL(dev))
9368 return I915_READ(D_COMP_HSW);
9370 return I915_READ(D_COMP_BDW);
9373 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9375 struct drm_device *dev = dev_priv->dev;
9377 if (IS_HASWELL(dev)) {
9378 mutex_lock(&dev_priv->rps.hw_lock);
9379 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9381 DRM_ERROR("Failed to write to D_COMP\n");
9382 mutex_unlock(&dev_priv->rps.hw_lock);
9384 I915_WRITE(D_COMP_BDW, val);
9385 POSTING_READ(D_COMP_BDW);
9390 * This function implements pieces of two sequences from BSpec:
9391 * - Sequence for display software to disable LCPLL
9392 * - Sequence for display software to allow package C8+
9393 * The steps implemented here are just the steps that actually touch the LCPLL
9394 * register. Callers should take care of disabling all the display engine
9395 * functions, doing the mode unset, fixing interrupts, etc.
9397 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9398 bool switch_to_fclk, bool allow_power_down)
9402 assert_can_disable_lcpll(dev_priv);
9404 val = I915_READ(LCPLL_CTL);
9406 if (switch_to_fclk) {
9407 val |= LCPLL_CD_SOURCE_FCLK;
9408 I915_WRITE(LCPLL_CTL, val);
9410 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9411 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9412 DRM_ERROR("Switching to FCLK failed\n");
9414 val = I915_READ(LCPLL_CTL);
9417 val |= LCPLL_PLL_DISABLE;
9418 I915_WRITE(LCPLL_CTL, val);
9419 POSTING_READ(LCPLL_CTL);
9421 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9422 DRM_ERROR("LCPLL still locked\n");
9424 val = hsw_read_dcomp(dev_priv);
9425 val |= D_COMP_COMP_DISABLE;
9426 hsw_write_dcomp(dev_priv, val);
9429 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9431 DRM_ERROR("D_COMP RCOMP still in progress\n");
9433 if (allow_power_down) {
9434 val = I915_READ(LCPLL_CTL);
9435 val |= LCPLL_POWER_DOWN_ALLOW;
9436 I915_WRITE(LCPLL_CTL, val);
9437 POSTING_READ(LCPLL_CTL);
9442 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9445 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9449 val = I915_READ(LCPLL_CTL);
9451 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9452 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9456 * Make sure we're not on PC8 state before disabling PC8, otherwise
9457 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9459 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9461 if (val & LCPLL_POWER_DOWN_ALLOW) {
9462 val &= ~LCPLL_POWER_DOWN_ALLOW;
9463 I915_WRITE(LCPLL_CTL, val);
9464 POSTING_READ(LCPLL_CTL);
9467 val = hsw_read_dcomp(dev_priv);
9468 val |= D_COMP_COMP_FORCE;
9469 val &= ~D_COMP_COMP_DISABLE;
9470 hsw_write_dcomp(dev_priv, val);
9472 val = I915_READ(LCPLL_CTL);
9473 val &= ~LCPLL_PLL_DISABLE;
9474 I915_WRITE(LCPLL_CTL, val);
9476 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9477 DRM_ERROR("LCPLL not locked yet\n");
9479 if (val & LCPLL_CD_SOURCE_FCLK) {
9480 val = I915_READ(LCPLL_CTL);
9481 val &= ~LCPLL_CD_SOURCE_FCLK;
9482 I915_WRITE(LCPLL_CTL, val);
9484 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9485 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9486 DRM_ERROR("Switching back to LCPLL failed\n");
9489 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9490 intel_update_cdclk(dev_priv->dev);
9494 * Package states C8 and deeper are really deep PC states that can only be
9495 * reached when all the devices on the system allow it, so even if the graphics
9496 * device allows PC8+, it doesn't mean the system will actually get to these
9497 * states. Our driver only allows PC8+ when going into runtime PM.
9499 * The requirements for PC8+ are that all the outputs are disabled, the power
9500 * well is disabled and most interrupts are disabled, and these are also
9501 * requirements for runtime PM. When these conditions are met, we manually do
9502 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9503 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9506 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9507 * the state of some registers, so when we come back from PC8+ we need to
9508 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9509 * need to take care of the registers kept by RC6. Notice that this happens even
9510 * if we don't put the device in PCI D3 state (which is what currently happens
9511 * because of the runtime PM support).
9513 * For more, read "Display Sequences for Package C8" on the hardware
9516 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9518 struct drm_device *dev = dev_priv->dev;
9521 DRM_DEBUG_KMS("Enabling package C8+\n");
9523 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9524 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9525 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9526 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9529 lpt_disable_clkout_dp(dev);
9530 hsw_disable_lcpll(dev_priv, true, true);
9533 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9535 struct drm_device *dev = dev_priv->dev;
9538 DRM_DEBUG_KMS("Disabling package C8+\n");
9540 hsw_restore_lcpll(dev_priv);
9541 lpt_init_pch_refclk(dev);
9543 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9544 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9545 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9546 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9549 intel_prepare_ddi(dev);
9552 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9554 struct drm_device *dev = old_state->dev;
9555 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9557 broxton_set_cdclk(dev, req_cdclk);
9560 /* compute the max rate for new configuration */
9561 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9563 struct intel_crtc *intel_crtc;
9564 struct intel_crtc_state *crtc_state;
9565 int max_pixel_rate = 0;
9567 for_each_intel_crtc(state->dev, intel_crtc) {
9570 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9571 if (IS_ERR(crtc_state))
9572 return PTR_ERR(crtc_state);
9574 if (!crtc_state->base.enable)
9577 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9579 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9580 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9581 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9583 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9586 return max_pixel_rate;
9589 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9591 struct drm_i915_private *dev_priv = dev->dev_private;
9595 if (WARN((I915_READ(LCPLL_CTL) &
9596 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9597 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9598 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9599 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9600 "trying to change cdclk frequency with cdclk not enabled\n"))
9603 mutex_lock(&dev_priv->rps.hw_lock);
9604 ret = sandybridge_pcode_write(dev_priv,
9605 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9606 mutex_unlock(&dev_priv->rps.hw_lock);
9608 DRM_ERROR("failed to inform pcode about cdclk change\n");
9612 val = I915_READ(LCPLL_CTL);
9613 val |= LCPLL_CD_SOURCE_FCLK;
9614 I915_WRITE(LCPLL_CTL, val);
9616 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9617 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9618 DRM_ERROR("Switching to FCLK failed\n");
9620 val = I915_READ(LCPLL_CTL);
9621 val &= ~LCPLL_CLK_FREQ_MASK;
9625 val |= LCPLL_CLK_FREQ_450;
9629 val |= LCPLL_CLK_FREQ_54O_BDW;
9633 val |= LCPLL_CLK_FREQ_337_5_BDW;
9637 val |= LCPLL_CLK_FREQ_675_BDW;
9641 WARN(1, "invalid cdclk frequency\n");
9645 I915_WRITE(LCPLL_CTL, val);
9647 val = I915_READ(LCPLL_CTL);
9648 val &= ~LCPLL_CD_SOURCE_FCLK;
9649 I915_WRITE(LCPLL_CTL, val);
9651 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9652 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9653 DRM_ERROR("Switching back to LCPLL failed\n");
9655 mutex_lock(&dev_priv->rps.hw_lock);
9656 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9657 mutex_unlock(&dev_priv->rps.hw_lock);
9659 intel_update_cdclk(dev);
9661 WARN(cdclk != dev_priv->cdclk_freq,
9662 "cdclk requested %d kHz but got %d kHz\n",
9663 cdclk, dev_priv->cdclk_freq);
9666 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9668 struct drm_i915_private *dev_priv = to_i915(state->dev);
9669 int max_pixclk = ilk_max_pixel_rate(state);
9673 * FIXME should also account for plane ratio
9674 * once 64bpp pixel formats are supported.
9676 if (max_pixclk > 540000)
9678 else if (max_pixclk > 450000)
9680 else if (max_pixclk > 337500)
9686 * FIXME move the cdclk caclulation to
9687 * compute_config() so we can fail gracegully.
9689 if (cdclk > dev_priv->max_cdclk_freq) {
9690 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9691 cdclk, dev_priv->max_cdclk_freq);
9692 cdclk = dev_priv->max_cdclk_freq;
9695 to_intel_atomic_state(state)->cdclk = cdclk;
9700 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9702 struct drm_device *dev = old_state->dev;
9703 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9705 broadwell_set_cdclk(dev, req_cdclk);
9708 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9709 struct intel_crtc_state *crtc_state)
9711 if (!intel_ddi_pll_select(crtc, crtc_state))
9714 crtc->lowfreq_avail = false;
9719 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9721 struct intel_crtc_state *pipe_config)
9725 pipe_config->ddi_pll_sel = SKL_DPLL0;
9726 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9729 pipe_config->ddi_pll_sel = SKL_DPLL1;
9730 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9733 pipe_config->ddi_pll_sel = SKL_DPLL2;
9734 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9737 DRM_ERROR("Incorrect port type\n");
9741 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9743 struct intel_crtc_state *pipe_config)
9745 u32 temp, dpll_ctl1;
9747 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9748 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9750 switch (pipe_config->ddi_pll_sel) {
9753 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9754 * of the shared DPLL framework and thus needs to be read out
9757 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9758 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9761 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9764 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9767 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9772 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9774 struct intel_crtc_state *pipe_config)
9776 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9778 switch (pipe_config->ddi_pll_sel) {
9779 case PORT_CLK_SEL_WRPLL1:
9780 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9782 case PORT_CLK_SEL_WRPLL2:
9783 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9788 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9789 struct intel_crtc_state *pipe_config)
9791 struct drm_device *dev = crtc->base.dev;
9792 struct drm_i915_private *dev_priv = dev->dev_private;
9793 struct intel_shared_dpll *pll;
9797 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9799 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9801 if (IS_SKYLAKE(dev))
9802 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9803 else if (IS_BROXTON(dev))
9804 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9806 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9808 if (pipe_config->shared_dpll >= 0) {
9809 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9811 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9812 &pipe_config->dpll_hw_state));
9816 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9817 * DDI E. So just check whether this pipe is wired to DDI E and whether
9818 * the PCH transcoder is on.
9820 if (INTEL_INFO(dev)->gen < 9 &&
9821 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9822 pipe_config->has_pch_encoder = true;
9824 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9825 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9826 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9828 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9832 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9833 struct intel_crtc_state *pipe_config)
9835 struct drm_device *dev = crtc->base.dev;
9836 struct drm_i915_private *dev_priv = dev->dev_private;
9837 enum intel_display_power_domain pfit_domain;
9840 if (!intel_display_power_is_enabled(dev_priv,
9841 POWER_DOMAIN_PIPE(crtc->pipe)))
9844 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9845 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9847 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9848 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9849 enum pipe trans_edp_pipe;
9850 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9852 WARN(1, "unknown pipe linked to edp transcoder\n");
9853 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9854 case TRANS_DDI_EDP_INPUT_A_ON:
9855 trans_edp_pipe = PIPE_A;
9857 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9858 trans_edp_pipe = PIPE_B;
9860 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9861 trans_edp_pipe = PIPE_C;
9865 if (trans_edp_pipe == crtc->pipe)
9866 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9869 if (!intel_display_power_is_enabled(dev_priv,
9870 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9873 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9874 if (!(tmp & PIPECONF_ENABLE))
9877 haswell_get_ddi_port_state(crtc, pipe_config);
9879 intel_get_pipe_timings(crtc, pipe_config);
9881 if (INTEL_INFO(dev)->gen >= 9) {
9882 skl_init_scalers(dev, crtc, pipe_config);
9885 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9887 if (INTEL_INFO(dev)->gen >= 9) {
9888 pipe_config->scaler_state.scaler_id = -1;
9889 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9892 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9893 if (INTEL_INFO(dev)->gen == 9)
9894 skylake_get_pfit_config(crtc, pipe_config);
9895 else if (INTEL_INFO(dev)->gen < 9)
9896 ironlake_get_pfit_config(crtc, pipe_config);
9898 MISSING_CASE(INTEL_INFO(dev)->gen);
9901 if (IS_HASWELL(dev))
9902 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9903 (I915_READ(IPS_CTL) & IPS_ENABLE);
9905 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9906 pipe_config->pixel_multiplier =
9907 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9909 pipe_config->pixel_multiplier = 1;
9915 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9917 struct drm_device *dev = crtc->dev;
9918 struct drm_i915_private *dev_priv = dev->dev_private;
9919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920 uint32_t cntl = 0, size = 0;
9923 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9924 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9925 unsigned int stride = roundup_pow_of_two(width) * 4;
9929 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9940 cntl |= CURSOR_ENABLE |
9941 CURSOR_GAMMA_ENABLE |
9942 CURSOR_FORMAT_ARGB |
9943 CURSOR_STRIDE(stride);
9945 size = (height << 12) | width;
9948 if (intel_crtc->cursor_cntl != 0 &&
9949 (intel_crtc->cursor_base != base ||
9950 intel_crtc->cursor_size != size ||
9951 intel_crtc->cursor_cntl != cntl)) {
9952 /* On these chipsets we can only modify the base/size/stride
9953 * whilst the cursor is disabled.
9955 I915_WRITE(_CURACNTR, 0);
9956 POSTING_READ(_CURACNTR);
9957 intel_crtc->cursor_cntl = 0;
9960 if (intel_crtc->cursor_base != base) {
9961 I915_WRITE(_CURABASE, base);
9962 intel_crtc->cursor_base = base;
9965 if (intel_crtc->cursor_size != size) {
9966 I915_WRITE(CURSIZE, size);
9967 intel_crtc->cursor_size = size;
9970 if (intel_crtc->cursor_cntl != cntl) {
9971 I915_WRITE(_CURACNTR, cntl);
9972 POSTING_READ(_CURACNTR);
9973 intel_crtc->cursor_cntl = cntl;
9977 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9979 struct drm_device *dev = crtc->dev;
9980 struct drm_i915_private *dev_priv = dev->dev_private;
9981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9982 int pipe = intel_crtc->pipe;
9987 cntl = MCURSOR_GAMMA_ENABLE;
9988 switch (intel_crtc->base.cursor->state->crtc_w) {
9990 cntl |= CURSOR_MODE_64_ARGB_AX;
9993 cntl |= CURSOR_MODE_128_ARGB_AX;
9996 cntl |= CURSOR_MODE_256_ARGB_AX;
9999 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10002 cntl |= pipe << 28; /* Connect to correct pipe */
10004 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10005 cntl |= CURSOR_PIPE_CSC_ENABLE;
10008 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10009 cntl |= CURSOR_ROTATE_180;
10011 if (intel_crtc->cursor_cntl != cntl) {
10012 I915_WRITE(CURCNTR(pipe), cntl);
10013 POSTING_READ(CURCNTR(pipe));
10014 intel_crtc->cursor_cntl = cntl;
10017 /* and commit changes on next vblank */
10018 I915_WRITE(CURBASE(pipe), base);
10019 POSTING_READ(CURBASE(pipe));
10021 intel_crtc->cursor_base = base;
10024 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10025 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10028 struct drm_device *dev = crtc->dev;
10029 struct drm_i915_private *dev_priv = dev->dev_private;
10030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10031 int pipe = intel_crtc->pipe;
10032 int x = crtc->cursor_x;
10033 int y = crtc->cursor_y;
10034 u32 base = 0, pos = 0;
10037 base = intel_crtc->cursor_addr;
10039 if (x >= intel_crtc->config->pipe_src_w)
10042 if (y >= intel_crtc->config->pipe_src_h)
10046 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10049 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10052 pos |= x << CURSOR_X_SHIFT;
10055 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10058 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10061 pos |= y << CURSOR_Y_SHIFT;
10063 if (base == 0 && intel_crtc->cursor_base == 0)
10066 I915_WRITE(CURPOS(pipe), pos);
10068 /* ILK+ do this automagically */
10069 if (HAS_GMCH_DISPLAY(dev) &&
10070 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10071 base += (intel_crtc->base.cursor->state->crtc_h *
10072 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10075 if (IS_845G(dev) || IS_I865G(dev))
10076 i845_update_cursor(crtc, base);
10078 i9xx_update_cursor(crtc, base);
10081 static bool cursor_size_ok(struct drm_device *dev,
10082 uint32_t width, uint32_t height)
10084 if (width == 0 || height == 0)
10088 * 845g/865g are special in that they are only limited by
10089 * the width of their cursors, the height is arbitrary up to
10090 * the precision of the register. Everything else requires
10091 * square cursors, limited to a few power-of-two sizes.
10093 if (IS_845G(dev) || IS_I865G(dev)) {
10094 if ((width & 63) != 0)
10097 if (width > (IS_845G(dev) ? 64 : 512))
10103 switch (width | height) {
10118 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10119 u16 *blue, uint32_t start, uint32_t size)
10121 int end = (start + size > 256) ? 256 : start + size, i;
10122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10124 for (i = start; i < end; i++) {
10125 intel_crtc->lut_r[i] = red[i] >> 8;
10126 intel_crtc->lut_g[i] = green[i] >> 8;
10127 intel_crtc->lut_b[i] = blue[i] >> 8;
10130 intel_crtc_load_lut(crtc);
10133 /* VESA 640x480x72Hz mode to set on the pipe */
10134 static struct drm_display_mode load_detect_mode = {
10135 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10136 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10139 struct drm_framebuffer *
10140 __intel_framebuffer_create(struct drm_device *dev,
10141 struct drm_mode_fb_cmd2 *mode_cmd,
10142 struct drm_i915_gem_object *obj)
10144 struct intel_framebuffer *intel_fb;
10147 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10149 drm_gem_object_unreference(&obj->base);
10150 return ERR_PTR(-ENOMEM);
10153 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10157 return &intel_fb->base;
10159 drm_gem_object_unreference(&obj->base);
10162 return ERR_PTR(ret);
10165 static struct drm_framebuffer *
10166 intel_framebuffer_create(struct drm_device *dev,
10167 struct drm_mode_fb_cmd2 *mode_cmd,
10168 struct drm_i915_gem_object *obj)
10170 struct drm_framebuffer *fb;
10173 ret = i915_mutex_lock_interruptible(dev);
10175 return ERR_PTR(ret);
10176 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10177 mutex_unlock(&dev->struct_mutex);
10183 intel_framebuffer_pitch_for_width(int width, int bpp)
10185 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10186 return ALIGN(pitch, 64);
10190 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10192 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10193 return PAGE_ALIGN(pitch * mode->vdisplay);
10196 static struct drm_framebuffer *
10197 intel_framebuffer_create_for_mode(struct drm_device *dev,
10198 struct drm_display_mode *mode,
10199 int depth, int bpp)
10201 struct drm_i915_gem_object *obj;
10202 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10204 obj = i915_gem_alloc_object(dev,
10205 intel_framebuffer_size_for_mode(mode, bpp));
10207 return ERR_PTR(-ENOMEM);
10209 mode_cmd.width = mode->hdisplay;
10210 mode_cmd.height = mode->vdisplay;
10211 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10213 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10215 return intel_framebuffer_create(dev, &mode_cmd, obj);
10218 static struct drm_framebuffer *
10219 mode_fits_in_fbdev(struct drm_device *dev,
10220 struct drm_display_mode *mode)
10222 #ifdef CONFIG_DRM_I915_FBDEV
10223 struct drm_i915_private *dev_priv = dev->dev_private;
10224 struct drm_i915_gem_object *obj;
10225 struct drm_framebuffer *fb;
10227 if (!dev_priv->fbdev)
10230 if (!dev_priv->fbdev->fb)
10233 obj = dev_priv->fbdev->fb->obj;
10236 fb = &dev_priv->fbdev->fb->base;
10237 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10238 fb->bits_per_pixel))
10241 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10250 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10251 struct drm_crtc *crtc,
10252 struct drm_display_mode *mode,
10253 struct drm_framebuffer *fb,
10256 struct drm_plane_state *plane_state;
10257 int hdisplay, vdisplay;
10260 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10261 if (IS_ERR(plane_state))
10262 return PTR_ERR(plane_state);
10265 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10267 hdisplay = vdisplay = 0;
10269 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10272 drm_atomic_set_fb_for_plane(plane_state, fb);
10273 plane_state->crtc_x = 0;
10274 plane_state->crtc_y = 0;
10275 plane_state->crtc_w = hdisplay;
10276 plane_state->crtc_h = vdisplay;
10277 plane_state->src_x = x << 16;
10278 plane_state->src_y = y << 16;
10279 plane_state->src_w = hdisplay << 16;
10280 plane_state->src_h = vdisplay << 16;
10285 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10286 struct drm_display_mode *mode,
10287 struct intel_load_detect_pipe *old,
10288 struct drm_modeset_acquire_ctx *ctx)
10290 struct intel_crtc *intel_crtc;
10291 struct intel_encoder *intel_encoder =
10292 intel_attached_encoder(connector);
10293 struct drm_crtc *possible_crtc;
10294 struct drm_encoder *encoder = &intel_encoder->base;
10295 struct drm_crtc *crtc = NULL;
10296 struct drm_device *dev = encoder->dev;
10297 struct drm_framebuffer *fb;
10298 struct drm_mode_config *config = &dev->mode_config;
10299 struct drm_atomic_state *state = NULL;
10300 struct drm_connector_state *connector_state;
10301 struct intel_crtc_state *crtc_state;
10304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10305 connector->base.id, connector->name,
10306 encoder->base.id, encoder->name);
10309 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10314 * Algorithm gets a little messy:
10316 * - if the connector already has an assigned crtc, use it (but make
10317 * sure it's on first)
10319 * - try to find the first unused crtc that can drive this connector,
10320 * and use that if we find one
10323 /* See if we already have a CRTC for this connector */
10324 if (encoder->crtc) {
10325 crtc = encoder->crtc;
10327 ret = drm_modeset_lock(&crtc->mutex, ctx);
10330 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10334 old->dpms_mode = connector->dpms;
10335 old->load_detect_temp = false;
10337 /* Make sure the crtc and connector are running */
10338 if (connector->dpms != DRM_MODE_DPMS_ON)
10339 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10344 /* Find an unused one (if possible) */
10345 for_each_crtc(dev, possible_crtc) {
10347 if (!(encoder->possible_crtcs & (1 << i)))
10349 if (possible_crtc->state->enable)
10352 crtc = possible_crtc;
10357 * If we didn't find an unused CRTC, don't use any.
10360 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10364 ret = drm_modeset_lock(&crtc->mutex, ctx);
10367 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10371 intel_crtc = to_intel_crtc(crtc);
10372 old->dpms_mode = connector->dpms;
10373 old->load_detect_temp = true;
10374 old->release_fb = NULL;
10376 state = drm_atomic_state_alloc(dev);
10380 state->acquire_ctx = ctx;
10382 connector_state = drm_atomic_get_connector_state(state, connector);
10383 if (IS_ERR(connector_state)) {
10384 ret = PTR_ERR(connector_state);
10388 connector_state->crtc = crtc;
10389 connector_state->best_encoder = &intel_encoder->base;
10391 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10392 if (IS_ERR(crtc_state)) {
10393 ret = PTR_ERR(crtc_state);
10397 crtc_state->base.active = crtc_state->base.enable = true;
10400 mode = &load_detect_mode;
10402 /* We need a framebuffer large enough to accommodate all accesses
10403 * that the plane may generate whilst we perform load detection.
10404 * We can not rely on the fbcon either being present (we get called
10405 * during its initialisation to detect all boot displays, or it may
10406 * not even exist) or that it is large enough to satisfy the
10409 fb = mode_fits_in_fbdev(dev, mode);
10411 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10412 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10413 old->release_fb = fb;
10415 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10417 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10421 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10425 drm_mode_copy(&crtc_state->base.mode, mode);
10427 if (drm_atomic_commit(state)) {
10428 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10429 if (old->release_fb)
10430 old->release_fb->funcs->destroy(old->release_fb);
10433 crtc->primary->crtc = crtc;
10435 /* let the connector get through one full cycle before testing */
10436 intel_wait_for_vblank(dev, intel_crtc->pipe);
10440 drm_atomic_state_free(state);
10443 if (ret == -EDEADLK) {
10444 drm_modeset_backoff(ctx);
10451 void intel_release_load_detect_pipe(struct drm_connector *connector,
10452 struct intel_load_detect_pipe *old,
10453 struct drm_modeset_acquire_ctx *ctx)
10455 struct drm_device *dev = connector->dev;
10456 struct intel_encoder *intel_encoder =
10457 intel_attached_encoder(connector);
10458 struct drm_encoder *encoder = &intel_encoder->base;
10459 struct drm_crtc *crtc = encoder->crtc;
10460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10461 struct drm_atomic_state *state;
10462 struct drm_connector_state *connector_state;
10463 struct intel_crtc_state *crtc_state;
10466 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10467 connector->base.id, connector->name,
10468 encoder->base.id, encoder->name);
10470 if (old->load_detect_temp) {
10471 state = drm_atomic_state_alloc(dev);
10475 state->acquire_ctx = ctx;
10477 connector_state = drm_atomic_get_connector_state(state, connector);
10478 if (IS_ERR(connector_state))
10481 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10482 if (IS_ERR(crtc_state))
10485 connector_state->best_encoder = NULL;
10486 connector_state->crtc = NULL;
10488 crtc_state->base.enable = crtc_state->base.active = false;
10490 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10495 ret = drm_atomic_commit(state);
10499 if (old->release_fb) {
10500 drm_framebuffer_unregister_private(old->release_fb);
10501 drm_framebuffer_unreference(old->release_fb);
10507 /* Switch crtc and encoder back off if necessary */
10508 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10509 connector->funcs->dpms(connector, old->dpms_mode);
10513 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10514 drm_atomic_state_free(state);
10517 static int i9xx_pll_refclk(struct drm_device *dev,
10518 const struct intel_crtc_state *pipe_config)
10520 struct drm_i915_private *dev_priv = dev->dev_private;
10521 u32 dpll = pipe_config->dpll_hw_state.dpll;
10523 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10524 return dev_priv->vbt.lvds_ssc_freq;
10525 else if (HAS_PCH_SPLIT(dev))
10527 else if (!IS_GEN2(dev))
10533 /* Returns the clock of the currently programmed mode of the given pipe. */
10534 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10535 struct intel_crtc_state *pipe_config)
10537 struct drm_device *dev = crtc->base.dev;
10538 struct drm_i915_private *dev_priv = dev->dev_private;
10539 int pipe = pipe_config->cpu_transcoder;
10540 u32 dpll = pipe_config->dpll_hw_state.dpll;
10542 intel_clock_t clock;
10544 int refclk = i9xx_pll_refclk(dev, pipe_config);
10546 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10547 fp = pipe_config->dpll_hw_state.fp0;
10549 fp = pipe_config->dpll_hw_state.fp1;
10551 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10552 if (IS_PINEVIEW(dev)) {
10553 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10554 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10556 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10557 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10560 if (!IS_GEN2(dev)) {
10561 if (IS_PINEVIEW(dev))
10562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10563 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10566 DPLL_FPA01_P1_POST_DIV_SHIFT);
10568 switch (dpll & DPLL_MODE_MASK) {
10569 case DPLLB_MODE_DAC_SERIAL:
10570 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10573 case DPLLB_MODE_LVDS:
10574 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10578 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10579 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10583 if (IS_PINEVIEW(dev))
10584 port_clock = pnv_calc_dpll_params(refclk, &clock);
10586 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10588 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10589 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10592 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10593 DPLL_FPA01_P1_POST_DIV_SHIFT);
10595 if (lvds & LVDS_CLKB_POWER_UP)
10600 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10603 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10604 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10606 if (dpll & PLL_P2_DIVIDE_BY_4)
10612 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10616 * This value includes pixel_multiplier. We will use
10617 * port_clock to compute adjusted_mode.crtc_clock in the
10618 * encoder's get_config() function.
10620 pipe_config->port_clock = port_clock;
10623 int intel_dotclock_calculate(int link_freq,
10624 const struct intel_link_m_n *m_n)
10627 * The calculation for the data clock is:
10628 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10629 * But we want to avoid losing precison if possible, so:
10630 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10632 * and the link clock is simpler:
10633 * link_clock = (m * link_clock) / n
10639 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10642 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10643 struct intel_crtc_state *pipe_config)
10645 struct drm_device *dev = crtc->base.dev;
10647 /* read out port_clock from the DPLL */
10648 i9xx_crtc_clock_get(crtc, pipe_config);
10651 * This value does not include pixel_multiplier.
10652 * We will check that port_clock and adjusted_mode.crtc_clock
10653 * agree once we know their relationship in the encoder's
10654 * get_config() function.
10656 pipe_config->base.adjusted_mode.crtc_clock =
10657 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10658 &pipe_config->fdi_m_n);
10661 /** Returns the currently programmed mode of the given pipe. */
10662 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10663 struct drm_crtc *crtc)
10665 struct drm_i915_private *dev_priv = dev->dev_private;
10666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10667 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10668 struct drm_display_mode *mode;
10669 struct intel_crtc_state pipe_config;
10670 int htot = I915_READ(HTOTAL(cpu_transcoder));
10671 int hsync = I915_READ(HSYNC(cpu_transcoder));
10672 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10673 int vsync = I915_READ(VSYNC(cpu_transcoder));
10674 enum pipe pipe = intel_crtc->pipe;
10676 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10681 * Construct a pipe_config sufficient for getting the clock info
10682 * back out of crtc_clock_get.
10684 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10685 * to use a real value here instead.
10687 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10688 pipe_config.pixel_multiplier = 1;
10689 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10690 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10691 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10692 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10694 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10695 mode->hdisplay = (htot & 0xffff) + 1;
10696 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10697 mode->hsync_start = (hsync & 0xffff) + 1;
10698 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10699 mode->vdisplay = (vtot & 0xffff) + 1;
10700 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10701 mode->vsync_start = (vsync & 0xffff) + 1;
10702 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10704 drm_mode_set_name(mode);
10709 void intel_mark_busy(struct drm_device *dev)
10711 struct drm_i915_private *dev_priv = dev->dev_private;
10713 if (dev_priv->mm.busy)
10716 intel_runtime_pm_get(dev_priv);
10717 i915_update_gfx_val(dev_priv);
10718 if (INTEL_INFO(dev)->gen >= 6)
10719 gen6_rps_busy(dev_priv);
10720 dev_priv->mm.busy = true;
10723 void intel_mark_idle(struct drm_device *dev)
10725 struct drm_i915_private *dev_priv = dev->dev_private;
10727 if (!dev_priv->mm.busy)
10730 dev_priv->mm.busy = false;
10732 if (INTEL_INFO(dev)->gen >= 6)
10733 gen6_rps_idle(dev->dev_private);
10735 intel_runtime_pm_put(dev_priv);
10738 static void intel_crtc_destroy(struct drm_crtc *crtc)
10740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10741 struct drm_device *dev = crtc->dev;
10742 struct intel_unpin_work *work;
10744 spin_lock_irq(&dev->event_lock);
10745 work = intel_crtc->unpin_work;
10746 intel_crtc->unpin_work = NULL;
10747 spin_unlock_irq(&dev->event_lock);
10750 cancel_work_sync(&work->work);
10754 drm_crtc_cleanup(crtc);
10759 static void intel_unpin_work_fn(struct work_struct *__work)
10761 struct intel_unpin_work *work =
10762 container_of(__work, struct intel_unpin_work, work);
10763 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10764 struct drm_device *dev = crtc->base.dev;
10765 struct drm_plane *primary = crtc->base.primary;
10767 mutex_lock(&dev->struct_mutex);
10768 intel_unpin_fb_obj(work->old_fb, primary->state);
10769 drm_gem_object_unreference(&work->pending_flip_obj->base);
10771 if (work->flip_queued_req)
10772 i915_gem_request_assign(&work->flip_queued_req, NULL);
10773 mutex_unlock(&dev->struct_mutex);
10775 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10776 drm_framebuffer_unreference(work->old_fb);
10778 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10779 atomic_dec(&crtc->unpin_work_count);
10784 static void do_intel_finish_page_flip(struct drm_device *dev,
10785 struct drm_crtc *crtc)
10787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10788 struct intel_unpin_work *work;
10789 unsigned long flags;
10791 /* Ignore early vblank irqs */
10792 if (intel_crtc == NULL)
10796 * This is called both by irq handlers and the reset code (to complete
10797 * lost pageflips) so needs the full irqsave spinlocks.
10799 spin_lock_irqsave(&dev->event_lock, flags);
10800 work = intel_crtc->unpin_work;
10802 /* Ensure we don't miss a work->pending update ... */
10805 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10806 spin_unlock_irqrestore(&dev->event_lock, flags);
10810 page_flip_completed(intel_crtc);
10812 spin_unlock_irqrestore(&dev->event_lock, flags);
10815 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10817 struct drm_i915_private *dev_priv = dev->dev_private;
10818 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10820 do_intel_finish_page_flip(dev, crtc);
10823 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10825 struct drm_i915_private *dev_priv = dev->dev_private;
10826 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10828 do_intel_finish_page_flip(dev, crtc);
10831 /* Is 'a' after or equal to 'b'? */
10832 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10834 return !((a - b) & 0x80000000);
10837 static bool page_flip_finished(struct intel_crtc *crtc)
10839 struct drm_device *dev = crtc->base.dev;
10840 struct drm_i915_private *dev_priv = dev->dev_private;
10842 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10843 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10847 * The relevant registers doen't exist on pre-ctg.
10848 * As the flip done interrupt doesn't trigger for mmio
10849 * flips on gmch platforms, a flip count check isn't
10850 * really needed there. But since ctg has the registers,
10851 * include it in the check anyway.
10853 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10857 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10858 * used the same base address. In that case the mmio flip might
10859 * have completed, but the CS hasn't even executed the flip yet.
10861 * A flip count check isn't enough as the CS might have updated
10862 * the base address just after start of vblank, but before we
10863 * managed to process the interrupt. This means we'd complete the
10864 * CS flip too soon.
10866 * Combining both checks should get us a good enough result. It may
10867 * still happen that the CS flip has been executed, but has not
10868 * yet actually completed. But in case the base address is the same
10869 * anyway, we don't really care.
10871 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10872 crtc->unpin_work->gtt_offset &&
10873 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10874 crtc->unpin_work->flip_count);
10877 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10879 struct drm_i915_private *dev_priv = dev->dev_private;
10880 struct intel_crtc *intel_crtc =
10881 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10882 unsigned long flags;
10886 * This is called both by irq handlers and the reset code (to complete
10887 * lost pageflips) so needs the full irqsave spinlocks.
10889 * NB: An MMIO update of the plane base pointer will also
10890 * generate a page-flip completion irq, i.e. every modeset
10891 * is also accompanied by a spurious intel_prepare_page_flip().
10893 spin_lock_irqsave(&dev->event_lock, flags);
10894 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10895 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10896 spin_unlock_irqrestore(&dev->event_lock, flags);
10899 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10901 /* Ensure that the work item is consistent when activating it ... */
10903 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10904 /* and that it is marked active as soon as the irq could fire. */
10908 static int intel_gen2_queue_flip(struct drm_device *dev,
10909 struct drm_crtc *crtc,
10910 struct drm_framebuffer *fb,
10911 struct drm_i915_gem_object *obj,
10912 struct drm_i915_gem_request *req,
10915 struct intel_engine_cs *ring = req->ring;
10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10920 ret = intel_ring_begin(req, 6);
10924 /* Can't queue multiple flips, so wait for the previous
10925 * one to finish before executing the next.
10927 if (intel_crtc->plane)
10928 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10930 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10931 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10932 intel_ring_emit(ring, MI_NOOP);
10933 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10934 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10935 intel_ring_emit(ring, fb->pitches[0]);
10936 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10937 intel_ring_emit(ring, 0); /* aux display base address, unused */
10939 intel_mark_page_flip_active(intel_crtc);
10943 static int intel_gen3_queue_flip(struct drm_device *dev,
10944 struct drm_crtc *crtc,
10945 struct drm_framebuffer *fb,
10946 struct drm_i915_gem_object *obj,
10947 struct drm_i915_gem_request *req,
10950 struct intel_engine_cs *ring = req->ring;
10951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10955 ret = intel_ring_begin(req, 6);
10959 if (intel_crtc->plane)
10960 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10962 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10963 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10964 intel_ring_emit(ring, MI_NOOP);
10965 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10966 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10967 intel_ring_emit(ring, fb->pitches[0]);
10968 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10969 intel_ring_emit(ring, MI_NOOP);
10971 intel_mark_page_flip_active(intel_crtc);
10975 static int intel_gen4_queue_flip(struct drm_device *dev,
10976 struct drm_crtc *crtc,
10977 struct drm_framebuffer *fb,
10978 struct drm_i915_gem_object *obj,
10979 struct drm_i915_gem_request *req,
10982 struct intel_engine_cs *ring = req->ring;
10983 struct drm_i915_private *dev_priv = dev->dev_private;
10984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10985 uint32_t pf, pipesrc;
10988 ret = intel_ring_begin(req, 4);
10992 /* i965+ uses the linear or tiled offsets from the
10993 * Display Registers (which do not change across a page-flip)
10994 * so we need only reprogram the base address.
10996 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10997 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10998 intel_ring_emit(ring, fb->pitches[0]);
10999 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11002 /* XXX Enabling the panel-fitter across page-flip is so far
11003 * untested on non-native modes, so ignore it for now.
11004 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11007 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11008 intel_ring_emit(ring, pf | pipesrc);
11010 intel_mark_page_flip_active(intel_crtc);
11014 static int intel_gen6_queue_flip(struct drm_device *dev,
11015 struct drm_crtc *crtc,
11016 struct drm_framebuffer *fb,
11017 struct drm_i915_gem_object *obj,
11018 struct drm_i915_gem_request *req,
11021 struct intel_engine_cs *ring = req->ring;
11022 struct drm_i915_private *dev_priv = dev->dev_private;
11023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11024 uint32_t pf, pipesrc;
11027 ret = intel_ring_begin(req, 4);
11031 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11034 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11036 /* Contrary to the suggestions in the documentation,
11037 * "Enable Panel Fitter" does not seem to be required when page
11038 * flipping with a non-native mode, and worse causes a normal
11040 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11043 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11044 intel_ring_emit(ring, pf | pipesrc);
11046 intel_mark_page_flip_active(intel_crtc);
11050 static int intel_gen7_queue_flip(struct drm_device *dev,
11051 struct drm_crtc *crtc,
11052 struct drm_framebuffer *fb,
11053 struct drm_i915_gem_object *obj,
11054 struct drm_i915_gem_request *req,
11057 struct intel_engine_cs *ring = req->ring;
11058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11059 uint32_t plane_bit = 0;
11062 switch (intel_crtc->plane) {
11064 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11067 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11070 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11073 WARN_ONCE(1, "unknown plane in flip command\n");
11078 if (ring->id == RCS) {
11081 * On Gen 8, SRM is now taking an extra dword to accommodate
11082 * 48bits addresses, and we need a NOOP for the batch size to
11090 * BSpec MI_DISPLAY_FLIP for IVB:
11091 * "The full packet must be contained within the same cache line."
11093 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11094 * cacheline, if we ever start emitting more commands before
11095 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11096 * then do the cacheline alignment, and finally emit the
11099 ret = intel_ring_cacheline_align(req);
11103 ret = intel_ring_begin(req, len);
11107 /* Unmask the flip-done completion message. Note that the bspec says that
11108 * we should do this for both the BCS and RCS, and that we must not unmask
11109 * more than one flip event at any time (or ensure that one flip message
11110 * can be sent by waiting for flip-done prior to queueing new flips).
11111 * Experimentation says that BCS works despite DERRMR masking all
11112 * flip-done completion events and that unmasking all planes at once
11113 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11114 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11116 if (ring->id == RCS) {
11117 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11118 intel_ring_emit(ring, DERRMR);
11119 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11120 DERRMR_PIPEB_PRI_FLIP_DONE |
11121 DERRMR_PIPEC_PRI_FLIP_DONE));
11123 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11124 MI_SRM_LRM_GLOBAL_GTT);
11126 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11127 MI_SRM_LRM_GLOBAL_GTT);
11128 intel_ring_emit(ring, DERRMR);
11129 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11130 if (IS_GEN8(dev)) {
11131 intel_ring_emit(ring, 0);
11132 intel_ring_emit(ring, MI_NOOP);
11136 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11137 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11138 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11139 intel_ring_emit(ring, (MI_NOOP));
11141 intel_mark_page_flip_active(intel_crtc);
11145 static bool use_mmio_flip(struct intel_engine_cs *ring,
11146 struct drm_i915_gem_object *obj)
11149 * This is not being used for older platforms, because
11150 * non-availability of flip done interrupt forces us to use
11151 * CS flips. Older platforms derive flip done using some clever
11152 * tricks involving the flip_pending status bits and vblank irqs.
11153 * So using MMIO flips there would disrupt this mechanism.
11159 if (INTEL_INFO(ring->dev)->gen < 5)
11162 if (i915.use_mmio_flip < 0)
11164 else if (i915.use_mmio_flip > 0)
11166 else if (i915.enable_execlists)
11169 return ring != i915_gem_request_get_ring(obj->last_write_req);
11172 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11174 struct drm_device *dev = intel_crtc->base.dev;
11175 struct drm_i915_private *dev_priv = dev->dev_private;
11176 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11177 const enum pipe pipe = intel_crtc->pipe;
11180 ctl = I915_READ(PLANE_CTL(pipe, 0));
11181 ctl &= ~PLANE_CTL_TILED_MASK;
11182 switch (fb->modifier[0]) {
11183 case DRM_FORMAT_MOD_NONE:
11185 case I915_FORMAT_MOD_X_TILED:
11186 ctl |= PLANE_CTL_TILED_X;
11188 case I915_FORMAT_MOD_Y_TILED:
11189 ctl |= PLANE_CTL_TILED_Y;
11191 case I915_FORMAT_MOD_Yf_TILED:
11192 ctl |= PLANE_CTL_TILED_YF;
11195 MISSING_CASE(fb->modifier[0]);
11199 * The stride is either expressed as a multiple of 64 bytes chunks for
11200 * linear buffers or in number of tiles for tiled buffers.
11202 stride = fb->pitches[0] /
11203 intel_fb_stride_alignment(dev, fb->modifier[0],
11207 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11208 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11210 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11211 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11213 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11214 POSTING_READ(PLANE_SURF(pipe, 0));
11217 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11219 struct drm_device *dev = intel_crtc->base.dev;
11220 struct drm_i915_private *dev_priv = dev->dev_private;
11221 struct intel_framebuffer *intel_fb =
11222 to_intel_framebuffer(intel_crtc->base.primary->fb);
11223 struct drm_i915_gem_object *obj = intel_fb->obj;
11227 reg = DSPCNTR(intel_crtc->plane);
11228 dspcntr = I915_READ(reg);
11230 if (obj->tiling_mode != I915_TILING_NONE)
11231 dspcntr |= DISPPLANE_TILED;
11233 dspcntr &= ~DISPPLANE_TILED;
11235 I915_WRITE(reg, dspcntr);
11237 I915_WRITE(DSPSURF(intel_crtc->plane),
11238 intel_crtc->unpin_work->gtt_offset);
11239 POSTING_READ(DSPSURF(intel_crtc->plane));
11244 * XXX: This is the temporary way to update the plane registers until we get
11245 * around to using the usual plane update functions for MMIO flips
11247 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11249 struct drm_device *dev = intel_crtc->base.dev;
11250 u32 start_vbl_count;
11252 intel_mark_page_flip_active(intel_crtc);
11254 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11256 if (INTEL_INFO(dev)->gen >= 9)
11257 skl_do_mmio_flip(intel_crtc);
11259 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11260 ilk_do_mmio_flip(intel_crtc);
11262 intel_pipe_update_end(intel_crtc, start_vbl_count);
11265 static void intel_mmio_flip_work_func(struct work_struct *work)
11267 struct intel_mmio_flip *mmio_flip =
11268 container_of(work, struct intel_mmio_flip, work);
11270 if (mmio_flip->req)
11271 WARN_ON(__i915_wait_request(mmio_flip->req,
11272 mmio_flip->crtc->reset_counter,
11274 &mmio_flip->i915->rps.mmioflips));
11276 intel_do_mmio_flip(mmio_flip->crtc);
11278 i915_gem_request_unreference__unlocked(mmio_flip->req);
11282 static int intel_queue_mmio_flip(struct drm_device *dev,
11283 struct drm_crtc *crtc,
11284 struct drm_framebuffer *fb,
11285 struct drm_i915_gem_object *obj,
11286 struct intel_engine_cs *ring,
11289 struct intel_mmio_flip *mmio_flip;
11291 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11292 if (mmio_flip == NULL)
11295 mmio_flip->i915 = to_i915(dev);
11296 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11297 mmio_flip->crtc = to_intel_crtc(crtc);
11299 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11300 schedule_work(&mmio_flip->work);
11305 static int intel_default_queue_flip(struct drm_device *dev,
11306 struct drm_crtc *crtc,
11307 struct drm_framebuffer *fb,
11308 struct drm_i915_gem_object *obj,
11309 struct drm_i915_gem_request *req,
11315 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11316 struct drm_crtc *crtc)
11318 struct drm_i915_private *dev_priv = dev->dev_private;
11319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11320 struct intel_unpin_work *work = intel_crtc->unpin_work;
11323 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11326 if (!work->enable_stall_check)
11329 if (work->flip_ready_vblank == 0) {
11330 if (work->flip_queued_req &&
11331 !i915_gem_request_completed(work->flip_queued_req, true))
11334 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11337 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11340 /* Potential stall - if we see that the flip has happened,
11341 * assume a missed interrupt. */
11342 if (INTEL_INFO(dev)->gen >= 4)
11343 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11345 addr = I915_READ(DSPADDR(intel_crtc->plane));
11347 /* There is a potential issue here with a false positive after a flip
11348 * to the same address. We could address this by checking for a
11349 * non-incrementing frame counter.
11351 return addr == work->gtt_offset;
11354 void intel_check_page_flip(struct drm_device *dev, int pipe)
11356 struct drm_i915_private *dev_priv = dev->dev_private;
11357 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11359 struct intel_unpin_work *work;
11361 WARN_ON(!in_interrupt());
11366 spin_lock(&dev->event_lock);
11367 work = intel_crtc->unpin_work;
11368 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11369 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11370 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11371 page_flip_completed(intel_crtc);
11374 if (work != NULL &&
11375 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11376 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11377 spin_unlock(&dev->event_lock);
11380 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11381 struct drm_framebuffer *fb,
11382 struct drm_pending_vblank_event *event,
11383 uint32_t page_flip_flags)
11385 struct drm_device *dev = crtc->dev;
11386 struct drm_i915_private *dev_priv = dev->dev_private;
11387 struct drm_framebuffer *old_fb = crtc->primary->fb;
11388 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11390 struct drm_plane *primary = crtc->primary;
11391 enum pipe pipe = intel_crtc->pipe;
11392 struct intel_unpin_work *work;
11393 struct intel_engine_cs *ring;
11395 struct drm_i915_gem_request *request = NULL;
11399 * drm_mode_page_flip_ioctl() should already catch this, but double
11400 * check to be safe. In the future we may enable pageflipping from
11401 * a disabled primary plane.
11403 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11406 /* Can't change pixel format via MI display flips. */
11407 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11411 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11412 * Note that pitch changes could also affect these register.
11414 if (INTEL_INFO(dev)->gen > 3 &&
11415 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11416 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11419 if (i915_terminally_wedged(&dev_priv->gpu_error))
11422 work = kzalloc(sizeof(*work), GFP_KERNEL);
11426 work->event = event;
11428 work->old_fb = old_fb;
11429 INIT_WORK(&work->work, intel_unpin_work_fn);
11431 ret = drm_crtc_vblank_get(crtc);
11435 /* We borrow the event spin lock for protecting unpin_work */
11436 spin_lock_irq(&dev->event_lock);
11437 if (intel_crtc->unpin_work) {
11438 /* Before declaring the flip queue wedged, check if
11439 * the hardware completed the operation behind our backs.
11441 if (__intel_pageflip_stall_check(dev, crtc)) {
11442 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11443 page_flip_completed(intel_crtc);
11445 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11446 spin_unlock_irq(&dev->event_lock);
11448 drm_crtc_vblank_put(crtc);
11453 intel_crtc->unpin_work = work;
11454 spin_unlock_irq(&dev->event_lock);
11456 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11457 flush_workqueue(dev_priv->wq);
11459 /* Reference the objects for the scheduled work. */
11460 drm_framebuffer_reference(work->old_fb);
11461 drm_gem_object_reference(&obj->base);
11463 crtc->primary->fb = fb;
11464 update_state_fb(crtc->primary);
11466 work->pending_flip_obj = obj;
11468 ret = i915_mutex_lock_interruptible(dev);
11472 atomic_inc(&intel_crtc->unpin_work_count);
11473 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11475 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11476 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11478 if (IS_VALLEYVIEW(dev)) {
11479 ring = &dev_priv->ring[BCS];
11480 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11481 /* vlv: DISPLAY_FLIP fails to change tiling */
11483 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11484 ring = &dev_priv->ring[BCS];
11485 } else if (INTEL_INFO(dev)->gen >= 7) {
11486 ring = i915_gem_request_get_ring(obj->last_write_req);
11487 if (ring == NULL || ring->id != RCS)
11488 ring = &dev_priv->ring[BCS];
11490 ring = &dev_priv->ring[RCS];
11493 mmio_flip = use_mmio_flip(ring, obj);
11495 /* When using CS flips, we want to emit semaphores between rings.
11496 * However, when using mmio flips we will create a task to do the
11497 * synchronisation, so all we want here is to pin the framebuffer
11498 * into the display plane and skip any waits.
11500 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11501 crtc->primary->state,
11502 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11504 goto cleanup_pending;
11506 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11507 + intel_crtc->dspaddr_offset;
11510 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11513 goto cleanup_unpin;
11515 i915_gem_request_assign(&work->flip_queued_req,
11516 obj->last_write_req);
11519 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11521 goto cleanup_unpin;
11524 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11527 goto cleanup_unpin;
11529 i915_gem_request_assign(&work->flip_queued_req, request);
11533 i915_add_request_no_flush(request);
11535 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11536 work->enable_stall_check = true;
11538 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11539 to_intel_plane(primary)->frontbuffer_bit);
11540 mutex_unlock(&dev->struct_mutex);
11542 intel_fbc_disable_crtc(intel_crtc);
11543 intel_frontbuffer_flip_prepare(dev,
11544 to_intel_plane(primary)->frontbuffer_bit);
11546 trace_i915_flip_request(intel_crtc->plane, obj);
11551 intel_unpin_fb_obj(fb, crtc->primary->state);
11554 i915_gem_request_cancel(request);
11555 atomic_dec(&intel_crtc->unpin_work_count);
11556 mutex_unlock(&dev->struct_mutex);
11558 crtc->primary->fb = old_fb;
11559 update_state_fb(crtc->primary);
11561 drm_gem_object_unreference_unlocked(&obj->base);
11562 drm_framebuffer_unreference(work->old_fb);
11564 spin_lock_irq(&dev->event_lock);
11565 intel_crtc->unpin_work = NULL;
11566 spin_unlock_irq(&dev->event_lock);
11568 drm_crtc_vblank_put(crtc);
11573 struct drm_atomic_state *state;
11574 struct drm_plane_state *plane_state;
11577 state = drm_atomic_state_alloc(dev);
11580 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11583 plane_state = drm_atomic_get_plane_state(state, primary);
11584 ret = PTR_ERR_OR_ZERO(plane_state);
11586 drm_atomic_set_fb_for_plane(plane_state, fb);
11588 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11590 ret = drm_atomic_commit(state);
11593 if (ret == -EDEADLK) {
11594 drm_modeset_backoff(state->acquire_ctx);
11595 drm_atomic_state_clear(state);
11600 drm_atomic_state_free(state);
11602 if (ret == 0 && event) {
11603 spin_lock_irq(&dev->event_lock);
11604 drm_send_vblank_event(dev, pipe, event);
11605 spin_unlock_irq(&dev->event_lock);
11613 * intel_wm_need_update - Check whether watermarks need updating
11614 * @plane: drm plane
11615 * @state: new plane state
11617 * Check current plane state versus the new one to determine whether
11618 * watermarks need to be recalculated.
11620 * Returns true or false.
11622 static bool intel_wm_need_update(struct drm_plane *plane,
11623 struct drm_plane_state *state)
11625 /* Update watermarks on tiling changes. */
11626 if (!plane->state->fb || !state->fb ||
11627 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11628 plane->state->rotation != state->rotation)
11631 if (plane->state->crtc_w != state->crtc_w)
11637 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11638 struct drm_plane_state *plane_state)
11640 struct drm_crtc *crtc = crtc_state->crtc;
11641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11642 struct drm_plane *plane = plane_state->plane;
11643 struct drm_device *dev = crtc->dev;
11644 struct drm_i915_private *dev_priv = dev->dev_private;
11645 struct intel_plane_state *old_plane_state =
11646 to_intel_plane_state(plane->state);
11647 int idx = intel_crtc->base.base.id, ret;
11648 int i = drm_plane_index(plane);
11649 bool mode_changed = needs_modeset(crtc_state);
11650 bool was_crtc_enabled = crtc->state->active;
11651 bool is_crtc_enabled = crtc_state->active;
11653 bool turn_off, turn_on, visible, was_visible;
11654 struct drm_framebuffer *fb = plane_state->fb;
11656 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11657 plane->type != DRM_PLANE_TYPE_CURSOR) {
11658 ret = skl_update_scaler_plane(
11659 to_intel_crtc_state(crtc_state),
11660 to_intel_plane_state(plane_state));
11666 * Disabling a plane is always okay; we just need to update
11667 * fb tracking in a special way since cleanup_fb() won't
11668 * get called by the plane helpers.
11670 if (old_plane_state->base.fb && !fb)
11671 intel_crtc->atomic.disabled_planes |= 1 << i;
11673 was_visible = old_plane_state->visible;
11674 visible = to_intel_plane_state(plane_state)->visible;
11676 if (!was_crtc_enabled && WARN_ON(was_visible))
11677 was_visible = false;
11679 if (!is_crtc_enabled && WARN_ON(visible))
11682 if (!was_visible && !visible)
11685 turn_off = was_visible && (!visible || mode_changed);
11686 turn_on = visible && (!was_visible || mode_changed);
11688 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11689 plane->base.id, fb ? fb->base.id : -1);
11691 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11692 plane->base.id, was_visible, visible,
11693 turn_off, turn_on, mode_changed);
11696 intel_crtc->atomic.update_wm_pre = true;
11697 /* must disable cxsr around plane enable/disable */
11698 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11699 intel_crtc->atomic.disable_cxsr = true;
11700 /* to potentially re-enable cxsr */
11701 intel_crtc->atomic.wait_vblank = true;
11702 intel_crtc->atomic.update_wm_post = true;
11704 } else if (turn_off) {
11705 intel_crtc->atomic.update_wm_post = true;
11706 /* must disable cxsr around plane enable/disable */
11707 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11708 if (is_crtc_enabled)
11709 intel_crtc->atomic.wait_vblank = true;
11710 intel_crtc->atomic.disable_cxsr = true;
11712 } else if (intel_wm_need_update(plane, plane_state)) {
11713 intel_crtc->atomic.update_wm_pre = true;
11717 intel_crtc->atomic.fb_bits |=
11718 to_intel_plane(plane)->frontbuffer_bit;
11720 switch (plane->type) {
11721 case DRM_PLANE_TYPE_PRIMARY:
11722 intel_crtc->atomic.wait_for_flips = true;
11723 intel_crtc->atomic.pre_disable_primary = turn_off;
11724 intel_crtc->atomic.post_enable_primary = turn_on;
11728 * FIXME: Actually if we will still have any other
11729 * plane enabled on the pipe we could let IPS enabled
11730 * still, but for now lets consider that when we make
11731 * primary invisible by setting DSPCNTR to 0 on
11732 * update_primary_plane function IPS needs to be
11735 intel_crtc->atomic.disable_ips = true;
11737 intel_crtc->atomic.disable_fbc = true;
11741 * FBC does not work on some platforms for rotated
11742 * planes, so disable it when rotation is not 0 and
11743 * update it when rotation is set back to 0.
11745 * FIXME: This is redundant with the fbc update done in
11746 * the primary plane enable function except that that
11747 * one is done too late. We eventually need to unify
11752 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11753 dev_priv->fbc.crtc == intel_crtc &&
11754 plane_state->rotation != BIT(DRM_ROTATE_0))
11755 intel_crtc->atomic.disable_fbc = true;
11758 * BDW signals flip done immediately if the plane
11759 * is disabled, even if the plane enable is already
11760 * armed to occur at the next vblank :(
11762 if (turn_on && IS_BROADWELL(dev))
11763 intel_crtc->atomic.wait_vblank = true;
11765 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11767 case DRM_PLANE_TYPE_CURSOR:
11769 case DRM_PLANE_TYPE_OVERLAY:
11770 if (turn_off && !mode_changed) {
11771 intel_crtc->atomic.wait_vblank = true;
11772 intel_crtc->atomic.update_sprite_watermarks |=
11779 static bool encoders_cloneable(const struct intel_encoder *a,
11780 const struct intel_encoder *b)
11782 /* masks could be asymmetric, so check both ways */
11783 return a == b || (a->cloneable & (1 << b->type) &&
11784 b->cloneable & (1 << a->type));
11787 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11788 struct intel_crtc *crtc,
11789 struct intel_encoder *encoder)
11791 struct intel_encoder *source_encoder;
11792 struct drm_connector *connector;
11793 struct drm_connector_state *connector_state;
11796 for_each_connector_in_state(state, connector, connector_state, i) {
11797 if (connector_state->crtc != &crtc->base)
11801 to_intel_encoder(connector_state->best_encoder);
11802 if (!encoders_cloneable(encoder, source_encoder))
11809 static bool check_encoder_cloning(struct drm_atomic_state *state,
11810 struct intel_crtc *crtc)
11812 struct intel_encoder *encoder;
11813 struct drm_connector *connector;
11814 struct drm_connector_state *connector_state;
11817 for_each_connector_in_state(state, connector, connector_state, i) {
11818 if (connector_state->crtc != &crtc->base)
11821 encoder = to_intel_encoder(connector_state->best_encoder);
11822 if (!check_single_encoder_cloning(state, crtc, encoder))
11829 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11830 struct drm_crtc_state *crtc_state)
11832 struct drm_device *dev = crtc->dev;
11833 struct drm_i915_private *dev_priv = dev->dev_private;
11834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11835 struct intel_crtc_state *pipe_config =
11836 to_intel_crtc_state(crtc_state);
11837 struct drm_atomic_state *state = crtc_state->state;
11838 int ret, idx = crtc->base.id;
11839 bool mode_changed = needs_modeset(crtc_state);
11841 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11842 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11846 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11847 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11848 idx, crtc->state->active, intel_crtc->active);
11850 if (mode_changed && !crtc_state->active)
11851 intel_crtc->atomic.update_wm_post = true;
11853 if (mode_changed && crtc_state->enable &&
11854 dev_priv->display.crtc_compute_clock &&
11855 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11856 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11863 if (INTEL_INFO(dev)->gen >= 9) {
11865 ret = skl_update_scaler_crtc(pipe_config);
11868 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11875 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11876 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11877 .load_lut = intel_crtc_load_lut,
11878 .atomic_begin = intel_begin_crtc_commit,
11879 .atomic_flush = intel_finish_crtc_commit,
11880 .atomic_check = intel_crtc_atomic_check,
11883 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11885 struct intel_connector *connector;
11887 for_each_intel_connector(dev, connector) {
11888 if (connector->base.encoder) {
11889 connector->base.state->best_encoder =
11890 connector->base.encoder;
11891 connector->base.state->crtc =
11892 connector->base.encoder->crtc;
11894 connector->base.state->best_encoder = NULL;
11895 connector->base.state->crtc = NULL;
11901 connected_sink_compute_bpp(struct intel_connector *connector,
11902 struct intel_crtc_state *pipe_config)
11904 int bpp = pipe_config->pipe_bpp;
11906 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11907 connector->base.base.id,
11908 connector->base.name);
11910 /* Don't use an invalid EDID bpc value */
11911 if (connector->base.display_info.bpc &&
11912 connector->base.display_info.bpc * 3 < bpp) {
11913 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11914 bpp, connector->base.display_info.bpc*3);
11915 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11918 /* Clamp bpp to 8 on screens without EDID 1.4 */
11919 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11920 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11922 pipe_config->pipe_bpp = 24;
11927 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11928 struct intel_crtc_state *pipe_config)
11930 struct drm_device *dev = crtc->base.dev;
11931 struct drm_atomic_state *state;
11932 struct drm_connector *connector;
11933 struct drm_connector_state *connector_state;
11936 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11938 else if (INTEL_INFO(dev)->gen >= 5)
11944 pipe_config->pipe_bpp = bpp;
11946 state = pipe_config->base.state;
11948 /* Clamp display bpp to EDID value */
11949 for_each_connector_in_state(state, connector, connector_state, i) {
11950 if (connector_state->crtc != &crtc->base)
11953 connected_sink_compute_bpp(to_intel_connector(connector),
11960 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11962 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11963 "type: 0x%x flags: 0x%x\n",
11965 mode->crtc_hdisplay, mode->crtc_hsync_start,
11966 mode->crtc_hsync_end, mode->crtc_htotal,
11967 mode->crtc_vdisplay, mode->crtc_vsync_start,
11968 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11971 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11972 struct intel_crtc_state *pipe_config,
11973 const char *context)
11975 struct drm_device *dev = crtc->base.dev;
11976 struct drm_plane *plane;
11977 struct intel_plane *intel_plane;
11978 struct intel_plane_state *state;
11979 struct drm_framebuffer *fb;
11981 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11982 context, pipe_config, pipe_name(crtc->pipe));
11984 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11985 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11986 pipe_config->pipe_bpp, pipe_config->dither);
11987 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11988 pipe_config->has_pch_encoder,
11989 pipe_config->fdi_lanes,
11990 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11991 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11992 pipe_config->fdi_m_n.tu);
11993 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11994 pipe_config->has_dp_encoder,
11995 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11996 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11997 pipe_config->dp_m_n.tu);
11999 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12000 pipe_config->has_dp_encoder,
12001 pipe_config->dp_m2_n2.gmch_m,
12002 pipe_config->dp_m2_n2.gmch_n,
12003 pipe_config->dp_m2_n2.link_m,
12004 pipe_config->dp_m2_n2.link_n,
12005 pipe_config->dp_m2_n2.tu);
12007 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12008 pipe_config->has_audio,
12009 pipe_config->has_infoframe);
12011 DRM_DEBUG_KMS("requested mode:\n");
12012 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12013 DRM_DEBUG_KMS("adjusted mode:\n");
12014 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12015 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12016 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12017 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12018 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12019 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12021 pipe_config->scaler_state.scaler_users,
12022 pipe_config->scaler_state.scaler_id);
12023 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12024 pipe_config->gmch_pfit.control,
12025 pipe_config->gmch_pfit.pgm_ratios,
12026 pipe_config->gmch_pfit.lvds_border_bits);
12027 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12028 pipe_config->pch_pfit.pos,
12029 pipe_config->pch_pfit.size,
12030 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12031 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12032 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12034 if (IS_BROXTON(dev)) {
12035 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12036 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12037 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12038 pipe_config->ddi_pll_sel,
12039 pipe_config->dpll_hw_state.ebb0,
12040 pipe_config->dpll_hw_state.ebb4,
12041 pipe_config->dpll_hw_state.pll0,
12042 pipe_config->dpll_hw_state.pll1,
12043 pipe_config->dpll_hw_state.pll2,
12044 pipe_config->dpll_hw_state.pll3,
12045 pipe_config->dpll_hw_state.pll6,
12046 pipe_config->dpll_hw_state.pll8,
12047 pipe_config->dpll_hw_state.pll9,
12048 pipe_config->dpll_hw_state.pll10,
12049 pipe_config->dpll_hw_state.pcsdw12);
12050 } else if (IS_SKYLAKE(dev)) {
12051 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12052 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12053 pipe_config->ddi_pll_sel,
12054 pipe_config->dpll_hw_state.ctrl1,
12055 pipe_config->dpll_hw_state.cfgcr1,
12056 pipe_config->dpll_hw_state.cfgcr2);
12057 } else if (HAS_DDI(dev)) {
12058 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12059 pipe_config->ddi_pll_sel,
12060 pipe_config->dpll_hw_state.wrpll);
12062 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12063 "fp0: 0x%x, fp1: 0x%x\n",
12064 pipe_config->dpll_hw_state.dpll,
12065 pipe_config->dpll_hw_state.dpll_md,
12066 pipe_config->dpll_hw_state.fp0,
12067 pipe_config->dpll_hw_state.fp1);
12070 DRM_DEBUG_KMS("planes on this crtc\n");
12071 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12072 intel_plane = to_intel_plane(plane);
12073 if (intel_plane->pipe != crtc->pipe)
12076 state = to_intel_plane_state(plane->state);
12077 fb = state->base.fb;
12079 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12080 "disabled, scaler_id = %d\n",
12081 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12082 plane->base.id, intel_plane->pipe,
12083 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12084 drm_plane_index(plane), state->scaler_id);
12088 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12089 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12090 plane->base.id, intel_plane->pipe,
12091 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12092 drm_plane_index(plane));
12093 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12094 fb->base.id, fb->width, fb->height, fb->pixel_format);
12095 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12097 state->src.x1 >> 16, state->src.y1 >> 16,
12098 drm_rect_width(&state->src) >> 16,
12099 drm_rect_height(&state->src) >> 16,
12100 state->dst.x1, state->dst.y1,
12101 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12105 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12107 struct drm_device *dev = state->dev;
12108 struct intel_encoder *encoder;
12109 struct drm_connector *connector;
12110 struct drm_connector_state *connector_state;
12111 unsigned int used_ports = 0;
12115 * Walk the connector list instead of the encoder
12116 * list to detect the problem on ddi platforms
12117 * where there's just one encoder per digital port.
12119 for_each_connector_in_state(state, connector, connector_state, i) {
12120 if (!connector_state->best_encoder)
12123 encoder = to_intel_encoder(connector_state->best_encoder);
12125 WARN_ON(!connector_state->crtc);
12127 switch (encoder->type) {
12128 unsigned int port_mask;
12129 case INTEL_OUTPUT_UNKNOWN:
12130 if (WARN_ON(!HAS_DDI(dev)))
12132 case INTEL_OUTPUT_DISPLAYPORT:
12133 case INTEL_OUTPUT_HDMI:
12134 case INTEL_OUTPUT_EDP:
12135 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12137 /* the same port mustn't appear more than once */
12138 if (used_ports & port_mask)
12141 used_ports |= port_mask;
12151 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12153 struct drm_crtc_state tmp_state;
12154 struct intel_crtc_scaler_state scaler_state;
12155 struct intel_dpll_hw_state dpll_hw_state;
12156 enum intel_dpll_id shared_dpll;
12157 uint32_t ddi_pll_sel;
12159 /* FIXME: before the switch to atomic started, a new pipe_config was
12160 * kzalloc'd. Code that depends on any field being zero should be
12161 * fixed, so that the crtc_state can be safely duplicated. For now,
12162 * only fields that are know to not cause problems are preserved. */
12164 tmp_state = crtc_state->base;
12165 scaler_state = crtc_state->scaler_state;
12166 shared_dpll = crtc_state->shared_dpll;
12167 dpll_hw_state = crtc_state->dpll_hw_state;
12168 ddi_pll_sel = crtc_state->ddi_pll_sel;
12170 memset(crtc_state, 0, sizeof *crtc_state);
12172 crtc_state->base = tmp_state;
12173 crtc_state->scaler_state = scaler_state;
12174 crtc_state->shared_dpll = shared_dpll;
12175 crtc_state->dpll_hw_state = dpll_hw_state;
12176 crtc_state->ddi_pll_sel = ddi_pll_sel;
12180 intel_modeset_pipe_config(struct drm_crtc *crtc,
12181 struct intel_crtc_state *pipe_config)
12183 struct drm_atomic_state *state = pipe_config->base.state;
12184 struct intel_encoder *encoder;
12185 struct drm_connector *connector;
12186 struct drm_connector_state *connector_state;
12187 int base_bpp, ret = -EINVAL;
12191 clear_intel_crtc_state(pipe_config);
12193 pipe_config->cpu_transcoder =
12194 (enum transcoder) to_intel_crtc(crtc)->pipe;
12197 * Sanitize sync polarity flags based on requested ones. If neither
12198 * positive or negative polarity is requested, treat this as meaning
12199 * negative polarity.
12201 if (!(pipe_config->base.adjusted_mode.flags &
12202 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12203 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12205 if (!(pipe_config->base.adjusted_mode.flags &
12206 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12207 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12209 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12210 * plane pixel format and any sink constraints into account. Returns the
12211 * source plane bpp so that dithering can be selected on mismatches
12212 * after encoders and crtc also have had their say. */
12213 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12219 * Determine the real pipe dimensions. Note that stereo modes can
12220 * increase the actual pipe size due to the frame doubling and
12221 * insertion of additional space for blanks between the frame. This
12222 * is stored in the crtc timings. We use the requested mode to do this
12223 * computation to clearly distinguish it from the adjusted mode, which
12224 * can be changed by the connectors in the below retry loop.
12226 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12227 &pipe_config->pipe_src_w,
12228 &pipe_config->pipe_src_h);
12231 /* Ensure the port clock defaults are reset when retrying. */
12232 pipe_config->port_clock = 0;
12233 pipe_config->pixel_multiplier = 1;
12235 /* Fill in default crtc timings, allow encoders to overwrite them. */
12236 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12237 CRTC_STEREO_DOUBLE);
12239 /* Pass our mode to the connectors and the CRTC to give them a chance to
12240 * adjust it according to limitations or connector properties, and also
12241 * a chance to reject the mode entirely.
12243 for_each_connector_in_state(state, connector, connector_state, i) {
12244 if (connector_state->crtc != crtc)
12247 encoder = to_intel_encoder(connector_state->best_encoder);
12249 if (!(encoder->compute_config(encoder, pipe_config))) {
12250 DRM_DEBUG_KMS("Encoder config failure\n");
12255 /* Set default port clock if not overwritten by the encoder. Needs to be
12256 * done afterwards in case the encoder adjusts the mode. */
12257 if (!pipe_config->port_clock)
12258 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12259 * pipe_config->pixel_multiplier;
12261 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12263 DRM_DEBUG_KMS("CRTC fixup failed\n");
12267 if (ret == RETRY) {
12268 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12273 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12275 goto encoder_retry;
12278 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12279 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12280 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12286 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12288 struct drm_encoder *encoder;
12289 struct drm_device *dev = crtc->dev;
12291 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12292 if (encoder->crtc == crtc)
12299 intel_modeset_update_state(struct drm_atomic_state *state)
12301 struct drm_device *dev = state->dev;
12302 struct intel_encoder *intel_encoder;
12303 struct drm_crtc *crtc;
12304 struct drm_crtc_state *crtc_state;
12305 struct drm_connector *connector;
12308 intel_shared_dpll_commit(state);
12310 for_each_intel_encoder(dev, intel_encoder) {
12311 if (!intel_encoder->base.crtc)
12314 crtc = intel_encoder->base.crtc;
12315 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12316 if (!crtc_state || !needs_modeset(crtc->state))
12319 intel_encoder->connectors_active = false;
12322 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12324 /* Double check state. */
12325 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12326 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12328 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12330 /* Update hwmode for vblank functions */
12331 if (crtc->state->active)
12332 crtc->hwmode = crtc->state->adjusted_mode;
12334 crtc->hwmode.crtc_clock = 0;
12337 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12338 if (!connector->encoder || !connector->encoder->crtc)
12341 crtc = connector->encoder->crtc;
12342 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12343 if (!crtc_state || !needs_modeset(crtc->state))
12346 if (crtc->state->active) {
12347 struct drm_property *dpms_property =
12348 dev->mode_config.dpms_property;
12350 connector->dpms = DRM_MODE_DPMS_ON;
12351 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12353 intel_encoder = to_intel_encoder(connector->encoder);
12354 intel_encoder->connectors_active = true;
12356 connector->dpms = DRM_MODE_DPMS_OFF;
12360 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12364 if (clock1 == clock2)
12367 if (!clock1 || !clock2)
12370 diff = abs(clock1 - clock2);
12372 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12378 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12379 list_for_each_entry((intel_crtc), \
12380 &(dev)->mode_config.crtc_list, \
12382 if (mask & (1 <<(intel_crtc)->pipe))
12386 intel_compare_m_n(unsigned int m, unsigned int n,
12387 unsigned int m2, unsigned int n2,
12390 if (m == m2 && n == n2)
12393 if (exact || !m || !n || !m2 || !n2)
12396 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12403 } else if (m < m2) {
12410 return m == m2 && n == n2;
12414 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12415 struct intel_link_m_n *m2_n2,
12418 if (m_n->tu == m2_n2->tu &&
12419 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12420 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12421 intel_compare_m_n(m_n->link_m, m_n->link_n,
12422 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12433 intel_pipe_config_compare(struct drm_device *dev,
12434 struct intel_crtc_state *current_config,
12435 struct intel_crtc_state *pipe_config,
12440 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12443 DRM_ERROR(fmt, ##__VA_ARGS__); \
12445 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12448 #define PIPE_CONF_CHECK_X(name) \
12449 if (current_config->name != pipe_config->name) { \
12450 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12451 "(expected 0x%08x, found 0x%08x)\n", \
12452 current_config->name, \
12453 pipe_config->name); \
12457 #define PIPE_CONF_CHECK_I(name) \
12458 if (current_config->name != pipe_config->name) { \
12459 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12460 "(expected %i, found %i)\n", \
12461 current_config->name, \
12462 pipe_config->name); \
12466 #define PIPE_CONF_CHECK_M_N(name) \
12467 if (!intel_compare_link_m_n(¤t_config->name, \
12468 &pipe_config->name,\
12470 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12471 "(expected tu %i gmch %i/%i link %i/%i, " \
12472 "found tu %i, gmch %i/%i link %i/%i)\n", \
12473 current_config->name.tu, \
12474 current_config->name.gmch_m, \
12475 current_config->name.gmch_n, \
12476 current_config->name.link_m, \
12477 current_config->name.link_n, \
12478 pipe_config->name.tu, \
12479 pipe_config->name.gmch_m, \
12480 pipe_config->name.gmch_n, \
12481 pipe_config->name.link_m, \
12482 pipe_config->name.link_n); \
12486 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12487 if (!intel_compare_link_m_n(¤t_config->name, \
12488 &pipe_config->name, adjust) && \
12489 !intel_compare_link_m_n(¤t_config->alt_name, \
12490 &pipe_config->name, adjust)) { \
12491 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12492 "(expected tu %i gmch %i/%i link %i/%i, " \
12493 "or tu %i gmch %i/%i link %i/%i, " \
12494 "found tu %i, gmch %i/%i link %i/%i)\n", \
12495 current_config->name.tu, \
12496 current_config->name.gmch_m, \
12497 current_config->name.gmch_n, \
12498 current_config->name.link_m, \
12499 current_config->name.link_n, \
12500 current_config->alt_name.tu, \
12501 current_config->alt_name.gmch_m, \
12502 current_config->alt_name.gmch_n, \
12503 current_config->alt_name.link_m, \
12504 current_config->alt_name.link_n, \
12505 pipe_config->name.tu, \
12506 pipe_config->name.gmch_m, \
12507 pipe_config->name.gmch_n, \
12508 pipe_config->name.link_m, \
12509 pipe_config->name.link_n); \
12513 /* This is required for BDW+ where there is only one set of registers for
12514 * switching between high and low RR.
12515 * This macro can be used whenever a comparison has to be made between one
12516 * hw state and multiple sw state variables.
12518 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12519 if ((current_config->name != pipe_config->name) && \
12520 (current_config->alt_name != pipe_config->name)) { \
12521 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12522 "(expected %i or %i, found %i)\n", \
12523 current_config->name, \
12524 current_config->alt_name, \
12525 pipe_config->name); \
12529 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12530 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12531 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12532 "(expected %i, found %i)\n", \
12533 current_config->name & (mask), \
12534 pipe_config->name & (mask)); \
12538 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12539 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12540 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12541 "(expected %i, found %i)\n", \
12542 current_config->name, \
12543 pipe_config->name); \
12547 #define PIPE_CONF_QUIRK(quirk) \
12548 ((current_config->quirks | pipe_config->quirks) & (quirk))
12550 PIPE_CONF_CHECK_I(cpu_transcoder);
12552 PIPE_CONF_CHECK_I(has_pch_encoder);
12553 PIPE_CONF_CHECK_I(fdi_lanes);
12554 PIPE_CONF_CHECK_M_N(fdi_m_n);
12556 PIPE_CONF_CHECK_I(has_dp_encoder);
12558 if (INTEL_INFO(dev)->gen < 8) {
12559 PIPE_CONF_CHECK_M_N(dp_m_n);
12561 PIPE_CONF_CHECK_I(has_drrs);
12562 if (current_config->has_drrs)
12563 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12565 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12567 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12568 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12569 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12570 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12571 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12572 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12574 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12575 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12576 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12577 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12578 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12579 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12581 PIPE_CONF_CHECK_I(pixel_multiplier);
12582 PIPE_CONF_CHECK_I(has_hdmi_sink);
12583 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12584 IS_VALLEYVIEW(dev))
12585 PIPE_CONF_CHECK_I(limited_color_range);
12586 PIPE_CONF_CHECK_I(has_infoframe);
12588 PIPE_CONF_CHECK_I(has_audio);
12590 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12591 DRM_MODE_FLAG_INTERLACE);
12593 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12594 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12595 DRM_MODE_FLAG_PHSYNC);
12596 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12597 DRM_MODE_FLAG_NHSYNC);
12598 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12599 DRM_MODE_FLAG_PVSYNC);
12600 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12601 DRM_MODE_FLAG_NVSYNC);
12604 PIPE_CONF_CHECK_I(pipe_src_w);
12605 PIPE_CONF_CHECK_I(pipe_src_h);
12607 PIPE_CONF_CHECK_I(gmch_pfit.control);
12608 /* pfit ratios are autocomputed by the hw on gen4+ */
12609 if (INTEL_INFO(dev)->gen < 4)
12610 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12611 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12613 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12614 if (current_config->pch_pfit.enabled) {
12615 PIPE_CONF_CHECK_I(pch_pfit.pos);
12616 PIPE_CONF_CHECK_I(pch_pfit.size);
12619 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12621 /* BDW+ don't expose a synchronous way to read the state */
12622 if (IS_HASWELL(dev))
12623 PIPE_CONF_CHECK_I(ips_enabled);
12625 PIPE_CONF_CHECK_I(double_wide);
12627 PIPE_CONF_CHECK_X(ddi_pll_sel);
12629 PIPE_CONF_CHECK_I(shared_dpll);
12630 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12631 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12632 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12633 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12634 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12635 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12636 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12637 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12639 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12640 PIPE_CONF_CHECK_I(pipe_bpp);
12642 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12643 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12645 #undef PIPE_CONF_CHECK_X
12646 #undef PIPE_CONF_CHECK_I
12647 #undef PIPE_CONF_CHECK_I_ALT
12648 #undef PIPE_CONF_CHECK_FLAGS
12649 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12650 #undef PIPE_CONF_QUIRK
12651 #undef INTEL_ERR_OR_DBG_KMS
12656 static void check_wm_state(struct drm_device *dev)
12658 struct drm_i915_private *dev_priv = dev->dev_private;
12659 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12660 struct intel_crtc *intel_crtc;
12663 if (INTEL_INFO(dev)->gen < 9)
12666 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12667 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12669 for_each_intel_crtc(dev, intel_crtc) {
12670 struct skl_ddb_entry *hw_entry, *sw_entry;
12671 const enum pipe pipe = intel_crtc->pipe;
12673 if (!intel_crtc->active)
12677 for_each_plane(dev_priv, pipe, plane) {
12678 hw_entry = &hw_ddb.plane[pipe][plane];
12679 sw_entry = &sw_ddb->plane[pipe][plane];
12681 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12684 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12685 "(expected (%u,%u), found (%u,%u))\n",
12686 pipe_name(pipe), plane + 1,
12687 sw_entry->start, sw_entry->end,
12688 hw_entry->start, hw_entry->end);
12692 hw_entry = &hw_ddb.cursor[pipe];
12693 sw_entry = &sw_ddb->cursor[pipe];
12695 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12698 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12699 "(expected (%u,%u), found (%u,%u))\n",
12701 sw_entry->start, sw_entry->end,
12702 hw_entry->start, hw_entry->end);
12707 check_connector_state(struct drm_device *dev)
12709 struct intel_connector *connector;
12711 for_each_intel_connector(dev, connector) {
12712 struct drm_encoder *encoder = connector->base.encoder;
12713 struct drm_connector_state *state = connector->base.state;
12715 /* This also checks the encoder/connector hw state with the
12716 * ->get_hw_state callbacks. */
12717 intel_connector_check_state(connector);
12719 I915_STATE_WARN(state->best_encoder != encoder,
12720 "connector's staged encoder doesn't match current encoder\n");
12725 check_encoder_state(struct drm_device *dev)
12727 struct intel_encoder *encoder;
12728 struct intel_connector *connector;
12730 for_each_intel_encoder(dev, encoder) {
12731 bool enabled = false;
12732 bool active = false;
12733 enum pipe pipe, tracked_pipe;
12735 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12736 encoder->base.base.id,
12737 encoder->base.name);
12739 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12740 "encoder's active_connectors set, but no crtc\n");
12742 for_each_intel_connector(dev, connector) {
12743 if (connector->base.encoder != &encoder->base)
12746 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12749 I915_STATE_WARN(connector->base.state->crtc !=
12750 encoder->base.crtc,
12751 "connector's crtc doesn't match encoder crtc\n");
12754 * for MST connectors if we unplug the connector is gone
12755 * away but the encoder is still connected to a crtc
12756 * until a modeset happens in response to the hotplug.
12758 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12761 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12762 "encoder's enabled state mismatch "
12763 "(expected %i, found %i)\n",
12764 !!encoder->base.crtc, enabled);
12765 I915_STATE_WARN(active && !encoder->base.crtc,
12766 "active encoder with no crtc\n");
12768 I915_STATE_WARN(encoder->connectors_active != active,
12769 "encoder's computed active state doesn't match tracked active state "
12770 "(expected %i, found %i)\n", active, encoder->connectors_active);
12772 active = encoder->get_hw_state(encoder, &pipe);
12773 I915_STATE_WARN(active != encoder->connectors_active,
12774 "encoder's hw state doesn't match sw tracking "
12775 "(expected %i, found %i)\n",
12776 encoder->connectors_active, active);
12778 if (!encoder->base.crtc)
12781 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12782 I915_STATE_WARN(active && pipe != tracked_pipe,
12783 "active encoder's pipe doesn't match"
12784 "(expected %i, found %i)\n",
12785 tracked_pipe, pipe);
12791 check_crtc_state(struct drm_device *dev)
12793 struct drm_i915_private *dev_priv = dev->dev_private;
12794 struct intel_crtc *crtc;
12795 struct intel_encoder *encoder;
12796 struct intel_crtc_state pipe_config;
12798 for_each_intel_crtc(dev, crtc) {
12799 bool enabled = false;
12800 bool active = false;
12802 memset(&pipe_config, 0, sizeof(pipe_config));
12804 DRM_DEBUG_KMS("[CRTC:%d]\n",
12805 crtc->base.base.id);
12807 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12808 "active crtc, but not enabled in sw tracking\n");
12810 for_each_intel_encoder(dev, encoder) {
12811 if (encoder->base.crtc != &crtc->base)
12814 if (encoder->connectors_active)
12818 I915_STATE_WARN(active != crtc->active,
12819 "crtc's computed active state doesn't match tracked active state "
12820 "(expected %i, found %i)\n", active, crtc->active);
12821 I915_STATE_WARN(enabled != crtc->base.state->enable,
12822 "crtc's computed enabled state doesn't match tracked enabled state "
12823 "(expected %i, found %i)\n", enabled,
12824 crtc->base.state->enable);
12826 active = dev_priv->display.get_pipe_config(crtc,
12829 /* hw state is inconsistent with the pipe quirk */
12830 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12831 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12832 active = crtc->active;
12834 for_each_intel_encoder(dev, encoder) {
12836 if (encoder->base.crtc != &crtc->base)
12838 if (encoder->get_hw_state(encoder, &pipe))
12839 encoder->get_config(encoder, &pipe_config);
12842 I915_STATE_WARN(crtc->active != active,
12843 "crtc active state doesn't match with hw state "
12844 "(expected %i, found %i)\n", crtc->active, active);
12846 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12847 "transitional active state does not match atomic hw state "
12848 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12853 if (!intel_pipe_config_compare(dev, crtc->config,
12854 &pipe_config, false)) {
12855 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12856 intel_dump_pipe_config(crtc, &pipe_config,
12858 intel_dump_pipe_config(crtc, crtc->config,
12865 check_shared_dpll_state(struct drm_device *dev)
12867 struct drm_i915_private *dev_priv = dev->dev_private;
12868 struct intel_crtc *crtc;
12869 struct intel_dpll_hw_state dpll_hw_state;
12872 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12873 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12874 int enabled_crtcs = 0, active_crtcs = 0;
12877 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12879 DRM_DEBUG_KMS("%s\n", pll->name);
12881 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12883 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12884 "more active pll users than references: %i vs %i\n",
12885 pll->active, hweight32(pll->config.crtc_mask));
12886 I915_STATE_WARN(pll->active && !pll->on,
12887 "pll in active use but not on in sw tracking\n");
12888 I915_STATE_WARN(pll->on && !pll->active,
12889 "pll in on but not on in use in sw tracking\n");
12890 I915_STATE_WARN(pll->on != active,
12891 "pll on state mismatch (expected %i, found %i)\n",
12894 for_each_intel_crtc(dev, crtc) {
12895 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12897 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12900 I915_STATE_WARN(pll->active != active_crtcs,
12901 "pll active crtcs mismatch (expected %i, found %i)\n",
12902 pll->active, active_crtcs);
12903 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12904 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12905 hweight32(pll->config.crtc_mask), enabled_crtcs);
12907 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12908 sizeof(dpll_hw_state)),
12909 "pll hw state mismatch\n");
12914 intel_modeset_check_state(struct drm_device *dev)
12916 check_wm_state(dev);
12917 check_connector_state(dev);
12918 check_encoder_state(dev);
12919 check_crtc_state(dev);
12920 check_shared_dpll_state(dev);
12923 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12927 * FDI already provided one idea for the dotclock.
12928 * Yell if the encoder disagrees.
12930 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12931 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12932 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12935 static void update_scanline_offset(struct intel_crtc *crtc)
12937 struct drm_device *dev = crtc->base.dev;
12940 * The scanline counter increments at the leading edge of hsync.
12942 * On most platforms it starts counting from vtotal-1 on the
12943 * first active line. That means the scanline counter value is
12944 * always one less than what we would expect. Ie. just after
12945 * start of vblank, which also occurs at start of hsync (on the
12946 * last active line), the scanline counter will read vblank_start-1.
12948 * On gen2 the scanline counter starts counting from 1 instead
12949 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12950 * to keep the value positive), instead of adding one.
12952 * On HSW+ the behaviour of the scanline counter depends on the output
12953 * type. For DP ports it behaves like most other platforms, but on HDMI
12954 * there's an extra 1 line difference. So we need to add two instead of
12955 * one to the value.
12957 if (IS_GEN2(dev)) {
12958 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12961 vtotal = mode->crtc_vtotal;
12962 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12965 crtc->scanline_offset = vtotal - 1;
12966 } else if (HAS_DDI(dev) &&
12967 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12968 crtc->scanline_offset = 2;
12970 crtc->scanline_offset = 1;
12973 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12975 struct drm_device *dev = state->dev;
12976 struct drm_i915_private *dev_priv = to_i915(dev);
12977 struct intel_shared_dpll_config *shared_dpll = NULL;
12978 struct intel_crtc *intel_crtc;
12979 struct intel_crtc_state *intel_crtc_state;
12980 struct drm_crtc *crtc;
12981 struct drm_crtc_state *crtc_state;
12984 if (!dev_priv->display.crtc_compute_clock)
12987 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12990 intel_crtc = to_intel_crtc(crtc);
12991 intel_crtc_state = to_intel_crtc_state(crtc_state);
12992 dpll = intel_crtc_state->shared_dpll;
12994 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12997 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13000 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13002 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13007 * This implements the workaround described in the "notes" section of the mode
13008 * set sequence documentation. When going from no pipes or single pipe to
13009 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13010 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13012 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13014 struct drm_crtc_state *crtc_state;
13015 struct intel_crtc *intel_crtc;
13016 struct drm_crtc *crtc;
13017 struct intel_crtc_state *first_crtc_state = NULL;
13018 struct intel_crtc_state *other_crtc_state = NULL;
13019 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13022 /* look at all crtc's that are going to be enabled in during modeset */
13023 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13024 intel_crtc = to_intel_crtc(crtc);
13026 if (!crtc_state->active || !needs_modeset(crtc_state))
13029 if (first_crtc_state) {
13030 other_crtc_state = to_intel_crtc_state(crtc_state);
13033 first_crtc_state = to_intel_crtc_state(crtc_state);
13034 first_pipe = intel_crtc->pipe;
13038 /* No workaround needed? */
13039 if (!first_crtc_state)
13042 /* w/a possibly needed, check how many crtc's are already enabled. */
13043 for_each_intel_crtc(state->dev, intel_crtc) {
13044 struct intel_crtc_state *pipe_config;
13046 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13047 if (IS_ERR(pipe_config))
13048 return PTR_ERR(pipe_config);
13050 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13052 if (!pipe_config->base.active ||
13053 needs_modeset(&pipe_config->base))
13056 /* 2 or more enabled crtcs means no need for w/a */
13057 if (enabled_pipe != INVALID_PIPE)
13060 enabled_pipe = intel_crtc->pipe;
13063 if (enabled_pipe != INVALID_PIPE)
13064 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13065 else if (other_crtc_state)
13066 other_crtc_state->hsw_workaround_pipe = first_pipe;
13071 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13073 struct drm_crtc *crtc;
13074 struct drm_crtc_state *crtc_state;
13077 /* add all active pipes to the state */
13078 for_each_crtc(state->dev, crtc) {
13079 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13080 if (IS_ERR(crtc_state))
13081 return PTR_ERR(crtc_state);
13083 if (!crtc_state->active || needs_modeset(crtc_state))
13086 crtc_state->mode_changed = true;
13088 ret = drm_atomic_add_affected_connectors(state, crtc);
13092 ret = drm_atomic_add_affected_planes(state, crtc);
13101 static int intel_modeset_checks(struct drm_atomic_state *state)
13103 struct drm_device *dev = state->dev;
13104 struct drm_i915_private *dev_priv = dev->dev_private;
13107 if (!check_digital_port_conflicts(state)) {
13108 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13113 * See if the config requires any additional preparation, e.g.
13114 * to adjust global state with pipes off. We need to do this
13115 * here so we can get the modeset_pipe updated config for the new
13116 * mode set on this crtc. For other crtcs we need to use the
13117 * adjusted_mode bits in the crtc directly.
13119 if (dev_priv->display.modeset_calc_cdclk) {
13120 unsigned int cdclk;
13122 ret = dev_priv->display.modeset_calc_cdclk(state);
13124 cdclk = to_intel_atomic_state(state)->cdclk;
13125 if (!ret && cdclk != dev_priv->cdclk_freq)
13126 ret = intel_modeset_all_pipes(state);
13131 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13133 intel_modeset_clear_plls(state);
13135 if (IS_HASWELL(dev))
13136 return haswell_mode_set_planes_workaround(state);
13142 * intel_atomic_check - validate state object
13144 * @state: state to validate
13146 static int intel_atomic_check(struct drm_device *dev,
13147 struct drm_atomic_state *state)
13149 struct drm_crtc *crtc;
13150 struct drm_crtc_state *crtc_state;
13152 bool any_ms = false;
13154 ret = drm_atomic_helper_check_modeset(dev, state);
13158 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13159 struct intel_crtc_state *pipe_config =
13160 to_intel_crtc_state(crtc_state);
13162 /* Catch I915_MODE_FLAG_INHERITED */
13163 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13164 crtc_state->mode_changed = true;
13166 if (!crtc_state->enable) {
13167 if (needs_modeset(crtc_state))
13172 if (!needs_modeset(crtc_state))
13175 /* FIXME: For only active_changed we shouldn't need to do any
13176 * state recomputation at all. */
13178 ret = drm_atomic_add_affected_connectors(state, crtc);
13182 ret = intel_modeset_pipe_config(crtc, pipe_config);
13186 if (i915.fastboot &&
13187 intel_pipe_config_compare(state->dev,
13188 to_intel_crtc_state(crtc->state),
13189 pipe_config, true)) {
13190 crtc_state->mode_changed = false;
13193 if (needs_modeset(crtc_state)) {
13196 ret = drm_atomic_add_affected_planes(state, crtc);
13201 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13202 needs_modeset(crtc_state) ?
13203 "[modeset]" : "[fastset]");
13207 ret = intel_modeset_checks(state);
13212 to_intel_atomic_state(state)->cdclk =
13213 to_i915(state->dev)->cdclk_freq;
13215 return drm_atomic_helper_check_planes(state->dev, state);
13219 * intel_atomic_commit - commit validated state object
13221 * @state: the top-level driver state object
13222 * @async: asynchronous commit
13224 * This function commits a top-level state object that has been validated
13225 * with drm_atomic_helper_check().
13227 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13228 * we can only handle plane-related operations and do not yet support
13229 * asynchronous commit.
13232 * Zero for success or -errno.
13234 static int intel_atomic_commit(struct drm_device *dev,
13235 struct drm_atomic_state *state,
13238 struct drm_i915_private *dev_priv = dev->dev_private;
13239 struct drm_crtc *crtc;
13240 struct drm_crtc_state *crtc_state;
13243 bool any_ms = false;
13246 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13250 ret = drm_atomic_helper_prepare_planes(dev, state);
13254 drm_atomic_helper_swap_state(dev, state);
13256 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13259 if (!needs_modeset(crtc->state))
13263 intel_pre_plane_update(intel_crtc);
13265 if (crtc_state->active) {
13266 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13267 dev_priv->display.crtc_disable(crtc);
13268 intel_crtc->active = false;
13269 intel_disable_shared_dpll(intel_crtc);
13273 /* Only after disabling all output pipelines that will be changed can we
13274 * update the the output configuration. */
13275 intel_modeset_update_state(state);
13277 /* The state has been swaped above, so state actually contains the
13278 * old state now. */
13280 modeset_update_crtc_power_domains(state);
13282 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13283 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13285 bool modeset = needs_modeset(crtc->state);
13287 if (modeset && crtc->state->active) {
13288 update_scanline_offset(to_intel_crtc(crtc));
13289 dev_priv->display.crtc_enable(crtc);
13293 intel_pre_plane_update(intel_crtc);
13295 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13296 intel_post_plane_update(intel_crtc);
13299 /* FIXME: add subpixel order */
13301 drm_atomic_helper_wait_for_vblanks(dev, state);
13302 drm_atomic_helper_cleanup_planes(dev, state);
13303 drm_atomic_state_free(state);
13306 intel_modeset_check_state(dev);
13311 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13313 struct drm_device *dev = crtc->dev;
13314 struct drm_atomic_state *state;
13315 struct drm_crtc_state *crtc_state;
13318 state = drm_atomic_state_alloc(dev);
13320 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13325 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13328 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13329 ret = PTR_ERR_OR_ZERO(crtc_state);
13331 if (!crtc_state->active)
13334 crtc_state->mode_changed = true;
13335 ret = drm_atomic_commit(state);
13338 if (ret == -EDEADLK) {
13339 drm_atomic_state_clear(state);
13340 drm_modeset_backoff(state->acquire_ctx);
13346 drm_atomic_state_free(state);
13349 #undef for_each_intel_crtc_masked
13351 static const struct drm_crtc_funcs intel_crtc_funcs = {
13352 .gamma_set = intel_crtc_gamma_set,
13353 .set_config = drm_atomic_helper_set_config,
13354 .destroy = intel_crtc_destroy,
13355 .page_flip = intel_crtc_page_flip,
13356 .atomic_duplicate_state = intel_crtc_duplicate_state,
13357 .atomic_destroy_state = intel_crtc_destroy_state,
13360 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13361 struct intel_shared_dpll *pll,
13362 struct intel_dpll_hw_state *hw_state)
13366 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13369 val = I915_READ(PCH_DPLL(pll->id));
13370 hw_state->dpll = val;
13371 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13372 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13374 return val & DPLL_VCO_ENABLE;
13377 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13378 struct intel_shared_dpll *pll)
13380 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13381 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13384 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13385 struct intel_shared_dpll *pll)
13387 /* PCH refclock must be enabled first */
13388 ibx_assert_pch_refclk_enabled(dev_priv);
13390 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13392 /* Wait for the clocks to stabilize. */
13393 POSTING_READ(PCH_DPLL(pll->id));
13396 /* The pixel multiplier can only be updated once the
13397 * DPLL is enabled and the clocks are stable.
13399 * So write it again.
13401 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13402 POSTING_READ(PCH_DPLL(pll->id));
13406 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13407 struct intel_shared_dpll *pll)
13409 struct drm_device *dev = dev_priv->dev;
13410 struct intel_crtc *crtc;
13412 /* Make sure no transcoder isn't still depending on us. */
13413 for_each_intel_crtc(dev, crtc) {
13414 if (intel_crtc_to_shared_dpll(crtc) == pll)
13415 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13418 I915_WRITE(PCH_DPLL(pll->id), 0);
13419 POSTING_READ(PCH_DPLL(pll->id));
13423 static char *ibx_pch_dpll_names[] = {
13428 static void ibx_pch_dpll_init(struct drm_device *dev)
13430 struct drm_i915_private *dev_priv = dev->dev_private;
13433 dev_priv->num_shared_dpll = 2;
13435 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13436 dev_priv->shared_dplls[i].id = i;
13437 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13438 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13439 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13440 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13441 dev_priv->shared_dplls[i].get_hw_state =
13442 ibx_pch_dpll_get_hw_state;
13446 static void intel_shared_dpll_init(struct drm_device *dev)
13448 struct drm_i915_private *dev_priv = dev->dev_private;
13450 intel_update_cdclk(dev);
13453 intel_ddi_pll_init(dev);
13454 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13455 ibx_pch_dpll_init(dev);
13457 dev_priv->num_shared_dpll = 0;
13459 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13463 * intel_prepare_plane_fb - Prepare fb for usage on plane
13464 * @plane: drm plane to prepare for
13465 * @fb: framebuffer to prepare for presentation
13467 * Prepares a framebuffer for usage on a display plane. Generally this
13468 * involves pinning the underlying object and updating the frontbuffer tracking
13469 * bits. Some older platforms need special physical address handling for
13472 * Returns 0 on success, negative error code on failure.
13475 intel_prepare_plane_fb(struct drm_plane *plane,
13476 struct drm_framebuffer *fb,
13477 const struct drm_plane_state *new_state)
13479 struct drm_device *dev = plane->dev;
13480 struct intel_plane *intel_plane = to_intel_plane(plane);
13481 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13482 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13488 mutex_lock(&dev->struct_mutex);
13490 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13491 INTEL_INFO(dev)->cursor_needs_physical) {
13492 int align = IS_I830(dev) ? 16 * 1024 : 256;
13493 ret = i915_gem_object_attach_phys(obj, align);
13495 DRM_DEBUG_KMS("failed to attach phys object\n");
13497 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13501 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13503 mutex_unlock(&dev->struct_mutex);
13509 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13510 * @plane: drm plane to clean up for
13511 * @fb: old framebuffer that was on plane
13513 * Cleans up a framebuffer that has just been removed from a plane.
13516 intel_cleanup_plane_fb(struct drm_plane *plane,
13517 struct drm_framebuffer *fb,
13518 const struct drm_plane_state *old_state)
13520 struct drm_device *dev = plane->dev;
13521 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13526 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13527 !INTEL_INFO(dev)->cursor_needs_physical) {
13528 mutex_lock(&dev->struct_mutex);
13529 intel_unpin_fb_obj(fb, old_state);
13530 mutex_unlock(&dev->struct_mutex);
13535 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13538 struct drm_device *dev;
13539 struct drm_i915_private *dev_priv;
13540 int crtc_clock, cdclk;
13542 if (!intel_crtc || !crtc_state)
13543 return DRM_PLANE_HELPER_NO_SCALING;
13545 dev = intel_crtc->base.dev;
13546 dev_priv = dev->dev_private;
13547 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13548 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13550 if (!crtc_clock || !cdclk)
13551 return DRM_PLANE_HELPER_NO_SCALING;
13554 * skl max scale is lower of:
13555 * close to 3 but not 3, -1 is for that purpose
13559 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13565 intel_check_primary_plane(struct drm_plane *plane,
13566 struct intel_crtc_state *crtc_state,
13567 struct intel_plane_state *state)
13569 struct drm_crtc *crtc = state->base.crtc;
13570 struct drm_framebuffer *fb = state->base.fb;
13571 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13572 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13573 bool can_position = false;
13575 /* use scaler when colorkey is not required */
13576 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13577 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13579 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13580 can_position = true;
13583 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13584 &state->dst, &state->clip,
13585 min_scale, max_scale,
13586 can_position, true,
13591 intel_commit_primary_plane(struct drm_plane *plane,
13592 struct intel_plane_state *state)
13594 struct drm_crtc *crtc = state->base.crtc;
13595 struct drm_framebuffer *fb = state->base.fb;
13596 struct drm_device *dev = plane->dev;
13597 struct drm_i915_private *dev_priv = dev->dev_private;
13598 struct intel_crtc *intel_crtc;
13599 struct drm_rect *src = &state->src;
13601 crtc = crtc ? crtc : plane->crtc;
13602 intel_crtc = to_intel_crtc(crtc);
13605 crtc->x = src->x1 >> 16;
13606 crtc->y = src->y1 >> 16;
13608 if (!crtc->state->active)
13611 if (state->visible)
13612 /* FIXME: kill this fastboot hack */
13613 intel_update_pipe_size(intel_crtc);
13615 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13619 intel_disable_primary_plane(struct drm_plane *plane,
13620 struct drm_crtc *crtc)
13622 struct drm_device *dev = plane->dev;
13623 struct drm_i915_private *dev_priv = dev->dev_private;
13625 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13628 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13630 struct drm_device *dev = crtc->dev;
13631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13633 if (intel_crtc->atomic.update_wm_pre)
13634 intel_update_watermarks(crtc);
13636 /* Perform vblank evasion around commit operation */
13637 if (crtc->state->active)
13638 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13640 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13641 skl_detach_scalers(intel_crtc);
13644 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13648 if (crtc->state->active)
13649 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13653 * intel_plane_destroy - destroy a plane
13654 * @plane: plane to destroy
13656 * Common destruction function for all types of planes (primary, cursor,
13659 void intel_plane_destroy(struct drm_plane *plane)
13661 struct intel_plane *intel_plane = to_intel_plane(plane);
13662 drm_plane_cleanup(plane);
13663 kfree(intel_plane);
13666 const struct drm_plane_funcs intel_plane_funcs = {
13667 .update_plane = drm_atomic_helper_update_plane,
13668 .disable_plane = drm_atomic_helper_disable_plane,
13669 .destroy = intel_plane_destroy,
13670 .set_property = drm_atomic_helper_plane_set_property,
13671 .atomic_get_property = intel_plane_atomic_get_property,
13672 .atomic_set_property = intel_plane_atomic_set_property,
13673 .atomic_duplicate_state = intel_plane_duplicate_state,
13674 .atomic_destroy_state = intel_plane_destroy_state,
13678 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13681 struct intel_plane *primary;
13682 struct intel_plane_state *state;
13683 const uint32_t *intel_primary_formats;
13686 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13687 if (primary == NULL)
13690 state = intel_create_plane_state(&primary->base);
13695 primary->base.state = &state->base;
13697 primary->can_scale = false;
13698 primary->max_downscale = 1;
13699 if (INTEL_INFO(dev)->gen >= 9) {
13700 primary->can_scale = true;
13701 state->scaler_id = -1;
13703 primary->pipe = pipe;
13704 primary->plane = pipe;
13705 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13706 primary->check_plane = intel_check_primary_plane;
13707 primary->commit_plane = intel_commit_primary_plane;
13708 primary->disable_plane = intel_disable_primary_plane;
13709 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13710 primary->plane = !pipe;
13712 if (INTEL_INFO(dev)->gen >= 9) {
13713 intel_primary_formats = skl_primary_formats;
13714 num_formats = ARRAY_SIZE(skl_primary_formats);
13715 } else if (INTEL_INFO(dev)->gen >= 4) {
13716 intel_primary_formats = i965_primary_formats;
13717 num_formats = ARRAY_SIZE(i965_primary_formats);
13719 intel_primary_formats = i8xx_primary_formats;
13720 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13723 drm_universal_plane_init(dev, &primary->base, 0,
13724 &intel_plane_funcs,
13725 intel_primary_formats, num_formats,
13726 DRM_PLANE_TYPE_PRIMARY);
13728 if (INTEL_INFO(dev)->gen >= 4)
13729 intel_create_rotation_property(dev, primary);
13731 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13733 return &primary->base;
13736 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13738 if (!dev->mode_config.rotation_property) {
13739 unsigned long flags = BIT(DRM_ROTATE_0) |
13740 BIT(DRM_ROTATE_180);
13742 if (INTEL_INFO(dev)->gen >= 9)
13743 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13745 dev->mode_config.rotation_property =
13746 drm_mode_create_rotation_property(dev, flags);
13748 if (dev->mode_config.rotation_property)
13749 drm_object_attach_property(&plane->base.base,
13750 dev->mode_config.rotation_property,
13751 plane->base.state->rotation);
13755 intel_check_cursor_plane(struct drm_plane *plane,
13756 struct intel_crtc_state *crtc_state,
13757 struct intel_plane_state *state)
13759 struct drm_crtc *crtc = crtc_state->base.crtc;
13760 struct drm_framebuffer *fb = state->base.fb;
13761 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13765 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13766 &state->dst, &state->clip,
13767 DRM_PLANE_HELPER_NO_SCALING,
13768 DRM_PLANE_HELPER_NO_SCALING,
13769 true, true, &state->visible);
13773 /* if we want to turn off the cursor ignore width and height */
13777 /* Check for which cursor types we support */
13778 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13779 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13780 state->base.crtc_w, state->base.crtc_h);
13784 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13785 if (obj->base.size < stride * state->base.crtc_h) {
13786 DRM_DEBUG_KMS("buffer is too small\n");
13790 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13791 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13799 intel_disable_cursor_plane(struct drm_plane *plane,
13800 struct drm_crtc *crtc)
13802 intel_crtc_update_cursor(crtc, false);
13806 intel_commit_cursor_plane(struct drm_plane *plane,
13807 struct intel_plane_state *state)
13809 struct drm_crtc *crtc = state->base.crtc;
13810 struct drm_device *dev = plane->dev;
13811 struct intel_crtc *intel_crtc;
13812 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13815 crtc = crtc ? crtc : plane->crtc;
13816 intel_crtc = to_intel_crtc(crtc);
13818 plane->fb = state->base.fb;
13819 crtc->cursor_x = state->base.crtc_x;
13820 crtc->cursor_y = state->base.crtc_y;
13822 if (intel_crtc->cursor_bo == obj)
13827 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13828 addr = i915_gem_obj_ggtt_offset(obj);
13830 addr = obj->phys_handle->busaddr;
13832 intel_crtc->cursor_addr = addr;
13833 intel_crtc->cursor_bo = obj;
13836 if (crtc->state->active)
13837 intel_crtc_update_cursor(crtc, state->visible);
13840 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13843 struct intel_plane *cursor;
13844 struct intel_plane_state *state;
13846 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13847 if (cursor == NULL)
13850 state = intel_create_plane_state(&cursor->base);
13855 cursor->base.state = &state->base;
13857 cursor->can_scale = false;
13858 cursor->max_downscale = 1;
13859 cursor->pipe = pipe;
13860 cursor->plane = pipe;
13861 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13862 cursor->check_plane = intel_check_cursor_plane;
13863 cursor->commit_plane = intel_commit_cursor_plane;
13864 cursor->disable_plane = intel_disable_cursor_plane;
13866 drm_universal_plane_init(dev, &cursor->base, 0,
13867 &intel_plane_funcs,
13868 intel_cursor_formats,
13869 ARRAY_SIZE(intel_cursor_formats),
13870 DRM_PLANE_TYPE_CURSOR);
13872 if (INTEL_INFO(dev)->gen >= 4) {
13873 if (!dev->mode_config.rotation_property)
13874 dev->mode_config.rotation_property =
13875 drm_mode_create_rotation_property(dev,
13876 BIT(DRM_ROTATE_0) |
13877 BIT(DRM_ROTATE_180));
13878 if (dev->mode_config.rotation_property)
13879 drm_object_attach_property(&cursor->base.base,
13880 dev->mode_config.rotation_property,
13881 state->base.rotation);
13884 if (INTEL_INFO(dev)->gen >=9)
13885 state->scaler_id = -1;
13887 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13889 return &cursor->base;
13892 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13893 struct intel_crtc_state *crtc_state)
13896 struct intel_scaler *intel_scaler;
13897 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13899 for (i = 0; i < intel_crtc->num_scalers; i++) {
13900 intel_scaler = &scaler_state->scalers[i];
13901 intel_scaler->in_use = 0;
13902 intel_scaler->mode = PS_SCALER_MODE_DYN;
13905 scaler_state->scaler_id = -1;
13908 static void intel_crtc_init(struct drm_device *dev, int pipe)
13910 struct drm_i915_private *dev_priv = dev->dev_private;
13911 struct intel_crtc *intel_crtc;
13912 struct intel_crtc_state *crtc_state = NULL;
13913 struct drm_plane *primary = NULL;
13914 struct drm_plane *cursor = NULL;
13917 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13918 if (intel_crtc == NULL)
13921 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13924 intel_crtc->config = crtc_state;
13925 intel_crtc->base.state = &crtc_state->base;
13926 crtc_state->base.crtc = &intel_crtc->base;
13928 /* initialize shared scalers */
13929 if (INTEL_INFO(dev)->gen >= 9) {
13930 if (pipe == PIPE_C)
13931 intel_crtc->num_scalers = 1;
13933 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13935 skl_init_scalers(dev, intel_crtc, crtc_state);
13938 primary = intel_primary_plane_create(dev, pipe);
13942 cursor = intel_cursor_plane_create(dev, pipe);
13946 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13947 cursor, &intel_crtc_funcs);
13951 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13952 for (i = 0; i < 256; i++) {
13953 intel_crtc->lut_r[i] = i;
13954 intel_crtc->lut_g[i] = i;
13955 intel_crtc->lut_b[i] = i;
13959 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13960 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13962 intel_crtc->pipe = pipe;
13963 intel_crtc->plane = pipe;
13964 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13965 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13966 intel_crtc->plane = !pipe;
13969 intel_crtc->cursor_base = ~0;
13970 intel_crtc->cursor_cntl = ~0;
13971 intel_crtc->cursor_size = ~0;
13973 intel_crtc->wm.cxsr_allowed = true;
13975 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13976 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13977 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13978 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13980 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13982 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13987 drm_plane_cleanup(primary);
13989 drm_plane_cleanup(cursor);
13994 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13996 struct drm_encoder *encoder = connector->base.encoder;
13997 struct drm_device *dev = connector->base.dev;
13999 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14001 if (!encoder || WARN_ON(!encoder->crtc))
14002 return INVALID_PIPE;
14004 return to_intel_crtc(encoder->crtc)->pipe;
14007 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14008 struct drm_file *file)
14010 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14011 struct drm_crtc *drmmode_crtc;
14012 struct intel_crtc *crtc;
14014 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14016 if (!drmmode_crtc) {
14017 DRM_ERROR("no such CRTC id\n");
14021 crtc = to_intel_crtc(drmmode_crtc);
14022 pipe_from_crtc_id->pipe = crtc->pipe;
14027 static int intel_encoder_clones(struct intel_encoder *encoder)
14029 struct drm_device *dev = encoder->base.dev;
14030 struct intel_encoder *source_encoder;
14031 int index_mask = 0;
14034 for_each_intel_encoder(dev, source_encoder) {
14035 if (encoders_cloneable(encoder, source_encoder))
14036 index_mask |= (1 << entry);
14044 static bool has_edp_a(struct drm_device *dev)
14046 struct drm_i915_private *dev_priv = dev->dev_private;
14048 if (!IS_MOBILE(dev))
14051 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14054 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14060 static bool intel_crt_present(struct drm_device *dev)
14062 struct drm_i915_private *dev_priv = dev->dev_private;
14064 if (INTEL_INFO(dev)->gen >= 9)
14067 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14070 if (IS_CHERRYVIEW(dev))
14073 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14079 static void intel_setup_outputs(struct drm_device *dev)
14081 struct drm_i915_private *dev_priv = dev->dev_private;
14082 struct intel_encoder *encoder;
14083 bool dpd_is_edp = false;
14085 intel_lvds_init(dev);
14087 if (intel_crt_present(dev))
14088 intel_crt_init(dev);
14090 if (IS_BROXTON(dev)) {
14092 * FIXME: Broxton doesn't support port detection via the
14093 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14094 * detect the ports.
14096 intel_ddi_init(dev, PORT_A);
14097 intel_ddi_init(dev, PORT_B);
14098 intel_ddi_init(dev, PORT_C);
14099 } else if (HAS_DDI(dev)) {
14103 * Haswell uses DDI functions to detect digital outputs.
14104 * On SKL pre-D0 the strap isn't connected, so we assume
14107 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14108 /* WaIgnoreDDIAStrap: skl */
14110 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14111 intel_ddi_init(dev, PORT_A);
14113 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14115 found = I915_READ(SFUSE_STRAP);
14117 if (found & SFUSE_STRAP_DDIB_DETECTED)
14118 intel_ddi_init(dev, PORT_B);
14119 if (found & SFUSE_STRAP_DDIC_DETECTED)
14120 intel_ddi_init(dev, PORT_C);
14121 if (found & SFUSE_STRAP_DDID_DETECTED)
14122 intel_ddi_init(dev, PORT_D);
14123 } else if (HAS_PCH_SPLIT(dev)) {
14125 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14127 if (has_edp_a(dev))
14128 intel_dp_init(dev, DP_A, PORT_A);
14130 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14131 /* PCH SDVOB multiplex with HDMIB */
14132 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14134 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14135 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14136 intel_dp_init(dev, PCH_DP_B, PORT_B);
14139 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14140 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14142 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14143 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14145 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14146 intel_dp_init(dev, PCH_DP_C, PORT_C);
14148 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14149 intel_dp_init(dev, PCH_DP_D, PORT_D);
14150 } else if (IS_VALLEYVIEW(dev)) {
14152 * The DP_DETECTED bit is the latched state of the DDC
14153 * SDA pin at boot. However since eDP doesn't require DDC
14154 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14155 * eDP ports may have been muxed to an alternate function.
14156 * Thus we can't rely on the DP_DETECTED bit alone to detect
14157 * eDP ports. Consult the VBT as well as DP_DETECTED to
14158 * detect eDP ports.
14160 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14161 !intel_dp_is_edp(dev, PORT_B))
14162 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14164 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14165 intel_dp_is_edp(dev, PORT_B))
14166 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14168 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14169 !intel_dp_is_edp(dev, PORT_C))
14170 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14172 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14173 intel_dp_is_edp(dev, PORT_C))
14174 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14176 if (IS_CHERRYVIEW(dev)) {
14177 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14178 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14180 /* eDP not supported on port D, so don't check VBT */
14181 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14182 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14185 intel_dsi_init(dev);
14186 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14187 bool found = false;
14189 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14190 DRM_DEBUG_KMS("probing SDVOB\n");
14191 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14192 if (!found && IS_G4X(dev)) {
14193 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14194 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14197 if (!found && IS_G4X(dev))
14198 intel_dp_init(dev, DP_B, PORT_B);
14201 /* Before G4X SDVOC doesn't have its own detect register */
14203 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14204 DRM_DEBUG_KMS("probing SDVOC\n");
14205 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14208 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14211 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14212 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14215 intel_dp_init(dev, DP_C, PORT_C);
14219 (I915_READ(DP_D) & DP_DETECTED))
14220 intel_dp_init(dev, DP_D, PORT_D);
14221 } else if (IS_GEN2(dev))
14222 intel_dvo_init(dev);
14224 if (SUPPORTS_TV(dev))
14225 intel_tv_init(dev);
14227 intel_psr_init(dev);
14229 for_each_intel_encoder(dev, encoder) {
14230 encoder->base.possible_crtcs = encoder->crtc_mask;
14231 encoder->base.possible_clones =
14232 intel_encoder_clones(encoder);
14235 intel_init_pch_refclk(dev);
14237 drm_helper_move_panel_connectors_to_head(dev);
14240 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14242 struct drm_device *dev = fb->dev;
14243 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14245 drm_framebuffer_cleanup(fb);
14246 mutex_lock(&dev->struct_mutex);
14247 WARN_ON(!intel_fb->obj->framebuffer_references--);
14248 drm_gem_object_unreference(&intel_fb->obj->base);
14249 mutex_unlock(&dev->struct_mutex);
14253 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14254 struct drm_file *file,
14255 unsigned int *handle)
14257 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14258 struct drm_i915_gem_object *obj = intel_fb->obj;
14260 return drm_gem_handle_create(file, &obj->base, handle);
14263 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14264 struct drm_file *file,
14265 unsigned flags, unsigned color,
14266 struct drm_clip_rect *clips,
14267 unsigned num_clips)
14269 struct drm_device *dev = fb->dev;
14270 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14271 struct drm_i915_gem_object *obj = intel_fb->obj;
14273 mutex_lock(&dev->struct_mutex);
14274 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14275 mutex_unlock(&dev->struct_mutex);
14280 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14281 .destroy = intel_user_framebuffer_destroy,
14282 .create_handle = intel_user_framebuffer_create_handle,
14283 .dirty = intel_user_framebuffer_dirty,
14287 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14288 uint32_t pixel_format)
14290 u32 gen = INTEL_INFO(dev)->gen;
14293 /* "The stride in bytes must not exceed the of the size of 8K
14294 * pixels and 32K bytes."
14296 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14297 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14299 } else if (gen >= 4) {
14300 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14304 } else if (gen >= 3) {
14305 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14310 /* XXX DSPC is limited to 4k tiled */
14315 static int intel_framebuffer_init(struct drm_device *dev,
14316 struct intel_framebuffer *intel_fb,
14317 struct drm_mode_fb_cmd2 *mode_cmd,
14318 struct drm_i915_gem_object *obj)
14320 unsigned int aligned_height;
14322 u32 pitch_limit, stride_alignment;
14324 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14326 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14327 /* Enforce that fb modifier and tiling mode match, but only for
14328 * X-tiled. This is needed for FBC. */
14329 if (!!(obj->tiling_mode == I915_TILING_X) !=
14330 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14331 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14335 if (obj->tiling_mode == I915_TILING_X)
14336 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14337 else if (obj->tiling_mode == I915_TILING_Y) {
14338 DRM_DEBUG("No Y tiling for legacy addfb\n");
14343 /* Passed in modifier sanity checking. */
14344 switch (mode_cmd->modifier[0]) {
14345 case I915_FORMAT_MOD_Y_TILED:
14346 case I915_FORMAT_MOD_Yf_TILED:
14347 if (INTEL_INFO(dev)->gen < 9) {
14348 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14349 mode_cmd->modifier[0]);
14352 case DRM_FORMAT_MOD_NONE:
14353 case I915_FORMAT_MOD_X_TILED:
14356 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14357 mode_cmd->modifier[0]);
14361 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14362 mode_cmd->pixel_format);
14363 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14364 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14365 mode_cmd->pitches[0], stride_alignment);
14369 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14370 mode_cmd->pixel_format);
14371 if (mode_cmd->pitches[0] > pitch_limit) {
14372 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14373 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14374 "tiled" : "linear",
14375 mode_cmd->pitches[0], pitch_limit);
14379 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14380 mode_cmd->pitches[0] != obj->stride) {
14381 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14382 mode_cmd->pitches[0], obj->stride);
14386 /* Reject formats not supported by any plane early. */
14387 switch (mode_cmd->pixel_format) {
14388 case DRM_FORMAT_C8:
14389 case DRM_FORMAT_RGB565:
14390 case DRM_FORMAT_XRGB8888:
14391 case DRM_FORMAT_ARGB8888:
14393 case DRM_FORMAT_XRGB1555:
14394 if (INTEL_INFO(dev)->gen > 3) {
14395 DRM_DEBUG("unsupported pixel format: %s\n",
14396 drm_get_format_name(mode_cmd->pixel_format));
14400 case DRM_FORMAT_ABGR8888:
14401 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14402 DRM_DEBUG("unsupported pixel format: %s\n",
14403 drm_get_format_name(mode_cmd->pixel_format));
14407 case DRM_FORMAT_XBGR8888:
14408 case DRM_FORMAT_XRGB2101010:
14409 case DRM_FORMAT_XBGR2101010:
14410 if (INTEL_INFO(dev)->gen < 4) {
14411 DRM_DEBUG("unsupported pixel format: %s\n",
14412 drm_get_format_name(mode_cmd->pixel_format));
14416 case DRM_FORMAT_ABGR2101010:
14417 if (!IS_VALLEYVIEW(dev)) {
14418 DRM_DEBUG("unsupported pixel format: %s\n",
14419 drm_get_format_name(mode_cmd->pixel_format));
14423 case DRM_FORMAT_YUYV:
14424 case DRM_FORMAT_UYVY:
14425 case DRM_FORMAT_YVYU:
14426 case DRM_FORMAT_VYUY:
14427 if (INTEL_INFO(dev)->gen < 5) {
14428 DRM_DEBUG("unsupported pixel format: %s\n",
14429 drm_get_format_name(mode_cmd->pixel_format));
14434 DRM_DEBUG("unsupported pixel format: %s\n",
14435 drm_get_format_name(mode_cmd->pixel_format));
14439 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14440 if (mode_cmd->offsets[0] != 0)
14443 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14444 mode_cmd->pixel_format,
14445 mode_cmd->modifier[0]);
14446 /* FIXME drm helper for size checks (especially planar formats)? */
14447 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14450 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14451 intel_fb->obj = obj;
14452 intel_fb->obj->framebuffer_references++;
14454 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14456 DRM_ERROR("framebuffer init failed %d\n", ret);
14463 static struct drm_framebuffer *
14464 intel_user_framebuffer_create(struct drm_device *dev,
14465 struct drm_file *filp,
14466 struct drm_mode_fb_cmd2 *mode_cmd)
14468 struct drm_i915_gem_object *obj;
14470 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14471 mode_cmd->handles[0]));
14472 if (&obj->base == NULL)
14473 return ERR_PTR(-ENOENT);
14475 return intel_framebuffer_create(dev, mode_cmd, obj);
14478 #ifndef CONFIG_DRM_I915_FBDEV
14479 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14484 static const struct drm_mode_config_funcs intel_mode_funcs = {
14485 .fb_create = intel_user_framebuffer_create,
14486 .output_poll_changed = intel_fbdev_output_poll_changed,
14487 .atomic_check = intel_atomic_check,
14488 .atomic_commit = intel_atomic_commit,
14489 .atomic_state_alloc = intel_atomic_state_alloc,
14490 .atomic_state_clear = intel_atomic_state_clear,
14493 /* Set up chip specific display functions */
14494 static void intel_init_display(struct drm_device *dev)
14496 struct drm_i915_private *dev_priv = dev->dev_private;
14498 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14499 dev_priv->display.find_dpll = g4x_find_best_dpll;
14500 else if (IS_CHERRYVIEW(dev))
14501 dev_priv->display.find_dpll = chv_find_best_dpll;
14502 else if (IS_VALLEYVIEW(dev))
14503 dev_priv->display.find_dpll = vlv_find_best_dpll;
14504 else if (IS_PINEVIEW(dev))
14505 dev_priv->display.find_dpll = pnv_find_best_dpll;
14507 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14509 if (INTEL_INFO(dev)->gen >= 9) {
14510 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14511 dev_priv->display.get_initial_plane_config =
14512 skylake_get_initial_plane_config;
14513 dev_priv->display.crtc_compute_clock =
14514 haswell_crtc_compute_clock;
14515 dev_priv->display.crtc_enable = haswell_crtc_enable;
14516 dev_priv->display.crtc_disable = haswell_crtc_disable;
14517 dev_priv->display.update_primary_plane =
14518 skylake_update_primary_plane;
14519 } else if (HAS_DDI(dev)) {
14520 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14521 dev_priv->display.get_initial_plane_config =
14522 ironlake_get_initial_plane_config;
14523 dev_priv->display.crtc_compute_clock =
14524 haswell_crtc_compute_clock;
14525 dev_priv->display.crtc_enable = haswell_crtc_enable;
14526 dev_priv->display.crtc_disable = haswell_crtc_disable;
14527 dev_priv->display.update_primary_plane =
14528 ironlake_update_primary_plane;
14529 } else if (HAS_PCH_SPLIT(dev)) {
14530 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14531 dev_priv->display.get_initial_plane_config =
14532 ironlake_get_initial_plane_config;
14533 dev_priv->display.crtc_compute_clock =
14534 ironlake_crtc_compute_clock;
14535 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14536 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14537 dev_priv->display.update_primary_plane =
14538 ironlake_update_primary_plane;
14539 } else if (IS_VALLEYVIEW(dev)) {
14540 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14541 dev_priv->display.get_initial_plane_config =
14542 i9xx_get_initial_plane_config;
14543 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14544 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14545 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14546 dev_priv->display.update_primary_plane =
14547 i9xx_update_primary_plane;
14549 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14550 dev_priv->display.get_initial_plane_config =
14551 i9xx_get_initial_plane_config;
14552 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14553 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14554 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14555 dev_priv->display.update_primary_plane =
14556 i9xx_update_primary_plane;
14559 /* Returns the core display clock speed */
14560 if (IS_SKYLAKE(dev))
14561 dev_priv->display.get_display_clock_speed =
14562 skylake_get_display_clock_speed;
14563 else if (IS_BROXTON(dev))
14564 dev_priv->display.get_display_clock_speed =
14565 broxton_get_display_clock_speed;
14566 else if (IS_BROADWELL(dev))
14567 dev_priv->display.get_display_clock_speed =
14568 broadwell_get_display_clock_speed;
14569 else if (IS_HASWELL(dev))
14570 dev_priv->display.get_display_clock_speed =
14571 haswell_get_display_clock_speed;
14572 else if (IS_VALLEYVIEW(dev))
14573 dev_priv->display.get_display_clock_speed =
14574 valleyview_get_display_clock_speed;
14575 else if (IS_GEN5(dev))
14576 dev_priv->display.get_display_clock_speed =
14577 ilk_get_display_clock_speed;
14578 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14579 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14580 dev_priv->display.get_display_clock_speed =
14581 i945_get_display_clock_speed;
14582 else if (IS_GM45(dev))
14583 dev_priv->display.get_display_clock_speed =
14584 gm45_get_display_clock_speed;
14585 else if (IS_CRESTLINE(dev))
14586 dev_priv->display.get_display_clock_speed =
14587 i965gm_get_display_clock_speed;
14588 else if (IS_PINEVIEW(dev))
14589 dev_priv->display.get_display_clock_speed =
14590 pnv_get_display_clock_speed;
14591 else if (IS_G33(dev) || IS_G4X(dev))
14592 dev_priv->display.get_display_clock_speed =
14593 g33_get_display_clock_speed;
14594 else if (IS_I915G(dev))
14595 dev_priv->display.get_display_clock_speed =
14596 i915_get_display_clock_speed;
14597 else if (IS_I945GM(dev) || IS_845G(dev))
14598 dev_priv->display.get_display_clock_speed =
14599 i9xx_misc_get_display_clock_speed;
14600 else if (IS_PINEVIEW(dev))
14601 dev_priv->display.get_display_clock_speed =
14602 pnv_get_display_clock_speed;
14603 else if (IS_I915GM(dev))
14604 dev_priv->display.get_display_clock_speed =
14605 i915gm_get_display_clock_speed;
14606 else if (IS_I865G(dev))
14607 dev_priv->display.get_display_clock_speed =
14608 i865_get_display_clock_speed;
14609 else if (IS_I85X(dev))
14610 dev_priv->display.get_display_clock_speed =
14611 i85x_get_display_clock_speed;
14613 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14614 dev_priv->display.get_display_clock_speed =
14615 i830_get_display_clock_speed;
14618 if (IS_GEN5(dev)) {
14619 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14620 } else if (IS_GEN6(dev)) {
14621 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14622 } else if (IS_IVYBRIDGE(dev)) {
14623 /* FIXME: detect B0+ stepping and use auto training */
14624 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14625 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14626 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14627 if (IS_BROADWELL(dev)) {
14628 dev_priv->display.modeset_commit_cdclk =
14629 broadwell_modeset_commit_cdclk;
14630 dev_priv->display.modeset_calc_cdclk =
14631 broadwell_modeset_calc_cdclk;
14633 } else if (IS_VALLEYVIEW(dev)) {
14634 dev_priv->display.modeset_commit_cdclk =
14635 valleyview_modeset_commit_cdclk;
14636 dev_priv->display.modeset_calc_cdclk =
14637 valleyview_modeset_calc_cdclk;
14638 } else if (IS_BROXTON(dev)) {
14639 dev_priv->display.modeset_commit_cdclk =
14640 broxton_modeset_commit_cdclk;
14641 dev_priv->display.modeset_calc_cdclk =
14642 broxton_modeset_calc_cdclk;
14645 switch (INTEL_INFO(dev)->gen) {
14647 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14651 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14656 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14660 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14663 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14664 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14667 /* Drop through - unsupported since execlist only. */
14669 /* Default just returns -ENODEV to indicate unsupported */
14670 dev_priv->display.queue_flip = intel_default_queue_flip;
14673 intel_panel_init_backlight_funcs(dev);
14675 mutex_init(&dev_priv->pps_mutex);
14679 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14680 * resume, or other times. This quirk makes sure that's the case for
14681 * affected systems.
14683 static void quirk_pipea_force(struct drm_device *dev)
14685 struct drm_i915_private *dev_priv = dev->dev_private;
14687 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14688 DRM_INFO("applying pipe a force quirk\n");
14691 static void quirk_pipeb_force(struct drm_device *dev)
14693 struct drm_i915_private *dev_priv = dev->dev_private;
14695 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14696 DRM_INFO("applying pipe b force quirk\n");
14700 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14702 static void quirk_ssc_force_disable(struct drm_device *dev)
14704 struct drm_i915_private *dev_priv = dev->dev_private;
14705 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14706 DRM_INFO("applying lvds SSC disable quirk\n");
14710 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14713 static void quirk_invert_brightness(struct drm_device *dev)
14715 struct drm_i915_private *dev_priv = dev->dev_private;
14716 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14717 DRM_INFO("applying inverted panel brightness quirk\n");
14720 /* Some VBT's incorrectly indicate no backlight is present */
14721 static void quirk_backlight_present(struct drm_device *dev)
14723 struct drm_i915_private *dev_priv = dev->dev_private;
14724 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14725 DRM_INFO("applying backlight present quirk\n");
14728 struct intel_quirk {
14730 int subsystem_vendor;
14731 int subsystem_device;
14732 void (*hook)(struct drm_device *dev);
14735 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14736 struct intel_dmi_quirk {
14737 void (*hook)(struct drm_device *dev);
14738 const struct dmi_system_id (*dmi_id_list)[];
14741 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14743 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14747 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14749 .dmi_id_list = &(const struct dmi_system_id[]) {
14751 .callback = intel_dmi_reverse_brightness,
14752 .ident = "NCR Corporation",
14753 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14754 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14757 { } /* terminating entry */
14759 .hook = quirk_invert_brightness,
14763 static struct intel_quirk intel_quirks[] = {
14764 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14765 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14767 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14768 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14770 /* 830 needs to leave pipe A & dpll A up */
14771 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14773 /* 830 needs to leave pipe B & dpll B up */
14774 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14776 /* Lenovo U160 cannot use SSC on LVDS */
14777 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14779 /* Sony Vaio Y cannot use SSC on LVDS */
14780 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14782 /* Acer Aspire 5734Z must invert backlight brightness */
14783 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14785 /* Acer/eMachines G725 */
14786 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14788 /* Acer/eMachines e725 */
14789 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14791 /* Acer/Packard Bell NCL20 */
14792 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14794 /* Acer Aspire 4736Z */
14795 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14797 /* Acer Aspire 5336 */
14798 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14800 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14801 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14803 /* Acer C720 Chromebook (Core i3 4005U) */
14804 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14806 /* Apple Macbook 2,1 (Core 2 T7400) */
14807 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14809 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14810 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14812 /* HP Chromebook 14 (Celeron 2955U) */
14813 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14815 /* Dell Chromebook 11 */
14816 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14819 static void intel_init_quirks(struct drm_device *dev)
14821 struct pci_dev *d = dev->pdev;
14824 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14825 struct intel_quirk *q = &intel_quirks[i];
14827 if (d->device == q->device &&
14828 (d->subsystem_vendor == q->subsystem_vendor ||
14829 q->subsystem_vendor == PCI_ANY_ID) &&
14830 (d->subsystem_device == q->subsystem_device ||
14831 q->subsystem_device == PCI_ANY_ID))
14834 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14835 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14836 intel_dmi_quirks[i].hook(dev);
14840 /* Disable the VGA plane that we never use */
14841 static void i915_disable_vga(struct drm_device *dev)
14843 struct drm_i915_private *dev_priv = dev->dev_private;
14845 u32 vga_reg = i915_vgacntrl_reg(dev);
14847 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14848 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14849 outb(SR01, VGA_SR_INDEX);
14850 sr1 = inb(VGA_SR_DATA);
14851 outb(sr1 | 1<<5, VGA_SR_DATA);
14852 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14855 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14856 POSTING_READ(vga_reg);
14859 void intel_modeset_init_hw(struct drm_device *dev)
14861 intel_update_cdclk(dev);
14862 intel_prepare_ddi(dev);
14863 intel_init_clock_gating(dev);
14864 intel_enable_gt_powersave(dev);
14867 void intel_modeset_init(struct drm_device *dev)
14869 struct drm_i915_private *dev_priv = dev->dev_private;
14872 struct intel_crtc *crtc;
14874 drm_mode_config_init(dev);
14876 dev->mode_config.min_width = 0;
14877 dev->mode_config.min_height = 0;
14879 dev->mode_config.preferred_depth = 24;
14880 dev->mode_config.prefer_shadow = 1;
14882 dev->mode_config.allow_fb_modifiers = true;
14884 dev->mode_config.funcs = &intel_mode_funcs;
14886 intel_init_quirks(dev);
14888 intel_init_pm(dev);
14890 if (INTEL_INFO(dev)->num_pipes == 0)
14893 intel_init_display(dev);
14894 intel_init_audio(dev);
14896 if (IS_GEN2(dev)) {
14897 dev->mode_config.max_width = 2048;
14898 dev->mode_config.max_height = 2048;
14899 } else if (IS_GEN3(dev)) {
14900 dev->mode_config.max_width = 4096;
14901 dev->mode_config.max_height = 4096;
14903 dev->mode_config.max_width = 8192;
14904 dev->mode_config.max_height = 8192;
14907 if (IS_845G(dev) || IS_I865G(dev)) {
14908 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14909 dev->mode_config.cursor_height = 1023;
14910 } else if (IS_GEN2(dev)) {
14911 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14912 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14914 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14915 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14918 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14920 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14921 INTEL_INFO(dev)->num_pipes,
14922 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14924 for_each_pipe(dev_priv, pipe) {
14925 intel_crtc_init(dev, pipe);
14926 for_each_sprite(dev_priv, pipe, sprite) {
14927 ret = intel_plane_init(dev, pipe, sprite);
14929 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14930 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14934 intel_init_dpio(dev);
14936 intel_shared_dpll_init(dev);
14938 /* Just disable it once at startup */
14939 i915_disable_vga(dev);
14940 intel_setup_outputs(dev);
14942 /* Just in case the BIOS is doing something questionable. */
14943 intel_fbc_disable(dev_priv);
14945 drm_modeset_lock_all(dev);
14946 intel_modeset_setup_hw_state(dev);
14947 drm_modeset_unlock_all(dev);
14949 for_each_intel_crtc(dev, crtc) {
14950 struct intel_initial_plane_config plane_config = {};
14956 * Note that reserving the BIOS fb up front prevents us
14957 * from stuffing other stolen allocations like the ring
14958 * on top. This prevents some ugliness at boot time, and
14959 * can even allow for smooth boot transitions if the BIOS
14960 * fb is large enough for the active pipe configuration.
14962 dev_priv->display.get_initial_plane_config(crtc,
14966 * If the fb is shared between multiple heads, we'll
14967 * just get the first one.
14969 intel_find_initial_plane_obj(crtc, &plane_config);
14973 static void intel_enable_pipe_a(struct drm_device *dev)
14975 struct intel_connector *connector;
14976 struct drm_connector *crt = NULL;
14977 struct intel_load_detect_pipe load_detect_temp;
14978 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14980 /* We can't just switch on the pipe A, we need to set things up with a
14981 * proper mode and output configuration. As a gross hack, enable pipe A
14982 * by enabling the load detect pipe once. */
14983 for_each_intel_connector(dev, connector) {
14984 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14985 crt = &connector->base;
14993 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14994 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14998 intel_check_plane_mapping(struct intel_crtc *crtc)
15000 struct drm_device *dev = crtc->base.dev;
15001 struct drm_i915_private *dev_priv = dev->dev_private;
15004 if (INTEL_INFO(dev)->num_pipes == 1)
15007 reg = DSPCNTR(!crtc->plane);
15008 val = I915_READ(reg);
15010 if ((val & DISPLAY_PLANE_ENABLE) &&
15011 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15017 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15019 struct drm_device *dev = crtc->base.dev;
15020 struct drm_i915_private *dev_priv = dev->dev_private;
15021 struct intel_encoder *encoder;
15025 /* Clear any frame start delays used for debugging left by the BIOS */
15026 reg = PIPECONF(crtc->config->cpu_transcoder);
15027 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15029 /* restore vblank interrupts to correct state */
15030 drm_crtc_vblank_reset(&crtc->base);
15031 if (crtc->active) {
15032 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15033 update_scanline_offset(crtc);
15034 drm_crtc_vblank_on(&crtc->base);
15037 /* We need to sanitize the plane -> pipe mapping first because this will
15038 * disable the crtc (and hence change the state) if it is wrong. Note
15039 * that gen4+ has a fixed plane -> pipe mapping. */
15040 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15043 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15044 crtc->base.base.id);
15046 /* Pipe has the wrong plane attached and the plane is active.
15047 * Temporarily change the plane mapping and disable everything
15049 plane = crtc->plane;
15050 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15051 crtc->plane = !plane;
15052 intel_crtc_disable_noatomic(&crtc->base);
15053 crtc->plane = plane;
15056 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15057 crtc->pipe == PIPE_A && !crtc->active) {
15058 /* BIOS forgot to enable pipe A, this mostly happens after
15059 * resume. Force-enable the pipe to fix this, the update_dpms
15060 * call below we restore the pipe to the right state, but leave
15061 * the required bits on. */
15062 intel_enable_pipe_a(dev);
15065 /* Adjust the state of the output pipe according to whether we
15066 * have active connectors/encoders. */
15068 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15069 enable |= encoder->connectors_active;
15072 intel_crtc_disable_noatomic(&crtc->base);
15074 if (crtc->active != crtc->base.state->active) {
15076 /* This can happen either due to bugs in the get_hw_state
15077 * functions or because of calls to intel_crtc_disable_noatomic,
15078 * or because the pipe is force-enabled due to the
15080 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15081 crtc->base.base.id,
15082 crtc->base.state->enable ? "enabled" : "disabled",
15083 crtc->active ? "enabled" : "disabled");
15085 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15086 crtc->base.state->active = crtc->active;
15087 crtc->base.enabled = crtc->active;
15089 /* Because we only establish the connector -> encoder ->
15090 * crtc links if something is active, this means the
15091 * crtc is now deactivated. Break the links. connector
15092 * -> encoder links are only establish when things are
15093 * actually up, hence no need to break them. */
15094 WARN_ON(crtc->active);
15096 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15097 WARN_ON(encoder->connectors_active);
15098 encoder->base.crtc = NULL;
15102 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15104 * We start out with underrun reporting disabled to avoid races.
15105 * For correct bookkeeping mark this on active crtcs.
15107 * Also on gmch platforms we dont have any hardware bits to
15108 * disable the underrun reporting. Which means we need to start
15109 * out with underrun reporting disabled also on inactive pipes,
15110 * since otherwise we'll complain about the garbage we read when
15111 * e.g. coming up after runtime pm.
15113 * No protection against concurrent access is required - at
15114 * worst a fifo underrun happens which also sets this to false.
15116 crtc->cpu_fifo_underrun_disabled = true;
15117 crtc->pch_fifo_underrun_disabled = true;
15121 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15123 struct intel_connector *connector;
15124 struct drm_device *dev = encoder->base.dev;
15126 /* We need to check both for a crtc link (meaning that the
15127 * encoder is active and trying to read from a pipe) and the
15128 * pipe itself being active. */
15129 bool has_active_crtc = encoder->base.crtc &&
15130 to_intel_crtc(encoder->base.crtc)->active;
15132 if (encoder->connectors_active && !has_active_crtc) {
15133 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15134 encoder->base.base.id,
15135 encoder->base.name);
15137 /* Connector is active, but has no active pipe. This is
15138 * fallout from our resume register restoring. Disable
15139 * the encoder manually again. */
15140 if (encoder->base.crtc) {
15141 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15142 encoder->base.base.id,
15143 encoder->base.name);
15144 encoder->disable(encoder);
15145 if (encoder->post_disable)
15146 encoder->post_disable(encoder);
15148 encoder->base.crtc = NULL;
15149 encoder->connectors_active = false;
15151 /* Inconsistent output/port/pipe state happens presumably due to
15152 * a bug in one of the get_hw_state functions. Or someplace else
15153 * in our code, like the register restore mess on resume. Clamp
15154 * things to off as a safer default. */
15155 for_each_intel_connector(dev, connector) {
15156 if (connector->encoder != encoder)
15158 connector->base.dpms = DRM_MODE_DPMS_OFF;
15159 connector->base.encoder = NULL;
15162 /* Enabled encoders without active connectors will be fixed in
15163 * the crtc fixup. */
15166 void i915_redisable_vga_power_on(struct drm_device *dev)
15168 struct drm_i915_private *dev_priv = dev->dev_private;
15169 u32 vga_reg = i915_vgacntrl_reg(dev);
15171 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15172 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15173 i915_disable_vga(dev);
15177 void i915_redisable_vga(struct drm_device *dev)
15179 struct drm_i915_private *dev_priv = dev->dev_private;
15181 /* This function can be called both from intel_modeset_setup_hw_state or
15182 * at a very early point in our resume sequence, where the power well
15183 * structures are not yet restored. Since this function is at a very
15184 * paranoid "someone might have enabled VGA while we were not looking"
15185 * level, just check if the power well is enabled instead of trying to
15186 * follow the "don't touch the power well if we don't need it" policy
15187 * the rest of the driver uses. */
15188 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15191 i915_redisable_vga_power_on(dev);
15194 static bool primary_get_hw_state(struct intel_crtc *crtc)
15196 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15198 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15201 static void readout_plane_state(struct intel_crtc *crtc,
15202 struct intel_crtc_state *crtc_state)
15204 struct intel_plane *p;
15205 struct intel_plane_state *plane_state;
15206 bool active = crtc_state->base.active;
15208 for_each_intel_plane(crtc->base.dev, p) {
15209 if (crtc->pipe != p->pipe)
15212 plane_state = to_intel_plane_state(p->base.state);
15214 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15215 plane_state->visible = primary_get_hw_state(crtc);
15218 p->disable_plane(&p->base, &crtc->base);
15220 plane_state->visible = false;
15225 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15227 struct drm_i915_private *dev_priv = dev->dev_private;
15229 struct intel_crtc *crtc;
15230 struct intel_encoder *encoder;
15231 struct intel_connector *connector;
15234 for_each_intel_crtc(dev, crtc) {
15235 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15236 memset(crtc->config, 0, sizeof(*crtc->config));
15237 crtc->config->base.crtc = &crtc->base;
15239 crtc->active = dev_priv->display.get_pipe_config(crtc,
15242 crtc->base.state->active = crtc->active;
15243 crtc->base.enabled = crtc->active;
15245 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15246 if (crtc->base.state->active) {
15247 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15248 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15249 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15252 * The initial mode needs to be set in order to keep
15253 * the atomic core happy. It wants a valid mode if the
15254 * crtc's enabled, so we do the above call.
15256 * At this point some state updated by the connectors
15257 * in their ->detect() callback has not run yet, so
15258 * no recalculation can be done yet.
15260 * Even if we could do a recalculation and modeset
15261 * right now it would cause a double modeset if
15262 * fbdev or userspace chooses a different initial mode.
15264 * If that happens, someone indicated they wanted a
15265 * mode change, which means it's safe to do a full
15268 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15271 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15272 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15274 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15275 crtc->base.base.id,
15276 crtc->active ? "enabled" : "disabled");
15279 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15280 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15282 pll->on = pll->get_hw_state(dev_priv, pll,
15283 &pll->config.hw_state);
15285 pll->config.crtc_mask = 0;
15286 for_each_intel_crtc(dev, crtc) {
15287 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15289 pll->config.crtc_mask |= 1 << crtc->pipe;
15293 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15294 pll->name, pll->config.crtc_mask, pll->on);
15296 if (pll->config.crtc_mask)
15297 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15300 for_each_intel_encoder(dev, encoder) {
15303 if (encoder->get_hw_state(encoder, &pipe)) {
15304 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15305 encoder->base.crtc = &crtc->base;
15306 encoder->get_config(encoder, crtc->config);
15308 encoder->base.crtc = NULL;
15311 encoder->connectors_active = false;
15312 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15313 encoder->base.base.id,
15314 encoder->base.name,
15315 encoder->base.crtc ? "enabled" : "disabled",
15319 for_each_intel_connector(dev, connector) {
15320 if (connector->get_hw_state(connector)) {
15321 connector->base.dpms = DRM_MODE_DPMS_ON;
15322 connector->encoder->connectors_active = true;
15323 connector->base.encoder = &connector->encoder->base;
15325 connector->base.dpms = DRM_MODE_DPMS_OFF;
15326 connector->base.encoder = NULL;
15328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15329 connector->base.base.id,
15330 connector->base.name,
15331 connector->base.encoder ? "enabled" : "disabled");
15335 /* Scan out the current hw modeset state,
15336 * and sanitizes it to the current state
15339 intel_modeset_setup_hw_state(struct drm_device *dev)
15341 struct drm_i915_private *dev_priv = dev->dev_private;
15343 struct intel_crtc *crtc;
15344 struct intel_encoder *encoder;
15347 intel_modeset_readout_hw_state(dev);
15349 /* HW state is read out, now we need to sanitize this mess. */
15350 for_each_intel_encoder(dev, encoder) {
15351 intel_sanitize_encoder(encoder);
15354 for_each_pipe(dev_priv, pipe) {
15355 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15356 intel_sanitize_crtc(crtc);
15357 intel_dump_pipe_config(crtc, crtc->config,
15358 "[setup_hw_state]");
15361 intel_modeset_update_connector_atomic_state(dev);
15363 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15364 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15366 if (!pll->on || pll->active)
15369 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15371 pll->disable(dev_priv, pll);
15375 if (IS_VALLEYVIEW(dev))
15376 vlv_wm_get_hw_state(dev);
15377 else if (IS_GEN9(dev))
15378 skl_wm_get_hw_state(dev);
15379 else if (HAS_PCH_SPLIT(dev))
15380 ilk_wm_get_hw_state(dev);
15382 for_each_intel_crtc(dev, crtc) {
15383 unsigned long put_domains;
15385 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15386 if (WARN_ON(put_domains))
15387 modeset_put_power_domains(dev_priv, put_domains);
15389 intel_display_set_init_power(dev_priv, false);
15392 void intel_display_resume(struct drm_device *dev)
15394 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15395 struct intel_connector *conn;
15396 struct intel_plane *plane;
15397 struct drm_crtc *crtc;
15403 state->acquire_ctx = dev->mode_config.acquire_ctx;
15405 /* preserve complete old state, including dpll */
15406 intel_atomic_get_shared_dpll_state(state);
15408 for_each_crtc(dev, crtc) {
15409 struct drm_crtc_state *crtc_state =
15410 drm_atomic_get_crtc_state(state, crtc);
15412 ret = PTR_ERR_OR_ZERO(crtc_state);
15416 /* force a restore */
15417 crtc_state->mode_changed = true;
15420 for_each_intel_plane(dev, plane) {
15421 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15426 for_each_intel_connector(dev, conn) {
15427 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15432 intel_modeset_setup_hw_state(dev);
15434 i915_redisable_vga(dev);
15435 ret = drm_atomic_commit(state);
15440 DRM_ERROR("Restoring old state failed with %i\n", ret);
15441 drm_atomic_state_free(state);
15444 void intel_modeset_gem_init(struct drm_device *dev)
15446 struct drm_i915_private *dev_priv = dev->dev_private;
15447 struct drm_crtc *c;
15448 struct drm_i915_gem_object *obj;
15451 mutex_lock(&dev->struct_mutex);
15452 intel_init_gt_powersave(dev);
15453 mutex_unlock(&dev->struct_mutex);
15456 * There may be no VBT; and if the BIOS enabled SSC we can
15457 * just keep using it to avoid unnecessary flicker. Whereas if the
15458 * BIOS isn't using it, don't assume it will work even if the VBT
15459 * indicates as much.
15461 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15462 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15465 intel_modeset_init_hw(dev);
15467 intel_setup_overlay(dev);
15470 * Make sure any fbs we allocated at startup are properly
15471 * pinned & fenced. When we do the allocation it's too early
15474 for_each_crtc(dev, c) {
15475 obj = intel_fb_obj(c->primary->fb);
15479 mutex_lock(&dev->struct_mutex);
15480 ret = intel_pin_and_fence_fb_obj(c->primary,
15484 mutex_unlock(&dev->struct_mutex);
15486 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15487 to_intel_crtc(c)->pipe);
15488 drm_framebuffer_unreference(c->primary->fb);
15489 c->primary->fb = NULL;
15490 c->primary->crtc = c->primary->state->crtc = NULL;
15491 update_state_fb(c->primary);
15492 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15496 intel_backlight_register(dev);
15499 void intel_connector_unregister(struct intel_connector *intel_connector)
15501 struct drm_connector *connector = &intel_connector->base;
15503 intel_panel_destroy_backlight(connector);
15504 drm_connector_unregister(connector);
15507 void intel_modeset_cleanup(struct drm_device *dev)
15509 struct drm_i915_private *dev_priv = dev->dev_private;
15510 struct drm_connector *connector;
15512 intel_disable_gt_powersave(dev);
15514 intel_backlight_unregister(dev);
15517 * Interrupts and polling as the first thing to avoid creating havoc.
15518 * Too much stuff here (turning of connectors, ...) would
15519 * experience fancy races otherwise.
15521 intel_irq_uninstall(dev_priv);
15524 * Due to the hpd irq storm handling the hotplug work can re-arm the
15525 * poll handlers. Hence disable polling after hpd handling is shut down.
15527 drm_kms_helper_poll_fini(dev);
15529 intel_unregister_dsm_handler();
15531 intel_fbc_disable(dev_priv);
15533 /* flush any delayed tasks or pending work */
15534 flush_scheduled_work();
15536 /* destroy the backlight and sysfs files before encoders/connectors */
15537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15538 struct intel_connector *intel_connector;
15540 intel_connector = to_intel_connector(connector);
15541 intel_connector->unregister(intel_connector);
15544 drm_mode_config_cleanup(dev);
15546 intel_cleanup_overlay(dev);
15548 mutex_lock(&dev->struct_mutex);
15549 intel_cleanup_gt_powersave(dev);
15550 mutex_unlock(&dev->struct_mutex);
15554 * Return which encoder is currently attached for connector.
15556 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15558 return &intel_attached_encoder(connector)->base;
15561 void intel_connector_attach_encoder(struct intel_connector *connector,
15562 struct intel_encoder *encoder)
15564 connector->encoder = encoder;
15565 drm_mode_connector_attach_encoder(&connector->base,
15570 * set vga decode state - true == enable VGA decode
15572 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15574 struct drm_i915_private *dev_priv = dev->dev_private;
15575 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15578 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15579 DRM_ERROR("failed to read control word\n");
15583 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15587 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15589 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15591 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15592 DRM_ERROR("failed to write control word\n");
15599 struct intel_display_error_state {
15601 u32 power_well_driver;
15603 int num_transcoders;
15605 struct intel_cursor_error_state {
15610 } cursor[I915_MAX_PIPES];
15612 struct intel_pipe_error_state {
15613 bool power_domain_on;
15616 } pipe[I915_MAX_PIPES];
15618 struct intel_plane_error_state {
15626 } plane[I915_MAX_PIPES];
15628 struct intel_transcoder_error_state {
15629 bool power_domain_on;
15630 enum transcoder cpu_transcoder;
15643 struct intel_display_error_state *
15644 intel_display_capture_error_state(struct drm_device *dev)
15646 struct drm_i915_private *dev_priv = dev->dev_private;
15647 struct intel_display_error_state *error;
15648 int transcoders[] = {
15656 if (INTEL_INFO(dev)->num_pipes == 0)
15659 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15663 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15664 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15666 for_each_pipe(dev_priv, i) {
15667 error->pipe[i].power_domain_on =
15668 __intel_display_power_is_enabled(dev_priv,
15669 POWER_DOMAIN_PIPE(i));
15670 if (!error->pipe[i].power_domain_on)
15673 error->cursor[i].control = I915_READ(CURCNTR(i));
15674 error->cursor[i].position = I915_READ(CURPOS(i));
15675 error->cursor[i].base = I915_READ(CURBASE(i));
15677 error->plane[i].control = I915_READ(DSPCNTR(i));
15678 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15679 if (INTEL_INFO(dev)->gen <= 3) {
15680 error->plane[i].size = I915_READ(DSPSIZE(i));
15681 error->plane[i].pos = I915_READ(DSPPOS(i));
15683 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15684 error->plane[i].addr = I915_READ(DSPADDR(i));
15685 if (INTEL_INFO(dev)->gen >= 4) {
15686 error->plane[i].surface = I915_READ(DSPSURF(i));
15687 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15690 error->pipe[i].source = I915_READ(PIPESRC(i));
15692 if (HAS_GMCH_DISPLAY(dev))
15693 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15696 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15697 if (HAS_DDI(dev_priv->dev))
15698 error->num_transcoders++; /* Account for eDP. */
15700 for (i = 0; i < error->num_transcoders; i++) {
15701 enum transcoder cpu_transcoder = transcoders[i];
15703 error->transcoder[i].power_domain_on =
15704 __intel_display_power_is_enabled(dev_priv,
15705 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15706 if (!error->transcoder[i].power_domain_on)
15709 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15711 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15712 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15713 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15714 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15715 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15716 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15717 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15723 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15726 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15727 struct drm_device *dev,
15728 struct intel_display_error_state *error)
15730 struct drm_i915_private *dev_priv = dev->dev_private;
15736 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15737 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15738 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15739 error->power_well_driver);
15740 for_each_pipe(dev_priv, i) {
15741 err_printf(m, "Pipe [%d]:\n", i);
15742 err_printf(m, " Power: %s\n",
15743 error->pipe[i].power_domain_on ? "on" : "off");
15744 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15745 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15747 err_printf(m, "Plane [%d]:\n", i);
15748 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15749 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15750 if (INTEL_INFO(dev)->gen <= 3) {
15751 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15752 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15754 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15755 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15756 if (INTEL_INFO(dev)->gen >= 4) {
15757 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15758 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15761 err_printf(m, "Cursor [%d]:\n", i);
15762 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15763 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15764 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15767 for (i = 0; i < error->num_transcoders; i++) {
15768 err_printf(m, "CPU transcoder: %c\n",
15769 transcoder_name(error->transcoder[i].cpu_transcoder));
15770 err_printf(m, " Power: %s\n",
15771 error->transcoder[i].power_domain_on ? "on" : "off");
15772 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15773 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15774 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15775 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15776 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15777 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15778 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15782 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15784 struct intel_crtc *crtc;
15786 for_each_intel_crtc(dev, crtc) {
15787 struct intel_unpin_work *work;
15789 spin_lock_irq(&dev->event_lock);
15791 work = crtc->unpin_work;
15793 if (work && work->event &&
15794 work->event->base.file_priv == file) {
15795 kfree(work->event);
15796 work->event = NULL;
15799 spin_unlock_irq(&dev->event_lock);