drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *match_clock,
  87                     intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *match_clock,
  91                         intel_clock_t *best_clock);
  92
  93 static bool
  94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                       int target, int refclk, intel_clock_t *match_clock,
  96                       intel_clock_t *best_clock);
  97 static bool
  98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99                            int target, int refclk, intel_clock_t *match_clock,
 100                            intel_clock_t *best_clock);
 101
 102 static inline u32 /* units of 100MHz */
 103 intel_fdi_link_freq(struct drm_device *dev)
 104 {
 105         if (IS_GEN5(dev)) {
 106                 struct drm_i915_private *dev_priv = dev->dev_private;
 107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 108         } else
 109                 return 27;
 110 }
 111
 112 static const intel_limit_t intel_limits_i8xx_dvo = {
 113         .dot = { .min = 25000, .max = 350000 },
 114         .vco = { .min = 930000, .max = 1400000 },
 115         .n = { .min = 3, .max = 16 },
 116         .m = { .min = 96, .max = 140 },
 117         .m1 = { .min = 18, .max = 26 },
 118         .m2 = { .min = 6, .max = 16 },
 119         .p = { .min = 4, .max = 128 },
 120         .p1 = { .min = 2, .max = 33 },
 121         .p2 = { .dot_limit = 165000,
 122                 .p2_slow = 4, .p2_fast = 2 },
 123         .find_pll = intel_find_best_PLL,
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i9xx_sdvo = {
 141         .dot = { .min = 20000, .max = 400000 },
 142         .vco = { .min = 1400000, .max = 2800000 },
 143         .n = { .min = 1, .max = 6 },
 144         .m = { .min = 70, .max = 120 },
 145         .m1 = { .min = 10, .max = 22 },
 146         .m2 = { .min = 5, .max = 9 },
 147         .p = { .min = 5, .max = 80 },
 148         .p1 = { .min = 1, .max = 8 },
 149         .p2 = { .dot_limit = 200000,
 150                 .p2_slow = 10, .p2_fast = 5 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_lvds = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 7, .max = 98 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 112000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168
 169 static const intel_limit_t intel_limits_g4x_sdvo = {
 170         .dot = { .min = 25000, .max = 270000 },
 171         .vco = { .min = 1750000, .max = 3500000},
 172         .n = { .min = 1, .max = 4 },
 173         .m = { .min = 104, .max = 138 },
 174         .m1 = { .min = 17, .max = 23 },
 175         .m2 = { .min = 5, .max = 11 },
 176         .p = { .min = 10, .max = 30 },
 177         .p1 = { .min = 1, .max = 3},
 178         .p2 = { .dot_limit = 270000,
 179                 .p2_slow = 10,
 180                 .p2_fast = 10
 181         },
 182         .find_pll = intel_g4x_find_best_PLL,
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_hdmi = {
 186         .dot = { .min = 22000, .max = 400000 },
 187         .vco = { .min = 1750000, .max = 3500000},
 188         .n = { .min = 1, .max = 4 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 16, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 5, .max = 80 },
 193         .p1 = { .min = 1, .max = 8},
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 10, .p2_fast = 5 },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 200         .dot = { .min = 20000, .max = 115000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 28, .max = 112 },
 207         .p1 = { .min = 2, .max = 8 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 14, .p2_fast = 14
 210         },
 211         .find_pll = intel_g4x_find_best_PLL,
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226         .find_pll = intel_g4x_find_best_PLL,
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_display_port = {
 230         .dot = { .min = 161670, .max = 227000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 2 },
 233         .m = { .min = 97, .max = 108 },
 234         .m1 = { .min = 0x10, .max = 0x12 },
 235         .m2 = { .min = 0x05, .max = 0x06 },
 236         .p = { .min = 10, .max = 20 },
 237         .p1 = { .min = 1, .max = 2},
 238         .p2 = { .dot_limit = 0,
 239                 .p2_slow = 10, .p2_fast = 10 },
 240         .find_pll = intel_find_pll_g4x_dp,
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_sdvo = {
 244         .dot = { .min = 20000, .max = 400000},
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         /* Pineview's Ncounter is a ring counter */
 247         .n = { .min = 3, .max = 6 },
 248         .m = { .min = 2, .max = 256 },
 249         /* Pineview only has one combined m divider, which we treat as m2. */
 250         .m1 = { .min = 0, .max = 0 },
 251         .m2 = { .min = 0, .max = 254 },
 252         .p = { .min = 5, .max = 80 },
 253         .p1 = { .min = 1, .max = 8 },
 254         .p2 = { .dot_limit = 200000,
 255                 .p2_slow = 10, .p2_fast = 5 },
 256         .find_pll = intel_find_best_PLL,
 257 };
 258
 259 static const intel_limit_t intel_limits_pineview_lvds = {
 260         .dot = { .min = 20000, .max = 400000 },
 261         .vco = { .min = 1700000, .max = 3500000 },
 262         .n = { .min = 3, .max = 6 },
 263         .m = { .min = 2, .max = 256 },
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 7, .max = 112 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 112000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 /* Ironlake / Sandybridge
 274  *
 275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 276  * the range value for them is (actual_value - 2).
 277  */
 278 static const intel_limit_t intel_limits_ironlake_dac = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 5 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 5, .max = 80 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 10, .p2_fast = 5 },
 289         .find_pll = intel_g4x_find_best_PLL,
 290 };
 291
 292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 3 },
 296         .m = { .min = 79, .max = 118 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 14, .max = 56 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 7, .p2_fast = 7 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 /* LVDS 100mhz refclk limits. */
 321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 322         .dot = { .min = 25000, .max = 350000 },
 323         .vco = { .min = 1760000, .max = 3510000 },
 324         .n = { .min = 1, .max = 2 },
 325         .m = { .min = 79, .max = 126 },
 326         .m1 = { .min = 12, .max = 22 },
 327         .m2 = { .min = 5, .max = 9 },
 328         .p = { .min = 28, .max = 112 },
 329         .p1 = { .min = 2, .max = 8 },
 330         .p2 = { .dot_limit = 225000,
 331                 .p2_slow = 14, .p2_fast = 14 },
 332         .find_pll = intel_g4x_find_best_PLL,
 333 };
 334
 335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 3 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 14, .max = 42 },
 343         .p1 = { .min = 2, .max = 6 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 7, .p2_fast = 7 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_display_port = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000},
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 81, .max = 90 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 10, .max = 20 },
 357         .p1 = { .min = 1, .max = 2},
 358         .p2 = { .dot_limit = 0,
 359                 .p2_slow = 10, .p2_fast = 10 },
 360         .find_pll = intel_find_pll_ironlake_dp,
 361 };
 362
 363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 364                                                 int refclk)
 365 {
 366         struct drm_device *dev = crtc->dev;
 367         struct drm_i915_private *dev_priv = dev->dev_private;
 368         const intel_limit_t *limit;
 369
 370         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 371                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 372                     LVDS_CLKB_POWER_UP) {
 373                         /* LVDS dual channel */
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_dual_lvds;
 378                 } else {
 379                         if (refclk == 100000)
 380                                 limit = &intel_limits_ironlake_single_lvds_100m;
 381                         else
 382                                 limit = &intel_limits_ironlake_single_lvds;
 383                 }
 384         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 385                         HAS_eDP)
 386                 limit = &intel_limits_ironlake_display_port;
 387         else
 388                 limit = &intel_limits_ironlake_dac;
 389
 390         return limit;
 391 }
 392
 393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 394 {
 395         struct drm_device *dev = crtc->dev;
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397         const intel_limit_t *limit;
 398
 399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 400                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 401                     LVDS_CLKB_POWER_UP)
 402                         /* LVDS with dual channel */
 403                         limit = &intel_limits_g4x_dual_channel_lvds;
 404                 else
 405                         /* LVDS with dual channel */
 406                         limit = &intel_limits_g4x_single_channel_lvds;
 407         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 408                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 409                 limit = &intel_limits_g4x_hdmi;
 410         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 411                 limit = &intel_limits_g4x_sdvo;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 413                 limit = &intel_limits_g4x_display_port;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (!IS_GEN2(dev)) {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i9xx_lvds;
 437                 else
 438                         limit = &intel_limits_i9xx_sdvo;
 439         } else {
 440                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 441                         limit = &intel_limits_i8xx_lvds;
 442                 else
 443                         limit = &intel_limits_i8xx_dvo;
 444         }
 445         return limit;
 446 }
 447
 448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 449 static void pineview_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = clock->m2 + 2;
 452         clock->p = clock->p1 * clock->p2;
 453         clock->vco = refclk * clock->m / clock->n;
 454         clock->dot = clock->vco / clock->p;
 455 }
 456
 457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 458 {
 459         if (IS_PINEVIEW(dev)) {
 460                 pineview_clock(refclk, clock);
 461                 return;
 462         }
 463         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 464         clock->p = clock->p1 * clock->p2;
 465         clock->vco = refclk * clock->m / (clock->n + 2);
 466         clock->dot = clock->vco / clock->p;
 467 }
 468
 469 /**
 470  * Returns whether any output on the specified pipe is of the specified type
 471  */
 472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 473 {
 474         struct drm_device *dev = crtc->dev;
 475         struct drm_mode_config *mode_config = &dev->mode_config;
 476         struct intel_encoder *encoder;
 477
 478         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 479                 if (encoder->base.crtc == crtc && encoder->type == type)
 480                         return true;
 481
 482         return false;
 483 }
 484
 485 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 486 /**
 487  * Returns whether the given set of divisors are valid for a given refclk with
 488  * the given connectors.
 489  */
 490
 491 static bool intel_PLL_is_valid(struct drm_device *dev,
 492                                const intel_limit_t *limit,
 493                                const intel_clock_t *clock)
 494 {
 495         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 496                 INTELPllInvalid("p1 out of range\n");
 497         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 498                 INTELPllInvalid("p out of range\n");
 499         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 500                 INTELPllInvalid("m2 out of range\n");
 501         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 502                 INTELPllInvalid("m1 out of range\n");
 503         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 504                 INTELPllInvalid("m1 <= m2\n");
 505         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 506                 INTELPllInvalid("m out of range\n");
 507         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 508                 INTELPllInvalid("n out of range\n");
 509         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 510                 INTELPllInvalid("vco out of range\n");
 511         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 512          * connector, etc., rather than just a single range.
 513          */
 514         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 515                 INTELPllInvalid("dot out of range\n");
 516
 517         return true;
 518 }
 519
 520 static bool
 521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 522                     int target, int refclk, intel_clock_t *match_clock,
 523                     intel_clock_t *best_clock)
 524
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         intel_clock_t clock;
 529         int err = target;
 530
 531         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 532             (I915_READ(LVDS)) != 0) {
 533                 /*
 534                  * For LVDS, if the panel is on, just rely on its current
 535                  * settings for dual-channel.  We haven't figured out how to
 536                  * reliably set up different single/dual channel state, if we
 537                  * even can.
 538                  */
 539                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 540                     LVDS_CLKB_POWER_UP)
 541                         clock.p2 = limit->p2.p2_fast;
 542                 else
 543                         clock.p2 = limit->p2.p2_slow;
 544         } else {
 545                 if (target < limit->p2.dot_limit)
 546                         clock.p2 = limit->p2.p2_slow;
 547                 else
 548                         clock.p2 = limit->p2.p2_fast;
 549         }
 550
 551         memset(best_clock, 0, sizeof(*best_clock));
 552
 553         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 554              clock.m1++) {
 555                 for (clock.m2 = limit->m2.min;
 556                      clock.m2 <= limit->m2.max; clock.m2++) {
 557                         /* m1 is always 0 in Pineview */
 558                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 559                                 break;
 560                         for (clock.n = limit->n.min;
 561                              clock.n <= limit->n.max; clock.n++) {
 562                                 for (clock.p1 = limit->p1.min;
 563                                         clock.p1 <= limit->p1.max; clock.p1++) {
 564                                         int this_err;
 565
 566                                         intel_clock(dev, refclk, &clock);
 567                                         if (!intel_PLL_is_valid(dev, limit,
 568                                                                 &clock))
 569                                                 continue;
 570                                         if (match_clock &&
 571                                             clock.p != match_clock->p)
 572                                                 continue;
 573
 574                                         this_err = abs(clock.dot - target);
 575                                         if (this_err < err) {
 576                                                 *best_clock = clock;
 577                                                 err = this_err;
 578                                         }
 579                                 }
 580                         }
 581                 }
 582         }
 583
 584         return (err != target);
 585 }
 586
 587 static bool
 588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 589                         int target, int refclk, intel_clock_t *match_clock,
 590                         intel_clock_t *best_clock)
 591 {
 592         struct drm_device *dev = crtc->dev;
 593         struct drm_i915_private *dev_priv = dev->dev_private;
 594         intel_clock_t clock;
 595         int max_n;
 596         bool found;
 597         /* approximately equals target * 0.00585 */
 598         int err_most = (target >> 8) + (target >> 9);
 599         found = false;
 600
 601         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 602                 int lvds_reg;
 603
 604                 if (HAS_PCH_SPLIT(dev))
 605                         lvds_reg = PCH_LVDS;
 606                 else
 607                         lvds_reg = LVDS;
 608                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 609                     LVDS_CLKB_POWER_UP)
 610                         clock.p2 = limit->p2.p2_fast;
 611                 else
 612                         clock.p2 = limit->p2.p2_slow;
 613         } else {
 614                 if (target < limit->p2.dot_limit)
 615                         clock.p2 = limit->p2.p2_slow;
 616                 else
 617                         clock.p2 = limit->p2.p2_fast;
 618         }
 619
 620         memset(best_clock, 0, sizeof(*best_clock));
 621         max_n = limit->n.max;
 622         /* based on hardware requirement, prefer smaller n to precision */
 623         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 624                 /* based on hardware requirement, prefere larger m1,m2 */
 625                 for (clock.m1 = limit->m1.max;
 626                      clock.m1 >= limit->m1.min; clock.m1--) {
 627                         for (clock.m2 = limit->m2.max;
 628                              clock.m2 >= limit->m2.min; clock.m2--) {
 629                                 for (clock.p1 = limit->p1.max;
 630                                      clock.p1 >= limit->p1.min; clock.p1--) {
 631                                         int this_err;
 632
 633                                         intel_clock(dev, refclk, &clock);
 634                                         if (!intel_PLL_is_valid(dev, limit,
 635                                                                 &clock))
 636                                                 continue;
 637                                         if (match_clock &&
 638                                             clock.p != match_clock->p)
 639                                                 continue;
 640
 641                                         this_err = abs(clock.dot - target);
 642                                         if (this_err < err_most) {
 643                                                 *best_clock = clock;
 644                                                 err_most = this_err;
 645                                                 max_n = clock.n;
 646                                                 found = true;
 647                                         }
 648                                 }
 649                         }
 650                 }
 651         }
 652         return found;
 653 }
 654
 655 static bool
 656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 657                            int target, int refclk, intel_clock_t *match_clock,
 658                            intel_clock_t *best_clock)
 659 {
 660         struct drm_device *dev = crtc->dev;
 661         intel_clock_t clock;
 662
 663         if (target < 200000) {
 664                 clock.n = 1;
 665                 clock.p1 = 2;
 666                 clock.p2 = 10;
 667                 clock.m1 = 12;
 668                 clock.m2 = 9;
 669         } else {
 670                 clock.n = 2;
 671                 clock.p1 = 1;
 672                 clock.p2 = 10;
 673                 clock.m1 = 14;
 674                 clock.m2 = 8;
 675         }
 676         intel_clock(dev, refclk, &clock);
 677         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 678         return true;
 679 }
 680
 681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 682 static bool
 683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                       int target, int refclk, intel_clock_t *match_clock,
 685                       intel_clock_t *best_clock)
 686 {
 687         intel_clock_t clock;
 688         if (target < 200000) {
 689                 clock.p1 = 2;
 690                 clock.p2 = 10;
 691                 clock.n = 2;
 692                 clock.m1 = 23;
 693                 clock.m2 = 8;
 694         } else {
 695                 clock.p1 = 1;
 696                 clock.p2 = 10;
 697                 clock.n = 1;
 698                 clock.m1 = 14;
 699                 clock.m2 = 2;
 700         }
 701         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 702         clock.p = (clock.p1 * clock.p2);
 703         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 704         clock.vco = 0;
 705         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 706         return true;
 707 }
 708
 709 /**
 710  * intel_wait_for_vblank - wait for vblank on a given pipe
 711  * @dev: drm device
 712  * @pipe: pipe to wait for
 713  *
 714  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 715  * mode setting code.
 716  */
 717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 718 {
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         int pipestat_reg = PIPESTAT(pipe);
 721
 722         /* Clear existing vblank status. Note this will clear any other
 723          * sticky status fields as well.
 724          *
 725          * This races with i915_driver_irq_handler() with the result
 726          * that either function could miss a vblank event.  Here it is not
 727          * fatal, as we will either wait upon the next vblank interrupt or
 728          * timeout.  Generally speaking intel_wait_for_vblank() is only
 729          * called during modeset at which time the GPU should be idle and
 730          * should *not* be performing page flips and thus not waiting on
 731          * vblanks...
 732          * Currently, the result of us stealing a vblank from the irq
 733          * handler is that a single frame will be skipped during swapbuffers.
 734          */
 735         I915_WRITE(pipestat_reg,
 736                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 737
 738         /* Wait for vblank interrupt bit to set */
 739         if (wait_for(I915_READ(pipestat_reg) &
 740                      PIPE_VBLANK_INTERRUPT_STATUS,
 741                      50))
 742                 DRM_DEBUG_KMS("vblank wait timed out\n");
 743 }
 744
 745 /*
 746  * intel_wait_for_pipe_off - wait for pipe to turn off
 747  * @dev: drm device
 748  * @pipe: pipe to wait for
 749  *
 750  * After disabling a pipe, we can't wait for vblank in the usual way,
 751  * spinning on the vblank interrupt status bit, since we won't actually
 752  * see an interrupt when the pipe is disabled.
 753  *
 754  * On Gen4 and above:
 755  *   wait for the pipe register state bit to turn off
 756  *
 757  * Otherwise:
 758  *   wait for the display line value to settle (it usually
 759  *   ends up stopping at the start of the next frame).
 760  *
 761  */
 762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765
 766         if (INTEL_INFO(dev)->gen >= 4) {
 767                 int reg = PIPECONF(pipe);
 768
 769                 /* Wait for the Pipe State to go off */
 770                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 771                              100))
 772                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 773         } else {
 774                 u32 last_line;
 775                 int reg = PIPEDSL(pipe);
 776                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 777
 778                 /* Wait for the display line to settle */
 779                 do {
 780                         last_line = I915_READ(reg) & DSL_LINEMASK;
 781                         mdelay(5);
 782                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 783                          time_after(timeout, jiffies));
 784                 if (time_after(jiffies, timeout))
 785                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 786         }
 787 }
 788
 789 static const char *state_string(bool enabled)
 790 {
 791         return enabled ? "on" : "off";
 792 }
 793
 794 /* Only for pre-ILK configs */
 795 static void assert_pll(struct drm_i915_private *dev_priv,
 796                        enum pipe pipe, bool state)
 797 {
 798         int reg;
 799         u32 val;
 800         bool cur_state;
 801
 802         reg = DPLL(pipe);
 803         val = I915_READ(reg);
 804         cur_state = !!(val & DPLL_VCO_ENABLE);
 805         WARN(cur_state != state,
 806              "PLL state assertion failure (expected %s, current %s)\n",
 807              state_string(state), state_string(cur_state));
 808 }
 809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 811
 812 /* For ILK+ */
 813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 814                            enum pipe pipe, bool state)
 815 {
 816         int reg;
 817         u32 val;
 818         bool cur_state;
 819
 820         if (HAS_PCH_CPT(dev_priv->dev)) {
 821                 u32 pch_dpll;
 822
 823                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 824
 825                 /* Make sure the selected PLL is enabled to the transcoder */
 826                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 827                      "transcoder %d PLL not enabled\n", pipe);
 828
 829                 /* Convert the transcoder pipe number to a pll pipe number */
 830                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 831         }
 832
 833         reg = PCH_DPLL(pipe);
 834         val = I915_READ(reg);
 835         cur_state = !!(val & DPLL_VCO_ENABLE);
 836         WARN(cur_state != state,
 837              "PCH PLL state assertion failure (expected %s, current %s)\n",
 838              state_string(state), state_string(cur_state));
 839 }
 840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 842
 843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 844                           enum pipe pipe, bool state)
 845 {
 846         int reg;
 847         u32 val;
 848         bool cur_state;
 849
 850         reg = FDI_TX_CTL(pipe);
 851         val = I915_READ(reg);
 852         cur_state = !!(val & FDI_TX_ENABLE);
 853         WARN(cur_state != state,
 854              "FDI TX state assertion failure (expected %s, current %s)\n",
 855              state_string(state), state_string(cur_state));
 856 }
 857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 859
 860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 861                           enum pipe pipe, bool state)
 862 {
 863         int reg;
 864         u32 val;
 865         bool cur_state;
 866
 867         reg = FDI_RX_CTL(pipe);
 868         val = I915_READ(reg);
 869         cur_state = !!(val & FDI_RX_ENABLE);
 870         WARN(cur_state != state,
 871              "FDI RX state assertion failure (expected %s, current %s)\n",
 872              state_string(state), state_string(cur_state));
 873 }
 874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 876
 877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 878                                       enum pipe pipe)
 879 {
 880         int reg;
 881         u32 val;
 882
 883         /* ILK FDI PLL is always enabled */
 884         if (dev_priv->info->gen == 5)
 885                 return;
 886
 887         reg = FDI_TX_CTL(pipe);
 888         val = I915_READ(reg);
 889         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 890 }
 891
 892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 893                                       enum pipe pipe)
 894 {
 895         int reg;
 896         u32 val;
 897
 898         reg = FDI_RX_CTL(pipe);
 899         val = I915_READ(reg);
 900         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 901 }
 902
 903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 904                                   enum pipe pipe)
 905 {
 906         int pp_reg, lvds_reg;
 907         u32 val;
 908         enum pipe panel_pipe = PIPE_A;
 909         bool locked = true;
 910
 911         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 912                 pp_reg = PCH_PP_CONTROL;
 913                 lvds_reg = PCH_LVDS;
 914         } else {
 915                 pp_reg = PP_CONTROL;
 916                 lvds_reg = LVDS;
 917         }
 918
 919         val = I915_READ(pp_reg);
 920         if (!(val & PANEL_POWER_ON) ||
 921             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 922                 locked = false;
 923
 924         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 925                 panel_pipe = PIPE_B;
 926
 927         WARN(panel_pipe == pipe && locked,
 928              "panel assertion failure, pipe %c regs locked\n",
 929              pipe_name(pipe));
 930 }
 931
 932 void assert_pipe(struct drm_i915_private *dev_priv,
 933                  enum pipe pipe, bool state)
 934 {
 935         int reg;
 936         u32 val;
 937         bool cur_state;
 938
 939         /* if we need the pipe A quirk it must be always on */
 940         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 941                 state = true;
 942
 943         reg = PIPECONF(pipe);
 944         val = I915_READ(reg);
 945         cur_state = !!(val & PIPECONF_ENABLE);
 946         WARN(cur_state != state,
 947              "pipe %c assertion failure (expected %s, current %s)\n",
 948              pipe_name(pipe), state_string(state), state_string(cur_state));
 949 }
 950
 951 static void assert_plane(struct drm_i915_private *dev_priv,
 952                          enum plane plane, bool state)
 953 {
 954         int reg;
 955         u32 val;
 956         bool cur_state;
 957
 958         reg = DSPCNTR(plane);
 959         val = I915_READ(reg);
 960         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 961         WARN(cur_state != state,
 962              "plane %c assertion failure (expected %s, current %s)\n",
 963              plane_name(plane), state_string(state), state_string(cur_state));
 964 }
 965
 966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
 967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
 968
 969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 970                                    enum pipe pipe)
 971 {
 972         int reg, i;
 973         u32 val;
 974         int cur_pipe;
 975
 976         /* Planes are fixed to pipes on ILK+ */
 977         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 978                 reg = DSPCNTR(pipe);
 979                 val = I915_READ(reg);
 980                 WARN((val & DISPLAY_PLANE_ENABLE),
 981                      "plane %c assertion failure, should be disabled but not\n",
 982                      plane_name(pipe));
 983                 return;
 984         }
 985
 986         /* Need to check both planes against the pipe */
 987         for (i = 0; i < 2; i++) {
 988                 reg = DSPCNTR(i);
 989                 val = I915_READ(reg);
 990                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 991                         DISPPLANE_SEL_PIPE_SHIFT;
 992                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 993                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 994                      plane_name(i), pipe_name(pipe));
 995         }
 996 }
 997
 998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 999 {
1000         u32 val;
1001         bool enabled;
1002
1003         val = I915_READ(PCH_DREF_CONTROL);
1004         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005                             DREF_SUPERSPREAD_SOURCE_MASK));
1006         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010                                        enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014         bool enabled;
1015
1016         reg = TRANSCONF(pipe);
1017         val = I915_READ(reg);
1018         enabled = !!(val & TRANS_ENABLE);
1019         WARN(enabled,
1020              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021              pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025                             enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027         if ((val & DP_PORT_EN) == 0)
1028                 return false;
1029
1030         if (HAS_PCH_CPT(dev_priv->dev)) {
1031                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034                         return false;
1035         } else {
1036                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037                         return false;
1038         }
1039         return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043                               enum pipe pipe, u32 val)
1044 {
1045         if ((val & PORT_ENABLE) == 0)
1046                 return false;
1047
1048         if (HAS_PCH_CPT(dev_priv->dev)) {
1049                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050                         return false;
1051         } else {
1052                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053                         return false;
1054         }
1055         return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059                               enum pipe pipe, u32 val)
1060 {
1061         if ((val & LVDS_PORT_EN) == 0)
1062                 return false;
1063
1064         if (HAS_PCH_CPT(dev_priv->dev)) {
1065                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066                         return false;
1067         } else {
1068                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069                         return false;
1070         }
1071         return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075                               enum pipe pipe, u32 val)
1076 {
1077         if ((val & ADPA_DAC_ENABLE) == 0)
1078                 return false;
1079         if (HAS_PCH_CPT(dev_priv->dev)) {
1080                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081                         return false;
1082         } else {
1083                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084                         return false;
1085         }
1086         return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090                                    enum pipe pipe, int reg, u32 port_sel)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099                                      enum pipe pipe, int reg)
1100 {
1101         u32 val = I915_READ(reg);
1102         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104              reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108                                       enum pipe pipe)
1109 {
1110         int reg;
1111         u32 val;
1112
1113         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117         reg = PCH_ADPA;
1118         val = I915_READ(reg);
1119         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120              "PCH VGA enabled on transcoder %c, should be disabled\n",
1121              pipe_name(pipe));
1122
1123         reg = PCH_LVDS;
1124         val = I915_READ(reg);
1125         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127              pipe_name(pipe));
1128
1129         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135  * intel_enable_pll - enable a PLL
1136  * @dev_priv: i915 private structure
1137  * @pipe: pipe PLL to enable
1138  *
1139  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1140  * make sure the PLL reg is writable first though, since the panel write
1141  * protect mechanism may be enabled.
1142  *
1143  * Note!  This is for pre-ILK only.
1144  */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147         int reg;
1148         u32 val;
1149
1150         /* No really, not for ILK+ */
1151         BUG_ON(dev_priv->info->gen >= 5);
1152
1153         /* PLL is protected by panel, make sure we can write it */
1154         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155                 assert_panel_unlocked(dev_priv, pipe);
1156
1157         reg = DPLL(pipe);
1158         val = I915_READ(reg);
1159         val |= DPLL_VCO_ENABLE;
1160
1161         /* We do this three times for luck */
1162         I915_WRITE(reg, val);
1163         POSTING_READ(reg);
1164         udelay(150); /* wait for warmup */
1165         I915_WRITE(reg, val);
1166         POSTING_READ(reg);
1167         udelay(150); /* wait for warmup */
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170         udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174  * intel_disable_pll - disable a PLL
1175  * @dev_priv: i915 private structure
1176  * @pipe: pipe PLL to disable
1177  *
1178  * Disable the PLL for @pipe, making sure the pipe is off first.
1179  *
1180  * Note!  This is for pre-ILK only.
1181  */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         /* Don't disable pipe A or pipe A PLLs if needed */
1188         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189                 return;
1190
1191         /* Make sure the pipe isn't still relying on us */
1192         assert_pipe_disabled(dev_priv, pipe);
1193
1194         reg = DPLL(pipe);
1195         val = I915_READ(reg);
1196         val &= ~DPLL_VCO_ENABLE;
1197         I915_WRITE(reg, val);
1198         POSTING_READ(reg);
1199 }
1200
1201 /**
1202  * intel_enable_pch_pll - enable PCH PLL
1203  * @dev_priv: i915 private structure
1204  * @pipe: pipe PLL to enable
1205  *
1206  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207  * drives the transcoder clock.
1208  */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210                                  enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         if (pipe > 1)
1216                 return;
1217
1218         /* PCH only available on ILK+ */
1219         BUG_ON(dev_priv->info->gen < 5);
1220
1221         /* PCH refclock must be enabled first */
1222         assert_pch_refclk_enabled(dev_priv);
1223
1224         reg = PCH_DPLL(pipe);
1225         val = I915_READ(reg);
1226         val |= DPLL_VCO_ENABLE;
1227         I915_WRITE(reg, val);
1228         POSTING_READ(reg);
1229         udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233                                   enum pipe pipe)
1234 {
1235         int reg;
1236         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237                 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239         if (pipe > 1)
1240                 return;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure transcoder isn't still depending on us */
1246         assert_transcoder_disabled(dev_priv, pipe);
1247
1248         if (pipe == 0)
1249                 pll_sel |= TRANSC_DPLLA_SEL;
1250         else if (pipe == 1)
1251                 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255                 return;
1256
1257         reg = PCH_DPLL(pipe);
1258         val = I915_READ(reg);
1259         val &= ~DPLL_VCO_ENABLE;
1260         I915_WRITE(reg, val);
1261         POSTING_READ(reg);
1262         udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266                                     enum pipe pipe)
1267 {
1268         int reg;
1269         u32 val, pipeconf_val;
1270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1271
1272         /* PCH only available on ILK+ */
1273         BUG_ON(dev_priv->info->gen < 5);
1274
1275         /* Make sure PCH DPLL is enabled */
1276         assert_pch_pll_enabled(dev_priv, pipe);
1277
1278         /* FDI must be feeding us bits for PCH ports */
1279         assert_fdi_tx_enabled(dev_priv, pipe);
1280         assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282         reg = TRANSCONF(pipe);
1283         val = I915_READ(reg);
1284         pipeconf_val = I915_READ(PIPECONF(pipe));
1285
1286         if (HAS_PCH_IBX(dev_priv->dev)) {
1287                 /*
1288                  * make the BPC in transcoder be consistent with
1289                  * that in pipeconf reg.
1290                  */
1291                 val &= ~PIPE_BPC_MASK;
1292                 val |= pipeconf_val & PIPE_BPC_MASK;
1293         }
1294
1295         val &= ~TRANS_INTERLACE_MASK;
1296         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1297                 if (HAS_PCH_IBX(dev_priv->dev) &&
1298                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299                         val |= TRANS_LEGACY_INTERLACED_ILK;
1300                 else
1301                         val |= TRANS_INTERLACED;
1302         else
1303                 val |= TRANS_PROGRESSIVE;
1304
1305         I915_WRITE(reg, val | TRANS_ENABLE);
1306         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308 }
1309
1310 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311                                      enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315
1316         /* FDI relies on the transcoder */
1317         assert_fdi_tx_disabled(dev_priv, pipe);
1318         assert_fdi_rx_disabled(dev_priv, pipe);
1319
1320         /* Ports must be off as well */
1321         assert_pch_ports_disabled(dev_priv, pipe);
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         val &= ~TRANS_ENABLE;
1326         I915_WRITE(reg, val);
1327         /* wait for PCH transcoder off, transcoder state */
1328         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1329                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1330 }
1331
1332 /**
1333  * intel_enable_pipe - enable a pipe, asserting requirements
1334  * @dev_priv: i915 private structure
1335  * @pipe: pipe to enable
1336  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1337  *
1338  * Enable @pipe, making sure that various hardware specific requirements
1339  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340  *
1341  * @pipe should be %PIPE_A or %PIPE_B.
1342  *
1343  * Will wait until the pipe is actually running (i.e. first vblank) before
1344  * returning.
1345  */
1346 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347                               bool pch_port)
1348 {
1349         int reg;
1350         u32 val;
1351
1352         /*
1353          * A pipe without a PLL won't actually be able to drive bits from
1354          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1355          * need the check.
1356          */
1357         if (!HAS_PCH_SPLIT(dev_priv->dev))
1358                 assert_pll_enabled(dev_priv, pipe);
1359         else {
1360                 if (pch_port) {
1361                         /* if driving the PCH, we need FDI enabled */
1362                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364                 }
1365                 /* FIXME: assert CPU port conditions for SNB+ */
1366         }
1367
1368         reg = PIPECONF(pipe);
1369         val = I915_READ(reg);
1370         if (val & PIPECONF_ENABLE)
1371                 return;
1372
1373         I915_WRITE(reg, val | PIPECONF_ENABLE);
1374         intel_wait_for_vblank(dev_priv->dev, pipe);
1375 }
1376
1377 /**
1378  * intel_disable_pipe - disable a pipe, asserting requirements
1379  * @dev_priv: i915 private structure
1380  * @pipe: pipe to disable
1381  *
1382  * Disable @pipe, making sure that various hardware specific requirements
1383  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384  *
1385  * @pipe should be %PIPE_A or %PIPE_B.
1386  *
1387  * Will wait until the pipe has shut down before returning.
1388  */
1389 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390                                enum pipe pipe)
1391 {
1392         int reg;
1393         u32 val;
1394
1395         /*
1396          * Make sure planes won't keep trying to pump pixels to us,
1397          * or we might hang the display.
1398          */
1399         assert_planes_disabled(dev_priv, pipe);
1400
1401         /* Don't disable pipe A or pipe A PLLs if needed */
1402         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403                 return;
1404
1405         reg = PIPECONF(pipe);
1406         val = I915_READ(reg);
1407         if ((val & PIPECONF_ENABLE) == 0)
1408                 return;
1409
1410         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1411         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412 }
1413
1414 /*
1415  * Plane regs are double buffered, going from enabled->disabled needs a
1416  * trigger in order to latch.  The display address reg provides this.
1417  */
1418 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419                                       enum plane plane)
1420 {
1421         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423 }
1424
1425 /**
1426  * intel_enable_plane - enable a display plane on a given pipe
1427  * @dev_priv: i915 private structure
1428  * @plane: plane to enable
1429  * @pipe: pipe being fed
1430  *
1431  * Enable @plane on @pipe, making sure that @pipe is running first.
1432  */
1433 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434                                enum plane plane, enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440         assert_pipe_enabled(dev_priv, pipe);
1441
1442         reg = DSPCNTR(plane);
1443         val = I915_READ(reg);
1444         if (val & DISPLAY_PLANE_ENABLE)
1445                 return;
1446
1447         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1448         intel_flush_display_plane(dev_priv, plane);
1449         intel_wait_for_vblank(dev_priv->dev, pipe);
1450 }
1451
1452 /**
1453  * intel_disable_plane - disable a display plane
1454  * @dev_priv: i915 private structure
1455  * @plane: plane to disable
1456  * @pipe: pipe consuming the data
1457  *
1458  * Disable @plane; should be an independent operation.
1459  */
1460 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461                                 enum plane plane, enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         reg = DSPCNTR(plane);
1467         val = I915_READ(reg);
1468         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469                 return;
1470
1471         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1472         intel_flush_display_plane(dev_priv, plane);
1473         intel_wait_for_vblank(dev_priv->dev, pipe);
1474 }
1475
1476 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1477                            enum pipe pipe, int reg, u32 port_sel)
1478 {
1479         u32 val = I915_READ(reg);
1480         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1481                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1482                 I915_WRITE(reg, val & ~DP_PORT_EN);
1483         }
1484 }
1485
1486 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487                              enum pipe pipe, int reg)
1488 {
1489         u32 val = I915_READ(reg);
1490         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1491                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492                               reg, pipe);
1493                 I915_WRITE(reg, val & ~PORT_ENABLE);
1494         }
1495 }
1496
1497 /* Disable any ports connected to this transcoder */
1498 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499                                     enum pipe pipe)
1500 {
1501         u32 reg, val;
1502
1503         val = I915_READ(PCH_PP_CONTROL);
1504         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
1506         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1509
1510         reg = PCH_ADPA;
1511         val = I915_READ(reg);
1512         if (adpa_pipe_enabled(dev_priv, val, pipe))
1513                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515         reg = PCH_LVDS;
1516         val = I915_READ(reg);
1517         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1519                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520                 POSTING_READ(reg);
1521                 udelay(100);
1522         }
1523
1524         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526         disable_pch_hdmi(dev_priv, pipe, HDMID);
1527 }
1528
1529 static void i8xx_disable_fbc(struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         u32 fbc_ctl;
1533
1534         /* Disable compression */
1535         fbc_ctl = I915_READ(FBC_CONTROL);
1536         if ((fbc_ctl & FBC_CTL_EN) == 0)
1537                 return;
1538
1539         fbc_ctl &= ~FBC_CTL_EN;
1540         I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542         /* Wait for compressing bit to clear */
1543         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544                 DRM_DEBUG_KMS("FBC idle timed out\n");
1545                 return;
1546         }
1547
1548         DRM_DEBUG_KMS("disabled FBC\n");
1549 }
1550
1551 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int cfb_pitch;
1560         int plane, i;
1561         u32 fbc_ctl, fbc_ctl2;
1562
1563         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1564         if (fb->pitches[0] < cfb_pitch)
1565                 cfb_pitch = fb->pitches[0];
1566
1567         /* FBC_CTL wants 64B units */
1568         cfb_pitch = (cfb_pitch / 64) - 1;
1569         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1570
1571         /* Clear old tags */
1572         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573                 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575         /* Set it up... */
1576         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577         fbc_ctl2 |= plane;
1578         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581         /* enable it... */
1582         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1583         if (IS_I945GM(dev))
1584                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1585         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1586         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1587         fbc_ctl |= obj->fence_reg;
1588         I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
1590         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591                       cfb_pitch, crtc->y, intel_crtc->plane);
1592 }
1593
1594 static bool i8xx_fbc_enabled(struct drm_device *dev)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599 }
1600
1601 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603         struct drm_device *dev = crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         struct drm_framebuffer *fb = crtc->fb;
1606         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607         struct drm_i915_gem_object *obj = intel_fb->obj;
1608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610         unsigned long stall_watermark = 200;
1611         u32 dpfc_ctl;
1612
1613         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1614         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1615         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1616
1617         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622         /* enable it... */
1623         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
1625         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1626 }
1627
1628 static void g4x_disable_fbc(struct drm_device *dev)
1629 {
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         u32 dpfc_ctl;
1632
1633         /* Disable compression */
1634         dpfc_ctl = I915_READ(DPFC_CONTROL);
1635         if (dpfc_ctl & DPFC_CTL_EN) {
1636                 dpfc_ctl &= ~DPFC_CTL_EN;
1637                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1638
1639                 DRM_DEBUG_KMS("disabled FBC\n");
1640         }
1641 }
1642
1643 static bool g4x_fbc_enabled(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648 }
1649
1650 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 blt_ecoskpd;
1654
1655         /* Make sure blitter notifies FBC of writes */
1656         gen6_gt_force_wake_get(dev_priv);
1657         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659                 GEN6_BLITTER_LOCK_SHIFT;
1660         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664                          GEN6_BLITTER_LOCK_SHIFT);
1665         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1667         gen6_gt_force_wake_put(dev_priv);
1668 }
1669
1670 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct drm_framebuffer *fb = crtc->fb;
1675         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1676         struct drm_i915_gem_object *obj = intel_fb->obj;
1677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1678         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1679         unsigned long stall_watermark = 200;
1680         u32 dpfc_ctl;
1681
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         dpfc_ctl &= DPFC_RESERVED;
1684         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1685         /* Set persistent mode for front-buffer rendering, ala X. */
1686         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1687         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1688         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1689
1690         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1694         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1695         /* enable it... */
1696         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1697
1698         if (IS_GEN6(dev)) {
1699                 I915_WRITE(SNB_DPFC_CTL_SA,
1700                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1701                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1702                 sandybridge_blit_fbc_update(dev);
1703         }
1704
1705         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706 }
1707
1708 static void ironlake_disable_fbc(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         u32 dpfc_ctl;
1712
1713         /* Disable compression */
1714         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1715         if (dpfc_ctl & DPFC_CTL_EN) {
1716                 dpfc_ctl &= ~DPFC_CTL_EN;
1717                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1718
1719                 DRM_DEBUG_KMS("disabled FBC\n");
1720         }
1721 }
1722
1723 static bool ironlake_fbc_enabled(struct drm_device *dev)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728 }
1729
1730 bool intel_fbc_enabled(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734         if (!dev_priv->display.fbc_enabled)
1735                 return false;
1736
1737         return dev_priv->display.fbc_enabled(dev);
1738 }
1739
1740 static void intel_fbc_work_fn(struct work_struct *__work)
1741 {
1742         struct intel_fbc_work *work =
1743                 container_of(to_delayed_work(__work),
1744                              struct intel_fbc_work, work);
1745         struct drm_device *dev = work->crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         mutex_lock(&dev->struct_mutex);
1749         if (work == dev_priv->fbc_work) {
1750                 /* Double check that we haven't switched fb without cancelling
1751                  * the prior work.
1752                  */
1753                 if (work->crtc->fb == work->fb) {
1754                         dev_priv->display.enable_fbc(work->crtc,
1755                                                      work->interval);
1756
1757                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1759                         dev_priv->cfb_y = work->crtc->y;
1760                 }
1761
1762                 dev_priv->fbc_work = NULL;
1763         }
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         kfree(work);
1767 }
1768
1769 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770 {
1771         if (dev_priv->fbc_work == NULL)
1772                 return;
1773
1774         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776         /* Synchronisation is provided by struct_mutex and checking of
1777          * dev_priv->fbc_work, so we can perform the cancellation
1778          * entirely asynchronously.
1779          */
1780         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781                 /* tasklet was killed before being run, clean up */
1782                 kfree(dev_priv->fbc_work);
1783
1784         /* Mark the work as no longer wanted so that if it does
1785          * wake-up (because the work was already running and waiting
1786          * for our mutex), it will discover that is no longer
1787          * necessary to run.
1788          */
1789         dev_priv->fbc_work = NULL;
1790 }
1791
1792 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1793 {
1794         struct intel_fbc_work *work;
1795         struct drm_device *dev = crtc->dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798         if (!dev_priv->display.enable_fbc)
1799                 return;
1800
1801         intel_cancel_fbc_work(dev_priv);
1802
1803         work = kzalloc(sizeof *work, GFP_KERNEL);
1804         if (work == NULL) {
1805                 dev_priv->display.enable_fbc(crtc, interval);
1806                 return;
1807         }
1808
1809         work->crtc = crtc;
1810         work->fb = crtc->fb;
1811         work->interval = interval;
1812         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814         dev_priv->fbc_work = work;
1815
1816         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818         /* Delay the actual enabling to let pageflipping cease and the
1819          * display to settle before starting the compression. Note that
1820          * this delay also serves a second purpose: it allows for a
1821          * vblank to pass after disabling the FBC before we attempt
1822          * to modify the control registers.
1823          *
1824          * A more complicated solution would involve tracking vblanks
1825          * following the termination of the page-flipping sequence
1826          * and indeed performing the enable as a co-routine and not
1827          * waiting synchronously upon the vblank.
1828          */
1829         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1830 }
1831
1832 void intel_disable_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836         intel_cancel_fbc_work(dev_priv);
1837
1838         if (!dev_priv->display.disable_fbc)
1839                 return;
1840
1841         dev_priv->display.disable_fbc(dev);
1842         dev_priv->cfb_plane = -1;
1843 }
1844
1845 /**
1846  * intel_update_fbc - enable/disable FBC as needed
1847  * @dev: the drm_device
1848  *
1849  * Set up the framebuffer compression hardware at mode set time.  We
1850  * enable it if possible:
1851  *   - plane A only (on pre-965)
1852  *   - no pixel mulitply/line duplication
1853  *   - no alpha buffer discard
1854  *   - no dual wide
1855  *   - framebuffer <= 2048 in width, 1536 in height
1856  *
1857  * We can't assume that any compression will take place (worst case),
1858  * so the compressed buffer has to be the same size as the uncompressed
1859  * one.  It also must reside (along with the line length buffer) in
1860  * stolen memory.
1861  *
1862  * We need to enable/disable FBC on a global basis.
1863  */
1864 static void intel_update_fbc(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         struct drm_crtc *crtc = NULL, *tmp_crtc;
1868         struct intel_crtc *intel_crtc;
1869         struct drm_framebuffer *fb;
1870         struct intel_framebuffer *intel_fb;
1871         struct drm_i915_gem_object *obj;
1872         int enable_fbc;
1873
1874         DRM_DEBUG_KMS("\n");
1875
1876         if (!i915_powersave)
1877                 return;
1878
1879         if (!I915_HAS_FBC(dev))
1880                 return;
1881
1882         /*
1883          * If FBC is already on, we just have to verify that we can
1884          * keep it that way...
1885          * Need to disable if:
1886          *   - more than one pipe is active
1887          *   - changing FBC params (stride, fence, mode)
1888          *   - new fb is too large to fit in compressed buffer
1889          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1890          */
1891         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1892                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1893                         if (crtc) {
1894                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896                                 goto out_disable;
1897                         }
1898                         crtc = tmp_crtc;
1899                 }
1900         }
1901
1902         if (!crtc || crtc->fb == NULL) {
1903                 DRM_DEBUG_KMS("no output, disabling\n");
1904                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1905                 goto out_disable;
1906         }
1907
1908         intel_crtc = to_intel_crtc(crtc);
1909         fb = crtc->fb;
1910         intel_fb = to_intel_framebuffer(fb);
1911         obj = intel_fb->obj;
1912
1913         enable_fbc = i915_enable_fbc;
1914         if (enable_fbc < 0) {
1915                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916                 enable_fbc = 1;
1917                 if (INTEL_INFO(dev)->gen <= 6)
1918                         enable_fbc = 0;
1919         }
1920         if (!enable_fbc) {
1921                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923                 goto out_disable;
1924         }
1925         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1926                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1927                               "compression\n");
1928                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1929                 goto out_disable;
1930         }
1931         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1933                 DRM_DEBUG_KMS("mode incompatible with compression, "
1934                               "disabling\n");
1935                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1936                 goto out_disable;
1937         }
1938         if ((crtc->mode.hdisplay > 2048) ||
1939             (crtc->mode.vdisplay > 1536)) {
1940                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1942                 goto out_disable;
1943         }
1944         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1945                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1947                 goto out_disable;
1948         }
1949
1950         /* The use of a CPU fence is mandatory in order to detect writes
1951          * by the CPU to the scanout and trigger updates to the FBC.
1952          */
1953         if (obj->tiling_mode != I915_TILING_X ||
1954             obj->fence_reg == I915_FENCE_REG_NONE) {
1955                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1957                 goto out_disable;
1958         }
1959
1960         /* If the kernel debugger is active, always disable compression */
1961         if (in_dbg_master())
1962                 goto out_disable;
1963
1964         /* If the scanout has not changed, don't modify the FBC settings.
1965          * Note that we make the fundamental assumption that the fb->obj
1966          * cannot be unpinned (and have its GTT offset and fence revoked)
1967          * without first being decoupled from the scanout and FBC disabled.
1968          */
1969         if (dev_priv->cfb_plane == intel_crtc->plane &&
1970             dev_priv->cfb_fb == fb->base.id &&
1971             dev_priv->cfb_y == crtc->y)
1972                 return;
1973
1974         if (intel_fbc_enabled(dev)) {
1975                 /* We update FBC along two paths, after changing fb/crtc
1976                  * configuration (modeswitching) and after page-flipping
1977                  * finishes. For the latter, we know that not only did
1978                  * we disable the FBC at the start of the page-flip
1979                  * sequence, but also more than one vblank has passed.
1980                  *
1981                  * For the former case of modeswitching, it is possible
1982                  * to switch between two FBC valid configurations
1983                  * instantaneously so we do need to disable the FBC
1984                  * before we can modify its control registers. We also
1985                  * have to wait for the next vblank for that to take
1986                  * effect. However, since we delay enabling FBC we can
1987                  * assume that a vblank has passed since disabling and
1988                  * that we can safely alter the registers in the deferred
1989                  * callback.
1990                  *
1991                  * In the scenario that we go from a valid to invalid
1992                  * and then back to valid FBC configuration we have
1993                  * no strict enforcement that a vblank occurred since
1994                  * disabling the FBC. However, along all current pipe
1995                  * disabling paths we do need to wait for a vblank at
1996                  * some point. And we wait before enabling FBC anyway.
1997                  */
1998                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999                 intel_disable_fbc(dev);
2000         }
2001
2002         intel_enable_fbc(crtc, 500);
2003         return;
2004
2005 out_disable:
2006         /* Multiple disables should be harmless */
2007         if (intel_fbc_enabled(dev)) {
2008                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009                 intel_disable_fbc(dev);
2010         }
2011 }
2012
2013 int
2014 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2015                            struct drm_i915_gem_object *obj,
2016                            struct intel_ring_buffer *pipelined)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         u32 alignment;
2020         int ret;
2021
2022         switch (obj->tiling_mode) {
2023         case I915_TILING_NONE:
2024                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025                         alignment = 128 * 1024;
2026                 else if (INTEL_INFO(dev)->gen >= 4)
2027                         alignment = 4 * 1024;
2028                 else
2029                         alignment = 64 * 1024;
2030                 break;
2031         case I915_TILING_X:
2032                 /* pin() will align the object as required by fence */
2033                 alignment = 0;
2034                 break;
2035         case I915_TILING_Y:
2036                 /* FIXME: Is this true? */
2037                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038                 return -EINVAL;
2039         default:
2040                 BUG();
2041         }
2042
2043         dev_priv->mm.interruptible = false;
2044         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2045         if (ret)
2046                 goto err_interruptible;
2047
2048         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049          * fence, whereas 965+ only requires a fence if using
2050          * framebuffer compression.  For simplicity, we always install
2051          * a fence as the cost is not that onerous.
2052          */
2053         if (obj->tiling_mode != I915_TILING_NONE) {
2054                 ret = i915_gem_object_get_fence(obj, pipelined);
2055                 if (ret)
2056                         goto err_unpin;
2057
2058                 i915_gem_object_pin_fence(obj);
2059         }
2060
2061         dev_priv->mm.interruptible = true;
2062         return 0;
2063
2064 err_unpin:
2065         i915_gem_object_unpin(obj);
2066 err_interruptible:
2067         dev_priv->mm.interruptible = true;
2068         return ret;
2069 }
2070
2071 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072 {
2073         i915_gem_object_unpin_fence(obj);
2074         i915_gem_object_unpin(obj);
2075 }
2076
2077 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078                              int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long Start, Offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093                 break;
2094         default:
2095                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096                 return -EINVAL;
2097         }
2098
2099         intel_fb = to_intel_framebuffer(fb);
2100         obj = intel_fb->obj;
2101
2102         reg = DSPCNTR(plane);
2103         dspcntr = I915_READ(reg);
2104         /* Mask out pixel format bits in case we change it */
2105         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106         switch (fb->bits_per_pixel) {
2107         case 8:
2108                 dspcntr |= DISPPLANE_8BPP;
2109                 break;
2110         case 16:
2111                 if (fb->depth == 15)
2112                         dspcntr |= DISPPLANE_15_16BPP;
2113                 else
2114                         dspcntr |= DISPPLANE_16BPP;
2115                 break;
2116         case 24:
2117         case 32:
2118                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119                 break;
2120         default:
2121                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122                 return -EINVAL;
2123         }
2124         if (INTEL_INFO(dev)->gen >= 4) {
2125                 if (obj->tiling_mode != I915_TILING_NONE)
2126                         dspcntr |= DISPPLANE_TILED;
2127                 else
2128                         dspcntr &= ~DISPPLANE_TILED;
2129         }
2130
2131         I915_WRITE(reg, dspcntr);
2132
2133         Start = obj->gtt_offset;
2134         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       Start, Offset, x, y, fb->pitches[0]);
2138         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2139         if (INTEL_INFO(dev)->gen >= 4) {
2140                 I915_WRITE(DSPSURF(plane), Start);
2141                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142                 I915_WRITE(DSPADDR(plane), Offset);
2143         } else
2144                 I915_WRITE(DSPADDR(plane), Start + Offset);
2145         POSTING_READ(reg);
2146
2147         return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151                                  struct drm_framebuffer *fb, int x, int y)
2152 {
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156         struct intel_framebuffer *intel_fb;
2157         struct drm_i915_gem_object *obj;
2158         int plane = intel_crtc->plane;
2159         unsigned long Start, Offset;
2160         u32 dspcntr;
2161         u32 reg;
2162
2163         switch (plane) {
2164         case 0:
2165         case 1:
2166         case 2:
2167                 break;
2168         default:
2169                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170                 return -EINVAL;
2171         }
2172
2173         intel_fb = to_intel_framebuffer(fb);
2174         obj = intel_fb->obj;
2175
2176         reg = DSPCNTR(plane);
2177         dspcntr = I915_READ(reg);
2178         /* Mask out pixel format bits in case we change it */
2179         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180         switch (fb->bits_per_pixel) {
2181         case 8:
2182                 dspcntr |= DISPPLANE_8BPP;
2183                 break;
2184         case 16:
2185                 if (fb->depth != 16)
2186                         return -EINVAL;
2187
2188                 dspcntr |= DISPPLANE_16BPP;
2189                 break;
2190         case 24:
2191         case 32:
2192                 if (fb->depth == 24)
2193                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194                 else if (fb->depth == 30)
2195                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196                 else
2197                         return -EINVAL;
2198                 break;
2199         default:
2200                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201                 return -EINVAL;
2202         }
2203
2204         if (obj->tiling_mode != I915_TILING_NONE)
2205                 dspcntr |= DISPPLANE_TILED;
2206         else
2207                 dspcntr &= ~DISPPLANE_TILED;
2208
2209         /* must disable */
2210         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212         I915_WRITE(reg, dspcntr);
2213
2214         Start = obj->gtt_offset;
2215         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2216
2217         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218                       Start, Offset, x, y, fb->pitches[0]);
2219         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2220         I915_WRITE(DSPSURF(plane), Start);
2221         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222         I915_WRITE(DSPADDR(plane), Offset);
2223         POSTING_READ(reg);
2224
2225         return 0;
2226 }
2227
2228 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2229 static int
2230 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231                            int x, int y, enum mode_set_atomic state)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         int ret;
2236
2237         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238         if (ret)
2239                 return ret;
2240
2241         intel_update_fbc(dev);
2242         intel_increase_pllclock(crtc);
2243
2244         return 0;
2245 }
2246
2247 static int
2248 intel_finish_fb(struct drm_framebuffer *old_fb)
2249 {
2250         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2251         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2252         bool was_interruptible = dev_priv->mm.interruptible;
2253         int ret;
2254
2255         wait_event(dev_priv->pending_flip_queue,
2256                    atomic_read(&dev_priv->mm.wedged) ||
2257                    atomic_read(&obj->pending_flip) == 0);
2258
2259         /* Big Hammer, we also need to ensure that any pending
2260          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2261          * current scanout is retired before unpinning the old
2262          * framebuffer.
2263          *
2264          * This should only fail upon a hung GPU, in which case we
2265          * can safely continue.
2266          */
2267         dev_priv->mm.interruptible = false;
2268         ret = i915_gem_object_finish_gpu(obj);
2269         dev_priv->mm.interruptible = was_interruptible;
2270
2271         return ret;
2272 }
2273
2274 static int
2275 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2276                     struct drm_framebuffer *old_fb)
2277 {
2278         struct drm_device *dev = crtc->dev;
2279         struct drm_i915_master_private *master_priv;
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int ret;
2282
2283         /* no fb bound */
2284         if (!crtc->fb) {
2285                 DRM_ERROR("No FB bound\n");
2286                 return 0;
2287         }
2288
2289         switch (intel_crtc->plane) {
2290         case 0:
2291         case 1:
2292                 break;
2293         case 2:
2294                 if (IS_IVYBRIDGE(dev))
2295                         break;
2296                 /* fall through otherwise */
2297         default:
2298                 DRM_ERROR("no plane for crtc\n");
2299                 return -EINVAL;
2300         }
2301
2302         mutex_lock(&dev->struct_mutex);
2303         ret = intel_pin_and_fence_fb_obj(dev,
2304                                          to_intel_framebuffer(crtc->fb)->obj,
2305                                          NULL);
2306         if (ret != 0) {
2307                 mutex_unlock(&dev->struct_mutex);
2308                 DRM_ERROR("pin & fence failed\n");
2309                 return ret;
2310         }
2311
2312         if (old_fb)
2313                 intel_finish_fb(old_fb);
2314
2315         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2316                                          LEAVE_ATOMIC_MODE_SET);
2317         if (ret) {
2318                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("failed to update base address\n");
2321                 return ret;
2322         }
2323
2324         if (old_fb) {
2325                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2326                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2327         }
2328
2329         mutex_unlock(&dev->struct_mutex);
2330
2331         if (!dev->primary->master)
2332                 return 0;
2333
2334         master_priv = dev->primary->master->driver_priv;
2335         if (!master_priv->sarea_priv)
2336                 return 0;
2337
2338         if (intel_crtc->pipe) {
2339                 master_priv->sarea_priv->pipeB_x = x;
2340                 master_priv->sarea_priv->pipeB_y = y;
2341         } else {
2342                 master_priv->sarea_priv->pipeA_x = x;
2343                 master_priv->sarea_priv->pipeA_y = y;
2344         }
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 /* The FDI link training functions for ILK/Ibexpeak. */
2440 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2441 {
2442         struct drm_device *dev = crtc->dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445         int pipe = intel_crtc->pipe;
2446         int plane = intel_crtc->plane;
2447         u32 reg, temp, tries;
2448
2449         /* FDI needs bits from pipe & plane first */
2450         assert_pipe_enabled(dev_priv, pipe);
2451         assert_plane_enabled(dev_priv, plane);
2452
2453         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2454            for train result */
2455         reg = FDI_RX_IMR(pipe);
2456         temp = I915_READ(reg);
2457         temp &= ~FDI_RX_SYMBOL_LOCK;
2458         temp &= ~FDI_RX_BIT_LOCK;
2459         I915_WRITE(reg, temp);
2460         I915_READ(reg);
2461         udelay(150);
2462
2463         /* enable CPU FDI TX and PCH FDI RX */
2464         reg = FDI_TX_CTL(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~(7 << 19);
2467         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2468         temp &= ~FDI_LINK_TRAIN_NONE;
2469         temp |= FDI_LINK_TRAIN_PATTERN_1;
2470         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2471
2472         reg = FDI_RX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~FDI_LINK_TRAIN_NONE;
2475         temp |= FDI_LINK_TRAIN_PATTERN_1;
2476         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2477
2478         POSTING_READ(reg);
2479         udelay(150);
2480
2481         /* Ironlake workaround, enable clock pointer after FDI enable*/
2482         if (HAS_PCH_IBX(dev)) {
2483                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2484                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2485                            FDI_RX_PHASE_SYNC_POINTER_EN);
2486         }
2487
2488         reg = FDI_RX_IIR(pipe);
2489         for (tries = 0; tries < 5; tries++) {
2490                 temp = I915_READ(reg);
2491                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2492
2493                 if ((temp & FDI_RX_BIT_LOCK)) {
2494                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2495                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2496                         break;
2497                 }
2498         }
2499         if (tries == 5)
2500                 DRM_ERROR("FDI train 1 fail!\n");
2501
2502         /* Train 2 */
2503         reg = FDI_TX_CTL(pipe);
2504         temp = I915_READ(reg);
2505         temp &= ~FDI_LINK_TRAIN_NONE;
2506         temp |= FDI_LINK_TRAIN_PATTERN_2;
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         temp &= ~FDI_LINK_TRAIN_NONE;
2512         temp |= FDI_LINK_TRAIN_PATTERN_2;
2513         I915_WRITE(reg, temp);
2514
2515         POSTING_READ(reg);
2516         udelay(150);
2517
2518         reg = FDI_RX_IIR(pipe);
2519         for (tries = 0; tries < 5; tries++) {
2520                 temp = I915_READ(reg);
2521                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523                 if (temp & FDI_RX_SYMBOL_LOCK) {
2524                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2525                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2526                         break;
2527                 }
2528         }
2529         if (tries == 5)
2530                 DRM_ERROR("FDI train 2 fail!\n");
2531
2532         DRM_DEBUG_KMS("FDI train done\n");
2533
2534 }
2535
2536 static const int snb_b_fdi_train_param[] = {
2537         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2538         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2539         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2540         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2541 };
2542
2543 /* The FDI link training functions for SNB/Cougarpoint. */
2544 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2545 {
2546         struct drm_device *dev = crtc->dev;
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549         int pipe = intel_crtc->pipe;
2550         u32 reg, temp, i;
2551
2552         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553            for train result */
2554         reg = FDI_RX_IMR(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~FDI_RX_SYMBOL_LOCK;
2557         temp &= ~FDI_RX_BIT_LOCK;
2558         I915_WRITE(reg, temp);
2559
2560         POSTING_READ(reg);
2561         udelay(150);
2562
2563         /* enable CPU FDI TX and PCH FDI RX */
2564         reg = FDI_TX_CTL(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~(7 << 19);
2567         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2568         temp &= ~FDI_LINK_TRAIN_NONE;
2569         temp |= FDI_LINK_TRAIN_PATTERN_1;
2570         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571         /* SNB-B */
2572         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2574
2575         reg = FDI_RX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         if (HAS_PCH_CPT(dev)) {
2578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580         } else {
2581                 temp &= ~FDI_LINK_TRAIN_NONE;
2582                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583         }
2584         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2585
2586         POSTING_READ(reg);
2587         udelay(150);
2588
2589         if (HAS_PCH_CPT(dev))
2590                 cpt_phase_pointer_enable(dev, pipe);
2591
2592         for (i = 0; i < 4; i++) {
2593                 reg = FDI_TX_CTL(pipe);
2594                 temp = I915_READ(reg);
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 temp |= snb_b_fdi_train_param[i];
2597                 I915_WRITE(reg, temp);
2598
2599                 POSTING_READ(reg);
2600                 udelay(500);
2601
2602                 reg = FDI_RX_IIR(pipe);
2603                 temp = I915_READ(reg);
2604                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2605
2606                 if (temp & FDI_RX_BIT_LOCK) {
2607                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2608                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2609                         break;
2610                 }
2611         }
2612         if (i == 4)
2613                 DRM_ERROR("FDI train 1 fail!\n");
2614
2615         /* Train 2 */
2616         reg = FDI_TX_CTL(pipe);
2617         temp = I915_READ(reg);
2618         temp &= ~FDI_LINK_TRAIN_NONE;
2619         temp |= FDI_LINK_TRAIN_PATTERN_2;
2620         if (IS_GEN6(dev)) {
2621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622                 /* SNB-B */
2623                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2624         }
2625         I915_WRITE(reg, temp);
2626
2627         reg = FDI_RX_CTL(pipe);
2628         temp = I915_READ(reg);
2629         if (HAS_PCH_CPT(dev)) {
2630                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2632         } else {
2633                 temp &= ~FDI_LINK_TRAIN_NONE;
2634                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2635         }
2636         I915_WRITE(reg, temp);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 reg = FDI_RX_IIR(pipe);
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if (temp & FDI_RX_SYMBOL_LOCK) {
2656                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 2 fail!\n");
2663
2664         DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 /* Manual link training for Ivy Bridge A0 parts */
2668 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         int pipe = intel_crtc->pipe;
2674         u32 reg, temp, i;
2675
2676         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2677            for train result */
2678         reg = FDI_RX_IMR(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_RX_SYMBOL_LOCK;
2681         temp &= ~FDI_RX_BIT_LOCK;
2682         I915_WRITE(reg, temp);
2683
2684         POSTING_READ(reg);
2685         udelay(150);
2686
2687         /* enable CPU FDI TX and PCH FDI RX */
2688         reg = FDI_TX_CTL(pipe);
2689         temp = I915_READ(reg);
2690         temp &= ~(7 << 19);
2691         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2692         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2693         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2694         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2696         temp |= FDI_COMPOSITE_SYNC;
2697         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2698
2699         reg = FDI_RX_CTL(pipe);
2700         temp = I915_READ(reg);
2701         temp &= ~FDI_LINK_TRAIN_AUTO;
2702         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2703         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2704         temp |= FDI_COMPOSITE_SYNC;
2705         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2706
2707         POSTING_READ(reg);
2708         udelay(150);
2709
2710         if (HAS_PCH_CPT(dev))
2711                 cpt_phase_pointer_enable(dev, pipe);
2712
2713         for (i = 0; i < 4; i++) {
2714                 reg = FDI_TX_CTL(pipe);
2715                 temp = I915_READ(reg);
2716                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717                 temp |= snb_b_fdi_train_param[i];
2718                 I915_WRITE(reg, temp);
2719
2720                 POSTING_READ(reg);
2721                 udelay(500);
2722
2723                 reg = FDI_RX_IIR(pipe);
2724                 temp = I915_READ(reg);
2725                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2726
2727                 if (temp & FDI_RX_BIT_LOCK ||
2728                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2729                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2730                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2731                         break;
2732                 }
2733         }
2734         if (i == 4)
2735                 DRM_ERROR("FDI train 1 fail!\n");
2736
2737         /* Train 2 */
2738         reg = FDI_TX_CTL(pipe);
2739         temp = I915_READ(reg);
2740         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2741         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2742         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2744         I915_WRITE(reg, temp);
2745
2746         reg = FDI_RX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2750         I915_WRITE(reg, temp);
2751
2752         POSTING_READ(reg);
2753         udelay(150);
2754
2755         for (i = 0; i < 4; i++) {
2756                 reg = FDI_TX_CTL(pipe);
2757                 temp = I915_READ(reg);
2758                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2759                 temp |= snb_b_fdi_train_param[i];
2760                 I915_WRITE(reg, temp);
2761
2762                 POSTING_READ(reg);
2763                 udelay(500);
2764
2765                 reg = FDI_RX_IIR(pipe);
2766                 temp = I915_READ(reg);
2767                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2768
2769                 if (temp & FDI_RX_SYMBOL_LOCK) {
2770                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2771                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2772                         break;
2773                 }
2774         }
2775         if (i == 4)
2776                 DRM_ERROR("FDI train 2 fail!\n");
2777
2778         DRM_DEBUG_KMS("FDI train done.\n");
2779 }
2780
2781 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2782 {
2783         struct drm_device *dev = crtc->dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786         int pipe = intel_crtc->pipe;
2787         u32 reg, temp;
2788
2789         /* Write the TU size bits so error detection works */
2790         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2791                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2792
2793         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2794         reg = FDI_RX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~((0x7 << 19) | (0x7 << 16));
2797         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2798         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2799         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2800
2801         POSTING_READ(reg);
2802         udelay(200);
2803
2804         /* Switch from Rawclk to PCDclk */
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp | FDI_PCDCLK);
2807
2808         POSTING_READ(reg);
2809         udelay(200);
2810
2811         /* Enable CPU FDI TX PLL, always on for Ironlake */
2812         reg = FDI_TX_CTL(pipe);
2813         temp = I915_READ(reg);
2814         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2815                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2816
2817                 POSTING_READ(reg);
2818                 udelay(100);
2819         }
2820 }
2821
2822 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         u32 flags = I915_READ(SOUTH_CHICKEN1);
2826
2827         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2828         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2829         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2830         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2831         POSTING_READ(SOUTH_CHICKEN1);
2832 }
2833 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2834 {
2835         struct drm_device *dev = crtc->dev;
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838         int pipe = intel_crtc->pipe;
2839         u32 reg, temp;
2840
2841         /* disable CPU FDI tx and PCH FDI rx */
2842         reg = FDI_TX_CTL(pipe);
2843         temp = I915_READ(reg);
2844         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2845         POSTING_READ(reg);
2846
2847         reg = FDI_RX_CTL(pipe);
2848         temp = I915_READ(reg);
2849         temp &= ~(0x7 << 16);
2850         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2851         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2852
2853         POSTING_READ(reg);
2854         udelay(100);
2855
2856         /* Ironlake workaround, disable clock pointer after downing FDI */
2857         if (HAS_PCH_IBX(dev)) {
2858                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2859                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2860                            I915_READ(FDI_RX_CHICKEN(pipe) &
2861                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2862         } else if (HAS_PCH_CPT(dev)) {
2863                 cpt_phase_pointer_disable(dev, pipe);
2864         }
2865
2866         /* still set train pattern 1 */
2867         reg = FDI_TX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~FDI_LINK_TRAIN_NONE;
2870         temp |= FDI_LINK_TRAIN_PATTERN_1;
2871         I915_WRITE(reg, temp);
2872
2873         reg = FDI_RX_CTL(pipe);
2874         temp = I915_READ(reg);
2875         if (HAS_PCH_CPT(dev)) {
2876                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2877                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2878         } else {
2879                 temp &= ~FDI_LINK_TRAIN_NONE;
2880                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2881         }
2882         /* BPC in FDI rx is consistent with that in PIPECONF */
2883         temp &= ~(0x07 << 16);
2884         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2885         I915_WRITE(reg, temp);
2886
2887         POSTING_READ(reg);
2888         udelay(100);
2889 }
2890
2891 /*
2892  * When we disable a pipe, we need to clear any pending scanline wait events
2893  * to avoid hanging the ring, which we assume we are waiting on.
2894  */
2895 static void intel_clear_scanline_wait(struct drm_device *dev)
2896 {
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct intel_ring_buffer *ring;
2899         u32 tmp;
2900
2901         if (IS_GEN2(dev))
2902                 /* Can't break the hang on i8xx */
2903                 return;
2904
2905         ring = LP_RING(dev_priv);
2906         tmp = I915_READ_CTL(ring);
2907         if (tmp & RING_WAIT)
2908                 I915_WRITE_CTL(ring, tmp);
2909 }
2910
2911 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2912 {
2913         struct drm_i915_gem_object *obj;
2914         struct drm_i915_private *dev_priv;
2915
2916         if (crtc->fb == NULL)
2917                 return;
2918
2919         obj = to_intel_framebuffer(crtc->fb)->obj;
2920         dev_priv = crtc->dev->dev_private;
2921         wait_event(dev_priv->pending_flip_queue,
2922                    atomic_read(&obj->pending_flip) == 0);
2923 }
2924
2925 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2926 {
2927         struct drm_device *dev = crtc->dev;
2928         struct drm_mode_config *mode_config = &dev->mode_config;
2929         struct intel_encoder *encoder;
2930
2931         /*
2932          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2933          * must be driven by its own crtc; no sharing is possible.
2934          */
2935         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2936                 if (encoder->base.crtc != crtc)
2937                         continue;
2938
2939                 switch (encoder->type) {
2940                 case INTEL_OUTPUT_EDP:
2941                         if (!intel_encoder_is_pch_edp(&encoder->base))
2942                                 return false;
2943                         continue;
2944                 }
2945         }
2946
2947         return true;
2948 }
2949
2950 /*
2951  * Enable PCH resources required for PCH ports:
2952  *   - PCH PLLs
2953  *   - FDI training & RX/TX
2954  *   - update transcoder timings
2955  *   - DP transcoding bits
2956  *   - transcoder
2957  */
2958 static void ironlake_pch_enable(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         int pipe = intel_crtc->pipe;
2964         u32 reg, temp, transc_sel;
2965
2966         /* For PCH output, training FDI link */
2967         dev_priv->display.fdi_link_train(crtc);
2968
2969         intel_enable_pch_pll(dev_priv, pipe);
2970
2971         if (HAS_PCH_CPT(dev)) {
2972                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2973                         TRANSC_DPLLB_SEL;
2974
2975                 /* Be sure PCH DPLL SEL is set */
2976                 temp = I915_READ(PCH_DPLL_SEL);
2977                 if (pipe == 0) {
2978                         temp &= ~(TRANSA_DPLLB_SEL);
2979                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2980                 } else if (pipe == 1) {
2981                         temp &= ~(TRANSB_DPLLB_SEL);
2982                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2983                 } else if (pipe == 2) {
2984                         temp &= ~(TRANSC_DPLLB_SEL);
2985                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2986                 }
2987                 I915_WRITE(PCH_DPLL_SEL, temp);
2988         }
2989
2990         /* set transcoder timing, panel must allow it */
2991         assert_panel_unlocked(dev_priv, pipe);
2992         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2993         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2994         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2995
2996         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2997         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2998         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2999         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3000
3001         intel_fdi_normal_train(crtc);
3002
3003         /* For PCH DP, enable TRANS_DP_CTL */
3004         if (HAS_PCH_CPT(dev) &&
3005             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3006              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3007                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3008                 reg = TRANS_DP_CTL(pipe);
3009                 temp = I915_READ(reg);
3010                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3011                           TRANS_DP_SYNC_MASK |
3012                           TRANS_DP_BPC_MASK);
3013                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3014                          TRANS_DP_ENH_FRAMING);
3015                 temp |= bpc << 9; /* same format but at 11:9 */
3016
3017                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3018                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3019                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3020                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3021
3022                 switch (intel_trans_dp_port_sel(crtc)) {
3023                 case PCH_DP_B:
3024                         temp |= TRANS_DP_PORT_SEL_B;
3025                         break;
3026                 case PCH_DP_C:
3027                         temp |= TRANS_DP_PORT_SEL_C;
3028                         break;
3029                 case PCH_DP_D:
3030                         temp |= TRANS_DP_PORT_SEL_D;
3031                         break;
3032                 default:
3033                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3034                         temp |= TRANS_DP_PORT_SEL_B;
3035                         break;
3036                 }
3037
3038                 I915_WRITE(reg, temp);
3039         }
3040
3041         intel_enable_transcoder(dev_priv, pipe);
3042 }
3043
3044 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3045 {
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3048         u32 temp;
3049
3050         temp = I915_READ(dslreg);
3051         udelay(500);
3052         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3053                 /* Without this, mode sets may fail silently on FDI */
3054                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3055                 udelay(250);
3056                 I915_WRITE(tc2reg, 0);
3057                 if (wait_for(I915_READ(dslreg) != temp, 5))
3058                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3059         }
3060 }
3061
3062 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3063 {
3064         struct drm_device *dev = crtc->dev;
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067         int pipe = intel_crtc->pipe;
3068         int plane = intel_crtc->plane;
3069         u32 temp;
3070         bool is_pch_port;
3071
3072         if (intel_crtc->active)
3073                 return;
3074
3075         intel_crtc->active = true;
3076         intel_update_watermarks(dev);
3077
3078         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3079                 temp = I915_READ(PCH_LVDS);
3080                 if ((temp & LVDS_PORT_EN) == 0)
3081                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3082         }
3083
3084         is_pch_port = intel_crtc_driving_pch(crtc);
3085
3086         if (is_pch_port)
3087                 ironlake_fdi_pll_enable(crtc);
3088         else
3089                 ironlake_fdi_disable(crtc);
3090
3091         /* Enable panel fitting for LVDS */
3092         if (dev_priv->pch_pf_size &&
3093             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3094                 /* Force use of hard-coded filter coefficients
3095                  * as some pre-programmed values are broken,
3096                  * e.g. x201.
3097                  */
3098                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3099                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3100                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3101         }
3102
3103         /*
3104          * On ILK+ LUT must be loaded before the pipe is running but with
3105          * clocks enabled
3106          */
3107         intel_crtc_load_lut(crtc);
3108
3109         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3110         intel_enable_plane(dev_priv, plane, pipe);
3111
3112         if (is_pch_port)
3113                 ironlake_pch_enable(crtc);
3114
3115         mutex_lock(&dev->struct_mutex);
3116         intel_update_fbc(dev);
3117         mutex_unlock(&dev->struct_mutex);
3118
3119         intel_crtc_update_cursor(crtc, true);
3120 }
3121
3122 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3123 {
3124         struct drm_device *dev = crtc->dev;
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127         int pipe = intel_crtc->pipe;
3128         int plane = intel_crtc->plane;
3129         u32 reg, temp;
3130
3131         if (!intel_crtc->active)
3132                 return;
3133
3134         intel_crtc_wait_for_pending_flips(crtc);
3135         drm_vblank_off(dev, pipe);
3136         intel_crtc_update_cursor(crtc, false);
3137
3138         intel_disable_plane(dev_priv, plane, pipe);
3139
3140         if (dev_priv->cfb_plane == plane)
3141                 intel_disable_fbc(dev);
3142
3143         intel_disable_pipe(dev_priv, pipe);
3144
3145         /* Disable PF */
3146         I915_WRITE(PF_CTL(pipe), 0);
3147         I915_WRITE(PF_WIN_SZ(pipe), 0);
3148
3149         ironlake_fdi_disable(crtc);
3150
3151         /* This is a horrible layering violation; we should be doing this in
3152          * the connector/encoder ->prepare instead, but we don't always have
3153          * enough information there about the config to know whether it will
3154          * actually be necessary or just cause undesired flicker.
3155          */
3156         intel_disable_pch_ports(dev_priv, pipe);
3157
3158         intel_disable_transcoder(dev_priv, pipe);
3159
3160         if (HAS_PCH_CPT(dev)) {
3161                 /* disable TRANS_DP_CTL */
3162                 reg = TRANS_DP_CTL(pipe);
3163                 temp = I915_READ(reg);
3164                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3165                 temp |= TRANS_DP_PORT_SEL_NONE;
3166                 I915_WRITE(reg, temp);
3167
3168                 /* disable DPLL_SEL */
3169                 temp = I915_READ(PCH_DPLL_SEL);
3170                 switch (pipe) {
3171                 case 0:
3172                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3173                         break;
3174                 case 1:
3175                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3176                         break;
3177                 case 2:
3178                         /* C shares PLL A or B */
3179                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3180                         break;
3181                 default:
3182                         BUG(); /* wtf */
3183                 }
3184                 I915_WRITE(PCH_DPLL_SEL, temp);
3185         }
3186
3187         /* disable PCH DPLL */
3188         if (!intel_crtc->no_pll)
3189                 intel_disable_pch_pll(dev_priv, pipe);
3190
3191         /* Switch from PCDclk to Rawclk */
3192         reg = FDI_RX_CTL(pipe);
3193         temp = I915_READ(reg);
3194         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3195
3196         /* Disable CPU FDI TX PLL */
3197         reg = FDI_TX_CTL(pipe);
3198         temp = I915_READ(reg);
3199         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3200
3201         POSTING_READ(reg);
3202         udelay(100);
3203
3204         reg = FDI_RX_CTL(pipe);
3205         temp = I915_READ(reg);
3206         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3207
3208         /* Wait for the clocks to turn off. */
3209         POSTING_READ(reg);
3210         udelay(100);
3211
3212         intel_crtc->active = false;
3213         intel_update_watermarks(dev);
3214
3215         mutex_lock(&dev->struct_mutex);
3216         intel_update_fbc(dev);
3217         intel_clear_scanline_wait(dev);
3218         mutex_unlock(&dev->struct_mutex);
3219 }
3220
3221 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3222 {
3223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224         int pipe = intel_crtc->pipe;
3225         int plane = intel_crtc->plane;
3226
3227         /* XXX: When our outputs are all unaware of DPMS modes other than off
3228          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3229          */
3230         switch (mode) {
3231         case DRM_MODE_DPMS_ON:
3232         case DRM_MODE_DPMS_STANDBY:
3233         case DRM_MODE_DPMS_SUSPEND:
3234                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3235                 ironlake_crtc_enable(crtc);
3236                 break;
3237
3238         case DRM_MODE_DPMS_OFF:
3239                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3240                 ironlake_crtc_disable(crtc);
3241                 break;
3242         }
3243 }
3244
3245 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3246 {
3247         if (!enable && intel_crtc->overlay) {
3248                 struct drm_device *dev = intel_crtc->base.dev;
3249                 struct drm_i915_private *dev_priv = dev->dev_private;
3250
3251                 mutex_lock(&dev->struct_mutex);
3252                 dev_priv->mm.interruptible = false;
3253                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3254                 dev_priv->mm.interruptible = true;
3255                 mutex_unlock(&dev->struct_mutex);
3256         }
3257
3258         /* Let userspace switch the overlay on again. In most cases userspace
3259          * has to recompute where to put it anyway.
3260          */
3261 }
3262
3263 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3264 {
3265         struct drm_device *dev = crtc->dev;
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3268         int pipe = intel_crtc->pipe;
3269         int plane = intel_crtc->plane;
3270
3271         if (intel_crtc->active)
3272                 return;
3273
3274         intel_crtc->active = true;
3275         intel_update_watermarks(dev);
3276
3277         intel_enable_pll(dev_priv, pipe);
3278         intel_enable_pipe(dev_priv, pipe, false);
3279         intel_enable_plane(dev_priv, plane, pipe);
3280
3281         intel_crtc_load_lut(crtc);
3282         intel_update_fbc(dev);
3283
3284         /* Give the overlay scaler a chance to enable if it's on this pipe */
3285         intel_crtc_dpms_overlay(intel_crtc, true);
3286         intel_crtc_update_cursor(crtc, true);
3287 }
3288
3289 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3290 {
3291         struct drm_device *dev = crtc->dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         int pipe = intel_crtc->pipe;
3295         int plane = intel_crtc->plane;
3296
3297         if (!intel_crtc->active)
3298                 return;
3299
3300         /* Give the overlay scaler a chance to disable if it's on this pipe */
3301         intel_crtc_wait_for_pending_flips(crtc);
3302         drm_vblank_off(dev, pipe);
3303         intel_crtc_dpms_overlay(intel_crtc, false);
3304         intel_crtc_update_cursor(crtc, false);
3305
3306         if (dev_priv->cfb_plane == plane)
3307                 intel_disable_fbc(dev);
3308
3309         intel_disable_plane(dev_priv, plane, pipe);
3310         intel_disable_pipe(dev_priv, pipe);
3311         intel_disable_pll(dev_priv, pipe);
3312
3313         intel_crtc->active = false;
3314         intel_update_fbc(dev);
3315         intel_update_watermarks(dev);
3316         intel_clear_scanline_wait(dev);
3317 }
3318
3319 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3320 {
3321         /* XXX: When our outputs are all unaware of DPMS modes other than off
3322          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3323          */
3324         switch (mode) {
3325         case DRM_MODE_DPMS_ON:
3326         case DRM_MODE_DPMS_STANDBY:
3327         case DRM_MODE_DPMS_SUSPEND:
3328                 i9xx_crtc_enable(crtc);
3329                 break;
3330         case DRM_MODE_DPMS_OFF:
3331                 i9xx_crtc_disable(crtc);
3332                 break;
3333         }
3334 }
3335
3336 /**
3337  * Sets the power management mode of the pipe and plane.
3338  */
3339 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3340 {
3341         struct drm_device *dev = crtc->dev;
3342         struct drm_i915_private *dev_priv = dev->dev_private;
3343         struct drm_i915_master_private *master_priv;
3344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345         int pipe = intel_crtc->pipe;
3346         bool enabled;
3347
3348         if (intel_crtc->dpms_mode == mode)
3349                 return;
3350
3351         intel_crtc->dpms_mode = mode;
3352
3353         dev_priv->display.dpms(crtc, mode);
3354
3355         if (!dev->primary->master)
3356                 return;
3357
3358         master_priv = dev->primary->master->driver_priv;
3359         if (!master_priv->sarea_priv)
3360                 return;
3361
3362         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3363
3364         switch (pipe) {
3365         case 0:
3366                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3367                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3368                 break;
3369         case 1:
3370                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3371                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3372                 break;
3373         default:
3374                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3375                 break;
3376         }
3377 }
3378
3379 static void intel_crtc_disable(struct drm_crtc *crtc)
3380 {
3381         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3382         struct drm_device *dev = crtc->dev;
3383
3384         /* Flush any pending WAITs before we disable the pipe. Note that
3385          * we need to drop the struct_mutex in order to acquire it again
3386          * during the lowlevel dpms routines around a couple of the
3387          * operations. It does not look trivial nor desirable to move
3388          * that locking higher. So instead we leave a window for the
3389          * submission of further commands on the fb before we can actually
3390          * disable it. This race with userspace exists anyway, and we can
3391          * only rely on the pipe being disabled by userspace after it
3392          * receives the hotplug notification and has flushed any pending
3393          * batches.
3394          */
3395         if (crtc->fb) {
3396                 mutex_lock(&dev->struct_mutex);
3397                 intel_finish_fb(crtc->fb);
3398                 mutex_unlock(&dev->struct_mutex);
3399         }
3400
3401         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3402         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3403         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3404
3405         if (crtc->fb) {
3406                 mutex_lock(&dev->struct_mutex);
3407                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3408                 mutex_unlock(&dev->struct_mutex);
3409         }
3410 }
3411
3412 /* Prepare for a mode set.
3413  *
3414  * Note we could be a lot smarter here.  We need to figure out which outputs
3415  * will be enabled, which disabled (in short, how the config will changes)
3416  * and perform the minimum necessary steps to accomplish that, e.g. updating
3417  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3418  * panel fitting is in the proper state, etc.
3419  */
3420 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3421 {
3422         i9xx_crtc_disable(crtc);
3423 }
3424
3425 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3426 {
3427         i9xx_crtc_enable(crtc);
3428 }
3429
3430 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3431 {
3432         ironlake_crtc_disable(crtc);
3433 }
3434
3435 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3436 {
3437         ironlake_crtc_enable(crtc);
3438 }
3439
3440 void intel_encoder_prepare(struct drm_encoder *encoder)
3441 {
3442         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3443         /* lvds has its own version of prepare see intel_lvds_prepare */
3444         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3445 }
3446
3447 void intel_encoder_commit(struct drm_encoder *encoder)
3448 {
3449         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3450         struct drm_device *dev = encoder->dev;
3451         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3452         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3453
3454         /* lvds has its own version of commit see intel_lvds_commit */
3455         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3456
3457         if (HAS_PCH_CPT(dev))
3458                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3459 }
3460
3461 void intel_encoder_destroy(struct drm_encoder *encoder)
3462 {
3463         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3464
3465         drm_encoder_cleanup(encoder);
3466         kfree(intel_encoder);
3467 }
3468
3469 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3470                                   struct drm_display_mode *mode,
3471                                   struct drm_display_mode *adjusted_mode)
3472 {
3473         struct drm_device *dev = crtc->dev;
3474
3475         if (HAS_PCH_SPLIT(dev)) {
3476                 /* FDI link clock is fixed at 2.7G */
3477                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3478                         return false;
3479         }
3480
3481         /* All interlaced capable intel hw wants timings in frames. */
3482         drm_mode_set_crtcinfo(adjusted_mode, 0);
3483
3484         return true;
3485 }
3486
3487 static int i945_get_display_clock_speed(struct drm_device *dev)
3488 {
3489         return 400000;
3490 }
3491
3492 static int i915_get_display_clock_speed(struct drm_device *dev)
3493 {
3494         return 333000;
3495 }
3496
3497 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3498 {
3499         return 200000;
3500 }
3501
3502 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3503 {
3504         u16 gcfgc = 0;
3505
3506         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3507
3508         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3509                 return 133000;
3510         else {
3511                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3512                 case GC_DISPLAY_CLOCK_333_MHZ:
3513                         return 333000;
3514                 default:
3515                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3516                         return 190000;
3517                 }
3518         }
3519 }
3520
3521 static int i865_get_display_clock_speed(struct drm_device *dev)
3522 {
3523         return 266000;
3524 }
3525
3526 static int i855_get_display_clock_speed(struct drm_device *dev)
3527 {
3528         u16 hpllcc = 0;
3529         /* Assume that the hardware is in the high speed state.  This
3530          * should be the default.
3531          */
3532         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3533         case GC_CLOCK_133_200:
3534         case GC_CLOCK_100_200:
3535                 return 200000;
3536         case GC_CLOCK_166_250:
3537                 return 250000;
3538         case GC_CLOCK_100_133:
3539                 return 133000;
3540         }
3541
3542         /* Shouldn't happen */
3543         return 0;
3544 }
3545
3546 static int i830_get_display_clock_speed(struct drm_device *dev)
3547 {
3548         return 133000;
3549 }
3550
3551 struct fdi_m_n {
3552         u32        tu;
3553         u32        gmch_m;
3554         u32        gmch_n;
3555         u32        link_m;
3556         u32        link_n;
3557 };
3558
3559 static void
3560 fdi_reduce_ratio(u32 *num, u32 *den)
3561 {
3562         while (*num > 0xffffff || *den > 0xffffff) {
3563                 *num >>= 1;
3564                 *den >>= 1;
3565         }
3566 }
3567
3568 static void
3569 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3570                      int link_clock, struct fdi_m_n *m_n)
3571 {
3572         m_n->tu = 64; /* default size */
3573
3574         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3575         m_n->gmch_m = bits_per_pixel * pixel_clock;
3576         m_n->gmch_n = link_clock * nlanes * 8;
3577         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3578
3579         m_n->link_m = pixel_clock;
3580         m_n->link_n = link_clock;
3581         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3582 }
3583
3584
3585 struct intel_watermark_params {
3586         unsigned long fifo_size;
3587         unsigned long max_wm;
3588         unsigned long default_wm;
3589         unsigned long guard_size;
3590         unsigned long cacheline_size;
3591 };
3592
3593 /* Pineview has different values for various configs */
3594 static const struct intel_watermark_params pineview_display_wm = {
3595         PINEVIEW_DISPLAY_FIFO,
3596         PINEVIEW_MAX_WM,
3597         PINEVIEW_DFT_WM,
3598         PINEVIEW_GUARD_WM,
3599         PINEVIEW_FIFO_LINE_SIZE
3600 };
3601 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3602         PINEVIEW_DISPLAY_FIFO,
3603         PINEVIEW_MAX_WM,
3604         PINEVIEW_DFT_HPLLOFF_WM,
3605         PINEVIEW_GUARD_WM,
3606         PINEVIEW_FIFO_LINE_SIZE
3607 };
3608 static const struct intel_watermark_params pineview_cursor_wm = {
3609         PINEVIEW_CURSOR_FIFO,
3610         PINEVIEW_CURSOR_MAX_WM,
3611         PINEVIEW_CURSOR_DFT_WM,
3612         PINEVIEW_CURSOR_GUARD_WM,
3613         PINEVIEW_FIFO_LINE_SIZE,
3614 };
3615 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3616         PINEVIEW_CURSOR_FIFO,
3617         PINEVIEW_CURSOR_MAX_WM,
3618         PINEVIEW_CURSOR_DFT_WM,
3619         PINEVIEW_CURSOR_GUARD_WM,
3620         PINEVIEW_FIFO_LINE_SIZE
3621 };
3622 static const struct intel_watermark_params g4x_wm_info = {
3623         G4X_FIFO_SIZE,
3624         G4X_MAX_WM,
3625         G4X_MAX_WM,
3626         2,
3627         G4X_FIFO_LINE_SIZE,
3628 };
3629 static const struct intel_watermark_params g4x_cursor_wm_info = {
3630         I965_CURSOR_FIFO,
3631         I965_CURSOR_MAX_WM,
3632         I965_CURSOR_DFT_WM,
3633         2,
3634         G4X_FIFO_LINE_SIZE,
3635 };
3636 static const struct intel_watermark_params i965_cursor_wm_info = {
3637         I965_CURSOR_FIFO,
3638         I965_CURSOR_MAX_WM,
3639         I965_CURSOR_DFT_WM,
3640         2,
3641         I915_FIFO_LINE_SIZE,
3642 };
3643 static const struct intel_watermark_params i945_wm_info = {
3644         I945_FIFO_SIZE,
3645         I915_MAX_WM,
3646         1,
3647         2,
3648         I915_FIFO_LINE_SIZE
3649 };
3650 static const struct intel_watermark_params i915_wm_info = {
3651         I915_FIFO_SIZE,
3652         I915_MAX_WM,
3653         1,
3654         2,
3655         I915_FIFO_LINE_SIZE
3656 };
3657 static const struct intel_watermark_params i855_wm_info = {
3658         I855GM_FIFO_SIZE,
3659         I915_MAX_WM,
3660         1,
3661         2,
3662         I830_FIFO_LINE_SIZE
3663 };
3664 static const struct intel_watermark_params i830_wm_info = {
3665         I830_FIFO_SIZE,
3666         I915_MAX_WM,
3667         1,
3668         2,
3669         I830_FIFO_LINE_SIZE
3670 };
3671
3672 static const struct intel_watermark_params ironlake_display_wm_info = {
3673         ILK_DISPLAY_FIFO,
3674         ILK_DISPLAY_MAXWM,
3675         ILK_DISPLAY_DFTWM,
3676         2,
3677         ILK_FIFO_LINE_SIZE
3678 };
3679 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3680         ILK_CURSOR_FIFO,
3681         ILK_CURSOR_MAXWM,
3682         ILK_CURSOR_DFTWM,
3683         2,
3684         ILK_FIFO_LINE_SIZE
3685 };
3686 static const struct intel_watermark_params ironlake_display_srwm_info = {
3687         ILK_DISPLAY_SR_FIFO,
3688         ILK_DISPLAY_MAX_SRWM,
3689         ILK_DISPLAY_DFT_SRWM,
3690         2,
3691         ILK_FIFO_LINE_SIZE
3692 };
3693 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3694         ILK_CURSOR_SR_FIFO,
3695         ILK_CURSOR_MAX_SRWM,
3696         ILK_CURSOR_DFT_SRWM,
3697         2,
3698         ILK_FIFO_LINE_SIZE
3699 };
3700
3701 static const struct intel_watermark_params sandybridge_display_wm_info = {
3702         SNB_DISPLAY_FIFO,
3703         SNB_DISPLAY_MAXWM,
3704         SNB_DISPLAY_DFTWM,
3705         2,
3706         SNB_FIFO_LINE_SIZE
3707 };
3708 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3709         SNB_CURSOR_FIFO,
3710         SNB_CURSOR_MAXWM,
3711         SNB_CURSOR_DFTWM,
3712         2,
3713         SNB_FIFO_LINE_SIZE
3714 };
3715 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3716         SNB_DISPLAY_SR_FIFO,
3717         SNB_DISPLAY_MAX_SRWM,
3718         SNB_DISPLAY_DFT_SRWM,
3719         2,
3720         SNB_FIFO_LINE_SIZE
3721 };
3722 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3723         SNB_CURSOR_SR_FIFO,
3724         SNB_CURSOR_MAX_SRWM,
3725         SNB_CURSOR_DFT_SRWM,
3726         2,
3727         SNB_FIFO_LINE_SIZE
3728 };
3729
3730
3731 /**
3732  * intel_calculate_wm - calculate watermark level
3733  * @clock_in_khz: pixel clock
3734  * @wm: chip FIFO params
3735  * @pixel_size: display pixel size
3736  * @latency_ns: memory latency for the platform
3737  *
3738  * Calculate the watermark level (the level at which the display plane will
3739  * start fetching from memory again).  Each chip has a different display
3740  * FIFO size and allocation, so the caller needs to figure that out and pass
3741  * in the correct intel_watermark_params structure.
3742  *
3743  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3744  * on the pixel size.  When it reaches the watermark level, it'll start
3745  * fetching FIFO line sized based chunks from memory until the FIFO fills
3746  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3747  * will occur, and a display engine hang could result.
3748  */
3749 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3750                                         const struct intel_watermark_params *wm,
3751                                         int fifo_size,
3752                                         int pixel_size,
3753                                         unsigned long latency_ns)
3754 {
3755         long entries_required, wm_size;
3756
3757         /*
3758          * Note: we need to make sure we don't overflow for various clock &
3759          * latency values.
3760          * clocks go from a few thousand to several hundred thousand.
3761          * latency is usually a few thousand
3762          */
3763         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3764                 1000;
3765         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3766
3767         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3768
3769         wm_size = fifo_size - (entries_required + wm->guard_size);
3770
3771         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3772
3773         /* Don't promote wm_size to unsigned... */
3774         if (wm_size > (long)wm->max_wm)
3775                 wm_size = wm->max_wm;
3776         if (wm_size <= 0)
3777                 wm_size = wm->default_wm;
3778         return wm_size;
3779 }
3780
3781 struct cxsr_latency {
3782         int is_desktop;
3783         int is_ddr3;
3784         unsigned long fsb_freq;
3785         unsigned long mem_freq;
3786         unsigned long display_sr;
3787         unsigned long display_hpll_disable;
3788         unsigned long cursor_sr;
3789         unsigned long cursor_hpll_disable;
3790 };
3791
3792 static const struct cxsr_latency cxsr_latency_table[] = {
3793         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3794         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3795         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3796         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3797         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3798
3799         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3800         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3801         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3802         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3803         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3804
3805         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3806         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3807         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3808         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3809         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3810
3811         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3812         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3813         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3814         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3815         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3816
3817         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3818         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3819         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3820         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3821         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3822
3823         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3824         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3825         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3826         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3827         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3828 };
3829
3830 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3831                                                          int is_ddr3,
3832                                                          int fsb,
3833                                                          int mem)
3834 {
3835         const struct cxsr_latency *latency;
3836         int i;
3837
3838         if (fsb == 0 || mem == 0)
3839                 return NULL;
3840
3841         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3842                 latency = &cxsr_latency_table[i];
3843                 if (is_desktop == latency->is_desktop &&
3844                     is_ddr3 == latency->is_ddr3 &&
3845                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3846                         return latency;
3847         }
3848
3849         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3850
3851         return NULL;
3852 }
3853
3854 static void pineview_disable_cxsr(struct drm_device *dev)
3855 {
3856         struct drm_i915_private *dev_priv = dev->dev_private;
3857
3858         /* deactivate cxsr */
3859         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3860 }
3861
3862 /*
3863  * Latency for FIFO fetches is dependent on several factors:
3864  *   - memory configuration (speed, channels)
3865  *   - chipset
3866  *   - current MCH state
3867  * It can be fairly high in some situations, so here we assume a fairly
3868  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3869  * set this value too high, the FIFO will fetch frequently to stay full)
3870  * and power consumption (set it too low to save power and we might see
3871  * FIFO underruns and display "flicker").
3872  *
3873  * A value of 5us seems to be a good balance; safe for very low end
3874  * platforms but not overly aggressive on lower latency configs.
3875  */
3876 static const int latency_ns = 5000;
3877
3878 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3879 {
3880         struct drm_i915_private *dev_priv = dev->dev_private;
3881         uint32_t dsparb = I915_READ(DSPARB);
3882         int size;
3883
3884         size = dsparb & 0x7f;
3885         if (plane)
3886                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3887
3888         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3889                       plane ? "B" : "A", size);
3890
3891         return size;
3892 }
3893
3894 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3895 {
3896         struct drm_i915_private *dev_priv = dev->dev_private;
3897         uint32_t dsparb = I915_READ(DSPARB);
3898         int size;
3899
3900         size = dsparb & 0x1ff;
3901         if (plane)
3902                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3903         size >>= 1; /* Convert to cachelines */
3904
3905         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3906                       plane ? "B" : "A", size);
3907
3908         return size;
3909 }
3910
3911 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3912 {
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         uint32_t dsparb = I915_READ(DSPARB);
3915         int size;
3916
3917         size = dsparb & 0x7f;
3918         size >>= 2; /* Convert to cachelines */
3919
3920         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3921                       plane ? "B" : "A",
3922                       size);
3923
3924         return size;
3925 }
3926
3927 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3928 {
3929         struct drm_i915_private *dev_priv = dev->dev_private;
3930         uint32_t dsparb = I915_READ(DSPARB);
3931         int size;
3932
3933         size = dsparb & 0x7f;
3934         size >>= 1; /* Convert to cachelines */
3935
3936         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3937                       plane ? "B" : "A", size);
3938
3939         return size;
3940 }
3941
3942 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3943 {
3944         struct drm_crtc *crtc, *enabled = NULL;
3945
3946         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3947                 if (crtc->enabled && crtc->fb) {
3948                         if (enabled)
3949                                 return NULL;
3950                         enabled = crtc;
3951                 }
3952         }
3953
3954         return enabled;
3955 }
3956
3957 static void pineview_update_wm(struct drm_device *dev)
3958 {
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct drm_crtc *crtc;
3961         const struct cxsr_latency *latency;
3962         u32 reg;
3963         unsigned long wm;
3964
3965         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3966                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3967         if (!latency) {
3968                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3969                 pineview_disable_cxsr(dev);
3970                 return;
3971         }
3972
3973         crtc = single_enabled_crtc(dev);
3974         if (crtc) {
3975                 int clock = crtc->mode.clock;
3976                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3977
3978                 /* Display SR */
3979                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3980                                         pineview_display_wm.fifo_size,
3981                                         pixel_size, latency->display_sr);
3982                 reg = I915_READ(DSPFW1);
3983                 reg &= ~DSPFW_SR_MASK;
3984                 reg |= wm << DSPFW_SR_SHIFT;
3985                 I915_WRITE(DSPFW1, reg);
3986                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3987
3988                 /* cursor SR */
3989                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3990                                         pineview_display_wm.fifo_size,
3991                                         pixel_size, latency->cursor_sr);
3992                 reg = I915_READ(DSPFW3);
3993                 reg &= ~DSPFW_CURSOR_SR_MASK;
3994                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3995                 I915_WRITE(DSPFW3, reg);
3996
3997                 /* Display HPLL off SR */
3998                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3999                                         pineview_display_hplloff_wm.fifo_size,
4000                                         pixel_size, latency->display_hpll_disable);
4001                 reg = I915_READ(DSPFW3);
4002                 reg &= ~DSPFW_HPLL_SR_MASK;
4003                 reg |= wm & DSPFW_HPLL_SR_MASK;
4004                 I915_WRITE(DSPFW3, reg);
4005
4006                 /* cursor HPLL off SR */
4007                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4008                                         pineview_display_hplloff_wm.fifo_size,
4009                                         pixel_size, latency->cursor_hpll_disable);
4010                 reg = I915_READ(DSPFW3);
4011                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4012                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4013                 I915_WRITE(DSPFW3, reg);
4014                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4015
4016                 /* activate cxsr */
4017                 I915_WRITE(DSPFW3,
4018                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4019                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4020         } else {
4021                 pineview_disable_cxsr(dev);
4022                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4023         }
4024 }
4025
4026 static bool g4x_compute_wm0(struct drm_device *dev,
4027                             int plane,
4028                             const struct intel_watermark_params *display,
4029                             int display_latency_ns,
4030                             const struct intel_watermark_params *cursor,
4031                             int cursor_latency_ns,
4032                             int *plane_wm,
4033                             int *cursor_wm)
4034 {
4035         struct drm_crtc *crtc;
4036         int htotal, hdisplay, clock, pixel_size;
4037         int line_time_us, line_count;
4038         int entries, tlb_miss;
4039
4040         crtc = intel_get_crtc_for_plane(dev, plane);
4041         if (crtc->fb == NULL || !crtc->enabled) {
4042                 *cursor_wm = cursor->guard_size;
4043                 *plane_wm = display->guard_size;
4044                 return false;
4045         }
4046
4047         htotal = crtc->mode.htotal;
4048         hdisplay = crtc->mode.hdisplay;
4049         clock = crtc->mode.clock;
4050         pixel_size = crtc->fb->bits_per_pixel / 8;
4051
4052         /* Use the small buffer method to calculate plane watermark */
4053         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4054         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4055         if (tlb_miss > 0)
4056                 entries += tlb_miss;
4057         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4058         *plane_wm = entries + display->guard_size;
4059         if (*plane_wm > (int)display->max_wm)
4060                 *plane_wm = display->max_wm;
4061
4062         /* Use the large buffer method to calculate cursor watermark */
4063         line_time_us = ((htotal * 1000) / clock);
4064         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4065         entries = line_count * 64 * pixel_size;
4066         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4067         if (tlb_miss > 0)
4068                 entries += tlb_miss;
4069         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4070         *cursor_wm = entries + cursor->guard_size;
4071         if (*cursor_wm > (int)cursor->max_wm)
4072                 *cursor_wm = (int)cursor->max_wm;
4073
4074         return true;
4075 }
4076
4077 /*
4078  * Check the wm result.
4079  *
4080  * If any calculated watermark values is larger than the maximum value that
4081  * can be programmed into the associated watermark register, that watermark
4082  * must be disabled.
4083  */
4084 static bool g4x_check_srwm(struct drm_device *dev,
4085                            int display_wm, int cursor_wm,
4086                            const struct intel_watermark_params *display,
4087                            const struct intel_watermark_params *cursor)
4088 {
4089         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4090                       display_wm, cursor_wm);
4091
4092         if (display_wm > display->max_wm) {
4093                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4094                               display_wm, display->max_wm);
4095                 return false;
4096         }
4097
4098         if (cursor_wm > cursor->max_wm) {
4099                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4100                               cursor_wm, cursor->max_wm);
4101                 return false;
4102         }
4103
4104         if (!(display_wm || cursor_wm)) {
4105                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4106                 return false;
4107         }
4108
4109         return true;
4110 }
4111
4112 static bool g4x_compute_srwm(struct drm_device *dev,
4113                              int plane,
4114                              int latency_ns,
4115                              const struct intel_watermark_params *display,
4116                              const struct intel_watermark_params *cursor,
4117                              int *display_wm, int *cursor_wm)
4118 {
4119         struct drm_crtc *crtc;
4120         int hdisplay, htotal, pixel_size, clock;
4121         unsigned long line_time_us;
4122         int line_count, line_size;
4123         int small, large;
4124         int entries;
4125
4126         if (!latency_ns) {
4127                 *display_wm = *cursor_wm = 0;
4128                 return false;
4129         }
4130
4131         crtc = intel_get_crtc_for_plane(dev, plane);
4132         hdisplay = crtc->mode.hdisplay;
4133         htotal = crtc->mode.htotal;
4134         clock = crtc->mode.clock;
4135         pixel_size = crtc->fb->bits_per_pixel / 8;
4136
4137         line_time_us = (htotal * 1000) / clock;
4138         line_count = (latency_ns / line_time_us + 1000) / 1000;
4139         line_size = hdisplay * pixel_size;
4140
4141         /* Use the minimum of the small and large buffer method for primary */
4142         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4143         large = line_count * line_size;
4144
4145         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4146         *display_wm = entries + display->guard_size;
4147
4148         /* calculate the self-refresh watermark for display cursor */
4149         entries = line_count * pixel_size * 64;
4150         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4151         *cursor_wm = entries + cursor->guard_size;
4152
4153         return g4x_check_srwm(dev,
4154                               *display_wm, *cursor_wm,
4155                               display, cursor);
4156 }
4157
4158 #define single_plane_enabled(mask) is_power_of_2(mask)
4159
4160 static void g4x_update_wm(struct drm_device *dev)
4161 {
4162         static const int sr_latency_ns = 12000;
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4165         int plane_sr, cursor_sr;
4166         unsigned int enabled = 0;
4167
4168         if (g4x_compute_wm0(dev, 0,
4169                             &g4x_wm_info, latency_ns,
4170                             &g4x_cursor_wm_info, latency_ns,
4171                             &planea_wm, &cursora_wm))
4172                 enabled |= 1;
4173
4174         if (g4x_compute_wm0(dev, 1,
4175                             &g4x_wm_info, latency_ns,
4176                             &g4x_cursor_wm_info, latency_ns,
4177                             &planeb_wm, &cursorb_wm))
4178                 enabled |= 2;
4179
4180         plane_sr = cursor_sr = 0;
4181         if (single_plane_enabled(enabled) &&
4182             g4x_compute_srwm(dev, ffs(enabled) - 1,
4183                              sr_latency_ns,
4184                              &g4x_wm_info,
4185                              &g4x_cursor_wm_info,
4186                              &plane_sr, &cursor_sr))
4187                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4188         else
4189                 I915_WRITE(FW_BLC_SELF,
4190                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4191
4192         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4193                       planea_wm, cursora_wm,
4194                       planeb_wm, cursorb_wm,
4195                       plane_sr, cursor_sr);
4196
4197         I915_WRITE(DSPFW1,
4198                    (plane_sr << DSPFW_SR_SHIFT) |
4199                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4200                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4201                    planea_wm);
4202         I915_WRITE(DSPFW2,
4203                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4204                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4205         /* HPLL off in SR has some issues on G4x... disable it */
4206         I915_WRITE(DSPFW3,
4207                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4208                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4209 }
4210
4211 static void i965_update_wm(struct drm_device *dev)
4212 {
4213         struct drm_i915_private *dev_priv = dev->dev_private;
4214         struct drm_crtc *crtc;
4215         int srwm = 1;
4216         int cursor_sr = 16;
4217
4218         /* Calc sr entries for one plane configs */
4219         crtc = single_enabled_crtc(dev);
4220         if (crtc) {
4221                 /* self-refresh has much higher latency */
4222                 static const int sr_latency_ns = 12000;
4223                 int clock = crtc->mode.clock;
4224                 int htotal = crtc->mode.htotal;
4225                 int hdisplay = crtc->mode.hdisplay;
4226                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4227                 unsigned long line_time_us;
4228                 int entries;
4229
4230                 line_time_us = ((htotal * 1000) / clock);
4231
4232                 /* Use ns/us then divide to preserve precision */
4233                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4234                         pixel_size * hdisplay;
4235                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4236                 srwm = I965_FIFO_SIZE - entries;
4237                 if (srwm < 0)
4238                         srwm = 1;
4239                 srwm &= 0x1ff;
4240                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4241                               entries, srwm);
4242
4243                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4244                         pixel_size * 64;
4245                 entries = DIV_ROUND_UP(entries,
4246                                           i965_cursor_wm_info.cacheline_size);
4247                 cursor_sr = i965_cursor_wm_info.fifo_size -
4248                         (entries + i965_cursor_wm_info.guard_size);
4249
4250                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4251                         cursor_sr = i965_cursor_wm_info.max_wm;
4252
4253                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4254                               "cursor %d\n", srwm, cursor_sr);
4255
4256                 if (IS_CRESTLINE(dev))
4257                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4258         } else {
4259                 /* Turn off self refresh if both pipes are enabled */
4260                 if (IS_CRESTLINE(dev))
4261                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4262                                    & ~FW_BLC_SELF_EN);
4263         }
4264
4265         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4266                       srwm);
4267
4268         /* 965 has limitations... */
4269         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4270                    (8 << 16) | (8 << 8) | (8 << 0));
4271         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4272         /* update cursor SR watermark */
4273         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4274 }
4275
4276 static void i9xx_update_wm(struct drm_device *dev)
4277 {
4278         struct drm_i915_private *dev_priv = dev->dev_private;
4279         const struct intel_watermark_params *wm_info;
4280         uint32_t fwater_lo;
4281         uint32_t fwater_hi;
4282         int cwm, srwm = 1;
4283         int fifo_size;
4284         int planea_wm, planeb_wm;
4285         struct drm_crtc *crtc, *enabled = NULL;
4286
4287         if (IS_I945GM(dev))
4288                 wm_info = &i945_wm_info;
4289         else if (!IS_GEN2(dev))
4290                 wm_info = &i915_wm_info;
4291         else
4292                 wm_info = &i855_wm_info;
4293
4294         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4295         crtc = intel_get_crtc_for_plane(dev, 0);
4296         if (crtc->enabled && crtc->fb) {
4297                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4298                                                wm_info, fifo_size,
4299                                                crtc->fb->bits_per_pixel / 8,
4300                                                latency_ns);
4301                 enabled = crtc;
4302         } else
4303                 planea_wm = fifo_size - wm_info->guard_size;
4304
4305         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4306         crtc = intel_get_crtc_for_plane(dev, 1);
4307         if (crtc->enabled && crtc->fb) {
4308                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4309                                                wm_info, fifo_size,
4310                                                crtc->fb->bits_per_pixel / 8,
4311                                                latency_ns);
4312                 if (enabled == NULL)
4313                         enabled = crtc;
4314                 else
4315                         enabled = NULL;
4316         } else
4317                 planeb_wm = fifo_size - wm_info->guard_size;
4318
4319         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4320
4321         /*
4322          * Overlay gets an aggressive default since video jitter is bad.
4323          */
4324         cwm = 2;
4325
4326         /* Play safe and disable self-refresh before adjusting watermarks. */
4327         if (IS_I945G(dev) || IS_I945GM(dev))
4328                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4329         else if (IS_I915GM(dev))
4330                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4331
4332         /* Calc sr entries for one plane configs */
4333         if (HAS_FW_BLC(dev) && enabled) {
4334                 /* self-refresh has much higher latency */
4335                 static const int sr_latency_ns = 6000;
4336                 int clock = enabled->mode.clock;
4337                 int htotal = enabled->mode.htotal;
4338                 int hdisplay = enabled->mode.hdisplay;
4339                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4340                 unsigned long line_time_us;
4341                 int entries;
4342
4343                 line_time_us = (htotal * 1000) / clock;
4344
4345                 /* Use ns/us then divide to preserve precision */
4346                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4347                         pixel_size * hdisplay;
4348                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4349                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4350                 srwm = wm_info->fifo_size - entries;
4351                 if (srwm < 0)
4352                         srwm = 1;
4353
4354                 if (IS_I945G(dev) || IS_I945GM(dev))
4355                         I915_WRITE(FW_BLC_SELF,
4356                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4357                 else if (IS_I915GM(dev))
4358                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4359         }
4360
4361         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4362                       planea_wm, planeb_wm, cwm, srwm);
4363
4364         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4365         fwater_hi = (cwm & 0x1f);
4366
4367         /* Set request length to 8 cachelines per fetch */
4368         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4369         fwater_hi = fwater_hi | (1 << 8);
4370
4371         I915_WRITE(FW_BLC, fwater_lo);
4372         I915_WRITE(FW_BLC2, fwater_hi);
4373
4374         if (HAS_FW_BLC(dev)) {
4375                 if (enabled) {
4376                         if (IS_I945G(dev) || IS_I945GM(dev))
4377                                 I915_WRITE(FW_BLC_SELF,
4378                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4379                         else if (IS_I915GM(dev))
4380                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4381                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4382                 } else
4383                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4384         }
4385 }
4386
4387 static void i830_update_wm(struct drm_device *dev)
4388 {
4389         struct drm_i915_private *dev_priv = dev->dev_private;
4390         struct drm_crtc *crtc;
4391         uint32_t fwater_lo;
4392         int planea_wm;
4393
4394         crtc = single_enabled_crtc(dev);
4395         if (crtc == NULL)
4396                 return;
4397
4398         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4399                                        dev_priv->display.get_fifo_size(dev, 0),
4400                                        crtc->fb->bits_per_pixel / 8,
4401                                        latency_ns);
4402         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4403         fwater_lo |= (3<<8) | planea_wm;
4404
4405         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4406
4407         I915_WRITE(FW_BLC, fwater_lo);
4408 }
4409
4410 #define ILK_LP0_PLANE_LATENCY           700
4411 #define ILK_LP0_CURSOR_LATENCY          1300
4412
4413 /*
4414  * Check the wm result.
4415  *
4416  * If any calculated watermark values is larger than the maximum value that
4417  * can be programmed into the associated watermark register, that watermark
4418  * must be disabled.
4419  */
4420 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4421                                 int fbc_wm, int display_wm, int cursor_wm,
4422                                 const struct intel_watermark_params *display,
4423                                 const struct intel_watermark_params *cursor)
4424 {
4425         struct drm_i915_private *dev_priv = dev->dev_private;
4426
4427         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4428                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4429
4430         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4431                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4432                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4433
4434                 /* fbc has it's own way to disable FBC WM */
4435                 I915_WRITE(DISP_ARB_CTL,
4436                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4437                 return false;
4438         }
4439
4440         if (display_wm > display->max_wm) {
4441                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4442                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4443                 return false;
4444         }
4445
4446         if (cursor_wm > cursor->max_wm) {
4447                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4448                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4449                 return false;
4450         }
4451
4452         if (!(fbc_wm || display_wm || cursor_wm)) {
4453                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4454                 return false;
4455         }
4456
4457         return true;
4458 }
4459
4460 /*
4461  * Compute watermark values of WM[1-3],
4462  */
4463 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4464                                   int latency_ns,
4465                                   const struct intel_watermark_params *display,
4466                                   const struct intel_watermark_params *cursor,
4467                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4468 {
4469         struct drm_crtc *crtc;
4470         unsigned long line_time_us;
4471         int hdisplay, htotal, pixel_size, clock;
4472         int line_count, line_size;
4473         int small, large;
4474         int entries;
4475
4476         if (!latency_ns) {
4477                 *fbc_wm = *display_wm = *cursor_wm = 0;
4478                 return false;
4479         }
4480
4481         crtc = intel_get_crtc_for_plane(dev, plane);
4482         hdisplay = crtc->mode.hdisplay;
4483         htotal = crtc->mode.htotal;
4484         clock = crtc->mode.clock;
4485         pixel_size = crtc->fb->bits_per_pixel / 8;
4486
4487         line_time_us = (htotal * 1000) / clock;
4488         line_count = (latency_ns / line_time_us + 1000) / 1000;
4489         line_size = hdisplay * pixel_size;
4490
4491         /* Use the minimum of the small and large buffer method for primary */
4492         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4493         large = line_count * line_size;
4494
4495         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4496         *display_wm = entries + display->guard_size;
4497
4498         /*
4499          * Spec says:
4500          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4501          */
4502         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4503
4504         /* calculate the self-refresh watermark for display cursor */
4505         entries = line_count * pixel_size * 64;
4506         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4507         *cursor_wm = entries + cursor->guard_size;
4508
4509         return ironlake_check_srwm(dev, level,
4510                                    *fbc_wm, *display_wm, *cursor_wm,
4511                                    display, cursor);
4512 }
4513
4514 static void ironlake_update_wm(struct drm_device *dev)
4515 {
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         int fbc_wm, plane_wm, cursor_wm;
4518         unsigned int enabled;
4519
4520         enabled = 0;
4521         if (g4x_compute_wm0(dev, 0,
4522                             &ironlake_display_wm_info,
4523                             ILK_LP0_PLANE_LATENCY,
4524                             &ironlake_cursor_wm_info,
4525                             ILK_LP0_CURSOR_LATENCY,
4526                             &plane_wm, &cursor_wm)) {
4527                 I915_WRITE(WM0_PIPEA_ILK,
4528                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4529                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4530                               " plane %d, " "cursor: %d\n",
4531                               plane_wm, cursor_wm);
4532                 enabled |= 1;
4533         }
4534
4535         if (g4x_compute_wm0(dev, 1,
4536                             &ironlake_display_wm_info,
4537                             ILK_LP0_PLANE_LATENCY,
4538                             &ironlake_cursor_wm_info,
4539                             ILK_LP0_CURSOR_LATENCY,
4540                             &plane_wm, &cursor_wm)) {
4541                 I915_WRITE(WM0_PIPEB_ILK,
4542                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4543                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4544                               " plane %d, cursor: %d\n",
4545                               plane_wm, cursor_wm);
4546                 enabled |= 2;
4547         }
4548
4549         /*
4550          * Calculate and update the self-refresh watermark only when one
4551          * display plane is used.
4552          */
4553         I915_WRITE(WM3_LP_ILK, 0);
4554         I915_WRITE(WM2_LP_ILK, 0);
4555         I915_WRITE(WM1_LP_ILK, 0);
4556
4557         if (!single_plane_enabled(enabled))
4558                 return;
4559         enabled = ffs(enabled) - 1;
4560
4561         /* WM1 */
4562         if (!ironlake_compute_srwm(dev, 1, enabled,
4563                                    ILK_READ_WM1_LATENCY() * 500,
4564                                    &ironlake_display_srwm_info,
4565                                    &ironlake_cursor_srwm_info,
4566                                    &fbc_wm, &plane_wm, &cursor_wm))
4567                 return;
4568
4569         I915_WRITE(WM1_LP_ILK,
4570                    WM1_LP_SR_EN |
4571                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4572                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4573                    (plane_wm << WM1_LP_SR_SHIFT) |
4574                    cursor_wm);
4575
4576         /* WM2 */
4577         if (!ironlake_compute_srwm(dev, 2, enabled,
4578                                    ILK_READ_WM2_LATENCY() * 500,
4579                                    &ironlake_display_srwm_info,
4580                                    &ironlake_cursor_srwm_info,
4581                                    &fbc_wm, &plane_wm, &cursor_wm))
4582                 return;
4583
4584         I915_WRITE(WM2_LP_ILK,
4585                    WM2_LP_EN |
4586                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4587                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4588                    (plane_wm << WM1_LP_SR_SHIFT) |
4589                    cursor_wm);
4590
4591         /*
4592          * WM3 is unsupported on ILK, probably because we don't have latency
4593          * data for that power state
4594          */
4595 }
4596
4597 void sandybridge_update_wm(struct drm_device *dev)
4598 {
4599         struct drm_i915_private *dev_priv = dev->dev_private;
4600         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4601         u32 val;
4602         int fbc_wm, plane_wm, cursor_wm;
4603         unsigned int enabled;
4604
4605         enabled = 0;
4606         if (g4x_compute_wm0(dev, 0,
4607                             &sandybridge_display_wm_info, latency,
4608                             &sandybridge_cursor_wm_info, latency,
4609                             &plane_wm, &cursor_wm)) {
4610                 val = I915_READ(WM0_PIPEA_ILK);
4611                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4612                 I915_WRITE(WM0_PIPEA_ILK, val |
4613                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4614                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4615                               " plane %d, " "cursor: %d\n",
4616                               plane_wm, cursor_wm);
4617                 enabled |= 1;
4618         }
4619
4620         if (g4x_compute_wm0(dev, 1,
4621                             &sandybridge_display_wm_info, latency,
4622                             &sandybridge_cursor_wm_info, latency,
4623                             &plane_wm, &cursor_wm)) {
4624                 val = I915_READ(WM0_PIPEB_ILK);
4625                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4626                 I915_WRITE(WM0_PIPEB_ILK, val |
4627                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4628                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4629                               " plane %d, cursor: %d\n",
4630                               plane_wm, cursor_wm);
4631                 enabled |= 2;
4632         }
4633
4634         /* IVB has 3 pipes */
4635         if (IS_IVYBRIDGE(dev) &&
4636             g4x_compute_wm0(dev, 2,
4637                             &sandybridge_display_wm_info, latency,
4638                             &sandybridge_cursor_wm_info, latency,
4639                             &plane_wm, &cursor_wm)) {
4640                 val = I915_READ(WM0_PIPEC_IVB);
4641                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4642                 I915_WRITE(WM0_PIPEC_IVB, val |
4643                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4644                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4645                               " plane %d, cursor: %d\n",
4646                               plane_wm, cursor_wm);
4647                 enabled |= 3;
4648         }
4649
4650         /*
4651          * Calculate and update the self-refresh watermark only when one
4652          * display plane is used.
4653          *
4654          * SNB support 3 levels of watermark.
4655          *
4656          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4657          * and disabled in the descending order
4658          *
4659          */
4660         I915_WRITE(WM3_LP_ILK, 0);
4661         I915_WRITE(WM2_LP_ILK, 0);
4662         I915_WRITE(WM1_LP_ILK, 0);
4663
4664         if (!single_plane_enabled(enabled) ||
4665             dev_priv->sprite_scaling_enabled)
4666                 return;
4667         enabled = ffs(enabled) - 1;
4668
4669         /* WM1 */
4670         if (!ironlake_compute_srwm(dev, 1, enabled,
4671                                    SNB_READ_WM1_LATENCY() * 500,
4672                                    &sandybridge_display_srwm_info,
4673                                    &sandybridge_cursor_srwm_info,
4674                                    &fbc_wm, &plane_wm, &cursor_wm))
4675                 return;
4676
4677         I915_WRITE(WM1_LP_ILK,
4678                    WM1_LP_SR_EN |
4679                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4680                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4681                    (plane_wm << WM1_LP_SR_SHIFT) |
4682                    cursor_wm);
4683
4684         /* WM2 */
4685         if (!ironlake_compute_srwm(dev, 2, enabled,
4686                                    SNB_READ_WM2_LATENCY() * 500,
4687                                    &sandybridge_display_srwm_info,
4688                                    &sandybridge_cursor_srwm_info,
4689                                    &fbc_wm, &plane_wm, &cursor_wm))
4690                 return;
4691
4692         I915_WRITE(WM2_LP_ILK,
4693                    WM2_LP_EN |
4694                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4695                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4696                    (plane_wm << WM1_LP_SR_SHIFT) |
4697                    cursor_wm);
4698
4699         /* WM3 */
4700         if (!ironlake_compute_srwm(dev, 3, enabled,
4701                                    SNB_READ_WM3_LATENCY() * 500,
4702                                    &sandybridge_display_srwm_info,
4703                                    &sandybridge_cursor_srwm_info,
4704                                    &fbc_wm, &plane_wm, &cursor_wm))
4705                 return;
4706
4707         I915_WRITE(WM3_LP_ILK,
4708                    WM3_LP_EN |
4709                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4710                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4711                    (plane_wm << WM1_LP_SR_SHIFT) |
4712                    cursor_wm);
4713 }
4714
4715 static bool
4716 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4717                               uint32_t sprite_width, int pixel_size,
4718                               const struct intel_watermark_params *display,
4719                               int display_latency_ns, int *sprite_wm)
4720 {
4721         struct drm_crtc *crtc;
4722         int clock;
4723         int entries, tlb_miss;
4724
4725         crtc = intel_get_crtc_for_plane(dev, plane);
4726         if (crtc->fb == NULL || !crtc->enabled) {
4727                 *sprite_wm = display->guard_size;
4728                 return false;
4729         }
4730
4731         clock = crtc->mode.clock;
4732
4733         /* Use the small buffer method to calculate the sprite watermark */
4734         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4735         tlb_miss = display->fifo_size*display->cacheline_size -
4736                 sprite_width * 8;
4737         if (tlb_miss > 0)
4738                 entries += tlb_miss;
4739         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4740         *sprite_wm = entries + display->guard_size;
4741         if (*sprite_wm > (int)display->max_wm)
4742                 *sprite_wm = display->max_wm;
4743
4744         return true;
4745 }
4746
4747 static bool
4748 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4749                                 uint32_t sprite_width, int pixel_size,
4750                                 const struct intel_watermark_params *display,
4751                                 int latency_ns, int *sprite_wm)
4752 {
4753         struct drm_crtc *crtc;
4754         unsigned long line_time_us;
4755         int clock;
4756         int line_count, line_size;
4757         int small, large;
4758         int entries;
4759
4760         if (!latency_ns) {
4761                 *sprite_wm = 0;
4762                 return false;
4763         }
4764
4765         crtc = intel_get_crtc_for_plane(dev, plane);
4766         clock = crtc->mode.clock;
4767         if (!clock) {
4768                 *sprite_wm = 0;
4769                 return false;
4770         }
4771
4772         line_time_us = (sprite_width * 1000) / clock;
4773         if (!line_time_us) {
4774                 *sprite_wm = 0;
4775                 return false;
4776         }
4777
4778         line_count = (latency_ns / line_time_us + 1000) / 1000;
4779         line_size = sprite_width * pixel_size;
4780
4781         /* Use the minimum of the small and large buffer method for primary */
4782         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4783         large = line_count * line_size;
4784
4785         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4786         *sprite_wm = entries + display->guard_size;
4787
4788         return *sprite_wm > 0x3ff ? false : true;
4789 }
4790
4791 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4792                                          uint32_t sprite_width, int pixel_size)
4793 {
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4796         u32 val;
4797         int sprite_wm, reg;
4798         int ret;
4799
4800         switch (pipe) {
4801         case 0:
4802                 reg = WM0_PIPEA_ILK;
4803                 break;
4804         case 1:
4805                 reg = WM0_PIPEB_ILK;
4806                 break;
4807         case 2:
4808                 reg = WM0_PIPEC_IVB;
4809                 break;
4810         default:
4811                 return; /* bad pipe */
4812         }
4813
4814         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4815                                             &sandybridge_display_wm_info,
4816                                             latency, &sprite_wm);
4817         if (!ret) {
4818                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4819                               pipe);
4820                 return;
4821         }
4822
4823         val = I915_READ(reg);
4824         val &= ~WM0_PIPE_SPRITE_MASK;
4825         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4826         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4827
4828
4829         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4830                                               pixel_size,
4831                                               &sandybridge_display_srwm_info,
4832                                               SNB_READ_WM1_LATENCY() * 500,
4833                                               &sprite_wm);
4834         if (!ret) {
4835                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4836                               pipe);
4837                 return;
4838         }
4839         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4840
4841         /* Only IVB has two more LP watermarks for sprite */
4842         if (!IS_IVYBRIDGE(dev))
4843                 return;
4844
4845         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4846                                               pixel_size,
4847                                               &sandybridge_display_srwm_info,
4848                                               SNB_READ_WM2_LATENCY() * 500,
4849                                               &sprite_wm);
4850         if (!ret) {
4851                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4852                               pipe);
4853                 return;
4854         }
4855         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4856
4857         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4858                                               pixel_size,
4859                                               &sandybridge_display_srwm_info,
4860                                               SNB_READ_WM3_LATENCY() * 500,
4861                                               &sprite_wm);
4862         if (!ret) {
4863                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4864                               pipe);
4865                 return;
4866         }
4867         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4868 }
4869
4870 /**
4871  * intel_update_watermarks - update FIFO watermark values based on current modes
4872  *
4873  * Calculate watermark values for the various WM regs based on current mode
4874  * and plane configuration.
4875  *
4876  * There are several cases to deal with here:
4877  *   - normal (i.e. non-self-refresh)
4878  *   - self-refresh (SR) mode
4879  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4880  *   - lines are small relative to FIFO size (buffer can hold more than 2
4881  *     lines), so need to account for TLB latency
4882  *
4883  *   The normal calculation is:
4884  *     watermark = dotclock * bytes per pixel * latency
4885  *   where latency is platform & configuration dependent (we assume pessimal
4886  *   values here).
4887  *
4888  *   The SR calculation is:
4889  *     watermark = (trunc(latency/line time)+1) * surface width *
4890  *       bytes per pixel
4891  *   where
4892  *     line time = htotal / dotclock
4893  *     surface width = hdisplay for normal plane and 64 for cursor
4894  *   and latency is assumed to be high, as above.
4895  *
4896  * The final value programmed to the register should always be rounded up,
4897  * and include an extra 2 entries to account for clock crossings.
4898  *
4899  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4900  * to set the non-SR watermarks to 8.
4901  */
4902 static void intel_update_watermarks(struct drm_device *dev)
4903 {
4904         struct drm_i915_private *dev_priv = dev->dev_private;
4905
4906         if (dev_priv->display.update_wm)
4907                 dev_priv->display.update_wm(dev);
4908 }
4909
4910 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4911                                     uint32_t sprite_width, int pixel_size)
4912 {
4913         struct drm_i915_private *dev_priv = dev->dev_private;
4914
4915         if (dev_priv->display.update_sprite_wm)
4916                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4917                                                    pixel_size);
4918 }
4919
4920 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4921 {
4922         if (i915_panel_use_ssc >= 0)
4923                 return i915_panel_use_ssc != 0;
4924         return dev_priv->lvds_use_ssc
4925                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4926 }
4927
4928 /**
4929  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4930  * @crtc: CRTC structure
4931  * @mode: requested mode
4932  *
4933  * A pipe may be connected to one or more outputs.  Based on the depth of the
4934  * attached framebuffer, choose a good color depth to use on the pipe.
4935  *
4936  * If possible, match the pipe depth to the fb depth.  In some cases, this
4937  * isn't ideal, because the connected output supports a lesser or restricted
4938  * set of depths.  Resolve that here:
4939  *    LVDS typically supports only 6bpc, so clamp down in that case
4940  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4941  *    Displays may support a restricted set as well, check EDID and clamp as
4942  *      appropriate.
4943  *    DP may want to dither down to 6bpc to fit larger modes
4944  *
4945  * RETURNS:
4946  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4947  * true if they don't match).
4948  */
4949 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4950                                          unsigned int *pipe_bpp,
4951                                          struct drm_display_mode *mode)
4952 {
4953         struct drm_device *dev = crtc->dev;
4954         struct drm_i915_private *dev_priv = dev->dev_private;
4955         struct drm_encoder *encoder;
4956         struct drm_connector *connector;
4957         unsigned int display_bpc = UINT_MAX, bpc;
4958
4959         /* Walk the encoders & connectors on this crtc, get min bpc */
4960         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4961                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4962
4963                 if (encoder->crtc != crtc)
4964                         continue;
4965
4966                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4967                         unsigned int lvds_bpc;
4968
4969                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4970                             LVDS_A3_POWER_UP)
4971                                 lvds_bpc = 8;
4972                         else
4973                                 lvds_bpc = 6;
4974
4975                         if (lvds_bpc < display_bpc) {
4976                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4977                                 display_bpc = lvds_bpc;
4978                         }
4979                         continue;
4980                 }
4981
4982                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4983                         /* Use VBT settings if we have an eDP panel */
4984                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4985
4986                         if (edp_bpc < display_bpc) {
4987                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4988                                 display_bpc = edp_bpc;
4989                         }
4990                         continue;
4991                 }
4992
4993                 /* Not one of the known troublemakers, check the EDID */
4994                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4995                                     head) {
4996                         if (connector->encoder != encoder)
4997                                 continue;
4998
4999                         /* Don't use an invalid EDID bpc value */
5000                         if (connector->display_info.bpc &&
5001                             connector->display_info.bpc < display_bpc) {
5002                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5003                                 display_bpc = connector->display_info.bpc;
5004                         }
5005                 }
5006
5007                 /*
5008                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5009                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5010                  */
5011                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5012                         if (display_bpc > 8 && display_bpc < 12) {
5013                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5014                                 display_bpc = 12;
5015                         } else {
5016                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5017                                 display_bpc = 8;
5018                         }
5019                 }
5020         }
5021
5022         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5023                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5024                 display_bpc = 6;
5025         }
5026
5027         /*
5028          * We could just drive the pipe at the highest bpc all the time and
5029          * enable dithering as needed, but that costs bandwidth.  So choose
5030          * the minimum value that expresses the full color range of the fb but
5031          * also stays within the max display bpc discovered above.
5032          */
5033
5034         switch (crtc->fb->depth) {
5035         case 8:
5036                 bpc = 8; /* since we go through a colormap */
5037                 break;
5038         case 15:
5039         case 16:
5040                 bpc = 6; /* min is 18bpp */
5041                 break;
5042         case 24:
5043                 bpc = 8;
5044                 break;
5045         case 30:
5046                 bpc = 10;
5047                 break;
5048         case 48:
5049                 bpc = 12;
5050                 break;
5051         default:
5052                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5053                 bpc = min((unsigned int)8, display_bpc);
5054                 break;
5055         }
5056
5057         display_bpc = min(display_bpc, bpc);
5058
5059         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5060                       bpc, display_bpc);
5061
5062         *pipe_bpp = display_bpc * 3;
5063
5064         return display_bpc != bpc;
5065 }
5066
5067 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5068 {
5069         struct drm_device *dev = crtc->dev;
5070         struct drm_i915_private *dev_priv = dev->dev_private;
5071         int refclk;
5072
5073         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5074             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5075                 refclk = dev_priv->lvds_ssc_freq * 1000;
5076                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5077                               refclk / 1000);
5078         } else if (!IS_GEN2(dev)) {
5079                 refclk = 96000;
5080         } else {
5081                 refclk = 48000;
5082         }
5083
5084         return refclk;
5085 }
5086
5087 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5088                                       intel_clock_t *clock)
5089 {
5090         /* SDVO TV has fixed PLL values depend on its clock range,
5091            this mirrors vbios setting. */
5092         if (adjusted_mode->clock >= 100000
5093             && adjusted_mode->clock < 140500) {
5094                 clock->p1 = 2;
5095                 clock->p2 = 10;
5096                 clock->n = 3;
5097                 clock->m1 = 16;
5098                 clock->m2 = 8;
5099         } else if (adjusted_mode->clock >= 140500
5100                    && adjusted_mode->clock <= 200000) {
5101                 clock->p1 = 1;
5102                 clock->p2 = 10;
5103                 clock->n = 6;
5104                 clock->m1 = 12;
5105                 clock->m2 = 8;
5106         }
5107 }
5108
5109 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5110                                      intel_clock_t *clock,
5111                                      intel_clock_t *reduced_clock)
5112 {
5113         struct drm_device *dev = crtc->dev;
5114         struct drm_i915_private *dev_priv = dev->dev_private;
5115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5116         int pipe = intel_crtc->pipe;
5117         u32 fp, fp2 = 0;
5118
5119         if (IS_PINEVIEW(dev)) {
5120                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5121                 if (reduced_clock)
5122                         fp2 = (1 << reduced_clock->n) << 16 |
5123                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5124         } else {
5125                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5126                 if (reduced_clock)
5127                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5128                                 reduced_clock->m2;
5129         }
5130
5131         I915_WRITE(FP0(pipe), fp);
5132
5133         intel_crtc->lowfreq_avail = false;
5134         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5135             reduced_clock && i915_powersave) {
5136                 I915_WRITE(FP1(pipe), fp2);
5137                 intel_crtc->lowfreq_avail = true;
5138         } else {
5139                 I915_WRITE(FP1(pipe), fp);
5140         }
5141 }
5142
5143 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5144                               struct drm_display_mode *mode,
5145                               struct drm_display_mode *adjusted_mode,
5146                               int x, int y,
5147                               struct drm_framebuffer *old_fb)
5148 {
5149         struct drm_device *dev = crtc->dev;
5150         struct drm_i915_private *dev_priv = dev->dev_private;
5151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5152         int pipe = intel_crtc->pipe;
5153         int plane = intel_crtc->plane;
5154         int refclk, num_connectors = 0;
5155         intel_clock_t clock, reduced_clock;
5156         u32 dpll, dspcntr, pipeconf, vsyncshift;
5157         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5158         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5159         struct drm_mode_config *mode_config = &dev->mode_config;
5160         struct intel_encoder *encoder;
5161         const intel_limit_t *limit;
5162         int ret;
5163         u32 temp;
5164         u32 lvds_sync = 0;
5165
5166         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5167                 if (encoder->base.crtc != crtc)
5168                         continue;
5169
5170                 switch (encoder->type) {
5171                 case INTEL_OUTPUT_LVDS:
5172                         is_lvds = true;
5173                         break;
5174                 case INTEL_OUTPUT_SDVO:
5175                 case INTEL_OUTPUT_HDMI:
5176                         is_sdvo = true;
5177                         if (encoder->needs_tv_clock)
5178                                 is_tv = true;
5179                         break;
5180                 case INTEL_OUTPUT_DVO:
5181                         is_dvo = true;
5182                         break;
5183                 case INTEL_OUTPUT_TVOUT:
5184                         is_tv = true;
5185                         break;
5186                 case INTEL_OUTPUT_ANALOG:
5187                         is_crt = true;
5188                         break;
5189                 case INTEL_OUTPUT_DISPLAYPORT:
5190                         is_dp = true;
5191                         break;
5192                 }
5193
5194                 num_connectors++;
5195         }
5196
5197         refclk = i9xx_get_refclk(crtc, num_connectors);
5198
5199         /*
5200          * Returns a set of divisors for the desired target clock with the given
5201          * refclk, or FALSE.  The returned values represent the clock equation:
5202          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5203          */
5204         limit = intel_limit(crtc, refclk);
5205         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5206                              &clock);
5207         if (!ok) {
5208                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5209                 return -EINVAL;
5210         }
5211
5212         /* Ensure that the cursor is valid for the new mode before changing... */
5213         intel_crtc_update_cursor(crtc, true);
5214
5215         if (is_lvds && dev_priv->lvds_downclock_avail) {
5216                 /*
5217                  * Ensure we match the reduced clock's P to the target clock.
5218                  * If the clocks don't match, we can't switch the display clock
5219                  * by using the FP0/FP1. In such case we will disable the LVDS
5220                  * downclock feature.
5221                 */
5222                 has_reduced_clock = limit->find_pll(limit, crtc,
5223                                                     dev_priv->lvds_downclock,
5224                                                     refclk,
5225                                                     &clock,
5226                                                     &reduced_clock);
5227         }
5228
5229         if (is_sdvo && is_tv)
5230                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5231
5232         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5233                                  &reduced_clock : NULL);
5234
5235         dpll = DPLL_VGA_MODE_DIS;
5236
5237         if (!IS_GEN2(dev)) {
5238                 if (is_lvds)
5239                         dpll |= DPLLB_MODE_LVDS;
5240                 else
5241                         dpll |= DPLLB_MODE_DAC_SERIAL;
5242                 if (is_sdvo) {
5243                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5244                         if (pixel_multiplier > 1) {
5245                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5246                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5247                         }
5248                         dpll |= DPLL_DVO_HIGH_SPEED;
5249                 }
5250                 if (is_dp)
5251                         dpll |= DPLL_DVO_HIGH_SPEED;
5252
5253                 /* compute bitmask from p1 value */
5254                 if (IS_PINEVIEW(dev))
5255                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5256                 else {
5257                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5258                         if (IS_G4X(dev) && has_reduced_clock)
5259                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5260                 }
5261                 switch (clock.p2) {
5262                 case 5:
5263                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5264                         break;
5265                 case 7:
5266                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5267                         break;
5268                 case 10:
5269                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5270                         break;
5271                 case 14:
5272                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5273                         break;
5274                 }
5275                 if (INTEL_INFO(dev)->gen >= 4)
5276                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5277         } else {
5278                 if (is_lvds) {
5279                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5280                 } else {
5281                         if (clock.p1 == 2)
5282                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5283                         else
5284                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5285                         if (clock.p2 == 4)
5286                                 dpll |= PLL_P2_DIVIDE_BY_4;
5287                 }
5288         }
5289
5290         if (is_sdvo && is_tv)
5291                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5292         else if (is_tv)
5293                 /* XXX: just matching BIOS for now */
5294                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5295                 dpll |= 3;
5296         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5297                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5298         else
5299                 dpll |= PLL_REF_INPUT_DREFCLK;
5300
5301         /* setup pipeconf */
5302         pipeconf = I915_READ(PIPECONF(pipe));
5303
5304         /* Set up the display plane register */
5305         dspcntr = DISPPLANE_GAMMA_ENABLE;
5306
5307         if (pipe == 0)
5308                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5309         else
5310                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5311
5312         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5313                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5314                  * core speed.
5315                  *
5316                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5317                  * pipe == 0 check?
5318                  */
5319                 if (mode->clock >
5320                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5321                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5322                 else
5323                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5324         }
5325
5326         /* default to 8bpc */
5327         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5328         if (is_dp) {
5329                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5330                         pipeconf |= PIPECONF_BPP_6 |
5331                                     PIPECONF_DITHER_EN |
5332                                     PIPECONF_DITHER_TYPE_SP;
5333                 }
5334         }
5335
5336         dpll |= DPLL_VCO_ENABLE;
5337
5338         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5339         drm_mode_debug_printmodeline(mode);
5340
5341         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5342
5343         POSTING_READ(DPLL(pipe));
5344         udelay(150);
5345
5346         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5347          * This is an exception to the general rule that mode_set doesn't turn
5348          * things on.
5349          */
5350         if (is_lvds) {
5351                 temp = I915_READ(LVDS);
5352                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5353                 if (pipe == 1) {
5354                         temp |= LVDS_PIPEB_SELECT;
5355                 } else {
5356                         temp &= ~LVDS_PIPEB_SELECT;
5357                 }
5358                 /* set the corresponsding LVDS_BORDER bit */
5359                 temp |= dev_priv->lvds_border_bits;
5360                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5361                  * set the DPLLs for dual-channel mode or not.
5362                  */
5363                 if (clock.p2 == 7)
5364                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5365                 else
5366                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5367
5368                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5369                  * appropriately here, but we need to look more thoroughly into how
5370                  * panels behave in the two modes.
5371                  */
5372                 /* set the dithering flag on LVDS as needed */
5373                 if (INTEL_INFO(dev)->gen >= 4) {
5374                         if (dev_priv->lvds_dither)
5375                                 temp |= LVDS_ENABLE_DITHER;
5376                         else
5377                                 temp &= ~LVDS_ENABLE_DITHER;
5378                 }
5379                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5380                         lvds_sync |= LVDS_HSYNC_POLARITY;
5381                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5382                         lvds_sync |= LVDS_VSYNC_POLARITY;
5383                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5384                     != lvds_sync) {
5385                         char flags[2] = "-+";
5386                         DRM_INFO("Changing LVDS panel from "
5387                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5388                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5389                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5390                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5391                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5392                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5393                         temp |= lvds_sync;
5394                 }
5395                 I915_WRITE(LVDS, temp);
5396         }
5397
5398         if (is_dp) {
5399                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5400         }
5401
5402         I915_WRITE(DPLL(pipe), dpll);
5403
5404         /* Wait for the clocks to stabilize. */
5405         POSTING_READ(DPLL(pipe));
5406         udelay(150);
5407
5408         if (INTEL_INFO(dev)->gen >= 4) {
5409                 temp = 0;
5410                 if (is_sdvo) {
5411                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5412                         if (temp > 1)
5413                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5414                         else
5415                                 temp = 0;
5416                 }
5417                 I915_WRITE(DPLL_MD(pipe), temp);
5418         } else {
5419                 /* The pixel multiplier can only be updated once the
5420                  * DPLL is enabled and the clocks are stable.
5421                  *
5422                  * So write it again.
5423                  */
5424                 I915_WRITE(DPLL(pipe), dpll);
5425         }
5426
5427         if (HAS_PIPE_CXSR(dev)) {
5428                 if (intel_crtc->lowfreq_avail) {
5429                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5430                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5431                 } else {
5432                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5433                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5434                 }
5435         }
5436
5437         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5438         if (!IS_GEN2(dev) &&
5439             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5440                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5441                 /* the chip adds 2 halflines automatically */
5442                 adjusted_mode->crtc_vtotal -= 1;
5443                 adjusted_mode->crtc_vblank_end -= 1;
5444                 vsyncshift = adjusted_mode->crtc_hsync_start
5445                              - adjusted_mode->crtc_htotal/2;
5446         } else {
5447                 pipeconf |= PIPECONF_PROGRESSIVE;
5448                 vsyncshift = 0;
5449         }
5450
5451         if (!IS_GEN3(dev))
5452                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5453
5454         I915_WRITE(HTOTAL(pipe),
5455                    (adjusted_mode->crtc_hdisplay - 1) |
5456                    ((adjusted_mode->crtc_htotal - 1) << 16));
5457         I915_WRITE(HBLANK(pipe),
5458                    (adjusted_mode->crtc_hblank_start - 1) |
5459                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5460         I915_WRITE(HSYNC(pipe),
5461                    (adjusted_mode->crtc_hsync_start - 1) |
5462                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5463
5464         I915_WRITE(VTOTAL(pipe),
5465                    (adjusted_mode->crtc_vdisplay - 1) |
5466                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5467         I915_WRITE(VBLANK(pipe),
5468                    (adjusted_mode->crtc_vblank_start - 1) |
5469                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5470         I915_WRITE(VSYNC(pipe),
5471                    (adjusted_mode->crtc_vsync_start - 1) |
5472                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5473
5474         /* pipesrc and dspsize control the size that is scaled from,
5475          * which should always be the user's requested size.
5476          */
5477         I915_WRITE(DSPSIZE(plane),
5478                    ((mode->vdisplay - 1) << 16) |
5479                    (mode->hdisplay - 1));
5480         I915_WRITE(DSPPOS(plane), 0);
5481         I915_WRITE(PIPESRC(pipe),
5482                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5483
5484         I915_WRITE(PIPECONF(pipe), pipeconf);
5485         POSTING_READ(PIPECONF(pipe));
5486         intel_enable_pipe(dev_priv, pipe, false);
5487
5488         intel_wait_for_vblank(dev, pipe);
5489
5490         I915_WRITE(DSPCNTR(plane), dspcntr);
5491         POSTING_READ(DSPCNTR(plane));
5492         intel_enable_plane(dev_priv, plane, pipe);
5493
5494         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5495
5496         intel_update_watermarks(dev);
5497
5498         return ret;
5499 }
5500
5501 /*
5502  * Initialize reference clocks when the driver loads
5503  */
5504 void ironlake_init_pch_refclk(struct drm_device *dev)
5505 {
5506         struct drm_i915_private *dev_priv = dev->dev_private;
5507         struct drm_mode_config *mode_config = &dev->mode_config;
5508         struct intel_encoder *encoder;
5509         u32 temp;
5510         bool has_lvds = false;
5511         bool has_cpu_edp = false;
5512         bool has_pch_edp = false;
5513         bool has_panel = false;
5514         bool has_ck505 = false;
5515         bool can_ssc = false;
5516
5517         /* We need to take the global config into account */
5518         list_for_each_entry(encoder, &mode_config->encoder_list,
5519                             base.head) {
5520                 switch (encoder->type) {
5521                 case INTEL_OUTPUT_LVDS:
5522                         has_panel = true;
5523                         has_lvds = true;
5524                         break;
5525                 case INTEL_OUTPUT_EDP:
5526                         has_panel = true;
5527                         if (intel_encoder_is_pch_edp(&encoder->base))
5528                                 has_pch_edp = true;
5529                         else
5530                                 has_cpu_edp = true;
5531                         break;
5532                 }
5533         }
5534
5535         if (HAS_PCH_IBX(dev)) {
5536                 has_ck505 = dev_priv->display_clock_mode;
5537                 can_ssc = has_ck505;
5538         } else {
5539                 has_ck505 = false;
5540                 can_ssc = true;
5541         }
5542
5543         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5544                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5545                       has_ck505);
5546
5547         /* Ironlake: try to setup display ref clock before DPLL
5548          * enabling. This is only under driver's control after
5549          * PCH B stepping, previous chipset stepping should be
5550          * ignoring this setting.
5551          */
5552         temp = I915_READ(PCH_DREF_CONTROL);
5553         /* Always enable nonspread source */
5554         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5555
5556         if (has_ck505)
5557                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5558         else
5559                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5560
5561         if (has_panel) {
5562                 temp &= ~DREF_SSC_SOURCE_MASK;
5563                 temp |= DREF_SSC_SOURCE_ENABLE;
5564
5565                 /* SSC must be turned on before enabling the CPU output  */
5566                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5567                         DRM_DEBUG_KMS("Using SSC on panel\n");
5568                         temp |= DREF_SSC1_ENABLE;
5569                 } else
5570                         temp &= ~DREF_SSC1_ENABLE;
5571
5572                 /* Get SSC going before enabling the outputs */
5573                 I915_WRITE(PCH_DREF_CONTROL, temp);
5574                 POSTING_READ(PCH_DREF_CONTROL);
5575                 udelay(200);
5576
5577                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5578
5579                 /* Enable CPU source on CPU attached eDP */
5580                 if (has_cpu_edp) {
5581                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5582                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5583                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5584                         }
5585                         else
5586                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5587                 } else
5588                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5589
5590                 I915_WRITE(PCH_DREF_CONTROL, temp);
5591                 POSTING_READ(PCH_DREF_CONTROL);
5592                 udelay(200);
5593         } else {
5594                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5595
5596                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5597
5598                 /* Turn off CPU output */
5599                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5600
5601                 I915_WRITE(PCH_DREF_CONTROL, temp);
5602                 POSTING_READ(PCH_DREF_CONTROL);
5603                 udelay(200);
5604
5605                 /* Turn off the SSC source */
5606                 temp &= ~DREF_SSC_SOURCE_MASK;
5607                 temp |= DREF_SSC_SOURCE_DISABLE;
5608
5609                 /* Turn off SSC1 */
5610                 temp &= ~ DREF_SSC1_ENABLE;
5611
5612                 I915_WRITE(PCH_DREF_CONTROL, temp);
5613                 POSTING_READ(PCH_DREF_CONTROL);
5614                 udelay(200);
5615         }
5616 }
5617
5618 static int ironlake_get_refclk(struct drm_crtc *crtc)
5619 {
5620         struct drm_device *dev = crtc->dev;
5621         struct drm_i915_private *dev_priv = dev->dev_private;
5622         struct intel_encoder *encoder;
5623         struct drm_mode_config *mode_config = &dev->mode_config;
5624         struct intel_encoder *edp_encoder = NULL;
5625         int num_connectors = 0;
5626         bool is_lvds = false;
5627
5628         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5629                 if (encoder->base.crtc != crtc)
5630                         continue;
5631
5632                 switch (encoder->type) {
5633                 case INTEL_OUTPUT_LVDS:
5634                         is_lvds = true;
5635                         break;
5636                 case INTEL_OUTPUT_EDP:
5637                         edp_encoder = encoder;
5638                         break;
5639                 }
5640                 num_connectors++;
5641         }
5642
5643         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5644                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5645                               dev_priv->lvds_ssc_freq);
5646                 return dev_priv->lvds_ssc_freq * 1000;
5647         }
5648
5649         return 120000;
5650 }
5651
5652 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5653                                   struct drm_display_mode *mode,
5654                                   struct drm_display_mode *adjusted_mode,
5655                                   int x, int y,
5656                                   struct drm_framebuffer *old_fb)
5657 {
5658         struct drm_device *dev = crtc->dev;
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5661         int pipe = intel_crtc->pipe;
5662         int plane = intel_crtc->plane;
5663         int refclk, num_connectors = 0;
5664         intel_clock_t clock, reduced_clock;
5665         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5666         bool ok, has_reduced_clock = false, is_sdvo = false;
5667         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5668         struct intel_encoder *has_edp_encoder = NULL;
5669         struct drm_mode_config *mode_config = &dev->mode_config;
5670         struct intel_encoder *encoder;
5671         const intel_limit_t *limit;
5672         int ret;
5673         struct fdi_m_n m_n = {0};
5674         u32 temp;
5675         u32 lvds_sync = 0;
5676         int target_clock, pixel_multiplier, lane, link_bw, factor;
5677         unsigned int pipe_bpp;
5678         bool dither;
5679
5680         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5681                 if (encoder->base.crtc != crtc)
5682                         continue;
5683
5684                 switch (encoder->type) {
5685                 case INTEL_OUTPUT_LVDS:
5686                         is_lvds = true;
5687                         break;
5688                 case INTEL_OUTPUT_SDVO:
5689                 case INTEL_OUTPUT_HDMI:
5690                         is_sdvo = true;
5691                         if (encoder->needs_tv_clock)
5692                                 is_tv = true;
5693                         break;
5694                 case INTEL_OUTPUT_TVOUT:
5695                         is_tv = true;
5696                         break;
5697                 case INTEL_OUTPUT_ANALOG:
5698                         is_crt = true;
5699                         break;
5700                 case INTEL_OUTPUT_DISPLAYPORT:
5701                         is_dp = true;
5702                         break;
5703                 case INTEL_OUTPUT_EDP:
5704                         has_edp_encoder = encoder;
5705                         break;
5706                 }
5707
5708                 num_connectors++;
5709         }
5710
5711         refclk = ironlake_get_refclk(crtc);
5712
5713         /*
5714          * Returns a set of divisors for the desired target clock with the given
5715          * refclk, or FALSE.  The returned values represent the clock equation:
5716          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5717          */
5718         limit = intel_limit(crtc, refclk);
5719         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5720                              &clock);
5721         if (!ok) {
5722                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5723                 return -EINVAL;
5724         }
5725
5726         /* Ensure that the cursor is valid for the new mode before changing... */
5727         intel_crtc_update_cursor(crtc, true);
5728
5729         if (is_lvds && dev_priv->lvds_downclock_avail) {
5730                 /*
5731                  * Ensure we match the reduced clock's P to the target clock.
5732                  * If the clocks don't match, we can't switch the display clock
5733                  * by using the FP0/FP1. In such case we will disable the LVDS
5734                  * downclock feature.
5735                 */
5736                 has_reduced_clock = limit->find_pll(limit, crtc,
5737                                                     dev_priv->lvds_downclock,
5738                                                     refclk,
5739                                                     &clock,
5740                                                     &reduced_clock);
5741         }
5742         /* SDVO TV has fixed PLL values depend on its clock range,
5743            this mirrors vbios setting. */
5744         if (is_sdvo && is_tv) {
5745                 if (adjusted_mode->clock >= 100000
5746                     && adjusted_mode->clock < 140500) {
5747                         clock.p1 = 2;
5748                         clock.p2 = 10;
5749                         clock.n = 3;
5750                         clock.m1 = 16;
5751                         clock.m2 = 8;
5752                 } else if (adjusted_mode->clock >= 140500
5753                            && adjusted_mode->clock <= 200000) {
5754                         clock.p1 = 1;
5755                         clock.p2 = 10;
5756                         clock.n = 6;
5757                         clock.m1 = 12;
5758                         clock.m2 = 8;
5759                 }
5760         }
5761
5762         /* FDI link */
5763         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5764         lane = 0;
5765         /* CPU eDP doesn't require FDI link, so just set DP M/N
5766            according to current link config */
5767         if (has_edp_encoder &&
5768             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5769                 target_clock = mode->clock;
5770                 intel_edp_link_config(has_edp_encoder,
5771                                       &lane, &link_bw);
5772         } else {
5773                 /* [e]DP over FDI requires target mode clock
5774                    instead of link clock */
5775                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5776                         target_clock = mode->clock;
5777                 else
5778                         target_clock = adjusted_mode->clock;
5779
5780                 /* FDI is a binary signal running at ~2.7GHz, encoding
5781                  * each output octet as 10 bits. The actual frequency
5782                  * is stored as a divider into a 100MHz clock, and the
5783                  * mode pixel clock is stored in units of 1KHz.
5784                  * Hence the bw of each lane in terms of the mode signal
5785                  * is:
5786                  */
5787                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5788         }
5789
5790         /* determine panel color depth */
5791         temp = I915_READ(PIPECONF(pipe));
5792         temp &= ~PIPE_BPC_MASK;
5793         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5794         switch (pipe_bpp) {
5795         case 18:
5796                 temp |= PIPE_6BPC;
5797                 break;
5798         case 24:
5799                 temp |= PIPE_8BPC;
5800                 break;
5801         case 30:
5802                 temp |= PIPE_10BPC;
5803                 break;
5804         case 36:
5805                 temp |= PIPE_12BPC;
5806                 break;
5807         default:
5808                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5809                         pipe_bpp);
5810                 temp |= PIPE_8BPC;
5811                 pipe_bpp = 24;
5812                 break;
5813         }
5814
5815         intel_crtc->bpp = pipe_bpp;
5816         I915_WRITE(PIPECONF(pipe), temp);
5817
5818         if (!lane) {
5819                 /*
5820                  * Account for spread spectrum to avoid
5821                  * oversubscribing the link. Max center spread
5822                  * is 2.5%; use 5% for safety's sake.
5823                  */
5824                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5825                 lane = bps / (link_bw * 8) + 1;
5826         }
5827
5828         intel_crtc->fdi_lanes = lane;
5829
5830         if (pixel_multiplier > 1)
5831                 link_bw *= pixel_multiplier;
5832         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5833                              &m_n);
5834
5835         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5836         if (has_reduced_clock)
5837                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5838                         reduced_clock.m2;
5839
5840         /* Enable autotuning of the PLL clock (if permissible) */
5841         factor = 21;
5842         if (is_lvds) {
5843                 if ((intel_panel_use_ssc(dev_priv) &&
5844                      dev_priv->lvds_ssc_freq == 100) ||
5845                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5846                         factor = 25;
5847         } else if (is_sdvo && is_tv)
5848                 factor = 20;
5849
5850         if (clock.m < factor * clock.n)
5851                 fp |= FP_CB_TUNE;
5852
5853         dpll = 0;
5854
5855         if (is_lvds)
5856                 dpll |= DPLLB_MODE_LVDS;
5857         else
5858                 dpll |= DPLLB_MODE_DAC_SERIAL;
5859         if (is_sdvo) {
5860                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5861                 if (pixel_multiplier > 1) {
5862                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5863                 }
5864                 dpll |= DPLL_DVO_HIGH_SPEED;
5865         }
5866         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5867                 dpll |= DPLL_DVO_HIGH_SPEED;
5868
5869         /* compute bitmask from p1 value */
5870         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5871         /* also FPA1 */
5872         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5873
5874         switch (clock.p2) {
5875         case 5:
5876                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5877                 break;
5878         case 7:
5879                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5880                 break;
5881         case 10:
5882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5883                 break;
5884         case 14:
5885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5886                 break;
5887         }
5888
5889         if (is_sdvo && is_tv)
5890                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5891         else if (is_tv)
5892                 /* XXX: just matching BIOS for now */
5893                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5894                 dpll |= 3;
5895         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5896                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5897         else
5898                 dpll |= PLL_REF_INPUT_DREFCLK;
5899
5900         /* setup pipeconf */
5901         pipeconf = I915_READ(PIPECONF(pipe));
5902
5903         /* Set up the display plane register */
5904         dspcntr = DISPPLANE_GAMMA_ENABLE;
5905
5906         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5907         drm_mode_debug_printmodeline(mode);
5908
5909         /* PCH eDP needs FDI, but CPU eDP does not */
5910         if (!intel_crtc->no_pll) {
5911                 if (!has_edp_encoder ||
5912                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5913                         I915_WRITE(PCH_FP0(pipe), fp);
5914                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5915
5916                         POSTING_READ(PCH_DPLL(pipe));
5917                         udelay(150);
5918                 }
5919         } else {
5920                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5921                     fp == I915_READ(PCH_FP0(0))) {
5922                         intel_crtc->use_pll_a = true;
5923                         DRM_DEBUG_KMS("using pipe a dpll\n");
5924                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5925                            fp == I915_READ(PCH_FP0(1))) {
5926                         intel_crtc->use_pll_a = false;
5927                         DRM_DEBUG_KMS("using pipe b dpll\n");
5928                 } else {
5929                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5930                         return -EINVAL;
5931                 }
5932         }
5933
5934         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5935          * This is an exception to the general rule that mode_set doesn't turn
5936          * things on.
5937          */
5938         if (is_lvds) {
5939                 temp = I915_READ(PCH_LVDS);
5940                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5941                 if (HAS_PCH_CPT(dev)) {
5942                         temp &= ~PORT_TRANS_SEL_MASK;
5943                         temp |= PORT_TRANS_SEL_CPT(pipe);
5944                 } else {
5945                         if (pipe == 1)
5946                                 temp |= LVDS_PIPEB_SELECT;
5947                         else
5948                                 temp &= ~LVDS_PIPEB_SELECT;
5949                 }
5950
5951                 /* set the corresponsding LVDS_BORDER bit */
5952                 temp |= dev_priv->lvds_border_bits;
5953                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5954                  * set the DPLLs for dual-channel mode or not.
5955                  */
5956                 if (clock.p2 == 7)
5957                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5958                 else
5959                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5960
5961                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5962                  * appropriately here, but we need to look more thoroughly into how
5963                  * panels behave in the two modes.
5964                  */
5965                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5966                         lvds_sync |= LVDS_HSYNC_POLARITY;
5967                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5968                         lvds_sync |= LVDS_VSYNC_POLARITY;
5969                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5970                     != lvds_sync) {
5971                         char flags[2] = "-+";
5972                         DRM_INFO("Changing LVDS panel from "
5973                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5974                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5975                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5976                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5977                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5978                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5979                         temp |= lvds_sync;
5980                 }
5981                 I915_WRITE(PCH_LVDS, temp);
5982         }
5983
5984         pipeconf &= ~PIPECONF_DITHER_EN;
5985         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5986         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5987                 pipeconf |= PIPECONF_DITHER_EN;
5988                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5989         }
5990         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5991                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5992         } else {
5993                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5994                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5995                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5996                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5997                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5998         }
5999
6000         if (!intel_crtc->no_pll &&
6001             (!has_edp_encoder ||
6002              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
6003                 I915_WRITE(PCH_DPLL(pipe), dpll);
6004
6005                 /* Wait for the clocks to stabilize. */
6006                 POSTING_READ(PCH_DPLL(pipe));
6007                 udelay(150);
6008
6009                 /* The pixel multiplier can only be updated once the
6010                  * DPLL is enabled and the clocks are stable.
6011                  *
6012                  * So write it again.
6013                  */
6014                 I915_WRITE(PCH_DPLL(pipe), dpll);
6015         }
6016
6017         intel_crtc->lowfreq_avail = false;
6018         if (!intel_crtc->no_pll) {
6019                 if (is_lvds && has_reduced_clock && i915_powersave) {
6020                         I915_WRITE(PCH_FP1(pipe), fp2);
6021                         intel_crtc->lowfreq_avail = true;
6022                         if (HAS_PIPE_CXSR(dev)) {
6023                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6024                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6025                         }
6026                 } else {
6027                         I915_WRITE(PCH_FP1(pipe), fp);
6028                         if (HAS_PIPE_CXSR(dev)) {
6029                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6030                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6031                         }
6032                 }
6033         }
6034
6035         pipeconf &= ~PIPECONF_INTERLACE_MASK;
6036         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6037                 pipeconf |= PIPECONF_INTERLACED_ILK;
6038                 /* the chip adds 2 halflines automatically */
6039                 adjusted_mode->crtc_vtotal -= 1;
6040                 adjusted_mode->crtc_vblank_end -= 1;
6041                 I915_WRITE(VSYNCSHIFT(pipe),
6042                            adjusted_mode->crtc_hsync_start
6043                            - adjusted_mode->crtc_htotal/2);
6044         } else {
6045                 pipeconf |= PIPECONF_PROGRESSIVE;
6046                 I915_WRITE(VSYNCSHIFT(pipe), 0);
6047         }
6048
6049         I915_WRITE(HTOTAL(pipe),
6050                    (adjusted_mode->crtc_hdisplay - 1) |
6051                    ((adjusted_mode->crtc_htotal - 1) << 16));
6052         I915_WRITE(HBLANK(pipe),
6053                    (adjusted_mode->crtc_hblank_start - 1) |
6054                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6055         I915_WRITE(HSYNC(pipe),
6056                    (adjusted_mode->crtc_hsync_start - 1) |
6057                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6058
6059         I915_WRITE(VTOTAL(pipe),
6060                    (adjusted_mode->crtc_vdisplay - 1) |
6061                    ((adjusted_mode->crtc_vtotal - 1) << 16));
6062         I915_WRITE(VBLANK(pipe),
6063                    (adjusted_mode->crtc_vblank_start - 1) |
6064                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
6065         I915_WRITE(VSYNC(pipe),
6066                    (adjusted_mode->crtc_vsync_start - 1) |
6067                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6068
6069         /* pipesrc controls the size that is scaled from, which should
6070          * always be the user's requested size.
6071          */
6072         I915_WRITE(PIPESRC(pipe),
6073                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6074
6075         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6076         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6077         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6078         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6079
6080         if (has_edp_encoder &&
6081             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6082                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6083         }
6084
6085         I915_WRITE(PIPECONF(pipe), pipeconf);
6086         POSTING_READ(PIPECONF(pipe));
6087
6088         intel_wait_for_vblank(dev, pipe);
6089
6090         I915_WRITE(DSPCNTR(plane), dspcntr);
6091         POSTING_READ(DSPCNTR(plane));
6092
6093         ret = intel_pipe_set_base(crtc, x, y, old_fb);
6094
6095         intel_update_watermarks(dev);
6096
6097         return ret;
6098 }
6099
6100 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6101                                struct drm_display_mode *mode,
6102                                struct drm_display_mode *adjusted_mode,
6103                                int x, int y,
6104                                struct drm_framebuffer *old_fb)
6105 {
6106         struct drm_device *dev = crtc->dev;
6107         struct drm_i915_private *dev_priv = dev->dev_private;
6108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6109         int pipe = intel_crtc->pipe;
6110         int ret;
6111
6112         drm_vblank_pre_modeset(dev, pipe);
6113
6114         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6115                                               x, y, old_fb);
6116         drm_vblank_post_modeset(dev, pipe);
6117
6118         if (ret)
6119                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6120         else
6121                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6122
6123         return ret;
6124 }
6125
6126 static bool intel_eld_uptodate(struct drm_connector *connector,
6127                                int reg_eldv, uint32_t bits_eldv,
6128                                int reg_elda, uint32_t bits_elda,
6129                                int reg_edid)
6130 {
6131         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6132         uint8_t *eld = connector->eld;
6133         uint32_t i;
6134
6135         i = I915_READ(reg_eldv);
6136         i &= bits_eldv;
6137
6138         if (!eld[0])
6139                 return !i;
6140
6141         if (!i)
6142                 return false;
6143
6144         i = I915_READ(reg_elda);
6145         i &= ~bits_elda;
6146         I915_WRITE(reg_elda, i);
6147
6148         for (i = 0; i < eld[2]; i++)
6149                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6150                         return false;
6151
6152         return true;
6153 }
6154
6155 static void g4x_write_eld(struct drm_connector *connector,
6156                           struct drm_crtc *crtc)
6157 {
6158         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6159         uint8_t *eld = connector->eld;
6160         uint32_t eldv;
6161         uint32_t len;
6162         uint32_t i;
6163
6164         i = I915_READ(G4X_AUD_VID_DID);
6165
6166         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6167                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6168         else
6169                 eldv = G4X_ELDV_DEVCTG;
6170
6171         if (intel_eld_uptodate(connector,
6172                                G4X_AUD_CNTL_ST, eldv,
6173                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6174                                G4X_HDMIW_HDMIEDID))
6175                 return;
6176
6177         i = I915_READ(G4X_AUD_CNTL_ST);
6178         i &= ~(eldv | G4X_ELD_ADDR);
6179         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6180         I915_WRITE(G4X_AUD_CNTL_ST, i);
6181
6182         if (!eld[0])
6183                 return;
6184
6185         len = min_t(uint8_t, eld[2], len);
6186         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6187         for (i = 0; i < len; i++)
6188                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6189
6190         i = I915_READ(G4X_AUD_CNTL_ST);
6191         i |= eldv;
6192         I915_WRITE(G4X_AUD_CNTL_ST, i);
6193 }
6194
6195 static void ironlake_write_eld(struct drm_connector *connector,
6196                                      struct drm_crtc *crtc)
6197 {
6198         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6199         uint8_t *eld = connector->eld;
6200         uint32_t eldv;
6201         uint32_t i;
6202         int len;
6203         int hdmiw_hdmiedid;
6204         int aud_config;
6205         int aud_cntl_st;
6206         int aud_cntrl_st2;
6207
6208         if (HAS_PCH_IBX(connector->dev)) {
6209                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6210                 aud_config = IBX_AUD_CONFIG_A;
6211                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6212                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6213         } else {
6214                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6215                 aud_config = CPT_AUD_CONFIG_A;
6216                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6217                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6218         }
6219
6220         i = to_intel_crtc(crtc)->pipe;
6221         hdmiw_hdmiedid += i * 0x100;
6222         aud_cntl_st += i * 0x100;
6223         aud_config += i * 0x100;
6224
6225         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6226
6227         i = I915_READ(aud_cntl_st);
6228         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
6229         if (!i) {
6230                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6231                 /* operate blindly on all ports */
6232                 eldv = IBX_ELD_VALIDB;
6233                 eldv |= IBX_ELD_VALIDB << 4;
6234                 eldv |= IBX_ELD_VALIDB << 8;
6235         } else {
6236                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6237                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6238         }
6239
6240         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6241                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6242                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6243                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6244         } else
6245                 I915_WRITE(aud_config, 0);
6246
6247         if (intel_eld_uptodate(connector,
6248                                aud_cntrl_st2, eldv,
6249                                aud_cntl_st, IBX_ELD_ADDRESS,
6250                                hdmiw_hdmiedid))
6251                 return;
6252
6253         i = I915_READ(aud_cntrl_st2);
6254         i &= ~eldv;
6255         I915_WRITE(aud_cntrl_st2, i);
6256
6257         if (!eld[0])
6258                 return;
6259
6260         i = I915_READ(aud_cntl_st);
6261         i &= ~IBX_ELD_ADDRESS;
6262         I915_WRITE(aud_cntl_st, i);
6263
6264         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6265         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6266         for (i = 0; i < len; i++)
6267                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6268
6269         i = I915_READ(aud_cntrl_st2);
6270         i |= eldv;
6271         I915_WRITE(aud_cntrl_st2, i);
6272 }
6273
6274 void intel_write_eld(struct drm_encoder *encoder,
6275                      struct drm_display_mode *mode)
6276 {
6277         struct drm_crtc *crtc = encoder->crtc;
6278         struct drm_connector *connector;
6279         struct drm_device *dev = encoder->dev;
6280         struct drm_i915_private *dev_priv = dev->dev_private;
6281
6282         connector = drm_select_eld(encoder, mode);
6283         if (!connector)
6284                 return;
6285
6286         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6287                          connector->base.id,
6288                          drm_get_connector_name(connector),
6289                          connector->encoder->base.id,
6290                          drm_get_encoder_name(connector->encoder));
6291
6292         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6293
6294         if (dev_priv->display.write_eld)
6295                 dev_priv->display.write_eld(connector, crtc);
6296 }
6297
6298 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6299 void intel_crtc_load_lut(struct drm_crtc *crtc)
6300 {
6301         struct drm_device *dev = crtc->dev;
6302         struct drm_i915_private *dev_priv = dev->dev_private;
6303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304         int palreg = PALETTE(intel_crtc->pipe);
6305         int i;
6306
6307         /* The clocks have to be on to load the palette. */
6308         if (!crtc->enabled || !intel_crtc->active)
6309                 return;
6310
6311         /* use legacy palette for Ironlake */
6312         if (HAS_PCH_SPLIT(dev))
6313                 palreg = LGC_PALETTE(intel_crtc->pipe);
6314
6315         for (i = 0; i < 256; i++) {
6316                 I915_WRITE(palreg + 4 * i,
6317                            (intel_crtc->lut_r[i] << 16) |
6318                            (intel_crtc->lut_g[i] << 8) |
6319                            intel_crtc->lut_b[i]);
6320         }
6321 }
6322
6323 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6324 {
6325         struct drm_device *dev = crtc->dev;
6326         struct drm_i915_private *dev_priv = dev->dev_private;
6327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328         bool visible = base != 0;
6329         u32 cntl;
6330
6331         if (intel_crtc->cursor_visible == visible)
6332                 return;
6333
6334         cntl = I915_READ(_CURACNTR);
6335         if (visible) {
6336                 /* On these chipsets we can only modify the base whilst
6337                  * the cursor is disabled.
6338                  */
6339                 I915_WRITE(_CURABASE, base);
6340
6341                 cntl &= ~(CURSOR_FORMAT_MASK);
6342                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6343                 cntl |= CURSOR_ENABLE |
6344                         CURSOR_GAMMA_ENABLE |
6345                         CURSOR_FORMAT_ARGB;
6346         } else
6347                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6348         I915_WRITE(_CURACNTR, cntl);
6349
6350         intel_crtc->cursor_visible = visible;
6351 }
6352
6353 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6354 {
6355         struct drm_device *dev = crtc->dev;
6356         struct drm_i915_private *dev_priv = dev->dev_private;
6357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358         int pipe = intel_crtc->pipe;
6359         bool visible = base != 0;
6360
6361         if (intel_crtc->cursor_visible != visible) {
6362                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6363                 if (base) {
6364                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6365                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6366                         cntl |= pipe << 28; /* Connect to correct pipe */
6367                 } else {
6368                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6369                         cntl |= CURSOR_MODE_DISABLE;
6370                 }
6371                 I915_WRITE(CURCNTR(pipe), cntl);
6372
6373                 intel_crtc->cursor_visible = visible;
6374         }
6375         /* and commit changes on next vblank */
6376         I915_WRITE(CURBASE(pipe), base);
6377 }
6378
6379 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6380 {
6381         struct drm_device *dev = crtc->dev;
6382         struct drm_i915_private *dev_priv = dev->dev_private;
6383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384         int pipe = intel_crtc->pipe;
6385         bool visible = base != 0;
6386
6387         if (intel_crtc->cursor_visible != visible) {
6388                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6389                 if (base) {
6390                         cntl &= ~CURSOR_MODE;
6391                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6392                 } else {
6393                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6394                         cntl |= CURSOR_MODE_DISABLE;
6395                 }
6396                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6397
6398                 intel_crtc->cursor_visible = visible;
6399         }
6400         /* and commit changes on next vblank */
6401         I915_WRITE(CURBASE_IVB(pipe), base);
6402 }
6403
6404 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6405 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6406                                      bool on)
6407 {
6408         struct drm_device *dev = crtc->dev;
6409         struct drm_i915_private *dev_priv = dev->dev_private;
6410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6411         int pipe = intel_crtc->pipe;
6412         int x = intel_crtc->cursor_x;
6413         int y = intel_crtc->cursor_y;
6414         u32 base, pos;
6415         bool visible;
6416
6417         pos = 0;
6418
6419         if (on && crtc->enabled && crtc->fb) {
6420                 base = intel_crtc->cursor_addr;
6421                 if (x > (int) crtc->fb->width)
6422                         base = 0;
6423
6424                 if (y > (int) crtc->fb->height)
6425                         base = 0;
6426         } else
6427                 base = 0;
6428
6429         if (x < 0) {
6430                 if (x + intel_crtc->cursor_width < 0)
6431                         base = 0;
6432
6433                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6434                 x = -x;
6435         }
6436         pos |= x << CURSOR_X_SHIFT;
6437
6438         if (y < 0) {
6439                 if (y + intel_crtc->cursor_height < 0)
6440                         base = 0;
6441
6442                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6443                 y = -y;
6444         }
6445         pos |= y << CURSOR_Y_SHIFT;
6446
6447         visible = base != 0;
6448         if (!visible && !intel_crtc->cursor_visible)
6449                 return;
6450
6451         if (IS_IVYBRIDGE(dev)) {
6452                 I915_WRITE(CURPOS_IVB(pipe), pos);
6453                 ivb_update_cursor(crtc, base);
6454         } else {
6455                 I915_WRITE(CURPOS(pipe), pos);
6456                 if (IS_845G(dev) || IS_I865G(dev))
6457                         i845_update_cursor(crtc, base);
6458                 else
6459                         i9xx_update_cursor(crtc, base);
6460         }
6461
6462         if (visible)
6463                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6464 }
6465
6466 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6467                                  struct drm_file *file,
6468                                  uint32_t handle,
6469                                  uint32_t width, uint32_t height)
6470 {
6471         struct drm_device *dev = crtc->dev;
6472         struct drm_i915_private *dev_priv = dev->dev_private;
6473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6474         struct drm_i915_gem_object *obj;
6475         uint32_t addr;
6476         int ret;
6477
6478         DRM_DEBUG_KMS("\n");
6479
6480         /* if we want to turn off the cursor ignore width and height */
6481         if (!handle) {
6482                 DRM_DEBUG_KMS("cursor off\n");
6483                 addr = 0;
6484                 obj = NULL;
6485                 mutex_lock(&dev->struct_mutex);
6486                 goto finish;
6487         }
6488
6489         /* Currently we only support 64x64 cursors */
6490         if (width != 64 || height != 64) {
6491                 DRM_ERROR("we currently only support 64x64 cursors\n");
6492                 return -EINVAL;
6493         }
6494
6495         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6496         if (&obj->base == NULL)
6497                 return -ENOENT;
6498
6499         if (obj->base.size < width * height * 4) {
6500                 DRM_ERROR("buffer is to small\n");
6501                 ret = -ENOMEM;
6502                 goto fail;
6503         }
6504
6505         /* we only need to pin inside GTT if cursor is non-phy */
6506         mutex_lock(&dev->struct_mutex);
6507         if (!dev_priv->info->cursor_needs_physical) {
6508                 if (obj->tiling_mode) {
6509                         DRM_ERROR("cursor cannot be tiled\n");
6510                         ret = -EINVAL;
6511                         goto fail_locked;
6512                 }
6513
6514                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6515                 if (ret) {
6516                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6517                         goto fail_locked;
6518                 }
6519
6520                 ret = i915_gem_object_put_fence(obj);
6521                 if (ret) {
6522                         DRM_ERROR("failed to release fence for cursor");
6523                         goto fail_unpin;
6524                 }
6525
6526                 addr = obj->gtt_offset;
6527         } else {
6528                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6529                 ret = i915_gem_attach_phys_object(dev, obj,
6530                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6531                                                   align);
6532                 if (ret) {
6533                         DRM_ERROR("failed to attach phys object\n");
6534                         goto fail_locked;
6535                 }
6536                 addr = obj->phys_obj->handle->busaddr;
6537         }
6538
6539         if (IS_GEN2(dev))
6540                 I915_WRITE(CURSIZE, (height << 12) | width);
6541
6542  finish:
6543         if (intel_crtc->cursor_bo) {
6544                 if (dev_priv->info->cursor_needs_physical) {
6545                         if (intel_crtc->cursor_bo != obj)
6546                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6547                 } else
6548                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6549                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6550         }
6551
6552         mutex_unlock(&dev->struct_mutex);
6553
6554         intel_crtc->cursor_addr = addr;
6555         intel_crtc->cursor_bo = obj;
6556         intel_crtc->cursor_width = width;
6557         intel_crtc->cursor_height = height;
6558
6559         intel_crtc_update_cursor(crtc, true);
6560
6561         return 0;
6562 fail_unpin:
6563         i915_gem_object_unpin(obj);
6564 fail_locked:
6565         mutex_unlock(&dev->struct_mutex);
6566 fail:
6567         drm_gem_object_unreference_unlocked(&obj->base);
6568         return ret;
6569 }
6570
6571 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6572 {
6573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6574
6575         intel_crtc->cursor_x = x;
6576         intel_crtc->cursor_y = y;
6577
6578         intel_crtc_update_cursor(crtc, true);
6579
6580         return 0;
6581 }
6582
6583 /** Sets the color ramps on behalf of RandR */
6584 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6585                                  u16 blue, int regno)
6586 {
6587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6588
6589         intel_crtc->lut_r[regno] = red >> 8;
6590         intel_crtc->lut_g[regno] = green >> 8;
6591         intel_crtc->lut_b[regno] = blue >> 8;
6592 }
6593
6594 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6595                              u16 *blue, int regno)
6596 {
6597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6598
6599         *red = intel_crtc->lut_r[regno] << 8;
6600         *green = intel_crtc->lut_g[regno] << 8;
6601         *blue = intel_crtc->lut_b[regno] << 8;
6602 }
6603
6604 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6605                                  u16 *blue, uint32_t start, uint32_t size)
6606 {
6607         int end = (start + size > 256) ? 256 : start + size, i;
6608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6609
6610         for (i = start; i < end; i++) {
6611                 intel_crtc->lut_r[i] = red[i] >> 8;
6612                 intel_crtc->lut_g[i] = green[i] >> 8;
6613                 intel_crtc->lut_b[i] = blue[i] >> 8;
6614         }
6615
6616         intel_crtc_load_lut(crtc);
6617 }
6618
6619 /**
6620  * Get a pipe with a simple mode set on it for doing load-based monitor
6621  * detection.
6622  *
6623  * It will be up to the load-detect code to adjust the pipe as appropriate for
6624  * its requirements.  The pipe will be connected to no other encoders.
6625  *
6626  * Currently this code will only succeed if there is a pipe with no encoders
6627  * configured for it.  In the future, it could choose to temporarily disable
6628  * some outputs to free up a pipe for its use.
6629  *
6630  * \return crtc, or NULL if no pipes are available.
6631  */
6632
6633 /* VESA 640x480x72Hz mode to set on the pipe */
6634 static struct drm_display_mode load_detect_mode = {
6635         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6636                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6637 };
6638
6639 static struct drm_framebuffer *
6640 intel_framebuffer_create(struct drm_device *dev,
6641                          struct drm_mode_fb_cmd2 *mode_cmd,
6642                          struct drm_i915_gem_object *obj)
6643 {
6644         struct intel_framebuffer *intel_fb;
6645         int ret;
6646
6647         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6648         if (!intel_fb) {
6649                 drm_gem_object_unreference_unlocked(&obj->base);
6650                 return ERR_PTR(-ENOMEM);
6651         }
6652
6653         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6654         if (ret) {
6655                 drm_gem_object_unreference_unlocked(&obj->base);
6656                 kfree(intel_fb);
6657                 return ERR_PTR(ret);
6658         }
6659
6660         return &intel_fb->base;
6661 }
6662
6663 static u32
6664 intel_framebuffer_pitch_for_width(int width, int bpp)
6665 {
6666         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6667         return ALIGN(pitch, 64);
6668 }
6669
6670 static u32
6671 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6672 {
6673         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6674         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6675 }
6676
6677 static struct drm_framebuffer *
6678 intel_framebuffer_create_for_mode(struct drm_device *dev,
6679                                   struct drm_display_mode *mode,
6680                                   int depth, int bpp)
6681 {
6682         struct drm_i915_gem_object *obj;
6683         struct drm_mode_fb_cmd2 mode_cmd;
6684
6685         obj = i915_gem_alloc_object(dev,
6686                                     intel_framebuffer_size_for_mode(mode, bpp));
6687         if (obj == NULL)
6688                 return ERR_PTR(-ENOMEM);
6689
6690         mode_cmd.width = mode->hdisplay;
6691         mode_cmd.height = mode->vdisplay;
6692         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6693                                                                 bpp);
6694         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6695
6696         return intel_framebuffer_create(dev, &mode_cmd, obj);
6697 }
6698
6699 static struct drm_framebuffer *
6700 mode_fits_in_fbdev(struct drm_device *dev,
6701                    struct drm_display_mode *mode)
6702 {
6703         struct drm_i915_private *dev_priv = dev->dev_private;
6704         struct drm_i915_gem_object *obj;
6705         struct drm_framebuffer *fb;
6706
6707         if (dev_priv->fbdev == NULL)
6708                 return NULL;
6709
6710         obj = dev_priv->fbdev->ifb.obj;
6711         if (obj == NULL)
6712                 return NULL;
6713
6714         fb = &dev_priv->fbdev->ifb.base;
6715         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6716                                                                fb->bits_per_pixel))
6717                 return NULL;
6718
6719         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6720                 return NULL;
6721
6722         return fb;
6723 }
6724
6725 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6726                                 struct drm_connector *connector,
6727                                 struct drm_display_mode *mode,
6728                                 struct intel_load_detect_pipe *old)
6729 {
6730         struct intel_crtc *intel_crtc;
6731         struct drm_crtc *possible_crtc;
6732         struct drm_encoder *encoder = &intel_encoder->base;
6733         struct drm_crtc *crtc = NULL;
6734         struct drm_device *dev = encoder->dev;
6735         struct drm_framebuffer *old_fb;
6736         int i = -1;
6737
6738         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6739                       connector->base.id, drm_get_connector_name(connector),
6740                       encoder->base.id, drm_get_encoder_name(encoder));
6741
6742         /*
6743          * Algorithm gets a little messy:
6744          *
6745          *   - if the connector already has an assigned crtc, use it (but make
6746          *     sure it's on first)
6747          *
6748          *   - try to find the first unused crtc that can drive this connector,
6749          *     and use that if we find one
6750          */
6751
6752         /* See if we already have a CRTC for this connector */
6753         if (encoder->crtc) {
6754                 crtc = encoder->crtc;
6755
6756                 intel_crtc = to_intel_crtc(crtc);
6757                 old->dpms_mode = intel_crtc->dpms_mode;
6758                 old->load_detect_temp = false;
6759
6760                 /* Make sure the crtc and connector are running */
6761                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6762                         struct drm_encoder_helper_funcs *encoder_funcs;
6763                         struct drm_crtc_helper_funcs *crtc_funcs;
6764
6765                         crtc_funcs = crtc->helper_private;
6766                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6767
6768                         encoder_funcs = encoder->helper_private;
6769                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6770                 }
6771
6772                 return true;
6773         }
6774
6775         /* Find an unused one (if possible) */
6776         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6777                 i++;
6778                 if (!(encoder->possible_crtcs & (1 << i)))
6779                         continue;
6780                 if (!possible_crtc->enabled) {
6781                         crtc = possible_crtc;
6782                         break;
6783                 }
6784         }
6785
6786         /*
6787          * If we didn't find an unused CRTC, don't use any.
6788          */
6789         if (!crtc) {
6790                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6791                 return false;
6792         }
6793
6794         encoder->crtc = crtc;
6795         connector->encoder = encoder;
6796
6797         intel_crtc = to_intel_crtc(crtc);
6798         old->dpms_mode = intel_crtc->dpms_mode;
6799         old->load_detect_temp = true;
6800         old->release_fb = NULL;
6801
6802         if (!mode)
6803                 mode = &load_detect_mode;
6804
6805         old_fb = crtc->fb;
6806
6807         /* We need a framebuffer large enough to accommodate all accesses
6808          * that the plane may generate whilst we perform load detection.
6809          * We can not rely on the fbcon either being present (we get called
6810          * during its initialisation to detect all boot displays, or it may
6811          * not even exist) or that it is large enough to satisfy the
6812          * requested mode.
6813          */
6814         crtc->fb = mode_fits_in_fbdev(dev, mode);
6815         if (crtc->fb == NULL) {
6816                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6817                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6818                 old->release_fb = crtc->fb;
6819         } else
6820                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6821         if (IS_ERR(crtc->fb)) {
6822                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6823                 crtc->fb = old_fb;
6824                 return false;
6825         }
6826
6827         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6828                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6829                 if (old->release_fb)
6830                         old->release_fb->funcs->destroy(old->release_fb);
6831                 crtc->fb = old_fb;
6832                 return false;
6833         }
6834
6835         /* let the connector get through one full cycle before testing */
6836         intel_wait_for_vblank(dev, intel_crtc->pipe);
6837
6838         return true;
6839 }
6840
6841 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6842                                     struct drm_connector *connector,
6843                                     struct intel_load_detect_pipe *old)
6844 {
6845         struct drm_encoder *encoder = &intel_encoder->base;
6846         struct drm_device *dev = encoder->dev;
6847         struct drm_crtc *crtc = encoder->crtc;
6848         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6849         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6850
6851         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6852                       connector->base.id, drm_get_connector_name(connector),
6853                       encoder->base.id, drm_get_encoder_name(encoder));
6854
6855         if (old->load_detect_temp) {
6856                 connector->encoder = NULL;
6857                 drm_helper_disable_unused_functions(dev);
6858
6859                 if (old->release_fb)
6860                         old->release_fb->funcs->destroy(old->release_fb);
6861
6862                 return;
6863         }
6864
6865         /* Switch crtc and encoder back off if necessary */
6866         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6867                 encoder_funcs->dpms(encoder, old->dpms_mode);
6868                 crtc_funcs->dpms(crtc, old->dpms_mode);
6869         }
6870 }
6871
6872 /* Returns the clock of the currently programmed mode of the given pipe. */
6873 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6874 {
6875         struct drm_i915_private *dev_priv = dev->dev_private;
6876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877         int pipe = intel_crtc->pipe;
6878         u32 dpll = I915_READ(DPLL(pipe));
6879         u32 fp;
6880         intel_clock_t clock;
6881
6882         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6883                 fp = I915_READ(FP0(pipe));
6884         else
6885                 fp = I915_READ(FP1(pipe));
6886
6887         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6888         if (IS_PINEVIEW(dev)) {
6889                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6890                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6891         } else {
6892                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6893                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6894         }
6895
6896         if (!IS_GEN2(dev)) {
6897                 if (IS_PINEVIEW(dev))
6898                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6899                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6900                 else
6901                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6902                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6903
6904                 switch (dpll & DPLL_MODE_MASK) {
6905                 case DPLLB_MODE_DAC_SERIAL:
6906                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6907                                 5 : 10;
6908                         break;
6909                 case DPLLB_MODE_LVDS:
6910                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6911                                 7 : 14;
6912                         break;
6913                 default:
6914                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6915                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6916                         return 0;
6917                 }
6918
6919                 /* XXX: Handle the 100Mhz refclk */
6920                 intel_clock(dev, 96000, &clock);
6921         } else {
6922                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6923
6924                 if (is_lvds) {
6925                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6926                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6927                         clock.p2 = 14;
6928
6929                         if ((dpll & PLL_REF_INPUT_MASK) ==
6930                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6931                                 /* XXX: might not be 66MHz */
6932                                 intel_clock(dev, 66000, &clock);
6933                         } else
6934                                 intel_clock(dev, 48000, &clock);
6935                 } else {
6936                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6937                                 clock.p1 = 2;
6938                         else {
6939                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6940                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6941                         }
6942                         if (dpll & PLL_P2_DIVIDE_BY_4)
6943                                 clock.p2 = 4;
6944                         else
6945                                 clock.p2 = 2;
6946
6947                         intel_clock(dev, 48000, &clock);
6948                 }
6949         }
6950
6951         /* XXX: It would be nice to validate the clocks, but we can't reuse
6952          * i830PllIsValid() because it relies on the xf86_config connector
6953          * configuration being accurate, which it isn't necessarily.
6954          */
6955
6956         return clock.dot;
6957 }
6958
6959 /** Returns the currently programmed mode of the given pipe. */
6960 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6961                                              struct drm_crtc *crtc)
6962 {
6963         struct drm_i915_private *dev_priv = dev->dev_private;
6964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6965         int pipe = intel_crtc->pipe;
6966         struct drm_display_mode *mode;
6967         int htot = I915_READ(HTOTAL(pipe));
6968         int hsync = I915_READ(HSYNC(pipe));
6969         int vtot = I915_READ(VTOTAL(pipe));
6970         int vsync = I915_READ(VSYNC(pipe));
6971
6972         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6973         if (!mode)
6974                 return NULL;
6975
6976         mode->clock = intel_crtc_clock_get(dev, crtc);
6977         mode->hdisplay = (htot & 0xffff) + 1;
6978         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6979         mode->hsync_start = (hsync & 0xffff) + 1;
6980         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6981         mode->vdisplay = (vtot & 0xffff) + 1;
6982         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6983         mode->vsync_start = (vsync & 0xffff) + 1;
6984         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6985
6986         drm_mode_set_name(mode);
6987         drm_mode_set_crtcinfo(mode, 0);
6988
6989         return mode;
6990 }
6991
6992 #define GPU_IDLE_TIMEOUT 500 /* ms */
6993
6994 /* When this timer fires, we've been idle for awhile */
6995 static void intel_gpu_idle_timer(unsigned long arg)
6996 {
6997         struct drm_device *dev = (struct drm_device *)arg;
6998         drm_i915_private_t *dev_priv = dev->dev_private;
6999
7000         if (!list_empty(&dev_priv->mm.active_list)) {
7001                 /* Still processing requests, so just re-arm the timer. */
7002                 mod_timer(&dev_priv->idle_timer, jiffies +
7003                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7004                 return;
7005         }
7006
7007         dev_priv->busy = false;
7008         queue_work(dev_priv->wq, &dev_priv->idle_work);
7009 }
7010
7011 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
7012
7013 static void intel_crtc_idle_timer(unsigned long arg)
7014 {
7015         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
7016         struct drm_crtc *crtc = &intel_crtc->base;
7017         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
7018         struct intel_framebuffer *intel_fb;
7019
7020         intel_fb = to_intel_framebuffer(crtc->fb);
7021         if (intel_fb && intel_fb->obj->active) {
7022                 /* The framebuffer is still being accessed by the GPU. */
7023                 mod_timer(&intel_crtc->idle_timer, jiffies +
7024                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7025                 return;
7026         }
7027
7028         intel_crtc->busy = false;
7029         queue_work(dev_priv->wq, &dev_priv->idle_work);
7030 }
7031
7032 static void intel_increase_pllclock(struct drm_crtc *crtc)
7033 {
7034         struct drm_device *dev = crtc->dev;
7035         drm_i915_private_t *dev_priv = dev->dev_private;
7036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037         int pipe = intel_crtc->pipe;
7038         int dpll_reg = DPLL(pipe);
7039         int dpll;
7040
7041         if (HAS_PCH_SPLIT(dev))
7042                 return;
7043
7044         if (!dev_priv->lvds_downclock_avail)
7045                 return;
7046
7047         dpll = I915_READ(dpll_reg);
7048         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7049                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7050
7051                 assert_panel_unlocked(dev_priv, pipe);
7052
7053                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7054                 I915_WRITE(dpll_reg, dpll);
7055                 intel_wait_for_vblank(dev, pipe);
7056
7057                 dpll = I915_READ(dpll_reg);
7058                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7059                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7060         }
7061
7062         /* Schedule downclock */
7063         mod_timer(&intel_crtc->idle_timer, jiffies +
7064                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7065 }
7066
7067 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7068 {
7069         struct drm_device *dev = crtc->dev;
7070         drm_i915_private_t *dev_priv = dev->dev_private;
7071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7072         int pipe = intel_crtc->pipe;
7073         int dpll_reg = DPLL(pipe);
7074         int dpll = I915_READ(dpll_reg);
7075
7076         if (HAS_PCH_SPLIT(dev))
7077                 return;
7078
7079         if (!dev_priv->lvds_downclock_avail)
7080                 return;
7081
7082         /*
7083          * Since this is called by a timer, we should never get here in
7084          * the manual case.
7085          */
7086         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7087                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7088
7089                 assert_panel_unlocked(dev_priv, pipe);
7090
7091                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7092                 I915_WRITE(dpll_reg, dpll);
7093                 intel_wait_for_vblank(dev, pipe);
7094                 dpll = I915_READ(dpll_reg);
7095                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7096                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7097         }
7098
7099 }
7100
7101 /**
7102  * intel_idle_update - adjust clocks for idleness
7103  * @work: work struct
7104  *
7105  * Either the GPU or display (or both) went idle.  Check the busy status
7106  * here and adjust the CRTC and GPU clocks as necessary.
7107  */
7108 static void intel_idle_update(struct work_struct *work)
7109 {
7110         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7111                                                     idle_work);
7112         struct drm_device *dev = dev_priv->dev;
7113         struct drm_crtc *crtc;
7114         struct intel_crtc *intel_crtc;
7115
7116         if (!i915_powersave)
7117                 return;
7118
7119         mutex_lock(&dev->struct_mutex);
7120
7121         i915_update_gfx_val(dev_priv);
7122
7123         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7124                 /* Skip inactive CRTCs */
7125                 if (!crtc->fb)
7126                         continue;
7127
7128                 intel_crtc = to_intel_crtc(crtc);
7129                 if (!intel_crtc->busy)
7130                         intel_decrease_pllclock(crtc);
7131         }
7132
7133
7134         mutex_unlock(&dev->struct_mutex);
7135 }
7136
7137 /**
7138  * intel_mark_busy - mark the GPU and possibly the display busy
7139  * @dev: drm device
7140  * @obj: object we're operating on
7141  *
7142  * Callers can use this function to indicate that the GPU is busy processing
7143  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
7144  * buffer), we'll also mark the display as busy, so we know to increase its
7145  * clock frequency.
7146  */
7147 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7148 {
7149         drm_i915_private_t *dev_priv = dev->dev_private;
7150         struct drm_crtc *crtc = NULL;
7151         struct intel_framebuffer *intel_fb;
7152         struct intel_crtc *intel_crtc;
7153
7154         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7155                 return;
7156
7157         if (!dev_priv->busy)
7158                 dev_priv->busy = true;
7159         else
7160                 mod_timer(&dev_priv->idle_timer, jiffies +
7161                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7162
7163         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7164                 if (!crtc->fb)
7165                         continue;
7166
7167                 intel_crtc = to_intel_crtc(crtc);
7168                 intel_fb = to_intel_framebuffer(crtc->fb);
7169                 if (intel_fb->obj == obj) {
7170                         if (!intel_crtc->busy) {
7171                                 /* Non-busy -> busy, upclock */
7172                                 intel_increase_pllclock(crtc);
7173                                 intel_crtc->busy = true;
7174                         } else {
7175                                 /* Busy -> busy, put off timer */
7176                                 mod_timer(&intel_crtc->idle_timer, jiffies +
7177                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7178                         }
7179                 }
7180         }
7181 }
7182
7183 static void intel_crtc_destroy(struct drm_crtc *crtc)
7184 {
7185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186         struct drm_device *dev = crtc->dev;
7187         struct intel_unpin_work *work;
7188         unsigned long flags;
7189
7190         spin_lock_irqsave(&dev->event_lock, flags);
7191         work = intel_crtc->unpin_work;
7192         intel_crtc->unpin_work = NULL;
7193         spin_unlock_irqrestore(&dev->event_lock, flags);
7194
7195         if (work) {
7196                 cancel_work_sync(&work->work);
7197                 kfree(work);
7198         }
7199
7200         drm_crtc_cleanup(crtc);
7201
7202         kfree(intel_crtc);
7203 }
7204
7205 static void intel_unpin_work_fn(struct work_struct *__work)
7206 {
7207         struct intel_unpin_work *work =
7208                 container_of(__work, struct intel_unpin_work, work);
7209
7210         mutex_lock(&work->dev->struct_mutex);
7211         intel_unpin_fb_obj(work->old_fb_obj);
7212         drm_gem_object_unreference(&work->pending_flip_obj->base);
7213         drm_gem_object_unreference(&work->old_fb_obj->base);
7214
7215         intel_update_fbc(work->dev);
7216         mutex_unlock(&work->dev->struct_mutex);
7217         kfree(work);
7218 }
7219
7220 static void do_intel_finish_page_flip(struct drm_device *dev,
7221                                       struct drm_crtc *crtc)
7222 {
7223         drm_i915_private_t *dev_priv = dev->dev_private;
7224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225         struct intel_unpin_work *work;
7226         struct drm_i915_gem_object *obj;
7227         struct drm_pending_vblank_event *e;
7228         struct timeval tnow, tvbl;
7229         unsigned long flags;
7230
7231         /* Ignore early vblank irqs */
7232         if (intel_crtc == NULL)
7233                 return;
7234
7235         do_gettimeofday(&tnow);
7236
7237         spin_lock_irqsave(&dev->event_lock, flags);
7238         work = intel_crtc->unpin_work;
7239         if (work == NULL || !work->pending) {
7240                 spin_unlock_irqrestore(&dev->event_lock, flags);
7241                 return;
7242         }
7243
7244         intel_crtc->unpin_work = NULL;
7245
7246         if (work->event) {
7247                 e = work->event;
7248                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7249
7250                 /* Called before vblank count and timestamps have
7251                  * been updated for the vblank interval of flip
7252                  * completion? Need to increment vblank count and
7253                  * add one videorefresh duration to returned timestamp
7254                  * to account for this. We assume this happened if we
7255                  * get called over 0.9 frame durations after the last
7256                  * timestamped vblank.
7257                  *
7258                  * This calculation can not be used with vrefresh rates
7259                  * below 5Hz (10Hz to be on the safe side) without
7260                  * promoting to 64 integers.
7261                  */
7262                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7263                     9 * crtc->framedur_ns) {
7264                         e->event.sequence++;
7265                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7266                                              crtc->framedur_ns);
7267                 }
7268
7269                 e->event.tv_sec = tvbl.tv_sec;
7270                 e->event.tv_usec = tvbl.tv_usec;
7271
7272                 list_add_tail(&e->base.link,
7273                               &e->base.file_priv->event_list);
7274                 wake_up_interruptible(&e->base.file_priv->event_wait);
7275         }
7276
7277         drm_vblank_put(dev, intel_crtc->pipe);
7278
7279         spin_unlock_irqrestore(&dev->event_lock, flags);
7280
7281         obj = work->old_fb_obj;
7282
7283         atomic_clear_mask(1 << intel_crtc->plane,
7284                           &obj->pending_flip.counter);
7285         if (atomic_read(&obj->pending_flip) == 0)
7286                 wake_up(&dev_priv->pending_flip_queue);
7287
7288         schedule_work(&work->work);
7289
7290         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7291 }
7292
7293 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7294 {
7295         drm_i915_private_t *dev_priv = dev->dev_private;
7296         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7297
7298         do_intel_finish_page_flip(dev, crtc);
7299 }
7300
7301 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7302 {
7303         drm_i915_private_t *dev_priv = dev->dev_private;
7304         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7305
7306         do_intel_finish_page_flip(dev, crtc);
7307 }
7308
7309 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7310 {
7311         drm_i915_private_t *dev_priv = dev->dev_private;
7312         struct intel_crtc *intel_crtc =
7313                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7314         unsigned long flags;
7315
7316         spin_lock_irqsave(&dev->event_lock, flags);
7317         if (intel_crtc->unpin_work) {
7318                 if ((++intel_crtc->unpin_work->pending) > 1)
7319                         DRM_ERROR("Prepared flip multiple times\n");
7320         } else {
7321                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7322         }
7323         spin_unlock_irqrestore(&dev->event_lock, flags);
7324 }
7325
7326 static int intel_gen2_queue_flip(struct drm_device *dev,
7327                                  struct drm_crtc *crtc,
7328                                  struct drm_framebuffer *fb,
7329                                  struct drm_i915_gem_object *obj)
7330 {
7331         struct drm_i915_private *dev_priv = dev->dev_private;
7332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7333         unsigned long offset;
7334         u32 flip_mask;
7335         int ret;
7336
7337         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7338         if (ret)
7339                 goto out;
7340
7341         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7342         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7343
7344         ret = BEGIN_LP_RING(6);
7345         if (ret)
7346                 goto out;
7347
7348         /* Can't queue multiple flips, so wait for the previous
7349          * one to finish before executing the next.
7350          */
7351         if (intel_crtc->plane)
7352                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7353         else
7354                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7355         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7356         OUT_RING(MI_NOOP);
7357         OUT_RING(MI_DISPLAY_FLIP |
7358                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7359         OUT_RING(fb->pitches[0]);
7360         OUT_RING(obj->gtt_offset + offset);
7361         OUT_RING(0); /* aux display base address, unused */
7362         ADVANCE_LP_RING();
7363 out:
7364         return ret;
7365 }
7366
7367 static int intel_gen3_queue_flip(struct drm_device *dev,
7368                                  struct drm_crtc *crtc,
7369                                  struct drm_framebuffer *fb,
7370                                  struct drm_i915_gem_object *obj)
7371 {
7372         struct drm_i915_private *dev_priv = dev->dev_private;
7373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7374         unsigned long offset;
7375         u32 flip_mask;
7376         int ret;
7377
7378         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7379         if (ret)
7380                 goto out;
7381
7382         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7383         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7384
7385         ret = BEGIN_LP_RING(6);
7386         if (ret)
7387                 goto out;
7388
7389         if (intel_crtc->plane)
7390                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7391         else
7392                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7393         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7394         OUT_RING(MI_NOOP);
7395         OUT_RING(MI_DISPLAY_FLIP_I915 |
7396                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7397         OUT_RING(fb->pitches[0]);
7398         OUT_RING(obj->gtt_offset + offset);
7399         OUT_RING(MI_NOOP);
7400
7401         ADVANCE_LP_RING();
7402 out:
7403         return ret;
7404 }
7405
7406 static int intel_gen4_queue_flip(struct drm_device *dev,
7407                                  struct drm_crtc *crtc,
7408                                  struct drm_framebuffer *fb,
7409                                  struct drm_i915_gem_object *obj)
7410 {
7411         struct drm_i915_private *dev_priv = dev->dev_private;
7412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413         uint32_t pf, pipesrc;
7414         int ret;
7415
7416         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7417         if (ret)
7418                 goto out;
7419
7420         ret = BEGIN_LP_RING(4);
7421         if (ret)
7422                 goto out;
7423
7424         /* i965+ uses the linear or tiled offsets from the
7425          * Display Registers (which do not change across a page-flip)
7426          * so we need only reprogram the base address.
7427          */
7428         OUT_RING(MI_DISPLAY_FLIP |
7429                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7430         OUT_RING(fb->pitches[0]);
7431         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7432
7433         /* XXX Enabling the panel-fitter across page-flip is so far
7434          * untested on non-native modes, so ignore it for now.
7435          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7436          */
7437         pf = 0;
7438         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7439         OUT_RING(pf | pipesrc);
7440         ADVANCE_LP_RING();
7441 out:
7442         return ret;
7443 }
7444
7445 static int intel_gen6_queue_flip(struct drm_device *dev,
7446                                  struct drm_crtc *crtc,
7447                                  struct drm_framebuffer *fb,
7448                                  struct drm_i915_gem_object *obj)
7449 {
7450         struct drm_i915_private *dev_priv = dev->dev_private;
7451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7452         uint32_t pf, pipesrc;
7453         int ret;
7454
7455         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7456         if (ret)
7457                 goto out;
7458
7459         ret = BEGIN_LP_RING(4);
7460         if (ret)
7461                 goto out;
7462
7463         OUT_RING(MI_DISPLAY_FLIP |
7464                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7465         OUT_RING(fb->pitches[0] | obj->tiling_mode);
7466         OUT_RING(obj->gtt_offset);
7467
7468         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7469         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7470         OUT_RING(pf | pipesrc);
7471         ADVANCE_LP_RING();
7472 out:
7473         return ret;
7474 }
7475
7476 /*
7477  * On gen7 we currently use the blit ring because (in early silicon at least)
7478  * the render ring doesn't give us interrpts for page flip completion, which
7479  * means clients will hang after the first flip is queued.  Fortunately the
7480  * blit ring generates interrupts properly, so use it instead.
7481  */
7482 static int intel_gen7_queue_flip(struct drm_device *dev,
7483                                  struct drm_crtc *crtc,
7484                                  struct drm_framebuffer *fb,
7485                                  struct drm_i915_gem_object *obj)
7486 {
7487         struct drm_i915_private *dev_priv = dev->dev_private;
7488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7489         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7490         int ret;
7491
7492         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7493         if (ret)
7494                 goto out;
7495
7496         ret = intel_ring_begin(ring, 4);
7497         if (ret)
7498                 goto out;
7499
7500         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7501         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7502         intel_ring_emit(ring, (obj->gtt_offset));
7503         intel_ring_emit(ring, (MI_NOOP));
7504         intel_ring_advance(ring);
7505 out:
7506         return ret;
7507 }
7508
7509 static int intel_default_queue_flip(struct drm_device *dev,
7510                                     struct drm_crtc *crtc,
7511                                     struct drm_framebuffer *fb,
7512                                     struct drm_i915_gem_object *obj)
7513 {
7514         return -ENODEV;
7515 }
7516
7517 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7518                                 struct drm_framebuffer *fb,
7519                                 struct drm_pending_vblank_event *event)
7520 {
7521         struct drm_device *dev = crtc->dev;
7522         struct drm_i915_private *dev_priv = dev->dev_private;
7523         struct intel_framebuffer *intel_fb;
7524         struct drm_i915_gem_object *obj;
7525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7526         struct intel_unpin_work *work;
7527         unsigned long flags;
7528         int ret;
7529
7530         work = kzalloc(sizeof *work, GFP_KERNEL);
7531         if (work == NULL)
7532                 return -ENOMEM;
7533
7534         work->event = event;
7535         work->dev = crtc->dev;
7536         intel_fb = to_intel_framebuffer(crtc->fb);
7537         work->old_fb_obj = intel_fb->obj;
7538         INIT_WORK(&work->work, intel_unpin_work_fn);
7539
7540         ret = drm_vblank_get(dev, intel_crtc->pipe);
7541         if (ret)
7542                 goto free_work;
7543
7544         /* We borrow the event spin lock for protecting unpin_work */
7545         spin_lock_irqsave(&dev->event_lock, flags);
7546         if (intel_crtc->unpin_work) {
7547                 spin_unlock_irqrestore(&dev->event_lock, flags);
7548                 kfree(work);
7549                 drm_vblank_put(dev, intel_crtc->pipe);
7550
7551                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7552                 return -EBUSY;
7553         }
7554         intel_crtc->unpin_work = work;
7555         spin_unlock_irqrestore(&dev->event_lock, flags);
7556
7557         intel_fb = to_intel_framebuffer(fb);
7558         obj = intel_fb->obj;
7559
7560         mutex_lock(&dev->struct_mutex);
7561
7562         /* Reference the objects for the scheduled work. */
7563         drm_gem_object_reference(&work->old_fb_obj->base);
7564         drm_gem_object_reference(&obj->base);
7565
7566         crtc->fb = fb;
7567
7568         work->pending_flip_obj = obj;
7569
7570         work->enable_stall_check = true;
7571
7572         /* Block clients from rendering to the new back buffer until
7573          * the flip occurs and the object is no longer visible.
7574          */
7575         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7576
7577         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7578         if (ret)
7579                 goto cleanup_pending;
7580
7581         intel_disable_fbc(dev);
7582         mutex_unlock(&dev->struct_mutex);
7583
7584         trace_i915_flip_request(intel_crtc->plane, obj);
7585
7586         return 0;
7587
7588 cleanup_pending:
7589         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7590         drm_gem_object_unreference(&work->old_fb_obj->base);
7591         drm_gem_object_unreference(&obj->base);
7592         mutex_unlock(&dev->struct_mutex);
7593
7594         spin_lock_irqsave(&dev->event_lock, flags);
7595         intel_crtc->unpin_work = NULL;
7596         spin_unlock_irqrestore(&dev->event_lock, flags);
7597
7598         drm_vblank_put(dev, intel_crtc->pipe);
7599 free_work:
7600         kfree(work);
7601
7602         return ret;
7603 }
7604
7605 static void intel_sanitize_modesetting(struct drm_device *dev,
7606                                        int pipe, int plane)
7607 {
7608         struct drm_i915_private *dev_priv = dev->dev_private;
7609         u32 reg, val;
7610
7611         /* Clear any frame start delays used for debugging left by the BIOS */
7612         for_each_pipe(pipe) {
7613                 reg = PIPECONF(pipe);
7614                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7615         }
7616
7617         if (HAS_PCH_SPLIT(dev))
7618                 return;
7619
7620         /* Who knows what state these registers were left in by the BIOS or
7621          * grub?
7622          *
7623          * If we leave the registers in a conflicting state (e.g. with the
7624          * display plane reading from the other pipe than the one we intend
7625          * to use) then when we attempt to teardown the active mode, we will
7626          * not disable the pipes and planes in the correct order -- leaving
7627          * a plane reading from a disabled pipe and possibly leading to
7628          * undefined behaviour.
7629          */
7630
7631         reg = DSPCNTR(plane);
7632         val = I915_READ(reg);
7633
7634         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7635                 return;
7636         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7637                 return;
7638
7639         /* This display plane is active and attached to the other CPU pipe. */
7640         pipe = !pipe;
7641
7642         /* Disable the plane and wait for it to stop reading from the pipe. */
7643         intel_disable_plane(dev_priv, plane, pipe);
7644         intel_disable_pipe(dev_priv, pipe);
7645 }
7646
7647 static void intel_crtc_reset(struct drm_crtc *crtc)
7648 {
7649         struct drm_device *dev = crtc->dev;
7650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7651
7652         /* Reset flags back to the 'unknown' status so that they
7653          * will be correctly set on the initial modeset.
7654          */
7655         intel_crtc->dpms_mode = -1;
7656
7657         /* We need to fix up any BIOS configuration that conflicts with
7658          * our expectations.
7659          */
7660         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7661 }
7662
7663 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7664         .dpms = intel_crtc_dpms,
7665         .mode_fixup = intel_crtc_mode_fixup,
7666         .mode_set = intel_crtc_mode_set,
7667         .mode_set_base = intel_pipe_set_base,
7668         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7669         .load_lut = intel_crtc_load_lut,
7670         .disable = intel_crtc_disable,
7671 };
7672
7673 static const struct drm_crtc_funcs intel_crtc_funcs = {
7674         .reset = intel_crtc_reset,
7675         .cursor_set = intel_crtc_cursor_set,
7676         .cursor_move = intel_crtc_cursor_move,
7677         .gamma_set = intel_crtc_gamma_set,
7678         .set_config = drm_crtc_helper_set_config,
7679         .destroy = intel_crtc_destroy,
7680         .page_flip = intel_crtc_page_flip,
7681 };
7682
7683 static void intel_crtc_init(struct drm_device *dev, int pipe)
7684 {
7685         drm_i915_private_t *dev_priv = dev->dev_private;
7686         struct intel_crtc *intel_crtc;
7687         int i;
7688
7689         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7690         if (intel_crtc == NULL)
7691                 return;
7692
7693         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7694
7695         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7696         for (i = 0; i < 256; i++) {
7697                 intel_crtc->lut_r[i] = i;
7698                 intel_crtc->lut_g[i] = i;
7699                 intel_crtc->lut_b[i] = i;
7700         }
7701
7702         /* Swap pipes & planes for FBC on pre-965 */
7703         intel_crtc->pipe = pipe;
7704         intel_crtc->plane = pipe;
7705         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7706                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7707                 intel_crtc->plane = !pipe;
7708         }
7709
7710         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7711                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7712         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7713         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7714
7715         intel_crtc_reset(&intel_crtc->base);
7716         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7717         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7718
7719         if (HAS_PCH_SPLIT(dev)) {
7720                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7721                         intel_crtc->no_pll = true;
7722                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7723                 intel_helper_funcs.commit = ironlake_crtc_commit;
7724         } else {
7725                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7726                 intel_helper_funcs.commit = i9xx_crtc_commit;
7727         }
7728
7729         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7730
7731         intel_crtc->busy = false;
7732
7733         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7734                     (unsigned long)intel_crtc);
7735 }
7736
7737 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7738                                 struct drm_file *file)
7739 {
7740         drm_i915_private_t *dev_priv = dev->dev_private;
7741         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7742         struct drm_mode_object *drmmode_obj;
7743         struct intel_crtc *crtc;
7744
7745         if (!dev_priv) {
7746                 DRM_ERROR("called with no initialization\n");
7747                 return -EINVAL;
7748         }
7749
7750         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7751                         DRM_MODE_OBJECT_CRTC);
7752
7753         if (!drmmode_obj) {
7754                 DRM_ERROR("no such CRTC id\n");
7755                 return -EINVAL;
7756         }
7757
7758         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7759         pipe_from_crtc_id->pipe = crtc->pipe;
7760
7761         return 0;
7762 }
7763
7764 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7765 {
7766         struct intel_encoder *encoder;
7767         int index_mask = 0;
7768         int entry = 0;
7769
7770         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7771                 if (type_mask & encoder->clone_mask)
7772                         index_mask |= (1 << entry);
7773                 entry++;
7774         }
7775
7776         return index_mask;
7777 }
7778
7779 static bool has_edp_a(struct drm_device *dev)
7780 {
7781         struct drm_i915_private *dev_priv = dev->dev_private;
7782
7783         if (!IS_MOBILE(dev))
7784                 return false;
7785
7786         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7787                 return false;
7788
7789         if (IS_GEN5(dev) &&
7790             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7791                 return false;
7792
7793         return true;
7794 }
7795
7796 static void intel_setup_outputs(struct drm_device *dev)
7797 {
7798         struct drm_i915_private *dev_priv = dev->dev_private;
7799         struct intel_encoder *encoder;
7800         bool dpd_is_edp = false;
7801         bool has_lvds;
7802
7803         has_lvds = intel_lvds_init(dev);
7804         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7805                 /* disable the panel fitter on everything but LVDS */
7806                 I915_WRITE(PFIT_CONTROL, 0);
7807         }
7808
7809         if (HAS_PCH_SPLIT(dev)) {
7810                 dpd_is_edp = intel_dpd_is_edp(dev);
7811
7812                 if (has_edp_a(dev))
7813                         intel_dp_init(dev, DP_A);
7814
7815                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7816                         intel_dp_init(dev, PCH_DP_D);
7817         }
7818
7819         intel_crt_init(dev);
7820
7821         if (HAS_PCH_SPLIT(dev)) {
7822                 int found;
7823
7824                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7825                         /* PCH SDVOB multiplex with HDMIB */
7826                         found = intel_sdvo_init(dev, PCH_SDVOB);
7827                         if (!found)
7828                                 intel_hdmi_init(dev, HDMIB);
7829                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7830                                 intel_dp_init(dev, PCH_DP_B);
7831                 }
7832
7833                 if (I915_READ(HDMIC) & PORT_DETECTED)
7834                         intel_hdmi_init(dev, HDMIC);
7835
7836                 if (I915_READ(HDMID) & PORT_DETECTED)
7837                         intel_hdmi_init(dev, HDMID);
7838
7839                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7840                         intel_dp_init(dev, PCH_DP_C);
7841
7842                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7843                         intel_dp_init(dev, PCH_DP_D);
7844
7845         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7846                 bool found = false;
7847
7848                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7849                         DRM_DEBUG_KMS("probing SDVOB\n");
7850                         found = intel_sdvo_init(dev, SDVOB);
7851                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7852                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7853                                 intel_hdmi_init(dev, SDVOB);
7854                         }
7855
7856                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7857                                 DRM_DEBUG_KMS("probing DP_B\n");
7858                                 intel_dp_init(dev, DP_B);
7859                         }
7860                 }
7861
7862                 /* Before G4X SDVOC doesn't have its own detect register */
7863
7864                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7865                         DRM_DEBUG_KMS("probing SDVOC\n");
7866                         found = intel_sdvo_init(dev, SDVOC);
7867                 }
7868
7869                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7870
7871                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7872                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7873                                 intel_hdmi_init(dev, SDVOC);
7874                         }
7875                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7876                                 DRM_DEBUG_KMS("probing DP_C\n");
7877                                 intel_dp_init(dev, DP_C);
7878                         }
7879                 }
7880
7881                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7882                     (I915_READ(DP_D) & DP_DETECTED)) {
7883                         DRM_DEBUG_KMS("probing DP_D\n");
7884                         intel_dp_init(dev, DP_D);
7885                 }
7886         } else if (IS_GEN2(dev))
7887                 intel_dvo_init(dev);
7888
7889         if (SUPPORTS_TV(dev))
7890                 intel_tv_init(dev);
7891
7892         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7893                 encoder->base.possible_crtcs = encoder->crtc_mask;
7894                 encoder->base.possible_clones =
7895                         intel_encoder_clones(dev, encoder->clone_mask);
7896         }
7897
7898         /* disable all the possible outputs/crtcs before entering KMS mode */
7899         drm_helper_disable_unused_functions(dev);
7900
7901         if (HAS_PCH_SPLIT(dev))
7902                 ironlake_init_pch_refclk(dev);
7903 }
7904
7905 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7906 {
7907         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7908
7909         drm_framebuffer_cleanup(fb);
7910         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7911
7912         kfree(intel_fb);
7913 }
7914
7915 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7916                                                 struct drm_file *file,
7917                                                 unsigned int *handle)
7918 {
7919         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7920         struct drm_i915_gem_object *obj = intel_fb->obj;
7921
7922         return drm_gem_handle_create(file, &obj->base, handle);
7923 }
7924
7925 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7926         .destroy = intel_user_framebuffer_destroy,
7927         .create_handle = intel_user_framebuffer_create_handle,
7928 };
7929
7930 int intel_framebuffer_init(struct drm_device *dev,
7931                            struct intel_framebuffer *intel_fb,
7932                            struct drm_mode_fb_cmd2 *mode_cmd,
7933                            struct drm_i915_gem_object *obj)
7934 {
7935         int ret;
7936
7937         if (obj->tiling_mode == I915_TILING_Y)
7938                 return -EINVAL;
7939
7940         if (mode_cmd->pitches[0] & 63)
7941                 return -EINVAL;
7942
7943         switch (mode_cmd->pixel_format) {
7944         case DRM_FORMAT_RGB332:
7945         case DRM_FORMAT_RGB565:
7946         case DRM_FORMAT_XRGB8888:
7947         case DRM_FORMAT_XBGR8888:
7948         case DRM_FORMAT_ARGB8888:
7949         case DRM_FORMAT_XRGB2101010:
7950         case DRM_FORMAT_ARGB2101010:
7951                 /* RGB formats are common across chipsets */
7952                 break;
7953         case DRM_FORMAT_YUYV:
7954         case DRM_FORMAT_UYVY:
7955         case DRM_FORMAT_YVYU:
7956         case DRM_FORMAT_VYUY:
7957                 break;
7958         default:
7959                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7960                                 mode_cmd->pixel_format);
7961                 return -EINVAL;
7962         }
7963
7964         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7965         if (ret) {
7966                 DRM_ERROR("framebuffer init failed %d\n", ret);
7967                 return ret;
7968         }
7969
7970         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7971         intel_fb->obj = obj;
7972         return 0;
7973 }
7974
7975 static struct drm_framebuffer *
7976 intel_user_framebuffer_create(struct drm_device *dev,
7977                               struct drm_file *filp,
7978                               struct drm_mode_fb_cmd2 *mode_cmd)
7979 {
7980         struct drm_i915_gem_object *obj;
7981
7982         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7983                                                 mode_cmd->handles[0]));
7984         if (&obj->base == NULL)
7985                 return ERR_PTR(-ENOENT);
7986
7987         return intel_framebuffer_create(dev, mode_cmd, obj);
7988 }
7989
7990 static const struct drm_mode_config_funcs intel_mode_funcs = {
7991         .fb_create = intel_user_framebuffer_create,
7992         .output_poll_changed = intel_fb_output_poll_changed,
7993 };
7994
7995 static struct drm_i915_gem_object *
7996 intel_alloc_context_page(struct drm_device *dev)
7997 {
7998         struct drm_i915_gem_object *ctx;
7999         int ret;
8000
8001         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8002
8003         ctx = i915_gem_alloc_object(dev, 4096);
8004         if (!ctx) {
8005                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
8006                 return NULL;
8007         }
8008
8009         ret = i915_gem_object_pin(ctx, 4096, true);
8010         if (ret) {
8011                 DRM_ERROR("failed to pin power context: %d\n", ret);
8012                 goto err_unref;
8013         }
8014
8015         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
8016         if (ret) {
8017                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
8018                 goto err_unpin;
8019         }
8020
8021         return ctx;
8022
8023 err_unpin:
8024         i915_gem_object_unpin(ctx);
8025 err_unref:
8026         drm_gem_object_unreference(&ctx->base);
8027         mutex_unlock(&dev->struct_mutex);
8028         return NULL;
8029 }
8030
8031 bool ironlake_set_drps(struct drm_device *dev, u8 val)
8032 {
8033         struct drm_i915_private *dev_priv = dev->dev_private;
8034         u16 rgvswctl;
8035
8036         rgvswctl = I915_READ16(MEMSWCTL);
8037         if (rgvswctl & MEMCTL_CMD_STS) {
8038                 DRM_DEBUG("gpu busy, RCS change rejected\n");
8039                 return false; /* still busy with another command */
8040         }
8041
8042         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8043                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8044         I915_WRITE16(MEMSWCTL, rgvswctl);
8045         POSTING_READ16(MEMSWCTL);
8046
8047         rgvswctl |= MEMCTL_CMD_STS;
8048         I915_WRITE16(MEMSWCTL, rgvswctl);
8049
8050         return true;
8051 }
8052
8053 void ironlake_enable_drps(struct drm_device *dev)
8054 {
8055         struct drm_i915_private *dev_priv = dev->dev_private;
8056         u32 rgvmodectl = I915_READ(MEMMODECTL);
8057         u8 fmax, fmin, fstart, vstart;
8058
8059         /* Enable temp reporting */
8060         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8061         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8062
8063         /* 100ms RC evaluation intervals */
8064         I915_WRITE(RCUPEI, 100000);
8065         I915_WRITE(RCDNEI, 100000);
8066
8067         /* Set max/min thresholds to 90ms and 80ms respectively */
8068         I915_WRITE(RCBMAXAVG, 90000);
8069         I915_WRITE(RCBMINAVG, 80000);
8070
8071         I915_WRITE(MEMIHYST, 1);
8072
8073         /* Set up min, max, and cur for interrupt handling */
8074         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8075         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8076         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8077                 MEMMODE_FSTART_SHIFT;
8078
8079         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8080                 PXVFREQ_PX_SHIFT;
8081
8082         dev_priv->fmax = fmax; /* IPS callback will increase this */
8083         dev_priv->fstart = fstart;
8084
8085         dev_priv->max_delay = fstart;
8086         dev_priv->min_delay = fmin;
8087         dev_priv->cur_delay = fstart;
8088
8089         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8090                          fmax, fmin, fstart);
8091
8092         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8093
8094         /*
8095          * Interrupts will be enabled in ironlake_irq_postinstall
8096          */
8097
8098         I915_WRITE(VIDSTART, vstart);
8099         POSTING_READ(VIDSTART);
8100
8101         rgvmodectl |= MEMMODE_SWMODE_EN;
8102         I915_WRITE(MEMMODECTL, rgvmodectl);
8103
8104         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8105                 DRM_ERROR("stuck trying to change perf mode\n");
8106         msleep(1);
8107
8108         ironlake_set_drps(dev, fstart);
8109
8110         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8111                 I915_READ(0x112e0);
8112         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8113         dev_priv->last_count2 = I915_READ(0x112f4);
8114         getrawmonotonic(&dev_priv->last_time2);
8115 }
8116
8117 void ironlake_disable_drps(struct drm_device *dev)
8118 {
8119         struct drm_i915_private *dev_priv = dev->dev_private;
8120         u16 rgvswctl = I915_READ16(MEMSWCTL);
8121
8122         /* Ack interrupts, disable EFC interrupt */
8123         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8124         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8125         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8126         I915_WRITE(DEIIR, DE_PCU_EVENT);
8127         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8128
8129         /* Go back to the starting frequency */
8130         ironlake_set_drps(dev, dev_priv->fstart);
8131         msleep(1);
8132         rgvswctl |= MEMCTL_CMD_STS;
8133         I915_WRITE(MEMSWCTL, rgvswctl);
8134         msleep(1);
8135
8136 }
8137
8138 void gen6_set_rps(struct drm_device *dev, u8 val)
8139 {
8140         struct drm_i915_private *dev_priv = dev->dev_private;
8141         u32 swreq;
8142
8143         swreq = (val & 0x3ff) << 25;
8144         I915_WRITE(GEN6_RPNSWREQ, swreq);
8145 }
8146
8147 void gen6_disable_rps(struct drm_device *dev)
8148 {
8149         struct drm_i915_private *dev_priv = dev->dev_private;
8150
8151         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8152         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8153         I915_WRITE(GEN6_PMIER, 0);
8154         /* Complete PM interrupt masking here doesn't race with the rps work
8155          * item again unmasking PM interrupts because that is using a different
8156          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8157          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8158
8159         spin_lock_irq(&dev_priv->rps_lock);
8160         dev_priv->pm_iir = 0;
8161         spin_unlock_irq(&dev_priv->rps_lock);
8162
8163         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8164 }
8165
8166 static unsigned long intel_pxfreq(u32 vidfreq)
8167 {
8168         unsigned long freq;
8169         int div = (vidfreq & 0x3f0000) >> 16;
8170         int post = (vidfreq & 0x3000) >> 12;
8171         int pre = (vidfreq & 0x7);
8172
8173         if (!pre)
8174                 return 0;
8175
8176         freq = ((div * 133333) / ((1<<post) * pre));
8177
8178         return freq;
8179 }
8180
8181 void intel_init_emon(struct drm_device *dev)
8182 {
8183         struct drm_i915_private *dev_priv = dev->dev_private;
8184         u32 lcfuse;
8185         u8 pxw[16];
8186         int i;
8187
8188         /* Disable to program */
8189         I915_WRITE(ECR, 0);
8190         POSTING_READ(ECR);
8191
8192         /* Program energy weights for various events */
8193         I915_WRITE(SDEW, 0x15040d00);
8194         I915_WRITE(CSIEW0, 0x007f0000);
8195         I915_WRITE(CSIEW1, 0x1e220004);
8196         I915_WRITE(CSIEW2, 0x04000004);
8197
8198         for (i = 0; i < 5; i++)
8199                 I915_WRITE(PEW + (i * 4), 0);
8200         for (i = 0; i < 3; i++)
8201                 I915_WRITE(DEW + (i * 4), 0);
8202
8203         /* Program P-state weights to account for frequency power adjustment */
8204         for (i = 0; i < 16; i++) {
8205                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8206                 unsigned long freq = intel_pxfreq(pxvidfreq);
8207                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8208                         PXVFREQ_PX_SHIFT;
8209                 unsigned long val;
8210
8211                 val = vid * vid;
8212                 val *= (freq / 1000);
8213                 val *= 255;
8214                 val /= (127*127*900);
8215                 if (val > 0xff)
8216                         DRM_ERROR("bad pxval: %ld\n", val);
8217                 pxw[i] = val;
8218         }
8219         /* Render standby states get 0 weight */
8220         pxw[14] = 0;
8221         pxw[15] = 0;
8222
8223         for (i = 0; i < 4; i++) {
8224                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8225                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8226                 I915_WRITE(PXW + (i * 4), val);
8227         }
8228
8229         /* Adjust magic regs to magic values (more experimental results) */
8230         I915_WRITE(OGW0, 0);
8231         I915_WRITE(OGW1, 0);
8232         I915_WRITE(EG0, 0x00007f00);
8233         I915_WRITE(EG1, 0x0000000e);
8234         I915_WRITE(EG2, 0x000e0000);
8235         I915_WRITE(EG3, 0x68000300);
8236         I915_WRITE(EG4, 0x42000000);
8237         I915_WRITE(EG5, 0x00140031);
8238         I915_WRITE(EG6, 0);
8239         I915_WRITE(EG7, 0);
8240
8241         for (i = 0; i < 8; i++)
8242                 I915_WRITE(PXWL + (i * 4), 0);
8243
8244         /* Enable PMON + select events */
8245         I915_WRITE(ECR, 0x80000019);
8246
8247         lcfuse = I915_READ(LCFUSE02);
8248
8249         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8250 }
8251
8252 static int intel_enable_rc6(struct drm_device *dev)
8253 {
8254         /*
8255          * Respect the kernel parameter if it is set
8256          */
8257         if (i915_enable_rc6 >= 0)
8258                 return i915_enable_rc6;
8259
8260         /*
8261          * Disable RC6 on Ironlake
8262          */
8263         if (INTEL_INFO(dev)->gen == 5)
8264                 return 0;
8265
8266         /*
8267          * Disable rc6 on Sandybridge
8268          */
8269         if (INTEL_INFO(dev)->gen == 6) {
8270                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8271                 return INTEL_RC6_ENABLE;
8272         }
8273         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8274         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8275 }
8276
8277 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8278 {
8279         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8280         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8281         u32 pcu_mbox, rc6_mask = 0;
8282         u32 gtfifodbg;
8283         int cur_freq, min_freq, max_freq;
8284         int rc6_mode;
8285         int i;
8286
8287         /* Here begins a magic sequence of register writes to enable
8288          * auto-downclocking.
8289          *
8290          * Perhaps there might be some value in exposing these to
8291          * userspace...
8292          */
8293         I915_WRITE(GEN6_RC_STATE, 0);
8294         mutex_lock(&dev_priv->dev->struct_mutex);
8295
8296         /* Clear the DBG now so we don't confuse earlier errors */
8297         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8298                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8299                 I915_WRITE(GTFIFODBG, gtfifodbg);
8300         }
8301
8302         gen6_gt_force_wake_get(dev_priv);
8303
8304         /* disable the counters and set deterministic thresholds */
8305         I915_WRITE(GEN6_RC_CONTROL, 0);
8306
8307         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8308         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8309         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8310         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8311         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8312
8313         for (i = 0; i < I915_NUM_RINGS; i++)
8314                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8315
8316         I915_WRITE(GEN6_RC_SLEEP, 0);
8317         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8318         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8319         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8320         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8321
8322         rc6_mode = intel_enable_rc6(dev_priv->dev);
8323         if (rc6_mode & INTEL_RC6_ENABLE)
8324                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
8325
8326         if (rc6_mode & INTEL_RC6p_ENABLE)
8327                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
8328
8329         if (rc6_mode & INTEL_RC6pp_ENABLE)
8330                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
8331
8332         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8333                         (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
8334                         (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
8335                         (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
8336
8337         I915_WRITE(GEN6_RC_CONTROL,
8338                    rc6_mask |
8339                    GEN6_RC_CTL_EI_MODE(1) |
8340                    GEN6_RC_CTL_HW_ENABLE);
8341
8342         I915_WRITE(GEN6_RPNSWREQ,
8343                    GEN6_FREQUENCY(10) |
8344                    GEN6_OFFSET(0) |
8345                    GEN6_AGGRESSIVE_TURBO);
8346         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8347                    GEN6_FREQUENCY(12));
8348
8349         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8350         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8351                    18 << 24 |
8352                    6 << 16);
8353         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8354         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8355         I915_WRITE(GEN6_RP_UP_EI, 100000);
8356         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8357         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8358         I915_WRITE(GEN6_RP_CONTROL,
8359                    GEN6_RP_MEDIA_TURBO |
8360                    GEN6_RP_MEDIA_HW_MODE |
8361                    GEN6_RP_MEDIA_IS_GFX |
8362                    GEN6_RP_ENABLE |
8363                    GEN6_RP_UP_BUSY_AVG |
8364                    GEN6_RP_DOWN_IDLE_CONT);
8365
8366         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8367                      500))
8368                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8369
8370         I915_WRITE(GEN6_PCODE_DATA, 0);
8371         I915_WRITE(GEN6_PCODE_MAILBOX,
8372                    GEN6_PCODE_READY |
8373                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8374         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8375                      500))
8376                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8377
8378         min_freq = (rp_state_cap & 0xff0000) >> 16;
8379         max_freq = rp_state_cap & 0xff;
8380         cur_freq = (gt_perf_status & 0xff00) >> 8;
8381
8382         /* Check for overclock support */
8383         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8384                      500))
8385                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8386         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8387         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8388         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8389                      500))
8390                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8391         if (pcu_mbox & (1<<31)) { /* OC supported */
8392                 max_freq = pcu_mbox & 0xff;
8393                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8394         }
8395
8396         /* In units of 100MHz */
8397         dev_priv->max_delay = max_freq;
8398         dev_priv->min_delay = min_freq;
8399         dev_priv->cur_delay = cur_freq;
8400
8401         /* requires MSI enabled */
8402         I915_WRITE(GEN6_PMIER,
8403                    GEN6_PM_MBOX_EVENT |
8404                    GEN6_PM_THERMAL_EVENT |
8405                    GEN6_PM_RP_DOWN_TIMEOUT |
8406                    GEN6_PM_RP_UP_THRESHOLD |
8407                    GEN6_PM_RP_DOWN_THRESHOLD |
8408                    GEN6_PM_RP_UP_EI_EXPIRED |
8409                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8410         spin_lock_irq(&dev_priv->rps_lock);
8411         WARN_ON(dev_priv->pm_iir != 0);
8412         I915_WRITE(GEN6_PMIMR, 0);
8413         spin_unlock_irq(&dev_priv->rps_lock);
8414         /* enable all PM interrupts */
8415         I915_WRITE(GEN6_PMINTRMSK, 0);
8416
8417         gen6_gt_force_wake_put(dev_priv);
8418         mutex_unlock(&dev_priv->dev->struct_mutex);
8419 }
8420
8421 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8422 {
8423         int min_freq = 15;
8424         int gpu_freq, ia_freq, max_ia_freq;
8425         int scaling_factor = 180;
8426
8427         max_ia_freq = cpufreq_quick_get_max(0);
8428         /*
8429          * Default to measured freq if none found, PCU will ensure we don't go
8430          * over
8431          */
8432         if (!max_ia_freq)
8433                 max_ia_freq = tsc_khz;
8434
8435         /* Convert from kHz to MHz */
8436         max_ia_freq /= 1000;
8437
8438         mutex_lock(&dev_priv->dev->struct_mutex);
8439
8440         /*
8441          * For each potential GPU frequency, load a ring frequency we'd like
8442          * to use for memory access.  We do this by specifying the IA frequency
8443          * the PCU should use as a reference to determine the ring frequency.
8444          */
8445         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8446              gpu_freq--) {
8447                 int diff = dev_priv->max_delay - gpu_freq;
8448
8449                 /*
8450                  * For GPU frequencies less than 750MHz, just use the lowest
8451                  * ring freq.
8452                  */
8453                 if (gpu_freq < min_freq)
8454                         ia_freq = 800;
8455                 else
8456                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8457                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8458
8459                 I915_WRITE(GEN6_PCODE_DATA,
8460                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8461                            gpu_freq);
8462                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8463                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8464                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8465                               GEN6_PCODE_READY) == 0, 10)) {
8466                         DRM_ERROR("pcode write of freq table timed out\n");
8467                         continue;
8468                 }
8469         }
8470
8471         mutex_unlock(&dev_priv->dev->struct_mutex);
8472 }
8473
8474 static void ironlake_init_clock_gating(struct drm_device *dev)
8475 {
8476         struct drm_i915_private *dev_priv = dev->dev_private;
8477         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8478
8479         /* Required for FBC */
8480         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8481                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8482                 DPFDUNIT_CLOCK_GATE_DISABLE;
8483         /* Required for CxSR */
8484         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8485
8486         I915_WRITE(PCH_3DCGDIS0,
8487                    MARIUNIT_CLOCK_GATE_DISABLE |
8488                    SVSMUNIT_CLOCK_GATE_DISABLE);
8489         I915_WRITE(PCH_3DCGDIS1,
8490                    VFMUNIT_CLOCK_GATE_DISABLE);
8491
8492         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8493
8494         /*
8495          * According to the spec the following bits should be set in
8496          * order to enable memory self-refresh
8497          * The bit 22/21 of 0x42004
8498          * The bit 5 of 0x42020
8499          * The bit 15 of 0x45000
8500          */
8501         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8502                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8503                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8504         I915_WRITE(ILK_DSPCLK_GATE,
8505                    (I915_READ(ILK_DSPCLK_GATE) |
8506                     ILK_DPARB_CLK_GATE));
8507         I915_WRITE(DISP_ARB_CTL,
8508                    (I915_READ(DISP_ARB_CTL) |
8509                     DISP_FBC_WM_DIS));
8510         I915_WRITE(WM3_LP_ILK, 0);
8511         I915_WRITE(WM2_LP_ILK, 0);
8512         I915_WRITE(WM1_LP_ILK, 0);
8513
8514         /*
8515          * Based on the document from hardware guys the following bits
8516          * should be set unconditionally in order to enable FBC.
8517          * The bit 22 of 0x42000
8518          * The bit 22 of 0x42004
8519          * The bit 7,8,9 of 0x42020.
8520          */
8521         if (IS_IRONLAKE_M(dev)) {
8522                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8523                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8524                            ILK_FBCQ_DIS);
8525                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8526                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8527                            ILK_DPARB_GATE);
8528                 I915_WRITE(ILK_DSPCLK_GATE,
8529                            I915_READ(ILK_DSPCLK_GATE) |
8530                            ILK_DPFC_DIS1 |
8531                            ILK_DPFC_DIS2 |
8532                            ILK_CLK_FBC);
8533         }
8534
8535         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8536                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8537                    ILK_ELPIN_409_SELECT);
8538         I915_WRITE(_3D_CHICKEN2,
8539                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8540                    _3D_CHICKEN2_WM_READ_PIPELINED);
8541 }
8542
8543 static void gen6_init_clock_gating(struct drm_device *dev)
8544 {
8545         struct drm_i915_private *dev_priv = dev->dev_private;
8546         int pipe;
8547         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8548
8549         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8550
8551         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8552                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8553                    ILK_ELPIN_409_SELECT);
8554
8555         I915_WRITE(WM3_LP_ILK, 0);
8556         I915_WRITE(WM2_LP_ILK, 0);
8557         I915_WRITE(WM1_LP_ILK, 0);
8558
8559         I915_WRITE(GEN6_UCGCTL1,
8560                    I915_READ(GEN6_UCGCTL1) |
8561                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE);
8562
8563         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8564          * gating disable must be set.  Failure to set it results in
8565          * flickering pixels due to Z write ordering failures after
8566          * some amount of runtime in the Mesa "fire" demo, and Unigine
8567          * Sanctuary and Tropics, and apparently anything else with
8568          * alpha test or pixel discard.
8569          *
8570          * According to the spec, bit 11 (RCCUNIT) must also be set,
8571          * but we didn't debug actual testcases to find it out.
8572          */
8573         I915_WRITE(GEN6_UCGCTL2,
8574                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8575                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8576
8577         /*
8578          * According to the spec the following bits should be
8579          * set in order to enable memory self-refresh and fbc:
8580          * The bit21 and bit22 of 0x42000
8581          * The bit21 and bit22 of 0x42004
8582          * The bit5 and bit7 of 0x42020
8583          * The bit14 of 0x70180
8584          * The bit14 of 0x71180
8585          */
8586         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8587                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8588                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8589         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8590                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8591                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8592         I915_WRITE(ILK_DSPCLK_GATE,
8593                    I915_READ(ILK_DSPCLK_GATE) |
8594                    ILK_DPARB_CLK_GATE  |
8595                    ILK_DPFD_CLK_GATE);
8596
8597         for_each_pipe(pipe) {
8598                 I915_WRITE(DSPCNTR(pipe),
8599                            I915_READ(DSPCNTR(pipe)) |
8600                            DISPPLANE_TRICKLE_FEED_DISABLE);
8601                 intel_flush_display_plane(dev_priv, pipe);
8602         }
8603 }
8604
8605 static void ivybridge_init_clock_gating(struct drm_device *dev)
8606 {
8607         struct drm_i915_private *dev_priv = dev->dev_private;
8608         int pipe;
8609         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8610
8611         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8612
8613         I915_WRITE(WM3_LP_ILK, 0);
8614         I915_WRITE(WM2_LP_ILK, 0);
8615         I915_WRITE(WM1_LP_ILK, 0);
8616
8617         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8618          * This implements the WaDisableRCZUnitClockGating workaround.
8619          */
8620         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8621
8622         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8623
8624         I915_WRITE(IVB_CHICKEN3,
8625                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8626                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8627
8628         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8629         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8630                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8631
8632         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8633         I915_WRITE(GEN7_L3CNTLREG1,
8634                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8635         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8636                         GEN7_WA_L3_CHICKEN_MODE);
8637
8638         /* This is required by WaCatErrorRejectionIssue */
8639         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8640                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8641                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8642
8643         for_each_pipe(pipe) {
8644                 I915_WRITE(DSPCNTR(pipe),
8645                            I915_READ(DSPCNTR(pipe)) |
8646                            DISPPLANE_TRICKLE_FEED_DISABLE);
8647                 intel_flush_display_plane(dev_priv, pipe);
8648         }
8649 }
8650
8651 static void g4x_init_clock_gating(struct drm_device *dev)
8652 {
8653         struct drm_i915_private *dev_priv = dev->dev_private;
8654         uint32_t dspclk_gate;
8655
8656         I915_WRITE(RENCLK_GATE_D1, 0);
8657         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8658                    GS_UNIT_CLOCK_GATE_DISABLE |
8659                    CL_UNIT_CLOCK_GATE_DISABLE);
8660         I915_WRITE(RAMCLK_GATE_D, 0);
8661         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8662                 OVRUNIT_CLOCK_GATE_DISABLE |
8663                 OVCUNIT_CLOCK_GATE_DISABLE;
8664         if (IS_GM45(dev))
8665                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8666         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8667 }
8668
8669 static void crestline_init_clock_gating(struct drm_device *dev)
8670 {
8671         struct drm_i915_private *dev_priv = dev->dev_private;
8672
8673         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8674         I915_WRITE(RENCLK_GATE_D2, 0);
8675         I915_WRITE(DSPCLK_GATE_D, 0);
8676         I915_WRITE(RAMCLK_GATE_D, 0);
8677         I915_WRITE16(DEUC, 0);
8678 }
8679
8680 static void broadwater_init_clock_gating(struct drm_device *dev)
8681 {
8682         struct drm_i915_private *dev_priv = dev->dev_private;
8683
8684         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8685                    I965_RCC_CLOCK_GATE_DISABLE |
8686                    I965_RCPB_CLOCK_GATE_DISABLE |
8687                    I965_ISC_CLOCK_GATE_DISABLE |
8688                    I965_FBC_CLOCK_GATE_DISABLE);
8689         I915_WRITE(RENCLK_GATE_D2, 0);
8690 }
8691
8692 static void gen3_init_clock_gating(struct drm_device *dev)
8693 {
8694         struct drm_i915_private *dev_priv = dev->dev_private;
8695         u32 dstate = I915_READ(D_STATE);
8696
8697         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8698                 DSTATE_DOT_CLOCK_GATING;
8699         I915_WRITE(D_STATE, dstate);
8700 }
8701
8702 static void i85x_init_clock_gating(struct drm_device *dev)
8703 {
8704         struct drm_i915_private *dev_priv = dev->dev_private;
8705
8706         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8707 }
8708
8709 static void i830_init_clock_gating(struct drm_device *dev)
8710 {
8711         struct drm_i915_private *dev_priv = dev->dev_private;
8712
8713         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8714 }
8715
8716 static void ibx_init_clock_gating(struct drm_device *dev)
8717 {
8718         struct drm_i915_private *dev_priv = dev->dev_private;
8719
8720         /*
8721          * On Ibex Peak and Cougar Point, we need to disable clock
8722          * gating for the panel power sequencer or it will fail to
8723          * start up when no ports are active.
8724          */
8725         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8726 }
8727
8728 static void cpt_init_clock_gating(struct drm_device *dev)
8729 {
8730         struct drm_i915_private *dev_priv = dev->dev_private;
8731         int pipe;
8732
8733         /*
8734          * On Ibex Peak and Cougar Point, we need to disable clock
8735          * gating for the panel power sequencer or it will fail to
8736          * start up when no ports are active.
8737          */
8738         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8739         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8740                    DPLS_EDP_PPS_FIX_DIS);
8741         /* Without this, mode sets may fail silently on FDI */
8742         for_each_pipe(pipe)
8743                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8744 }
8745
8746 static void ironlake_teardown_rc6(struct drm_device *dev)
8747 {
8748         struct drm_i915_private *dev_priv = dev->dev_private;
8749
8750         if (dev_priv->renderctx) {
8751                 i915_gem_object_unpin(dev_priv->renderctx);
8752                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8753                 dev_priv->renderctx = NULL;
8754         }
8755
8756         if (dev_priv->pwrctx) {
8757                 i915_gem_object_unpin(dev_priv->pwrctx);
8758                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8759                 dev_priv->pwrctx = NULL;
8760         }
8761 }
8762
8763 static void ironlake_disable_rc6(struct drm_device *dev)
8764 {
8765         struct drm_i915_private *dev_priv = dev->dev_private;
8766
8767         if (I915_READ(PWRCTXA)) {
8768                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8769                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8770                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8771                          50);
8772
8773                 I915_WRITE(PWRCTXA, 0);
8774                 POSTING_READ(PWRCTXA);
8775
8776                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8777                 POSTING_READ(RSTDBYCTL);
8778         }
8779
8780         ironlake_teardown_rc6(dev);
8781 }
8782
8783 static int ironlake_setup_rc6(struct drm_device *dev)
8784 {
8785         struct drm_i915_private *dev_priv = dev->dev_private;
8786
8787         if (dev_priv->renderctx == NULL)
8788                 dev_priv->renderctx = intel_alloc_context_page(dev);
8789         if (!dev_priv->renderctx)
8790                 return -ENOMEM;
8791
8792         if (dev_priv->pwrctx == NULL)
8793                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8794         if (!dev_priv->pwrctx) {
8795                 ironlake_teardown_rc6(dev);
8796                 return -ENOMEM;
8797         }
8798
8799         return 0;
8800 }
8801
8802 void ironlake_enable_rc6(struct drm_device *dev)
8803 {
8804         struct drm_i915_private *dev_priv = dev->dev_private;
8805         int ret;
8806
8807         /* rc6 disabled by default due to repeated reports of hanging during
8808          * boot and resume.
8809          */
8810         if (!intel_enable_rc6(dev))
8811                 return;
8812
8813         mutex_lock(&dev->struct_mutex);
8814         ret = ironlake_setup_rc6(dev);
8815         if (ret) {
8816                 mutex_unlock(&dev->struct_mutex);
8817                 return;
8818         }
8819
8820         /*
8821          * GPU can automatically power down the render unit if given a page
8822          * to save state.
8823          */
8824         ret = BEGIN_LP_RING(6);
8825         if (ret) {
8826                 ironlake_teardown_rc6(dev);
8827                 mutex_unlock(&dev->struct_mutex);
8828                 return;
8829         }
8830
8831         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8832         OUT_RING(MI_SET_CONTEXT);
8833         OUT_RING(dev_priv->renderctx->gtt_offset |
8834                  MI_MM_SPACE_GTT |
8835                  MI_SAVE_EXT_STATE_EN |
8836                  MI_RESTORE_EXT_STATE_EN |
8837                  MI_RESTORE_INHIBIT);
8838         OUT_RING(MI_SUSPEND_FLUSH);
8839         OUT_RING(MI_NOOP);
8840         OUT_RING(MI_FLUSH);
8841         ADVANCE_LP_RING();
8842
8843         /*
8844          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8845          * does an implicit flush, combined with MI_FLUSH above, it should be
8846          * safe to assume that renderctx is valid
8847          */
8848         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8849         if (ret) {
8850                 DRM_ERROR("failed to enable ironlake power power savings\n");
8851                 ironlake_teardown_rc6(dev);
8852                 mutex_unlock(&dev->struct_mutex);
8853                 return;
8854         }
8855
8856         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8857         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8858         mutex_unlock(&dev->struct_mutex);
8859 }
8860
8861 void intel_init_clock_gating(struct drm_device *dev)
8862 {
8863         struct drm_i915_private *dev_priv = dev->dev_private;
8864
8865         dev_priv->display.init_clock_gating(dev);
8866
8867         if (dev_priv->display.init_pch_clock_gating)
8868                 dev_priv->display.init_pch_clock_gating(dev);
8869 }
8870
8871 /* Set up chip specific display functions */
8872 static void intel_init_display(struct drm_device *dev)
8873 {
8874         struct drm_i915_private *dev_priv = dev->dev_private;
8875
8876         /* We always want a DPMS function */
8877         if (HAS_PCH_SPLIT(dev)) {
8878                 dev_priv->display.dpms = ironlake_crtc_dpms;
8879                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8880                 dev_priv->display.update_plane = ironlake_update_plane;
8881         } else {
8882                 dev_priv->display.dpms = i9xx_crtc_dpms;
8883                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8884                 dev_priv->display.update_plane = i9xx_update_plane;
8885         }
8886
8887         if (I915_HAS_FBC(dev)) {
8888                 if (HAS_PCH_SPLIT(dev)) {
8889                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8890                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8891                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8892                 } else if (IS_GM45(dev)) {
8893                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8894                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8895                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8896                 } else if (IS_CRESTLINE(dev)) {
8897                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8898                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8899                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8900                 }
8901                 /* 855GM needs testing */
8902         }
8903
8904         /* Returns the core display clock speed */
8905         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8906                 dev_priv->display.get_display_clock_speed =
8907                         i945_get_display_clock_speed;
8908         else if (IS_I915G(dev))
8909                 dev_priv->display.get_display_clock_speed =
8910                         i915_get_display_clock_speed;
8911         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8912                 dev_priv->display.get_display_clock_speed =
8913                         i9xx_misc_get_display_clock_speed;
8914         else if (IS_I915GM(dev))
8915                 dev_priv->display.get_display_clock_speed =
8916                         i915gm_get_display_clock_speed;
8917         else if (IS_I865G(dev))
8918                 dev_priv->display.get_display_clock_speed =
8919                         i865_get_display_clock_speed;
8920         else if (IS_I85X(dev))
8921                 dev_priv->display.get_display_clock_speed =
8922                         i855_get_display_clock_speed;
8923         else /* 852, 830 */
8924                 dev_priv->display.get_display_clock_speed =
8925                         i830_get_display_clock_speed;
8926
8927         /* For FIFO watermark updates */
8928         if (HAS_PCH_SPLIT(dev)) {
8929                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8930                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8931
8932                 /* IVB configs may use multi-threaded forcewake */
8933                 if (IS_IVYBRIDGE(dev)) {
8934                         u32     ecobus;
8935
8936                         /* A small trick here - if the bios hasn't configured MT forcewake,
8937                          * and if the device is in RC6, then force_wake_mt_get will not wake
8938                          * the device and the ECOBUS read will return zero. Which will be
8939                          * (correctly) interpreted by the test below as MT forcewake being
8940                          * disabled.
8941                          */
8942                         mutex_lock(&dev->struct_mutex);
8943                         __gen6_gt_force_wake_mt_get(dev_priv);
8944                         ecobus = I915_READ_NOTRACE(ECOBUS);
8945                         __gen6_gt_force_wake_mt_put(dev_priv);
8946                         mutex_unlock(&dev->struct_mutex);
8947
8948                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8949                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8950                                 dev_priv->display.force_wake_get =
8951                                         __gen6_gt_force_wake_mt_get;
8952                                 dev_priv->display.force_wake_put =
8953                                         __gen6_gt_force_wake_mt_put;
8954                         }
8955                 }
8956
8957                 if (HAS_PCH_IBX(dev))
8958                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8959                 else if (HAS_PCH_CPT(dev))
8960                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8961
8962                 if (IS_GEN5(dev)) {
8963                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8964                                 dev_priv->display.update_wm = ironlake_update_wm;
8965                         else {
8966                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8967                                               "Disable CxSR\n");
8968                                 dev_priv->display.update_wm = NULL;
8969                         }
8970                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8971                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8972                         dev_priv->display.write_eld = ironlake_write_eld;
8973                 } else if (IS_GEN6(dev)) {
8974                         if (SNB_READ_WM0_LATENCY()) {
8975                                 dev_priv->display.update_wm = sandybridge_update_wm;
8976                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8977                         } else {
8978                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8979                                               "Disable CxSR\n");
8980                                 dev_priv->display.update_wm = NULL;
8981                         }
8982                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8983                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8984                         dev_priv->display.write_eld = ironlake_write_eld;
8985                 } else if (IS_IVYBRIDGE(dev)) {
8986                         /* FIXME: detect B0+ stepping and use auto training */
8987                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8988                         if (SNB_READ_WM0_LATENCY()) {
8989                                 dev_priv->display.update_wm = sandybridge_update_wm;
8990                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8991                         } else {
8992                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8993                                               "Disable CxSR\n");
8994                                 dev_priv->display.update_wm = NULL;
8995                         }
8996                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8997                         dev_priv->display.write_eld = ironlake_write_eld;
8998                 } else
8999                         dev_priv->display.update_wm = NULL;
9000         } else if (IS_PINEVIEW(dev)) {
9001                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
9002                                             dev_priv->is_ddr3,
9003                                             dev_priv->fsb_freq,
9004                                             dev_priv->mem_freq)) {
9005                         DRM_INFO("failed to find known CxSR latency "
9006                                  "(found ddr%s fsb freq %d, mem freq %d), "
9007                                  "disabling CxSR\n",
9008                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9009                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9010                         /* Disable CxSR and never update its watermark again */
9011                         pineview_disable_cxsr(dev);
9012                         dev_priv->display.update_wm = NULL;
9013                 } else
9014                         dev_priv->display.update_wm = pineview_update_wm;
9015                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9016         } else if (IS_G4X(dev)) {
9017                 dev_priv->display.write_eld = g4x_write_eld;
9018                 dev_priv->display.update_wm = g4x_update_wm;
9019                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9020         } else if (IS_GEN4(dev)) {
9021                 dev_priv->display.update_wm = i965_update_wm;
9022                 if (IS_CRESTLINE(dev))
9023                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
9024                 else if (IS_BROADWATER(dev))
9025                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
9026         } else if (IS_GEN3(dev)) {
9027                 dev_priv->display.update_wm = i9xx_update_wm;
9028                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9029                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9030         } else if (IS_I865G(dev)) {
9031                 dev_priv->display.update_wm = i830_update_wm;
9032                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9033                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9034         } else if (IS_I85X(dev)) {
9035                 dev_priv->display.update_wm = i9xx_update_wm;
9036                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
9037                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9038         } else {
9039                 dev_priv->display.update_wm = i830_update_wm;
9040                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9041                 if (IS_845G(dev))
9042                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9043                 else
9044                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9045         }
9046
9047         /* Default just returns -ENODEV to indicate unsupported */
9048         dev_priv->display.queue_flip = intel_default_queue_flip;
9049
9050         switch (INTEL_INFO(dev)->gen) {
9051         case 2:
9052                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9053                 break;
9054
9055         case 3:
9056                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9057                 break;
9058
9059         case 4:
9060         case 5:
9061                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9062                 break;
9063
9064         case 6:
9065                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9066                 break;
9067         case 7:
9068                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9069                 break;
9070         }
9071 }
9072
9073 /*
9074  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9075  * resume, or other times.  This quirk makes sure that's the case for
9076  * affected systems.
9077  */
9078 static void quirk_pipea_force(struct drm_device *dev)
9079 {
9080         struct drm_i915_private *dev_priv = dev->dev_private;
9081
9082         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9083         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9084 }
9085
9086 /*
9087  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9088  */
9089 static void quirk_ssc_force_disable(struct drm_device *dev)
9090 {
9091         struct drm_i915_private *dev_priv = dev->dev_private;
9092         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9093 }
9094
9095 struct intel_quirk {
9096         int device;
9097         int subsystem_vendor;
9098         int subsystem_device;
9099         void (*hook)(struct drm_device *dev);
9100 };
9101
9102 struct intel_quirk intel_quirks[] = {
9103         /* HP Mini needs pipe A force quirk (LP: #322104) */
9104         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9105
9106         /* Thinkpad R31 needs pipe A force quirk */
9107         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9108         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9109         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9110
9111         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9112         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
9113         /* ThinkPad X40 needs pipe A force quirk */
9114
9115         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9116         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9117
9118         /* 855 & before need to leave pipe A & dpll A up */
9119         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9120         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9121
9122         /* Lenovo U160 cannot use SSC on LVDS */
9123         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9124
9125         /* Sony Vaio Y cannot use SSC on LVDS */
9126         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9127 };
9128
9129 static void intel_init_quirks(struct drm_device *dev)
9130 {
9131         struct pci_dev *d = dev->pdev;
9132         int i;
9133
9134         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9135                 struct intel_quirk *q = &intel_quirks[i];
9136
9137                 if (d->device == q->device &&
9138                     (d->subsystem_vendor == q->subsystem_vendor ||
9139                      q->subsystem_vendor == PCI_ANY_ID) &&
9140                     (d->subsystem_device == q->subsystem_device ||
9141                      q->subsystem_device == PCI_ANY_ID))
9142                         q->hook(dev);
9143         }
9144 }
9145
9146 /* Disable the VGA plane that we never use */
9147 static void i915_disable_vga(struct drm_device *dev)
9148 {
9149         struct drm_i915_private *dev_priv = dev->dev_private;
9150         u8 sr1;
9151         u32 vga_reg;
9152
9153         if (HAS_PCH_SPLIT(dev))
9154                 vga_reg = CPU_VGACNTRL;
9155         else
9156                 vga_reg = VGACNTRL;
9157
9158         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9159         outb(1, VGA_SR_INDEX);
9160         sr1 = inb(VGA_SR_DATA);
9161         outb(sr1 | 1<<5, VGA_SR_DATA);
9162         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9163         udelay(300);
9164
9165         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9166         POSTING_READ(vga_reg);
9167 }
9168
9169 void intel_modeset_init(struct drm_device *dev)
9170 {
9171         struct drm_i915_private *dev_priv = dev->dev_private;
9172         int i, ret;
9173
9174         drm_mode_config_init(dev);
9175
9176         dev->mode_config.min_width = 0;
9177         dev->mode_config.min_height = 0;
9178
9179         dev->mode_config.preferred_depth = 24;
9180         dev->mode_config.prefer_shadow = 1;
9181
9182         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9183
9184         intel_init_quirks(dev);
9185
9186         intel_init_display(dev);
9187
9188         if (IS_GEN2(dev)) {
9189                 dev->mode_config.max_width = 2048;
9190                 dev->mode_config.max_height = 2048;
9191         } else if (IS_GEN3(dev)) {
9192                 dev->mode_config.max_width = 4096;
9193                 dev->mode_config.max_height = 4096;
9194         } else {
9195                 dev->mode_config.max_width = 8192;
9196                 dev->mode_config.max_height = 8192;
9197         }
9198         dev->mode_config.fb_base = dev->agp->base;
9199
9200         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9201                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9202
9203         for (i = 0; i < dev_priv->num_pipe; i++) {
9204                 intel_crtc_init(dev, i);
9205                 ret = intel_plane_init(dev, i);
9206                 if (ret)
9207                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9208         }
9209
9210         /* Just disable it once at startup */
9211         i915_disable_vga(dev);
9212         intel_setup_outputs(dev);
9213
9214         intel_init_clock_gating(dev);
9215
9216         if (IS_IRONLAKE_M(dev)) {
9217                 ironlake_enable_drps(dev);
9218                 intel_init_emon(dev);
9219         }
9220
9221         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9222                 gen6_enable_rps(dev_priv);
9223                 gen6_update_ring_freq(dev_priv);
9224         }
9225
9226         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9227         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9228                     (unsigned long)dev);
9229 }
9230
9231 void intel_modeset_gem_init(struct drm_device *dev)
9232 {
9233         if (IS_IRONLAKE_M(dev))
9234                 ironlake_enable_rc6(dev);
9235
9236         intel_setup_overlay(dev);
9237 }
9238
9239 void intel_modeset_cleanup(struct drm_device *dev)
9240 {
9241         struct drm_i915_private *dev_priv = dev->dev_private;
9242         struct drm_crtc *crtc;
9243         struct intel_crtc *intel_crtc;
9244
9245         drm_kms_helper_poll_fini(dev);
9246         mutex_lock(&dev->struct_mutex);
9247
9248         intel_unregister_dsm_handler();
9249
9250
9251         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9252                 /* Skip inactive CRTCs */
9253                 if (!crtc->fb)
9254                         continue;
9255
9256                 intel_crtc = to_intel_crtc(crtc);
9257                 intel_increase_pllclock(crtc);
9258         }
9259
9260         intel_disable_fbc(dev);
9261
9262         if (IS_IRONLAKE_M(dev))
9263                 ironlake_disable_drps(dev);
9264         if (IS_GEN6(dev) || IS_GEN7(dev))
9265                 gen6_disable_rps(dev);
9266
9267         if (IS_IRONLAKE_M(dev))
9268                 ironlake_disable_rc6(dev);
9269
9270         mutex_unlock(&dev->struct_mutex);
9271
9272         /* Disable the irq before mode object teardown, for the irq might
9273          * enqueue unpin/hotplug work. */
9274         drm_irq_uninstall(dev);
9275         cancel_work_sync(&dev_priv->hotplug_work);
9276         cancel_work_sync(&dev_priv->rps_work);
9277
9278         /* flush any delayed tasks or pending work */
9279         flush_scheduled_work();
9280
9281         /* Shut off idle work before the crtcs get freed. */
9282         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9283                 intel_crtc = to_intel_crtc(crtc);
9284                 del_timer_sync(&intel_crtc->idle_timer);
9285         }
9286         del_timer_sync(&dev_priv->idle_timer);
9287         cancel_work_sync(&dev_priv->idle_work);
9288
9289         drm_mode_config_cleanup(dev);
9290 }
9291
9292 /*
9293  * Return which encoder is currently attached for connector.
9294  */
9295 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9296 {
9297         return &intel_attached_encoder(connector)->base;
9298 }
9299
9300 void intel_connector_attach_encoder(struct intel_connector *connector,
9301                                     struct intel_encoder *encoder)
9302 {
9303         connector->encoder = encoder;
9304         drm_mode_connector_attach_encoder(&connector->base,
9305                                           &encoder->base);
9306 }
9307
9308 /*
9309  * set vga decode state - true == enable VGA decode
9310  */
9311 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9312 {
9313         struct drm_i915_private *dev_priv = dev->dev_private;
9314         u16 gmch_ctrl;
9315
9316         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9317         if (state)
9318                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9319         else
9320                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9321         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9322         return 0;
9323 }
9324
9325 #ifdef CONFIG_DEBUG_FS
9326 #include <linux/seq_file.h>
9327
9328 struct intel_display_error_state {
9329         struct intel_cursor_error_state {
9330                 u32 control;
9331                 u32 position;
9332                 u32 base;
9333                 u32 size;
9334         } cursor[2];
9335
9336         struct intel_pipe_error_state {
9337                 u32 conf;
9338                 u32 source;
9339
9340                 u32 htotal;
9341                 u32 hblank;
9342                 u32 hsync;
9343                 u32 vtotal;
9344                 u32 vblank;
9345                 u32 vsync;
9346         } pipe[2];
9347
9348         struct intel_plane_error_state {
9349                 u32 control;
9350                 u32 stride;
9351                 u32 size;
9352                 u32 pos;
9353                 u32 addr;
9354                 u32 surface;
9355                 u32 tile_offset;
9356         } plane[2];
9357 };
9358
9359 struct intel_display_error_state *
9360 intel_display_capture_error_state(struct drm_device *dev)
9361 {
9362         drm_i915_private_t *dev_priv = dev->dev_private;
9363         struct intel_display_error_state *error;
9364         int i;
9365
9366         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9367         if (error == NULL)
9368                 return NULL;
9369
9370         for (i = 0; i < 2; i++) {
9371                 error->cursor[i].control = I915_READ(CURCNTR(i));
9372                 error->cursor[i].position = I915_READ(CURPOS(i));
9373                 error->cursor[i].base = I915_READ(CURBASE(i));
9374
9375                 error->plane[i].control = I915_READ(DSPCNTR(i));
9376                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9377                 error->plane[i].size = I915_READ(DSPSIZE(i));
9378                 error->plane[i].pos = I915_READ(DSPPOS(i));
9379                 error->plane[i].addr = I915_READ(DSPADDR(i));
9380                 if (INTEL_INFO(dev)->gen >= 4) {
9381                         error->plane[i].surface = I915_READ(DSPSURF(i));
9382                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9383                 }
9384
9385                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9386                 error->pipe[i].source = I915_READ(PIPESRC(i));
9387                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9388                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9389                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9390                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9391                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9392                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9393         }
9394
9395         return error;
9396 }
9397
9398 void
9399 intel_display_print_error_state(struct seq_file *m,
9400                                 struct drm_device *dev,
9401                                 struct intel_display_error_state *error)
9402 {
9403         int i;
9404
9405         for (i = 0; i < 2; i++) {
9406                 seq_printf(m, "Pipe [%d]:\n", i);
9407                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9408                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9409                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9410                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9411                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9412                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9413                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9414                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9415
9416                 seq_printf(m, "Plane [%d]:\n", i);
9417                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9418                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9419                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9420                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9421                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9422                 if (INTEL_INFO(dev)->gen >= 4) {
9423                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9424                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9425                 }
9426
9427                 seq_printf(m, "Cursor [%d]:\n", i);
9428                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9429                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9430                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9431         }
9432 }
9433 #endif