drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static inline u32 /* units of 100MHz */
 102 intel_fdi_link_freq(struct drm_device *dev)
 103 {
 104         if (IS_GEN5(dev)) {
 105                 struct drm_i915_private *dev_priv = dev->dev_private;
 106                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 107         } else
 108                 return 27;
 109 }
 110
 111 static const intel_limit_t intel_limits_i8xx_dvo = {
 112         .dot = { .min = 25000, .max = 350000 },
 113         .vco = { .min = 930000, .max = 1400000 },
 114         .n = { .min = 3, .max = 16 },
 115         .m = { .min = 96, .max = 140 },
 116         .m1 = { .min = 18, .max = 26 },
 117         .m2 = { .min = 6, .max = 16 },
 118         .p = { .min = 4, .max = 128 },
 119         .p1 = { .min = 2, .max = 33 },
 120         .p2 = { .dot_limit = 165000,
 121                 .p2_slow = 4, .p2_fast = 2 },
 122         .find_pll = intel_find_best_PLL,
 123 };
 124
 125 static const intel_limit_t intel_limits_i8xx_lvds = {
 126         .dot = { .min = 25000, .max = 350000 },
 127         .vco = { .min = 930000, .max = 1400000 },
 128         .n = { .min = 3, .max = 16 },
 129         .m = { .min = 96, .max = 140 },
 130         .m1 = { .min = 18, .max = 26 },
 131         .m2 = { .min = 6, .max = 16 },
 132         .p = { .min = 4, .max = 128 },
 133         .p1 = { .min = 1, .max = 6 },
 134         .p2 = { .dot_limit = 165000,
 135                 .p2_slow = 14, .p2_fast = 7 },
 136         .find_pll = intel_find_best_PLL,
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 10, .max = 22 },
 145         .m2 = { .min = 5, .max = 9 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150         .find_pll = intel_find_best_PLL,
 151 };
 152
 153 static const intel_limit_t intel_limits_i9xx_lvds = {
 154         .dot = { .min = 20000, .max = 400000 },
 155         .vco = { .min = 1400000, .max = 2800000 },
 156         .n = { .min = 1, .max = 6 },
 157         .m = { .min = 70, .max = 120 },
 158         .m1 = { .min = 10, .max = 22 },
 159         .m2 = { .min = 5, .max = 9 },
 160         .p = { .min = 7, .max = 98 },
 161         .p1 = { .min = 1, .max = 8 },
 162         .p2 = { .dot_limit = 112000,
 163                 .p2_slow = 14, .p2_fast = 7 },
 164         .find_pll = intel_find_best_PLL,
 165 };
 166
 167
 168 static const intel_limit_t intel_limits_g4x_sdvo = {
 169         .dot = { .min = 25000, .max = 270000 },
 170         .vco = { .min = 1750000, .max = 3500000},
 171         .n = { .min = 1, .max = 4 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 10, .max = 30 },
 176         .p1 = { .min = 1, .max = 3},
 177         .p2 = { .dot_limit = 270000,
 178                 .p2_slow = 10,
 179                 .p2_fast = 10
 180         },
 181         .find_pll = intel_g4x_find_best_PLL,
 182 };
 183
 184 static const intel_limit_t intel_limits_g4x_hdmi = {
 185         .dot = { .min = 22000, .max = 400000 },
 186         .vco = { .min = 1750000, .max = 3500000},
 187         .n = { .min = 1, .max = 4 },
 188         .m = { .min = 104, .max = 138 },
 189         .m1 = { .min = 16, .max = 23 },
 190         .m2 = { .min = 5, .max = 11 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8},
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195         .find_pll = intel_g4x_find_best_PLL,
 196 };
 197
 198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 199         .dot = { .min = 20000, .max = 115000 },
 200         .vco = { .min = 1750000, .max = 3500000 },
 201         .n = { .min = 1, .max = 3 },
 202         .m = { .min = 104, .max = 138 },
 203         .m1 = { .min = 17, .max = 23 },
 204         .m2 = { .min = 5, .max = 11 },
 205         .p = { .min = 28, .max = 112 },
 206         .p1 = { .min = 2, .max = 8 },
 207         .p2 = { .dot_limit = 0,
 208                 .p2_slow = 14, .p2_fast = 14
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 214         .dot = { .min = 80000, .max = 224000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 14, .max = 42 },
 221         .p1 = { .min = 2, .max = 6 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 7, .p2_fast = 7
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_display_port = {
 229         .dot = { .min = 161670, .max = 227000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 2 },
 232         .m = { .min = 97, .max = 108 },
 233         .m1 = { .min = 0x10, .max = 0x12 },
 234         .m2 = { .min = 0x05, .max = 0x06 },
 235         .p = { .min = 10, .max = 20 },
 236         .p1 = { .min = 1, .max = 2},
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 10, .p2_fast = 10 },
 239         .find_pll = intel_find_pll_g4x_dp,
 240 };
 241
 242 static const intel_limit_t intel_limits_pineview_sdvo = {
 243         .dot = { .min = 20000, .max = 400000},
 244         .vco = { .min = 1700000, .max = 3500000 },
 245         /* Pineview's Ncounter is a ring counter */
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         /* Pineview only has one combined m divider, which we treat as m2. */
 249         .m1 = { .min = 0, .max = 0 },
 250         .m2 = { .min = 0, .max = 254 },
 251         .p = { .min = 5, .max = 80 },
 252         .p1 = { .min = 1, .max = 8 },
 253         .p2 = { .dot_limit = 200000,
 254                 .p2_slow = 10, .p2_fast = 5 },
 255         .find_pll = intel_find_best_PLL,
 256 };
 257
 258 static const intel_limit_t intel_limits_pineview_lvds = {
 259         .dot = { .min = 20000, .max = 400000 },
 260         .vco = { .min = 1700000, .max = 3500000 },
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         .m1 = { .min = 0, .max = 0 },
 264         .m2 = { .min = 0, .max = 254 },
 265         .p = { .min = 7, .max = 112 },
 266         .p1 = { .min = 1, .max = 8 },
 267         .p2 = { .dot_limit = 112000,
 268                 .p2_slow = 14, .p2_fast = 14 },
 269         .find_pll = intel_find_best_PLL,
 270 };
 271
 272 /* Ironlake / Sandybridge
 273  *
 274  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 275  * the range value for them is (actual_value - 2).
 276  */
 277 static const intel_limit_t intel_limits_ironlake_dac = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 5 },
 281         .m = { .min = 79, .max = 127 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288         .find_pll = intel_g4x_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 292         .dot = { .min = 25000, .max = 350000 },
 293         .vco = { .min = 1760000, .max = 3510000 },
 294         .n = { .min = 1, .max = 3 },
 295         .m = { .min = 79, .max = 118 },
 296         .m1 = { .min = 12, .max = 22 },
 297         .m2 = { .min = 5, .max = 9 },
 298         .p = { .min = 28, .max = 112 },
 299         .p1 = { .min = 2, .max = 8 },
 300         .p2 = { .dot_limit = 225000,
 301                 .p2_slow = 14, .p2_fast = 14 },
 302         .find_pll = intel_g4x_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 56 },
 313         .p1 = { .min = 2, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316         .find_pll = intel_g4x_find_best_PLL,
 317 };
 318
 319 /* LVDS 100mhz refclk limits. */
 320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 2 },
 324         .m = { .min = 79, .max = 126 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_ironlake_display_port = {
 349         .dot = { .min = 25000, .max = 350000 },
 350         .vco = { .min = 1760000, .max = 3510000},
 351         .n = { .min = 1, .max = 2 },
 352         .m = { .min = 81, .max = 90 },
 353         .m1 = { .min = 12, .max = 22 },
 354         .m2 = { .min = 5, .max = 9 },
 355         .p = { .min = 10, .max = 20 },
 356         .p1 = { .min = 1, .max = 2},
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 10, .p2_fast = 10 },
 359         .find_pll = intel_find_pll_ironlake_dp,
 360 };
 361
 362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 363 {
 364         unsigned long flags;
 365         u32 val = 0;
 366
 367         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 368         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 369                 DRM_ERROR("DPIO idle wait timed out\n");
 370                 goto out_unlock;
 371         }
 372
 373         I915_WRITE(DPIO_REG, reg);
 374         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 375                    DPIO_BYTE);
 376         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 377                 DRM_ERROR("DPIO read wait timed out\n");
 378                 goto out_unlock;
 379         }
 380         val = I915_READ(DPIO_DATA);
 381
 382 out_unlock:
 383         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 384         return val;
 385 }
 386
 387 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 388                              u32 val)
 389 {
 390         unsigned long flags;
 391
 392         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 393         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 394                 DRM_ERROR("DPIO idle wait timed out\n");
 395                 goto out_unlock;
 396         }
 397
 398         I915_WRITE(DPIO_DATA, val);
 399         I915_WRITE(DPIO_REG, reg);
 400         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 401                    DPIO_BYTE);
 402         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 403                 DRM_ERROR("DPIO write wait timed out\n");
 404
 405 out_unlock:
 406         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 407 }
 408
 409 static void vlv_init_dpio(struct drm_device *dev)
 410 {
 411         struct drm_i915_private *dev_priv = dev->dev_private;
 412
 413         /* Reset the DPIO config */
 414         I915_WRITE(DPIO_CTL, 0);
 415         POSTING_READ(DPIO_CTL);
 416         I915_WRITE(DPIO_CTL, 1);
 417         POSTING_READ(DPIO_CTL);
 418 }
 419
 420 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 421 {
 422         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 423         return 1;
 424 }
 425
 426 static const struct dmi_system_id intel_dual_link_lvds[] = {
 427         {
 428                 .callback = intel_dual_link_lvds_callback,
 429                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 430                 .matches = {
 431                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 432                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 433                 },
 434         },
 435         { }     /* terminating entry */
 436 };
 437
 438 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 439                               unsigned int reg)
 440 {
 441         unsigned int val;
 442
 443         /* use the module option value if specified */
 444         if (i915_lvds_channel_mode > 0)
 445                 return i915_lvds_channel_mode == 2;
 446
 447         if (dmi_check_system(intel_dual_link_lvds))
 448                 return true;
 449
 450         if (dev_priv->lvds_val)
 451                 val = dev_priv->lvds_val;
 452         else {
 453                 /* BIOS should set the proper LVDS register value at boot, but
 454                  * in reality, it doesn't set the value when the lid is closed;
 455                  * we need to check "the value to be set" in VBT when LVDS
 456                  * register is uninitialized.
 457                  */
 458                 val = I915_READ(reg);
 459                 if (!(val & ~LVDS_DETECTED))
 460                         val = dev_priv->bios_lvds_val;
 461                 dev_priv->lvds_val = val;
 462         }
 463         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 464 }
 465
 466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 467                                                 int refclk)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_i915_private *dev_priv = dev->dev_private;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 475                         /* LVDS dual channel */
 476                         if (refclk == 100000)
 477                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 478                         else
 479                                 limit = &intel_limits_ironlake_dual_lvds;
 480                 } else {
 481                         if (refclk == 100000)
 482                                 limit = &intel_limits_ironlake_single_lvds_100m;
 483                         else
 484                                 limit = &intel_limits_ironlake_single_lvds;
 485                 }
 486         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 487                         HAS_eDP)
 488                 limit = &intel_limits_ironlake_display_port;
 489         else
 490                 limit = &intel_limits_ironlake_dac;
 491
 492         return limit;
 493 }
 494
 495 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 496 {
 497         struct drm_device *dev = crtc->dev;
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         const intel_limit_t *limit;
 500
 501         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 502                 if (is_dual_link_lvds(dev_priv, LVDS))
 503                         /* LVDS with dual channel */
 504                         limit = &intel_limits_g4x_dual_channel_lvds;
 505                 else
 506                         /* LVDS with dual channel */
 507                         limit = &intel_limits_g4x_single_channel_lvds;
 508         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 509                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 510                 limit = &intel_limits_g4x_hdmi;
 511         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 512                 limit = &intel_limits_g4x_sdvo;
 513         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 514                 limit = &intel_limits_g4x_display_port;
 515         } else /* The option is for other outputs */
 516                 limit = &intel_limits_i9xx_sdvo;
 517
 518         return limit;
 519 }
 520
 521 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 522 {
 523         struct drm_device *dev = crtc->dev;
 524         const intel_limit_t *limit;
 525
 526         if (HAS_PCH_SPLIT(dev))
 527                 limit = intel_ironlake_limit(crtc, refclk);
 528         else if (IS_G4X(dev)) {
 529                 limit = intel_g4x_limit(crtc);
 530         } else if (IS_PINEVIEW(dev)) {
 531                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 532                         limit = &intel_limits_pineview_lvds;
 533                 else
 534                         limit = &intel_limits_pineview_sdvo;
 535         } else if (!IS_GEN2(dev)) {
 536                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 537                         limit = &intel_limits_i9xx_lvds;
 538                 else
 539                         limit = &intel_limits_i9xx_sdvo;
 540         } else {
 541                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i8xx_lvds;
 543                 else
 544                         limit = &intel_limits_i8xx_dvo;
 545         }
 546         return limit;
 547 }
 548
 549 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 550 static void pineview_clock(int refclk, intel_clock_t *clock)
 551 {
 552         clock->m = clock->m2 + 2;
 553         clock->p = clock->p1 * clock->p2;
 554         clock->vco = refclk * clock->m / clock->n;
 555         clock->dot = clock->vco / clock->p;
 556 }
 557
 558 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 559 {
 560         if (IS_PINEVIEW(dev)) {
 561                 pineview_clock(refclk, clock);
 562                 return;
 563         }
 564         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 565         clock->p = clock->p1 * clock->p2;
 566         clock->vco = refclk * clock->m / (clock->n + 2);
 567         clock->dot = clock->vco / clock->p;
 568 }
 569
 570 /**
 571  * Returns whether any output on the specified pipe is of the specified type
 572  */
 573 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 574 {
 575         struct drm_device *dev = crtc->dev;
 576         struct drm_mode_config *mode_config = &dev->mode_config;
 577         struct intel_encoder *encoder;
 578
 579         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 580                 if (encoder->base.crtc == crtc && encoder->type == type)
 581                         return true;
 582
 583         return false;
 584 }
 585
 586 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 587 /**
 588  * Returns whether the given set of divisors are valid for a given refclk with
 589  * the given connectors.
 590  */
 591
 592 static bool intel_PLL_is_valid(struct drm_device *dev,
 593                                const intel_limit_t *limit,
 594                                const intel_clock_t *clock)
 595 {
 596         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 597                 INTELPllInvalid("p1 out of range\n");
 598         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 599                 INTELPllInvalid("p out of range\n");
 600         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 601                 INTELPllInvalid("m2 out of range\n");
 602         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 603                 INTELPllInvalid("m1 out of range\n");
 604         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 605                 INTELPllInvalid("m1 <= m2\n");
 606         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 607                 INTELPllInvalid("m out of range\n");
 608         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 609                 INTELPllInvalid("n out of range\n");
 610         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 611                 INTELPllInvalid("vco out of range\n");
 612         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 613          * connector, etc., rather than just a single range.
 614          */
 615         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 616                 INTELPllInvalid("dot out of range\n");
 617
 618         return true;
 619 }
 620
 621 static bool
 622 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 623                     int target, int refclk, intel_clock_t *match_clock,
 624                     intel_clock_t *best_clock)
 625
 626 {
 627         struct drm_device *dev = crtc->dev;
 628         struct drm_i915_private *dev_priv = dev->dev_private;
 629         intel_clock_t clock;
 630         int err = target;
 631
 632         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 633             (I915_READ(LVDS)) != 0) {
 634                 /*
 635                  * For LVDS, if the panel is on, just rely on its current
 636                  * settings for dual-channel.  We haven't figured out how to
 637                  * reliably set up different single/dual channel state, if we
 638                  * even can.
 639                  */
 640                 if (is_dual_link_lvds(dev_priv, LVDS))
 641                         clock.p2 = limit->p2.p2_fast;
 642                 else
 643                         clock.p2 = limit->p2.p2_slow;
 644         } else {
 645                 if (target < limit->p2.dot_limit)
 646                         clock.p2 = limit->p2.p2_slow;
 647                 else
 648                         clock.p2 = limit->p2.p2_fast;
 649         }
 650
 651         memset(best_clock, 0, sizeof(*best_clock));
 652
 653         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 654              clock.m1++) {
 655                 for (clock.m2 = limit->m2.min;
 656                      clock.m2 <= limit->m2.max; clock.m2++) {
 657                         /* m1 is always 0 in Pineview */
 658                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 659                                 break;
 660                         for (clock.n = limit->n.min;
 661                              clock.n <= limit->n.max; clock.n++) {
 662                                 for (clock.p1 = limit->p1.min;
 663                                         clock.p1 <= limit->p1.max; clock.p1++) {
 664                                         int this_err;
 665
 666                                         intel_clock(dev, refclk, &clock);
 667                                         if (!intel_PLL_is_valid(dev, limit,
 668                                                                 &clock))
 669                                                 continue;
 670                                         if (match_clock &&
 671                                             clock.p != match_clock->p)
 672                                                 continue;
 673
 674                                         this_err = abs(clock.dot - target);
 675                                         if (this_err < err) {
 676                                                 *best_clock = clock;
 677                                                 err = this_err;
 678                                         }
 679                                 }
 680                         }
 681                 }
 682         }
 683
 684         return (err != target);
 685 }
 686
 687 static bool
 688 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 689                         int target, int refclk, intel_clock_t *match_clock,
 690                         intel_clock_t *best_clock)
 691 {
 692         struct drm_device *dev = crtc->dev;
 693         struct drm_i915_private *dev_priv = dev->dev_private;
 694         intel_clock_t clock;
 695         int max_n;
 696         bool found;
 697         /* approximately equals target * 0.00585 */
 698         int err_most = (target >> 8) + (target >> 9);
 699         found = false;
 700
 701         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 702                 int lvds_reg;
 703
 704                 if (HAS_PCH_SPLIT(dev))
 705                         lvds_reg = PCH_LVDS;
 706                 else
 707                         lvds_reg = LVDS;
 708                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 709                     LVDS_CLKB_POWER_UP)
 710                         clock.p2 = limit->p2.p2_fast;
 711                 else
 712                         clock.p2 = limit->p2.p2_slow;
 713         } else {
 714                 if (target < limit->p2.dot_limit)
 715                         clock.p2 = limit->p2.p2_slow;
 716                 else
 717                         clock.p2 = limit->p2.p2_fast;
 718         }
 719
 720         memset(best_clock, 0, sizeof(*best_clock));
 721         max_n = limit->n.max;
 722         /* based on hardware requirement, prefer smaller n to precision */
 723         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 724                 /* based on hardware requirement, prefere larger m1,m2 */
 725                 for (clock.m1 = limit->m1.max;
 726                      clock.m1 >= limit->m1.min; clock.m1--) {
 727                         for (clock.m2 = limit->m2.max;
 728                              clock.m2 >= limit->m2.min; clock.m2--) {
 729                                 for (clock.p1 = limit->p1.max;
 730                                      clock.p1 >= limit->p1.min; clock.p1--) {
 731                                         int this_err;
 732
 733                                         intel_clock(dev, refclk, &clock);
 734                                         if (!intel_PLL_is_valid(dev, limit,
 735                                                                 &clock))
 736                                                 continue;
 737                                         if (match_clock &&
 738                                             clock.p != match_clock->p)
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err_most) {
 743                                                 *best_clock = clock;
 744                                                 err_most = this_err;
 745                                                 max_n = clock.n;
 746                                                 found = true;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752         return found;
 753 }
 754
 755 static bool
 756 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 757                            int target, int refclk, intel_clock_t *match_clock,
 758                            intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->dev;
 761         intel_clock_t clock;
 762
 763         if (target < 200000) {
 764                 clock.n = 1;
 765                 clock.p1 = 2;
 766                 clock.p2 = 10;
 767                 clock.m1 = 12;
 768                 clock.m2 = 9;
 769         } else {
 770                 clock.n = 2;
 771                 clock.p1 = 1;
 772                 clock.p2 = 10;
 773                 clock.m1 = 14;
 774                 clock.m2 = 8;
 775         }
 776         intel_clock(dev, refclk, &clock);
 777         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 778         return true;
 779 }
 780
 781 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 782 static bool
 783 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 784                       int target, int refclk, intel_clock_t *match_clock,
 785                       intel_clock_t *best_clock)
 786 {
 787         intel_clock_t clock;
 788         if (target < 200000) {
 789                 clock.p1 = 2;
 790                 clock.p2 = 10;
 791                 clock.n = 2;
 792                 clock.m1 = 23;
 793                 clock.m2 = 8;
 794         } else {
 795                 clock.p1 = 1;
 796                 clock.p2 = 10;
 797                 clock.n = 1;
 798                 clock.m1 = 14;
 799                 clock.m2 = 2;
 800         }
 801         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 802         clock.p = (clock.p1 * clock.p2);
 803         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 804         clock.vco = 0;
 805         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 806         return true;
 807 }
 808
 809 /**
 810  * intel_wait_for_vblank - wait for vblank on a given pipe
 811  * @dev: drm device
 812  * @pipe: pipe to wait for
 813  *
 814  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 815  * mode setting code.
 816  */
 817 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         int pipestat_reg = PIPESTAT(pipe);
 821
 822         /* Clear existing vblank status. Note this will clear any other
 823          * sticky status fields as well.
 824          *
 825          * This races with i915_driver_irq_handler() with the result
 826          * that either function could miss a vblank event.  Here it is not
 827          * fatal, as we will either wait upon the next vblank interrupt or
 828          * timeout.  Generally speaking intel_wait_for_vblank() is only
 829          * called during modeset at which time the GPU should be idle and
 830          * should *not* be performing page flips and thus not waiting on
 831          * vblanks...
 832          * Currently, the result of us stealing a vblank from the irq
 833          * handler is that a single frame will be skipped during swapbuffers.
 834          */
 835         I915_WRITE(pipestat_reg,
 836                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 837
 838         /* Wait for vblank interrupt bit to set */
 839         if (wait_for(I915_READ(pipestat_reg) &
 840                      PIPE_VBLANK_INTERRUPT_STATUS,
 841                      50))
 842                 DRM_DEBUG_KMS("vblank wait timed out\n");
 843 }
 844
 845 /*
 846  * intel_wait_for_pipe_off - wait for pipe to turn off
 847  * @dev: drm device
 848  * @pipe: pipe to wait for
 849  *
 850  * After disabling a pipe, we can't wait for vblank in the usual way,
 851  * spinning on the vblank interrupt status bit, since we won't actually
 852  * see an interrupt when the pipe is disabled.
 853  *
 854  * On Gen4 and above:
 855  *   wait for the pipe register state bit to turn off
 856  *
 857  * Otherwise:
 858  *   wait for the display line value to settle (it usually
 859  *   ends up stopping at the start of the next frame).
 860  *
 861  */
 862 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 863 {
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865
 866         if (INTEL_INFO(dev)->gen >= 4) {
 867                 int reg = PIPECONF(pipe);
 868
 869                 /* Wait for the Pipe State to go off */
 870                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 871                              100))
 872                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 873         } else {
 874                 u32 last_line;
 875                 int reg = PIPEDSL(pipe);
 876                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 877
 878                 /* Wait for the display line to settle */
 879                 do {
 880                         last_line = I915_READ(reg) & DSL_LINEMASK;
 881                         mdelay(5);
 882                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 883                          time_after(timeout, jiffies));
 884                 if (time_after(jiffies, timeout))
 885                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 886         }
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 /* For ILK+ */
 913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 914                            struct intel_crtc *intel_crtc, bool state)
 915 {
 916         int reg;
 917         u32 val;
 918         bool cur_state;
 919
 920         if (!intel_crtc->pch_pll) {
 921                 WARN(1, "asserting PCH PLL enabled with no PLL\n");
 922                 return;
 923         }
 924
 925         if (HAS_PCH_CPT(dev_priv->dev)) {
 926                 u32 pch_dpll;
 927
 928                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 929
 930                 /* Make sure the selected PLL is enabled to the transcoder */
 931                 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
 932                      "transcoder %d PLL not enabled\n", intel_crtc->pipe);
 933         }
 934
 935         reg = intel_crtc->pch_pll->pll_reg;
 936         val = I915_READ(reg);
 937         cur_state = !!(val & DPLL_VCO_ENABLE);
 938         WARN(cur_state != state,
 939              "PCH PLL state assertion failure (expected %s, current %s)\n",
 940              state_string(state), state_string(cur_state));
 941 }
 942 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 943 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 944
 945 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 946                           enum pipe pipe, bool state)
 947 {
 948         int reg;
 949         u32 val;
 950         bool cur_state;
 951
 952         reg = FDI_TX_CTL(pipe);
 953         val = I915_READ(reg);
 954         cur_state = !!(val & FDI_TX_ENABLE);
 955         WARN(cur_state != state,
 956              "FDI TX state assertion failure (expected %s, current %s)\n",
 957              state_string(state), state_string(cur_state));
 958 }
 959 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 960 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 961
 962 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 963                           enum pipe pipe, bool state)
 964 {
 965         int reg;
 966         u32 val;
 967         bool cur_state;
 968
 969         reg = FDI_RX_CTL(pipe);
 970         val = I915_READ(reg);
 971         cur_state = !!(val & FDI_RX_ENABLE);
 972         WARN(cur_state != state,
 973              "FDI RX state assertion failure (expected %s, current %s)\n",
 974              state_string(state), state_string(cur_state));
 975 }
 976 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 977 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 978
 979 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 980                                       enum pipe pipe)
 981 {
 982         int reg;
 983         u32 val;
 984
 985         /* ILK FDI PLL is always enabled */
 986         if (dev_priv->info->gen == 5)
 987                 return;
 988
 989         reg = FDI_TX_CTL(pipe);
 990         val = I915_READ(reg);
 991         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 992 }
 993
 994 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 995                                       enum pipe pipe)
 996 {
 997         int reg;
 998         u32 val;
 999
1000         reg = FDI_RX_CTL(pipe);
1001         val = I915_READ(reg);
1002         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1003 }
1004
1005 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1006                                   enum pipe pipe)
1007 {
1008         int pp_reg, lvds_reg;
1009         u32 val;
1010         enum pipe panel_pipe = PIPE_A;
1011         bool locked = true;
1012
1013         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1014                 pp_reg = PCH_PP_CONTROL;
1015                 lvds_reg = PCH_LVDS;
1016         } else {
1017                 pp_reg = PP_CONTROL;
1018                 lvds_reg = LVDS;
1019         }
1020
1021         val = I915_READ(pp_reg);
1022         if (!(val & PANEL_POWER_ON) ||
1023             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1024                 locked = false;
1025
1026         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1027                 panel_pipe = PIPE_B;
1028
1029         WARN(panel_pipe == pipe && locked,
1030              "panel assertion failure, pipe %c regs locked\n",
1031              pipe_name(pipe));
1032 }
1033
1034 void assert_pipe(struct drm_i915_private *dev_priv,
1035                  enum pipe pipe, bool state)
1036 {
1037         int reg;
1038         u32 val;
1039         bool cur_state;
1040
1041         /* if we need the pipe A quirk it must be always on */
1042         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1043                 state = true;
1044
1045         reg = PIPECONF(pipe);
1046         val = I915_READ(reg);
1047         cur_state = !!(val & PIPECONF_ENABLE);
1048         WARN(cur_state != state,
1049              "pipe %c assertion failure (expected %s, current %s)\n",
1050              pipe_name(pipe), state_string(state), state_string(cur_state));
1051 }
1052
1053 static void assert_plane(struct drm_i915_private *dev_priv,
1054                          enum plane plane, bool state)
1055 {
1056         int reg;
1057         u32 val;
1058         bool cur_state;
1059
1060         reg = DSPCNTR(plane);
1061         val = I915_READ(reg);
1062         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1063         WARN(cur_state != state,
1064              "plane %c assertion failure (expected %s, current %s)\n",
1065              plane_name(plane), state_string(state), state_string(cur_state));
1066 }
1067
1068 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1069 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1070
1071 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1072                                    enum pipe pipe)
1073 {
1074         int reg, i;
1075         u32 val;
1076         int cur_pipe;
1077
1078         /* Planes are fixed to pipes on ILK+ */
1079         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080                 reg = DSPCNTR(pipe);
1081                 val = I915_READ(reg);
1082                 WARN((val & DISPLAY_PLANE_ENABLE),
1083                      "plane %c assertion failure, should be disabled but not\n",
1084                      plane_name(pipe));
1085                 return;
1086         }
1087
1088         /* Need to check both planes against the pipe */
1089         for (i = 0; i < 2; i++) {
1090                 reg = DSPCNTR(i);
1091                 val = I915_READ(reg);
1092                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1093                         DISPPLANE_SEL_PIPE_SHIFT;
1094                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1095                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1096                      plane_name(i), pipe_name(pipe));
1097         }
1098 }
1099
1100 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1101 {
1102         u32 val;
1103         bool enabled;
1104
1105         val = I915_READ(PCH_DREF_CONTROL);
1106         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1107                             DREF_SUPERSPREAD_SOURCE_MASK));
1108         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1109 }
1110
1111 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1112                                        enum pipe pipe)
1113 {
1114         int reg;
1115         u32 val;
1116         bool enabled;
1117
1118         reg = TRANSCONF(pipe);
1119         val = I915_READ(reg);
1120         enabled = !!(val & TRANS_ENABLE);
1121         WARN(enabled,
1122              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1123              pipe_name(pipe));
1124 }
1125
1126 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1127                             enum pipe pipe, u32 port_sel, u32 val)
1128 {
1129         if ((val & DP_PORT_EN) == 0)
1130                 return false;
1131
1132         if (HAS_PCH_CPT(dev_priv->dev)) {
1133                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1134                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1135                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1136                         return false;
1137         } else {
1138                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1139                         return false;
1140         }
1141         return true;
1142 }
1143
1144 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1145                               enum pipe pipe, u32 val)
1146 {
1147         if ((val & PORT_ENABLE) == 0)
1148                 return false;
1149
1150         if (HAS_PCH_CPT(dev_priv->dev)) {
1151                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1152                         return false;
1153         } else {
1154                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1155                         return false;
1156         }
1157         return true;
1158 }
1159
1160 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1161                               enum pipe pipe, u32 val)
1162 {
1163         if ((val & LVDS_PORT_EN) == 0)
1164                 return false;
1165
1166         if (HAS_PCH_CPT(dev_priv->dev)) {
1167                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1168                         return false;
1169         } else {
1170                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1171                         return false;
1172         }
1173         return true;
1174 }
1175
1176 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1177                               enum pipe pipe, u32 val)
1178 {
1179         if ((val & ADPA_DAC_ENABLE) == 0)
1180                 return false;
1181         if (HAS_PCH_CPT(dev_priv->dev)) {
1182                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1183                         return false;
1184         } else {
1185                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1186                         return false;
1187         }
1188         return true;
1189 }
1190
1191 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1192                                    enum pipe pipe, int reg, u32 port_sel)
1193 {
1194         u32 val = I915_READ(reg);
1195         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1196              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1197              reg, pipe_name(pipe));
1198 }
1199
1200 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1201                                      enum pipe pipe, int reg)
1202 {
1203         u32 val = I915_READ(reg);
1204         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1205              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1206              reg, pipe_name(pipe));
1207 }
1208
1209 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1210                                       enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1216         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1217         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1218
1219         reg = PCH_ADPA;
1220         val = I915_READ(reg);
1221         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1222              "PCH VGA enabled on transcoder %c, should be disabled\n",
1223              pipe_name(pipe));
1224
1225         reg = PCH_LVDS;
1226         val = I915_READ(reg);
1227         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1228              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1229              pipe_name(pipe));
1230
1231         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1232         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1233         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1234 }
1235
1236 /**
1237  * intel_enable_pll - enable a PLL
1238  * @dev_priv: i915 private structure
1239  * @pipe: pipe PLL to enable
1240  *
1241  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1242  * make sure the PLL reg is writable first though, since the panel write
1243  * protect mechanism may be enabled.
1244  *
1245  * Note!  This is for pre-ILK only.
1246  */
1247 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1248 {
1249         int reg;
1250         u32 val;
1251
1252         /* No really, not for ILK+ */
1253         BUG_ON(dev_priv->info->gen >= 5);
1254
1255         /* PLL is protected by panel, make sure we can write it */
1256         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1257                 assert_panel_unlocked(dev_priv, pipe);
1258
1259         reg = DPLL(pipe);
1260         val = I915_READ(reg);
1261         val |= DPLL_VCO_ENABLE;
1262
1263         /* We do this three times for luck */
1264         I915_WRITE(reg, val);
1265         POSTING_READ(reg);
1266         udelay(150); /* wait for warmup */
1267         I915_WRITE(reg, val);
1268         POSTING_READ(reg);
1269         udelay(150); /* wait for warmup */
1270         I915_WRITE(reg, val);
1271         POSTING_READ(reg);
1272         udelay(150); /* wait for warmup */
1273 }
1274
1275 /**
1276  * intel_disable_pll - disable a PLL
1277  * @dev_priv: i915 private structure
1278  * @pipe: pipe PLL to disable
1279  *
1280  * Disable the PLL for @pipe, making sure the pipe is off first.
1281  *
1282  * Note!  This is for pre-ILK only.
1283  */
1284 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1285 {
1286         int reg;
1287         u32 val;
1288
1289         /* Don't disable pipe A or pipe A PLLs if needed */
1290         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1291                 return;
1292
1293         /* Make sure the pipe isn't still relying on us */
1294         assert_pipe_disabled(dev_priv, pipe);
1295
1296         reg = DPLL(pipe);
1297         val = I915_READ(reg);
1298         val &= ~DPLL_VCO_ENABLE;
1299         I915_WRITE(reg, val);
1300         POSTING_READ(reg);
1301 }
1302
1303 /**
1304  * intel_enable_pch_pll - enable PCH PLL
1305  * @dev_priv: i915 private structure
1306  * @pipe: pipe PLL to enable
1307  *
1308  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1309  * drives the transcoder clock.
1310  */
1311 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1312 {
1313         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1314         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1315         int reg;
1316         u32 val;
1317
1318         /* PCH only available on ILK+ */
1319         BUG_ON(dev_priv->info->gen < 5);
1320         BUG_ON(pll == NULL);
1321         BUG_ON(pll->refcount == 0);
1322
1323         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1324                       pll->pll_reg, pll->active, pll->on,
1325                       intel_crtc->base.base.id);
1326
1327         /* PCH refclock must be enabled first */
1328         assert_pch_refclk_enabled(dev_priv);
1329
1330         if (pll->active++ && pll->on) {
1331                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1332                 return;
1333         }
1334
1335         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1336
1337         reg = pll->pll_reg;
1338         val = I915_READ(reg);
1339         val |= DPLL_VCO_ENABLE;
1340         I915_WRITE(reg, val);
1341         POSTING_READ(reg);
1342         udelay(200);
1343
1344         pll->on = true;
1345 }
1346
1347 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1348 {
1349         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1350         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1351         int reg;
1352         u32 val;
1353
1354         /* PCH only available on ILK+ */
1355         BUG_ON(dev_priv->info->gen < 5);
1356         if (pll == NULL)
1357                return;
1358
1359         BUG_ON(pll->refcount == 0);
1360
1361         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1362                       pll->pll_reg, pll->active, pll->on,
1363                       intel_crtc->base.base.id);
1364
1365         BUG_ON(pll->active == 0);
1366         if (--pll->active) {
1367                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1368                 return;
1369         }
1370
1371         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1372
1373         /* Make sure transcoder isn't still depending on us */
1374         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1375
1376         reg = pll->pll_reg;
1377         val = I915_READ(reg);
1378         val &= ~DPLL_VCO_ENABLE;
1379         I915_WRITE(reg, val);
1380         POSTING_READ(reg);
1381         udelay(200);
1382
1383         pll->on = false;
1384 }
1385
1386 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1387                                     enum pipe pipe)
1388 {
1389         int reg;
1390         u32 val, pipeconf_val;
1391         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1392
1393         /* PCH only available on ILK+ */
1394         BUG_ON(dev_priv->info->gen < 5);
1395
1396         /* Make sure PCH DPLL is enabled */
1397         assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1398
1399         /* FDI must be feeding us bits for PCH ports */
1400         assert_fdi_tx_enabled(dev_priv, pipe);
1401         assert_fdi_rx_enabled(dev_priv, pipe);
1402
1403         reg = TRANSCONF(pipe);
1404         val = I915_READ(reg);
1405         pipeconf_val = I915_READ(PIPECONF(pipe));
1406
1407         if (HAS_PCH_IBX(dev_priv->dev)) {
1408                 /*
1409                  * make the BPC in transcoder be consistent with
1410                  * that in pipeconf reg.
1411                  */
1412                 val &= ~PIPE_BPC_MASK;
1413                 val |= pipeconf_val & PIPE_BPC_MASK;
1414         }
1415
1416         val &= ~TRANS_INTERLACE_MASK;
1417         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1418                 if (HAS_PCH_IBX(dev_priv->dev) &&
1419                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1420                         val |= TRANS_LEGACY_INTERLACED_ILK;
1421                 else
1422                         val |= TRANS_INTERLACED;
1423         else
1424                 val |= TRANS_PROGRESSIVE;
1425
1426         I915_WRITE(reg, val | TRANS_ENABLE);
1427         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1428                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1429 }
1430
1431 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1432                                      enum pipe pipe)
1433 {
1434         int reg;
1435         u32 val;
1436
1437         /* FDI relies on the transcoder */
1438         assert_fdi_tx_disabled(dev_priv, pipe);
1439         assert_fdi_rx_disabled(dev_priv, pipe);
1440
1441         /* Ports must be off as well */
1442         assert_pch_ports_disabled(dev_priv, pipe);
1443
1444         reg = TRANSCONF(pipe);
1445         val = I915_READ(reg);
1446         val &= ~TRANS_ENABLE;
1447         I915_WRITE(reg, val);
1448         /* wait for PCH transcoder off, transcoder state */
1449         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1450                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1451 }
1452
1453 /**
1454  * intel_enable_pipe - enable a pipe, asserting requirements
1455  * @dev_priv: i915 private structure
1456  * @pipe: pipe to enable
1457  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1458  *
1459  * Enable @pipe, making sure that various hardware specific requirements
1460  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1461  *
1462  * @pipe should be %PIPE_A or %PIPE_B.
1463  *
1464  * Will wait until the pipe is actually running (i.e. first vblank) before
1465  * returning.
1466  */
1467 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1468                               bool pch_port)
1469 {
1470         int reg;
1471         u32 val;
1472
1473         /*
1474          * A pipe without a PLL won't actually be able to drive bits from
1475          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1476          * need the check.
1477          */
1478         if (!HAS_PCH_SPLIT(dev_priv->dev))
1479                 assert_pll_enabled(dev_priv, pipe);
1480         else {
1481                 if (pch_port) {
1482                         /* if driving the PCH, we need FDI enabled */
1483                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1484                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1485                 }
1486                 /* FIXME: assert CPU port conditions for SNB+ */
1487         }
1488
1489         reg = PIPECONF(pipe);
1490         val = I915_READ(reg);
1491         if (val & PIPECONF_ENABLE)
1492                 return;
1493
1494         I915_WRITE(reg, val | PIPECONF_ENABLE);
1495         intel_wait_for_vblank(dev_priv->dev, pipe);
1496 }
1497
1498 /**
1499  * intel_disable_pipe - disable a pipe, asserting requirements
1500  * @dev_priv: i915 private structure
1501  * @pipe: pipe to disable
1502  *
1503  * Disable @pipe, making sure that various hardware specific requirements
1504  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1505  *
1506  * @pipe should be %PIPE_A or %PIPE_B.
1507  *
1508  * Will wait until the pipe has shut down before returning.
1509  */
1510 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1511                                enum pipe pipe)
1512 {
1513         int reg;
1514         u32 val;
1515
1516         /*
1517          * Make sure planes won't keep trying to pump pixels to us,
1518          * or we might hang the display.
1519          */
1520         assert_planes_disabled(dev_priv, pipe);
1521
1522         /* Don't disable pipe A or pipe A PLLs if needed */
1523         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1524                 return;
1525
1526         reg = PIPECONF(pipe);
1527         val = I915_READ(reg);
1528         if ((val & PIPECONF_ENABLE) == 0)
1529                 return;
1530
1531         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1532         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1533 }
1534
1535 /*
1536  * Plane regs are double buffered, going from enabled->disabled needs a
1537  * trigger in order to latch.  The display address reg provides this.
1538  */
1539 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1540                                       enum plane plane)
1541 {
1542         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1543         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1544 }
1545
1546 /**
1547  * intel_enable_plane - enable a display plane on a given pipe
1548  * @dev_priv: i915 private structure
1549  * @plane: plane to enable
1550  * @pipe: pipe being fed
1551  *
1552  * Enable @plane on @pipe, making sure that @pipe is running first.
1553  */
1554 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1555                                enum plane plane, enum pipe pipe)
1556 {
1557         int reg;
1558         u32 val;
1559
1560         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1561         assert_pipe_enabled(dev_priv, pipe);
1562
1563         reg = DSPCNTR(plane);
1564         val = I915_READ(reg);
1565         if (val & DISPLAY_PLANE_ENABLE)
1566                 return;
1567
1568         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1569         intel_flush_display_plane(dev_priv, plane);
1570         intel_wait_for_vblank(dev_priv->dev, pipe);
1571 }
1572
1573 /**
1574  * intel_disable_plane - disable a display plane
1575  * @dev_priv: i915 private structure
1576  * @plane: plane to disable
1577  * @pipe: pipe consuming the data
1578  *
1579  * Disable @plane; should be an independent operation.
1580  */
1581 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1582                                 enum plane plane, enum pipe pipe)
1583 {
1584         int reg;
1585         u32 val;
1586
1587         reg = DSPCNTR(plane);
1588         val = I915_READ(reg);
1589         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1590                 return;
1591
1592         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1593         intel_flush_display_plane(dev_priv, plane);
1594         intel_wait_for_vblank(dev_priv->dev, pipe);
1595 }
1596
1597 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1598                            enum pipe pipe, int reg, u32 port_sel)
1599 {
1600         u32 val = I915_READ(reg);
1601         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1602                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1603                 I915_WRITE(reg, val & ~DP_PORT_EN);
1604         }
1605 }
1606
1607 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1608                              enum pipe pipe, int reg)
1609 {
1610         u32 val = I915_READ(reg);
1611         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1612                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1613                               reg, pipe);
1614                 I915_WRITE(reg, val & ~PORT_ENABLE);
1615         }
1616 }
1617
1618 /* Disable any ports connected to this transcoder */
1619 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1620                                     enum pipe pipe)
1621 {
1622         u32 reg, val;
1623
1624         val = I915_READ(PCH_PP_CONTROL);
1625         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1626
1627         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1628         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1629         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1630
1631         reg = PCH_ADPA;
1632         val = I915_READ(reg);
1633         if (adpa_pipe_enabled(dev_priv, val, pipe))
1634                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1635
1636         reg = PCH_LVDS;
1637         val = I915_READ(reg);
1638         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1639                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1640                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1641                 POSTING_READ(reg);
1642                 udelay(100);
1643         }
1644
1645         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1646         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1647         disable_pch_hdmi(dev_priv, pipe, HDMID);
1648 }
1649
1650 int
1651 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1652                            struct drm_i915_gem_object *obj,
1653                            struct intel_ring_buffer *pipelined)
1654 {
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         u32 alignment;
1657         int ret;
1658
1659         switch (obj->tiling_mode) {
1660         case I915_TILING_NONE:
1661                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1662                         alignment = 128 * 1024;
1663                 else if (INTEL_INFO(dev)->gen >= 4)
1664                         alignment = 4 * 1024;
1665                 else
1666                         alignment = 64 * 1024;
1667                 break;
1668         case I915_TILING_X:
1669                 /* pin() will align the object as required by fence */
1670                 alignment = 0;
1671                 break;
1672         case I915_TILING_Y:
1673                 /* FIXME: Is this true? */
1674                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1675                 return -EINVAL;
1676         default:
1677                 BUG();
1678         }
1679
1680         dev_priv->mm.interruptible = false;
1681         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1682         if (ret)
1683                 goto err_interruptible;
1684
1685         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1686          * fence, whereas 965+ only requires a fence if using
1687          * framebuffer compression.  For simplicity, we always install
1688          * a fence as the cost is not that onerous.
1689          */
1690         ret = i915_gem_object_get_fence(obj);
1691         if (ret)
1692                 goto err_unpin;
1693
1694         i915_gem_object_pin_fence(obj);
1695
1696         dev_priv->mm.interruptible = true;
1697         return 0;
1698
1699 err_unpin:
1700         i915_gem_object_unpin(obj);
1701 err_interruptible:
1702         dev_priv->mm.interruptible = true;
1703         return ret;
1704 }
1705
1706 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1707 {
1708         i915_gem_object_unpin_fence(obj);
1709         i915_gem_object_unpin(obj);
1710 }
1711
1712 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1713                              int x, int y)
1714 {
1715         struct drm_device *dev = crtc->dev;
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1718         struct intel_framebuffer *intel_fb;
1719         struct drm_i915_gem_object *obj;
1720         int plane = intel_crtc->plane;
1721         unsigned long Start, Offset;
1722         u32 dspcntr;
1723         u32 reg;
1724
1725         switch (plane) {
1726         case 0:
1727         case 1:
1728                 break;
1729         default:
1730                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1731                 return -EINVAL;
1732         }
1733
1734         intel_fb = to_intel_framebuffer(fb);
1735         obj = intel_fb->obj;
1736
1737         reg = DSPCNTR(plane);
1738         dspcntr = I915_READ(reg);
1739         /* Mask out pixel format bits in case we change it */
1740         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1741         switch (fb->bits_per_pixel) {
1742         case 8:
1743                 dspcntr |= DISPPLANE_8BPP;
1744                 break;
1745         case 16:
1746                 if (fb->depth == 15)
1747                         dspcntr |= DISPPLANE_15_16BPP;
1748                 else
1749                         dspcntr |= DISPPLANE_16BPP;
1750                 break;
1751         case 24:
1752         case 32:
1753                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1754                 break;
1755         default:
1756                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1757                 return -EINVAL;
1758         }
1759         if (INTEL_INFO(dev)->gen >= 4) {
1760                 if (obj->tiling_mode != I915_TILING_NONE)
1761                         dspcntr |= DISPPLANE_TILED;
1762                 else
1763                         dspcntr &= ~DISPPLANE_TILED;
1764         }
1765
1766         I915_WRITE(reg, dspcntr);
1767
1768         Start = obj->gtt_offset;
1769         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1770
1771         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1772                       Start, Offset, x, y, fb->pitches[0]);
1773         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1774         if (INTEL_INFO(dev)->gen >= 4) {
1775                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1776                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1777                 I915_WRITE(DSPADDR(plane), Offset);
1778         } else
1779                 I915_WRITE(DSPADDR(plane), Start + Offset);
1780         POSTING_READ(reg);
1781
1782         return 0;
1783 }
1784
1785 static int ironlake_update_plane(struct drm_crtc *crtc,
1786                                  struct drm_framebuffer *fb, int x, int y)
1787 {
1788         struct drm_device *dev = crtc->dev;
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         struct intel_framebuffer *intel_fb;
1792         struct drm_i915_gem_object *obj;
1793         int plane = intel_crtc->plane;
1794         unsigned long Start, Offset;
1795         u32 dspcntr;
1796         u32 reg;
1797
1798         switch (plane) {
1799         case 0:
1800         case 1:
1801         case 2:
1802                 break;
1803         default:
1804                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1805                 return -EINVAL;
1806         }
1807
1808         intel_fb = to_intel_framebuffer(fb);
1809         obj = intel_fb->obj;
1810
1811         reg = DSPCNTR(plane);
1812         dspcntr = I915_READ(reg);
1813         /* Mask out pixel format bits in case we change it */
1814         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1815         switch (fb->bits_per_pixel) {
1816         case 8:
1817                 dspcntr |= DISPPLANE_8BPP;
1818                 break;
1819         case 16:
1820                 if (fb->depth != 16)
1821                         return -EINVAL;
1822
1823                 dspcntr |= DISPPLANE_16BPP;
1824                 break;
1825         case 24:
1826         case 32:
1827                 if (fb->depth == 24)
1828                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1829                 else if (fb->depth == 30)
1830                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1831                 else
1832                         return -EINVAL;
1833                 break;
1834         default:
1835                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1836                 return -EINVAL;
1837         }
1838
1839         if (obj->tiling_mode != I915_TILING_NONE)
1840                 dspcntr |= DISPPLANE_TILED;
1841         else
1842                 dspcntr &= ~DISPPLANE_TILED;
1843
1844         /* must disable */
1845         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1846
1847         I915_WRITE(reg, dspcntr);
1848
1849         Start = obj->gtt_offset;
1850         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1851
1852         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1853                       Start, Offset, x, y, fb->pitches[0]);
1854         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1855         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1856         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1857         I915_WRITE(DSPADDR(plane), Offset);
1858         POSTING_READ(reg);
1859
1860         return 0;
1861 }
1862
1863 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1864 static int
1865 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1866                            int x, int y, enum mode_set_atomic state)
1867 {
1868         struct drm_device *dev = crtc->dev;
1869         struct drm_i915_private *dev_priv = dev->dev_private;
1870
1871         if (dev_priv->display.disable_fbc)
1872                 dev_priv->display.disable_fbc(dev);
1873         intel_increase_pllclock(crtc);
1874
1875         return dev_priv->display.update_plane(crtc, fb, x, y);
1876 }
1877
1878 static int
1879 intel_finish_fb(struct drm_framebuffer *old_fb)
1880 {
1881         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1882         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1883         bool was_interruptible = dev_priv->mm.interruptible;
1884         int ret;
1885
1886         wait_event(dev_priv->pending_flip_queue,
1887                    atomic_read(&dev_priv->mm.wedged) ||
1888                    atomic_read(&obj->pending_flip) == 0);
1889
1890         /* Big Hammer, we also need to ensure that any pending
1891          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1892          * current scanout is retired before unpinning the old
1893          * framebuffer.
1894          *
1895          * This should only fail upon a hung GPU, in which case we
1896          * can safely continue.
1897          */
1898         dev_priv->mm.interruptible = false;
1899         ret = i915_gem_object_finish_gpu(obj);
1900         dev_priv->mm.interruptible = was_interruptible;
1901
1902         return ret;
1903 }
1904
1905 static int
1906 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1907                     struct drm_framebuffer *old_fb)
1908 {
1909         struct drm_device *dev = crtc->dev;
1910         struct drm_i915_private *dev_priv = dev->dev_private;
1911         struct drm_i915_master_private *master_priv;
1912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1913         int ret;
1914
1915         /* no fb bound */
1916         if (!crtc->fb) {
1917                 DRM_ERROR("No FB bound\n");
1918                 return 0;
1919         }
1920
1921         switch (intel_crtc->plane) {
1922         case 0:
1923         case 1:
1924                 break;
1925         case 2:
1926                 if (IS_IVYBRIDGE(dev))
1927                         break;
1928                 /* fall through otherwise */
1929         default:
1930                 DRM_ERROR("no plane for crtc\n");
1931                 return -EINVAL;
1932         }
1933
1934         mutex_lock(&dev->struct_mutex);
1935         ret = intel_pin_and_fence_fb_obj(dev,
1936                                          to_intel_framebuffer(crtc->fb)->obj,
1937                                          NULL);
1938         if (ret != 0) {
1939                 mutex_unlock(&dev->struct_mutex);
1940                 DRM_ERROR("pin & fence failed\n");
1941                 return ret;
1942         }
1943
1944         if (old_fb)
1945                 intel_finish_fb(old_fb);
1946
1947         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1948         if (ret) {
1949                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1950                 mutex_unlock(&dev->struct_mutex);
1951                 DRM_ERROR("failed to update base address\n");
1952                 return ret;
1953         }
1954
1955         if (old_fb) {
1956                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1957                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1958         }
1959
1960         intel_update_fbc(dev);
1961         mutex_unlock(&dev->struct_mutex);
1962
1963         if (!dev->primary->master)
1964                 return 0;
1965
1966         master_priv = dev->primary->master->driver_priv;
1967         if (!master_priv->sarea_priv)
1968                 return 0;
1969
1970         if (intel_crtc->pipe) {
1971                 master_priv->sarea_priv->pipeB_x = x;
1972                 master_priv->sarea_priv->pipeB_y = y;
1973         } else {
1974                 master_priv->sarea_priv->pipeA_x = x;
1975                 master_priv->sarea_priv->pipeA_y = y;
1976         }
1977
1978         return 0;
1979 }
1980
1981 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1982 {
1983         struct drm_device *dev = crtc->dev;
1984         struct drm_i915_private *dev_priv = dev->dev_private;
1985         u32 dpa_ctl;
1986
1987         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1988         dpa_ctl = I915_READ(DP_A);
1989         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1990
1991         if (clock < 200000) {
1992                 u32 temp;
1993                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1994                 /* workaround for 160Mhz:
1995                    1) program 0x4600c bits 15:0 = 0x8124
1996                    2) program 0x46010 bit 0 = 1
1997                    3) program 0x46034 bit 24 = 1
1998                    4) program 0x64000 bit 14 = 1
1999                    */
2000                 temp = I915_READ(0x4600c);
2001                 temp &= 0xffff0000;
2002                 I915_WRITE(0x4600c, temp | 0x8124);
2003
2004                 temp = I915_READ(0x46010);
2005                 I915_WRITE(0x46010, temp | 1);
2006
2007                 temp = I915_READ(0x46034);
2008                 I915_WRITE(0x46034, temp | (1 << 24));
2009         } else {
2010                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2011         }
2012         I915_WRITE(DP_A, dpa_ctl);
2013
2014         POSTING_READ(DP_A);
2015         udelay(500);
2016 }
2017
2018 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2019 {
2020         struct drm_device *dev = crtc->dev;
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2023         int pipe = intel_crtc->pipe;
2024         u32 reg, temp;
2025
2026         /* enable normal train */
2027         reg = FDI_TX_CTL(pipe);
2028         temp = I915_READ(reg);
2029         if (IS_IVYBRIDGE(dev)) {
2030                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2031                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2032         } else {
2033                 temp &= ~FDI_LINK_TRAIN_NONE;
2034                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2035         }
2036         I915_WRITE(reg, temp);
2037
2038         reg = FDI_RX_CTL(pipe);
2039         temp = I915_READ(reg);
2040         if (HAS_PCH_CPT(dev)) {
2041                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2042                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2043         } else {
2044                 temp &= ~FDI_LINK_TRAIN_NONE;
2045                 temp |= FDI_LINK_TRAIN_NONE;
2046         }
2047         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2048
2049         /* wait one idle pattern time */
2050         POSTING_READ(reg);
2051         udelay(1000);
2052
2053         /* IVB wants error correction enabled */
2054         if (IS_IVYBRIDGE(dev))
2055                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2056                            FDI_FE_ERRC_ENABLE);
2057 }
2058
2059 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2060 {
2061         struct drm_i915_private *dev_priv = dev->dev_private;
2062         u32 flags = I915_READ(SOUTH_CHICKEN1);
2063
2064         flags |= FDI_PHASE_SYNC_OVR(pipe);
2065         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2066         flags |= FDI_PHASE_SYNC_EN(pipe);
2067         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2068         POSTING_READ(SOUTH_CHICKEN1);
2069 }
2070
2071 /* The FDI link training functions for ILK/Ibexpeak. */
2072 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077         int pipe = intel_crtc->pipe;
2078         int plane = intel_crtc->plane;
2079         u32 reg, temp, tries;
2080
2081         /* FDI needs bits from pipe & plane first */
2082         assert_pipe_enabled(dev_priv, pipe);
2083         assert_plane_enabled(dev_priv, plane);
2084
2085         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2086            for train result */
2087         reg = FDI_RX_IMR(pipe);
2088         temp = I915_READ(reg);
2089         temp &= ~FDI_RX_SYMBOL_LOCK;
2090         temp &= ~FDI_RX_BIT_LOCK;
2091         I915_WRITE(reg, temp);
2092         I915_READ(reg);
2093         udelay(150);
2094
2095         /* enable CPU FDI TX and PCH FDI RX */
2096         reg = FDI_TX_CTL(pipe);
2097         temp = I915_READ(reg);
2098         temp &= ~(7 << 19);
2099         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2100         temp &= ~FDI_LINK_TRAIN_NONE;
2101         temp |= FDI_LINK_TRAIN_PATTERN_1;
2102         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2103
2104         reg = FDI_RX_CTL(pipe);
2105         temp = I915_READ(reg);
2106         temp &= ~FDI_LINK_TRAIN_NONE;
2107         temp |= FDI_LINK_TRAIN_PATTERN_1;
2108         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2109
2110         POSTING_READ(reg);
2111         udelay(150);
2112
2113         /* Ironlake workaround, enable clock pointer after FDI enable*/
2114         if (HAS_PCH_IBX(dev)) {
2115                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2116                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2117                            FDI_RX_PHASE_SYNC_POINTER_EN);
2118         }
2119
2120         reg = FDI_RX_IIR(pipe);
2121         for (tries = 0; tries < 5; tries++) {
2122                 temp = I915_READ(reg);
2123                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2124
2125                 if ((temp & FDI_RX_BIT_LOCK)) {
2126                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2127                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2128                         break;
2129                 }
2130         }
2131         if (tries == 5)
2132                 DRM_ERROR("FDI train 1 fail!\n");
2133
2134         /* Train 2 */
2135         reg = FDI_TX_CTL(pipe);
2136         temp = I915_READ(reg);
2137         temp &= ~FDI_LINK_TRAIN_NONE;
2138         temp |= FDI_LINK_TRAIN_PATTERN_2;
2139         I915_WRITE(reg, temp);
2140
2141         reg = FDI_RX_CTL(pipe);
2142         temp = I915_READ(reg);
2143         temp &= ~FDI_LINK_TRAIN_NONE;
2144         temp |= FDI_LINK_TRAIN_PATTERN_2;
2145         I915_WRITE(reg, temp);
2146
2147         POSTING_READ(reg);
2148         udelay(150);
2149
2150         reg = FDI_RX_IIR(pipe);
2151         for (tries = 0; tries < 5; tries++) {
2152                 temp = I915_READ(reg);
2153                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2154
2155                 if (temp & FDI_RX_SYMBOL_LOCK) {
2156                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2157                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2158                         break;
2159                 }
2160         }
2161         if (tries == 5)
2162                 DRM_ERROR("FDI train 2 fail!\n");
2163
2164         DRM_DEBUG_KMS("FDI train done\n");
2165
2166 }
2167
2168 static const int snb_b_fdi_train_param[] = {
2169         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2170         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2171         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2172         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2173 };
2174
2175 /* The FDI link training functions for SNB/Cougarpoint. */
2176 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2177 {
2178         struct drm_device *dev = crtc->dev;
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181         int pipe = intel_crtc->pipe;
2182         u32 reg, temp, i, retry;
2183
2184         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2185            for train result */
2186         reg = FDI_RX_IMR(pipe);
2187         temp = I915_READ(reg);
2188         temp &= ~FDI_RX_SYMBOL_LOCK;
2189         temp &= ~FDI_RX_BIT_LOCK;
2190         I915_WRITE(reg, temp);
2191
2192         POSTING_READ(reg);
2193         udelay(150);
2194
2195         /* enable CPU FDI TX and PCH FDI RX */
2196         reg = FDI_TX_CTL(pipe);
2197         temp = I915_READ(reg);
2198         temp &= ~(7 << 19);
2199         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2200         temp &= ~FDI_LINK_TRAIN_NONE;
2201         temp |= FDI_LINK_TRAIN_PATTERN_1;
2202         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2203         /* SNB-B */
2204         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2205         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2206
2207         reg = FDI_RX_CTL(pipe);
2208         temp = I915_READ(reg);
2209         if (HAS_PCH_CPT(dev)) {
2210                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2211                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2212         } else {
2213                 temp &= ~FDI_LINK_TRAIN_NONE;
2214                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2215         }
2216         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2217
2218         POSTING_READ(reg);
2219         udelay(150);
2220
2221         if (HAS_PCH_CPT(dev))
2222                 cpt_phase_pointer_enable(dev, pipe);
2223
2224         for (i = 0; i < 4; i++) {
2225                 reg = FDI_TX_CTL(pipe);
2226                 temp = I915_READ(reg);
2227                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2228                 temp |= snb_b_fdi_train_param[i];
2229                 I915_WRITE(reg, temp);
2230
2231                 POSTING_READ(reg);
2232                 udelay(500);
2233
2234                 for (retry = 0; retry < 5; retry++) {
2235                         reg = FDI_RX_IIR(pipe);
2236                         temp = I915_READ(reg);
2237                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2238                         if (temp & FDI_RX_BIT_LOCK) {
2239                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2240                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2241                                 break;
2242                         }
2243                         udelay(50);
2244                 }
2245                 if (retry < 5)
2246                         break;
2247         }
2248         if (i == 4)
2249                 DRM_ERROR("FDI train 1 fail!\n");
2250
2251         /* Train 2 */
2252         reg = FDI_TX_CTL(pipe);
2253         temp = I915_READ(reg);
2254         temp &= ~FDI_LINK_TRAIN_NONE;
2255         temp |= FDI_LINK_TRAIN_PATTERN_2;
2256         if (IS_GEN6(dev)) {
2257                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2258                 /* SNB-B */
2259                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2260         }
2261         I915_WRITE(reg, temp);
2262
2263         reg = FDI_RX_CTL(pipe);
2264         temp = I915_READ(reg);
2265         if (HAS_PCH_CPT(dev)) {
2266                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2268         } else {
2269                 temp &= ~FDI_LINK_TRAIN_NONE;
2270                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2271         }
2272         I915_WRITE(reg, temp);
2273
2274         POSTING_READ(reg);
2275         udelay(150);
2276
2277         for (i = 0; i < 4; i++) {
2278                 reg = FDI_TX_CTL(pipe);
2279                 temp = I915_READ(reg);
2280                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2281                 temp |= snb_b_fdi_train_param[i];
2282                 I915_WRITE(reg, temp);
2283
2284                 POSTING_READ(reg);
2285                 udelay(500);
2286
2287                 for (retry = 0; retry < 5; retry++) {
2288                         reg = FDI_RX_IIR(pipe);
2289                         temp = I915_READ(reg);
2290                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2291                         if (temp & FDI_RX_SYMBOL_LOCK) {
2292                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2293                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2294                                 break;
2295                         }
2296                         udelay(50);
2297                 }
2298                 if (retry < 5)
2299                         break;
2300         }
2301         if (i == 4)
2302                 DRM_ERROR("FDI train 2 fail!\n");
2303
2304         DRM_DEBUG_KMS("FDI train done.\n");
2305 }
2306
2307 /* Manual link training for Ivy Bridge A0 parts */
2308 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2309 {
2310         struct drm_device *dev = crtc->dev;
2311         struct drm_i915_private *dev_priv = dev->dev_private;
2312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2313         int pipe = intel_crtc->pipe;
2314         u32 reg, temp, i;
2315
2316         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2317            for train result */
2318         reg = FDI_RX_IMR(pipe);
2319         temp = I915_READ(reg);
2320         temp &= ~FDI_RX_SYMBOL_LOCK;
2321         temp &= ~FDI_RX_BIT_LOCK;
2322         I915_WRITE(reg, temp);
2323
2324         POSTING_READ(reg);
2325         udelay(150);
2326
2327         /* enable CPU FDI TX and PCH FDI RX */
2328         reg = FDI_TX_CTL(pipe);
2329         temp = I915_READ(reg);
2330         temp &= ~(7 << 19);
2331         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2332         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2333         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2334         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2335         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2336         temp |= FDI_COMPOSITE_SYNC;
2337         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2338
2339         reg = FDI_RX_CTL(pipe);
2340         temp = I915_READ(reg);
2341         temp &= ~FDI_LINK_TRAIN_AUTO;
2342         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2343         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2344         temp |= FDI_COMPOSITE_SYNC;
2345         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2346
2347         POSTING_READ(reg);
2348         udelay(150);
2349
2350         if (HAS_PCH_CPT(dev))
2351                 cpt_phase_pointer_enable(dev, pipe);
2352
2353         for (i = 0; i < 4; i++) {
2354                 reg = FDI_TX_CTL(pipe);
2355                 temp = I915_READ(reg);
2356                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2357                 temp |= snb_b_fdi_train_param[i];
2358                 I915_WRITE(reg, temp);
2359
2360                 POSTING_READ(reg);
2361                 udelay(500);
2362
2363                 reg = FDI_RX_IIR(pipe);
2364                 temp = I915_READ(reg);
2365                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367                 if (temp & FDI_RX_BIT_LOCK ||
2368                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2369                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2370                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2371                         break;
2372                 }
2373         }
2374         if (i == 4)
2375                 DRM_ERROR("FDI train 1 fail!\n");
2376
2377         /* Train 2 */
2378         reg = FDI_TX_CTL(pipe);
2379         temp = I915_READ(reg);
2380         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2381         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2382         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2383         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2384         I915_WRITE(reg, temp);
2385
2386         reg = FDI_RX_CTL(pipe);
2387         temp = I915_READ(reg);
2388         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2389         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2390         I915_WRITE(reg, temp);
2391
2392         POSTING_READ(reg);
2393         udelay(150);
2394
2395         for (i = 0; i < 4; i++) {
2396                 reg = FDI_TX_CTL(pipe);
2397                 temp = I915_READ(reg);
2398                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2399                 temp |= snb_b_fdi_train_param[i];
2400                 I915_WRITE(reg, temp);
2401
2402                 POSTING_READ(reg);
2403                 udelay(500);
2404
2405                 reg = FDI_RX_IIR(pipe);
2406                 temp = I915_READ(reg);
2407                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409                 if (temp & FDI_RX_SYMBOL_LOCK) {
2410                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2411                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2412                         break;
2413                 }
2414         }
2415         if (i == 4)
2416                 DRM_ERROR("FDI train 2 fail!\n");
2417
2418         DRM_DEBUG_KMS("FDI train done.\n");
2419 }
2420
2421 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         u32 reg, temp;
2428
2429         /* Write the TU size bits so error detection works */
2430         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2431                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2432
2433         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2434         reg = FDI_RX_CTL(pipe);
2435         temp = I915_READ(reg);
2436         temp &= ~((0x7 << 19) | (0x7 << 16));
2437         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2438         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2439         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2440
2441         POSTING_READ(reg);
2442         udelay(200);
2443
2444         /* Switch from Rawclk to PCDclk */
2445         temp = I915_READ(reg);
2446         I915_WRITE(reg, temp | FDI_PCDCLK);
2447
2448         POSTING_READ(reg);
2449         udelay(200);
2450
2451         /* Enable CPU FDI TX PLL, always on for Ironlake */
2452         reg = FDI_TX_CTL(pipe);
2453         temp = I915_READ(reg);
2454         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2455                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2456
2457                 POSTING_READ(reg);
2458                 udelay(100);
2459         }
2460 }
2461
2462 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2463 {
2464         struct drm_i915_private *dev_priv = dev->dev_private;
2465         u32 flags = I915_READ(SOUTH_CHICKEN1);
2466
2467         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2468         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2469         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2470         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2471         POSTING_READ(SOUTH_CHICKEN1);
2472 }
2473 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2474 {
2475         struct drm_device *dev = crtc->dev;
2476         struct drm_i915_private *dev_priv = dev->dev_private;
2477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2478         int pipe = intel_crtc->pipe;
2479         u32 reg, temp;
2480
2481         /* disable CPU FDI tx and PCH FDI rx */
2482         reg = FDI_TX_CTL(pipe);
2483         temp = I915_READ(reg);
2484         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2485         POSTING_READ(reg);
2486
2487         reg = FDI_RX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(0x7 << 16);
2490         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2491         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2492
2493         POSTING_READ(reg);
2494         udelay(100);
2495
2496         /* Ironlake workaround, disable clock pointer after downing FDI */
2497         if (HAS_PCH_IBX(dev)) {
2498                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2500                            I915_READ(FDI_RX_CHICKEN(pipe) &
2501                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2502         } else if (HAS_PCH_CPT(dev)) {
2503                 cpt_phase_pointer_disable(dev, pipe);
2504         }
2505
2506         /* still set train pattern 1 */
2507         reg = FDI_TX_CTL(pipe);
2508         temp = I915_READ(reg);
2509         temp &= ~FDI_LINK_TRAIN_NONE;
2510         temp |= FDI_LINK_TRAIN_PATTERN_1;
2511         I915_WRITE(reg, temp);
2512
2513         reg = FDI_RX_CTL(pipe);
2514         temp = I915_READ(reg);
2515         if (HAS_PCH_CPT(dev)) {
2516                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2517                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2518         } else {
2519                 temp &= ~FDI_LINK_TRAIN_NONE;
2520                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2521         }
2522         /* BPC in FDI rx is consistent with that in PIPECONF */
2523         temp &= ~(0x07 << 16);
2524         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(100);
2529 }
2530
2531 /*
2532  * When we disable a pipe, we need to clear any pending scanline wait events
2533  * to avoid hanging the ring, which we assume we are waiting on.
2534  */
2535 static void intel_clear_scanline_wait(struct drm_device *dev)
2536 {
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         struct intel_ring_buffer *ring;
2539         u32 tmp;
2540
2541         if (IS_GEN2(dev))
2542                 /* Can't break the hang on i8xx */
2543                 return;
2544
2545         ring = LP_RING(dev_priv);
2546         tmp = I915_READ_CTL(ring);
2547         if (tmp & RING_WAIT)
2548                 I915_WRITE_CTL(ring, tmp);
2549 }
2550
2551 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2552 {
2553         struct drm_device *dev = crtc->dev;
2554
2555         if (crtc->fb == NULL)
2556                 return;
2557
2558         mutex_lock(&dev->struct_mutex);
2559         intel_finish_fb(crtc->fb);
2560         mutex_unlock(&dev->struct_mutex);
2561 }
2562
2563 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_mode_config *mode_config = &dev->mode_config;
2567         struct intel_encoder *encoder;
2568
2569         /*
2570          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2571          * must be driven by its own crtc; no sharing is possible.
2572          */
2573         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2574                 if (encoder->base.crtc != crtc)
2575                         continue;
2576
2577                 switch (encoder->type) {
2578                 case INTEL_OUTPUT_EDP:
2579                         if (!intel_encoder_is_pch_edp(&encoder->base))
2580                                 return false;
2581                         continue;
2582                 }
2583         }
2584
2585         return true;
2586 }
2587
2588 /*
2589  * Enable PCH resources required for PCH ports:
2590  *   - PCH PLLs
2591  *   - FDI training & RX/TX
2592  *   - update transcoder timings
2593  *   - DP transcoding bits
2594  *   - transcoder
2595  */
2596 static void ironlake_pch_enable(struct drm_crtc *crtc)
2597 {
2598         struct drm_device *dev = crtc->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601         int pipe = intel_crtc->pipe;
2602         u32 reg, temp;
2603
2604         /* For PCH output, training FDI link */
2605         dev_priv->display.fdi_link_train(crtc);
2606
2607         intel_enable_pch_pll(intel_crtc);
2608
2609         if (HAS_PCH_CPT(dev)) {
2610                 u32 sel;
2611
2612                 temp = I915_READ(PCH_DPLL_SEL);
2613                 switch (pipe) {
2614                 default:
2615                 case 0:
2616                         temp |= TRANSA_DPLL_ENABLE;
2617                         sel = TRANSA_DPLLB_SEL;
2618                         break;
2619                 case 1:
2620                         temp |= TRANSB_DPLL_ENABLE;
2621                         sel = TRANSB_DPLLB_SEL;
2622                         break;
2623                 case 2:
2624                         temp |= TRANSC_DPLL_ENABLE;
2625                         sel = TRANSC_DPLLB_SEL;
2626                         break;
2627                 }
2628                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2629                         temp |= sel;
2630                 else
2631                         temp &= ~sel;
2632                 I915_WRITE(PCH_DPLL_SEL, temp);
2633         }
2634
2635         /* set transcoder timing, panel must allow it */
2636         assert_panel_unlocked(dev_priv, pipe);
2637         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2638         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2639         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2640
2641         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2642         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2643         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2644         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2645
2646         intel_fdi_normal_train(crtc);
2647
2648         /* For PCH DP, enable TRANS_DP_CTL */
2649         if (HAS_PCH_CPT(dev) &&
2650             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2651              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2652                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2653                 reg = TRANS_DP_CTL(pipe);
2654                 temp = I915_READ(reg);
2655                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2656                           TRANS_DP_SYNC_MASK |
2657                           TRANS_DP_BPC_MASK);
2658                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2659                          TRANS_DP_ENH_FRAMING);
2660                 temp |= bpc << 9; /* same format but at 11:9 */
2661
2662                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2663                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2664                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2665                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2666
2667                 switch (intel_trans_dp_port_sel(crtc)) {
2668                 case PCH_DP_B:
2669                         temp |= TRANS_DP_PORT_SEL_B;
2670                         break;
2671                 case PCH_DP_C:
2672                         temp |= TRANS_DP_PORT_SEL_C;
2673                         break;
2674                 case PCH_DP_D:
2675                         temp |= TRANS_DP_PORT_SEL_D;
2676                         break;
2677                 default:
2678                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2679                         temp |= TRANS_DP_PORT_SEL_B;
2680                         break;
2681                 }
2682
2683                 I915_WRITE(reg, temp);
2684         }
2685
2686         intel_enable_transcoder(dev_priv, pipe);
2687 }
2688
2689 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2690 {
2691         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2692
2693         if (pll == NULL)
2694                 return;
2695
2696         if (pll->refcount == 0) {
2697                 WARN(1, "bad PCH PLL refcount\n");
2698                 return;
2699         }
2700
2701         --pll->refcount;
2702         intel_crtc->pch_pll = NULL;
2703 }
2704
2705 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2706 {
2707         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2708         struct intel_pch_pll *pll;
2709         int i;
2710
2711         pll = intel_crtc->pch_pll;
2712         if (pll) {
2713                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2714                               intel_crtc->base.base.id, pll->pll_reg);
2715                 goto prepare;
2716         }
2717
2718         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2719                 pll = &dev_priv->pch_plls[i];
2720
2721                 /* Only want to check enabled timings first */
2722                 if (pll->refcount == 0)
2723                         continue;
2724
2725                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2726                     fp == I915_READ(pll->fp0_reg)) {
2727                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2728                                       intel_crtc->base.base.id,
2729                                       pll->pll_reg, pll->refcount, pll->active);
2730
2731                         goto found;
2732                 }
2733         }
2734
2735         /* Ok no matching timings, maybe there's a free one? */
2736         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2737                 pll = &dev_priv->pch_plls[i];
2738                 if (pll->refcount == 0) {
2739                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2740                                       intel_crtc->base.base.id, pll->pll_reg);
2741                         goto found;
2742                 }
2743         }
2744
2745         return NULL;
2746
2747 found:
2748         intel_crtc->pch_pll = pll;
2749         pll->refcount++;
2750         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2751 prepare: /* separate function? */
2752         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2753         I915_WRITE(pll->fp0_reg, fp);
2754         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2755
2756         POSTING_READ(pll->pll_reg);
2757         udelay(150);
2758         pll->on = false;
2759         return pll;
2760 }
2761
2762 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2763 {
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2766         u32 temp;
2767
2768         temp = I915_READ(dslreg);
2769         udelay(500);
2770         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2771                 /* Without this, mode sets may fail silently on FDI */
2772                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2773                 udelay(250);
2774                 I915_WRITE(tc2reg, 0);
2775                 if (wait_for(I915_READ(dslreg) != temp, 5))
2776                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2777         }
2778 }
2779
2780 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2781 {
2782         struct drm_device *dev = crtc->dev;
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2785         int pipe = intel_crtc->pipe;
2786         int plane = intel_crtc->plane;
2787         u32 temp;
2788         bool is_pch_port;
2789
2790         if (intel_crtc->active)
2791                 return;
2792
2793         intel_crtc->active = true;
2794         intel_update_watermarks(dev);
2795
2796         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2797                 temp = I915_READ(PCH_LVDS);
2798                 if ((temp & LVDS_PORT_EN) == 0)
2799                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2800         }
2801
2802         is_pch_port = intel_crtc_driving_pch(crtc);
2803
2804         if (is_pch_port)
2805                 ironlake_fdi_pll_enable(crtc);
2806         else
2807                 ironlake_fdi_disable(crtc);
2808
2809         /* Enable panel fitting for LVDS */
2810         if (dev_priv->pch_pf_size &&
2811             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2812                 /* Force use of hard-coded filter coefficients
2813                  * as some pre-programmed values are broken,
2814                  * e.g. x201.
2815                  */
2816                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2817                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2818                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2819         }
2820
2821         /*
2822          * On ILK+ LUT must be loaded before the pipe is running but with
2823          * clocks enabled
2824          */
2825         intel_crtc_load_lut(crtc);
2826
2827         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2828         intel_enable_plane(dev_priv, plane, pipe);
2829
2830         if (is_pch_port)
2831                 ironlake_pch_enable(crtc);
2832
2833         mutex_lock(&dev->struct_mutex);
2834         intel_update_fbc(dev);
2835         mutex_unlock(&dev->struct_mutex);
2836
2837         intel_crtc_update_cursor(crtc, true);
2838 }
2839
2840 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2841 {
2842         struct drm_device *dev = crtc->dev;
2843         struct drm_i915_private *dev_priv = dev->dev_private;
2844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2845         int pipe = intel_crtc->pipe;
2846         int plane = intel_crtc->plane;
2847         u32 reg, temp;
2848
2849         if (!intel_crtc->active)
2850                 return;
2851
2852         intel_crtc_wait_for_pending_flips(crtc);
2853         drm_vblank_off(dev, pipe);
2854         intel_crtc_update_cursor(crtc, false);
2855
2856         intel_disable_plane(dev_priv, plane, pipe);
2857
2858         if (dev_priv->cfb_plane == plane)
2859                 intel_disable_fbc(dev);
2860
2861         intel_disable_pipe(dev_priv, pipe);
2862
2863         /* Disable PF */
2864         I915_WRITE(PF_CTL(pipe), 0);
2865         I915_WRITE(PF_WIN_SZ(pipe), 0);
2866
2867         ironlake_fdi_disable(crtc);
2868
2869         /* This is a horrible layering violation; we should be doing this in
2870          * the connector/encoder ->prepare instead, but we don't always have
2871          * enough information there about the config to know whether it will
2872          * actually be necessary or just cause undesired flicker.
2873          */
2874         intel_disable_pch_ports(dev_priv, pipe);
2875
2876         intel_disable_transcoder(dev_priv, pipe);
2877
2878         if (HAS_PCH_CPT(dev)) {
2879                 /* disable TRANS_DP_CTL */
2880                 reg = TRANS_DP_CTL(pipe);
2881                 temp = I915_READ(reg);
2882                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2883                 temp |= TRANS_DP_PORT_SEL_NONE;
2884                 I915_WRITE(reg, temp);
2885
2886                 /* disable DPLL_SEL */
2887                 temp = I915_READ(PCH_DPLL_SEL);
2888                 switch (pipe) {
2889                 case 0:
2890                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2891                         break;
2892                 case 1:
2893                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2894                         break;
2895                 case 2:
2896                         /* C shares PLL A or B */
2897                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2898                         break;
2899                 default:
2900                         BUG(); /* wtf */
2901                 }
2902                 I915_WRITE(PCH_DPLL_SEL, temp);
2903         }
2904
2905         /* disable PCH DPLL */
2906         intel_disable_pch_pll(intel_crtc);
2907
2908         /* Switch from PCDclk to Rawclk */
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2912
2913         /* Disable CPU FDI TX PLL */
2914         reg = FDI_TX_CTL(pipe);
2915         temp = I915_READ(reg);
2916         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2917
2918         POSTING_READ(reg);
2919         udelay(100);
2920
2921         reg = FDI_RX_CTL(pipe);
2922         temp = I915_READ(reg);
2923         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2924
2925         /* Wait for the clocks to turn off. */
2926         POSTING_READ(reg);
2927         udelay(100);
2928
2929         intel_crtc->active = false;
2930         intel_update_watermarks(dev);
2931
2932         mutex_lock(&dev->struct_mutex);
2933         intel_update_fbc(dev);
2934         intel_clear_scanline_wait(dev);
2935         mutex_unlock(&dev->struct_mutex);
2936 }
2937
2938 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2939 {
2940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941         int pipe = intel_crtc->pipe;
2942         int plane = intel_crtc->plane;
2943
2944         /* XXX: When our outputs are all unaware of DPMS modes other than off
2945          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2946          */
2947         switch (mode) {
2948         case DRM_MODE_DPMS_ON:
2949         case DRM_MODE_DPMS_STANDBY:
2950         case DRM_MODE_DPMS_SUSPEND:
2951                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2952                 ironlake_crtc_enable(crtc);
2953                 break;
2954
2955         case DRM_MODE_DPMS_OFF:
2956                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2957                 ironlake_crtc_disable(crtc);
2958                 break;
2959         }
2960 }
2961
2962 static void ironlake_crtc_off(struct drm_crtc *crtc)
2963 {
2964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965         intel_put_pch_pll(intel_crtc);
2966 }
2967
2968 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2969 {
2970         if (!enable && intel_crtc->overlay) {
2971                 struct drm_device *dev = intel_crtc->base.dev;
2972                 struct drm_i915_private *dev_priv = dev->dev_private;
2973
2974                 mutex_lock(&dev->struct_mutex);
2975                 dev_priv->mm.interruptible = false;
2976                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2977                 dev_priv->mm.interruptible = true;
2978                 mutex_unlock(&dev->struct_mutex);
2979         }
2980
2981         /* Let userspace switch the overlay on again. In most cases userspace
2982          * has to recompute where to put it anyway.
2983          */
2984 }
2985
2986 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2987 {
2988         struct drm_device *dev = crtc->dev;
2989         struct drm_i915_private *dev_priv = dev->dev_private;
2990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2991         int pipe = intel_crtc->pipe;
2992         int plane = intel_crtc->plane;
2993
2994         if (intel_crtc->active)
2995                 return;
2996
2997         intel_crtc->active = true;
2998         intel_update_watermarks(dev);
2999
3000         intel_enable_pll(dev_priv, pipe);
3001         intel_enable_pipe(dev_priv, pipe, false);
3002         intel_enable_plane(dev_priv, plane, pipe);
3003
3004         intel_crtc_load_lut(crtc);
3005         intel_update_fbc(dev);
3006
3007         /* Give the overlay scaler a chance to enable if it's on this pipe */
3008         intel_crtc_dpms_overlay(intel_crtc, true);
3009         intel_crtc_update_cursor(crtc, true);
3010 }
3011
3012 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3013 {
3014         struct drm_device *dev = crtc->dev;
3015         struct drm_i915_private *dev_priv = dev->dev_private;
3016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3017         int pipe = intel_crtc->pipe;
3018         int plane = intel_crtc->plane;
3019
3020         if (!intel_crtc->active)
3021                 return;
3022
3023         /* Give the overlay scaler a chance to disable if it's on this pipe */
3024         intel_crtc_wait_for_pending_flips(crtc);
3025         drm_vblank_off(dev, pipe);
3026         intel_crtc_dpms_overlay(intel_crtc, false);
3027         intel_crtc_update_cursor(crtc, false);
3028
3029         if (dev_priv->cfb_plane == plane)
3030                 intel_disable_fbc(dev);
3031
3032         intel_disable_plane(dev_priv, plane, pipe);
3033         intel_disable_pipe(dev_priv, pipe);
3034         intel_disable_pll(dev_priv, pipe);
3035
3036         intel_crtc->active = false;
3037         intel_update_fbc(dev);
3038         intel_update_watermarks(dev);
3039         intel_clear_scanline_wait(dev);
3040 }
3041
3042 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3043 {
3044         /* XXX: When our outputs are all unaware of DPMS modes other than off
3045          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3046          */
3047         switch (mode) {
3048         case DRM_MODE_DPMS_ON:
3049         case DRM_MODE_DPMS_STANDBY:
3050         case DRM_MODE_DPMS_SUSPEND:
3051                 i9xx_crtc_enable(crtc);
3052                 break;
3053         case DRM_MODE_DPMS_OFF:
3054                 i9xx_crtc_disable(crtc);
3055                 break;
3056         }
3057 }
3058
3059 static void i9xx_crtc_off(struct drm_crtc *crtc)
3060 {
3061 }
3062
3063 /**
3064  * Sets the power management mode of the pipe and plane.
3065  */
3066 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3067 {
3068         struct drm_device *dev = crtc->dev;
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct drm_i915_master_private *master_priv;
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3072         int pipe = intel_crtc->pipe;
3073         bool enabled;
3074
3075         if (intel_crtc->dpms_mode == mode)
3076                 return;
3077
3078         intel_crtc->dpms_mode = mode;
3079
3080         dev_priv->display.dpms(crtc, mode);
3081
3082         if (!dev->primary->master)
3083                 return;
3084
3085         master_priv = dev->primary->master->driver_priv;
3086         if (!master_priv->sarea_priv)
3087                 return;
3088
3089         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3090
3091         switch (pipe) {
3092         case 0:
3093                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3094                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3095                 break;
3096         case 1:
3097                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3098                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3099                 break;
3100         default:
3101                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3102                 break;
3103         }
3104 }
3105
3106 static void intel_crtc_disable(struct drm_crtc *crtc)
3107 {
3108         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3109         struct drm_device *dev = crtc->dev;
3110         struct drm_i915_private *dev_priv = dev->dev_private;
3111
3112         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3113         dev_priv->display.off(crtc);
3114
3115         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3116         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3117
3118         if (crtc->fb) {
3119                 mutex_lock(&dev->struct_mutex);
3120                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3121                 mutex_unlock(&dev->struct_mutex);
3122         }
3123 }
3124
3125 /* Prepare for a mode set.
3126  *
3127  * Note we could be a lot smarter here.  We need to figure out which outputs
3128  * will be enabled, which disabled (in short, how the config will changes)
3129  * and perform the minimum necessary steps to accomplish that, e.g. updating
3130  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3131  * panel fitting is in the proper state, etc.
3132  */
3133 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3134 {
3135         i9xx_crtc_disable(crtc);
3136 }
3137
3138 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3139 {
3140         i9xx_crtc_enable(crtc);
3141 }
3142
3143 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3144 {
3145         ironlake_crtc_disable(crtc);
3146 }
3147
3148 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3149 {
3150         ironlake_crtc_enable(crtc);
3151 }
3152
3153 void intel_encoder_prepare(struct drm_encoder *encoder)
3154 {
3155         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3156         /* lvds has its own version of prepare see intel_lvds_prepare */
3157         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3158 }
3159
3160 void intel_encoder_commit(struct drm_encoder *encoder)
3161 {
3162         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3163         struct drm_device *dev = encoder->dev;
3164         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3165         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3166
3167         /* lvds has its own version of commit see intel_lvds_commit */
3168         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3169
3170         if (HAS_PCH_CPT(dev))
3171                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3172 }
3173
3174 void intel_encoder_destroy(struct drm_encoder *encoder)
3175 {
3176         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3177
3178         drm_encoder_cleanup(encoder);
3179         kfree(intel_encoder);
3180 }
3181
3182 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3183                                   struct drm_display_mode *mode,
3184                                   struct drm_display_mode *adjusted_mode)
3185 {
3186         struct drm_device *dev = crtc->dev;
3187
3188         if (HAS_PCH_SPLIT(dev)) {
3189                 /* FDI link clock is fixed at 2.7G */
3190                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3191                         return false;
3192         }
3193
3194         /* All interlaced capable intel hw wants timings in frames. */
3195         drm_mode_set_crtcinfo(adjusted_mode, 0);
3196
3197         return true;
3198 }
3199
3200 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3201 {
3202         return 400000; /* FIXME */
3203 }
3204
3205 static int i945_get_display_clock_speed(struct drm_device *dev)
3206 {
3207         return 400000;
3208 }
3209
3210 static int i915_get_display_clock_speed(struct drm_device *dev)
3211 {
3212         return 333000;
3213 }
3214
3215 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3216 {
3217         return 200000;
3218 }
3219
3220 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3221 {
3222         u16 gcfgc = 0;
3223
3224         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3225
3226         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3227                 return 133000;
3228         else {
3229                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3230                 case GC_DISPLAY_CLOCK_333_MHZ:
3231                         return 333000;
3232                 default:
3233                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3234                         return 190000;
3235                 }
3236         }
3237 }
3238
3239 static int i865_get_display_clock_speed(struct drm_device *dev)
3240 {
3241         return 266000;
3242 }
3243
3244 static int i855_get_display_clock_speed(struct drm_device *dev)
3245 {
3246         u16 hpllcc = 0;
3247         /* Assume that the hardware is in the high speed state.  This
3248          * should be the default.
3249          */
3250         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3251         case GC_CLOCK_133_200:
3252         case GC_CLOCK_100_200:
3253                 return 200000;
3254         case GC_CLOCK_166_250:
3255                 return 250000;
3256         case GC_CLOCK_100_133:
3257                 return 133000;
3258         }
3259
3260         /* Shouldn't happen */
3261         return 0;
3262 }
3263
3264 static int i830_get_display_clock_speed(struct drm_device *dev)
3265 {
3266         return 133000;
3267 }
3268
3269 struct fdi_m_n {
3270         u32        tu;
3271         u32        gmch_m;
3272         u32        gmch_n;
3273         u32        link_m;
3274         u32        link_n;
3275 };
3276
3277 static void
3278 fdi_reduce_ratio(u32 *num, u32 *den)
3279 {
3280         while (*num > 0xffffff || *den > 0xffffff) {
3281                 *num >>= 1;
3282                 *den >>= 1;
3283         }
3284 }
3285
3286 static void
3287 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3288                      int link_clock, struct fdi_m_n *m_n)
3289 {
3290         m_n->tu = 64; /* default size */
3291
3292         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3293         m_n->gmch_m = bits_per_pixel * pixel_clock;
3294         m_n->gmch_n = link_clock * nlanes * 8;
3295         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3296
3297         m_n->link_m = pixel_clock;
3298         m_n->link_n = link_clock;
3299         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3300 }
3301
3302 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3303 {
3304         if (i915_panel_use_ssc >= 0)
3305                 return i915_panel_use_ssc != 0;
3306         return dev_priv->lvds_use_ssc
3307                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3308 }
3309
3310 /**
3311  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3312  * @crtc: CRTC structure
3313  * @mode: requested mode
3314  *
3315  * A pipe may be connected to one or more outputs.  Based on the depth of the
3316  * attached framebuffer, choose a good color depth to use on the pipe.
3317  *
3318  * If possible, match the pipe depth to the fb depth.  In some cases, this
3319  * isn't ideal, because the connected output supports a lesser or restricted
3320  * set of depths.  Resolve that here:
3321  *    LVDS typically supports only 6bpc, so clamp down in that case
3322  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3323  *    Displays may support a restricted set as well, check EDID and clamp as
3324  *      appropriate.
3325  *    DP may want to dither down to 6bpc to fit larger modes
3326  *
3327  * RETURNS:
3328  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3329  * true if they don't match).
3330  */
3331 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3332                                          unsigned int *pipe_bpp,
3333                                          struct drm_display_mode *mode)
3334 {
3335         struct drm_device *dev = crtc->dev;
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         struct drm_encoder *encoder;
3338         struct drm_connector *connector;
3339         unsigned int display_bpc = UINT_MAX, bpc;
3340
3341         /* Walk the encoders & connectors on this crtc, get min bpc */
3342         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3343                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3344
3345                 if (encoder->crtc != crtc)
3346                         continue;
3347
3348                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3349                         unsigned int lvds_bpc;
3350
3351                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3352                             LVDS_A3_POWER_UP)
3353                                 lvds_bpc = 8;
3354                         else
3355                                 lvds_bpc = 6;
3356
3357                         if (lvds_bpc < display_bpc) {
3358                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3359                                 display_bpc = lvds_bpc;
3360                         }
3361                         continue;
3362                 }
3363
3364                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3365                         /* Use VBT settings if we have an eDP panel */
3366                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3367
3368                         if (edp_bpc < display_bpc) {
3369                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3370                                 display_bpc = edp_bpc;
3371                         }
3372                         continue;
3373                 }
3374
3375                 /* Not one of the known troublemakers, check the EDID */
3376                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3377                                     head) {
3378                         if (connector->encoder != encoder)
3379                                 continue;
3380
3381                         /* Don't use an invalid EDID bpc value */
3382                         if (connector->display_info.bpc &&
3383                             connector->display_info.bpc < display_bpc) {
3384                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3385                                 display_bpc = connector->display_info.bpc;
3386                         }
3387                 }
3388
3389                 /*
3390                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3391                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3392                  */
3393                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3394                         if (display_bpc > 8 && display_bpc < 12) {
3395                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3396                                 display_bpc = 12;
3397                         } else {
3398                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3399                                 display_bpc = 8;
3400                         }
3401                 }
3402         }
3403
3404         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3405                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3406                 display_bpc = 6;
3407         }
3408
3409         /*
3410          * We could just drive the pipe at the highest bpc all the time and
3411          * enable dithering as needed, but that costs bandwidth.  So choose
3412          * the minimum value that expresses the full color range of the fb but
3413          * also stays within the max display bpc discovered above.
3414          */
3415
3416         switch (crtc->fb->depth) {
3417         case 8:
3418                 bpc = 8; /* since we go through a colormap */
3419                 break;
3420         case 15:
3421         case 16:
3422                 bpc = 6; /* min is 18bpp */
3423                 break;
3424         case 24:
3425                 bpc = 8;
3426                 break;
3427         case 30:
3428                 bpc = 10;
3429                 break;
3430         case 48:
3431                 bpc = 12;
3432                 break;
3433         default:
3434                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3435                 bpc = min((unsigned int)8, display_bpc);
3436                 break;
3437         }
3438
3439         display_bpc = min(display_bpc, bpc);
3440
3441         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3442                       bpc, display_bpc);
3443
3444         *pipe_bpp = display_bpc * 3;
3445
3446         return display_bpc != bpc;
3447 }
3448
3449 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         int refclk;
3454
3455         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3456             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3457                 refclk = dev_priv->lvds_ssc_freq * 1000;
3458                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3459                               refclk / 1000);
3460         } else if (!IS_GEN2(dev)) {
3461                 refclk = 96000;
3462         } else {
3463                 refclk = 48000;
3464         }
3465
3466         return refclk;
3467 }
3468
3469 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3470                                       intel_clock_t *clock)
3471 {
3472         /* SDVO TV has fixed PLL values depend on its clock range,
3473            this mirrors vbios setting. */
3474         if (adjusted_mode->clock >= 100000
3475             && adjusted_mode->clock < 140500) {
3476                 clock->p1 = 2;
3477                 clock->p2 = 10;
3478                 clock->n = 3;
3479                 clock->m1 = 16;
3480                 clock->m2 = 8;
3481         } else if (adjusted_mode->clock >= 140500
3482                    && adjusted_mode->clock <= 200000) {
3483                 clock->p1 = 1;
3484                 clock->p2 = 10;
3485                 clock->n = 6;
3486                 clock->m1 = 12;
3487                 clock->m2 = 8;
3488         }
3489 }
3490
3491 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3492                                      intel_clock_t *clock,
3493                                      intel_clock_t *reduced_clock)
3494 {
3495         struct drm_device *dev = crtc->dev;
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498         int pipe = intel_crtc->pipe;
3499         u32 fp, fp2 = 0;
3500
3501         if (IS_PINEVIEW(dev)) {
3502                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3503                 if (reduced_clock)
3504                         fp2 = (1 << reduced_clock->n) << 16 |
3505                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3506         } else {
3507                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3508                 if (reduced_clock)
3509                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3510                                 reduced_clock->m2;
3511         }
3512
3513         I915_WRITE(FP0(pipe), fp);
3514
3515         intel_crtc->lowfreq_avail = false;
3516         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3517             reduced_clock && i915_powersave) {
3518                 I915_WRITE(FP1(pipe), fp2);
3519                 intel_crtc->lowfreq_avail = true;
3520         } else {
3521                 I915_WRITE(FP1(pipe), fp);
3522         }
3523 }
3524
3525 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3526                               struct drm_display_mode *adjusted_mode)
3527 {
3528         struct drm_device *dev = crtc->dev;
3529         struct drm_i915_private *dev_priv = dev->dev_private;
3530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531         int pipe = intel_crtc->pipe;
3532         u32 temp;
3533
3534         temp = I915_READ(LVDS);
3535         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3536         if (pipe == 1) {
3537                 temp |= LVDS_PIPEB_SELECT;
3538         } else {
3539                 temp &= ~LVDS_PIPEB_SELECT;
3540         }
3541         /* set the corresponsding LVDS_BORDER bit */
3542         temp |= dev_priv->lvds_border_bits;
3543         /* Set the B0-B3 data pairs corresponding to whether we're going to
3544          * set the DPLLs for dual-channel mode or not.
3545          */
3546         if (clock->p2 == 7)
3547                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3548         else
3549                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3550
3551         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3552          * appropriately here, but we need to look more thoroughly into how
3553          * panels behave in the two modes.
3554          */
3555         /* set the dithering flag on LVDS as needed */
3556         if (INTEL_INFO(dev)->gen >= 4) {
3557                 if (dev_priv->lvds_dither)
3558                         temp |= LVDS_ENABLE_DITHER;
3559                 else
3560                         temp &= ~LVDS_ENABLE_DITHER;
3561         }
3562         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3563         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3564                 temp |= LVDS_HSYNC_POLARITY;
3565         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3566                 temp |= LVDS_VSYNC_POLARITY;
3567         I915_WRITE(LVDS, temp);
3568 }
3569
3570 static void i9xx_update_pll(struct drm_crtc *crtc,
3571                             struct drm_display_mode *mode,
3572                             struct drm_display_mode *adjusted_mode,
3573                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3574                             int num_connectors)
3575 {
3576         struct drm_device *dev = crtc->dev;
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3579         int pipe = intel_crtc->pipe;
3580         u32 dpll;
3581         bool is_sdvo;
3582
3583         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3584                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3585
3586         dpll = DPLL_VGA_MODE_DIS;
3587
3588         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3589                 dpll |= DPLLB_MODE_LVDS;
3590         else
3591                 dpll |= DPLLB_MODE_DAC_SERIAL;
3592         if (is_sdvo) {
3593                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3594                 if (pixel_multiplier > 1) {
3595                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3596                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3597                 }
3598                 dpll |= DPLL_DVO_HIGH_SPEED;
3599         }
3600         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3601                 dpll |= DPLL_DVO_HIGH_SPEED;
3602
3603         /* compute bitmask from p1 value */
3604         if (IS_PINEVIEW(dev))
3605                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3606         else {
3607                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3608                 if (IS_G4X(dev) && reduced_clock)
3609                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3610         }
3611         switch (clock->p2) {
3612         case 5:
3613                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3614                 break;
3615         case 7:
3616                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3617                 break;
3618         case 10:
3619                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3620                 break;
3621         case 14:
3622                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3623                 break;
3624         }
3625         if (INTEL_INFO(dev)->gen >= 4)
3626                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3627
3628         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3629                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3630         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3631                 /* XXX: just matching BIOS for now */
3632                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3633                 dpll |= 3;
3634         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3635                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3636                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3637         else
3638                 dpll |= PLL_REF_INPUT_DREFCLK;
3639
3640         dpll |= DPLL_VCO_ENABLE;
3641         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3642         POSTING_READ(DPLL(pipe));
3643         udelay(150);
3644
3645         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3646          * This is an exception to the general rule that mode_set doesn't turn
3647          * things on.
3648          */
3649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3650                 intel_update_lvds(crtc, clock, adjusted_mode);
3651
3652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3653                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3654
3655         I915_WRITE(DPLL(pipe), dpll);
3656
3657         /* Wait for the clocks to stabilize. */
3658         POSTING_READ(DPLL(pipe));
3659         udelay(150);
3660
3661         if (INTEL_INFO(dev)->gen >= 4) {
3662                 u32 temp = 0;
3663                 if (is_sdvo) {
3664                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3665                         if (temp > 1)
3666                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3667                         else
3668                                 temp = 0;
3669                 }
3670                 I915_WRITE(DPLL_MD(pipe), temp);
3671         } else {
3672                 /* The pixel multiplier can only be updated once the
3673                  * DPLL is enabled and the clocks are stable.
3674                  *
3675                  * So write it again.
3676                  */
3677                 I915_WRITE(DPLL(pipe), dpll);
3678         }
3679 }
3680
3681 static void i8xx_update_pll(struct drm_crtc *crtc,
3682                             struct drm_display_mode *adjusted_mode,
3683                             intel_clock_t *clock,
3684                             int num_connectors)
3685 {
3686         struct drm_device *dev = crtc->dev;
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689         int pipe = intel_crtc->pipe;
3690         u32 dpll;
3691
3692         dpll = DPLL_VGA_MODE_DIS;
3693
3694         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3695                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3696         } else {
3697                 if (clock->p1 == 2)
3698                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3699                 else
3700                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3701                 if (clock->p2 == 4)
3702                         dpll |= PLL_P2_DIVIDE_BY_4;
3703         }
3704
3705         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3706                 /* XXX: just matching BIOS for now */
3707                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3708                 dpll |= 3;
3709         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3710                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3711                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3712         else
3713                 dpll |= PLL_REF_INPUT_DREFCLK;
3714
3715         dpll |= DPLL_VCO_ENABLE;
3716         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3717         POSTING_READ(DPLL(pipe));
3718         udelay(150);
3719
3720         I915_WRITE(DPLL(pipe), dpll);
3721
3722         /* Wait for the clocks to stabilize. */
3723         POSTING_READ(DPLL(pipe));
3724         udelay(150);
3725
3726         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3727          * This is an exception to the general rule that mode_set doesn't turn
3728          * things on.
3729          */
3730         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3731                 intel_update_lvds(crtc, clock, adjusted_mode);
3732
3733         /* The pixel multiplier can only be updated once the
3734          * DPLL is enabled and the clocks are stable.
3735          *
3736          * So write it again.
3737          */
3738         I915_WRITE(DPLL(pipe), dpll);
3739 }
3740
3741 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3742                               struct drm_display_mode *mode,
3743                               struct drm_display_mode *adjusted_mode,
3744                               int x, int y,
3745                               struct drm_framebuffer *old_fb)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         int pipe = intel_crtc->pipe;
3751         int plane = intel_crtc->plane;
3752         int refclk, num_connectors = 0;
3753         intel_clock_t clock, reduced_clock;
3754         u32 dspcntr, pipeconf, vsyncshift;
3755         bool ok, has_reduced_clock = false, is_sdvo = false;
3756         bool is_lvds = false, is_tv = false, is_dp = false;
3757         struct drm_mode_config *mode_config = &dev->mode_config;
3758         struct intel_encoder *encoder;
3759         const intel_limit_t *limit;
3760         int ret;
3761
3762         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3763                 if (encoder->base.crtc != crtc)
3764                         continue;
3765
3766                 switch (encoder->type) {
3767                 case INTEL_OUTPUT_LVDS:
3768                         is_lvds = true;
3769                         break;
3770                 case INTEL_OUTPUT_SDVO:
3771                 case INTEL_OUTPUT_HDMI:
3772                         is_sdvo = true;
3773                         if (encoder->needs_tv_clock)
3774                                 is_tv = true;
3775                         break;
3776                 case INTEL_OUTPUT_TVOUT:
3777                         is_tv = true;
3778                         break;
3779                 case INTEL_OUTPUT_DISPLAYPORT:
3780                         is_dp = true;
3781                         break;
3782                 }
3783
3784                 num_connectors++;
3785         }
3786
3787         refclk = i9xx_get_refclk(crtc, num_connectors);
3788
3789         /*
3790          * Returns a set of divisors for the desired target clock with the given
3791          * refclk, or FALSE.  The returned values represent the clock equation:
3792          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3793          */
3794         limit = intel_limit(crtc, refclk);
3795         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3796                              &clock);
3797         if (!ok) {
3798                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3799                 return -EINVAL;
3800         }
3801
3802         /* Ensure that the cursor is valid for the new mode before changing... */
3803         intel_crtc_update_cursor(crtc, true);
3804
3805         if (is_lvds && dev_priv->lvds_downclock_avail) {
3806                 /*
3807                  * Ensure we match the reduced clock's P to the target clock.
3808                  * If the clocks don't match, we can't switch the display clock
3809                  * by using the FP0/FP1. In such case we will disable the LVDS
3810                  * downclock feature.
3811                 */
3812                 has_reduced_clock = limit->find_pll(limit, crtc,
3813                                                     dev_priv->lvds_downclock,
3814                                                     refclk,
3815                                                     &clock,
3816                                                     &reduced_clock);
3817         }
3818
3819         if (is_sdvo && is_tv)
3820                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3821
3822         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3823                                  &reduced_clock : NULL);
3824
3825         if (IS_GEN2(dev))
3826                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3827         else
3828                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3829                                 has_reduced_clock ? &reduced_clock : NULL,
3830                                 num_connectors);
3831
3832         /* setup pipeconf */
3833         pipeconf = I915_READ(PIPECONF(pipe));
3834
3835         /* Set up the display plane register */
3836         dspcntr = DISPPLANE_GAMMA_ENABLE;
3837
3838         if (pipe == 0)
3839                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3840         else
3841                 dspcntr |= DISPPLANE_SEL_PIPE_B;
3842
3843         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3844                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3845                  * core speed.
3846                  *
3847                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3848                  * pipe == 0 check?
3849                  */
3850                 if (mode->clock >
3851                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3852                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3853                 else
3854                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3855         }
3856
3857         /* default to 8bpc */
3858         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3859         if (is_dp) {
3860                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3861                         pipeconf |= PIPECONF_BPP_6 |
3862                                     PIPECONF_DITHER_EN |
3863                                     PIPECONF_DITHER_TYPE_SP;
3864                 }
3865         }
3866
3867         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3868         drm_mode_debug_printmodeline(mode);
3869
3870         if (HAS_PIPE_CXSR(dev)) {
3871                 if (intel_crtc->lowfreq_avail) {
3872                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3873                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3874                 } else {
3875                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3876                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3877                 }
3878         }
3879
3880         pipeconf &= ~PIPECONF_INTERLACE_MASK;
3881         if (!IS_GEN2(dev) &&
3882             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3883                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3884                 /* the chip adds 2 halflines automatically */
3885                 adjusted_mode->crtc_vtotal -= 1;
3886                 adjusted_mode->crtc_vblank_end -= 1;
3887                 vsyncshift = adjusted_mode->crtc_hsync_start
3888                              - adjusted_mode->crtc_htotal/2;
3889         } else {
3890                 pipeconf |= PIPECONF_PROGRESSIVE;
3891                 vsyncshift = 0;
3892         }
3893
3894         if (!IS_GEN3(dev))
3895                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3896
3897         I915_WRITE(HTOTAL(pipe),
3898                    (adjusted_mode->crtc_hdisplay - 1) |
3899                    ((adjusted_mode->crtc_htotal - 1) << 16));
3900         I915_WRITE(HBLANK(pipe),
3901                    (adjusted_mode->crtc_hblank_start - 1) |
3902                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3903         I915_WRITE(HSYNC(pipe),
3904                    (adjusted_mode->crtc_hsync_start - 1) |
3905                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3906
3907         I915_WRITE(VTOTAL(pipe),
3908                    (adjusted_mode->crtc_vdisplay - 1) |
3909                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3910         I915_WRITE(VBLANK(pipe),
3911                    (adjusted_mode->crtc_vblank_start - 1) |
3912                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3913         I915_WRITE(VSYNC(pipe),
3914                    (adjusted_mode->crtc_vsync_start - 1) |
3915                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3916
3917         /* pipesrc and dspsize control the size that is scaled from,
3918          * which should always be the user's requested size.
3919          */
3920         I915_WRITE(DSPSIZE(plane),
3921                    ((mode->vdisplay - 1) << 16) |
3922                    (mode->hdisplay - 1));
3923         I915_WRITE(DSPPOS(plane), 0);
3924         I915_WRITE(PIPESRC(pipe),
3925                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3926
3927         I915_WRITE(PIPECONF(pipe), pipeconf);
3928         POSTING_READ(PIPECONF(pipe));
3929         intel_enable_pipe(dev_priv, pipe, false);
3930
3931         intel_wait_for_vblank(dev, pipe);
3932
3933         I915_WRITE(DSPCNTR(plane), dspcntr);
3934         POSTING_READ(DSPCNTR(plane));
3935
3936         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3937
3938         intel_update_watermarks(dev);
3939
3940         return ret;
3941 }
3942
3943 /*
3944  * Initialize reference clocks when the driver loads
3945  */
3946 void ironlake_init_pch_refclk(struct drm_device *dev)
3947 {
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         struct drm_mode_config *mode_config = &dev->mode_config;
3950         struct intel_encoder *encoder;
3951         u32 temp;
3952         bool has_lvds = false;
3953         bool has_cpu_edp = false;
3954         bool has_pch_edp = false;
3955         bool has_panel = false;
3956         bool has_ck505 = false;
3957         bool can_ssc = false;
3958
3959         /* We need to take the global config into account */
3960         list_for_each_entry(encoder, &mode_config->encoder_list,
3961                             base.head) {
3962                 switch (encoder->type) {
3963                 case INTEL_OUTPUT_LVDS:
3964                         has_panel = true;
3965                         has_lvds = true;
3966                         break;
3967                 case INTEL_OUTPUT_EDP:
3968                         has_panel = true;
3969                         if (intel_encoder_is_pch_edp(&encoder->base))
3970                                 has_pch_edp = true;
3971                         else
3972                                 has_cpu_edp = true;
3973                         break;
3974                 }
3975         }
3976
3977         if (HAS_PCH_IBX(dev)) {
3978                 has_ck505 = dev_priv->display_clock_mode;
3979                 can_ssc = has_ck505;
3980         } else {
3981                 has_ck505 = false;
3982                 can_ssc = true;
3983         }
3984
3985         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3986                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3987                       has_ck505);
3988
3989         /* Ironlake: try to setup display ref clock before DPLL
3990          * enabling. This is only under driver's control after
3991          * PCH B stepping, previous chipset stepping should be
3992          * ignoring this setting.
3993          */
3994         temp = I915_READ(PCH_DREF_CONTROL);
3995         /* Always enable nonspread source */
3996         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3997
3998         if (has_ck505)
3999                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4000         else
4001                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4002
4003         if (has_panel) {
4004                 temp &= ~DREF_SSC_SOURCE_MASK;
4005                 temp |= DREF_SSC_SOURCE_ENABLE;
4006
4007                 /* SSC must be turned on before enabling the CPU output  */
4008                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4009                         DRM_DEBUG_KMS("Using SSC on panel\n");
4010                         temp |= DREF_SSC1_ENABLE;
4011                 } else
4012                         temp &= ~DREF_SSC1_ENABLE;
4013
4014                 /* Get SSC going before enabling the outputs */
4015                 I915_WRITE(PCH_DREF_CONTROL, temp);
4016                 POSTING_READ(PCH_DREF_CONTROL);
4017                 udelay(200);
4018
4019                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4020
4021                 /* Enable CPU source on CPU attached eDP */
4022                 if (has_cpu_edp) {
4023                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4024                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4025                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4026                         }
4027                         else
4028                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4029                 } else
4030                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4031
4032                 I915_WRITE(PCH_DREF_CONTROL, temp);
4033                 POSTING_READ(PCH_DREF_CONTROL);
4034                 udelay(200);
4035         } else {
4036                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4037
4038                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4039
4040                 /* Turn off CPU output */
4041                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4042
4043                 I915_WRITE(PCH_DREF_CONTROL, temp);
4044                 POSTING_READ(PCH_DREF_CONTROL);
4045                 udelay(200);
4046
4047                 /* Turn off the SSC source */
4048                 temp &= ~DREF_SSC_SOURCE_MASK;
4049                 temp |= DREF_SSC_SOURCE_DISABLE;
4050
4051                 /* Turn off SSC1 */
4052                 temp &= ~ DREF_SSC1_ENABLE;
4053
4054                 I915_WRITE(PCH_DREF_CONTROL, temp);
4055                 POSTING_READ(PCH_DREF_CONTROL);
4056                 udelay(200);
4057         }
4058 }
4059
4060 static int ironlake_get_refclk(struct drm_crtc *crtc)
4061 {
4062         struct drm_device *dev = crtc->dev;
4063         struct drm_i915_private *dev_priv = dev->dev_private;
4064         struct intel_encoder *encoder;
4065         struct drm_mode_config *mode_config = &dev->mode_config;
4066         struct intel_encoder *edp_encoder = NULL;
4067         int num_connectors = 0;
4068         bool is_lvds = false;
4069
4070         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4071                 if (encoder->base.crtc != crtc)
4072                         continue;
4073
4074                 switch (encoder->type) {
4075                 case INTEL_OUTPUT_LVDS:
4076                         is_lvds = true;
4077                         break;
4078                 case INTEL_OUTPUT_EDP:
4079                         edp_encoder = encoder;
4080                         break;
4081                 }
4082                 num_connectors++;
4083         }
4084
4085         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4086                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4087                               dev_priv->lvds_ssc_freq);
4088                 return dev_priv->lvds_ssc_freq * 1000;
4089         }
4090
4091         return 120000;
4092 }
4093
4094 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4095                                   struct drm_display_mode *mode,
4096                                   struct drm_display_mode *adjusted_mode,
4097                                   int x, int y,
4098                                   struct drm_framebuffer *old_fb)
4099 {
4100         struct drm_device *dev = crtc->dev;
4101         struct drm_i915_private *dev_priv = dev->dev_private;
4102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103         int pipe = intel_crtc->pipe;
4104         int plane = intel_crtc->plane;
4105         int refclk, num_connectors = 0;
4106         intel_clock_t clock, reduced_clock;
4107         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4108         bool ok, has_reduced_clock = false, is_sdvo = false;
4109         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4110         struct drm_mode_config *mode_config = &dev->mode_config;
4111         struct intel_encoder *encoder, *edp_encoder = NULL;
4112         const intel_limit_t *limit;
4113         int ret;
4114         struct fdi_m_n m_n = {0};
4115         u32 temp;
4116         int target_clock, pixel_multiplier, lane, link_bw, factor;
4117         unsigned int pipe_bpp;
4118         bool dither;
4119         bool is_cpu_edp = false, is_pch_edp = false;
4120
4121         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4122                 if (encoder->base.crtc != crtc)
4123                         continue;
4124
4125                 switch (encoder->type) {
4126                 case INTEL_OUTPUT_LVDS:
4127                         is_lvds = true;
4128                         break;
4129                 case INTEL_OUTPUT_SDVO:
4130                 case INTEL_OUTPUT_HDMI:
4131                         is_sdvo = true;
4132                         if (encoder->needs_tv_clock)
4133                                 is_tv = true;
4134                         break;
4135                 case INTEL_OUTPUT_TVOUT:
4136                         is_tv = true;
4137                         break;
4138                 case INTEL_OUTPUT_ANALOG:
4139                         is_crt = true;
4140                         break;
4141                 case INTEL_OUTPUT_DISPLAYPORT:
4142                         is_dp = true;
4143                         break;
4144                 case INTEL_OUTPUT_EDP:
4145                         is_dp = true;
4146                         if (intel_encoder_is_pch_edp(&encoder->base))
4147                                 is_pch_edp = true;
4148                         else
4149                                 is_cpu_edp = true;
4150                         edp_encoder = encoder;
4151                         break;
4152                 }
4153
4154                 num_connectors++;
4155         }
4156
4157         refclk = ironlake_get_refclk(crtc);
4158
4159         /*
4160          * Returns a set of divisors for the desired target clock with the given
4161          * refclk, or FALSE.  The returned values represent the clock equation:
4162          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4163          */
4164         limit = intel_limit(crtc, refclk);
4165         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4166                              &clock);
4167         if (!ok) {
4168                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4169                 return -EINVAL;
4170         }
4171
4172         /* Ensure that the cursor is valid for the new mode before changing... */
4173         intel_crtc_update_cursor(crtc, true);
4174
4175         if (is_lvds && dev_priv->lvds_downclock_avail) {
4176                 /*
4177                  * Ensure we match the reduced clock's P to the target clock.
4178                  * If the clocks don't match, we can't switch the display clock
4179                  * by using the FP0/FP1. In such case we will disable the LVDS
4180                  * downclock feature.
4181                 */
4182                 has_reduced_clock = limit->find_pll(limit, crtc,
4183                                                     dev_priv->lvds_downclock,
4184                                                     refclk,
4185                                                     &clock,
4186                                                     &reduced_clock);
4187         }
4188         /* SDVO TV has fixed PLL values depend on its clock range,
4189            this mirrors vbios setting. */
4190         if (is_sdvo && is_tv) {
4191                 if (adjusted_mode->clock >= 100000
4192                     && adjusted_mode->clock < 140500) {
4193                         clock.p1 = 2;
4194                         clock.p2 = 10;
4195                         clock.n = 3;
4196                         clock.m1 = 16;
4197                         clock.m2 = 8;
4198                 } else if (adjusted_mode->clock >= 140500
4199                            && adjusted_mode->clock <= 200000) {
4200                         clock.p1 = 1;
4201                         clock.p2 = 10;
4202                         clock.n = 6;
4203                         clock.m1 = 12;
4204                         clock.m2 = 8;
4205                 }
4206         }
4207
4208         /* FDI link */
4209         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4210         lane = 0;
4211         /* CPU eDP doesn't require FDI link, so just set DP M/N
4212            according to current link config */
4213         if (is_cpu_edp) {
4214                 target_clock = mode->clock;
4215                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4216         } else {
4217                 /* [e]DP over FDI requires target mode clock
4218                    instead of link clock */
4219                 if (is_dp)
4220                         target_clock = mode->clock;
4221                 else
4222                         target_clock = adjusted_mode->clock;
4223
4224                 /* FDI is a binary signal running at ~2.7GHz, encoding
4225                  * each output octet as 10 bits. The actual frequency
4226                  * is stored as a divider into a 100MHz clock, and the
4227                  * mode pixel clock is stored in units of 1KHz.
4228                  * Hence the bw of each lane in terms of the mode signal
4229                  * is:
4230                  */
4231                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4232         }
4233
4234         /* determine panel color depth */
4235         temp = I915_READ(PIPECONF(pipe));
4236         temp &= ~PIPE_BPC_MASK;
4237         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4238         switch (pipe_bpp) {
4239         case 18:
4240                 temp |= PIPE_6BPC;
4241                 break;
4242         case 24:
4243                 temp |= PIPE_8BPC;
4244                 break;
4245         case 30:
4246                 temp |= PIPE_10BPC;
4247                 break;
4248         case 36:
4249                 temp |= PIPE_12BPC;
4250                 break;
4251         default:
4252                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4253                         pipe_bpp);
4254                 temp |= PIPE_8BPC;
4255                 pipe_bpp = 24;
4256                 break;
4257         }
4258
4259         intel_crtc->bpp = pipe_bpp;
4260         I915_WRITE(PIPECONF(pipe), temp);
4261
4262         if (!lane) {
4263                 /*
4264                  * Account for spread spectrum to avoid
4265                  * oversubscribing the link. Max center spread
4266                  * is 2.5%; use 5% for safety's sake.
4267                  */
4268                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4269                 lane = bps / (link_bw * 8) + 1;
4270         }
4271
4272         intel_crtc->fdi_lanes = lane;
4273
4274         if (pixel_multiplier > 1)
4275                 link_bw *= pixel_multiplier;
4276         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4277                              &m_n);
4278
4279         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4280         if (has_reduced_clock)
4281                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4282                         reduced_clock.m2;
4283
4284         /* Enable autotuning of the PLL clock (if permissible) */
4285         factor = 21;
4286         if (is_lvds) {
4287                 if ((intel_panel_use_ssc(dev_priv) &&
4288                      dev_priv->lvds_ssc_freq == 100) ||
4289                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4290                         factor = 25;
4291         } else if (is_sdvo && is_tv)
4292                 factor = 20;
4293
4294         if (clock.m < factor * clock.n)
4295                 fp |= FP_CB_TUNE;
4296
4297         dpll = 0;
4298
4299         if (is_lvds)
4300                 dpll |= DPLLB_MODE_LVDS;
4301         else
4302                 dpll |= DPLLB_MODE_DAC_SERIAL;
4303         if (is_sdvo) {
4304                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4305                 if (pixel_multiplier > 1) {
4306                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4307                 }
4308                 dpll |= DPLL_DVO_HIGH_SPEED;
4309         }
4310         if (is_dp && !is_cpu_edp)
4311                 dpll |= DPLL_DVO_HIGH_SPEED;
4312
4313         /* compute bitmask from p1 value */
4314         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4315         /* also FPA1 */
4316         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4317
4318         switch (clock.p2) {
4319         case 5:
4320                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4321                 break;
4322         case 7:
4323                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4324                 break;
4325         case 10:
4326                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4327                 break;
4328         case 14:
4329                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4330                 break;
4331         }
4332
4333         if (is_sdvo && is_tv)
4334                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4335         else if (is_tv)
4336                 /* XXX: just matching BIOS for now */
4337                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4338                 dpll |= 3;
4339         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4340                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4341         else
4342                 dpll |= PLL_REF_INPUT_DREFCLK;
4343
4344         /* setup pipeconf */
4345         pipeconf = I915_READ(PIPECONF(pipe));
4346
4347         /* Set up the display plane register */
4348         dspcntr = DISPPLANE_GAMMA_ENABLE;
4349
4350         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4351         drm_mode_debug_printmodeline(mode);
4352
4353         /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4354         if (!is_cpu_edp) {
4355                 struct intel_pch_pll *pll;
4356
4357                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4358                 if (pll == NULL) {
4359                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4360                                          pipe);
4361                         return -EINVAL;
4362                 }
4363         } else
4364                 intel_put_pch_pll(intel_crtc);
4365
4366         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4367          * This is an exception to the general rule that mode_set doesn't turn
4368          * things on.
4369          */
4370         if (is_lvds) {
4371                 temp = I915_READ(PCH_LVDS);
4372                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4373                 if (HAS_PCH_CPT(dev)) {
4374                         temp &= ~PORT_TRANS_SEL_MASK;
4375                         temp |= PORT_TRANS_SEL_CPT(pipe);
4376                 } else {
4377                         if (pipe == 1)
4378                                 temp |= LVDS_PIPEB_SELECT;
4379                         else
4380                                 temp &= ~LVDS_PIPEB_SELECT;
4381                 }
4382
4383                 /* set the corresponsding LVDS_BORDER bit */
4384                 temp |= dev_priv->lvds_border_bits;
4385                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4386                  * set the DPLLs for dual-channel mode or not.
4387                  */
4388                 if (clock.p2 == 7)
4389                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4390                 else
4391                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4392
4393                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4394                  * appropriately here, but we need to look more thoroughly into how
4395                  * panels behave in the two modes.
4396                  */
4397                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4398                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4399                         temp |= LVDS_HSYNC_POLARITY;
4400                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4401                         temp |= LVDS_VSYNC_POLARITY;
4402                 I915_WRITE(PCH_LVDS, temp);
4403         }
4404
4405         pipeconf &= ~PIPECONF_DITHER_EN;
4406         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4407         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4408                 pipeconf |= PIPECONF_DITHER_EN;
4409                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4410         }
4411         if (is_dp && !is_cpu_edp) {
4412                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4413         } else {
4414                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4415                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4416                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4417                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4418                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4419         }
4420
4421         if (intel_crtc->pch_pll) {
4422                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4423
4424                 /* Wait for the clocks to stabilize. */
4425                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4426                 udelay(150);
4427
4428                 /* The pixel multiplier can only be updated once the
4429                  * DPLL is enabled and the clocks are stable.
4430                  *
4431                  * So write it again.
4432                  */
4433                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4434         }
4435
4436         intel_crtc->lowfreq_avail = false;
4437         if (intel_crtc->pch_pll) {
4438                 if (is_lvds && has_reduced_clock && i915_powersave) {
4439                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4440                         intel_crtc->lowfreq_avail = true;
4441                         if (HAS_PIPE_CXSR(dev)) {
4442                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4443                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4444                         }
4445                 } else {
4446                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4447                         if (HAS_PIPE_CXSR(dev)) {
4448                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4449                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4450                         }
4451                 }
4452         }
4453
4454         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4455         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4456                 pipeconf |= PIPECONF_INTERLACED_ILK;
4457                 /* the chip adds 2 halflines automatically */
4458                 adjusted_mode->crtc_vtotal -= 1;
4459                 adjusted_mode->crtc_vblank_end -= 1;
4460                 I915_WRITE(VSYNCSHIFT(pipe),
4461                            adjusted_mode->crtc_hsync_start
4462                            - adjusted_mode->crtc_htotal/2);
4463         } else {
4464                 pipeconf |= PIPECONF_PROGRESSIVE;
4465                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4466         }
4467
4468         I915_WRITE(HTOTAL(pipe),
4469                    (adjusted_mode->crtc_hdisplay - 1) |
4470                    ((adjusted_mode->crtc_htotal - 1) << 16));
4471         I915_WRITE(HBLANK(pipe),
4472                    (adjusted_mode->crtc_hblank_start - 1) |
4473                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4474         I915_WRITE(HSYNC(pipe),
4475                    (adjusted_mode->crtc_hsync_start - 1) |
4476                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4477
4478         I915_WRITE(VTOTAL(pipe),
4479                    (adjusted_mode->crtc_vdisplay - 1) |
4480                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4481         I915_WRITE(VBLANK(pipe),
4482                    (adjusted_mode->crtc_vblank_start - 1) |
4483                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4484         I915_WRITE(VSYNC(pipe),
4485                    (adjusted_mode->crtc_vsync_start - 1) |
4486                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4487
4488         /* pipesrc controls the size that is scaled from, which should
4489          * always be the user's requested size.
4490          */
4491         I915_WRITE(PIPESRC(pipe),
4492                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4493
4494         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4495         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4496         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4497         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4498
4499         if (is_cpu_edp)
4500                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4501
4502         I915_WRITE(PIPECONF(pipe), pipeconf);
4503         POSTING_READ(PIPECONF(pipe));
4504
4505         intel_wait_for_vblank(dev, pipe);
4506
4507         I915_WRITE(DSPCNTR(plane), dspcntr);
4508         POSTING_READ(DSPCNTR(plane));
4509
4510         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4511
4512         intel_update_watermarks(dev);
4513
4514         return ret;
4515 }
4516
4517 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4518                                struct drm_display_mode *mode,
4519                                struct drm_display_mode *adjusted_mode,
4520                                int x, int y,
4521                                struct drm_framebuffer *old_fb)
4522 {
4523         struct drm_device *dev = crtc->dev;
4524         struct drm_i915_private *dev_priv = dev->dev_private;
4525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4526         int pipe = intel_crtc->pipe;
4527         int ret;
4528
4529         drm_vblank_pre_modeset(dev, pipe);
4530
4531         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4532                                               x, y, old_fb);
4533         drm_vblank_post_modeset(dev, pipe);
4534
4535         if (ret)
4536                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4537         else
4538                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4539
4540         return ret;
4541 }
4542
4543 static bool intel_eld_uptodate(struct drm_connector *connector,
4544                                int reg_eldv, uint32_t bits_eldv,
4545                                int reg_elda, uint32_t bits_elda,
4546                                int reg_edid)
4547 {
4548         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4549         uint8_t *eld = connector->eld;
4550         uint32_t i;
4551
4552         i = I915_READ(reg_eldv);
4553         i &= bits_eldv;
4554
4555         if (!eld[0])
4556                 return !i;
4557
4558         if (!i)
4559                 return false;
4560
4561         i = I915_READ(reg_elda);
4562         i &= ~bits_elda;
4563         I915_WRITE(reg_elda, i);
4564
4565         for (i = 0; i < eld[2]; i++)
4566                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4567                         return false;
4568
4569         return true;
4570 }
4571
4572 static void g4x_write_eld(struct drm_connector *connector,
4573                           struct drm_crtc *crtc)
4574 {
4575         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4576         uint8_t *eld = connector->eld;
4577         uint32_t eldv;
4578         uint32_t len;
4579         uint32_t i;
4580
4581         i = I915_READ(G4X_AUD_VID_DID);
4582
4583         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4584                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4585         else
4586                 eldv = G4X_ELDV_DEVCTG;
4587
4588         if (intel_eld_uptodate(connector,
4589                                G4X_AUD_CNTL_ST, eldv,
4590                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4591                                G4X_HDMIW_HDMIEDID))
4592                 return;
4593
4594         i = I915_READ(G4X_AUD_CNTL_ST);
4595         i &= ~(eldv | G4X_ELD_ADDR);
4596         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4597         I915_WRITE(G4X_AUD_CNTL_ST, i);
4598
4599         if (!eld[0])
4600                 return;
4601
4602         len = min_t(uint8_t, eld[2], len);
4603         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4604         for (i = 0; i < len; i++)
4605                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4606
4607         i = I915_READ(G4X_AUD_CNTL_ST);
4608         i |= eldv;
4609         I915_WRITE(G4X_AUD_CNTL_ST, i);
4610 }
4611
4612 static void ironlake_write_eld(struct drm_connector *connector,
4613                                      struct drm_crtc *crtc)
4614 {
4615         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4616         uint8_t *eld = connector->eld;
4617         uint32_t eldv;
4618         uint32_t i;
4619         int len;
4620         int hdmiw_hdmiedid;
4621         int aud_config;
4622         int aud_cntl_st;
4623         int aud_cntrl_st2;
4624
4625         if (HAS_PCH_IBX(connector->dev)) {
4626                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4627                 aud_config = IBX_AUD_CONFIG_A;
4628                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4629                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4630         } else {
4631                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4632                 aud_config = CPT_AUD_CONFIG_A;
4633                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4634                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4635         }
4636
4637         i = to_intel_crtc(crtc)->pipe;
4638         hdmiw_hdmiedid += i * 0x100;
4639         aud_cntl_st += i * 0x100;
4640         aud_config += i * 0x100;
4641
4642         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4643
4644         i = I915_READ(aud_cntl_st);
4645         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4646         if (!i) {
4647                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4648                 /* operate blindly on all ports */
4649                 eldv = IBX_ELD_VALIDB;
4650                 eldv |= IBX_ELD_VALIDB << 4;
4651                 eldv |= IBX_ELD_VALIDB << 8;
4652         } else {
4653                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4654                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4655         }
4656
4657         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4658                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4659                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4660                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4661         } else
4662                 I915_WRITE(aud_config, 0);
4663
4664         if (intel_eld_uptodate(connector,
4665                                aud_cntrl_st2, eldv,
4666                                aud_cntl_st, IBX_ELD_ADDRESS,
4667                                hdmiw_hdmiedid))
4668                 return;
4669
4670         i = I915_READ(aud_cntrl_st2);
4671         i &= ~eldv;
4672         I915_WRITE(aud_cntrl_st2, i);
4673
4674         if (!eld[0])
4675                 return;
4676
4677         i = I915_READ(aud_cntl_st);
4678         i &= ~IBX_ELD_ADDRESS;
4679         I915_WRITE(aud_cntl_st, i);
4680
4681         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
4682         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4683         for (i = 0; i < len; i++)
4684                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4685
4686         i = I915_READ(aud_cntrl_st2);
4687         i |= eldv;
4688         I915_WRITE(aud_cntrl_st2, i);
4689 }
4690
4691 void intel_write_eld(struct drm_encoder *encoder,
4692                      struct drm_display_mode *mode)
4693 {
4694         struct drm_crtc *crtc = encoder->crtc;
4695         struct drm_connector *connector;
4696         struct drm_device *dev = encoder->dev;
4697         struct drm_i915_private *dev_priv = dev->dev_private;
4698
4699         connector = drm_select_eld(encoder, mode);
4700         if (!connector)
4701                 return;
4702
4703         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4704                          connector->base.id,
4705                          drm_get_connector_name(connector),
4706                          connector->encoder->base.id,
4707                          drm_get_encoder_name(connector->encoder));
4708
4709         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4710
4711         if (dev_priv->display.write_eld)
4712                 dev_priv->display.write_eld(connector, crtc);
4713 }
4714
4715 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4716 void intel_crtc_load_lut(struct drm_crtc *crtc)
4717 {
4718         struct drm_device *dev = crtc->dev;
4719         struct drm_i915_private *dev_priv = dev->dev_private;
4720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4721         int palreg = PALETTE(intel_crtc->pipe);
4722         int i;
4723
4724         /* The clocks have to be on to load the palette. */
4725         if (!crtc->enabled || !intel_crtc->active)
4726                 return;
4727
4728         /* use legacy palette for Ironlake */
4729         if (HAS_PCH_SPLIT(dev))
4730                 palreg = LGC_PALETTE(intel_crtc->pipe);
4731
4732         for (i = 0; i < 256; i++) {
4733                 I915_WRITE(palreg + 4 * i,
4734                            (intel_crtc->lut_r[i] << 16) |
4735                            (intel_crtc->lut_g[i] << 8) |
4736                            intel_crtc->lut_b[i]);
4737         }
4738 }
4739
4740 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4741 {
4742         struct drm_device *dev = crtc->dev;
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4745         bool visible = base != 0;
4746         u32 cntl;
4747
4748         if (intel_crtc->cursor_visible == visible)
4749                 return;
4750
4751         cntl = I915_READ(_CURACNTR);
4752         if (visible) {
4753                 /* On these chipsets we can only modify the base whilst
4754                  * the cursor is disabled.
4755                  */
4756                 I915_WRITE(_CURABASE, base);
4757
4758                 cntl &= ~(CURSOR_FORMAT_MASK);
4759                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4760                 cntl |= CURSOR_ENABLE |
4761                         CURSOR_GAMMA_ENABLE |
4762                         CURSOR_FORMAT_ARGB;
4763         } else
4764                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4765         I915_WRITE(_CURACNTR, cntl);
4766
4767         intel_crtc->cursor_visible = visible;
4768 }
4769
4770 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4771 {
4772         struct drm_device *dev = crtc->dev;
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775         int pipe = intel_crtc->pipe;
4776         bool visible = base != 0;
4777
4778         if (intel_crtc->cursor_visible != visible) {
4779                 uint32_t cntl = I915_READ(CURCNTR(pipe));
4780                 if (base) {
4781                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4782                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4783                         cntl |= pipe << 28; /* Connect to correct pipe */
4784                 } else {
4785                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4786                         cntl |= CURSOR_MODE_DISABLE;
4787                 }
4788                 I915_WRITE(CURCNTR(pipe), cntl);
4789
4790                 intel_crtc->cursor_visible = visible;
4791         }
4792         /* and commit changes on next vblank */
4793         I915_WRITE(CURBASE(pipe), base);
4794 }
4795
4796 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4797 {
4798         struct drm_device *dev = crtc->dev;
4799         struct drm_i915_private *dev_priv = dev->dev_private;
4800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4801         int pipe = intel_crtc->pipe;
4802         bool visible = base != 0;
4803
4804         if (intel_crtc->cursor_visible != visible) {
4805                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4806                 if (base) {
4807                         cntl &= ~CURSOR_MODE;
4808                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4809                 } else {
4810                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4811                         cntl |= CURSOR_MODE_DISABLE;
4812                 }
4813                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4814
4815                 intel_crtc->cursor_visible = visible;
4816         }
4817         /* and commit changes on next vblank */
4818         I915_WRITE(CURBASE_IVB(pipe), base);
4819 }
4820
4821 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4822 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4823                                      bool on)
4824 {
4825         struct drm_device *dev = crtc->dev;
4826         struct drm_i915_private *dev_priv = dev->dev_private;
4827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4828         int pipe = intel_crtc->pipe;
4829         int x = intel_crtc->cursor_x;
4830         int y = intel_crtc->cursor_y;
4831         u32 base, pos;
4832         bool visible;
4833
4834         pos = 0;
4835
4836         if (on && crtc->enabled && crtc->fb) {
4837                 base = intel_crtc->cursor_addr;
4838                 if (x > (int) crtc->fb->width)
4839                         base = 0;
4840
4841                 if (y > (int) crtc->fb->height)
4842                         base = 0;
4843         } else
4844                 base = 0;
4845
4846         if (x < 0) {
4847                 if (x + intel_crtc->cursor_width < 0)
4848                         base = 0;
4849
4850                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4851                 x = -x;
4852         }
4853         pos |= x << CURSOR_X_SHIFT;
4854
4855         if (y < 0) {
4856                 if (y + intel_crtc->cursor_height < 0)
4857                         base = 0;
4858
4859                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4860                 y = -y;
4861         }
4862         pos |= y << CURSOR_Y_SHIFT;
4863
4864         visible = base != 0;
4865         if (!visible && !intel_crtc->cursor_visible)
4866                 return;
4867
4868         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4869                 I915_WRITE(CURPOS_IVB(pipe), pos);
4870                 ivb_update_cursor(crtc, base);
4871         } else {
4872                 I915_WRITE(CURPOS(pipe), pos);
4873                 if (IS_845G(dev) || IS_I865G(dev))
4874                         i845_update_cursor(crtc, base);
4875                 else
4876                         i9xx_update_cursor(crtc, base);
4877         }
4878
4879         if (visible)
4880                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4881 }
4882
4883 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4884                                  struct drm_file *file,
4885                                  uint32_t handle,
4886                                  uint32_t width, uint32_t height)
4887 {
4888         struct drm_device *dev = crtc->dev;
4889         struct drm_i915_private *dev_priv = dev->dev_private;
4890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891         struct drm_i915_gem_object *obj;
4892         uint32_t addr;
4893         int ret;
4894
4895         DRM_DEBUG_KMS("\n");
4896
4897         /* if we want to turn off the cursor ignore width and height */
4898         if (!handle) {
4899                 DRM_DEBUG_KMS("cursor off\n");
4900                 addr = 0;
4901                 obj = NULL;
4902                 mutex_lock(&dev->struct_mutex);
4903                 goto finish;
4904         }
4905
4906         /* Currently we only support 64x64 cursors */
4907         if (width != 64 || height != 64) {
4908                 DRM_ERROR("we currently only support 64x64 cursors\n");
4909                 return -EINVAL;
4910         }
4911
4912         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4913         if (&obj->base == NULL)
4914                 return -ENOENT;
4915
4916         if (obj->base.size < width * height * 4) {
4917                 DRM_ERROR("buffer is to small\n");
4918                 ret = -ENOMEM;
4919                 goto fail;
4920         }
4921
4922         /* we only need to pin inside GTT if cursor is non-phy */
4923         mutex_lock(&dev->struct_mutex);
4924         if (!dev_priv->info->cursor_needs_physical) {
4925                 if (obj->tiling_mode) {
4926                         DRM_ERROR("cursor cannot be tiled\n");
4927                         ret = -EINVAL;
4928                         goto fail_locked;
4929                 }
4930
4931                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4932                 if (ret) {
4933                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4934                         goto fail_locked;
4935                 }
4936
4937                 ret = i915_gem_object_put_fence(obj);
4938                 if (ret) {
4939                         DRM_ERROR("failed to release fence for cursor");
4940                         goto fail_unpin;
4941                 }
4942
4943                 addr = obj->gtt_offset;
4944         } else {
4945                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4946                 ret = i915_gem_attach_phys_object(dev, obj,
4947                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4948                                                   align);
4949                 if (ret) {
4950                         DRM_ERROR("failed to attach phys object\n");
4951                         goto fail_locked;
4952                 }
4953                 addr = obj->phys_obj->handle->busaddr;
4954         }
4955
4956         if (IS_GEN2(dev))
4957                 I915_WRITE(CURSIZE, (height << 12) | width);
4958
4959  finish:
4960         if (intel_crtc->cursor_bo) {
4961                 if (dev_priv->info->cursor_needs_physical) {
4962                         if (intel_crtc->cursor_bo != obj)
4963                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4964                 } else
4965                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4966                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4967         }
4968
4969         mutex_unlock(&dev->struct_mutex);
4970
4971         intel_crtc->cursor_addr = addr;
4972         intel_crtc->cursor_bo = obj;
4973         intel_crtc->cursor_width = width;
4974         intel_crtc->cursor_height = height;
4975
4976         intel_crtc_update_cursor(crtc, true);
4977
4978         return 0;
4979 fail_unpin:
4980         i915_gem_object_unpin(obj);
4981 fail_locked:
4982         mutex_unlock(&dev->struct_mutex);
4983 fail:
4984         drm_gem_object_unreference_unlocked(&obj->base);
4985         return ret;
4986 }
4987
4988 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4989 {
4990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4991
4992         intel_crtc->cursor_x = x;
4993         intel_crtc->cursor_y = y;
4994
4995         intel_crtc_update_cursor(crtc, true);
4996
4997         return 0;
4998 }
4999
5000 /** Sets the color ramps on behalf of RandR */
5001 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5002                                  u16 blue, int regno)
5003 {
5004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005
5006         intel_crtc->lut_r[regno] = red >> 8;
5007         intel_crtc->lut_g[regno] = green >> 8;
5008         intel_crtc->lut_b[regno] = blue >> 8;
5009 }
5010
5011 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5012                              u16 *blue, int regno)
5013 {
5014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5015
5016         *red = intel_crtc->lut_r[regno] << 8;
5017         *green = intel_crtc->lut_g[regno] << 8;
5018         *blue = intel_crtc->lut_b[regno] << 8;
5019 }
5020
5021 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5022                                  u16 *blue, uint32_t start, uint32_t size)
5023 {
5024         int end = (start + size > 256) ? 256 : start + size, i;
5025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026
5027         for (i = start; i < end; i++) {
5028                 intel_crtc->lut_r[i] = red[i] >> 8;
5029                 intel_crtc->lut_g[i] = green[i] >> 8;
5030                 intel_crtc->lut_b[i] = blue[i] >> 8;
5031         }
5032
5033         intel_crtc_load_lut(crtc);
5034 }
5035
5036 /**
5037  * Get a pipe with a simple mode set on it for doing load-based monitor
5038  * detection.
5039  *
5040  * It will be up to the load-detect code to adjust the pipe as appropriate for
5041  * its requirements.  The pipe will be connected to no other encoders.
5042  *
5043  * Currently this code will only succeed if there is a pipe with no encoders
5044  * configured for it.  In the future, it could choose to temporarily disable
5045  * some outputs to free up a pipe for its use.
5046  *
5047  * \return crtc, or NULL if no pipes are available.
5048  */
5049
5050 /* VESA 640x480x72Hz mode to set on the pipe */
5051 static struct drm_display_mode load_detect_mode = {
5052         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5053                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5054 };
5055
5056 static struct drm_framebuffer *
5057 intel_framebuffer_create(struct drm_device *dev,
5058                          struct drm_mode_fb_cmd2 *mode_cmd,
5059                          struct drm_i915_gem_object *obj)
5060 {
5061         struct intel_framebuffer *intel_fb;
5062         int ret;
5063
5064         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5065         if (!intel_fb) {
5066                 drm_gem_object_unreference_unlocked(&obj->base);
5067                 return ERR_PTR(-ENOMEM);
5068         }
5069
5070         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5071         if (ret) {
5072                 drm_gem_object_unreference_unlocked(&obj->base);
5073                 kfree(intel_fb);
5074                 return ERR_PTR(ret);
5075         }
5076
5077         return &intel_fb->base;
5078 }
5079
5080 static u32
5081 intel_framebuffer_pitch_for_width(int width, int bpp)
5082 {
5083         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5084         return ALIGN(pitch, 64);
5085 }
5086
5087 static u32
5088 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5089 {
5090         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5091         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5092 }
5093
5094 static struct drm_framebuffer *
5095 intel_framebuffer_create_for_mode(struct drm_device *dev,
5096                                   struct drm_display_mode *mode,
5097                                   int depth, int bpp)
5098 {
5099         struct drm_i915_gem_object *obj;
5100         struct drm_mode_fb_cmd2 mode_cmd;
5101
5102         obj = i915_gem_alloc_object(dev,
5103                                     intel_framebuffer_size_for_mode(mode, bpp));
5104         if (obj == NULL)
5105                 return ERR_PTR(-ENOMEM);
5106
5107         mode_cmd.width = mode->hdisplay;
5108         mode_cmd.height = mode->vdisplay;
5109         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5110                                                                 bpp);
5111         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5112
5113         return intel_framebuffer_create(dev, &mode_cmd, obj);
5114 }
5115
5116 static struct drm_framebuffer *
5117 mode_fits_in_fbdev(struct drm_device *dev,
5118                    struct drm_display_mode *mode)
5119 {
5120         struct drm_i915_private *dev_priv = dev->dev_private;
5121         struct drm_i915_gem_object *obj;
5122         struct drm_framebuffer *fb;
5123
5124         if (dev_priv->fbdev == NULL)
5125                 return NULL;
5126
5127         obj = dev_priv->fbdev->ifb.obj;
5128         if (obj == NULL)
5129                 return NULL;
5130
5131         fb = &dev_priv->fbdev->ifb.base;
5132         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5133                                                                fb->bits_per_pixel))
5134                 return NULL;
5135
5136         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5137                 return NULL;
5138
5139         return fb;
5140 }
5141
5142 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5143                                 struct drm_connector *connector,
5144                                 struct drm_display_mode *mode,
5145                                 struct intel_load_detect_pipe *old)
5146 {
5147         struct intel_crtc *intel_crtc;
5148         struct drm_crtc *possible_crtc;
5149         struct drm_encoder *encoder = &intel_encoder->base;
5150         struct drm_crtc *crtc = NULL;
5151         struct drm_device *dev = encoder->dev;
5152         struct drm_framebuffer *old_fb;
5153         int i = -1;
5154
5155         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5156                       connector->base.id, drm_get_connector_name(connector),
5157                       encoder->base.id, drm_get_encoder_name(encoder));
5158
5159         /*
5160          * Algorithm gets a little messy:
5161          *
5162          *   - if the connector already has an assigned crtc, use it (but make
5163          *     sure it's on first)
5164          *
5165          *   - try to find the first unused crtc that can drive this connector,
5166          *     and use that if we find one
5167          */
5168
5169         /* See if we already have a CRTC for this connector */
5170         if (encoder->crtc) {
5171                 crtc = encoder->crtc;
5172
5173                 intel_crtc = to_intel_crtc(crtc);
5174                 old->dpms_mode = intel_crtc->dpms_mode;
5175                 old->load_detect_temp = false;
5176
5177                 /* Make sure the crtc and connector are running */
5178                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5179                         struct drm_encoder_helper_funcs *encoder_funcs;
5180                         struct drm_crtc_helper_funcs *crtc_funcs;
5181
5182                         crtc_funcs = crtc->helper_private;
5183                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5184
5185                         encoder_funcs = encoder->helper_private;
5186                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5187                 }
5188
5189                 return true;
5190         }
5191
5192         /* Find an unused one (if possible) */
5193         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5194                 i++;
5195                 if (!(encoder->possible_crtcs & (1 << i)))
5196                         continue;
5197                 if (!possible_crtc->enabled) {
5198                         crtc = possible_crtc;
5199                         break;
5200                 }
5201         }
5202
5203         /*
5204          * If we didn't find an unused CRTC, don't use any.
5205          */
5206         if (!crtc) {
5207                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5208                 return false;
5209         }
5210
5211         encoder->crtc = crtc;
5212         connector->encoder = encoder;
5213
5214         intel_crtc = to_intel_crtc(crtc);
5215         old->dpms_mode = intel_crtc->dpms_mode;
5216         old->load_detect_temp = true;
5217         old->release_fb = NULL;
5218
5219         if (!mode)
5220                 mode = &load_detect_mode;
5221
5222         old_fb = crtc->fb;
5223
5224         /* We need a framebuffer large enough to accommodate all accesses
5225          * that the plane may generate whilst we perform load detection.
5226          * We can not rely on the fbcon either being present (we get called
5227          * during its initialisation to detect all boot displays, or it may
5228          * not even exist) or that it is large enough to satisfy the
5229          * requested mode.
5230          */
5231         crtc->fb = mode_fits_in_fbdev(dev, mode);
5232         if (crtc->fb == NULL) {
5233                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5234                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5235                 old->release_fb = crtc->fb;
5236         } else
5237                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5238         if (IS_ERR(crtc->fb)) {
5239                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5240                 crtc->fb = old_fb;
5241                 return false;
5242         }
5243
5244         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5245                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5246                 if (old->release_fb)
5247                         old->release_fb->funcs->destroy(old->release_fb);
5248                 crtc->fb = old_fb;
5249                 return false;
5250         }
5251
5252         /* let the connector get through one full cycle before testing */
5253         intel_wait_for_vblank(dev, intel_crtc->pipe);
5254
5255         return true;
5256 }
5257
5258 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5259                                     struct drm_connector *connector,
5260                                     struct intel_load_detect_pipe *old)
5261 {
5262         struct drm_encoder *encoder = &intel_encoder->base;
5263         struct drm_device *dev = encoder->dev;
5264         struct drm_crtc *crtc = encoder->crtc;
5265         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5266         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5267
5268         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5269                       connector->base.id, drm_get_connector_name(connector),
5270                       encoder->base.id, drm_get_encoder_name(encoder));
5271
5272         if (old->load_detect_temp) {
5273                 connector->encoder = NULL;
5274                 drm_helper_disable_unused_functions(dev);
5275
5276                 if (old->release_fb)
5277                         old->release_fb->funcs->destroy(old->release_fb);
5278
5279                 return;
5280         }
5281
5282         /* Switch crtc and encoder back off if necessary */
5283         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5284                 encoder_funcs->dpms(encoder, old->dpms_mode);
5285                 crtc_funcs->dpms(crtc, old->dpms_mode);
5286         }
5287 }
5288
5289 /* Returns the clock of the currently programmed mode of the given pipe. */
5290 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5291 {
5292         struct drm_i915_private *dev_priv = dev->dev_private;
5293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294         int pipe = intel_crtc->pipe;
5295         u32 dpll = I915_READ(DPLL(pipe));
5296         u32 fp;
5297         intel_clock_t clock;
5298
5299         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5300                 fp = I915_READ(FP0(pipe));
5301         else
5302                 fp = I915_READ(FP1(pipe));
5303
5304         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5305         if (IS_PINEVIEW(dev)) {
5306                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5307                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5308         } else {
5309                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5310                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5311         }
5312
5313         if (!IS_GEN2(dev)) {
5314                 if (IS_PINEVIEW(dev))
5315                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5316                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5317                 else
5318                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5319                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5320
5321                 switch (dpll & DPLL_MODE_MASK) {
5322                 case DPLLB_MODE_DAC_SERIAL:
5323                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5324                                 5 : 10;
5325                         break;
5326                 case DPLLB_MODE_LVDS:
5327                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5328                                 7 : 14;
5329                         break;
5330                 default:
5331                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5332                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5333                         return 0;
5334                 }
5335
5336                 /* XXX: Handle the 100Mhz refclk */
5337                 intel_clock(dev, 96000, &clock);
5338         } else {
5339                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5340
5341                 if (is_lvds) {
5342                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5343                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5344                         clock.p2 = 14;
5345
5346                         if ((dpll & PLL_REF_INPUT_MASK) ==
5347                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5348                                 /* XXX: might not be 66MHz */
5349                                 intel_clock(dev, 66000, &clock);
5350                         } else
5351                                 intel_clock(dev, 48000, &clock);
5352                 } else {
5353                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5354                                 clock.p1 = 2;
5355                         else {
5356                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5357                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5358                         }
5359                         if (dpll & PLL_P2_DIVIDE_BY_4)
5360                                 clock.p2 = 4;
5361                         else
5362                                 clock.p2 = 2;
5363
5364                         intel_clock(dev, 48000, &clock);
5365                 }
5366         }
5367
5368         /* XXX: It would be nice to validate the clocks, but we can't reuse
5369          * i830PllIsValid() because it relies on the xf86_config connector
5370          * configuration being accurate, which it isn't necessarily.
5371          */
5372
5373         return clock.dot;
5374 }
5375
5376 /** Returns the currently programmed mode of the given pipe. */
5377 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5378                                              struct drm_crtc *crtc)
5379 {
5380         struct drm_i915_private *dev_priv = dev->dev_private;
5381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5382         int pipe = intel_crtc->pipe;
5383         struct drm_display_mode *mode;
5384         int htot = I915_READ(HTOTAL(pipe));
5385         int hsync = I915_READ(HSYNC(pipe));
5386         int vtot = I915_READ(VTOTAL(pipe));
5387         int vsync = I915_READ(VSYNC(pipe));
5388
5389         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5390         if (!mode)
5391                 return NULL;
5392
5393         mode->clock = intel_crtc_clock_get(dev, crtc);
5394         mode->hdisplay = (htot & 0xffff) + 1;
5395         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5396         mode->hsync_start = (hsync & 0xffff) + 1;
5397         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5398         mode->vdisplay = (vtot & 0xffff) + 1;
5399         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5400         mode->vsync_start = (vsync & 0xffff) + 1;
5401         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5402
5403         drm_mode_set_name(mode);
5404         drm_mode_set_crtcinfo(mode, 0);
5405
5406         return mode;
5407 }
5408
5409 #define GPU_IDLE_TIMEOUT 500 /* ms */
5410
5411 /* When this timer fires, we've been idle for awhile */
5412 static void intel_gpu_idle_timer(unsigned long arg)
5413 {
5414         struct drm_device *dev = (struct drm_device *)arg;
5415         drm_i915_private_t *dev_priv = dev->dev_private;
5416
5417         if (!list_empty(&dev_priv->mm.active_list)) {
5418                 /* Still processing requests, so just re-arm the timer. */
5419                 mod_timer(&dev_priv->idle_timer, jiffies +
5420                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5421                 return;
5422         }
5423
5424         dev_priv->busy = false;
5425         queue_work(dev_priv->wq, &dev_priv->idle_work);
5426 }
5427
5428 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5429
5430 static void intel_crtc_idle_timer(unsigned long arg)
5431 {
5432         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5433         struct drm_crtc *crtc = &intel_crtc->base;
5434         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5435         struct intel_framebuffer *intel_fb;
5436
5437         intel_fb = to_intel_framebuffer(crtc->fb);
5438         if (intel_fb && intel_fb->obj->active) {
5439                 /* The framebuffer is still being accessed by the GPU. */
5440                 mod_timer(&intel_crtc->idle_timer, jiffies +
5441                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5442                 return;
5443         }
5444
5445         intel_crtc->busy = false;
5446         queue_work(dev_priv->wq, &dev_priv->idle_work);
5447 }
5448
5449 static void intel_increase_pllclock(struct drm_crtc *crtc)
5450 {
5451         struct drm_device *dev = crtc->dev;
5452         drm_i915_private_t *dev_priv = dev->dev_private;
5453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5454         int pipe = intel_crtc->pipe;
5455         int dpll_reg = DPLL(pipe);
5456         int dpll;
5457
5458         if (HAS_PCH_SPLIT(dev))
5459                 return;
5460
5461         if (!dev_priv->lvds_downclock_avail)
5462                 return;
5463
5464         dpll = I915_READ(dpll_reg);
5465         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5466                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5467
5468                 assert_panel_unlocked(dev_priv, pipe);
5469
5470                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5471                 I915_WRITE(dpll_reg, dpll);
5472                 intel_wait_for_vblank(dev, pipe);
5473
5474                 dpll = I915_READ(dpll_reg);
5475                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5476                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5477         }
5478
5479         /* Schedule downclock */
5480         mod_timer(&intel_crtc->idle_timer, jiffies +
5481                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5482 }
5483
5484 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5485 {
5486         struct drm_device *dev = crtc->dev;
5487         drm_i915_private_t *dev_priv = dev->dev_private;
5488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489         int pipe = intel_crtc->pipe;
5490         int dpll_reg = DPLL(pipe);
5491         int dpll = I915_READ(dpll_reg);
5492
5493         if (HAS_PCH_SPLIT(dev))
5494                 return;
5495
5496         if (!dev_priv->lvds_downclock_avail)
5497                 return;
5498
5499         /*
5500          * Since this is called by a timer, we should never get here in
5501          * the manual case.
5502          */
5503         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5504                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5505
5506                 assert_panel_unlocked(dev_priv, pipe);
5507
5508                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5509                 I915_WRITE(dpll_reg, dpll);
5510                 intel_wait_for_vblank(dev, pipe);
5511                 dpll = I915_READ(dpll_reg);
5512                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5513                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5514         }
5515
5516 }
5517
5518 /**
5519  * intel_idle_update - adjust clocks for idleness
5520  * @work: work struct
5521  *
5522  * Either the GPU or display (or both) went idle.  Check the busy status
5523  * here and adjust the CRTC and GPU clocks as necessary.
5524  */
5525 static void intel_idle_update(struct work_struct *work)
5526 {
5527         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5528                                                     idle_work);
5529         struct drm_device *dev = dev_priv->dev;
5530         struct drm_crtc *crtc;
5531         struct intel_crtc *intel_crtc;
5532
5533         if (!i915_powersave)
5534                 return;
5535
5536         mutex_lock(&dev->struct_mutex);
5537
5538         i915_update_gfx_val(dev_priv);
5539
5540         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5541                 /* Skip inactive CRTCs */
5542                 if (!crtc->fb)
5543                         continue;
5544
5545                 intel_crtc = to_intel_crtc(crtc);
5546                 if (!intel_crtc->busy)
5547                         intel_decrease_pllclock(crtc);
5548         }
5549
5550
5551         mutex_unlock(&dev->struct_mutex);
5552 }
5553
5554 /**
5555  * intel_mark_busy - mark the GPU and possibly the display busy
5556  * @dev: drm device
5557  * @obj: object we're operating on
5558  *
5559  * Callers can use this function to indicate that the GPU is busy processing
5560  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5561  * buffer), we'll also mark the display as busy, so we know to increase its
5562  * clock frequency.
5563  */
5564 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5565 {
5566         drm_i915_private_t *dev_priv = dev->dev_private;
5567         struct drm_crtc *crtc = NULL;
5568         struct intel_framebuffer *intel_fb;
5569         struct intel_crtc *intel_crtc;
5570
5571         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5572                 return;
5573
5574         if (!dev_priv->busy)
5575                 dev_priv->busy = true;
5576         else
5577                 mod_timer(&dev_priv->idle_timer, jiffies +
5578                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5579
5580         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5581                 if (!crtc->fb)
5582                         continue;
5583
5584                 intel_crtc = to_intel_crtc(crtc);
5585                 intel_fb = to_intel_framebuffer(crtc->fb);
5586                 if (intel_fb->obj == obj) {
5587                         if (!intel_crtc->busy) {
5588                                 /* Non-busy -> busy, upclock */
5589                                 intel_increase_pllclock(crtc);
5590                                 intel_crtc->busy = true;
5591                         } else {
5592                                 /* Busy -> busy, put off timer */
5593                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5594                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5595                         }
5596                 }
5597         }
5598 }
5599
5600 static void intel_crtc_destroy(struct drm_crtc *crtc)
5601 {
5602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603         struct drm_device *dev = crtc->dev;
5604         struct intel_unpin_work *work;
5605         unsigned long flags;
5606
5607         spin_lock_irqsave(&dev->event_lock, flags);
5608         work = intel_crtc->unpin_work;
5609         intel_crtc->unpin_work = NULL;
5610         spin_unlock_irqrestore(&dev->event_lock, flags);
5611
5612         if (work) {
5613                 cancel_work_sync(&work->work);
5614                 kfree(work);
5615         }
5616
5617         drm_crtc_cleanup(crtc);
5618
5619         kfree(intel_crtc);
5620 }
5621
5622 static void intel_unpin_work_fn(struct work_struct *__work)
5623 {
5624         struct intel_unpin_work *work =
5625                 container_of(__work, struct intel_unpin_work, work);
5626
5627         mutex_lock(&work->dev->struct_mutex);
5628         intel_unpin_fb_obj(work->old_fb_obj);
5629         drm_gem_object_unreference(&work->pending_flip_obj->base);
5630         drm_gem_object_unreference(&work->old_fb_obj->base);
5631
5632         intel_update_fbc(work->dev);
5633         mutex_unlock(&work->dev->struct_mutex);
5634         kfree(work);
5635 }
5636
5637 static void do_intel_finish_page_flip(struct drm_device *dev,
5638                                       struct drm_crtc *crtc)
5639 {
5640         drm_i915_private_t *dev_priv = dev->dev_private;
5641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5642         struct intel_unpin_work *work;
5643         struct drm_i915_gem_object *obj;
5644         struct drm_pending_vblank_event *e;
5645         struct timeval tnow, tvbl;
5646         unsigned long flags;
5647
5648         /* Ignore early vblank irqs */
5649         if (intel_crtc == NULL)
5650                 return;
5651
5652         do_gettimeofday(&tnow);
5653
5654         spin_lock_irqsave(&dev->event_lock, flags);
5655         work = intel_crtc->unpin_work;
5656         if (work == NULL || !work->pending) {
5657                 spin_unlock_irqrestore(&dev->event_lock, flags);
5658                 return;
5659         }
5660
5661         intel_crtc->unpin_work = NULL;
5662
5663         if (work->event) {
5664                 e = work->event;
5665                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5666
5667                 /* Called before vblank count and timestamps have
5668                  * been updated for the vblank interval of flip
5669                  * completion? Need to increment vblank count and
5670                  * add one videorefresh duration to returned timestamp
5671                  * to account for this. We assume this happened if we
5672                  * get called over 0.9 frame durations after the last
5673                  * timestamped vblank.
5674                  *
5675                  * This calculation can not be used with vrefresh rates
5676                  * below 5Hz (10Hz to be on the safe side) without
5677                  * promoting to 64 integers.
5678                  */
5679                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5680                     9 * crtc->framedur_ns) {
5681                         e->event.sequence++;
5682                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5683                                              crtc->framedur_ns);
5684                 }
5685
5686                 e->event.tv_sec = tvbl.tv_sec;
5687                 e->event.tv_usec = tvbl.tv_usec;
5688
5689                 list_add_tail(&e->base.link,
5690                               &e->base.file_priv->event_list);
5691                 wake_up_interruptible(&e->base.file_priv->event_wait);
5692         }
5693
5694         drm_vblank_put(dev, intel_crtc->pipe);
5695
5696         spin_unlock_irqrestore(&dev->event_lock, flags);
5697
5698         obj = work->old_fb_obj;
5699
5700         atomic_clear_mask(1 << intel_crtc->plane,
5701                           &obj->pending_flip.counter);
5702         if (atomic_read(&obj->pending_flip) == 0)
5703                 wake_up(&dev_priv->pending_flip_queue);
5704
5705         schedule_work(&work->work);
5706
5707         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5708 }
5709
5710 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5711 {
5712         drm_i915_private_t *dev_priv = dev->dev_private;
5713         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5714
5715         do_intel_finish_page_flip(dev, crtc);
5716 }
5717
5718 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5719 {
5720         drm_i915_private_t *dev_priv = dev->dev_private;
5721         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5722
5723         do_intel_finish_page_flip(dev, crtc);
5724 }
5725
5726 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5727 {
5728         drm_i915_private_t *dev_priv = dev->dev_private;
5729         struct intel_crtc *intel_crtc =
5730                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5731         unsigned long flags;
5732
5733         spin_lock_irqsave(&dev->event_lock, flags);
5734         if (intel_crtc->unpin_work) {
5735                 if ((++intel_crtc->unpin_work->pending) > 1)
5736                         DRM_ERROR("Prepared flip multiple times\n");
5737         } else {
5738                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5739         }
5740         spin_unlock_irqrestore(&dev->event_lock, flags);
5741 }
5742
5743 static int intel_gen2_queue_flip(struct drm_device *dev,
5744                                  struct drm_crtc *crtc,
5745                                  struct drm_framebuffer *fb,
5746                                  struct drm_i915_gem_object *obj)
5747 {
5748         struct drm_i915_private *dev_priv = dev->dev_private;
5749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5750         unsigned long offset;
5751         u32 flip_mask;
5752         int ret;
5753
5754         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5755         if (ret)
5756                 goto err;
5757
5758         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5759         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5760
5761         ret = BEGIN_LP_RING(6);
5762         if (ret)
5763                 goto err_unpin;
5764
5765         /* Can't queue multiple flips, so wait for the previous
5766          * one to finish before executing the next.
5767          */
5768         if (intel_crtc->plane)
5769                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5770         else
5771                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5772         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5773         OUT_RING(MI_NOOP);
5774         OUT_RING(MI_DISPLAY_FLIP |
5775                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5776         OUT_RING(fb->pitches[0]);
5777         OUT_RING(obj->gtt_offset + offset);
5778         OUT_RING(0); /* aux display base address, unused */
5779         ADVANCE_LP_RING();
5780         return 0;
5781
5782 err_unpin:
5783         intel_unpin_fb_obj(obj);
5784 err:
5785         return ret;
5786 }
5787
5788 static int intel_gen3_queue_flip(struct drm_device *dev,
5789                                  struct drm_crtc *crtc,
5790                                  struct drm_framebuffer *fb,
5791                                  struct drm_i915_gem_object *obj)
5792 {
5793         struct drm_i915_private *dev_priv = dev->dev_private;
5794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5795         unsigned long offset;
5796         u32 flip_mask;
5797         int ret;
5798
5799         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5800         if (ret)
5801                 goto err;
5802
5803         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5804         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5805
5806         ret = BEGIN_LP_RING(6);
5807         if (ret)
5808                 goto err_unpin;
5809
5810         if (intel_crtc->plane)
5811                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5812         else
5813                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5814         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5815         OUT_RING(MI_NOOP);
5816         OUT_RING(MI_DISPLAY_FLIP_I915 |
5817                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5818         OUT_RING(fb->pitches[0]);
5819         OUT_RING(obj->gtt_offset + offset);
5820         OUT_RING(MI_NOOP);
5821
5822         ADVANCE_LP_RING();
5823         return 0;
5824
5825 err_unpin:
5826         intel_unpin_fb_obj(obj);
5827 err:
5828         return ret;
5829 }
5830
5831 static int intel_gen4_queue_flip(struct drm_device *dev,
5832                                  struct drm_crtc *crtc,
5833                                  struct drm_framebuffer *fb,
5834                                  struct drm_i915_gem_object *obj)
5835 {
5836         struct drm_i915_private *dev_priv = dev->dev_private;
5837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5838         uint32_t pf, pipesrc;
5839         int ret;
5840
5841         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5842         if (ret)
5843                 goto err;
5844
5845         ret = BEGIN_LP_RING(4);
5846         if (ret)
5847                 goto err_unpin;
5848
5849         /* i965+ uses the linear or tiled offsets from the
5850          * Display Registers (which do not change across a page-flip)
5851          * so we need only reprogram the base address.
5852          */
5853         OUT_RING(MI_DISPLAY_FLIP |
5854                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5855         OUT_RING(fb->pitches[0]);
5856         OUT_RING(obj->gtt_offset | obj->tiling_mode);
5857
5858         /* XXX Enabling the panel-fitter across page-flip is so far
5859          * untested on non-native modes, so ignore it for now.
5860          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5861          */
5862         pf = 0;
5863         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5864         OUT_RING(pf | pipesrc);
5865         ADVANCE_LP_RING();
5866         return 0;
5867
5868 err_unpin:
5869         intel_unpin_fb_obj(obj);
5870 err:
5871         return ret;
5872 }
5873
5874 static int intel_gen6_queue_flip(struct drm_device *dev,
5875                                  struct drm_crtc *crtc,
5876                                  struct drm_framebuffer *fb,
5877                                  struct drm_i915_gem_object *obj)
5878 {
5879         struct drm_i915_private *dev_priv = dev->dev_private;
5880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881         uint32_t pf, pipesrc;
5882         int ret;
5883
5884         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5885         if (ret)
5886                 goto err;
5887
5888         ret = BEGIN_LP_RING(4);
5889         if (ret)
5890                 goto err_unpin;
5891
5892         OUT_RING(MI_DISPLAY_FLIP |
5893                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5894         OUT_RING(fb->pitches[0] | obj->tiling_mode);
5895         OUT_RING(obj->gtt_offset);
5896
5897         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5898         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5899         OUT_RING(pf | pipesrc);
5900         ADVANCE_LP_RING();
5901         return 0;
5902
5903 err_unpin:
5904         intel_unpin_fb_obj(obj);
5905 err:
5906         return ret;
5907 }
5908
5909 /*
5910  * On gen7 we currently use the blit ring because (in early silicon at least)
5911  * the render ring doesn't give us interrpts for page flip completion, which
5912  * means clients will hang after the first flip is queued.  Fortunately the
5913  * blit ring generates interrupts properly, so use it instead.
5914  */
5915 static int intel_gen7_queue_flip(struct drm_device *dev,
5916                                  struct drm_crtc *crtc,
5917                                  struct drm_framebuffer *fb,
5918                                  struct drm_i915_gem_object *obj)
5919 {
5920         struct drm_i915_private *dev_priv = dev->dev_private;
5921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5922         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5923         int ret;
5924
5925         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5926         if (ret)
5927                 goto err;
5928
5929         ret = intel_ring_begin(ring, 4);
5930         if (ret)
5931                 goto err_unpin;
5932
5933         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5934         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5935         intel_ring_emit(ring, (obj->gtt_offset));
5936         intel_ring_emit(ring, (MI_NOOP));
5937         intel_ring_advance(ring);
5938         return 0;
5939
5940 err_unpin:
5941         intel_unpin_fb_obj(obj);
5942 err:
5943         return ret;
5944 }
5945
5946 static int intel_default_queue_flip(struct drm_device *dev,
5947                                     struct drm_crtc *crtc,
5948                                     struct drm_framebuffer *fb,
5949                                     struct drm_i915_gem_object *obj)
5950 {
5951         return -ENODEV;
5952 }
5953
5954 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5955                                 struct drm_framebuffer *fb,
5956                                 struct drm_pending_vblank_event *event)
5957 {
5958         struct drm_device *dev = crtc->dev;
5959         struct drm_i915_private *dev_priv = dev->dev_private;
5960         struct intel_framebuffer *intel_fb;
5961         struct drm_i915_gem_object *obj;
5962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5963         struct intel_unpin_work *work;
5964         unsigned long flags;
5965         int ret;
5966
5967         work = kzalloc(sizeof *work, GFP_KERNEL);
5968         if (work == NULL)
5969                 return -ENOMEM;
5970
5971         work->event = event;
5972         work->dev = crtc->dev;
5973         intel_fb = to_intel_framebuffer(crtc->fb);
5974         work->old_fb_obj = intel_fb->obj;
5975         INIT_WORK(&work->work, intel_unpin_work_fn);
5976
5977         ret = drm_vblank_get(dev, intel_crtc->pipe);
5978         if (ret)
5979                 goto free_work;
5980
5981         /* We borrow the event spin lock for protecting unpin_work */
5982         spin_lock_irqsave(&dev->event_lock, flags);
5983         if (intel_crtc->unpin_work) {
5984                 spin_unlock_irqrestore(&dev->event_lock, flags);
5985                 kfree(work);
5986                 drm_vblank_put(dev, intel_crtc->pipe);
5987
5988                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5989                 return -EBUSY;
5990         }
5991         intel_crtc->unpin_work = work;
5992         spin_unlock_irqrestore(&dev->event_lock, flags);
5993
5994         intel_fb = to_intel_framebuffer(fb);
5995         obj = intel_fb->obj;
5996
5997         mutex_lock(&dev->struct_mutex);
5998
5999         /* Reference the objects for the scheduled work. */
6000         drm_gem_object_reference(&work->old_fb_obj->base);
6001         drm_gem_object_reference(&obj->base);
6002
6003         crtc->fb = fb;
6004
6005         work->pending_flip_obj = obj;
6006
6007         work->enable_stall_check = true;
6008
6009         /* Block clients from rendering to the new back buffer until
6010          * the flip occurs and the object is no longer visible.
6011          */
6012         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6013
6014         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6015         if (ret)
6016                 goto cleanup_pending;
6017
6018         intel_disable_fbc(dev);
6019         mutex_unlock(&dev->struct_mutex);
6020
6021         trace_i915_flip_request(intel_crtc->plane, obj);
6022
6023         return 0;
6024
6025 cleanup_pending:
6026         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6027         drm_gem_object_unreference(&work->old_fb_obj->base);
6028         drm_gem_object_unreference(&obj->base);
6029         mutex_unlock(&dev->struct_mutex);
6030
6031         spin_lock_irqsave(&dev->event_lock, flags);
6032         intel_crtc->unpin_work = NULL;
6033         spin_unlock_irqrestore(&dev->event_lock, flags);
6034
6035         drm_vblank_put(dev, intel_crtc->pipe);
6036 free_work:
6037         kfree(work);
6038
6039         return ret;
6040 }
6041
6042 static void intel_sanitize_modesetting(struct drm_device *dev,
6043                                        int pipe, int plane)
6044 {
6045         struct drm_i915_private *dev_priv = dev->dev_private;
6046         u32 reg, val;
6047
6048         /* Clear any frame start delays used for debugging left by the BIOS */
6049         for_each_pipe(pipe) {
6050                 reg = PIPECONF(pipe);
6051                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6052         }
6053
6054         if (HAS_PCH_SPLIT(dev))
6055                 return;
6056
6057         /* Who knows what state these registers were left in by the BIOS or
6058          * grub?
6059          *
6060          * If we leave the registers in a conflicting state (e.g. with the
6061          * display plane reading from the other pipe than the one we intend
6062          * to use) then when we attempt to teardown the active mode, we will
6063          * not disable the pipes and planes in the correct order -- leaving
6064          * a plane reading from a disabled pipe and possibly leading to
6065          * undefined behaviour.
6066          */
6067
6068         reg = DSPCNTR(plane);
6069         val = I915_READ(reg);
6070
6071         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6072                 return;
6073         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6074                 return;
6075
6076         /* This display plane is active and attached to the other CPU pipe. */
6077         pipe = !pipe;
6078
6079         /* Disable the plane and wait for it to stop reading from the pipe. */
6080         intel_disable_plane(dev_priv, plane, pipe);
6081         intel_disable_pipe(dev_priv, pipe);
6082 }
6083
6084 static void intel_crtc_reset(struct drm_crtc *crtc)
6085 {
6086         struct drm_device *dev = crtc->dev;
6087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6088
6089         /* Reset flags back to the 'unknown' status so that they
6090          * will be correctly set on the initial modeset.
6091          */
6092         intel_crtc->dpms_mode = -1;
6093
6094         /* We need to fix up any BIOS configuration that conflicts with
6095          * our expectations.
6096          */
6097         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6098 }
6099
6100 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6101         .dpms = intel_crtc_dpms,
6102         .mode_fixup = intel_crtc_mode_fixup,
6103         .mode_set = intel_crtc_mode_set,
6104         .mode_set_base = intel_pipe_set_base,
6105         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6106         .load_lut = intel_crtc_load_lut,
6107         .disable = intel_crtc_disable,
6108 };
6109
6110 static const struct drm_crtc_funcs intel_crtc_funcs = {
6111         .reset = intel_crtc_reset,
6112         .cursor_set = intel_crtc_cursor_set,
6113         .cursor_move = intel_crtc_cursor_move,
6114         .gamma_set = intel_crtc_gamma_set,
6115         .set_config = drm_crtc_helper_set_config,
6116         .destroy = intel_crtc_destroy,
6117         .page_flip = intel_crtc_page_flip,
6118 };
6119
6120 static void intel_pch_pll_init(struct drm_device *dev)
6121 {
6122         drm_i915_private_t *dev_priv = dev->dev_private;
6123         int i;
6124
6125         if (dev_priv->num_pch_pll == 0) {
6126                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6127                 return;
6128         }
6129
6130         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6131                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6132                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6133                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6134         }
6135 }
6136
6137 static void intel_crtc_init(struct drm_device *dev, int pipe)
6138 {
6139         drm_i915_private_t *dev_priv = dev->dev_private;
6140         struct intel_crtc *intel_crtc;
6141         int i;
6142
6143         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6144         if (intel_crtc == NULL)
6145                 return;
6146
6147         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6148
6149         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6150         for (i = 0; i < 256; i++) {
6151                 intel_crtc->lut_r[i] = i;
6152                 intel_crtc->lut_g[i] = i;
6153                 intel_crtc->lut_b[i] = i;
6154         }
6155
6156         /* Swap pipes & planes for FBC on pre-965 */
6157         intel_crtc->pipe = pipe;
6158         intel_crtc->plane = pipe;
6159         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6160                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6161                 intel_crtc->plane = !pipe;
6162         }
6163
6164         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6165                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6166         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6167         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6168
6169         intel_crtc_reset(&intel_crtc->base);
6170         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6171         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6172
6173         if (HAS_PCH_SPLIT(dev)) {
6174                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6175                 intel_helper_funcs.commit = ironlake_crtc_commit;
6176         } else {
6177                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6178                 intel_helper_funcs.commit = i9xx_crtc_commit;
6179         }
6180
6181         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6182
6183         intel_crtc->busy = false;
6184
6185         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6186                     (unsigned long)intel_crtc);
6187 }
6188
6189 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6190                                 struct drm_file *file)
6191 {
6192         drm_i915_private_t *dev_priv = dev->dev_private;
6193         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6194         struct drm_mode_object *drmmode_obj;
6195         struct intel_crtc *crtc;
6196
6197         if (!dev_priv) {
6198                 DRM_ERROR("called with no initialization\n");
6199                 return -EINVAL;
6200         }
6201
6202         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6203                         DRM_MODE_OBJECT_CRTC);
6204
6205         if (!drmmode_obj) {
6206                 DRM_ERROR("no such CRTC id\n");
6207                 return -EINVAL;
6208         }
6209
6210         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6211         pipe_from_crtc_id->pipe = crtc->pipe;
6212
6213         return 0;
6214 }
6215
6216 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6217 {
6218         struct intel_encoder *encoder;
6219         int index_mask = 0;
6220         int entry = 0;
6221
6222         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6223                 if (type_mask & encoder->clone_mask)
6224                         index_mask |= (1 << entry);
6225                 entry++;
6226         }
6227
6228         return index_mask;
6229 }
6230
6231 static bool has_edp_a(struct drm_device *dev)
6232 {
6233         struct drm_i915_private *dev_priv = dev->dev_private;
6234
6235         if (!IS_MOBILE(dev))
6236                 return false;
6237
6238         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6239                 return false;
6240
6241         if (IS_GEN5(dev) &&
6242             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6243                 return false;
6244
6245         return true;
6246 }
6247
6248 static void intel_setup_outputs(struct drm_device *dev)
6249 {
6250         struct drm_i915_private *dev_priv = dev->dev_private;
6251         struct intel_encoder *encoder;
6252         bool dpd_is_edp = false;
6253         bool has_lvds;
6254
6255         has_lvds = intel_lvds_init(dev);
6256         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6257                 /* disable the panel fitter on everything but LVDS */
6258                 I915_WRITE(PFIT_CONTROL, 0);
6259         }
6260
6261         if (HAS_PCH_SPLIT(dev)) {
6262                 dpd_is_edp = intel_dpd_is_edp(dev);
6263
6264                 if (has_edp_a(dev))
6265                         intel_dp_init(dev, DP_A);
6266
6267                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6268                         intel_dp_init(dev, PCH_DP_D);
6269         }
6270
6271         intel_crt_init(dev);
6272
6273         if (HAS_PCH_SPLIT(dev)) {
6274                 int found;
6275
6276                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6277                         /* PCH SDVOB multiplex with HDMIB */
6278                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6279                         if (!found)
6280                                 intel_hdmi_init(dev, HDMIB);
6281                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6282                                 intel_dp_init(dev, PCH_DP_B);
6283                 }
6284
6285                 if (I915_READ(HDMIC) & PORT_DETECTED)
6286                         intel_hdmi_init(dev, HDMIC);
6287
6288                 if (I915_READ(HDMID) & PORT_DETECTED)
6289                         intel_hdmi_init(dev, HDMID);
6290
6291                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6292                         intel_dp_init(dev, PCH_DP_C);
6293
6294                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6295                         intel_dp_init(dev, PCH_DP_D);
6296
6297         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6298                 bool found = false;
6299
6300                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6301                         DRM_DEBUG_KMS("probing SDVOB\n");
6302                         found = intel_sdvo_init(dev, SDVOB, true);
6303                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6304                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6305                                 intel_hdmi_init(dev, SDVOB);
6306                         }
6307
6308                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6309                                 DRM_DEBUG_KMS("probing DP_B\n");
6310                                 intel_dp_init(dev, DP_B);
6311                         }
6312                 }
6313
6314                 /* Before G4X SDVOC doesn't have its own detect register */
6315
6316                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6317                         DRM_DEBUG_KMS("probing SDVOC\n");
6318                         found = intel_sdvo_init(dev, SDVOC, false);
6319                 }
6320
6321                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6322
6323                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6324                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6325                                 intel_hdmi_init(dev, SDVOC);
6326                         }
6327                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6328                                 DRM_DEBUG_KMS("probing DP_C\n");
6329                                 intel_dp_init(dev, DP_C);
6330                         }
6331                 }
6332
6333                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6334                     (I915_READ(DP_D) & DP_DETECTED)) {
6335                         DRM_DEBUG_KMS("probing DP_D\n");
6336                         intel_dp_init(dev, DP_D);
6337                 }
6338         } else if (IS_GEN2(dev))
6339                 intel_dvo_init(dev);
6340
6341         if (SUPPORTS_TV(dev))
6342                 intel_tv_init(dev);
6343
6344         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6345                 encoder->base.possible_crtcs = encoder->crtc_mask;
6346                 encoder->base.possible_clones =
6347                         intel_encoder_clones(dev, encoder->clone_mask);
6348         }
6349
6350         /* disable all the possible outputs/crtcs before entering KMS mode */
6351         drm_helper_disable_unused_functions(dev);
6352
6353         if (HAS_PCH_SPLIT(dev))
6354                 ironlake_init_pch_refclk(dev);
6355 }
6356
6357 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6358 {
6359         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6360
6361         drm_framebuffer_cleanup(fb);
6362         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6363
6364         kfree(intel_fb);
6365 }
6366
6367 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6368                                                 struct drm_file *file,
6369                                                 unsigned int *handle)
6370 {
6371         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6372         struct drm_i915_gem_object *obj = intel_fb->obj;
6373
6374         return drm_gem_handle_create(file, &obj->base, handle);
6375 }
6376
6377 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6378         .destroy = intel_user_framebuffer_destroy,
6379         .create_handle = intel_user_framebuffer_create_handle,
6380 };
6381
6382 int intel_framebuffer_init(struct drm_device *dev,
6383                            struct intel_framebuffer *intel_fb,
6384                            struct drm_mode_fb_cmd2 *mode_cmd,
6385                            struct drm_i915_gem_object *obj)
6386 {
6387         int ret;
6388
6389         if (obj->tiling_mode == I915_TILING_Y)
6390                 return -EINVAL;
6391
6392         if (mode_cmd->pitches[0] & 63)
6393                 return -EINVAL;
6394
6395         switch (mode_cmd->pixel_format) {
6396         case DRM_FORMAT_RGB332:
6397         case DRM_FORMAT_RGB565:
6398         case DRM_FORMAT_XRGB8888:
6399         case DRM_FORMAT_XBGR8888:
6400         case DRM_FORMAT_ARGB8888:
6401         case DRM_FORMAT_XRGB2101010:
6402         case DRM_FORMAT_ARGB2101010:
6403                 /* RGB formats are common across chipsets */
6404                 break;
6405         case DRM_FORMAT_YUYV:
6406         case DRM_FORMAT_UYVY:
6407         case DRM_FORMAT_YVYU:
6408         case DRM_FORMAT_VYUY:
6409                 break;
6410         default:
6411                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6412                                 mode_cmd->pixel_format);
6413                 return -EINVAL;
6414         }
6415
6416         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6417         if (ret) {
6418                 DRM_ERROR("framebuffer init failed %d\n", ret);
6419                 return ret;
6420         }
6421
6422         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6423         intel_fb->obj = obj;
6424         return 0;
6425 }
6426
6427 static struct drm_framebuffer *
6428 intel_user_framebuffer_create(struct drm_device *dev,
6429                               struct drm_file *filp,
6430                               struct drm_mode_fb_cmd2 *mode_cmd)
6431 {
6432         struct drm_i915_gem_object *obj;
6433
6434         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6435                                                 mode_cmd->handles[0]));
6436         if (&obj->base == NULL)
6437                 return ERR_PTR(-ENOENT);
6438
6439         return intel_framebuffer_create(dev, mode_cmd, obj);
6440 }
6441
6442 static const struct drm_mode_config_funcs intel_mode_funcs = {
6443         .fb_create = intel_user_framebuffer_create,
6444         .output_poll_changed = intel_fb_output_poll_changed,
6445 };
6446
6447 /* Set up chip specific display functions */
6448 static void intel_init_display(struct drm_device *dev)
6449 {
6450         struct drm_i915_private *dev_priv = dev->dev_private;
6451
6452         /* We always want a DPMS function */
6453         if (HAS_PCH_SPLIT(dev)) {
6454                 dev_priv->display.dpms = ironlake_crtc_dpms;
6455                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6456                 dev_priv->display.off = ironlake_crtc_off;
6457                 dev_priv->display.update_plane = ironlake_update_plane;
6458         } else {
6459                 dev_priv->display.dpms = i9xx_crtc_dpms;
6460                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6461                 dev_priv->display.off = i9xx_crtc_off;
6462                 dev_priv->display.update_plane = i9xx_update_plane;
6463         }
6464
6465         /* Returns the core display clock speed */
6466         if (IS_VALLEYVIEW(dev))
6467                 dev_priv->display.get_display_clock_speed =
6468                         valleyview_get_display_clock_speed;
6469         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6470                 dev_priv->display.get_display_clock_speed =
6471                         i945_get_display_clock_speed;
6472         else if (IS_I915G(dev))
6473                 dev_priv->display.get_display_clock_speed =
6474                         i915_get_display_clock_speed;
6475         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6476                 dev_priv->display.get_display_clock_speed =
6477                         i9xx_misc_get_display_clock_speed;
6478         else if (IS_I915GM(dev))
6479                 dev_priv->display.get_display_clock_speed =
6480                         i915gm_get_display_clock_speed;
6481         else if (IS_I865G(dev))
6482                 dev_priv->display.get_display_clock_speed =
6483                         i865_get_display_clock_speed;
6484         else if (IS_I85X(dev))
6485                 dev_priv->display.get_display_clock_speed =
6486                         i855_get_display_clock_speed;
6487         else /* 852, 830 */
6488                 dev_priv->display.get_display_clock_speed =
6489                         i830_get_display_clock_speed;
6490
6491         if (HAS_PCH_SPLIT(dev)) {
6492                 if (IS_GEN5(dev)) {
6493                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6494                         dev_priv->display.write_eld = ironlake_write_eld;
6495                 } else if (IS_GEN6(dev)) {
6496                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6497                         dev_priv->display.write_eld = ironlake_write_eld;
6498                 } else if (IS_IVYBRIDGE(dev)) {
6499                         /* FIXME: detect B0+ stepping and use auto training */
6500                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6501                         dev_priv->display.write_eld = ironlake_write_eld;
6502                 } else
6503                         dev_priv->display.update_wm = NULL;
6504         } else if (IS_VALLEYVIEW(dev)) {
6505                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6506                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6507         } else if (IS_G4X(dev)) {
6508                 dev_priv->display.write_eld = g4x_write_eld;
6509         }
6510
6511         /* Default just returns -ENODEV to indicate unsupported */
6512         dev_priv->display.queue_flip = intel_default_queue_flip;
6513
6514         switch (INTEL_INFO(dev)->gen) {
6515         case 2:
6516                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6517                 break;
6518
6519         case 3:
6520                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6521                 break;
6522
6523         case 4:
6524         case 5:
6525                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6526                 break;
6527
6528         case 6:
6529                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6530                 break;
6531         case 7:
6532                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6533                 break;
6534         }
6535 }
6536
6537 /*
6538  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6539  * resume, or other times.  This quirk makes sure that's the case for
6540  * affected systems.
6541  */
6542 static void quirk_pipea_force(struct drm_device *dev)
6543 {
6544         struct drm_i915_private *dev_priv = dev->dev_private;
6545
6546         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6547         DRM_INFO("applying pipe a force quirk\n");
6548 }
6549
6550 /*
6551  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6552  */
6553 static void quirk_ssc_force_disable(struct drm_device *dev)
6554 {
6555         struct drm_i915_private *dev_priv = dev->dev_private;
6556         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6557         DRM_INFO("applying lvds SSC disable quirk\n");
6558 }
6559
6560 /*
6561  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6562  * brightness value
6563  */
6564 static void quirk_invert_brightness(struct drm_device *dev)
6565 {
6566         struct drm_i915_private *dev_priv = dev->dev_private;
6567         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6568         DRM_INFO("applying inverted panel brightness quirk\n");
6569 }
6570
6571 struct intel_quirk {
6572         int device;
6573         int subsystem_vendor;
6574         int subsystem_device;
6575         void (*hook)(struct drm_device *dev);
6576 };
6577
6578 static struct intel_quirk intel_quirks[] = {
6579         /* HP Mini needs pipe A force quirk (LP: #322104) */
6580         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6581
6582         /* Thinkpad R31 needs pipe A force quirk */
6583         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6584         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6585         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6586
6587         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6588         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6589         /* ThinkPad X40 needs pipe A force quirk */
6590
6591         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6592         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6593
6594         /* 855 & before need to leave pipe A & dpll A up */
6595         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6596         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6597
6598         /* Lenovo U160 cannot use SSC on LVDS */
6599         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6600
6601         /* Sony Vaio Y cannot use SSC on LVDS */
6602         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6603
6604         /* Acer Aspire 5734Z must invert backlight brightness */
6605         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6606 };
6607
6608 static void intel_init_quirks(struct drm_device *dev)
6609 {
6610         struct pci_dev *d = dev->pdev;
6611         int i;
6612
6613         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6614                 struct intel_quirk *q = &intel_quirks[i];
6615
6616                 if (d->device == q->device &&
6617                     (d->subsystem_vendor == q->subsystem_vendor ||
6618                      q->subsystem_vendor == PCI_ANY_ID) &&
6619                     (d->subsystem_device == q->subsystem_device ||
6620                      q->subsystem_device == PCI_ANY_ID))
6621                         q->hook(dev);
6622         }
6623 }
6624
6625 /* Disable the VGA plane that we never use */
6626 static void i915_disable_vga(struct drm_device *dev)
6627 {
6628         struct drm_i915_private *dev_priv = dev->dev_private;
6629         u8 sr1;
6630         u32 vga_reg;
6631
6632         if (HAS_PCH_SPLIT(dev))
6633                 vga_reg = CPU_VGACNTRL;
6634         else
6635                 vga_reg = VGACNTRL;
6636
6637         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6638         outb(SR01, VGA_SR_INDEX);
6639         sr1 = inb(VGA_SR_DATA);
6640         outb(sr1 | 1<<5, VGA_SR_DATA);
6641         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6642         udelay(300);
6643
6644         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6645         POSTING_READ(vga_reg);
6646 }
6647
6648 static void ivb_pch_pwm_override(struct drm_device *dev)
6649 {
6650         struct drm_i915_private *dev_priv = dev->dev_private;
6651
6652         /*
6653          * IVB has CPU eDP backlight regs too, set things up to let the
6654          * PCH regs control the backlight
6655          */
6656         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6657         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6658         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6659 }
6660
6661 void intel_modeset_init_hw(struct drm_device *dev)
6662 {
6663         struct drm_i915_private *dev_priv = dev->dev_private;
6664
6665         intel_init_clock_gating(dev);
6666
6667         if (IS_IRONLAKE_M(dev)) {
6668                 ironlake_enable_drps(dev);
6669                 intel_init_emon(dev);
6670         }
6671
6672         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6673                 gen6_enable_rps(dev_priv);
6674                 gen6_update_ring_freq(dev_priv);
6675         }
6676
6677         if (IS_IVYBRIDGE(dev))
6678                 ivb_pch_pwm_override(dev);
6679 }
6680
6681 void intel_modeset_init(struct drm_device *dev)
6682 {
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684         int i, ret;
6685
6686         drm_mode_config_init(dev);
6687
6688         dev->mode_config.min_width = 0;
6689         dev->mode_config.min_height = 0;
6690
6691         dev->mode_config.preferred_depth = 24;
6692         dev->mode_config.prefer_shadow = 1;
6693
6694         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6695
6696         intel_init_quirks(dev);
6697
6698         intel_init_pm(dev);
6699
6700         intel_init_display(dev);
6701
6702         if (IS_GEN2(dev)) {
6703                 dev->mode_config.max_width = 2048;
6704                 dev->mode_config.max_height = 2048;
6705         } else if (IS_GEN3(dev)) {
6706                 dev->mode_config.max_width = 4096;
6707                 dev->mode_config.max_height = 4096;
6708         } else {
6709                 dev->mode_config.max_width = 8192;
6710                 dev->mode_config.max_height = 8192;
6711         }
6712         dev->mode_config.fb_base = dev->agp->base;
6713
6714         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6715                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6716
6717         for (i = 0; i < dev_priv->num_pipe; i++) {
6718                 intel_crtc_init(dev, i);
6719                 ret = intel_plane_init(dev, i);
6720                 if (ret)
6721                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6722         }
6723
6724         intel_pch_pll_init(dev);
6725
6726         /* Just disable it once at startup */
6727         i915_disable_vga(dev);
6728         intel_setup_outputs(dev);
6729
6730         intel_modeset_init_hw(dev);
6731
6732         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6733         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6734                     (unsigned long)dev);
6735 }
6736
6737 void intel_modeset_gem_init(struct drm_device *dev)
6738 {
6739         if (IS_IRONLAKE_M(dev))
6740                 ironlake_enable_rc6(dev);
6741
6742         intel_setup_overlay(dev);
6743 }
6744
6745 void intel_modeset_cleanup(struct drm_device *dev)
6746 {
6747         struct drm_i915_private *dev_priv = dev->dev_private;
6748         struct drm_crtc *crtc;
6749         struct intel_crtc *intel_crtc;
6750
6751         drm_kms_helper_poll_fini(dev);
6752         mutex_lock(&dev->struct_mutex);
6753
6754         intel_unregister_dsm_handler();
6755
6756
6757         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6758                 /* Skip inactive CRTCs */
6759                 if (!crtc->fb)
6760                         continue;
6761
6762                 intel_crtc = to_intel_crtc(crtc);
6763                 intel_increase_pllclock(crtc);
6764         }
6765
6766         intel_disable_fbc(dev);
6767
6768         if (IS_IRONLAKE_M(dev))
6769                 ironlake_disable_drps(dev);
6770         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6771                 gen6_disable_rps(dev);
6772
6773         if (IS_IRONLAKE_M(dev))
6774                 ironlake_disable_rc6(dev);
6775
6776         if (IS_VALLEYVIEW(dev))
6777                 vlv_init_dpio(dev);
6778
6779         mutex_unlock(&dev->struct_mutex);
6780
6781         /* Disable the irq before mode object teardown, for the irq might
6782          * enqueue unpin/hotplug work. */
6783         drm_irq_uninstall(dev);
6784         cancel_work_sync(&dev_priv->hotplug_work);
6785         cancel_work_sync(&dev_priv->rps_work);
6786
6787         /* flush any delayed tasks or pending work */
6788         flush_scheduled_work();
6789
6790         /* Shut off idle work before the crtcs get freed. */
6791         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6792                 intel_crtc = to_intel_crtc(crtc);
6793                 del_timer_sync(&intel_crtc->idle_timer);
6794         }
6795         del_timer_sync(&dev_priv->idle_timer);
6796         cancel_work_sync(&dev_priv->idle_work);
6797
6798         drm_mode_config_cleanup(dev);
6799 }
6800
6801 /*
6802  * Return which encoder is currently attached for connector.
6803  */
6804 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6805 {
6806         return &intel_attached_encoder(connector)->base;
6807 }
6808
6809 void intel_connector_attach_encoder(struct intel_connector *connector,
6810                                     struct intel_encoder *encoder)
6811 {
6812         connector->encoder = encoder;
6813         drm_mode_connector_attach_encoder(&connector->base,
6814                                           &encoder->base);
6815 }
6816
6817 /*
6818  * set vga decode state - true == enable VGA decode
6819  */
6820 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6821 {
6822         struct drm_i915_private *dev_priv = dev->dev_private;
6823         u16 gmch_ctrl;
6824
6825         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6826         if (state)
6827                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6828         else
6829                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6830         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6831         return 0;
6832 }
6833
6834 #ifdef CONFIG_DEBUG_FS
6835 #include <linux/seq_file.h>
6836
6837 struct intel_display_error_state {
6838         struct intel_cursor_error_state {
6839                 u32 control;
6840                 u32 position;
6841                 u32 base;
6842                 u32 size;
6843         } cursor[2];
6844
6845         struct intel_pipe_error_state {
6846                 u32 conf;
6847                 u32 source;
6848
6849                 u32 htotal;
6850                 u32 hblank;
6851                 u32 hsync;
6852                 u32 vtotal;
6853                 u32 vblank;
6854                 u32 vsync;
6855         } pipe[2];
6856
6857         struct intel_plane_error_state {
6858                 u32 control;
6859                 u32 stride;
6860                 u32 size;
6861                 u32 pos;
6862                 u32 addr;
6863                 u32 surface;
6864                 u32 tile_offset;
6865         } plane[2];
6866 };
6867
6868 struct intel_display_error_state *
6869 intel_display_capture_error_state(struct drm_device *dev)
6870 {
6871         drm_i915_private_t *dev_priv = dev->dev_private;
6872         struct intel_display_error_state *error;
6873         int i;
6874
6875         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6876         if (error == NULL)
6877                 return NULL;
6878
6879         for (i = 0; i < 2; i++) {
6880                 error->cursor[i].control = I915_READ(CURCNTR(i));
6881                 error->cursor[i].position = I915_READ(CURPOS(i));
6882                 error->cursor[i].base = I915_READ(CURBASE(i));
6883
6884                 error->plane[i].control = I915_READ(DSPCNTR(i));
6885                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6886                 error->plane[i].size = I915_READ(DSPSIZE(i));
6887                 error->plane[i].pos = I915_READ(DSPPOS(i));
6888                 error->plane[i].addr = I915_READ(DSPADDR(i));
6889                 if (INTEL_INFO(dev)->gen >= 4) {
6890                         error->plane[i].surface = I915_READ(DSPSURF(i));
6891                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6892                 }
6893
6894                 error->pipe[i].conf = I915_READ(PIPECONF(i));
6895                 error->pipe[i].source = I915_READ(PIPESRC(i));
6896                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6897                 error->pipe[i].hblank = I915_READ(HBLANK(i));
6898                 error->pipe[i].hsync = I915_READ(HSYNC(i));
6899                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6900                 error->pipe[i].vblank = I915_READ(VBLANK(i));
6901                 error->pipe[i].vsync = I915_READ(VSYNC(i));
6902         }
6903
6904         return error;
6905 }
6906
6907 void
6908 intel_display_print_error_state(struct seq_file *m,
6909                                 struct drm_device *dev,
6910                                 struct intel_display_error_state *error)
6911 {
6912         int i;
6913
6914         for (i = 0; i < 2; i++) {
6915                 seq_printf(m, "Pipe [%d]:\n", i);
6916                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
6917                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
6918                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
6919                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
6920                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
6921                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
6922                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
6923                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
6924
6925                 seq_printf(m, "Plane [%d]:\n", i);
6926                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
6927                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
6928                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
6929                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
6930                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
6931                 if (INTEL_INFO(dev)->gen >= 4) {
6932                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
6933                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
6934                 }
6935
6936                 seq_printf(m, "Cursor [%d]:\n", i);
6937                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
6938                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
6939                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
6940         }
6941 }
6942 #endif