drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_gem_dmabuf.h"
  40 #include "intel_dsi.h"
  41 #include "i915_trace.h"
  42 #include <drm/drm_atomic.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_dp_helper.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_plane_helper.h>
  47 #include <drm/drm_rect.h>
  48 #include <linux/dma_remapping.h>
  49 #include <linux/reservation.h>
  50
  51 static bool is_mmio_work(struct intel_flip_work *work)
  52 {
  53         return work->mmio_work.func;
  54 }
  55
  56 /* Primary plane formats for gen <= 3 */
  57 static const uint32_t i8xx_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB1555,
  61         DRM_FORMAT_XRGB8888,
  62 };
  63
  64 /* Primary plane formats for gen >= 4 */
  65 static const uint32_t i965_primary_formats[] = {
  66         DRM_FORMAT_C8,
  67         DRM_FORMAT_RGB565,
  68         DRM_FORMAT_XRGB8888,
  69         DRM_FORMAT_XBGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72 };
  73
  74 static const uint32_t skl_primary_formats[] = {
  75         DRM_FORMAT_C8,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_XBGR8888,
  79         DRM_FORMAT_ARGB8888,
  80         DRM_FORMAT_ABGR8888,
  81         DRM_FORMAT_XRGB2101010,
  82         DRM_FORMAT_XBGR2101010,
  83         DRM_FORMAT_YUYV,
  84         DRM_FORMAT_YVYU,
  85         DRM_FORMAT_UYVY,
  86         DRM_FORMAT_VYUY,
  87 };
  88
  89 /* Cursor formats */
  90 static const uint32_t intel_cursor_formats[] = {
  91         DRM_FORMAT_ARGB8888,
  92 };
  93
  94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  95                                 struct intel_crtc_state *pipe_config);
  96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  97                                    struct intel_crtc_state *pipe_config);
  98
  99 static int intel_framebuffer_init(struct drm_device *dev,
 100                                   struct intel_framebuffer *ifb,
 101                                   struct drm_mode_fb_cmd2 *mode_cmd,
 102                                   struct drm_i915_gem_object *obj);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 119         struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 126 static int bxt_calc_cdclk(int max_pixclk);
 127
 128 struct intel_limit {
 129         struct {
 130                 int min, max;
 131         } dot, vco, n, m, m1, m2, p, p1;
 132
 133         struct {
 134                 int dot_limit;
 135                 int p2_slow, p2_fast;
 136         } p2;
 137 };
 138
 139 /* returns HPLL frequency in kHz */
 140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 141 {
 142         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 143
 144         /* Obtain SKU information */
 145         mutex_lock(&dev_priv->sb_lock);
 146         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 147                 CCK_FUSE_HPLL_FREQ_MASK;
 148         mutex_unlock(&dev_priv->sb_lock);
 149
 150         return vco_freq[hpll_freq] * 1000;
 151 }
 152
 153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 154                       const char *name, u32 reg, int ref_freq)
 155 {
 156         u32 val;
 157         int divider;
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 170 }
 171
 172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 173                                   const char *name, u32 reg)
 174 {
 175         if (dev_priv->hpll_freq == 0)
 176                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 177
 178         return vlv_get_cck_clock(dev_priv, name, reg,
 179                                  dev_priv->hpll_freq);
 180 }
 181
 182 static int
 183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 184 {
 185         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 186 }
 187
 188 static int
 189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 190 {
 191         /* RAWCLK_FREQ_VLV register updated from power well code */
 192         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 193                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 194 }
 195
 196 static int
 197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 198 {
 199         uint32_t clkcfg;
 200
 201         /* hrawclock is 1/4 the FSB frequency */
 202         clkcfg = I915_READ(CLKCFG);
 203         switch (clkcfg & CLKCFG_FSB_MASK) {
 204         case CLKCFG_FSB_400:
 205                 return 100000;
 206         case CLKCFG_FSB_533:
 207                 return 133333;
 208         case CLKCFG_FSB_667:
 209                 return 166667;
 210         case CLKCFG_FSB_800:
 211                 return 200000;
 212         case CLKCFG_FSB_1067:
 213                 return 266667;
 214         case CLKCFG_FSB_1333:
 215                 return 333333;
 216         /* these two are just a guess; one of them might be right */
 217         case CLKCFG_FSB_1600:
 218         case CLKCFG_FSB_1600_ALT:
 219                 return 400000;
 220         default:
 221                 return 133333;
 222         }
 223 }
 224
 225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 226 {
 227         if (HAS_PCH_SPLIT(dev_priv))
 228                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 229         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 230                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 231         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 232                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 233         else
 234                 return; /* no rawclk on other platforms, or no need to know it */
 235
 236         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 237 }
 238
 239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 240 {
 241         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 242                 return;
 243
 244         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 245                                                       CCK_CZ_CLOCK_CONTROL);
 246
 247         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 248 }
 249
 250 static inline u32 /* units of 100MHz */
 251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 252                     const struct intel_crtc_state *pipe_config)
 253 {
 254         if (HAS_DDI(dev_priv))
 255                 return pipe_config->port_clock; /* SPLL */
 256         else if (IS_GEN5(dev_priv))
 257                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 258         else
 259                 return 270000;
 260 }
 261
 262 static const struct intel_limit intel_limits_i8xx_dac = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 2, .max = 33 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 4, .p2_fast = 2 },
 273 };
 274
 275 static const struct intel_limit intel_limits_i8xx_dvo = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 908000, .max = 1512000 },
 278         .n = { .min = 2, .max = 16 },
 279         .m = { .min = 96, .max = 140 },
 280         .m1 = { .min = 18, .max = 26 },
 281         .m2 = { .min = 6, .max = 16 },
 282         .p = { .min = 4, .max = 128 },
 283         .p1 = { .min = 2, .max = 33 },
 284         .p2 = { .dot_limit = 165000,
 285                 .p2_slow = 4, .p2_fast = 4 },
 286 };
 287
 288 static const struct intel_limit intel_limits_i8xx_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 908000, .max = 1512000 },
 291         .n = { .min = 2, .max = 16 },
 292         .m = { .min = 96, .max = 140 },
 293         .m1 = { .min = 18, .max = 26 },
 294         .m2 = { .min = 6, .max = 16 },
 295         .p = { .min = 4, .max = 128 },
 296         .p1 = { .min = 1, .max = 6 },
 297         .p2 = { .dot_limit = 165000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301 static const struct intel_limit intel_limits_i9xx_sdvo = {
 302         .dot = { .min = 20000, .max = 400000 },
 303         .vco = { .min = 1400000, .max = 2800000 },
 304         .n = { .min = 1, .max = 6 },
 305         .m = { .min = 70, .max = 120 },
 306         .m1 = { .min = 8, .max = 18 },
 307         .m2 = { .min = 3, .max = 7 },
 308         .p = { .min = 5, .max = 80 },
 309         .p1 = { .min = 1, .max = 8 },
 310         .p2 = { .dot_limit = 200000,
 311                 .p2_slow = 10, .p2_fast = 5 },
 312 };
 313
 314 static const struct intel_limit intel_limits_i9xx_lvds = {
 315         .dot = { .min = 20000, .max = 400000 },
 316         .vco = { .min = 1400000, .max = 2800000 },
 317         .n = { .min = 1, .max = 6 },
 318         .m = { .min = 70, .max = 120 },
 319         .m1 = { .min = 8, .max = 18 },
 320         .m2 = { .min = 3, .max = 7 },
 321         .p = { .min = 7, .max = 98 },
 322         .p1 = { .min = 1, .max = 8 },
 323         .p2 = { .dot_limit = 112000,
 324                 .p2_slow = 14, .p2_fast = 7 },
 325 };
 326
 327
 328 static const struct intel_limit intel_limits_g4x_sdvo = {
 329         .dot = { .min = 25000, .max = 270000 },
 330         .vco = { .min = 1750000, .max = 3500000},
 331         .n = { .min = 1, .max = 4 },
 332         .m = { .min = 104, .max = 138 },
 333         .m1 = { .min = 17, .max = 23 },
 334         .m2 = { .min = 5, .max = 11 },
 335         .p = { .min = 10, .max = 30 },
 336         .p1 = { .min = 1, .max = 3},
 337         .p2 = { .dot_limit = 270000,
 338                 .p2_slow = 10,
 339                 .p2_fast = 10
 340         },
 341 };
 342
 343 static const struct intel_limit intel_limits_g4x_hdmi = {
 344         .dot = { .min = 22000, .max = 400000 },
 345         .vco = { .min = 1750000, .max = 3500000},
 346         .n = { .min = 1, .max = 4 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 16, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 5, .max = 80 },
 351         .p1 = { .min = 1, .max = 8},
 352         .p2 = { .dot_limit = 165000,
 353                 .p2_slow = 10, .p2_fast = 5 },
 354 };
 355
 356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 357         .dot = { .min = 20000, .max = 115000 },
 358         .vco = { .min = 1750000, .max = 3500000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 104, .max = 138 },
 361         .m1 = { .min = 17, .max = 23 },
 362         .m2 = { .min = 5, .max = 11 },
 363         .p = { .min = 28, .max = 112 },
 364         .p1 = { .min = 2, .max = 8 },
 365         .p2 = { .dot_limit = 0,
 366                 .p2_slow = 14, .p2_fast = 14
 367         },
 368 };
 369
 370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 371         .dot = { .min = 80000, .max = 224000 },
 372         .vco = { .min = 1750000, .max = 3500000 },
 373         .n = { .min = 1, .max = 3 },
 374         .m = { .min = 104, .max = 138 },
 375         .m1 = { .min = 17, .max = 23 },
 376         .m2 = { .min = 5, .max = 11 },
 377         .p = { .min = 14, .max = 42 },
 378         .p1 = { .min = 2, .max = 6 },
 379         .p2 = { .dot_limit = 0,
 380                 .p2_slow = 7, .p2_fast = 7
 381         },
 382 };
 383
 384 static const struct intel_limit intel_limits_pineview_sdvo = {
 385         .dot = { .min = 20000, .max = 400000},
 386         .vco = { .min = 1700000, .max = 3500000 },
 387         /* Pineview's Ncounter is a ring counter */
 388         .n = { .min = 3, .max = 6 },
 389         .m = { .min = 2, .max = 256 },
 390         /* Pineview only has one combined m divider, which we treat as m2. */
 391         .m1 = { .min = 0, .max = 0 },
 392         .m2 = { .min = 0, .max = 254 },
 393         .p = { .min = 5, .max = 80 },
 394         .p1 = { .min = 1, .max = 8 },
 395         .p2 = { .dot_limit = 200000,
 396                 .p2_slow = 10, .p2_fast = 5 },
 397 };
 398
 399 static const struct intel_limit intel_limits_pineview_lvds = {
 400         .dot = { .min = 20000, .max = 400000 },
 401         .vco = { .min = 1700000, .max = 3500000 },
 402         .n = { .min = 3, .max = 6 },
 403         .m = { .min = 2, .max = 256 },
 404         .m1 = { .min = 0, .max = 0 },
 405         .m2 = { .min = 0, .max = 254 },
 406         .p = { .min = 7, .max = 112 },
 407         .p1 = { .min = 1, .max = 8 },
 408         .p2 = { .dot_limit = 112000,
 409                 .p2_slow = 14, .p2_fast = 14 },
 410 };
 411
 412 /* Ironlake / Sandybridge
 413  *
 414  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 415  * the range value for them is (actual_value - 2).
 416  */
 417 static const struct intel_limit intel_limits_ironlake_dac = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 5 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 5, .max = 80 },
 425         .p1 = { .min = 1, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 10, .p2_fast = 5 },
 428 };
 429
 430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 3 },
 434         .m = { .min = 79, .max = 118 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 127 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 56 },
 451         .p1 = { .min = 2, .max = 8 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 /* LVDS 100mhz refclk limits. */
 457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 458         .dot = { .min = 25000, .max = 350000 },
 459         .vco = { .min = 1760000, .max = 3510000 },
 460         .n = { .min = 1, .max = 2 },
 461         .m = { .min = 79, .max = 126 },
 462         .m1 = { .min = 12, .max = 22 },
 463         .m2 = { .min = 5, .max = 9 },
 464         .p = { .min = 28, .max = 112 },
 465         .p1 = { .min = 2, .max = 8 },
 466         .p2 = { .dot_limit = 225000,
 467                 .p2_slow = 14, .p2_fast = 14 },
 468 };
 469
 470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 471         .dot = { .min = 25000, .max = 350000 },
 472         .vco = { .min = 1760000, .max = 3510000 },
 473         .n = { .min = 1, .max = 3 },
 474         .m = { .min = 79, .max = 126 },
 475         .m1 = { .min = 12, .max = 22 },
 476         .m2 = { .min = 5, .max = 9 },
 477         .p = { .min = 14, .max = 42 },
 478         .p1 = { .min = 2, .max = 6 },
 479         .p2 = { .dot_limit = 225000,
 480                 .p2_slow = 7, .p2_fast = 7 },
 481 };
 482
 483 static const struct intel_limit intel_limits_vlv = {
 484          /*
 485           * These are the data rate limits (measured in fast clocks)
 486           * since those are the strictest limits we have. The fast
 487           * clock and actual rate limits are more relaxed, so checking
 488           * them would make no difference.
 489           */
 490         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 491         .vco = { .min = 4000000, .max = 6000000 },
 492         .n = { .min = 1, .max = 7 },
 493         .m1 = { .min = 2, .max = 3 },
 494         .m2 = { .min = 11, .max = 156 },
 495         .p1 = { .min = 2, .max = 3 },
 496         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 497 };
 498
 499 static const struct intel_limit intel_limits_chv = {
 500         /*
 501          * These are the data rate limits (measured in fast clocks)
 502          * since those are the strictest limits we have.  The fast
 503          * clock and actual rate limits are more relaxed, so checking
 504          * them would make no difference.
 505          */
 506         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 507         .vco = { .min = 4800000, .max = 6480000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 511         .p1 = { .min = 2, .max = 4 },
 512         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 513 };
 514
 515 static const struct intel_limit intel_limits_bxt = {
 516         /* FIXME: find real dot limits */
 517         .dot = { .min = 0, .max = INT_MAX },
 518         .vco = { .min = 4800000, .max = 6700000 },
 519         .n = { .min = 1, .max = 1 },
 520         .m1 = { .min = 2, .max = 2 },
 521         /* FIXME: find real m2 limits */
 522         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 523         .p1 = { .min = 2, .max = 4 },
 524         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 525 };
 526
 527 static bool
 528 needs_modeset(struct drm_crtc_state *state)
 529 {
 530         return drm_atomic_crtc_needs_modeset(state);
 531 }
 532
 533 /*
 534  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 535  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 536  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 537  * The helpers' return value is the rate of the clock that is fed to the
 538  * display engine's pipe which can be the above fast dot clock rate or a
 539  * divided-down version of it.
 540  */
 541 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 542 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 543 {
 544         clock->m = clock->m2 + 2;
 545         clock->p = clock->p1 * clock->p2;
 546         if (WARN_ON(clock->n == 0 || clock->p == 0))
 547                 return 0;
 548         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 549         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 550
 551         return clock->dot;
 552 }
 553
 554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 555 {
 556         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 557 }
 558
 559 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 560 {
 561         clock->m = i9xx_dpll_compute_m(clock);
 562         clock->p = clock->p1 * clock->p2;
 563         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 564                 return 0;
 565         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 566         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 567
 568         return clock->dot;
 569 }
 570
 571 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 572 {
 573         clock->m = clock->m1 * clock->m2;
 574         clock->p = clock->p1 * clock->p2;
 575         if (WARN_ON(clock->n == 0 || clock->p == 0))
 576                 return 0;
 577         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 578         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 579
 580         return clock->dot / 5;
 581 }
 582
 583 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 584 {
 585         clock->m = clock->m1 * clock->m2;
 586         clock->p = clock->p1 * clock->p2;
 587         if (WARN_ON(clock->n == 0 || clock->p == 0))
 588                 return 0;
 589         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 590                         clock->n << 22);
 591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 592
 593         return clock->dot / 5;
 594 }
 595
 596 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 597 /**
 598  * Returns whether the given set of divisors are valid for a given refclk with
 599  * the given connectors.
 600  */
 601
 602 static bool intel_PLL_is_valid(struct drm_device *dev,
 603                                const struct intel_limit *limit,
 604                                const struct dpll *clock)
 605 {
 606         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 607                 INTELPllInvalid("n out of range\n");
 608         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 609                 INTELPllInvalid("p1 out of range\n");
 610         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 611                 INTELPllInvalid("m2 out of range\n");
 612         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 613                 INTELPllInvalid("m1 out of range\n");
 614
 615         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 616             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 617                 if (clock->m1 <= clock->m2)
 618                         INTELPllInvalid("m1 <= m2\n");
 619
 620         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 621                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 622                         INTELPllInvalid("p out of range\n");
 623                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 624                         INTELPllInvalid("m out of range\n");
 625         }
 626
 627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 628                 INTELPllInvalid("vco out of range\n");
 629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 630          * connector, etc., rather than just a single range.
 631          */
 632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 633                 INTELPllInvalid("dot out of range\n");
 634
 635         return true;
 636 }
 637
 638 static int
 639 i9xx_select_p2_div(const struct intel_limit *limit,
 640                    const struct intel_crtc_state *crtc_state,
 641                    int target)
 642 {
 643         struct drm_device *dev = crtc_state->base.crtc->dev;
 644
 645         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 646                 /*
 647                  * For LVDS just rely on its current settings for dual-channel.
 648                  * We haven't figured out how to reliably set up different
 649                  * single/dual channel state, if we even can.
 650                  */
 651                 if (intel_is_dual_link_lvds(dev))
 652                         return limit->p2.p2_fast;
 653                 else
 654                         return limit->p2.p2_slow;
 655         } else {
 656                 if (target < limit->p2.dot_limit)
 657                         return limit->p2.p2_slow;
 658                 else
 659                         return limit->p2.p2_fast;
 660         }
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 i9xx_find_best_dpll(const struct intel_limit *limit,
 675                     struct intel_crtc_state *crtc_state,
 676                     int target, int refclk, struct dpll *match_clock,
 677                     struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         if (clock.m2 >= clock.m1)
 692                                 break;
 693                         for (clock.n = limit->n.min;
 694                              clock.n <= limit->n.max; clock.n++) {
 695                                 for (clock.p1 = limit->p1.min;
 696                                         clock.p1 <= limit->p1.max; clock.p1++) {
 697                                         int this_err;
 698
 699                                         i9xx_calc_dpll_params(refclk, &clock);
 700                                         if (!intel_PLL_is_valid(dev, limit,
 701                                                                 &clock))
 702                                                 continue;
 703                                         if (match_clock &&
 704                                             clock.p != match_clock->p)
 705                                                 continue;
 706
 707                                         this_err = abs(clock.dot - target);
 708                                         if (this_err < err) {
 709                                                 *best_clock = clock;
 710                                                 err = this_err;
 711                                         }
 712                                 }
 713                         }
 714                 }
 715         }
 716
 717         return (err != target);
 718 }
 719
 720 /*
 721  * Returns a set of divisors for the desired target clock with the given
 722  * refclk, or FALSE.  The returned values represent the clock equation:
 723  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 724  *
 725  * Target and reference clocks are specified in kHz.
 726  *
 727  * If match_clock is provided, then best_clock P divider must match the P
 728  * divider from @match_clock used for LVDS downclocking.
 729  */
 730 static bool
 731 pnv_find_best_dpll(const struct intel_limit *limit,
 732                    struct intel_crtc_state *crtc_state,
 733                    int target, int refclk, struct dpll *match_clock,
 734                    struct dpll *best_clock)
 735 {
 736         struct drm_device *dev = crtc_state->base.crtc->dev;
 737         struct dpll clock;
 738         int err = target;
 739
 740         memset(best_clock, 0, sizeof(*best_clock));
 741
 742         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 743
 744         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 745              clock.m1++) {
 746                 for (clock.m2 = limit->m2.min;
 747                      clock.m2 <= limit->m2.max; clock.m2++) {
 748                         for (clock.n = limit->n.min;
 749                              clock.n <= limit->n.max; clock.n++) {
 750                                 for (clock.p1 = limit->p1.min;
 751                                         clock.p1 <= limit->p1.max; clock.p1++) {
 752                                         int this_err;
 753
 754                                         pnv_calc_dpll_params(refclk, &clock);
 755                                         if (!intel_PLL_is_valid(dev, limit,
 756                                                                 &clock))
 757                                                 continue;
 758                                         if (match_clock &&
 759                                             clock.p != match_clock->p)
 760                                                 continue;
 761
 762                                         this_err = abs(clock.dot - target);
 763                                         if (this_err < err) {
 764                                                 *best_clock = clock;
 765                                                 err = this_err;
 766                                         }
 767                                 }
 768                         }
 769                 }
 770         }
 771
 772         return (err != target);
 773 }
 774
 775 /*
 776  * Returns a set of divisors for the desired target clock with the given
 777  * refclk, or FALSE.  The returned values represent the clock equation:
 778  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 779  *
 780  * Target and reference clocks are specified in kHz.
 781  *
 782  * If match_clock is provided, then best_clock P divider must match the P
 783  * divider from @match_clock used for LVDS downclocking.
 784  */
 785 static bool
 786 g4x_find_best_dpll(const struct intel_limit *limit,
 787                    struct intel_crtc_state *crtc_state,
 788                    int target, int refclk, struct dpll *match_clock,
 789                    struct dpll *best_clock)
 790 {
 791         struct drm_device *dev = crtc_state->base.crtc->dev;
 792         struct dpll clock;
 793         int max_n;
 794         bool found = false;
 795         /* approximately equals target * 0.00585 */
 796         int err_most = (target >> 8) + (target >> 9);
 797
 798         memset(best_clock, 0, sizeof(*best_clock));
 799
 800         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 801
 802         max_n = limit->n.max;
 803         /* based on hardware requirement, prefer smaller n to precision */
 804         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 805                 /* based on hardware requirement, prefere larger m1,m2 */
 806                 for (clock.m1 = limit->m1.max;
 807                      clock.m1 >= limit->m1.min; clock.m1--) {
 808                         for (clock.m2 = limit->m2.max;
 809                              clock.m2 >= limit->m2.min; clock.m2--) {
 810                                 for (clock.p1 = limit->p1.max;
 811                                      clock.p1 >= limit->p1.min; clock.p1--) {
 812                                         int this_err;
 813
 814                                         i9xx_calc_dpll_params(refclk, &clock);
 815                                         if (!intel_PLL_is_valid(dev, limit,
 816                                                                 &clock))
 817                                                 continue;
 818
 819                                         this_err = abs(clock.dot - target);
 820                                         if (this_err < err_most) {
 821                                                 *best_clock = clock;
 822                                                 err_most = this_err;
 823                                                 max_n = clock.n;
 824                                                 found = true;
 825                                         }
 826                                 }
 827                         }
 828                 }
 829         }
 830         return found;
 831 }
 832
 833 /*
 834  * Check if the calculated PLL configuration is more optimal compared to the
 835  * best configuration and error found so far. Return the calculated error.
 836  */
 837 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 838                                const struct dpll *calculated_clock,
 839                                const struct dpll *best_clock,
 840                                unsigned int best_error_ppm,
 841                                unsigned int *error_ppm)
 842 {
 843         /*
 844          * For CHV ignore the error and consider only the P value.
 845          * Prefer a bigger P value based on HW requirements.
 846          */
 847         if (IS_CHERRYVIEW(dev)) {
 848                 *error_ppm = 0;
 849
 850                 return calculated_clock->p > best_clock->p;
 851         }
 852
 853         if (WARN_ON_ONCE(!target_freq))
 854                 return false;
 855
 856         *error_ppm = div_u64(1000000ULL *
 857                                 abs(target_freq - calculated_clock->dot),
 858                              target_freq);
 859         /*
 860          * Prefer a better P value over a better (smaller) error if the error
 861          * is small. Ensure this preference for future configurations too by
 862          * setting the error to 0.
 863          */
 864         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 865                 *error_ppm = 0;
 866
 867                 return true;
 868         }
 869
 870         return *error_ppm + 10 < best_error_ppm;
 871 }
 872
 873 /*
 874  * Returns a set of divisors for the desired target clock with the given
 875  * refclk, or FALSE.  The returned values represent the clock equation:
 876  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 877  */
 878 static bool
 879 vlv_find_best_dpll(const struct intel_limit *limit,
 880                    struct intel_crtc_state *crtc_state,
 881                    int target, int refclk, struct dpll *match_clock,
 882                    struct dpll *best_clock)
 883 {
 884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 885         struct drm_device *dev = crtc->base.dev;
 886         struct dpll clock;
 887         unsigned int bestppm = 1000000;
 888         /* min update 19.2 MHz */
 889         int max_n = min(limit->n.max, refclk / 19200);
 890         bool found = false;
 891
 892         target *= 5; /* fast clock */
 893
 894         memset(best_clock, 0, sizeof(*best_clock));
 895
 896         /* based on hardware requirement, prefer smaller n to precision */
 897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 898                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 899                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 900                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 901                                 clock.p = clock.p1 * clock.p2;
 902                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 903                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 904                                         unsigned int ppm;
 905
 906                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 907                                                                      refclk * clock.m1);
 908
 909                                         vlv_calc_dpll_params(refclk, &clock);
 910
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         if (!vlv_PLL_is_optimal(dev, target,
 916                                                                 &clock,
 917                                                                 best_clock,
 918                                                                 bestppm, &ppm))
 919                                                 continue;
 920
 921                                         *best_clock = clock;
 922                                         bestppm = ppm;
 923                                         found = true;
 924                                 }
 925                         }
 926                 }
 927         }
 928
 929         return found;
 930 }
 931
 932 /*
 933  * Returns a set of divisors for the desired target clock with the given
 934  * refclk, or FALSE.  The returned values represent the clock equation:
 935  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 936  */
 937 static bool
 938 chv_find_best_dpll(const struct intel_limit *limit,
 939                    struct intel_crtc_state *crtc_state,
 940                    int target, int refclk, struct dpll *match_clock,
 941                    struct dpll *best_clock)
 942 {
 943         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 944         struct drm_device *dev = crtc->base.dev;
 945         unsigned int best_error_ppm;
 946         struct dpll clock;
 947         uint64_t m2;
 948         int found = false;
 949
 950         memset(best_clock, 0, sizeof(*best_clock));
 951         best_error_ppm = 1000000;
 952
 953         /*
 954          * Based on hardware doc, the n always set to 1, and m1 always
 955          * set to 2.  If requires to support 200Mhz refclk, we need to
 956          * revisit this because n may not 1 anymore.
 957          */
 958         clock.n = 1, clock.m1 = 2;
 959         target *= 5;    /* fast clock */
 960
 961         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 962                 for (clock.p2 = limit->p2.p2_fast;
 963                                 clock.p2 >= limit->p2.p2_slow;
 964                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 965                         unsigned int error_ppm;
 966
 967                         clock.p = clock.p1 * clock.p2;
 968
 969                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 970                                         clock.n) << 22, refclk * clock.m1);
 971
 972                         if (m2 > INT_MAX/clock.m1)
 973                                 continue;
 974
 975                         clock.m2 = m2;
 976
 977                         chv_calc_dpll_params(refclk, &clock);
 978
 979                         if (!intel_PLL_is_valid(dev, limit, &clock))
 980                                 continue;
 981
 982                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 983                                                 best_error_ppm, &error_ppm))
 984                                 continue;
 985
 986                         *best_clock = clock;
 987                         best_error_ppm = error_ppm;
 988                         found = true;
 989                 }
 990         }
 991
 992         return found;
 993 }
 994
 995 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 996                         struct dpll *best_clock)
 997 {
 998         int refclk = 100000;
 999         const struct intel_limit *limit = &intel_limits_bxt;
1000
1001         return chv_find_best_dpll(limit, crtc_state,
1002                                   target_clock, refclk, NULL, best_clock);
1003 }
1004
1005 bool intel_crtc_active(struct drm_crtc *crtc)
1006 {
1007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008
1009         /* Be paranoid as we can arrive here with only partial
1010          * state retrieved from the hardware during setup.
1011          *
1012          * We can ditch the adjusted_mode.crtc_clock check as soon
1013          * as Haswell has gained clock readout/fastboot support.
1014          *
1015          * We can ditch the crtc->primary->fb check as soon as we can
1016          * properly reconstruct framebuffers.
1017          *
1018          * FIXME: The intel_crtc->active here should be switched to
1019          * crtc->state->active once we have proper CRTC states wired up
1020          * for atomic.
1021          */
1022         return intel_crtc->active && crtc->primary->state->fb &&
1023                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1024 }
1025
1026 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1027                                              enum pipe pipe)
1028 {
1029         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1031
1032         return intel_crtc->config->cpu_transcoder;
1033 }
1034
1035 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(dev);
1038         i915_reg_t reg = PIPEDSL(pipe);
1039         u32 line1, line2;
1040         u32 line_mask;
1041
1042         if (IS_GEN2(dev))
1043                 line_mask = DSL_LINEMASK_GEN2;
1044         else
1045                 line_mask = DSL_LINEMASK_GEN3;
1046
1047         line1 = I915_READ(reg) & line_mask;
1048         msleep(5);
1049         line2 = I915_READ(reg) & line_mask;
1050
1051         return line1 == line2;
1052 }
1053
1054 /*
1055  * intel_wait_for_pipe_off - wait for pipe to turn off
1056  * @crtc: crtc whose pipe to wait for
1057  *
1058  * After disabling a pipe, we can't wait for vblank in the usual way,
1059  * spinning on the vblank interrupt status bit, since we won't actually
1060  * see an interrupt when the pipe is disabled.
1061  *
1062  * On Gen4 and above:
1063  *   wait for the pipe register state bit to turn off
1064  *
1065  * Otherwise:
1066  *   wait for the display line value to settle (it usually
1067  *   ends up stopping at the start of the next frame).
1068  *
1069  */
1070 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1071 {
1072         struct drm_device *dev = crtc->base.dev;
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1075         enum pipe pipe = crtc->pipe;
1076
1077         if (INTEL_INFO(dev)->gen >= 4) {
1078                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1079
1080                 /* Wait for the Pipe State to go off */
1081                 if (intel_wait_for_register(dev_priv,
1082                                             reg, I965_PIPECONF_ACTIVE, 0,
1083                                             100))
1084                         WARN(1, "pipe_off wait timed out\n");
1085         } else {
1086                 /* Wait for the display line to settle */
1087                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1088                         WARN(1, "pipe_off wait timed out\n");
1089         }
1090 }
1091
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094                 enum pipe pipe, bool state)
1095 {
1096         u32 val;
1097         bool cur_state;
1098
1099         val = I915_READ(DPLL(pipe));
1100         cur_state = !!(val & DPLL_VCO_ENABLE);
1101         I915_STATE_WARN(cur_state != state,
1102              "PLL state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105
1106 /* XXX: the dsi pll is shared between MIPI DSI ports */
1107 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111
1112         mutex_lock(&dev_priv->sb_lock);
1113         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1114         mutex_unlock(&dev_priv->sb_lock);
1115
1116         cur_state = val & DSI_PLL_VCO_EN;
1117         I915_STATE_WARN(cur_state != state,
1118              "DSI PLL state assertion failure (expected %s, current %s)\n",
1119                         onoff(state), onoff(cur_state));
1120 }
1121
1122 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1123                           enum pipe pipe, bool state)
1124 {
1125         bool cur_state;
1126         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1127                                                                       pipe);
1128
1129         if (HAS_DDI(dev_priv)) {
1130                 /* DDI does not have a specific FDI_TX register */
1131                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1135                 cur_state = !!(val & FDI_TX_ENABLE);
1136         }
1137         I915_STATE_WARN(cur_state != state,
1138              "FDI TX state assertion failure (expected %s, current %s)\n",
1139                         onoff(state), onoff(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         u32 val;
1148         bool cur_state;
1149
1150         val = I915_READ(FDI_RX_CTL(pipe));
1151         cur_state = !!(val & FDI_RX_ENABLE);
1152         I915_STATE_WARN(cur_state != state,
1153              "FDI RX state assertion failure (expected %s, current %s)\n",
1154                         onoff(state), onoff(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160                                       enum pipe pipe)
1161 {
1162         u32 val;
1163
1164         /* ILK FDI PLL is always enabled */
1165         if (IS_GEN5(dev_priv))
1166                 return;
1167
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv))
1170                 return;
1171
1172         val = I915_READ(FDI_TX_CTL(pipe));
1173         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1174 }
1175
1176 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1177                        enum pipe pipe, bool state)
1178 {
1179         u32 val;
1180         bool cur_state;
1181
1182         val = I915_READ(FDI_RX_CTL(pipe));
1183         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184         I915_STATE_WARN(cur_state != state,
1185              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186                         onoff(state), onoff(cur_state));
1187 }
1188
1189 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190                            enum pipe pipe)
1191 {
1192         struct drm_device *dev = &dev_priv->drm;
1193         i915_reg_t pp_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (WARN_ON(HAS_DDI(dev)))
1199                 return;
1200
1201         if (HAS_PCH_SPLIT(dev)) {
1202                 u32 port_sel;
1203
1204                 pp_reg = PCH_PP_CONTROL;
1205                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1206
1207                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1208                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1209                         panel_pipe = PIPE_B;
1210                 /* XXX: else fix for eDP */
1211         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1212                 /* presumably write lock depends on pipe, not port select */
1213                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1214                 panel_pipe = pipe;
1215         } else {
1216                 pp_reg = PP_CONTROL;
1217                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1218                         panel_pipe = PIPE_B;
1219         }
1220
1221         val = I915_READ(pp_reg);
1222         if (!(val & PANEL_POWER_ON) ||
1223             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1224                 locked = false;
1225
1226         I915_STATE_WARN(panel_pipe == pipe && locked,
1227              "panel assertion failure, pipe %c regs locked\n",
1228              pipe_name(pipe));
1229 }
1230
1231 static void assert_cursor(struct drm_i915_private *dev_priv,
1232                           enum pipe pipe, bool state)
1233 {
1234         struct drm_device *dev = &dev_priv->drm;
1235         bool cur_state;
1236
1237         if (IS_845G(dev) || IS_I865G(dev))
1238                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1239         else
1240                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244                         pipe_name(pipe), onoff(state), onoff(cur_state));
1245 }
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1248
1249 void assert_pipe(struct drm_i915_private *dev_priv,
1250                  enum pipe pipe, bool state)
1251 {
1252         bool cur_state;
1253         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1254                                                                       pipe);
1255         enum intel_display_power_domain power_domain;
1256
1257         /* if we need the pipe quirk it must be always on */
1258         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1259             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1260                 state = true;
1261
1262         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1263         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1264                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1265                 cur_state = !!(val & PIPECONF_ENABLE);
1266
1267                 intel_display_power_put(dev_priv, power_domain);
1268         } else {
1269                 cur_state = false;
1270         }
1271
1272         I915_STATE_WARN(cur_state != state,
1273              "pipe %c assertion failure (expected %s, current %s)\n",
1274                         pipe_name(pipe), onoff(state), onoff(cur_state));
1275 }
1276
1277 static void assert_plane(struct drm_i915_private *dev_priv,
1278                          enum plane plane, bool state)
1279 {
1280         u32 val;
1281         bool cur_state;
1282
1283         val = I915_READ(DSPCNTR(plane));
1284         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1285         I915_STATE_WARN(cur_state != state,
1286              "plane %c assertion failure (expected %s, current %s)\n",
1287                         plane_name(plane), onoff(state), onoff(cur_state));
1288 }
1289
1290 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1291 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1292
1293 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1294                                    enum pipe pipe)
1295 {
1296         struct drm_device *dev = &dev_priv->drm;
1297         int i;
1298
1299         /* Primary planes are fixed to pipes on gen4+ */
1300         if (INTEL_INFO(dev)->gen >= 4) {
1301                 u32 val = I915_READ(DSPCNTR(pipe));
1302                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1303                      "plane %c assertion failure, should be disabled but not\n",
1304                      plane_name(pipe));
1305                 return;
1306         }
1307
1308         /* Need to check both planes against the pipe */
1309         for_each_pipe(dev_priv, i) {
1310                 u32 val = I915_READ(DSPCNTR(i));
1311                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1312                         DISPPLANE_SEL_PIPE_SHIFT;
1313                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1314                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1315                      plane_name(i), pipe_name(pipe));
1316         }
1317 }
1318
1319 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1320                                     enum pipe pipe)
1321 {
1322         struct drm_device *dev = &dev_priv->drm;
1323         int sprite;
1324
1325         if (INTEL_INFO(dev)->gen >= 9) {
1326                 for_each_sprite(dev_priv, pipe, sprite) {
1327                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1328                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1329                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1330                              sprite, pipe_name(pipe));
1331                 }
1332         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1333                 for_each_sprite(dev_priv, pipe, sprite) {
1334                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1335                         I915_STATE_WARN(val & SP_ENABLE,
1336                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337                              sprite_name(pipe, sprite), pipe_name(pipe));
1338                 }
1339         } else if (INTEL_INFO(dev)->gen >= 7) {
1340                 u32 val = I915_READ(SPRCTL(pipe));
1341                 I915_STATE_WARN(val & SPRITE_ENABLE,
1342                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343                      plane_name(pipe), pipe_name(pipe));
1344         } else if (INTEL_INFO(dev)->gen >= 5) {
1345                 u32 val = I915_READ(DVSCNTR(pipe));
1346                 I915_STATE_WARN(val & DVS_ENABLE,
1347                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348                      plane_name(pipe), pipe_name(pipe));
1349         }
1350 }
1351
1352 static void assert_vblank_disabled(struct drm_crtc *crtc)
1353 {
1354         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1355                 drm_crtc_vblank_put(crtc);
1356 }
1357
1358 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359                                     enum pipe pipe)
1360 {
1361         u32 val;
1362         bool enabled;
1363
1364         val = I915_READ(PCH_TRANSCONF(pipe));
1365         enabled = !!(val & TRANS_ENABLE);
1366         I915_STATE_WARN(enabled,
1367              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1368              pipe_name(pipe));
1369 }
1370
1371 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1372                             enum pipe pipe, u32 port_sel, u32 val)
1373 {
1374         if ((val & DP_PORT_EN) == 0)
1375                 return false;
1376
1377         if (HAS_PCH_CPT(dev_priv)) {
1378                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1379                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380                         return false;
1381         } else if (IS_CHERRYVIEW(dev_priv)) {
1382                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386                         return false;
1387         }
1388         return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & SDVO_ENABLE) == 0)
1395                 return false;
1396
1397         if (HAS_PCH_CPT(dev_priv)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399                         return false;
1400         } else if (IS_CHERRYVIEW(dev_priv)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402                         return false;
1403         } else {
1404                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405                         return false;
1406         }
1407         return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411                               enum pipe pipe, u32 val)
1412 {
1413         if ((val & LVDS_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv)) {
1417                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418                         return false;
1419         } else {
1420                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421                         return false;
1422         }
1423         return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427                               enum pipe pipe, u32 val)
1428 {
1429         if ((val & ADPA_DAC_ENABLE) == 0)
1430                 return false;
1431         if (HAS_PCH_CPT(dev_priv)) {
1432                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433                         return false;
1434         } else {
1435                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436                         return false;
1437         }
1438         return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442                                    enum pipe pipe, i915_reg_t reg,
1443                                    u32 port_sel)
1444 {
1445         u32 val = I915_READ(reg);
1446         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1447              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448              i915_mmio_reg_offset(reg), pipe_name(pipe));
1449
1450         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1451              && (val & DP_PIPEB_SELECT),
1452              "IBX PCH dp port still using transcoder B\n");
1453 }
1454
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1456                                      enum pipe pipe, i915_reg_t reg)
1457 {
1458         u32 val = I915_READ(reg);
1459         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1460              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461              i915_mmio_reg_offset(reg), pipe_name(pipe));
1462
1463         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1464              && (val & SDVO_PIPE_B_SELECT),
1465              "IBX PCH hdmi port still using transcoder B\n");
1466 }
1467
1468 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469                                       enum pipe pipe)
1470 {
1471         u32 val;
1472
1473         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477         val = I915_READ(PCH_ADPA);
1478         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479              "PCH VGA enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         val = I915_READ(PCH_LVDS);
1483         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1484              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485              pipe_name(pipe));
1486
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 }
1491
1492 static void _vlv_enable_pll(struct intel_crtc *crtc,
1493                             const struct intel_crtc_state *pipe_config)
1494 {
1495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1496         enum pipe pipe = crtc->pipe;
1497
1498         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1499         POSTING_READ(DPLL(pipe));
1500         udelay(150);
1501
1502         if (intel_wait_for_register(dev_priv,
1503                                     DPLL(pipe),
1504                                     DPLL_LOCK_VLV,
1505                                     DPLL_LOCK_VLV,
1506                                     1))
1507                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1514         enum pipe pipe = crtc->pipe;
1515
1516         assert_pipe_disabled(dev_priv, pipe);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         assert_panel_unlocked(dev_priv, pipe);
1520
1521         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1522                 _vlv_enable_pll(crtc, pipe_config);
1523
1524         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1525         POSTING_READ(DPLL_MD(pipe));
1526 }
1527
1528
1529 static void _chv_enable_pll(struct intel_crtc *crtc,
1530                             const struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533         enum pipe pipe = crtc->pipe;
1534         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1535         u32 tmp;
1536
1537         mutex_lock(&dev_priv->sb_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         mutex_unlock(&dev_priv->sb_lock);
1545
1546         /*
1547          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1548          */
1549         udelay(1);
1550
1551         /* Enable PLL */
1552         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1553
1554         /* Check PLL is locked */
1555         if (intel_wait_for_register(dev_priv,
1556                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1557                                     1))
1558                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1559 }
1560
1561 static void chv_enable_pll(struct intel_crtc *crtc,
1562                            const struct intel_crtc_state *pipe_config)
1563 {
1564         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1565         enum pipe pipe = crtc->pipe;
1566
1567         assert_pipe_disabled(dev_priv, pipe);
1568
1569         /* PLL is protected by panel, make sure we can write it */
1570         assert_panel_unlocked(dev_priv, pipe);
1571
1572         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1573                 _chv_enable_pll(crtc, pipe_config);
1574
1575         if (pipe != PIPE_A) {
1576                 /*
1577                  * WaPixelRepeatModeFixForC0:chv
1578                  *
1579                  * DPLLCMD is AWOL. Use chicken bits to propagate
1580                  * the value from DPLLBMD to either pipe B or C.
1581                  */
1582                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1583                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1584                 I915_WRITE(CBR4_VLV, 0);
1585                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1586
1587                 /*
1588                  * DPLLB VGA mode also seems to cause problems.
1589                  * We should always have it disabled.
1590                  */
1591                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1592         } else {
1593                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1594                 POSTING_READ(DPLL_MD(pipe));
1595         }
1596 }
1597
1598 static int intel_num_dvo_pipes(struct drm_device *dev)
1599 {
1600         struct intel_crtc *crtc;
1601         int count = 0;
1602
1603         for_each_intel_crtc(dev, crtc) {
1604                 count += crtc->base.state->active &&
1605                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1606         }
1607
1608         return count;
1609 }
1610
1611 static void i9xx_enable_pll(struct intel_crtc *crtc)
1612 {
1613         struct drm_device *dev = crtc->base.dev;
1614         struct drm_i915_private *dev_priv = to_i915(dev);
1615         i915_reg_t reg = DPLL(crtc->pipe);
1616         u32 dpll = crtc->config->dpll_hw_state.dpll;
1617
1618         assert_pipe_disabled(dev_priv, crtc->pipe);
1619
1620         /* PLL is protected by panel, make sure we can write it */
1621         if (IS_MOBILE(dev) && !IS_I830(dev))
1622                 assert_panel_unlocked(dev_priv, crtc->pipe);
1623
1624         /* Enable DVO 2x clock on both PLLs if necessary */
1625         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1626                 /*
1627                  * It appears to be important that we don't enable this
1628                  * for the current pipe before otherwise configuring the
1629                  * PLL. No idea how this should be handled if multiple
1630                  * DVO outputs are enabled simultaneosly.
1631                  */
1632                 dpll |= DPLL_DVO_2X_MODE;
1633                 I915_WRITE(DPLL(!crtc->pipe),
1634                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1635         }
1636
1637         /*
1638          * Apparently we need to have VGA mode enabled prior to changing
1639          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1640          * dividers, even though the register value does change.
1641          */
1642         I915_WRITE(reg, 0);
1643
1644         I915_WRITE(reg, dpll);
1645
1646         /* Wait for the clocks to stabilize. */
1647         POSTING_READ(reg);
1648         udelay(150);
1649
1650         if (INTEL_INFO(dev)->gen >= 4) {
1651                 I915_WRITE(DPLL_MD(crtc->pipe),
1652                            crtc->config->dpll_hw_state.dpll_md);
1653         } else {
1654                 /* The pixel multiplier can only be updated once the
1655                  * DPLL is enabled and the clocks are stable.
1656                  *
1657                  * So write it again.
1658                  */
1659                 I915_WRITE(reg, dpll);
1660         }
1661
1662         /* We do this three times for luck */
1663         I915_WRITE(reg, dpll);
1664         POSTING_READ(reg);
1665         udelay(150); /* wait for warmup */
1666         I915_WRITE(reg, dpll);
1667         POSTING_READ(reg);
1668         udelay(150); /* wait for warmup */
1669         I915_WRITE(reg, dpll);
1670         POSTING_READ(reg);
1671         udelay(150); /* wait for warmup */
1672 }
1673
1674 /**
1675  * i9xx_disable_pll - disable a PLL
1676  * @dev_priv: i915 private structure
1677  * @pipe: pipe PLL to disable
1678  *
1679  * Disable the PLL for @pipe, making sure the pipe is off first.
1680  *
1681  * Note!  This is for pre-ILK only.
1682  */
1683 static void i9xx_disable_pll(struct intel_crtc *crtc)
1684 {
1685         struct drm_device *dev = crtc->base.dev;
1686         struct drm_i915_private *dev_priv = to_i915(dev);
1687         enum pipe pipe = crtc->pipe;
1688
1689         /* Disable DVO 2x clock on both PLLs if necessary */
1690         if (IS_I830(dev) &&
1691             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1692             !intel_num_dvo_pipes(dev)) {
1693                 I915_WRITE(DPLL(PIPE_B),
1694                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1695                 I915_WRITE(DPLL(PIPE_A),
1696                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1697         }
1698
1699         /* Don't disable pipe or pipe PLLs if needed */
1700         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1701             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1702                 return;
1703
1704         /* Make sure the pipe isn't still relying on us */
1705         assert_pipe_disabled(dev_priv, pipe);
1706
1707         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1708         POSTING_READ(DPLL(pipe));
1709 }
1710
1711 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713         u32 val;
1714
1715         /* Make sure the pipe isn't still relying on us */
1716         assert_pipe_disabled(dev_priv, pipe);
1717
1718         val = DPLL_INTEGRATED_REF_CLK_VLV |
1719                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1720         if (pipe != PIPE_A)
1721                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1722
1723         I915_WRITE(DPLL(pipe), val);
1724         POSTING_READ(DPLL(pipe));
1725 }
1726
1727 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1728 {
1729         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1730         u32 val;
1731
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734
1735         val = DPLL_SSC_REF_CLK_CHV |
1736                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737         if (pipe != PIPE_A)
1738                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740         I915_WRITE(DPLL(pipe), val);
1741         POSTING_READ(DPLL(pipe));
1742
1743         mutex_lock(&dev_priv->sb_lock);
1744
1745         /* Disable 10bit clock to display controller */
1746         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1747         val &= ~DPIO_DCLKP_EN;
1748         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1749
1750         mutex_unlock(&dev_priv->sb_lock);
1751 }
1752
1753 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1754                          struct intel_digital_port *dport,
1755                          unsigned int expected_mask)
1756 {
1757         u32 port_mask;
1758         i915_reg_t dpll_reg;
1759
1760         switch (dport->port) {
1761         case PORT_B:
1762                 port_mask = DPLL_PORTB_READY_MASK;
1763                 dpll_reg = DPLL(0);
1764                 break;
1765         case PORT_C:
1766                 port_mask = DPLL_PORTC_READY_MASK;
1767                 dpll_reg = DPLL(0);
1768                 expected_mask <<= 4;
1769                 break;
1770         case PORT_D:
1771                 port_mask = DPLL_PORTD_READY_MASK;
1772                 dpll_reg = DPIO_PHY_STATUS;
1773                 break;
1774         default:
1775                 BUG();
1776         }
1777
1778         if (intel_wait_for_register(dev_priv,
1779                                     dpll_reg, port_mask, expected_mask,
1780                                     1000))
1781                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1782                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1783 }
1784
1785 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1786                                            enum pipe pipe)
1787 {
1788         struct drm_device *dev = &dev_priv->drm;
1789         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         i915_reg_t reg;
1792         uint32_t val, pipeconf_val;
1793
1794         /* Make sure PCH DPLL is enabled */
1795         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1796
1797         /* FDI must be feeding us bits for PCH ports */
1798         assert_fdi_tx_enabled(dev_priv, pipe);
1799         assert_fdi_rx_enabled(dev_priv, pipe);
1800
1801         if (HAS_PCH_CPT(dev)) {
1802                 /* Workaround: Set the timing override bit before enabling the
1803                  * pch transcoder. */
1804                 reg = TRANS_CHICKEN2(pipe);
1805                 val = I915_READ(reg);
1806                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1807                 I915_WRITE(reg, val);
1808         }
1809
1810         reg = PCH_TRANSCONF(pipe);
1811         val = I915_READ(reg);
1812         pipeconf_val = I915_READ(PIPECONF(pipe));
1813
1814         if (HAS_PCH_IBX(dev_priv)) {
1815                 /*
1816                  * Make the BPC in transcoder be consistent with
1817                  * that in pipeconf reg. For HDMI we must use 8bpc
1818                  * here for both 8bpc and 12bpc.
1819                  */
1820                 val &= ~PIPECONF_BPC_MASK;
1821                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1822                         val |= PIPECONF_8BPC;
1823                 else
1824                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1825         }
1826
1827         val &= ~TRANS_INTERLACE_MASK;
1828         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1829                 if (HAS_PCH_IBX(dev_priv) &&
1830                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1831                         val |= TRANS_LEGACY_INTERLACED_ILK;
1832                 else
1833                         val |= TRANS_INTERLACED;
1834         else
1835                 val |= TRANS_PROGRESSIVE;
1836
1837         I915_WRITE(reg, val | TRANS_ENABLE);
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1840                                     100))
1841                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1842 }
1843
1844 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1845                                       enum transcoder cpu_transcoder)
1846 {
1847         u32 val, pipeconf_val;
1848
1849         /* FDI must be feeding us bits for PCH ports */
1850         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1851         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1852
1853         /* Workaround: set timing override bit. */
1854         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1855         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1857
1858         val = TRANS_ENABLE;
1859         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1860
1861         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1862             PIPECONF_INTERLACED_ILK)
1863                 val |= TRANS_INTERLACED;
1864         else
1865                 val |= TRANS_PROGRESSIVE;
1866
1867         I915_WRITE(LPT_TRANSCONF, val);
1868         if (intel_wait_for_register(dev_priv,
1869                                     LPT_TRANSCONF,
1870                                     TRANS_STATE_ENABLE,
1871                                     TRANS_STATE_ENABLE,
1872                                     100))
1873                 DRM_ERROR("Failed to enable PCH transcoder\n");
1874 }
1875
1876 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1877                                             enum pipe pipe)
1878 {
1879         struct drm_device *dev = &dev_priv->drm;
1880         i915_reg_t reg;
1881         uint32_t val;
1882
1883         /* FDI relies on the transcoder */
1884         assert_fdi_tx_disabled(dev_priv, pipe);
1885         assert_fdi_rx_disabled(dev_priv, pipe);
1886
1887         /* Ports must be off as well */
1888         assert_pch_ports_disabled(dev_priv, pipe);
1889
1890         reg = PCH_TRANSCONF(pipe);
1891         val = I915_READ(reg);
1892         val &= ~TRANS_ENABLE;
1893         I915_WRITE(reg, val);
1894         /* wait for PCH transcoder off, transcoder state */
1895         if (intel_wait_for_register(dev_priv,
1896                                     reg, TRANS_STATE_ENABLE, 0,
1897                                     50))
1898                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1899
1900         if (HAS_PCH_CPT(dev)) {
1901                 /* Workaround: Clear the timing override chicken bit again. */
1902                 reg = TRANS_CHICKEN2(pipe);
1903                 val = I915_READ(reg);
1904                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1905                 I915_WRITE(reg, val);
1906         }
1907 }
1908
1909 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1910 {
1911         u32 val;
1912
1913         val = I915_READ(LPT_TRANSCONF);
1914         val &= ~TRANS_ENABLE;
1915         I915_WRITE(LPT_TRANSCONF, val);
1916         /* wait for PCH transcoder off, transcoder state */
1917         if (intel_wait_for_register(dev_priv,
1918                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1919                                     50))
1920                 DRM_ERROR("Failed to disable PCH transcoder\n");
1921
1922         /* Workaround: clear timing override bit. */
1923         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1924         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1925         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1926 }
1927
1928 /**
1929  * intel_enable_pipe - enable a pipe, asserting requirements
1930  * @crtc: crtc responsible for the pipe
1931  *
1932  * Enable @crtc's pipe, making sure that various hardware specific requirements
1933  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1934  */
1935 static void intel_enable_pipe(struct intel_crtc *crtc)
1936 {
1937         struct drm_device *dev = crtc->base.dev;
1938         struct drm_i915_private *dev_priv = to_i915(dev);
1939         enum pipe pipe = crtc->pipe;
1940         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1941         enum pipe pch_transcoder;
1942         i915_reg_t reg;
1943         u32 val;
1944
1945         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1946
1947         assert_planes_disabled(dev_priv, pipe);
1948         assert_cursor_disabled(dev_priv, pipe);
1949         assert_sprites_disabled(dev_priv, pipe);
1950
1951         if (HAS_PCH_LPT(dev_priv))
1952                 pch_transcoder = TRANSCODER_A;
1953         else
1954                 pch_transcoder = pipe;
1955
1956         /*
1957          * A pipe without a PLL won't actually be able to drive bits from
1958          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1959          * need the check.
1960          */
1961         if (HAS_GMCH_DISPLAY(dev_priv))
1962                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1963                         assert_dsi_pll_enabled(dev_priv);
1964                 else
1965                         assert_pll_enabled(dev_priv, pipe);
1966         else {
1967                 if (crtc->config->has_pch_encoder) {
1968                         /* if driving the PCH, we need FDI enabled */
1969                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1970                         assert_fdi_tx_pll_enabled(dev_priv,
1971                                                   (enum pipe) cpu_transcoder);
1972                 }
1973                 /* FIXME: assert CPU port conditions for SNB+ */
1974         }
1975
1976         reg = PIPECONF(cpu_transcoder);
1977         val = I915_READ(reg);
1978         if (val & PIPECONF_ENABLE) {
1979                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1980                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1981                 return;
1982         }
1983
1984         I915_WRITE(reg, val | PIPECONF_ENABLE);
1985         POSTING_READ(reg);
1986
1987         /*
1988          * Until the pipe starts DSL will read as 0, which would cause
1989          * an apparent vblank timestamp jump, which messes up also the
1990          * frame count when it's derived from the timestamps. So let's
1991          * wait for the pipe to start properly before we call
1992          * drm_crtc_vblank_on()
1993          */
1994         if (dev->max_vblank_count == 0 &&
1995             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1996                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1997 }
1998
1999 /**
2000  * intel_disable_pipe - disable a pipe, asserting requirements
2001  * @crtc: crtc whose pipes is to be disabled
2002  *
2003  * Disable the pipe of @crtc, making sure that various hardware
2004  * specific requirements are met, if applicable, e.g. plane
2005  * disabled, panel fitter off, etc.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2012         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2013         enum pipe pipe = crtc->pipe;
2014         i915_reg_t reg;
2015         u32 val;
2016
2017         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2018
2019         /*
2020          * Make sure planes won't keep trying to pump pixels to us,
2021          * or we might hang the display.
2022          */
2023         assert_planes_disabled(dev_priv, pipe);
2024         assert_cursor_disabled(dev_priv, pipe);
2025         assert_sprites_disabled(dev_priv, pipe);
2026
2027         reg = PIPECONF(cpu_transcoder);
2028         val = I915_READ(reg);
2029         if ((val & PIPECONF_ENABLE) == 0)
2030                 return;
2031
2032         /*
2033          * Double wide has implications for planes
2034          * so best keep it disabled when not needed.
2035          */
2036         if (crtc->config->double_wide)
2037                 val &= ~PIPECONF_DOUBLE_WIDE;
2038
2039         /* Don't disable pipe or pipe PLLs if needed */
2040         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2041             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2042                 val &= ~PIPECONF_ENABLE;
2043
2044         I915_WRITE(reg, val);
2045         if ((val & PIPECONF_ENABLE) == 0)
2046                 intel_wait_for_pipe_off(crtc);
2047 }
2048
2049 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2050 {
2051         return IS_GEN2(dev_priv) ? 2048 : 4096;
2052 }
2053
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2055                                            uint64_t fb_modifier, unsigned int cpp)
2056 {
2057         switch (fb_modifier) {
2058         case DRM_FORMAT_MOD_NONE:
2059                 return cpp;
2060         case I915_FORMAT_MOD_X_TILED:
2061                 if (IS_GEN2(dev_priv))
2062                         return 128;
2063                 else
2064                         return 512;
2065         case I915_FORMAT_MOD_Y_TILED:
2066                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2067                         return 128;
2068                 else
2069                         return 512;
2070         case I915_FORMAT_MOD_Yf_TILED:
2071                 switch (cpp) {
2072                 case 1:
2073                         return 64;
2074                 case 2:
2075                 case 4:
2076                         return 128;
2077                 case 8:
2078                 case 16:
2079                         return 256;
2080                 default:
2081                         MISSING_CASE(cpp);
2082                         return cpp;
2083                 }
2084                 break;
2085         default:
2086                 MISSING_CASE(fb_modifier);
2087                 return cpp;
2088         }
2089 }
2090
2091 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2092                                uint64_t fb_modifier, unsigned int cpp)
2093 {
2094         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2095                 return 1;
2096         else
2097                 return intel_tile_size(dev_priv) /
2098                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2099 }
2100
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2103                             unsigned int *tile_width,
2104                             unsigned int *tile_height,
2105                             uint64_t fb_modifier,
2106                             unsigned int cpp)
2107 {
2108         unsigned int tile_width_bytes =
2109                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2110
2111         *tile_width = tile_width_bytes / cpp;
2112         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2113 }
2114
2115 unsigned int
2116 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2117                       uint32_t pixel_format, uint64_t fb_modifier)
2118 {
2119         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2120         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2121
2122         return ALIGN(height, tile_height);
2123 }
2124
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2126 {
2127         unsigned int size = 0;
2128         int i;
2129
2130         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2131                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2132
2133         return size;
2134 }
2135
2136 static void
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2138                         const struct drm_framebuffer *fb,
2139                         unsigned int rotation)
2140 {
2141         if (intel_rotation_90_or_270(rotation)) {
2142                 *view = i915_ggtt_view_rotated;
2143                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2144         } else {
2145                 *view = i915_ggtt_view_normal;
2146         }
2147 }
2148
2149 static void
2150 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2151                    struct drm_framebuffer *fb)
2152 {
2153         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2154         unsigned int tile_size, tile_width, tile_height, cpp;
2155
2156         tile_size = intel_tile_size(dev_priv);
2157
2158         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2159         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2160                         fb->modifier[0], cpp);
2161
2162         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2163         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2164
2165         if (info->pixel_format == DRM_FORMAT_NV12) {
2166                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2167                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2168                                 fb->modifier[1], cpp);
2169
2170                 info->uv_offset = fb->offsets[1];
2171                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2172                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2173         }
2174 }
2175
2176 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2177 {
2178         if (INTEL_INFO(dev_priv)->gen >= 9)
2179                 return 256 * 1024;
2180         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2181                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2182                 return 128 * 1024;
2183         else if (INTEL_INFO(dev_priv)->gen >= 4)
2184                 return 4 * 1024;
2185         else
2186                 return 0;
2187 }
2188
2189 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2190                                          uint64_t fb_modifier)
2191 {
2192         switch (fb_modifier) {
2193         case DRM_FORMAT_MOD_NONE:
2194                 return intel_linear_alignment(dev_priv);
2195         case I915_FORMAT_MOD_X_TILED:
2196                 if (INTEL_INFO(dev_priv)->gen >= 9)
2197                         return 256 * 1024;
2198                 return 0;
2199         case I915_FORMAT_MOD_Y_TILED:
2200         case I915_FORMAT_MOD_Yf_TILED:
2201                 return 1 * 1024 * 1024;
2202         default:
2203                 MISSING_CASE(fb_modifier);
2204                 return 0;
2205         }
2206 }
2207
2208 int
2209 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2210                            unsigned int rotation)
2211 {
2212         struct drm_device *dev = fb->dev;
2213         struct drm_i915_private *dev_priv = to_i915(dev);
2214         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2215         struct i915_ggtt_view view;
2216         u32 alignment;
2217         int ret;
2218
2219         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2220
2221         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2222
2223         intel_fill_fb_ggtt_view(&view, fb, rotation);
2224
2225         /* Note that the w/a also requires 64 PTE of padding following the
2226          * bo. We currently fill all unused PTE with the shadow page and so
2227          * we should always have valid PTE following the scanout preventing
2228          * the VT-d warning.
2229          */
2230         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2231                 alignment = 256 * 1024;
2232
2233         /*
2234          * Global gtt pte registers are special registers which actually forward
2235          * writes to a chunk of system memory. Which means that there is no risk
2236          * that the register values disappear as soon as we call
2237          * intel_runtime_pm_put(), so it is correct to wrap only the
2238          * pin/unpin/fence and not more.
2239          */
2240         intel_runtime_pm_get(dev_priv);
2241
2242         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2243                                                    &view);
2244         if (ret)
2245                 goto err_pm;
2246
2247         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2248          * fence, whereas 965+ only requires a fence if using
2249          * framebuffer compression.  For simplicity, we always install
2250          * a fence as the cost is not that onerous.
2251          */
2252         if (view.type == I915_GGTT_VIEW_NORMAL) {
2253                 ret = i915_gem_object_get_fence(obj);
2254                 if (ret == -EDEADLK) {
2255                         /*
2256                          * -EDEADLK means there are no free fences
2257                          * no pending flips.
2258                          *
2259                          * This is propagated to atomic, but it uses
2260                          * -EDEADLK to force a locking recovery, so
2261                          * change the returned error to -EBUSY.
2262                          */
2263                         ret = -EBUSY;
2264                         goto err_unpin;
2265                 } else if (ret)
2266                         goto err_unpin;
2267
2268                 i915_gem_object_pin_fence(obj);
2269         }
2270
2271         intel_runtime_pm_put(dev_priv);
2272         return 0;
2273
2274 err_unpin:
2275         i915_gem_object_unpin_from_display_plane(obj, &view);
2276 err_pm:
2277         intel_runtime_pm_put(dev_priv);
2278         return ret;
2279 }
2280
2281 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2282 {
2283         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2284         struct i915_ggtt_view view;
2285
2286         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2287
2288         intel_fill_fb_ggtt_view(&view, fb, rotation);
2289
2290         if (view.type == I915_GGTT_VIEW_NORMAL)
2291                 i915_gem_object_unpin_fence(obj);
2292
2293         i915_gem_object_unpin_from_display_plane(obj, &view);
2294 }
2295
2296 /*
2297  * Adjust the tile offset by moving the difference into
2298  * the x/y offsets.
2299  *
2300  * Input tile dimensions and pitch must already be
2301  * rotated to match x and y, and in pixel units.
2302  */
2303 static u32 intel_adjust_tile_offset(int *x, int *y,
2304                                     unsigned int tile_width,
2305                                     unsigned int tile_height,
2306                                     unsigned int tile_size,
2307                                     unsigned int pitch_tiles,
2308                                     u32 old_offset,
2309                                     u32 new_offset)
2310 {
2311         unsigned int tiles;
2312
2313         WARN_ON(old_offset & (tile_size - 1));
2314         WARN_ON(new_offset & (tile_size - 1));
2315         WARN_ON(new_offset > old_offset);
2316
2317         tiles = (old_offset - new_offset) / tile_size;
2318
2319         *y += tiles / pitch_tiles * tile_height;
2320         *x += tiles % pitch_tiles * tile_width;
2321
2322         return new_offset;
2323 }
2324
2325 /*
2326  * Computes the linear offset to the base tile and adjusts
2327  * x, y. bytes per pixel is assumed to be a power-of-two.
2328  *
2329  * In the 90/270 rotated case, x and y are assumed
2330  * to be already rotated to match the rotated GTT view, and
2331  * pitch is the tile_height aligned framebuffer height.
2332  */
2333 u32 intel_compute_tile_offset(int *x, int *y,
2334                               const struct drm_framebuffer *fb, int plane,
2335                               unsigned int pitch,
2336                               unsigned int rotation)
2337 {
2338         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2339         uint64_t fb_modifier = fb->modifier[plane];
2340         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2341         u32 offset, offset_aligned, alignment;
2342
2343         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2344         if (alignment)
2345                 alignment--;
2346
2347         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2348                 unsigned int tile_size, tile_width, tile_height;
2349                 unsigned int tile_rows, tiles, pitch_tiles;
2350
2351                 tile_size = intel_tile_size(dev_priv);
2352                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2353                                 fb_modifier, cpp);
2354
2355                 if (intel_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                          tile_size, pitch_tiles,
2373                                          offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 static int i9xx_format_to_fourcc(int format)
2386 {
2387         switch (format) {
2388         case DISPPLANE_8BPP:
2389                 return DRM_FORMAT_C8;
2390         case DISPPLANE_BGRX555:
2391                 return DRM_FORMAT_XRGB1555;
2392         case DISPPLANE_BGRX565:
2393                 return DRM_FORMAT_RGB565;
2394         default:
2395         case DISPPLANE_BGRX888:
2396                 return DRM_FORMAT_XRGB8888;
2397         case DISPPLANE_RGBX888:
2398                 return DRM_FORMAT_XBGR8888;
2399         case DISPPLANE_BGRX101010:
2400                 return DRM_FORMAT_XRGB2101010;
2401         case DISPPLANE_RGBX101010:
2402                 return DRM_FORMAT_XBGR2101010;
2403         }
2404 }
2405
2406 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2407 {
2408         switch (format) {
2409         case PLANE_CTL_FORMAT_RGB_565:
2410                 return DRM_FORMAT_RGB565;
2411         default:
2412         case PLANE_CTL_FORMAT_XRGB_8888:
2413                 if (rgb_order) {
2414                         if (alpha)
2415                                 return DRM_FORMAT_ABGR8888;
2416                         else
2417                                 return DRM_FORMAT_XBGR8888;
2418                 } else {
2419                         if (alpha)
2420                                 return DRM_FORMAT_ARGB8888;
2421                         else
2422                                 return DRM_FORMAT_XRGB8888;
2423                 }
2424         case PLANE_CTL_FORMAT_XRGB_2101010:
2425                 if (rgb_order)
2426                         return DRM_FORMAT_XBGR2101010;
2427                 else
2428                         return DRM_FORMAT_XRGB2101010;
2429         }
2430 }
2431
2432 static bool
2433 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2434                               struct intel_initial_plane_config *plane_config)
2435 {
2436         struct drm_device *dev = crtc->base.dev;
2437         struct drm_i915_private *dev_priv = to_i915(dev);
2438         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2439         struct drm_i915_gem_object *obj = NULL;
2440         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2441         struct drm_framebuffer *fb = &plane_config->fb->base;
2442         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2443         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2444                                     PAGE_SIZE);
2445
2446         size_aligned -= base_aligned;
2447
2448         if (plane_config->size == 0)
2449                 return false;
2450
2451         /* If the FB is too big, just don't use it since fbdev is not very
2452          * important and we should probably use that space with FBC or other
2453          * features. */
2454         if (size_aligned * 2 > ggtt->stolen_usable_size)
2455                 return false;
2456
2457         mutex_lock(&dev->struct_mutex);
2458
2459         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2460                                                              base_aligned,
2461                                                              base_aligned,
2462                                                              size_aligned);
2463         if (!obj) {
2464                 mutex_unlock(&dev->struct_mutex);
2465                 return false;
2466         }
2467
2468         obj->tiling_mode = plane_config->tiling;
2469         if (obj->tiling_mode == I915_TILING_X)
2470                 obj->stride = fb->pitches[0];
2471
2472         mode_cmd.pixel_format = fb->pixel_format;
2473         mode_cmd.width = fb->width;
2474         mode_cmd.height = fb->height;
2475         mode_cmd.pitches[0] = fb->pitches[0];
2476         mode_cmd.modifier[0] = fb->modifier[0];
2477         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2478
2479         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2480                                    &mode_cmd, obj)) {
2481                 DRM_DEBUG_KMS("intel fb init failed\n");
2482                 goto out_unref_obj;
2483         }
2484
2485         mutex_unlock(&dev->struct_mutex);
2486
2487         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2488         return true;
2489
2490 out_unref_obj:
2491         drm_gem_object_unreference(&obj->base);
2492         mutex_unlock(&dev->struct_mutex);
2493         return false;
2494 }
2495
2496 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2497 static void
2498 update_state_fb(struct drm_plane *plane)
2499 {
2500         if (plane->fb == plane->state->fb)
2501                 return;
2502
2503         if (plane->state->fb)
2504                 drm_framebuffer_unreference(plane->state->fb);
2505         plane->state->fb = plane->fb;
2506         if (plane->state->fb)
2507                 drm_framebuffer_reference(plane->state->fb);
2508 }
2509
2510 static void
2511 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2512                              struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = intel_crtc->base.dev;
2515         struct drm_i915_private *dev_priv = to_i915(dev);
2516         struct drm_crtc *c;
2517         struct intel_crtc *i;
2518         struct drm_i915_gem_object *obj;
2519         struct drm_plane *primary = intel_crtc->base.primary;
2520         struct drm_plane_state *plane_state = primary->state;
2521         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2522         struct intel_plane *intel_plane = to_intel_plane(primary);
2523         struct intel_plane_state *intel_state =
2524                 to_intel_plane_state(plane_state);
2525         struct drm_framebuffer *fb;
2526
2527         if (!plane_config->fb)
2528                 return;
2529
2530         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2531                 fb = &plane_config->fb->base;
2532                 goto valid_fb;
2533         }
2534
2535         kfree(plane_config->fb);
2536
2537         /*
2538          * Failed to alloc the obj, check to see if we should share
2539          * an fb with another CRTC instead
2540          */
2541         for_each_crtc(dev, c) {
2542                 i = to_intel_crtc(c);
2543
2544                 if (c == &intel_crtc->base)
2545                         continue;
2546
2547                 if (!i->active)
2548                         continue;
2549
2550                 fb = c->primary->fb;
2551                 if (!fb)
2552                         continue;
2553
2554                 obj = intel_fb_obj(fb);
2555                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2556                         drm_framebuffer_reference(fb);
2557                         goto valid_fb;
2558                 }
2559         }
2560
2561         /*
2562          * We've failed to reconstruct the BIOS FB.  Current display state
2563          * indicates that the primary plane is visible, but has a NULL FB,
2564          * which will lead to problems later if we don't fix it up.  The
2565          * simplest solution is to just disable the primary plane now and
2566          * pretend the BIOS never had it enabled.
2567          */
2568         to_intel_plane_state(plane_state)->visible = false;
2569         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2570         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2571         intel_plane->disable_plane(primary, &intel_crtc->base);
2572
2573         return;
2574
2575 valid_fb:
2576         plane_state->src_x = 0;
2577         plane_state->src_y = 0;
2578         plane_state->src_w = fb->width << 16;
2579         plane_state->src_h = fb->height << 16;
2580
2581         plane_state->crtc_x = 0;
2582         plane_state->crtc_y = 0;
2583         plane_state->crtc_w = fb->width;
2584         plane_state->crtc_h = fb->height;
2585
2586         intel_state->src.x1 = plane_state->src_x;
2587         intel_state->src.y1 = plane_state->src_y;
2588         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2589         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2590         intel_state->dst.x1 = plane_state->crtc_x;
2591         intel_state->dst.y1 = plane_state->crtc_y;
2592         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2593         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2594
2595         obj = intel_fb_obj(fb);
2596         if (obj->tiling_mode != I915_TILING_NONE)
2597                 dev_priv->preserve_bios_swizzle = true;
2598
2599         drm_framebuffer_reference(fb);
2600         primary->fb = primary->state->fb = fb;
2601         primary->crtc = primary->state->crtc = &intel_crtc->base;
2602         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2603         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2604 }
2605
2606 static void i9xx_update_primary_plane(struct drm_plane *primary,
2607                                       const struct intel_crtc_state *crtc_state,
2608                                       const struct intel_plane_state *plane_state)
2609 {
2610         struct drm_device *dev = primary->dev;
2611         struct drm_i915_private *dev_priv = to_i915(dev);
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2613         struct drm_framebuffer *fb = plane_state->base.fb;
2614         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2615         int plane = intel_crtc->plane;
2616         u32 linear_offset;
2617         u32 dspcntr;
2618         i915_reg_t reg = DSPCNTR(plane);
2619         unsigned int rotation = plane_state->base.rotation;
2620         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2621         int x = plane_state->src.x1 >> 16;
2622         int y = plane_state->src.y1 >> 16;
2623
2624         dspcntr = DISPPLANE_GAMMA_ENABLE;
2625
2626         dspcntr |= DISPLAY_PLANE_ENABLE;
2627
2628         if (INTEL_INFO(dev)->gen < 4) {
2629                 if (intel_crtc->pipe == PIPE_B)
2630                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2631
2632                 /* pipesrc and dspsize control the size that is scaled from,
2633                  * which should always be the user's requested size.
2634                  */
2635                 I915_WRITE(DSPSIZE(plane),
2636                            ((crtc_state->pipe_src_h - 1) << 16) |
2637                            (crtc_state->pipe_src_w - 1));
2638                 I915_WRITE(DSPPOS(plane), 0);
2639         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2640                 I915_WRITE(PRIMSIZE(plane),
2641                            ((crtc_state->pipe_src_h - 1) << 16) |
2642                            (crtc_state->pipe_src_w - 1));
2643                 I915_WRITE(PRIMPOS(plane), 0);
2644                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2645         }
2646
2647         switch (fb->pixel_format) {
2648         case DRM_FORMAT_C8:
2649                 dspcntr |= DISPPLANE_8BPP;
2650                 break;
2651         case DRM_FORMAT_XRGB1555:
2652                 dspcntr |= DISPPLANE_BGRX555;
2653                 break;
2654         case DRM_FORMAT_RGB565:
2655                 dspcntr |= DISPPLANE_BGRX565;
2656                 break;
2657         case DRM_FORMAT_XRGB8888:
2658                 dspcntr |= DISPPLANE_BGRX888;
2659                 break;
2660         case DRM_FORMAT_XBGR8888:
2661                 dspcntr |= DISPPLANE_RGBX888;
2662                 break;
2663         case DRM_FORMAT_XRGB2101010:
2664                 dspcntr |= DISPPLANE_BGRX101010;
2665                 break;
2666         case DRM_FORMAT_XBGR2101010:
2667                 dspcntr |= DISPPLANE_RGBX101010;
2668                 break;
2669         default:
2670                 BUG();
2671         }
2672
2673         if (INTEL_INFO(dev)->gen >= 4 &&
2674             obj->tiling_mode != I915_TILING_NONE)
2675                 dspcntr |= DISPPLANE_TILED;
2676
2677         if (IS_G4X(dev))
2678                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2679
2680         linear_offset = y * fb->pitches[0] + x * cpp;
2681
2682         if (INTEL_INFO(dev)->gen >= 4) {
2683                 intel_crtc->dspaddr_offset =
2684                         intel_compute_tile_offset(&x, &y, fb, 0,
2685                                                   fb->pitches[0], rotation);
2686                 linear_offset -= intel_crtc->dspaddr_offset;
2687         } else {
2688                 intel_crtc->dspaddr_offset = linear_offset;
2689         }
2690
2691         if (rotation == BIT(DRM_ROTATE_180)) {
2692                 dspcntr |= DISPPLANE_ROTATE_180;
2693
2694                 x += (crtc_state->pipe_src_w - 1);
2695                 y += (crtc_state->pipe_src_h - 1);
2696
2697                 /* Finding the last pixel of the last line of the display
2698                 data and adding to linear_offset*/
2699                 linear_offset +=
2700                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2701                         (crtc_state->pipe_src_w - 1) * cpp;
2702         }
2703
2704         intel_crtc->adjusted_x = x;
2705         intel_crtc->adjusted_y = y;
2706
2707         I915_WRITE(reg, dspcntr);
2708
2709         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2710         if (INTEL_INFO(dev)->gen >= 4) {
2711                 I915_WRITE(DSPSURF(plane),
2712                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2713                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2714                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2715         } else
2716                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2717         POSTING_READ(reg);
2718 }
2719
2720 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2721                                        struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int plane = intel_crtc->plane;
2727
2728         I915_WRITE(DSPCNTR(plane), 0);
2729         if (INTEL_INFO(dev_priv)->gen >= 4)
2730                 I915_WRITE(DSPSURF(plane), 0);
2731         else
2732                 I915_WRITE(DSPADDR(plane), 0);
2733         POSTING_READ(DSPCNTR(plane));
2734 }
2735
2736 static void ironlake_update_primary_plane(struct drm_plane *primary,
2737                                           const struct intel_crtc_state *crtc_state,
2738                                           const struct intel_plane_state *plane_state)
2739 {
2740         struct drm_device *dev = primary->dev;
2741         struct drm_i915_private *dev_priv = to_i915(dev);
2742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2743         struct drm_framebuffer *fb = plane_state->base.fb;
2744         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2745         int plane = intel_crtc->plane;
2746         u32 linear_offset;
2747         u32 dspcntr;
2748         i915_reg_t reg = DSPCNTR(plane);
2749         unsigned int rotation = plane_state->base.rotation;
2750         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2751         int x = plane_state->src.x1 >> 16;
2752         int y = plane_state->src.y1 >> 16;
2753
2754         dspcntr = DISPPLANE_GAMMA_ENABLE;
2755         dspcntr |= DISPLAY_PLANE_ENABLE;
2756
2757         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2758                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2759
2760         switch (fb->pixel_format) {
2761         case DRM_FORMAT_C8:
2762                 dspcntr |= DISPPLANE_8BPP;
2763                 break;
2764         case DRM_FORMAT_RGB565:
2765                 dspcntr |= DISPPLANE_BGRX565;
2766                 break;
2767         case DRM_FORMAT_XRGB8888:
2768                 dspcntr |= DISPPLANE_BGRX888;
2769                 break;
2770         case DRM_FORMAT_XBGR8888:
2771                 dspcntr |= DISPPLANE_RGBX888;
2772                 break;
2773         case DRM_FORMAT_XRGB2101010:
2774                 dspcntr |= DISPPLANE_BGRX101010;
2775                 break;
2776         case DRM_FORMAT_XBGR2101010:
2777                 dspcntr |= DISPPLANE_RGBX101010;
2778                 break;
2779         default:
2780                 BUG();
2781         }
2782
2783         if (obj->tiling_mode != I915_TILING_NONE)
2784                 dspcntr |= DISPPLANE_TILED;
2785
2786         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2787                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2788
2789         linear_offset = y * fb->pitches[0] + x * cpp;
2790         intel_crtc->dspaddr_offset =
2791                 intel_compute_tile_offset(&x, &y, fb, 0,
2792                                           fb->pitches[0], rotation);
2793         linear_offset -= intel_crtc->dspaddr_offset;
2794         if (rotation == BIT(DRM_ROTATE_180)) {
2795                 dspcntr |= DISPPLANE_ROTATE_180;
2796
2797                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2798                         x += (crtc_state->pipe_src_w - 1);
2799                         y += (crtc_state->pipe_src_h - 1);
2800
2801                         /* Finding the last pixel of the last line of the display
2802                         data and adding to linear_offset*/
2803                         linear_offset +=
2804                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2805                                 (crtc_state->pipe_src_w - 1) * cpp;
2806                 }
2807         }
2808
2809         intel_crtc->adjusted_x = x;
2810         intel_crtc->adjusted_y = y;
2811
2812         I915_WRITE(reg, dspcntr);
2813
2814         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2815         I915_WRITE(DSPSURF(plane),
2816                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2817         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2818                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2819         } else {
2820                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2821                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2822         }
2823         POSTING_READ(reg);
2824 }
2825
2826 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2827                               uint64_t fb_modifier, uint32_t pixel_format)
2828 {
2829         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2830                 return 64;
2831         } else {
2832                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2833
2834                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2835         }
2836 }
2837
2838 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2839                            struct drm_i915_gem_object *obj,
2840                            unsigned int plane)
2841 {
2842         struct i915_ggtt_view view;
2843         struct i915_vma *vma;
2844         u64 offset;
2845
2846         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2847                                 intel_plane->base.state->rotation);
2848
2849         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2850         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2851                 view.type))
2852                 return -1;
2853
2854         offset = vma->node.start;
2855
2856         if (plane == 1) {
2857                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2858                           PAGE_SIZE;
2859         }
2860
2861         WARN_ON(upper_32_bits(offset));
2862
2863         return lower_32_bits(offset);
2864 }
2865
2866 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2867 {
2868         struct drm_device *dev = intel_crtc->base.dev;
2869         struct drm_i915_private *dev_priv = to_i915(dev);
2870
2871         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2872         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2873         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2874 }
2875
2876 /*
2877  * This function detaches (aka. unbinds) unused scalers in hardware
2878  */
2879 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2880 {
2881         struct intel_crtc_scaler_state *scaler_state;
2882         int i;
2883
2884         scaler_state = &intel_crtc->config->scaler_state;
2885
2886         /* loop through and disable scalers that aren't in use */
2887         for (i = 0; i < intel_crtc->num_scalers; i++) {
2888                 if (!scaler_state->scalers[i].in_use)
2889                         skl_detach_scaler(intel_crtc, i);
2890         }
2891 }
2892
2893 u32 skl_plane_ctl_format(uint32_t pixel_format)
2894 {
2895         switch (pixel_format) {
2896         case DRM_FORMAT_C8:
2897                 return PLANE_CTL_FORMAT_INDEXED;
2898         case DRM_FORMAT_RGB565:
2899                 return PLANE_CTL_FORMAT_RGB_565;
2900         case DRM_FORMAT_XBGR8888:
2901                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2902         case DRM_FORMAT_XRGB8888:
2903                 return PLANE_CTL_FORMAT_XRGB_8888;
2904         /*
2905          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2906          * to be already pre-multiplied. We need to add a knob (or a different
2907          * DRM_FORMAT) for user-space to configure that.
2908          */
2909         case DRM_FORMAT_ABGR8888:
2910                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2911                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2912         case DRM_FORMAT_ARGB8888:
2913                 return PLANE_CTL_FORMAT_XRGB_8888 |
2914                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2915         case DRM_FORMAT_XRGB2101010:
2916                 return PLANE_CTL_FORMAT_XRGB_2101010;
2917         case DRM_FORMAT_XBGR2101010:
2918                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2919         case DRM_FORMAT_YUYV:
2920                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2921         case DRM_FORMAT_YVYU:
2922                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2923         case DRM_FORMAT_UYVY:
2924                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2925         case DRM_FORMAT_VYUY:
2926                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2927         default:
2928                 MISSING_CASE(pixel_format);
2929         }
2930
2931         return 0;
2932 }
2933
2934 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2935 {
2936         switch (fb_modifier) {
2937         case DRM_FORMAT_MOD_NONE:
2938                 break;
2939         case I915_FORMAT_MOD_X_TILED:
2940                 return PLANE_CTL_TILED_X;
2941         case I915_FORMAT_MOD_Y_TILED:
2942                 return PLANE_CTL_TILED_Y;
2943         case I915_FORMAT_MOD_Yf_TILED:
2944                 return PLANE_CTL_TILED_YF;
2945         default:
2946                 MISSING_CASE(fb_modifier);
2947         }
2948
2949         return 0;
2950 }
2951
2952 u32 skl_plane_ctl_rotation(unsigned int rotation)
2953 {
2954         switch (rotation) {
2955         case BIT(DRM_ROTATE_0):
2956                 break;
2957         /*
2958          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2959          * while i915 HW rotation is clockwise, thats why this swapping.
2960          */
2961         case BIT(DRM_ROTATE_90):
2962                 return PLANE_CTL_ROTATE_270;
2963         case BIT(DRM_ROTATE_180):
2964                 return PLANE_CTL_ROTATE_180;
2965         case BIT(DRM_ROTATE_270):
2966                 return PLANE_CTL_ROTATE_90;
2967         default:
2968                 MISSING_CASE(rotation);
2969         }
2970
2971         return 0;
2972 }
2973
2974 static void skylake_update_primary_plane(struct drm_plane *plane,
2975                                          const struct intel_crtc_state *crtc_state,
2976                                          const struct intel_plane_state *plane_state)
2977 {
2978         struct drm_device *dev = plane->dev;
2979         struct drm_i915_private *dev_priv = to_i915(dev);
2980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2981         struct drm_framebuffer *fb = plane_state->base.fb;
2982         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2983         int pipe = intel_crtc->pipe;
2984         u32 plane_ctl, stride_div, stride;
2985         u32 tile_height, plane_offset, plane_size;
2986         unsigned int rotation = plane_state->base.rotation;
2987         int x_offset, y_offset;
2988         u32 surf_addr;
2989         int scaler_id = plane_state->scaler_id;
2990         int src_x = plane_state->src.x1 >> 16;
2991         int src_y = plane_state->src.y1 >> 16;
2992         int src_w = drm_rect_width(&plane_state->src) >> 16;
2993         int src_h = drm_rect_height(&plane_state->src) >> 16;
2994         int dst_x = plane_state->dst.x1;
2995         int dst_y = plane_state->dst.y1;
2996         int dst_w = drm_rect_width(&plane_state->dst);
2997         int dst_h = drm_rect_height(&plane_state->dst);
2998
2999         plane_ctl = PLANE_CTL_ENABLE |
3000                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3001                     PLANE_CTL_PIPE_CSC_ENABLE;
3002
3003         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3004         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3005         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3006         plane_ctl |= skl_plane_ctl_rotation(rotation);
3007
3008         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3009                                                fb->pixel_format);
3010         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3011
3012         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3013
3014         if (intel_rotation_90_or_270(rotation)) {
3015                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3016
3017                 /* stride = Surface height in tiles */
3018                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3019                 stride = DIV_ROUND_UP(fb->height, tile_height);
3020                 x_offset = stride * tile_height - src_y - src_h;
3021                 y_offset = src_x;
3022                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3023         } else {
3024                 stride = fb->pitches[0] / stride_div;
3025                 x_offset = src_x;
3026                 y_offset = src_y;
3027                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3028         }
3029         plane_offset = y_offset << 16 | x_offset;
3030
3031         intel_crtc->adjusted_x = x_offset;
3032         intel_crtc->adjusted_y = y_offset;
3033
3034         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3035         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3036         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3037         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3038
3039         if (scaler_id >= 0) {
3040                 uint32_t ps_ctrl = 0;
3041
3042                 WARN_ON(!dst_w || !dst_h);
3043                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3044                         crtc_state->scaler_state.scalers[scaler_id].mode;
3045                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3046                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3047                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3048                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3049                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3050         } else {
3051                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3052         }
3053
3054         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3055
3056         POSTING_READ(PLANE_SURF(pipe, 0));
3057 }
3058
3059 static void skylake_disable_primary_plane(struct drm_plane *primary,
3060                                           struct drm_crtc *crtc)
3061 {
3062         struct drm_device *dev = crtc->dev;
3063         struct drm_i915_private *dev_priv = to_i915(dev);
3064         int pipe = to_intel_crtc(crtc)->pipe;
3065
3066         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3067         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3068         POSTING_READ(PLANE_SURF(pipe, 0));
3069 }
3070
3071 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3072 static int
3073 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3074                            int x, int y, enum mode_set_atomic state)
3075 {
3076         /* Support for kgdboc is disabled, this needs a major rework. */
3077         DRM_ERROR("legacy panic handler not supported any more.\n");
3078
3079         return -ENODEV;
3080 }
3081
3082 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3083 {
3084         struct intel_crtc *crtc;
3085
3086         for_each_intel_crtc(&dev_priv->drm, crtc)
3087                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3088 }
3089
3090 static void intel_update_primary_planes(struct drm_device *dev)
3091 {
3092         struct drm_crtc *crtc;
3093
3094         for_each_crtc(dev, crtc) {
3095                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3096                 struct intel_plane_state *plane_state;
3097
3098                 drm_modeset_lock_crtc(crtc, &plane->base);
3099                 plane_state = to_intel_plane_state(plane->base.state);
3100
3101                 if (plane_state->visible)
3102                         plane->update_plane(&plane->base,
3103                                             to_intel_crtc_state(crtc->state),
3104                                             plane_state);
3105
3106                 drm_modeset_unlock_crtc(crtc);
3107         }
3108 }
3109
3110 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3111 {
3112         /* no reset support for gen2 */
3113         if (IS_GEN2(dev_priv))
3114                 return;
3115
3116         /* reset doesn't touch the display */
3117         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3118                 return;
3119
3120         drm_modeset_lock_all(&dev_priv->drm);
3121         /*
3122          * Disabling the crtcs gracefully seems nicer. Also the
3123          * g33 docs say we should at least disable all the planes.
3124          */
3125         intel_display_suspend(&dev_priv->drm);
3126 }
3127
3128 void intel_finish_reset(struct drm_i915_private *dev_priv)
3129 {
3130         /*
3131          * Flips in the rings will be nuked by the reset,
3132          * so complete all pending flips so that user space
3133          * will get its events and not get stuck.
3134          */
3135         intel_complete_page_flips(dev_priv);
3136
3137         /* no reset support for gen2 */
3138         if (IS_GEN2(dev_priv))
3139                 return;
3140
3141         /* reset doesn't touch the display */
3142         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3143                 /*
3144                  * Flips in the rings have been nuked by the reset,
3145                  * so update the base address of all primary
3146                  * planes to the the last fb to make sure we're
3147                  * showing the correct fb after a reset.
3148                  *
3149                  * FIXME: Atomic will make this obsolete since we won't schedule
3150                  * CS-based flips (which might get lost in gpu resets) any more.
3151                  */
3152                 intel_update_primary_planes(&dev_priv->drm);
3153                 return;
3154         }
3155
3156         /*
3157          * The display has been reset as well,
3158          * so need a full re-initialization.
3159          */
3160         intel_runtime_pm_disable_interrupts(dev_priv);
3161         intel_runtime_pm_enable_interrupts(dev_priv);
3162
3163         intel_modeset_init_hw(&dev_priv->drm);
3164
3165         spin_lock_irq(&dev_priv->irq_lock);
3166         if (dev_priv->display.hpd_irq_setup)
3167                 dev_priv->display.hpd_irq_setup(dev_priv);
3168         spin_unlock_irq(&dev_priv->irq_lock);
3169
3170         intel_display_resume(&dev_priv->drm);
3171
3172         intel_hpd_init(dev_priv);
3173
3174         drm_modeset_unlock_all(&dev_priv->drm);
3175 }
3176
3177 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3178 {
3179         struct drm_device *dev = crtc->dev;
3180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181         unsigned reset_counter;
3182         bool pending;
3183
3184         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3185         if (intel_crtc->reset_counter != reset_counter)
3186                 return false;
3187
3188         spin_lock_irq(&dev->event_lock);
3189         pending = to_intel_crtc(crtc)->flip_work != NULL;
3190         spin_unlock_irq(&dev->event_lock);
3191
3192         return pending;
3193 }
3194
3195 static void intel_update_pipe_config(struct intel_crtc *crtc,
3196                                      struct intel_crtc_state *old_crtc_state)
3197 {
3198         struct drm_device *dev = crtc->base.dev;
3199         struct drm_i915_private *dev_priv = to_i915(dev);
3200         struct intel_crtc_state *pipe_config =
3201                 to_intel_crtc_state(crtc->base.state);
3202
3203         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3204         crtc->base.mode = crtc->base.state->mode;
3205
3206         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3207                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3208                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3209
3210         /*
3211          * Update pipe size and adjust fitter if needed: the reason for this is
3212          * that in compute_mode_changes we check the native mode (not the pfit
3213          * mode) to see if we can flip rather than do a full mode set. In the
3214          * fastboot case, we'll flip, but if we don't update the pipesrc and
3215          * pfit state, we'll end up with a big fb scanned out into the wrong
3216          * sized surface.
3217          */
3218
3219         I915_WRITE(PIPESRC(crtc->pipe),
3220                    ((pipe_config->pipe_src_w - 1) << 16) |
3221                    (pipe_config->pipe_src_h - 1));
3222
3223         /* on skylake this is done by detaching scalers */
3224         if (INTEL_INFO(dev)->gen >= 9) {
3225                 skl_detach_scalers(crtc);
3226
3227                 if (pipe_config->pch_pfit.enabled)
3228                         skylake_pfit_enable(crtc);
3229         } else if (HAS_PCH_SPLIT(dev)) {
3230                 if (pipe_config->pch_pfit.enabled)
3231                         ironlake_pfit_enable(crtc);
3232                 else if (old_crtc_state->pch_pfit.enabled)
3233                         ironlake_pfit_disable(crtc, true);
3234         }
3235 }
3236
3237 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = to_i915(dev);
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         int pipe = intel_crtc->pipe;
3243         i915_reg_t reg;
3244         u32 temp;
3245
3246         /* enable normal train */
3247         reg = FDI_TX_CTL(pipe);
3248         temp = I915_READ(reg);
3249         if (IS_IVYBRIDGE(dev)) {
3250                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3251                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3252         } else {
3253                 temp &= ~FDI_LINK_TRAIN_NONE;
3254                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3255         }
3256         I915_WRITE(reg, temp);
3257
3258         reg = FDI_RX_CTL(pipe);
3259         temp = I915_READ(reg);
3260         if (HAS_PCH_CPT(dev)) {
3261                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3262                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3263         } else {
3264                 temp &= ~FDI_LINK_TRAIN_NONE;
3265                 temp |= FDI_LINK_TRAIN_NONE;
3266         }
3267         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3268
3269         /* wait one idle pattern time */
3270         POSTING_READ(reg);
3271         udelay(1000);
3272
3273         /* IVB wants error correction enabled */
3274         if (IS_IVYBRIDGE(dev))
3275                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3276                            FDI_FE_ERRC_ENABLE);
3277 }
3278
3279 /* The FDI link training functions for ILK/Ibexpeak. */
3280 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3281 {
3282         struct drm_device *dev = crtc->dev;
3283         struct drm_i915_private *dev_priv = to_i915(dev);
3284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285         int pipe = intel_crtc->pipe;
3286         i915_reg_t reg;
3287         u32 temp, tries;
3288
3289         /* FDI needs bits from pipe first */
3290         assert_pipe_enabled(dev_priv, pipe);
3291
3292         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3293            for train result */
3294         reg = FDI_RX_IMR(pipe);
3295         temp = I915_READ(reg);
3296         temp &= ~FDI_RX_SYMBOL_LOCK;
3297         temp &= ~FDI_RX_BIT_LOCK;
3298         I915_WRITE(reg, temp);
3299         I915_READ(reg);
3300         udelay(150);
3301
3302         /* enable CPU FDI TX and PCH FDI RX */
3303         reg = FDI_TX_CTL(pipe);
3304         temp = I915_READ(reg);
3305         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3306         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3307         temp &= ~FDI_LINK_TRAIN_NONE;
3308         temp |= FDI_LINK_TRAIN_PATTERN_1;
3309         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3310
3311         reg = FDI_RX_CTL(pipe);
3312         temp = I915_READ(reg);
3313         temp &= ~FDI_LINK_TRAIN_NONE;
3314         temp |= FDI_LINK_TRAIN_PATTERN_1;
3315         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3316
3317         POSTING_READ(reg);
3318         udelay(150);
3319
3320         /* Ironlake workaround, enable clock pointer after FDI enable*/
3321         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3322         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3323                    FDI_RX_PHASE_SYNC_POINTER_EN);
3324
3325         reg = FDI_RX_IIR(pipe);
3326         for (tries = 0; tries < 5; tries++) {
3327                 temp = I915_READ(reg);
3328                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330                 if ((temp & FDI_RX_BIT_LOCK)) {
3331                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3332                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333                         break;
3334                 }
3335         }
3336         if (tries == 5)
3337                 DRM_ERROR("FDI train 1 fail!\n");
3338
3339         /* Train 2 */
3340         reg = FDI_TX_CTL(pipe);
3341         temp = I915_READ(reg);
3342         temp &= ~FDI_LINK_TRAIN_NONE;
3343         temp |= FDI_LINK_TRAIN_PATTERN_2;
3344         I915_WRITE(reg, temp);
3345
3346         reg = FDI_RX_CTL(pipe);
3347         temp = I915_READ(reg);
3348         temp &= ~FDI_LINK_TRAIN_NONE;
3349         temp |= FDI_LINK_TRAIN_PATTERN_2;
3350         I915_WRITE(reg, temp);
3351
3352         POSTING_READ(reg);
3353         udelay(150);
3354
3355         reg = FDI_RX_IIR(pipe);
3356         for (tries = 0; tries < 5; tries++) {
3357                 temp = I915_READ(reg);
3358                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3359
3360                 if (temp & FDI_RX_SYMBOL_LOCK) {
3361                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3362                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3363                         break;
3364                 }
3365         }
3366         if (tries == 5)
3367                 DRM_ERROR("FDI train 2 fail!\n");
3368
3369         DRM_DEBUG_KMS("FDI train done\n");
3370
3371 }
3372
3373 static const int snb_b_fdi_train_param[] = {
3374         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3375         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3376         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3377         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3378 };
3379
3380 /* The FDI link training functions for SNB/Cougarpoint. */
3381 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         struct drm_i915_private *dev_priv = to_i915(dev);
3385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386         int pipe = intel_crtc->pipe;
3387         i915_reg_t reg;
3388         u32 temp, i, retry;
3389
3390         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3391            for train result */
3392         reg = FDI_RX_IMR(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~FDI_RX_SYMBOL_LOCK;
3395         temp &= ~FDI_RX_BIT_LOCK;
3396         I915_WRITE(reg, temp);
3397
3398         POSTING_READ(reg);
3399         udelay(150);
3400
3401         /* enable CPU FDI TX and PCH FDI RX */
3402         reg = FDI_TX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3405         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3406         temp &= ~FDI_LINK_TRAIN_NONE;
3407         temp |= FDI_LINK_TRAIN_PATTERN_1;
3408         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3409         /* SNB-B */
3410         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3411         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3412
3413         I915_WRITE(FDI_RX_MISC(pipe),
3414                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3415
3416         reg = FDI_RX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         if (HAS_PCH_CPT(dev)) {
3419                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3420                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3421         } else {
3422                 temp &= ~FDI_LINK_TRAIN_NONE;
3423                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3424         }
3425         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427         POSTING_READ(reg);
3428         udelay(150);
3429
3430         for (i = 0; i < 4; i++) {
3431                 reg = FDI_TX_CTL(pipe);
3432                 temp = I915_READ(reg);
3433                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3434                 temp |= snb_b_fdi_train_param[i];
3435                 I915_WRITE(reg, temp);
3436
3437                 POSTING_READ(reg);
3438                 udelay(500);
3439
3440                 for (retry = 0; retry < 5; retry++) {
3441                         reg = FDI_RX_IIR(pipe);
3442                         temp = I915_READ(reg);
3443                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3444                         if (temp & FDI_RX_BIT_LOCK) {
3445                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3447                                 break;
3448                         }
3449                         udelay(50);
3450                 }
3451                 if (retry < 5)
3452                         break;
3453         }
3454         if (i == 4)
3455                 DRM_ERROR("FDI train 1 fail!\n");
3456
3457         /* Train 2 */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         temp &= ~FDI_LINK_TRAIN_NONE;
3461         temp |= FDI_LINK_TRAIN_PATTERN_2;
3462         if (IS_GEN6(dev)) {
3463                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3464                 /* SNB-B */
3465                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3466         }
3467         I915_WRITE(reg, temp);
3468
3469         reg = FDI_RX_CTL(pipe);
3470         temp = I915_READ(reg);
3471         if (HAS_PCH_CPT(dev)) {
3472                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3473                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3474         } else {
3475                 temp &= ~FDI_LINK_TRAIN_NONE;
3476                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3477         }
3478         I915_WRITE(reg, temp);
3479
3480         POSTING_READ(reg);
3481         udelay(150);
3482
3483         for (i = 0; i < 4; i++) {
3484                 reg = FDI_TX_CTL(pipe);
3485                 temp = I915_READ(reg);
3486                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3487                 temp |= snb_b_fdi_train_param[i];
3488                 I915_WRITE(reg, temp);
3489
3490                 POSTING_READ(reg);
3491                 udelay(500);
3492
3493                 for (retry = 0; retry < 5; retry++) {
3494                         reg = FDI_RX_IIR(pipe);
3495                         temp = I915_READ(reg);
3496                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497                         if (temp & FDI_RX_SYMBOL_LOCK) {
3498                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3499                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3500                                 break;
3501                         }
3502                         udelay(50);
3503                 }
3504                 if (retry < 5)
3505                         break;
3506         }
3507         if (i == 4)
3508                 DRM_ERROR("FDI train 2 fail!\n");
3509
3510         DRM_DEBUG_KMS("FDI train done.\n");
3511 }
3512
3513 /* Manual link training for Ivy Bridge A0 parts */
3514 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         struct drm_i915_private *dev_priv = to_i915(dev);
3518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3519         int pipe = intel_crtc->pipe;
3520         i915_reg_t reg;
3521         u32 temp, i, j;
3522
3523         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3524            for train result */
3525         reg = FDI_RX_IMR(pipe);
3526         temp = I915_READ(reg);
3527         temp &= ~FDI_RX_SYMBOL_LOCK;
3528         temp &= ~FDI_RX_BIT_LOCK;
3529         I915_WRITE(reg, temp);
3530
3531         POSTING_READ(reg);
3532         udelay(150);
3533
3534         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3535                       I915_READ(FDI_RX_IIR(pipe)));
3536
3537         /* Try each vswing and preemphasis setting twice before moving on */
3538         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3539                 /* disable first in case we need to retry */
3540                 reg = FDI_TX_CTL(pipe);
3541                 temp = I915_READ(reg);
3542                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3543                 temp &= ~FDI_TX_ENABLE;
3544                 I915_WRITE(reg, temp);
3545
3546                 reg = FDI_RX_CTL(pipe);
3547                 temp = I915_READ(reg);
3548                 temp &= ~FDI_LINK_TRAIN_AUTO;
3549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550                 temp &= ~FDI_RX_ENABLE;
3551                 I915_WRITE(reg, temp);
3552
3553                 /* enable CPU FDI TX and PCH FDI RX */
3554                 reg = FDI_TX_CTL(pipe);
3555                 temp = I915_READ(reg);
3556                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3557                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3558                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3559                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560                 temp |= snb_b_fdi_train_param[j/2];
3561                 temp |= FDI_COMPOSITE_SYNC;
3562                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3563
3564                 I915_WRITE(FDI_RX_MISC(pipe),
3565                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3566
3567                 reg = FDI_RX_CTL(pipe);
3568                 temp = I915_READ(reg);
3569                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3570                 temp |= FDI_COMPOSITE_SYNC;
3571                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3572
3573                 POSTING_READ(reg);
3574                 udelay(1); /* should be 0.5us */
3575
3576                 for (i = 0; i < 4; i++) {
3577                         reg = FDI_RX_IIR(pipe);
3578                         temp = I915_READ(reg);
3579                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3580
3581                         if (temp & FDI_RX_BIT_LOCK ||
3582                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3583                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3584                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3585                                               i);
3586                                 break;
3587                         }
3588                         udelay(1); /* should be 0.5us */
3589                 }
3590                 if (i == 4) {
3591                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3592                         continue;
3593                 }
3594
3595                 /* Train 2 */
3596                 reg = FDI_TX_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3599                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3600                 I915_WRITE(reg, temp);
3601
3602                 reg = FDI_RX_CTL(pipe);
3603                 temp = I915_READ(reg);
3604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3605                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3606                 I915_WRITE(reg, temp);
3607
3608                 POSTING_READ(reg);
3609                 udelay(2); /* should be 1.5us */
3610
3611                 for (i = 0; i < 4; i++) {
3612                         reg = FDI_RX_IIR(pipe);
3613                         temp = I915_READ(reg);
3614                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3615
3616                         if (temp & FDI_RX_SYMBOL_LOCK ||
3617                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3618                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3619                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3620                                               i);
3621                                 goto train_done;
3622                         }
3623                         udelay(2); /* should be 1.5us */
3624                 }
3625                 if (i == 4)
3626                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3627         }
3628
3629 train_done:
3630         DRM_DEBUG_KMS("FDI train done.\n");
3631 }
3632
3633 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3634 {
3635         struct drm_device *dev = intel_crtc->base.dev;
3636         struct drm_i915_private *dev_priv = to_i915(dev);
3637         int pipe = intel_crtc->pipe;
3638         i915_reg_t reg;
3639         u32 temp;
3640
3641         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3642         reg = FDI_RX_CTL(pipe);
3643         temp = I915_READ(reg);
3644         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3645         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3646         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3647         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3648
3649         POSTING_READ(reg);
3650         udelay(200);
3651
3652         /* Switch from Rawclk to PCDclk */
3653         temp = I915_READ(reg);
3654         I915_WRITE(reg, temp | FDI_PCDCLK);
3655
3656         POSTING_READ(reg);
3657         udelay(200);
3658
3659         /* Enable CPU FDI TX PLL, always on for Ironlake */
3660         reg = FDI_TX_CTL(pipe);
3661         temp = I915_READ(reg);
3662         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3663                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3664
3665                 POSTING_READ(reg);
3666                 udelay(100);
3667         }
3668 }
3669
3670 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3671 {
3672         struct drm_device *dev = intel_crtc->base.dev;
3673         struct drm_i915_private *dev_priv = to_i915(dev);
3674         int pipe = intel_crtc->pipe;
3675         i915_reg_t reg;
3676         u32 temp;
3677
3678         /* Switch from PCDclk to Rawclk */
3679         reg = FDI_RX_CTL(pipe);
3680         temp = I915_READ(reg);
3681         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3682
3683         /* Disable CPU FDI TX PLL */
3684         reg = FDI_TX_CTL(pipe);
3685         temp = I915_READ(reg);
3686         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3687
3688         POSTING_READ(reg);
3689         udelay(100);
3690
3691         reg = FDI_RX_CTL(pipe);
3692         temp = I915_READ(reg);
3693         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3694
3695         /* Wait for the clocks to turn off. */
3696         POSTING_READ(reg);
3697         udelay(100);
3698 }
3699
3700 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3701 {
3702         struct drm_device *dev = crtc->dev;
3703         struct drm_i915_private *dev_priv = to_i915(dev);
3704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705         int pipe = intel_crtc->pipe;
3706         i915_reg_t reg;
3707         u32 temp;
3708
3709         /* disable CPU FDI tx and PCH FDI rx */
3710         reg = FDI_TX_CTL(pipe);
3711         temp = I915_READ(reg);
3712         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3713         POSTING_READ(reg);
3714
3715         reg = FDI_RX_CTL(pipe);
3716         temp = I915_READ(reg);
3717         temp &= ~(0x7 << 16);
3718         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3719         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3720
3721         POSTING_READ(reg);
3722         udelay(100);
3723
3724         /* Ironlake workaround, disable clock pointer after downing FDI */
3725         if (HAS_PCH_IBX(dev))
3726                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3727
3728         /* still set train pattern 1 */
3729         reg = FDI_TX_CTL(pipe);
3730         temp = I915_READ(reg);
3731         temp &= ~FDI_LINK_TRAIN_NONE;
3732         temp |= FDI_LINK_TRAIN_PATTERN_1;
3733         I915_WRITE(reg, temp);
3734
3735         reg = FDI_RX_CTL(pipe);
3736         temp = I915_READ(reg);
3737         if (HAS_PCH_CPT(dev)) {
3738                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3739                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3740         } else {
3741                 temp &= ~FDI_LINK_TRAIN_NONE;
3742                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3743         }
3744         /* BPC in FDI rx is consistent with that in PIPECONF */
3745         temp &= ~(0x07 << 16);
3746         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3747         I915_WRITE(reg, temp);
3748
3749         POSTING_READ(reg);
3750         udelay(100);
3751 }
3752
3753 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3754 {
3755         struct intel_crtc *crtc;
3756
3757         /* Note that we don't need to be called with mode_config.lock here
3758          * as our list of CRTC objects is static for the lifetime of the
3759          * device and so cannot disappear as we iterate. Similarly, we can
3760          * happily treat the predicates as racy, atomic checks as userspace
3761          * cannot claim and pin a new fb without at least acquring the
3762          * struct_mutex and so serialising with us.
3763          */
3764         for_each_intel_crtc(dev, crtc) {
3765                 if (atomic_read(&crtc->unpin_work_count) == 0)
3766                         continue;
3767
3768                 if (crtc->flip_work)
3769                         intel_wait_for_vblank(dev, crtc->pipe);
3770
3771                 return true;
3772         }
3773
3774         return false;
3775 }
3776
3777 static void page_flip_completed(struct intel_crtc *intel_crtc)
3778 {
3779         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3780         struct intel_flip_work *work = intel_crtc->flip_work;
3781
3782         intel_crtc->flip_work = NULL;
3783
3784         if (work->event)
3785                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3786
3787         drm_crtc_vblank_put(&intel_crtc->base);
3788
3789         wake_up_all(&dev_priv->pending_flip_queue);
3790         queue_work(dev_priv->wq, &work->unpin_work);
3791
3792         trace_i915_flip_complete(intel_crtc->plane,
3793                                  work->pending_flip_obj);
3794 }
3795
3796 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3797 {
3798         struct drm_device *dev = crtc->dev;
3799         struct drm_i915_private *dev_priv = to_i915(dev);
3800         long ret;
3801
3802         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3803
3804         ret = wait_event_interruptible_timeout(
3805                                         dev_priv->pending_flip_queue,
3806                                         !intel_crtc_has_pending_flip(crtc),
3807                                         60*HZ);
3808
3809         if (ret < 0)
3810                 return ret;
3811
3812         if (ret == 0) {
3813                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814                 struct intel_flip_work *work;
3815
3816                 spin_lock_irq(&dev->event_lock);
3817                 work = intel_crtc->flip_work;
3818                 if (work && !is_mmio_work(work)) {
3819                         WARN_ONCE(1, "Removing stuck page flip\n");
3820                         page_flip_completed(intel_crtc);
3821                 }
3822                 spin_unlock_irq(&dev->event_lock);
3823         }
3824
3825         return 0;
3826 }
3827
3828 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3829 {
3830         u32 temp;
3831
3832         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833
3834         mutex_lock(&dev_priv->sb_lock);
3835
3836         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3837         temp |= SBI_SSCCTL_DISABLE;
3838         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3839
3840         mutex_unlock(&dev_priv->sb_lock);
3841 }
3842
3843 /* Program iCLKIP clock to the desired frequency */
3844 static void lpt_program_iclkip(struct drm_crtc *crtc)
3845 {
3846         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3847         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3848         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3849         u32 temp;
3850
3851         lpt_disable_iclkip(dev_priv);
3852
3853         /* The iCLK virtual clock root frequency is in MHz,
3854          * but the adjusted_mode->crtc_clock in in KHz. To get the
3855          * divisors, it is necessary to divide one by another, so we
3856          * convert the virtual clock precision to KHz here for higher
3857          * precision.
3858          */
3859         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3860                 u32 iclk_virtual_root_freq = 172800 * 1000;
3861                 u32 iclk_pi_range = 64;
3862                 u32 desired_divisor;
3863
3864                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3865                                                     clock << auxdiv);
3866                 divsel = (desired_divisor / iclk_pi_range) - 2;
3867                 phaseinc = desired_divisor % iclk_pi_range;
3868
3869                 /*
3870                  * Near 20MHz is a corner case which is
3871                  * out of range for the 7-bit divisor
3872                  */
3873                 if (divsel <= 0x7f)
3874                         break;
3875         }
3876
3877         /* This should not happen with any sane values */
3878         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3879                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3880         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3881                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3882
3883         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3884                         clock,
3885                         auxdiv,
3886                         divsel,
3887                         phasedir,
3888                         phaseinc);
3889
3890         mutex_lock(&dev_priv->sb_lock);
3891
3892         /* Program SSCDIVINTPHASE6 */
3893         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3894         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3895         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3896         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3897         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3898         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3899         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3900         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3901
3902         /* Program SSCAUXDIV */
3903         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3904         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3905         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3906         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3907
3908         /* Enable modulator and associated divider */
3909         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3910         temp &= ~SBI_SSCCTL_DISABLE;
3911         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3912
3913         mutex_unlock(&dev_priv->sb_lock);
3914
3915         /* Wait for initialization time */
3916         udelay(24);
3917
3918         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3919 }
3920
3921 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3922 {
3923         u32 divsel, phaseinc, auxdiv;
3924         u32 iclk_virtual_root_freq = 172800 * 1000;
3925         u32 iclk_pi_range = 64;
3926         u32 desired_divisor;
3927         u32 temp;
3928
3929         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3930                 return 0;
3931
3932         mutex_lock(&dev_priv->sb_lock);
3933
3934         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3935         if (temp & SBI_SSCCTL_DISABLE) {
3936                 mutex_unlock(&dev_priv->sb_lock);
3937                 return 0;
3938         }
3939
3940         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3941         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3942                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3943         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3944                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3945
3946         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3947         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3948                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3949
3950         mutex_unlock(&dev_priv->sb_lock);
3951
3952         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3953
3954         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3955                                  desired_divisor << auxdiv);
3956 }
3957
3958 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3959                                                 enum pipe pch_transcoder)
3960 {
3961         struct drm_device *dev = crtc->base.dev;
3962         struct drm_i915_private *dev_priv = to_i915(dev);
3963         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3964
3965         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3966                    I915_READ(HTOTAL(cpu_transcoder)));
3967         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3968                    I915_READ(HBLANK(cpu_transcoder)));
3969         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3970                    I915_READ(HSYNC(cpu_transcoder)));
3971
3972         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3973                    I915_READ(VTOTAL(cpu_transcoder)));
3974         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3975                    I915_READ(VBLANK(cpu_transcoder)));
3976         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3977                    I915_READ(VSYNC(cpu_transcoder)));
3978         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3979                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3980 }
3981
3982 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3983 {
3984         struct drm_i915_private *dev_priv = to_i915(dev);
3985         uint32_t temp;
3986
3987         temp = I915_READ(SOUTH_CHICKEN1);
3988         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3989                 return;
3990
3991         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3992         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3993
3994         temp &= ~FDI_BC_BIFURCATION_SELECT;
3995         if (enable)
3996                 temp |= FDI_BC_BIFURCATION_SELECT;
3997
3998         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3999         I915_WRITE(SOUTH_CHICKEN1, temp);
4000         POSTING_READ(SOUTH_CHICKEN1);
4001 }
4002
4003 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4004 {
4005         struct drm_device *dev = intel_crtc->base.dev;
4006
4007         switch (intel_crtc->pipe) {
4008         case PIPE_A:
4009                 break;
4010         case PIPE_B:
4011                 if (intel_crtc->config->fdi_lanes > 2)
4012                         cpt_set_fdi_bc_bifurcation(dev, false);
4013                 else
4014                         cpt_set_fdi_bc_bifurcation(dev, true);
4015
4016                 break;
4017         case PIPE_C:
4018                 cpt_set_fdi_bc_bifurcation(dev, true);
4019
4020                 break;
4021         default:
4022                 BUG();
4023         }
4024 }
4025
4026 /* Return which DP Port should be selected for Transcoder DP control */
4027 static enum port
4028 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4029 {
4030         struct drm_device *dev = crtc->dev;
4031         struct intel_encoder *encoder;
4032
4033         for_each_encoder_on_crtc(dev, crtc, encoder) {
4034                 if (encoder->type == INTEL_OUTPUT_DP ||
4035                     encoder->type == INTEL_OUTPUT_EDP)
4036                         return enc_to_dig_port(&encoder->base)->port;
4037         }
4038
4039         return -1;
4040 }
4041
4042 /*
4043  * Enable PCH resources required for PCH ports:
4044  *   - PCH PLLs
4045  *   - FDI training & RX/TX
4046  *   - update transcoder timings
4047  *   - DP transcoding bits
4048  *   - transcoder
4049  */
4050 static void ironlake_pch_enable(struct drm_crtc *crtc)
4051 {
4052         struct drm_device *dev = crtc->dev;
4053         struct drm_i915_private *dev_priv = to_i915(dev);
4054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4055         int pipe = intel_crtc->pipe;
4056         u32 temp;
4057
4058         assert_pch_transcoder_disabled(dev_priv, pipe);
4059
4060         if (IS_IVYBRIDGE(dev))
4061                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4062
4063         /* Write the TU size bits before fdi link training, so that error
4064          * detection works. */
4065         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4066                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4067
4068         /* For PCH output, training FDI link */
4069         dev_priv->display.fdi_link_train(crtc);
4070
4071         /* We need to program the right clock selection before writing the pixel
4072          * mutliplier into the DPLL. */
4073         if (HAS_PCH_CPT(dev)) {
4074                 u32 sel;
4075
4076                 temp = I915_READ(PCH_DPLL_SEL);
4077                 temp |= TRANS_DPLL_ENABLE(pipe);
4078                 sel = TRANS_DPLLB_SEL(pipe);
4079                 if (intel_crtc->config->shared_dpll ==
4080                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4081                         temp |= sel;
4082                 else
4083                         temp &= ~sel;
4084                 I915_WRITE(PCH_DPLL_SEL, temp);
4085         }
4086
4087         /* XXX: pch pll's can be enabled any time before we enable the PCH
4088          * transcoder, and we actually should do this to not upset any PCH
4089          * transcoder that already use the clock when we share it.
4090          *
4091          * Note that enable_shared_dpll tries to do the right thing, but
4092          * get_shared_dpll unconditionally resets the pll - we need that to have
4093          * the right LVDS enable sequence. */
4094         intel_enable_shared_dpll(intel_crtc);
4095
4096         /* set transcoder timing, panel must allow it */
4097         assert_panel_unlocked(dev_priv, pipe);
4098         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4099
4100         intel_fdi_normal_train(crtc);
4101
4102         /* For PCH DP, enable TRANS_DP_CTL */
4103         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4104                 const struct drm_display_mode *adjusted_mode =
4105                         &intel_crtc->config->base.adjusted_mode;
4106                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4107                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4108                 temp = I915_READ(reg);
4109                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4110                           TRANS_DP_SYNC_MASK |
4111                           TRANS_DP_BPC_MASK);
4112                 temp |= TRANS_DP_OUTPUT_ENABLE;
4113                 temp |= bpc << 9; /* same format but at 11:9 */
4114
4115                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4116                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4117                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4118                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4119
4120                 switch (intel_trans_dp_port_sel(crtc)) {
4121                 case PORT_B:
4122                         temp |= TRANS_DP_PORT_SEL_B;
4123                         break;
4124                 case PORT_C:
4125                         temp |= TRANS_DP_PORT_SEL_C;
4126                         break;
4127                 case PORT_D:
4128                         temp |= TRANS_DP_PORT_SEL_D;
4129                         break;
4130                 default:
4131                         BUG();
4132                 }
4133
4134                 I915_WRITE(reg, temp);
4135         }
4136
4137         ironlake_enable_pch_transcoder(dev_priv, pipe);
4138 }
4139
4140 static void lpt_pch_enable(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = to_i915(dev);
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4146
4147         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4148
4149         lpt_program_iclkip(crtc);
4150
4151         /* Set transcoder timing. */
4152         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4153
4154         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4155 }
4156
4157 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4158 {
4159         struct drm_i915_private *dev_priv = to_i915(dev);
4160         i915_reg_t dslreg = PIPEDSL(pipe);
4161         u32 temp;
4162
4163         temp = I915_READ(dslreg);
4164         udelay(500);
4165         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4166                 if (wait_for(I915_READ(dslreg) != temp, 5))
4167                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4168         }
4169 }
4170
4171 static int
4172 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4173                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4174                   int src_w, int src_h, int dst_w, int dst_h)
4175 {
4176         struct intel_crtc_scaler_state *scaler_state =
4177                 &crtc_state->scaler_state;
4178         struct intel_crtc *intel_crtc =
4179                 to_intel_crtc(crtc_state->base.crtc);
4180         int need_scaling;
4181
4182         need_scaling = intel_rotation_90_or_270(rotation) ?
4183                 (src_h != dst_w || src_w != dst_h):
4184                 (src_w != dst_w || src_h != dst_h);
4185
4186         /*
4187          * if plane is being disabled or scaler is no more required or force detach
4188          *  - free scaler binded to this plane/crtc
4189          *  - in order to do this, update crtc->scaler_usage
4190          *
4191          * Here scaler state in crtc_state is set free so that
4192          * scaler can be assigned to other user. Actual register
4193          * update to free the scaler is done in plane/panel-fit programming.
4194          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4195          */
4196         if (force_detach || !need_scaling) {
4197                 if (*scaler_id >= 0) {
4198                         scaler_state->scaler_users &= ~(1 << scaler_user);
4199                         scaler_state->scalers[*scaler_id].in_use = 0;
4200
4201                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4202                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4203                                 intel_crtc->pipe, scaler_user, *scaler_id,
4204                                 scaler_state->scaler_users);
4205                         *scaler_id = -1;
4206                 }
4207                 return 0;
4208         }
4209
4210         /* range checks */
4211         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4212                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4213
4214                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4215                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4216                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4217                         "size is out of scaler range\n",
4218                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4219                 return -EINVAL;
4220         }
4221
4222         /* mark this plane as a scaler user in crtc_state */
4223         scaler_state->scaler_users |= (1 << scaler_user);
4224         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4225                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4226                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4227                 scaler_state->scaler_users);
4228
4229         return 0;
4230 }
4231
4232 /**
4233  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4234  *
4235  * @state: crtc's scaler state
4236  *
4237  * Return
4238  *     0 - scaler_usage updated successfully
4239  *    error - requested scaling cannot be supported or other error condition
4240  */
4241 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4242 {
4243         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4244         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4245
4246         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4247                       intel_crtc->base.base.id, intel_crtc->base.name,
4248                       intel_crtc->pipe, SKL_CRTC_INDEX);
4249
4250         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4251                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4252                 state->pipe_src_w, state->pipe_src_h,
4253                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4254 }
4255
4256 /**
4257  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4258  *
4259  * @state: crtc's scaler state
4260  * @plane_state: atomic plane state to update
4261  *
4262  * Return
4263  *     0 - scaler_usage updated successfully
4264  *    error - requested scaling cannot be supported or other error condition
4265  */
4266 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4267                                    struct intel_plane_state *plane_state)
4268 {
4269
4270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4271         struct intel_plane *intel_plane =
4272                 to_intel_plane(plane_state->base.plane);
4273         struct drm_framebuffer *fb = plane_state->base.fb;
4274         int ret;
4275
4276         bool force_detach = !fb || !plane_state->visible;
4277
4278         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4279                       intel_plane->base.base.id, intel_plane->base.name,
4280                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4281
4282         ret = skl_update_scaler(crtc_state, force_detach,
4283                                 drm_plane_index(&intel_plane->base),
4284                                 &plane_state->scaler_id,
4285                                 plane_state->base.rotation,
4286                                 drm_rect_width(&plane_state->src) >> 16,
4287                                 drm_rect_height(&plane_state->src) >> 16,
4288                                 drm_rect_width(&plane_state->dst),
4289                                 drm_rect_height(&plane_state->dst));
4290
4291         if (ret || plane_state->scaler_id < 0)
4292                 return ret;
4293
4294         /* check colorkey */
4295         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4296                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4297                               intel_plane->base.base.id,
4298                               intel_plane->base.name);
4299                 return -EINVAL;
4300         }
4301
4302         /* Check src format */
4303         switch (fb->pixel_format) {
4304         case DRM_FORMAT_RGB565:
4305         case DRM_FORMAT_XBGR8888:
4306         case DRM_FORMAT_XRGB8888:
4307         case DRM_FORMAT_ABGR8888:
4308         case DRM_FORMAT_ARGB8888:
4309         case DRM_FORMAT_XRGB2101010:
4310         case DRM_FORMAT_XBGR2101010:
4311         case DRM_FORMAT_YUYV:
4312         case DRM_FORMAT_YVYU:
4313         case DRM_FORMAT_UYVY:
4314         case DRM_FORMAT_VYUY:
4315                 break;
4316         default:
4317                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4318                               intel_plane->base.base.id, intel_plane->base.name,
4319                               fb->base.id, fb->pixel_format);
4320                 return -EINVAL;
4321         }
4322
4323         return 0;
4324 }
4325
4326 static void skylake_scaler_disable(struct intel_crtc *crtc)
4327 {
4328         int i;
4329
4330         for (i = 0; i < crtc->num_scalers; i++)
4331                 skl_detach_scaler(crtc, i);
4332 }
4333
4334 static void skylake_pfit_enable(struct intel_crtc *crtc)
4335 {
4336         struct drm_device *dev = crtc->base.dev;
4337         struct drm_i915_private *dev_priv = to_i915(dev);
4338         int pipe = crtc->pipe;
4339         struct intel_crtc_scaler_state *scaler_state =
4340                 &crtc->config->scaler_state;
4341
4342         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4343
4344         if (crtc->config->pch_pfit.enabled) {
4345                 int id;
4346
4347                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4348                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4349                         return;
4350                 }
4351
4352                 id = scaler_state->scaler_id;
4353                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4354                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4355                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4356                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4357
4358                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4359         }
4360 }
4361
4362 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4363 {
4364         struct drm_device *dev = crtc->base.dev;
4365         struct drm_i915_private *dev_priv = to_i915(dev);
4366         int pipe = crtc->pipe;
4367
4368         if (crtc->config->pch_pfit.enabled) {
4369                 /* Force use of hard-coded filter coefficients
4370                  * as some pre-programmed values are broken,
4371                  * e.g. x201.
4372                  */
4373                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4374                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4375                                                  PF_PIPE_SEL_IVB(pipe));
4376                 else
4377                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4378                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4379                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4380         }
4381 }
4382
4383 void hsw_enable_ips(struct intel_crtc *crtc)
4384 {
4385         struct drm_device *dev = crtc->base.dev;
4386         struct drm_i915_private *dev_priv = to_i915(dev);
4387
4388         if (!crtc->config->ips_enabled)
4389                 return;
4390
4391         /*
4392          * We can only enable IPS after we enable a plane and wait for a vblank
4393          * This function is called from post_plane_update, which is run after
4394          * a vblank wait.
4395          */
4396
4397         assert_plane_enabled(dev_priv, crtc->plane);
4398         if (IS_BROADWELL(dev)) {
4399                 mutex_lock(&dev_priv->rps.hw_lock);
4400                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4401                 mutex_unlock(&dev_priv->rps.hw_lock);
4402                 /* Quoting Art Runyan: "its not safe to expect any particular
4403                  * value in IPS_CTL bit 31 after enabling IPS through the
4404                  * mailbox." Moreover, the mailbox may return a bogus state,
4405                  * so we need to just enable it and continue on.
4406                  */
4407         } else {
4408                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4409                 /* The bit only becomes 1 in the next vblank, so this wait here
4410                  * is essentially intel_wait_for_vblank. If we don't have this
4411                  * and don't wait for vblanks until the end of crtc_enable, then
4412                  * the HW state readout code will complain that the expected
4413                  * IPS_CTL value is not the one we read. */
4414                 if (intel_wait_for_register(dev_priv,
4415                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4416                                             50))
4417                         DRM_ERROR("Timed out waiting for IPS enable\n");
4418         }
4419 }
4420
4421 void hsw_disable_ips(struct intel_crtc *crtc)
4422 {
4423         struct drm_device *dev = crtc->base.dev;
4424         struct drm_i915_private *dev_priv = to_i915(dev);
4425
4426         if (!crtc->config->ips_enabled)
4427                 return;
4428
4429         assert_plane_enabled(dev_priv, crtc->plane);
4430         if (IS_BROADWELL(dev)) {
4431                 mutex_lock(&dev_priv->rps.hw_lock);
4432                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4433                 mutex_unlock(&dev_priv->rps.hw_lock);
4434                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4435                 if (intel_wait_for_register(dev_priv,
4436                                             IPS_CTL, IPS_ENABLE, 0,
4437                                             42))
4438                         DRM_ERROR("Timed out waiting for IPS disable\n");
4439         } else {
4440                 I915_WRITE(IPS_CTL, 0);
4441                 POSTING_READ(IPS_CTL);
4442         }
4443
4444         /* We need to wait for a vblank before we can disable the plane. */
4445         intel_wait_for_vblank(dev, crtc->pipe);
4446 }
4447
4448 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4449 {
4450         if (intel_crtc->overlay) {
4451                 struct drm_device *dev = intel_crtc->base.dev;
4452                 struct drm_i915_private *dev_priv = to_i915(dev);
4453
4454                 mutex_lock(&dev->struct_mutex);
4455                 dev_priv->mm.interruptible = false;
4456                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4457                 dev_priv->mm.interruptible = true;
4458                 mutex_unlock(&dev->struct_mutex);
4459         }
4460
4461         /* Let userspace switch the overlay on again. In most cases userspace
4462          * has to recompute where to put it anyway.
4463          */
4464 }
4465
4466 /**
4467  * intel_post_enable_primary - Perform operations after enabling primary plane
4468  * @crtc: the CRTC whose primary plane was just enabled
4469  *
4470  * Performs potentially sleeping operations that must be done after the primary
4471  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4472  * called due to an explicit primary plane update, or due to an implicit
4473  * re-enable that is caused when a sprite plane is updated to no longer
4474  * completely hide the primary plane.
4475  */
4476 static void
4477 intel_post_enable_primary(struct drm_crtc *crtc)
4478 {
4479         struct drm_device *dev = crtc->dev;
4480         struct drm_i915_private *dev_priv = to_i915(dev);
4481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4482         int pipe = intel_crtc->pipe;
4483
4484         /*
4485          * FIXME IPS should be fine as long as one plane is
4486          * enabled, but in practice it seems to have problems
4487          * when going from primary only to sprite only and vice
4488          * versa.
4489          */
4490         hsw_enable_ips(intel_crtc);
4491
4492         /*
4493          * Gen2 reports pipe underruns whenever all planes are disabled.
4494          * So don't enable underrun reporting before at least some planes
4495          * are enabled.
4496          * FIXME: Need to fix the logic to work when we turn off all planes
4497          * but leave the pipe running.
4498          */
4499         if (IS_GEN2(dev))
4500                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4501
4502         /* Underruns don't always raise interrupts, so check manually. */
4503         intel_check_cpu_fifo_underruns(dev_priv);
4504         intel_check_pch_fifo_underruns(dev_priv);
4505 }
4506
4507 /* FIXME move all this to pre_plane_update() with proper state tracking */
4508 static void
4509 intel_pre_disable_primary(struct drm_crtc *crtc)
4510 {
4511         struct drm_device *dev = crtc->dev;
4512         struct drm_i915_private *dev_priv = to_i915(dev);
4513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514         int pipe = intel_crtc->pipe;
4515
4516         /*
4517          * Gen2 reports pipe underruns whenever all planes are disabled.
4518          * So diasble underrun reporting before all the planes get disabled.
4519          * FIXME: Need to fix the logic to work when we turn off all planes
4520          * but leave the pipe running.
4521          */
4522         if (IS_GEN2(dev))
4523                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4524
4525         /*
4526          * FIXME IPS should be fine as long as one plane is
4527          * enabled, but in practice it seems to have problems
4528          * when going from primary only to sprite only and vice
4529          * versa.
4530          */
4531         hsw_disable_ips(intel_crtc);
4532 }
4533
4534 /* FIXME get rid of this and use pre_plane_update */
4535 static void
4536 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4537 {
4538         struct drm_device *dev = crtc->dev;
4539         struct drm_i915_private *dev_priv = to_i915(dev);
4540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541         int pipe = intel_crtc->pipe;
4542
4543         intel_pre_disable_primary(crtc);
4544
4545         /*
4546          * Vblank time updates from the shadow to live plane control register
4547          * are blocked if the memory self-refresh mode is active at that
4548          * moment. So to make sure the plane gets truly disabled, disable
4549          * first the self-refresh mode. The self-refresh enable bit in turn
4550          * will be checked/applied by the HW only at the next frame start
4551          * event which is after the vblank start event, so we need to have a
4552          * wait-for-vblank between disabling the plane and the pipe.
4553          */
4554         if (HAS_GMCH_DISPLAY(dev)) {
4555                 intel_set_memory_cxsr(dev_priv, false);
4556                 dev_priv->wm.vlv.cxsr = false;
4557                 intel_wait_for_vblank(dev, pipe);
4558         }
4559 }
4560
4561 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4562 {
4563         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4564         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4565         struct intel_crtc_state *pipe_config =
4566                 to_intel_crtc_state(crtc->base.state);
4567         struct drm_device *dev = crtc->base.dev;
4568         struct drm_plane *primary = crtc->base.primary;
4569         struct drm_plane_state *old_pri_state =
4570                 drm_atomic_get_existing_plane_state(old_state, primary);
4571
4572         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4573
4574         crtc->wm.cxsr_allowed = true;
4575
4576         if (pipe_config->update_wm_post && pipe_config->base.active)
4577                 intel_update_watermarks(&crtc->base);
4578
4579         if (old_pri_state) {
4580                 struct intel_plane_state *primary_state =
4581                         to_intel_plane_state(primary->state);
4582                 struct intel_plane_state *old_primary_state =
4583                         to_intel_plane_state(old_pri_state);
4584
4585                 intel_fbc_post_update(crtc);
4586
4587                 if (primary_state->visible &&
4588                     (needs_modeset(&pipe_config->base) ||
4589                      !old_primary_state->visible))
4590                         intel_post_enable_primary(&crtc->base);
4591         }
4592 }
4593
4594 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4595 {
4596         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4597         struct drm_device *dev = crtc->base.dev;
4598         struct drm_i915_private *dev_priv = to_i915(dev);
4599         struct intel_crtc_state *pipe_config =
4600                 to_intel_crtc_state(crtc->base.state);
4601         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4602         struct drm_plane *primary = crtc->base.primary;
4603         struct drm_plane_state *old_pri_state =
4604                 drm_atomic_get_existing_plane_state(old_state, primary);
4605         bool modeset = needs_modeset(&pipe_config->base);
4606
4607         if (old_pri_state) {
4608                 struct intel_plane_state *primary_state =
4609                         to_intel_plane_state(primary->state);
4610                 struct intel_plane_state *old_primary_state =
4611                         to_intel_plane_state(old_pri_state);
4612
4613                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4614
4615                 if (old_primary_state->visible &&
4616                     (modeset || !primary_state->visible))
4617                         intel_pre_disable_primary(&crtc->base);
4618         }
4619
4620         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4621                 crtc->wm.cxsr_allowed = false;
4622
4623                 /*
4624                  * Vblank time updates from the shadow to live plane control register
4625                  * are blocked if the memory self-refresh mode is active at that
4626                  * moment. So to make sure the plane gets truly disabled, disable
4627                  * first the self-refresh mode. The self-refresh enable bit in turn
4628                  * will be checked/applied by the HW only at the next frame start
4629                  * event which is after the vblank start event, so we need to have a
4630                  * wait-for-vblank between disabling the plane and the pipe.
4631                  */
4632                 if (old_crtc_state->base.active) {
4633                         intel_set_memory_cxsr(dev_priv, false);
4634                         dev_priv->wm.vlv.cxsr = false;
4635                         intel_wait_for_vblank(dev, crtc->pipe);
4636                 }
4637         }
4638
4639         /*
4640          * IVB workaround: must disable low power watermarks for at least
4641          * one frame before enabling scaling.  LP watermarks can be re-enabled
4642          * when scaling is disabled.
4643          *
4644          * WaCxSRDisabledForSpriteScaling:ivb
4645          */
4646         if (pipe_config->disable_lp_wm) {
4647                 ilk_disable_lp_wm(dev);
4648                 intel_wait_for_vblank(dev, crtc->pipe);
4649         }
4650
4651         /*
4652          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4653          * watermark programming here.
4654          */
4655         if (needs_modeset(&pipe_config->base))
4656                 return;
4657
4658         /*
4659          * For platforms that support atomic watermarks, program the
4660          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4661          * will be the intermediate values that are safe for both pre- and
4662          * post- vblank; when vblank happens, the 'active' values will be set
4663          * to the final 'target' values and we'll do this again to get the
4664          * optimal watermarks.  For gen9+ platforms, the values we program here
4665          * will be the final target values which will get automatically latched
4666          * at vblank time; no further programming will be necessary.
4667          *
4668          * If a platform hasn't been transitioned to atomic watermarks yet,
4669          * we'll continue to update watermarks the old way, if flags tell
4670          * us to.
4671          */
4672         if (dev_priv->display.initial_watermarks != NULL)
4673                 dev_priv->display.initial_watermarks(pipe_config);
4674         else if (pipe_config->update_wm_pre)
4675                 intel_update_watermarks(&crtc->base);
4676 }
4677
4678 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4679 {
4680         struct drm_device *dev = crtc->dev;
4681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4682         struct drm_plane *p;
4683         int pipe = intel_crtc->pipe;
4684
4685         intel_crtc_dpms_overlay_disable(intel_crtc);
4686
4687         drm_for_each_plane_mask(p, dev, plane_mask)
4688                 to_intel_plane(p)->disable_plane(p, crtc);
4689
4690         /*
4691          * FIXME: Once we grow proper nuclear flip support out of this we need
4692          * to compute the mask of flip planes precisely. For the time being
4693          * consider this a flip to a NULL plane.
4694          */
4695         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4696 }
4697
4698 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         struct drm_i915_private *dev_priv = to_i915(dev);
4702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703         struct intel_encoder *encoder;
4704         int pipe = intel_crtc->pipe;
4705         struct intel_crtc_state *pipe_config =
4706                 to_intel_crtc_state(crtc->state);
4707
4708         if (WARN_ON(intel_crtc->active))
4709                 return;
4710
4711         /*
4712          * Sometimes spurious CPU pipe underruns happen during FDI
4713          * training, at least with VGA+HDMI cloning. Suppress them.
4714          *
4715          * On ILK we get an occasional spurious CPU pipe underruns
4716          * between eDP port A enable and vdd enable. Also PCH port
4717          * enable seems to result in the occasional CPU pipe underrun.
4718          *
4719          * Spurious PCH underruns also occur during PCH enabling.
4720          */
4721         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4722                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4723         if (intel_crtc->config->has_pch_encoder)
4724                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4725
4726         if (intel_crtc->config->has_pch_encoder)
4727                 intel_prepare_shared_dpll(intel_crtc);
4728
4729         if (intel_crtc_has_dp_encoder(intel_crtc->config))
4730                 intel_dp_set_m_n(intel_crtc, M1_N1);
4731
4732         intel_set_pipe_timings(intel_crtc);
4733         intel_set_pipe_src_size(intel_crtc);
4734
4735         if (intel_crtc->config->has_pch_encoder) {
4736                 intel_cpu_transcoder_set_m_n(intel_crtc,
4737                                      &intel_crtc->config->fdi_m_n, NULL);
4738         }
4739
4740         ironlake_set_pipeconf(crtc);
4741
4742         intel_crtc->active = true;
4743
4744         for_each_encoder_on_crtc(dev, crtc, encoder)
4745                 if (encoder->pre_enable)
4746                         encoder->pre_enable(encoder);
4747
4748         if (intel_crtc->config->has_pch_encoder) {
4749                 /* Note: FDI PLL enabling _must_ be done before we enable the
4750                  * cpu pipes, hence this is separate from all the other fdi/pch
4751                  * enabling. */
4752                 ironlake_fdi_pll_enable(intel_crtc);
4753         } else {
4754                 assert_fdi_tx_disabled(dev_priv, pipe);
4755                 assert_fdi_rx_disabled(dev_priv, pipe);
4756         }
4757
4758         ironlake_pfit_enable(intel_crtc);
4759
4760         /*
4761          * On ILK+ LUT must be loaded before the pipe is running but with
4762          * clocks enabled
4763          */
4764         intel_color_load_luts(&pipe_config->base);
4765
4766         if (dev_priv->display.initial_watermarks != NULL)
4767                 dev_priv->display.initial_watermarks(intel_crtc->config);
4768         intel_enable_pipe(intel_crtc);
4769
4770         if (intel_crtc->config->has_pch_encoder)
4771                 ironlake_pch_enable(crtc);
4772
4773         assert_vblank_disabled(crtc);
4774         drm_crtc_vblank_on(crtc);
4775
4776         for_each_encoder_on_crtc(dev, crtc, encoder)
4777                 encoder->enable(encoder);
4778
4779         if (HAS_PCH_CPT(dev))
4780                 cpt_verify_modeset(dev, intel_crtc->pipe);
4781
4782         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4783         if (intel_crtc->config->has_pch_encoder)
4784                 intel_wait_for_vblank(dev, pipe);
4785         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4786         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4787 }
4788
4789 /* IPS only exists on ULT machines and is tied to pipe A. */
4790 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4791 {
4792         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4793 }
4794
4795 static void haswell_crtc_enable(struct drm_crtc *crtc)
4796 {
4797         struct drm_device *dev = crtc->dev;
4798         struct drm_i915_private *dev_priv = to_i915(dev);
4799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4800         struct intel_encoder *encoder;
4801         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4802         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4803         struct intel_crtc_state *pipe_config =
4804                 to_intel_crtc_state(crtc->state);
4805
4806         if (WARN_ON(intel_crtc->active))
4807                 return;
4808
4809         if (intel_crtc->config->has_pch_encoder)
4810                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4811                                                       false);
4812
4813         for_each_encoder_on_crtc(dev, crtc, encoder)
4814                 if (encoder->pre_pll_enable)
4815                         encoder->pre_pll_enable(encoder);
4816
4817         if (intel_crtc->config->shared_dpll)
4818                 intel_enable_shared_dpll(intel_crtc);
4819
4820         if (intel_crtc_has_dp_encoder(intel_crtc->config))
4821                 intel_dp_set_m_n(intel_crtc, M1_N1);
4822
4823         if (!transcoder_is_dsi(cpu_transcoder))
4824                 intel_set_pipe_timings(intel_crtc);
4825
4826         intel_set_pipe_src_size(intel_crtc);
4827
4828         if (cpu_transcoder != TRANSCODER_EDP &&
4829             !transcoder_is_dsi(cpu_transcoder)) {
4830                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4831                            intel_crtc->config->pixel_multiplier - 1);
4832         }
4833
4834         if (intel_crtc->config->has_pch_encoder) {
4835                 intel_cpu_transcoder_set_m_n(intel_crtc,
4836                                      &intel_crtc->config->fdi_m_n, NULL);
4837         }
4838
4839         if (!transcoder_is_dsi(cpu_transcoder))
4840                 haswell_set_pipeconf(crtc);
4841
4842         haswell_set_pipemisc(crtc);
4843
4844         intel_color_set_csc(&pipe_config->base);
4845
4846         intel_crtc->active = true;
4847
4848         if (intel_crtc->config->has_pch_encoder)
4849                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4850         else
4851                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4852
4853         for_each_encoder_on_crtc(dev, crtc, encoder) {
4854                 if (encoder->pre_enable)
4855                         encoder->pre_enable(encoder);
4856         }
4857
4858         if (intel_crtc->config->has_pch_encoder)
4859                 dev_priv->display.fdi_link_train(crtc);
4860
4861         if (!transcoder_is_dsi(cpu_transcoder))
4862                 intel_ddi_enable_pipe_clock(intel_crtc);
4863
4864         if (INTEL_INFO(dev)->gen >= 9)
4865                 skylake_pfit_enable(intel_crtc);
4866         else
4867                 ironlake_pfit_enable(intel_crtc);
4868
4869         /*
4870          * On ILK+ LUT must be loaded before the pipe is running but with
4871          * clocks enabled
4872          */
4873         intel_color_load_luts(&pipe_config->base);
4874
4875         intel_ddi_set_pipe_settings(crtc);
4876         if (!transcoder_is_dsi(cpu_transcoder))
4877                 intel_ddi_enable_transcoder_func(crtc);
4878
4879         if (dev_priv->display.initial_watermarks != NULL)
4880                 dev_priv->display.initial_watermarks(pipe_config);
4881         else
4882                 intel_update_watermarks(crtc);
4883
4884         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4885         if (!transcoder_is_dsi(cpu_transcoder))
4886                 intel_enable_pipe(intel_crtc);
4887
4888         if (intel_crtc->config->has_pch_encoder)
4889                 lpt_pch_enable(crtc);
4890
4891         if (intel_crtc->config->dp_encoder_is_mst)
4892                 intel_ddi_set_vc_payload_alloc(crtc, true);
4893
4894         assert_vblank_disabled(crtc);
4895         drm_crtc_vblank_on(crtc);
4896
4897         for_each_encoder_on_crtc(dev, crtc, encoder) {
4898                 encoder->enable(encoder);
4899                 intel_opregion_notify_encoder(encoder, true);
4900         }
4901
4902         if (intel_crtc->config->has_pch_encoder) {
4903                 intel_wait_for_vblank(dev, pipe);
4904                 intel_wait_for_vblank(dev, pipe);
4905                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4907                                                       true);
4908         }
4909
4910         /* If we change the relative order between pipe/planes enabling, we need
4911          * to change the workaround. */
4912         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4913         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4914                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4915                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4916         }
4917 }
4918
4919 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4920 {
4921         struct drm_device *dev = crtc->base.dev;
4922         struct drm_i915_private *dev_priv = to_i915(dev);
4923         int pipe = crtc->pipe;
4924
4925         /* To avoid upsetting the power well on haswell only disable the pfit if
4926          * it's in use. The hw state code will make sure we get this right. */
4927         if (force || crtc->config->pch_pfit.enabled) {
4928                 I915_WRITE(PF_CTL(pipe), 0);
4929                 I915_WRITE(PF_WIN_POS(pipe), 0);
4930                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4931         }
4932 }
4933
4934 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4935 {
4936         struct drm_device *dev = crtc->dev;
4937         struct drm_i915_private *dev_priv = to_i915(dev);
4938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4939         struct intel_encoder *encoder;
4940         int pipe = intel_crtc->pipe;
4941
4942         /*
4943          * Sometimes spurious CPU pipe underruns happen when the
4944          * pipe is already disabled, but FDI RX/TX is still enabled.
4945          * Happens at least with VGA+HDMI cloning. Suppress them.
4946          */
4947         if (intel_crtc->config->has_pch_encoder) {
4948                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4949                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4950         }
4951
4952         for_each_encoder_on_crtc(dev, crtc, encoder)
4953                 encoder->disable(encoder);
4954
4955         drm_crtc_vblank_off(crtc);
4956         assert_vblank_disabled(crtc);
4957
4958         intel_disable_pipe(intel_crtc);
4959
4960         ironlake_pfit_disable(intel_crtc, false);
4961
4962         if (intel_crtc->config->has_pch_encoder)
4963                 ironlake_fdi_disable(crtc);
4964
4965         for_each_encoder_on_crtc(dev, crtc, encoder)
4966                 if (encoder->post_disable)
4967                         encoder->post_disable(encoder);
4968
4969         if (intel_crtc->config->has_pch_encoder) {
4970                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4971
4972                 if (HAS_PCH_CPT(dev)) {
4973                         i915_reg_t reg;
4974                         u32 temp;
4975
4976                         /* disable TRANS_DP_CTL */
4977                         reg = TRANS_DP_CTL(pipe);
4978                         temp = I915_READ(reg);
4979                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4980                                   TRANS_DP_PORT_SEL_MASK);
4981                         temp |= TRANS_DP_PORT_SEL_NONE;
4982                         I915_WRITE(reg, temp);
4983
4984                         /* disable DPLL_SEL */
4985                         temp = I915_READ(PCH_DPLL_SEL);
4986                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4987                         I915_WRITE(PCH_DPLL_SEL, temp);
4988                 }
4989
4990                 ironlake_fdi_pll_disable(intel_crtc);
4991         }
4992
4993         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4994         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4995 }
4996
4997 static void haswell_crtc_disable(struct drm_crtc *crtc)
4998 {
4999         struct drm_device *dev = crtc->dev;
5000         struct drm_i915_private *dev_priv = to_i915(dev);
5001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002         struct intel_encoder *encoder;
5003         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5004
5005         if (intel_crtc->config->has_pch_encoder)
5006                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5007                                                       false);
5008
5009         for_each_encoder_on_crtc(dev, crtc, encoder) {
5010                 intel_opregion_notify_encoder(encoder, false);
5011                 encoder->disable(encoder);
5012         }
5013
5014         drm_crtc_vblank_off(crtc);
5015         assert_vblank_disabled(crtc);
5016
5017         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5018         if (!transcoder_is_dsi(cpu_transcoder))
5019                 intel_disable_pipe(intel_crtc);
5020
5021         if (intel_crtc->config->dp_encoder_is_mst)
5022                 intel_ddi_set_vc_payload_alloc(crtc, false);
5023
5024         if (!transcoder_is_dsi(cpu_transcoder))
5025                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5026
5027         if (INTEL_INFO(dev)->gen >= 9)
5028                 skylake_scaler_disable(intel_crtc);
5029         else
5030                 ironlake_pfit_disable(intel_crtc, false);
5031
5032         if (!transcoder_is_dsi(cpu_transcoder))
5033                 intel_ddi_disable_pipe_clock(intel_crtc);
5034
5035         for_each_encoder_on_crtc(dev, crtc, encoder)
5036                 if (encoder->post_disable)
5037                         encoder->post_disable(encoder);
5038
5039         if (intel_crtc->config->has_pch_encoder) {
5040                 lpt_disable_pch_transcoder(dev_priv);
5041                 lpt_disable_iclkip(dev_priv);
5042                 intel_ddi_fdi_disable(crtc);
5043
5044                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5045                                                       true);
5046         }
5047 }
5048
5049 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5050 {
5051         struct drm_device *dev = crtc->base.dev;
5052         struct drm_i915_private *dev_priv = to_i915(dev);
5053         struct intel_crtc_state *pipe_config = crtc->config;
5054
5055         if (!pipe_config->gmch_pfit.control)
5056                 return;
5057
5058         /*
5059          * The panel fitter should only be adjusted whilst the pipe is disabled,
5060          * according to register description and PRM.
5061          */
5062         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5063         assert_pipe_disabled(dev_priv, crtc->pipe);
5064
5065         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5066         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5067
5068         /* Border color in case we don't scale up to the full screen. Black by
5069          * default, change to something else for debugging. */
5070         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5071 }
5072
5073 static enum intel_display_power_domain port_to_power_domain(enum port port)
5074 {
5075         switch (port) {
5076         case PORT_A:
5077                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5078         case PORT_B:
5079                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5080         case PORT_C:
5081                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5082         case PORT_D:
5083                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5084         case PORT_E:
5085                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5086         default:
5087                 MISSING_CASE(port);
5088                 return POWER_DOMAIN_PORT_OTHER;
5089         }
5090 }
5091
5092 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5093 {
5094         switch (port) {
5095         case PORT_A:
5096                 return POWER_DOMAIN_AUX_A;
5097         case PORT_B:
5098                 return POWER_DOMAIN_AUX_B;
5099         case PORT_C:
5100                 return POWER_DOMAIN_AUX_C;
5101         case PORT_D:
5102                 return POWER_DOMAIN_AUX_D;
5103         case PORT_E:
5104                 /* FIXME: Check VBT for actual wiring of PORT E */
5105                 return POWER_DOMAIN_AUX_D;
5106         default:
5107                 MISSING_CASE(port);
5108                 return POWER_DOMAIN_AUX_A;
5109         }
5110 }
5111
5112 enum intel_display_power_domain
5113 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5114 {
5115         struct drm_device *dev = intel_encoder->base.dev;
5116         struct intel_digital_port *intel_dig_port;
5117
5118         switch (intel_encoder->type) {
5119         case INTEL_OUTPUT_UNKNOWN:
5120                 /* Only DDI platforms should ever use this output type */
5121                 WARN_ON_ONCE(!HAS_DDI(dev));
5122         case INTEL_OUTPUT_DP:
5123         case INTEL_OUTPUT_HDMI:
5124         case INTEL_OUTPUT_EDP:
5125                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5126                 return port_to_power_domain(intel_dig_port->port);
5127         case INTEL_OUTPUT_DP_MST:
5128                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5129                 return port_to_power_domain(intel_dig_port->port);
5130         case INTEL_OUTPUT_ANALOG:
5131                 return POWER_DOMAIN_PORT_CRT;
5132         case INTEL_OUTPUT_DSI:
5133                 return POWER_DOMAIN_PORT_DSI;
5134         default:
5135                 return POWER_DOMAIN_PORT_OTHER;
5136         }
5137 }
5138
5139 enum intel_display_power_domain
5140 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5141 {
5142         struct drm_device *dev = intel_encoder->base.dev;
5143         struct intel_digital_port *intel_dig_port;
5144
5145         switch (intel_encoder->type) {
5146         case INTEL_OUTPUT_UNKNOWN:
5147         case INTEL_OUTPUT_HDMI:
5148                 /*
5149                  * Only DDI platforms should ever use these output types.
5150                  * We can get here after the HDMI detect code has already set
5151                  * the type of the shared encoder. Since we can't be sure
5152                  * what's the status of the given connectors, play safe and
5153                  * run the DP detection too.
5154                  */
5155                 WARN_ON_ONCE(!HAS_DDI(dev));
5156         case INTEL_OUTPUT_DP:
5157         case INTEL_OUTPUT_EDP:
5158                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5159                 return port_to_aux_power_domain(intel_dig_port->port);
5160         case INTEL_OUTPUT_DP_MST:
5161                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5162                 return port_to_aux_power_domain(intel_dig_port->port);
5163         default:
5164                 MISSING_CASE(intel_encoder->type);
5165                 return POWER_DOMAIN_AUX_A;
5166         }
5167 }
5168
5169 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5170                                             struct intel_crtc_state *crtc_state)
5171 {
5172         struct drm_device *dev = crtc->dev;
5173         struct drm_encoder *encoder;
5174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175         enum pipe pipe = intel_crtc->pipe;
5176         unsigned long mask;
5177         enum transcoder transcoder = crtc_state->cpu_transcoder;
5178
5179         if (!crtc_state->base.active)
5180                 return 0;
5181
5182         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5183         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5184         if (crtc_state->pch_pfit.enabled ||
5185             crtc_state->pch_pfit.force_thru)
5186                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5187
5188         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5189                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5190
5191                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5192         }
5193
5194         if (crtc_state->shared_dpll)
5195                 mask |= BIT(POWER_DOMAIN_PLLS);
5196
5197         return mask;
5198 }
5199
5200 static unsigned long
5201 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5202                                struct intel_crtc_state *crtc_state)
5203 {
5204         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206         enum intel_display_power_domain domain;
5207         unsigned long domains, new_domains, old_domains;
5208
5209         old_domains = intel_crtc->enabled_power_domains;
5210         intel_crtc->enabled_power_domains = new_domains =
5211                 get_crtc_power_domains(crtc, crtc_state);
5212
5213         domains = new_domains & ~old_domains;
5214
5215         for_each_power_domain(domain, domains)
5216                 intel_display_power_get(dev_priv, domain);
5217
5218         return old_domains & ~new_domains;
5219 }
5220
5221 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5222                                       unsigned long domains)
5223 {
5224         enum intel_display_power_domain domain;
5225
5226         for_each_power_domain(domain, domains)
5227                 intel_display_power_put(dev_priv, domain);
5228 }
5229
5230 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5231 {
5232         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5233
5234         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5235             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5236                 return max_cdclk_freq;
5237         else if (IS_CHERRYVIEW(dev_priv))
5238                 return max_cdclk_freq*95/100;
5239         else if (INTEL_INFO(dev_priv)->gen < 4)
5240                 return 2*max_cdclk_freq*90/100;
5241         else
5242                 return max_cdclk_freq*90/100;
5243 }
5244
5245 static int skl_calc_cdclk(int max_pixclk, int vco);
5246
5247 static void intel_update_max_cdclk(struct drm_device *dev)
5248 {
5249         struct drm_i915_private *dev_priv = to_i915(dev);
5250
5251         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5252                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5253                 int max_cdclk, vco;
5254
5255                 vco = dev_priv->skl_preferred_vco_freq;
5256                 WARN_ON(vco != 8100000 && vco != 8640000);
5257
5258                 /*
5259                  * Use the lower (vco 8640) cdclk values as a
5260                  * first guess. skl_calc_cdclk() will correct it
5261                  * if the preferred vco is 8100 instead.
5262                  */
5263                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5264                         max_cdclk = 617143;
5265                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5266                         max_cdclk = 540000;
5267                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5268                         max_cdclk = 432000;
5269                 else
5270                         max_cdclk = 308571;
5271
5272                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5273         } else if (IS_BROXTON(dev)) {
5274                 dev_priv->max_cdclk_freq = 624000;
5275         } else if (IS_BROADWELL(dev))  {
5276                 /*
5277                  * FIXME with extra cooling we can allow
5278                  * 540 MHz for ULX and 675 Mhz for ULT.
5279                  * How can we know if extra cooling is
5280                  * available? PCI ID, VTB, something else?
5281                  */
5282                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5283                         dev_priv->max_cdclk_freq = 450000;
5284                 else if (IS_BDW_ULX(dev))
5285                         dev_priv->max_cdclk_freq = 450000;
5286                 else if (IS_BDW_ULT(dev))
5287                         dev_priv->max_cdclk_freq = 540000;
5288                 else
5289                         dev_priv->max_cdclk_freq = 675000;
5290         } else if (IS_CHERRYVIEW(dev)) {
5291                 dev_priv->max_cdclk_freq = 320000;
5292         } else if (IS_VALLEYVIEW(dev)) {
5293                 dev_priv->max_cdclk_freq = 400000;
5294         } else {
5295                 /* otherwise assume cdclk is fixed */
5296                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5297         }
5298
5299         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5300
5301         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302                          dev_priv->max_cdclk_freq);
5303
5304         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5305                          dev_priv->max_dotclk_freq);
5306 }
5307
5308 static void intel_update_cdclk(struct drm_device *dev)
5309 {
5310         struct drm_i915_private *dev_priv = to_i915(dev);
5311
5312         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5313
5314         if (INTEL_GEN(dev_priv) >= 9)
5315                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5316                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5317                                  dev_priv->cdclk_pll.ref);
5318         else
5319                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5320                                  dev_priv->cdclk_freq);
5321
5322         /*
5323          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5324          * Programmng [sic] note: bit[9:2] should be programmed to the number
5325          * of cdclk that generates 4MHz reference clock freq which is used to
5326          * generate GMBus clock. This will vary with the cdclk freq.
5327          */
5328         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5329                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5330 }
5331
5332 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5333 static int skl_cdclk_decimal(int cdclk)
5334 {
5335         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5336 }
5337
5338 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5339 {
5340         int ratio;
5341
5342         if (cdclk == dev_priv->cdclk_pll.ref)
5343                 return 0;
5344
5345         switch (cdclk) {
5346         default:
5347                 MISSING_CASE(cdclk);
5348         case 144000:
5349         case 288000:
5350         case 384000:
5351         case 576000:
5352                 ratio = 60;
5353                 break;
5354         case 624000:
5355                 ratio = 65;
5356                 break;
5357         }
5358
5359         return dev_priv->cdclk_pll.ref * ratio;
5360 }
5361
5362 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5363 {
5364         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5365
5366         /* Timeout 200us */
5367         if (intel_wait_for_register(dev_priv,
5368                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5369                                     1))
5370                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5371
5372         dev_priv->cdclk_pll.vco = 0;
5373 }
5374
5375 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5376 {
5377         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5378         u32 val;
5379
5380         val = I915_READ(BXT_DE_PLL_CTL);
5381         val &= ~BXT_DE_PLL_RATIO_MASK;
5382         val |= BXT_DE_PLL_RATIO(ratio);
5383         I915_WRITE(BXT_DE_PLL_CTL, val);
5384
5385         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5386
5387         /* Timeout 200us */
5388         if (intel_wait_for_register(dev_priv,
5389                                     BXT_DE_PLL_ENABLE,
5390                                     BXT_DE_PLL_LOCK,
5391                                     BXT_DE_PLL_LOCK,
5392                                     1))
5393                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5394
5395         dev_priv->cdclk_pll.vco = vco;
5396 }
5397
5398 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5399 {
5400         u32 val, divider;
5401         int vco, ret;
5402
5403         vco = bxt_de_pll_vco(dev_priv, cdclk);
5404
5405         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5406
5407         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5408         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5409         case 8:
5410                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5411                 break;
5412         case 4:
5413                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5414                 break;
5415         case 3:
5416                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5417                 break;
5418         case 2:
5419                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5420                 break;
5421         default:
5422                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5423                 WARN_ON(vco != 0);
5424
5425                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5426                 break;
5427         }
5428
5429         /* Inform power controller of upcoming frequency change */
5430         mutex_lock(&dev_priv->rps.hw_lock);
5431         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5432                                       0x80000000);
5433         mutex_unlock(&dev_priv->rps.hw_lock);
5434
5435         if (ret) {
5436                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5437                           ret, cdclk);
5438                 return;
5439         }
5440
5441         if (dev_priv->cdclk_pll.vco != 0 &&
5442             dev_priv->cdclk_pll.vco != vco)
5443                 bxt_de_pll_disable(dev_priv);
5444
5445         if (dev_priv->cdclk_pll.vco != vco)
5446                 bxt_de_pll_enable(dev_priv, vco);
5447
5448         val = divider | skl_cdclk_decimal(cdclk);
5449         /*
5450          * FIXME if only the cd2x divider needs changing, it could be done
5451          * without shutting off the pipe (if only one pipe is active).
5452          */
5453         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5454         /*
5455          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5456          * enable otherwise.
5457          */
5458         if (cdclk >= 500000)
5459                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5460         I915_WRITE(CDCLK_CTL, val);
5461
5462         mutex_lock(&dev_priv->rps.hw_lock);
5463         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5464                                       DIV_ROUND_UP(cdclk, 25000));
5465         mutex_unlock(&dev_priv->rps.hw_lock);
5466
5467         if (ret) {
5468                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5469                           ret, cdclk);
5470                 return;
5471         }
5472
5473         intel_update_cdclk(&dev_priv->drm);
5474 }
5475
5476 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5477 {
5478         u32 cdctl, expected;
5479
5480         intel_update_cdclk(&dev_priv->drm);
5481
5482         if (dev_priv->cdclk_pll.vco == 0 ||
5483             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5484                 goto sanitize;
5485
5486         /* DPLL okay; verify the cdclock
5487          *
5488          * Some BIOS versions leave an incorrect decimal frequency value and
5489          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5490          * so sanitize this register.
5491          */
5492         cdctl = I915_READ(CDCLK_CTL);
5493         /*
5494          * Let's ignore the pipe field, since BIOS could have configured the
5495          * dividers both synching to an active pipe, or asynchronously
5496          * (PIPE_NONE).
5497          */
5498         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5499
5500         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5501                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5502         /*
5503          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5504          * enable otherwise.
5505          */
5506         if (dev_priv->cdclk_freq >= 500000)
5507                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5508
5509         if (cdctl == expected)
5510                 /* All well; nothing to sanitize */
5511                 return;
5512
5513 sanitize:
5514         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5515
5516         /* force cdclk programming */
5517         dev_priv->cdclk_freq = 0;
5518
5519         /* force full PLL disable + enable */
5520         dev_priv->cdclk_pll.vco = -1;
5521 }
5522
5523 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5524 {
5525         bxt_sanitize_cdclk(dev_priv);
5526
5527         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5528                 return;
5529
5530         /*
5531          * FIXME:
5532          * - The initial CDCLK needs to be read from VBT.
5533          *   Need to make this change after VBT has changes for BXT.
5534          */
5535         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5536 }
5537
5538 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5539 {
5540         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5541 }
5542
5543 static int skl_calc_cdclk(int max_pixclk, int vco)
5544 {
5545         if (vco == 8640000) {
5546                 if (max_pixclk > 540000)
5547                         return 617143;
5548                 else if (max_pixclk > 432000)
5549                         return 540000;
5550                 else if (max_pixclk > 308571)
5551                         return 432000;
5552                 else
5553                         return 308571;
5554         } else {
5555                 if (max_pixclk > 540000)
5556                         return 675000;
5557                 else if (max_pixclk > 450000)
5558                         return 540000;
5559                 else if (max_pixclk > 337500)
5560                         return 450000;
5561                 else
5562                         return 337500;
5563         }
5564 }
5565
5566 static void
5567 skl_dpll0_update(struct drm_i915_private *dev_priv)
5568 {
5569         u32 val;
5570
5571         dev_priv->cdclk_pll.ref = 24000;
5572         dev_priv->cdclk_pll.vco = 0;
5573
5574         val = I915_READ(LCPLL1_CTL);
5575         if ((val & LCPLL_PLL_ENABLE) == 0)
5576                 return;
5577
5578         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5579                 return;
5580
5581         val = I915_READ(DPLL_CTRL1);
5582
5583         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5584                             DPLL_CTRL1_SSC(SKL_DPLL0) |
5585                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5586                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5587                 return;
5588
5589         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5590         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5591         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5592         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5593         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5594                 dev_priv->cdclk_pll.vco = 8100000;
5595                 break;
5596         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5597         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5598                 dev_priv->cdclk_pll.vco = 8640000;
5599                 break;
5600         default:
5601                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5602                 break;
5603         }
5604 }
5605
5606 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5607 {
5608         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5609
5610         dev_priv->skl_preferred_vco_freq = vco;
5611
5612         if (changed)
5613                 intel_update_max_cdclk(&dev_priv->drm);
5614 }
5615
5616 static void
5617 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5618 {
5619         int min_cdclk = skl_calc_cdclk(0, vco);
5620         u32 val;
5621
5622         WARN_ON(vco != 8100000 && vco != 8640000);
5623
5624         /* select the minimum CDCLK before enabling DPLL 0 */
5625         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5626         I915_WRITE(CDCLK_CTL, val);
5627         POSTING_READ(CDCLK_CTL);
5628
5629         /*
5630          * We always enable DPLL0 with the lowest link rate possible, but still
5631          * taking into account the VCO required to operate the eDP panel at the
5632          * desired frequency. The usual DP link rates operate with a VCO of
5633          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5634          * The modeset code is responsible for the selection of the exact link
5635          * rate later on, with the constraint of choosing a frequency that
5636          * works with vco.
5637          */
5638         val = I915_READ(DPLL_CTRL1);
5639
5640         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5641                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5642         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5643         if (vco == 8640000)
5644                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5645                                             SKL_DPLL0);
5646         else
5647                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5648                                             SKL_DPLL0);
5649
5650         I915_WRITE(DPLL_CTRL1, val);
5651         POSTING_READ(DPLL_CTRL1);
5652
5653         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5654
5655         if (intel_wait_for_register(dev_priv,
5656                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5657                                     5))
5658                 DRM_ERROR("DPLL0 not locked\n");
5659
5660         dev_priv->cdclk_pll.vco = vco;
5661
5662         /* We'll want to keep using the current vco from now on. */
5663         skl_set_preferred_cdclk_vco(dev_priv, vco);
5664 }
5665
5666 static void
5667 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5668 {
5669         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5670         if (intel_wait_for_register(dev_priv,
5671                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
5672                                    1))
5673                 DRM_ERROR("Couldn't disable DPLL0\n");
5674
5675         dev_priv->cdclk_pll.vco = 0;
5676 }
5677
5678 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5679 {
5680         int ret;
5681         u32 val;
5682
5683         /* inform PCU we want to change CDCLK */
5684         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5685         mutex_lock(&dev_priv->rps.hw_lock);
5686         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5687         mutex_unlock(&dev_priv->rps.hw_lock);
5688
5689         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5690 }
5691
5692 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5693 {
5694         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
5695 }
5696
5697 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5698 {
5699         struct drm_device *dev = &dev_priv->drm;
5700         u32 freq_select, pcu_ack;
5701
5702         WARN_ON((cdclk == 24000) != (vco == 0));
5703
5704         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5705
5706         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5707                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5708                 return;
5709         }
5710
5711         /* set CDCLK_CTL */
5712         switch (cdclk) {
5713         case 450000:
5714         case 432000:
5715                 freq_select = CDCLK_FREQ_450_432;
5716                 pcu_ack = 1;
5717                 break;
5718         case 540000:
5719                 freq_select = CDCLK_FREQ_540;
5720                 pcu_ack = 2;
5721                 break;
5722         case 308571:
5723         case 337500:
5724         default:
5725                 freq_select = CDCLK_FREQ_337_308;
5726                 pcu_ack = 0;
5727                 break;
5728         case 617143:
5729         case 675000:
5730                 freq_select = CDCLK_FREQ_675_617;
5731                 pcu_ack = 3;
5732                 break;
5733         }
5734
5735         if (dev_priv->cdclk_pll.vco != 0 &&
5736             dev_priv->cdclk_pll.vco != vco)
5737                 skl_dpll0_disable(dev_priv);
5738
5739         if (dev_priv->cdclk_pll.vco != vco)
5740                 skl_dpll0_enable(dev_priv, vco);
5741
5742         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5743         POSTING_READ(CDCLK_CTL);
5744
5745         /* inform PCU of the change */
5746         mutex_lock(&dev_priv->rps.hw_lock);
5747         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5748         mutex_unlock(&dev_priv->rps.hw_lock);
5749
5750         intel_update_cdclk(dev);
5751 }
5752
5753 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5754
5755 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5756 {
5757         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5758 }
5759
5760 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5761 {
5762         int cdclk, vco;
5763
5764         skl_sanitize_cdclk(dev_priv);
5765
5766         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5767                 /*
5768                  * Use the current vco as our initial
5769                  * guess as to what the preferred vco is.
5770                  */
5771                 if (dev_priv->skl_preferred_vco_freq == 0)
5772                         skl_set_preferred_cdclk_vco(dev_priv,
5773                                                     dev_priv->cdclk_pll.vco);
5774                 return;
5775         }
5776
5777         vco = dev_priv->skl_preferred_vco_freq;
5778         if (vco == 0)
5779                 vco = 8100000;
5780         cdclk = skl_calc_cdclk(0, vco);
5781
5782         skl_set_cdclk(dev_priv, cdclk, vco);
5783 }
5784
5785 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5786 {
5787         uint32_t cdctl, expected;
5788
5789         /*
5790          * check if the pre-os intialized the display
5791          * There is SWF18 scratchpad register defined which is set by the
5792          * pre-os which can be used by the OS drivers to check the status
5793          */
5794         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5795                 goto sanitize;
5796
5797         intel_update_cdclk(&dev_priv->drm);
5798         /* Is PLL enabled and locked ? */
5799         if (dev_priv->cdclk_pll.vco == 0 ||
5800             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5801                 goto sanitize;
5802
5803         /* DPLL okay; verify the cdclock
5804          *
5805          * Noticed in some instances that the freq selection is correct but
5806          * decimal part is programmed wrong from BIOS where pre-os does not
5807          * enable display. Verify the same as well.
5808          */
5809         cdctl = I915_READ(CDCLK_CTL);
5810         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5811                 skl_cdclk_decimal(dev_priv->cdclk_freq);
5812         if (cdctl == expected)
5813                 /* All well; nothing to sanitize */
5814                 return;
5815
5816 sanitize:
5817         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5818
5819         /* force cdclk programming */
5820         dev_priv->cdclk_freq = 0;
5821         /* force full PLL disable + enable */
5822         dev_priv->cdclk_pll.vco = -1;
5823 }
5824
5825 /* Adjust CDclk dividers to allow high res or save power if possible */
5826 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5827 {
5828         struct drm_i915_private *dev_priv = to_i915(dev);
5829         u32 val, cmd;
5830
5831         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5832                                         != dev_priv->cdclk_freq);
5833
5834         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5835                 cmd = 2;
5836         else if (cdclk == 266667)
5837                 cmd = 1;
5838         else
5839                 cmd = 0;
5840
5841         mutex_lock(&dev_priv->rps.hw_lock);
5842         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5843         val &= ~DSPFREQGUAR_MASK;
5844         val |= (cmd << DSPFREQGUAR_SHIFT);
5845         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5846         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5847                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5848                      50)) {
5849                 DRM_ERROR("timed out waiting for CDclk change\n");
5850         }
5851         mutex_unlock(&dev_priv->rps.hw_lock);
5852
5853         mutex_lock(&dev_priv->sb_lock);
5854
5855         if (cdclk == 400000) {
5856                 u32 divider;
5857
5858                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5859
5860                 /* adjust cdclk divider */
5861                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5862                 val &= ~CCK_FREQUENCY_VALUES;
5863                 val |= divider;
5864                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5865
5866                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5867                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5868                              50))
5869                         DRM_ERROR("timed out waiting for CDclk change\n");
5870         }
5871
5872         /* adjust self-refresh exit latency value */
5873         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5874         val &= ~0x7f;
5875
5876         /*
5877          * For high bandwidth configs, we set a higher latency in the bunit
5878          * so that the core display fetch happens in time to avoid underruns.
5879          */
5880         if (cdclk == 400000)
5881                 val |= 4500 / 250; /* 4.5 usec */
5882         else
5883                 val |= 3000 / 250; /* 3.0 usec */
5884         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5885
5886         mutex_unlock(&dev_priv->sb_lock);
5887
5888         intel_update_cdclk(dev);
5889 }
5890
5891 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5892 {
5893         struct drm_i915_private *dev_priv = to_i915(dev);
5894         u32 val, cmd;
5895
5896         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5897                                                 != dev_priv->cdclk_freq);
5898
5899         switch (cdclk) {
5900         case 333333:
5901         case 320000:
5902         case 266667:
5903         case 200000:
5904                 break;
5905         default:
5906                 MISSING_CASE(cdclk);
5907                 return;
5908         }
5909
5910         /*
5911          * Specs are full of misinformation, but testing on actual
5912          * hardware has shown that we just need to write the desired
5913          * CCK divider into the Punit register.
5914          */
5915         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5916
5917         mutex_lock(&dev_priv->rps.hw_lock);
5918         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5919         val &= ~DSPFREQGUAR_MASK_CHV;
5920         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5921         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5922         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5923                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5924                      50)) {
5925                 DRM_ERROR("timed out waiting for CDclk change\n");
5926         }
5927         mutex_unlock(&dev_priv->rps.hw_lock);
5928
5929         intel_update_cdclk(dev);
5930 }
5931
5932 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5933                                  int max_pixclk)
5934 {
5935         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5936         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5937
5938         /*
5939          * Really only a few cases to deal with, as only 4 CDclks are supported:
5940          *   200MHz
5941          *   267MHz
5942          *   320/333MHz (depends on HPLL freq)
5943          *   400MHz (VLV only)
5944          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5945          * of the lower bin and adjust if needed.
5946          *
5947          * We seem to get an unstable or solid color picture at 200MHz.
5948          * Not sure what's wrong. For now use 200MHz only when all pipes
5949          * are off.
5950          */
5951         if (!IS_CHERRYVIEW(dev_priv) &&
5952             max_pixclk > freq_320*limit/100)
5953                 return 400000;
5954         else if (max_pixclk > 266667*limit/100)
5955                 return freq_320;
5956         else if (max_pixclk > 0)
5957                 return 266667;
5958         else
5959                 return 200000;
5960 }
5961
5962 static int bxt_calc_cdclk(int max_pixclk)
5963 {
5964         if (max_pixclk > 576000)
5965                 return 624000;
5966         else if (max_pixclk > 384000)
5967                 return 576000;
5968         else if (max_pixclk > 288000)
5969                 return 384000;
5970         else if (max_pixclk > 144000)
5971                 return 288000;
5972         else
5973                 return 144000;
5974 }
5975
5976 /* Compute the max pixel clock for new configuration. */
5977 static int intel_mode_max_pixclk(struct drm_device *dev,
5978                                  struct drm_atomic_state *state)
5979 {
5980         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5981         struct drm_i915_private *dev_priv = to_i915(dev);
5982         struct drm_crtc *crtc;
5983         struct drm_crtc_state *crtc_state;
5984         unsigned max_pixclk = 0, i;
5985         enum pipe pipe;
5986
5987         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5988                sizeof(intel_state->min_pixclk));
5989
5990         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5991                 int pixclk = 0;
5992
5993                 if (crtc_state->enable)
5994                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5995
5996                 intel_state->min_pixclk[i] = pixclk;
5997         }
5998
5999         for_each_pipe(dev_priv, pipe)
6000                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6001
6002         return max_pixclk;
6003 }
6004
6005 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6006 {
6007         struct drm_device *dev = state->dev;
6008         struct drm_i915_private *dev_priv = to_i915(dev);
6009         int max_pixclk = intel_mode_max_pixclk(dev, state);
6010         struct intel_atomic_state *intel_state =
6011                 to_intel_atomic_state(state);
6012
6013         intel_state->cdclk = intel_state->dev_cdclk =
6014                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6015
6016         if (!intel_state->active_crtcs)
6017                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6018
6019         return 0;
6020 }
6021
6022 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6023 {
6024         int max_pixclk = ilk_max_pixel_rate(state);
6025         struct intel_atomic_state *intel_state =
6026                 to_intel_atomic_state(state);
6027
6028         intel_state->cdclk = intel_state->dev_cdclk =
6029                 bxt_calc_cdclk(max_pixclk);
6030
6031         if (!intel_state->active_crtcs)
6032                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6033
6034         return 0;
6035 }
6036
6037 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6038 {
6039         unsigned int credits, default_credits;
6040
6041         if (IS_CHERRYVIEW(dev_priv))
6042                 default_credits = PFI_CREDIT(12);
6043         else
6044                 default_credits = PFI_CREDIT(8);
6045
6046         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6047                 /* CHV suggested value is 31 or 63 */
6048                 if (IS_CHERRYVIEW(dev_priv))
6049                         credits = PFI_CREDIT_63;
6050                 else
6051                         credits = PFI_CREDIT(15);
6052         } else {
6053                 credits = default_credits;
6054         }
6055
6056         /*
6057          * WA - write default credits before re-programming
6058          * FIXME: should we also set the resend bit here?
6059          */
6060         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6061                    default_credits);
6062
6063         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6064                    credits | PFI_CREDIT_RESEND);
6065
6066         /*
6067          * FIXME is this guaranteed to clear
6068          * immediately or should we poll for it?
6069          */
6070         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6071 }
6072
6073 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6074 {
6075         struct drm_device *dev = old_state->dev;
6076         struct drm_i915_private *dev_priv = to_i915(dev);
6077         struct intel_atomic_state *old_intel_state =
6078                 to_intel_atomic_state(old_state);
6079         unsigned req_cdclk = old_intel_state->dev_cdclk;
6080
6081         /*
6082          * FIXME: We can end up here with all power domains off, yet
6083          * with a CDCLK frequency other than the minimum. To account
6084          * for this take the PIPE-A power domain, which covers the HW
6085          * blocks needed for the following programming. This can be
6086          * removed once it's guaranteed that we get here either with
6087          * the minimum CDCLK set, or the required power domains
6088          * enabled.
6089          */
6090         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6091
6092         if (IS_CHERRYVIEW(dev))
6093                 cherryview_set_cdclk(dev, req_cdclk);
6094         else
6095                 valleyview_set_cdclk(dev, req_cdclk);
6096
6097         vlv_program_pfi_credits(dev_priv);
6098
6099         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6100 }
6101
6102 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6103 {
6104         struct drm_device *dev = crtc->dev;
6105         struct drm_i915_private *dev_priv = to_i915(dev);
6106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6107         struct intel_encoder *encoder;
6108         struct intel_crtc_state *pipe_config =
6109                 to_intel_crtc_state(crtc->state);
6110         int pipe = intel_crtc->pipe;
6111
6112         if (WARN_ON(intel_crtc->active))
6113                 return;
6114
6115         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6116                 intel_dp_set_m_n(intel_crtc, M1_N1);
6117
6118         intel_set_pipe_timings(intel_crtc);
6119         intel_set_pipe_src_size(intel_crtc);
6120
6121         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6122                 struct drm_i915_private *dev_priv = to_i915(dev);
6123
6124                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6125                 I915_WRITE(CHV_CANVAS(pipe), 0);
6126         }
6127
6128         i9xx_set_pipeconf(intel_crtc);
6129
6130         intel_crtc->active = true;
6131
6132         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6133
6134         for_each_encoder_on_crtc(dev, crtc, encoder)
6135                 if (encoder->pre_pll_enable)
6136                         encoder->pre_pll_enable(encoder);
6137
6138         if (IS_CHERRYVIEW(dev)) {
6139                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6140                 chv_enable_pll(intel_crtc, intel_crtc->config);
6141         } else {
6142                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6143                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6144         }
6145
6146         for_each_encoder_on_crtc(dev, crtc, encoder)
6147                 if (encoder->pre_enable)
6148                         encoder->pre_enable(encoder);
6149
6150         i9xx_pfit_enable(intel_crtc);
6151
6152         intel_color_load_luts(&pipe_config->base);
6153
6154         intel_update_watermarks(crtc);
6155         intel_enable_pipe(intel_crtc);
6156
6157         assert_vblank_disabled(crtc);
6158         drm_crtc_vblank_on(crtc);
6159
6160         for_each_encoder_on_crtc(dev, crtc, encoder)
6161                 encoder->enable(encoder);
6162 }
6163
6164 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6165 {
6166         struct drm_device *dev = crtc->base.dev;
6167         struct drm_i915_private *dev_priv = to_i915(dev);
6168
6169         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6170         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6171 }
6172
6173 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6174 {
6175         struct drm_device *dev = crtc->dev;
6176         struct drm_i915_private *dev_priv = to_i915(dev);
6177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178         struct intel_encoder *encoder;
6179         struct intel_crtc_state *pipe_config =
6180                 to_intel_crtc_state(crtc->state);
6181         enum pipe pipe = intel_crtc->pipe;
6182
6183         if (WARN_ON(intel_crtc->active))
6184                 return;
6185
6186         i9xx_set_pll_dividers(intel_crtc);
6187
6188         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6189                 intel_dp_set_m_n(intel_crtc, M1_N1);
6190
6191         intel_set_pipe_timings(intel_crtc);
6192         intel_set_pipe_src_size(intel_crtc);
6193
6194         i9xx_set_pipeconf(intel_crtc);
6195
6196         intel_crtc->active = true;
6197
6198         if (!IS_GEN2(dev))
6199                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6200
6201         for_each_encoder_on_crtc(dev, crtc, encoder)
6202                 if (encoder->pre_enable)
6203                         encoder->pre_enable(encoder);
6204
6205         i9xx_enable_pll(intel_crtc);
6206
6207         i9xx_pfit_enable(intel_crtc);
6208
6209         intel_color_load_luts(&pipe_config->base);
6210
6211         intel_update_watermarks(crtc);
6212         intel_enable_pipe(intel_crtc);
6213
6214         assert_vblank_disabled(crtc);
6215         drm_crtc_vblank_on(crtc);
6216
6217         for_each_encoder_on_crtc(dev, crtc, encoder)
6218                 encoder->enable(encoder);
6219 }
6220
6221 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6222 {
6223         struct drm_device *dev = crtc->base.dev;
6224         struct drm_i915_private *dev_priv = to_i915(dev);
6225
6226         if (!crtc->config->gmch_pfit.control)
6227                 return;
6228
6229         assert_pipe_disabled(dev_priv, crtc->pipe);
6230
6231         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6232                          I915_READ(PFIT_CONTROL));
6233         I915_WRITE(PFIT_CONTROL, 0);
6234 }
6235
6236 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6237 {
6238         struct drm_device *dev = crtc->dev;
6239         struct drm_i915_private *dev_priv = to_i915(dev);
6240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6241         struct intel_encoder *encoder;
6242         int pipe = intel_crtc->pipe;
6243
6244         /*
6245          * On gen2 planes are double buffered but the pipe isn't, so we must
6246          * wait for planes to fully turn off before disabling the pipe.
6247          */
6248         if (IS_GEN2(dev))
6249                 intel_wait_for_vblank(dev, pipe);
6250
6251         for_each_encoder_on_crtc(dev, crtc, encoder)
6252                 encoder->disable(encoder);
6253
6254         drm_crtc_vblank_off(crtc);
6255         assert_vblank_disabled(crtc);
6256
6257         intel_disable_pipe(intel_crtc);
6258
6259         i9xx_pfit_disable(intel_crtc);
6260
6261         for_each_encoder_on_crtc(dev, crtc, encoder)
6262                 if (encoder->post_disable)
6263                         encoder->post_disable(encoder);
6264
6265         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6266                 if (IS_CHERRYVIEW(dev))
6267                         chv_disable_pll(dev_priv, pipe);
6268                 else if (IS_VALLEYVIEW(dev))
6269                         vlv_disable_pll(dev_priv, pipe);
6270                 else
6271                         i9xx_disable_pll(intel_crtc);
6272         }
6273
6274         for_each_encoder_on_crtc(dev, crtc, encoder)
6275                 if (encoder->post_pll_disable)
6276                         encoder->post_pll_disable(encoder);
6277
6278         if (!IS_GEN2(dev))
6279                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6280 }
6281
6282 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6283 {
6284         struct intel_encoder *encoder;
6285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6287         enum intel_display_power_domain domain;
6288         unsigned long domains;
6289
6290         if (!intel_crtc->active)
6291                 return;
6292
6293         if (to_intel_plane_state(crtc->primary->state)->visible) {
6294                 WARN_ON(intel_crtc->flip_work);
6295
6296                 intel_pre_disable_primary_noatomic(crtc);
6297
6298                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6299                 to_intel_plane_state(crtc->primary->state)->visible = false;
6300         }
6301
6302         dev_priv->display.crtc_disable(crtc);
6303
6304         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6305                       crtc->base.id, crtc->name);
6306
6307         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6308         crtc->state->active = false;
6309         intel_crtc->active = false;
6310         crtc->enabled = false;
6311         crtc->state->connector_mask = 0;
6312         crtc->state->encoder_mask = 0;
6313
6314         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6315                 encoder->base.crtc = NULL;
6316
6317         intel_fbc_disable(intel_crtc);
6318         intel_update_watermarks(crtc);
6319         intel_disable_shared_dpll(intel_crtc);
6320
6321         domains = intel_crtc->enabled_power_domains;
6322         for_each_power_domain(domain, domains)
6323                 intel_display_power_put(dev_priv, domain);
6324         intel_crtc->enabled_power_domains = 0;
6325
6326         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6327         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6328 }
6329
6330 /*
6331  * turn all crtc's off, but do not adjust state
6332  * This has to be paired with a call to intel_modeset_setup_hw_state.
6333  */
6334 int intel_display_suspend(struct drm_device *dev)
6335 {
6336         struct drm_i915_private *dev_priv = to_i915(dev);
6337         struct drm_atomic_state *state;
6338         int ret;
6339
6340         state = drm_atomic_helper_suspend(dev);
6341         ret = PTR_ERR_OR_ZERO(state);
6342         if (ret)
6343                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6344         else
6345                 dev_priv->modeset_restore_state = state;
6346         return ret;
6347 }
6348
6349 void intel_encoder_destroy(struct drm_encoder *encoder)
6350 {
6351         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6352
6353         drm_encoder_cleanup(encoder);
6354         kfree(intel_encoder);
6355 }
6356
6357 /* Cross check the actual hw state with our own modeset state tracking (and it's
6358  * internal consistency). */
6359 static void intel_connector_verify_state(struct intel_connector *connector)
6360 {
6361         struct drm_crtc *crtc = connector->base.state->crtc;
6362
6363         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6364                       connector->base.base.id,
6365                       connector->base.name);
6366
6367         if (connector->get_hw_state(connector)) {
6368                 struct intel_encoder *encoder = connector->encoder;
6369                 struct drm_connector_state *conn_state = connector->base.state;
6370
6371                 I915_STATE_WARN(!crtc,
6372                          "connector enabled without attached crtc\n");
6373
6374                 if (!crtc)
6375                         return;
6376
6377                 I915_STATE_WARN(!crtc->state->active,
6378                       "connector is active, but attached crtc isn't\n");
6379
6380                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6381                         return;
6382
6383                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6384                         "atomic encoder doesn't match attached encoder\n");
6385
6386                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6387                         "attached encoder crtc differs from connector crtc\n");
6388         } else {
6389                 I915_STATE_WARN(crtc && crtc->state->active,
6390                         "attached crtc is active, but connector isn't\n");
6391                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6392                         "best encoder set without crtc!\n");
6393         }
6394 }
6395
6396 int intel_connector_init(struct intel_connector *connector)
6397 {
6398         drm_atomic_helper_connector_reset(&connector->base);
6399
6400         if (!connector->base.state)
6401                 return -ENOMEM;
6402
6403         return 0;
6404 }
6405
6406 struct intel_connector *intel_connector_alloc(void)
6407 {
6408         struct intel_connector *connector;
6409
6410         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6411         if (!connector)
6412                 return NULL;
6413
6414         if (intel_connector_init(connector) < 0) {
6415                 kfree(connector);
6416                 return NULL;
6417         }
6418
6419         return connector;
6420 }
6421
6422 /* Simple connector->get_hw_state implementation for encoders that support only
6423  * one connector and no cloning and hence the encoder state determines the state
6424  * of the connector. */
6425 bool intel_connector_get_hw_state(struct intel_connector *connector)
6426 {
6427         enum pipe pipe = 0;
6428         struct intel_encoder *encoder = connector->encoder;
6429
6430         return encoder->get_hw_state(encoder, &pipe);
6431 }
6432
6433 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6434 {
6435         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6436                 return crtc_state->fdi_lanes;
6437
6438         return 0;
6439 }
6440
6441 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6442                                      struct intel_crtc_state *pipe_config)
6443 {
6444         struct drm_atomic_state *state = pipe_config->base.state;
6445         struct intel_crtc *other_crtc;
6446         struct intel_crtc_state *other_crtc_state;
6447
6448         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6449                       pipe_name(pipe), pipe_config->fdi_lanes);
6450         if (pipe_config->fdi_lanes > 4) {
6451                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6452                               pipe_name(pipe), pipe_config->fdi_lanes);
6453                 return -EINVAL;
6454         }
6455
6456         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6457                 if (pipe_config->fdi_lanes > 2) {
6458                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6459                                       pipe_config->fdi_lanes);
6460                         return -EINVAL;
6461                 } else {
6462                         return 0;
6463                 }
6464         }
6465
6466         if (INTEL_INFO(dev)->num_pipes == 2)
6467                 return 0;
6468
6469         /* Ivybridge 3 pipe is really complicated */
6470         switch (pipe) {
6471         case PIPE_A:
6472                 return 0;
6473         case PIPE_B:
6474                 if (pipe_config->fdi_lanes <= 2)
6475                         return 0;
6476
6477                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6478                 other_crtc_state =
6479                         intel_atomic_get_crtc_state(state, other_crtc);
6480                 if (IS_ERR(other_crtc_state))
6481                         return PTR_ERR(other_crtc_state);
6482
6483                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6484                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6485                                       pipe_name(pipe), pipe_config->fdi_lanes);
6486                         return -EINVAL;
6487                 }
6488                 return 0;
6489         case PIPE_C:
6490                 if (pipe_config->fdi_lanes > 2) {
6491                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6492                                       pipe_name(pipe), pipe_config->fdi_lanes);
6493                         return -EINVAL;
6494                 }
6495
6496                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6497                 other_crtc_state =
6498                         intel_atomic_get_crtc_state(state, other_crtc);
6499                 if (IS_ERR(other_crtc_state))
6500                         return PTR_ERR(other_crtc_state);
6501
6502                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6503                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6504                         return -EINVAL;
6505                 }
6506                 return 0;
6507         default:
6508                 BUG();
6509         }
6510 }
6511
6512 #define RETRY 1
6513 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6514                                        struct intel_crtc_state *pipe_config)
6515 {
6516         struct drm_device *dev = intel_crtc->base.dev;
6517         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6518         int lane, link_bw, fdi_dotclock, ret;
6519         bool needs_recompute = false;
6520
6521 retry:
6522         /* FDI is a binary signal running at ~2.7GHz, encoding
6523          * each output octet as 10 bits. The actual frequency
6524          * is stored as a divider into a 100MHz clock, and the
6525          * mode pixel clock is stored in units of 1KHz.
6526          * Hence the bw of each lane in terms of the mode signal
6527          * is:
6528          */
6529         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6530
6531         fdi_dotclock = adjusted_mode->crtc_clock;
6532
6533         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6534                                            pipe_config->pipe_bpp);
6535
6536         pipe_config->fdi_lanes = lane;
6537
6538         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6539                                link_bw, &pipe_config->fdi_m_n);
6540
6541         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6542         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6543                 pipe_config->pipe_bpp -= 2*3;
6544                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6545                               pipe_config->pipe_bpp);
6546                 needs_recompute = true;
6547                 pipe_config->bw_constrained = true;
6548
6549                 goto retry;
6550         }
6551
6552         if (needs_recompute)
6553                 return RETRY;
6554
6555         return ret;
6556 }
6557
6558 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6559                                      struct intel_crtc_state *pipe_config)
6560 {
6561         if (pipe_config->pipe_bpp > 24)
6562                 return false;
6563
6564         /* HSW can handle pixel rate up to cdclk? */
6565         if (IS_HASWELL(dev_priv))
6566                 return true;
6567
6568         /*
6569          * We compare against max which means we must take
6570          * the increased cdclk requirement into account when
6571          * calculating the new cdclk.
6572          *
6573          * Should measure whether using a lower cdclk w/o IPS
6574          */
6575         return ilk_pipe_pixel_rate(pipe_config) <=
6576                 dev_priv->max_cdclk_freq * 95 / 100;
6577 }
6578
6579 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6580                                    struct intel_crtc_state *pipe_config)
6581 {
6582         struct drm_device *dev = crtc->base.dev;
6583         struct drm_i915_private *dev_priv = to_i915(dev);
6584
6585         pipe_config->ips_enabled = i915.enable_ips &&
6586                 hsw_crtc_supports_ips(crtc) &&
6587                 pipe_config_supports_ips(dev_priv, pipe_config);
6588 }
6589
6590 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6591 {
6592         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6593
6594         /* GDG double wide on either pipe, otherwise pipe A only */
6595         return INTEL_INFO(dev_priv)->gen < 4 &&
6596                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6597 }
6598
6599 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6600                                      struct intel_crtc_state *pipe_config)
6601 {
6602         struct drm_device *dev = crtc->base.dev;
6603         struct drm_i915_private *dev_priv = to_i915(dev);
6604         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6605         int clock_limit = dev_priv->max_dotclk_freq;
6606
6607         if (INTEL_INFO(dev)->gen < 4) {
6608                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6609
6610                 /*
6611                  * Enable double wide mode when the dot clock
6612                  * is > 90% of the (display) core speed.
6613                  */
6614                 if (intel_crtc_supports_double_wide(crtc) &&
6615                     adjusted_mode->crtc_clock > clock_limit) {
6616                         clock_limit = dev_priv->max_dotclk_freq;
6617                         pipe_config->double_wide = true;
6618                 }
6619         }
6620
6621         if (adjusted_mode->crtc_clock > clock_limit) {
6622                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6623                               adjusted_mode->crtc_clock, clock_limit,
6624                               yesno(pipe_config->double_wide));
6625                 return -EINVAL;
6626         }
6627
6628         /*
6629          * Pipe horizontal size must be even in:
6630          * - DVO ganged mode
6631          * - LVDS dual channel mode
6632          * - Double wide pipe
6633          */
6634         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6635              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6636                 pipe_config->pipe_src_w &= ~1;
6637
6638         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6639          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6640          */
6641         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6642                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6643                 return -EINVAL;
6644
6645         if (HAS_IPS(dev))
6646                 hsw_compute_ips_config(crtc, pipe_config);
6647
6648         if (pipe_config->has_pch_encoder)
6649                 return ironlake_fdi_compute_config(crtc, pipe_config);
6650
6651         return 0;
6652 }
6653
6654 static int skylake_get_display_clock_speed(struct drm_device *dev)
6655 {
6656         struct drm_i915_private *dev_priv = to_i915(dev);
6657         uint32_t cdctl;
6658
6659         skl_dpll0_update(dev_priv);
6660
6661         if (dev_priv->cdclk_pll.vco == 0)
6662                 return dev_priv->cdclk_pll.ref;
6663
6664         cdctl = I915_READ(CDCLK_CTL);
6665
6666         if (dev_priv->cdclk_pll.vco == 8640000) {
6667                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6668                 case CDCLK_FREQ_450_432:
6669                         return 432000;
6670                 case CDCLK_FREQ_337_308:
6671                         return 308571;
6672                 case CDCLK_FREQ_540:
6673                         return 540000;
6674                 case CDCLK_FREQ_675_617:
6675                         return 617143;
6676                 default:
6677                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6678                 }
6679         } else {
6680                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6681                 case CDCLK_FREQ_450_432:
6682                         return 450000;
6683                 case CDCLK_FREQ_337_308:
6684                         return 337500;
6685                 case CDCLK_FREQ_540:
6686                         return 540000;
6687                 case CDCLK_FREQ_675_617:
6688                         return 675000;
6689                 default:
6690                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6691                 }
6692         }
6693
6694         return dev_priv->cdclk_pll.ref;
6695 }
6696
6697 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6698 {
6699         u32 val;
6700
6701         dev_priv->cdclk_pll.ref = 19200;
6702         dev_priv->cdclk_pll.vco = 0;
6703
6704         val = I915_READ(BXT_DE_PLL_ENABLE);
6705         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6706                 return;
6707
6708         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6709                 return;
6710
6711         val = I915_READ(BXT_DE_PLL_CTL);
6712         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6713                 dev_priv->cdclk_pll.ref;
6714 }
6715
6716 static int broxton_get_display_clock_speed(struct drm_device *dev)
6717 {
6718         struct drm_i915_private *dev_priv = to_i915(dev);
6719         u32 divider;
6720         int div, vco;
6721
6722         bxt_de_pll_update(dev_priv);
6723
6724         vco = dev_priv->cdclk_pll.vco;
6725         if (vco == 0)
6726                 return dev_priv->cdclk_pll.ref;
6727
6728         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6729
6730         switch (divider) {
6731         case BXT_CDCLK_CD2X_DIV_SEL_1:
6732                 div = 2;
6733                 break;
6734         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6735                 div = 3;
6736                 break;
6737         case BXT_CDCLK_CD2X_DIV_SEL_2:
6738                 div = 4;
6739                 break;
6740         case BXT_CDCLK_CD2X_DIV_SEL_4:
6741                 div = 8;
6742                 break;
6743         default:
6744                 MISSING_CASE(divider);
6745                 return dev_priv->cdclk_pll.ref;
6746         }
6747
6748         return DIV_ROUND_CLOSEST(vco, div);
6749 }
6750
6751 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6752 {
6753         struct drm_i915_private *dev_priv = to_i915(dev);
6754         uint32_t lcpll = I915_READ(LCPLL_CTL);
6755         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6756
6757         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6758                 return 800000;
6759         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6760                 return 450000;
6761         else if (freq == LCPLL_CLK_FREQ_450)
6762                 return 450000;
6763         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6764                 return 540000;
6765         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6766                 return 337500;
6767         else
6768                 return 675000;
6769 }
6770
6771 static int haswell_get_display_clock_speed(struct drm_device *dev)
6772 {
6773         struct drm_i915_private *dev_priv = to_i915(dev);
6774         uint32_t lcpll = I915_READ(LCPLL_CTL);
6775         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6776
6777         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6778                 return 800000;
6779         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6780                 return 450000;
6781         else if (freq == LCPLL_CLK_FREQ_450)
6782                 return 450000;
6783         else if (IS_HSW_ULT(dev))
6784                 return 337500;
6785         else
6786                 return 540000;
6787 }
6788
6789 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6790 {
6791         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6792                                       CCK_DISPLAY_CLOCK_CONTROL);
6793 }
6794
6795 static int ilk_get_display_clock_speed(struct drm_device *dev)
6796 {
6797         return 450000;
6798 }
6799
6800 static int i945_get_display_clock_speed(struct drm_device *dev)
6801 {
6802         return 400000;
6803 }
6804
6805 static int i915_get_display_clock_speed(struct drm_device *dev)
6806 {
6807         return 333333;
6808 }
6809
6810 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6811 {
6812         return 200000;
6813 }
6814
6815 static int pnv_get_display_clock_speed(struct drm_device *dev)
6816 {
6817         u16 gcfgc = 0;
6818
6819         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6820
6821         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6822         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6823                 return 266667;
6824         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6825                 return 333333;
6826         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6827                 return 444444;
6828         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6829                 return 200000;
6830         default:
6831                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6832         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6833                 return 133333;
6834         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6835                 return 166667;
6836         }
6837 }
6838
6839 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6840 {
6841         u16 gcfgc = 0;
6842
6843         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6844
6845         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6846                 return 133333;
6847         else {
6848                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6849                 case GC_DISPLAY_CLOCK_333_MHZ:
6850                         return 333333;
6851                 default:
6852                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6853                         return 190000;
6854                 }
6855         }
6856 }
6857
6858 static int i865_get_display_clock_speed(struct drm_device *dev)
6859 {
6860         return 266667;
6861 }
6862
6863 static int i85x_get_display_clock_speed(struct drm_device *dev)
6864 {
6865         u16 hpllcc = 0;
6866
6867         /*
6868          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6869          * encoding is different :(
6870          * FIXME is this the right way to detect 852GM/852GMV?
6871          */
6872         if (dev->pdev->revision == 0x1)
6873                 return 133333;
6874
6875         pci_bus_read_config_word(dev->pdev->bus,
6876                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6877
6878         /* Assume that the hardware is in the high speed state.  This
6879          * should be the default.
6880          */
6881         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6882         case GC_CLOCK_133_200:
6883         case GC_CLOCK_133_200_2:
6884         case GC_CLOCK_100_200:
6885                 return 200000;
6886         case GC_CLOCK_166_250:
6887                 return 250000;
6888         case GC_CLOCK_100_133:
6889                 return 133333;
6890         case GC_CLOCK_133_266:
6891         case GC_CLOCK_133_266_2:
6892         case GC_CLOCK_166_266:
6893                 return 266667;
6894         }
6895
6896         /* Shouldn't happen */
6897         return 0;
6898 }
6899
6900 static int i830_get_display_clock_speed(struct drm_device *dev)
6901 {
6902         return 133333;
6903 }
6904
6905 static unsigned int intel_hpll_vco(struct drm_device *dev)
6906 {
6907         struct drm_i915_private *dev_priv = to_i915(dev);
6908         static const unsigned int blb_vco[8] = {
6909                 [0] = 3200000,
6910                 [1] = 4000000,
6911                 [2] = 5333333,
6912                 [3] = 4800000,
6913                 [4] = 6400000,
6914         };
6915         static const unsigned int pnv_vco[8] = {
6916                 [0] = 3200000,
6917                 [1] = 4000000,
6918                 [2] = 5333333,
6919                 [3] = 4800000,
6920                 [4] = 2666667,
6921         };
6922         static const unsigned int cl_vco[8] = {
6923                 [0] = 3200000,
6924                 [1] = 4000000,
6925                 [2] = 5333333,
6926                 [3] = 6400000,
6927                 [4] = 3333333,
6928                 [5] = 3566667,
6929                 [6] = 4266667,
6930         };
6931         static const unsigned int elk_vco[8] = {
6932                 [0] = 3200000,
6933                 [1] = 4000000,
6934                 [2] = 5333333,
6935                 [3] = 4800000,
6936         };
6937         static const unsigned int ctg_vco[8] = {
6938                 [0] = 3200000,
6939                 [1] = 4000000,
6940                 [2] = 5333333,
6941                 [3] = 6400000,
6942                 [4] = 2666667,
6943                 [5] = 4266667,
6944         };
6945         const unsigned int *vco_table;
6946         unsigned int vco;
6947         uint8_t tmp = 0;
6948
6949         /* FIXME other chipsets? */
6950         if (IS_GM45(dev))
6951                 vco_table = ctg_vco;
6952         else if (IS_G4X(dev))
6953                 vco_table = elk_vco;
6954         else if (IS_CRESTLINE(dev))
6955                 vco_table = cl_vco;
6956         else if (IS_PINEVIEW(dev))
6957                 vco_table = pnv_vco;
6958         else if (IS_G33(dev))
6959                 vco_table = blb_vco;
6960         else
6961                 return 0;
6962
6963         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6964
6965         vco = vco_table[tmp & 0x7];
6966         if (vco == 0)
6967                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6968         else
6969                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6970
6971         return vco;
6972 }
6973
6974 static int gm45_get_display_clock_speed(struct drm_device *dev)
6975 {
6976         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6977         uint16_t tmp = 0;
6978
6979         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6980
6981         cdclk_sel = (tmp >> 12) & 0x1;
6982
6983         switch (vco) {
6984         case 2666667:
6985         case 4000000:
6986         case 5333333:
6987                 return cdclk_sel ? 333333 : 222222;
6988         case 3200000:
6989                 return cdclk_sel ? 320000 : 228571;
6990         default:
6991                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6992                 return 222222;
6993         }
6994 }
6995
6996 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6997 {
6998         static const uint8_t div_3200[] = { 16, 10,  8 };
6999         static const uint8_t div_4000[] = { 20, 12, 10 };
7000         static const uint8_t div_5333[] = { 24, 16, 14 };
7001         const uint8_t *div_table;
7002         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7003         uint16_t tmp = 0;
7004
7005         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7006
7007         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7008
7009         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7010                 goto fail;
7011
7012         switch (vco) {
7013         case 3200000:
7014                 div_table = div_3200;
7015                 break;
7016         case 4000000:
7017                 div_table = div_4000;
7018                 break;
7019         case 5333333:
7020                 div_table = div_5333;
7021                 break;
7022         default:
7023                 goto fail;
7024         }
7025
7026         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7027
7028 fail:
7029         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7030         return 200000;
7031 }
7032
7033 static int g33_get_display_clock_speed(struct drm_device *dev)
7034 {
7035         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7036         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7037         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7038         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7039         const uint8_t *div_table;
7040         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7041         uint16_t tmp = 0;
7042
7043         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7044
7045         cdclk_sel = (tmp >> 4) & 0x7;
7046
7047         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7048                 goto fail;
7049
7050         switch (vco) {
7051         case 3200000:
7052                 div_table = div_3200;
7053                 break;
7054         case 4000000:
7055                 div_table = div_4000;
7056                 break;
7057         case 4800000:
7058                 div_table = div_4800;
7059                 break;
7060         case 5333333:
7061                 div_table = div_5333;
7062                 break;
7063         default:
7064                 goto fail;
7065         }
7066
7067         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7068
7069 fail:
7070         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7071         return 190476;
7072 }
7073
7074 static void
7075 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7076 {
7077         while (*num > DATA_LINK_M_N_MASK ||
7078                *den > DATA_LINK_M_N_MASK) {
7079                 *num >>= 1;
7080                 *den >>= 1;
7081         }
7082 }
7083
7084 static void compute_m_n(unsigned int m, unsigned int n,
7085                         uint32_t *ret_m, uint32_t *ret_n)
7086 {
7087         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7088         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7089         intel_reduce_m_n_ratio(ret_m, ret_n);
7090 }
7091
7092 void
7093 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7094                        int pixel_clock, int link_clock,
7095                        struct intel_link_m_n *m_n)
7096 {
7097         m_n->tu = 64;
7098
7099         compute_m_n(bits_per_pixel * pixel_clock,
7100                     link_clock * nlanes * 8,
7101                     &m_n->gmch_m, &m_n->gmch_n);
7102
7103         compute_m_n(pixel_clock, link_clock,
7104                     &m_n->link_m, &m_n->link_n);
7105 }
7106
7107 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7108 {
7109         if (i915.panel_use_ssc >= 0)
7110                 return i915.panel_use_ssc != 0;
7111         return dev_priv->vbt.lvds_use_ssc
7112                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7113 }
7114
7115 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7116 {
7117         return (1 << dpll->n) << 16 | dpll->m2;
7118 }
7119
7120 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7121 {
7122         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7123 }
7124
7125 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7126                                      struct intel_crtc_state *crtc_state,
7127                                      struct dpll *reduced_clock)
7128 {
7129         struct drm_device *dev = crtc->base.dev;
7130         u32 fp, fp2 = 0;
7131
7132         if (IS_PINEVIEW(dev)) {
7133                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7134                 if (reduced_clock)
7135                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7136         } else {
7137                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7138                 if (reduced_clock)
7139                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7140         }
7141
7142         crtc_state->dpll_hw_state.fp0 = fp;
7143
7144         crtc->lowfreq_avail = false;
7145         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7146             reduced_clock) {
7147                 crtc_state->dpll_hw_state.fp1 = fp2;
7148                 crtc->lowfreq_avail = true;
7149         } else {
7150                 crtc_state->dpll_hw_state.fp1 = fp;
7151         }
7152 }
7153
7154 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7155                 pipe)
7156 {
7157         u32 reg_val;
7158
7159         /*
7160          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7161          * and set it to a reasonable value instead.
7162          */
7163         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7164         reg_val &= 0xffffff00;
7165         reg_val |= 0x00000030;
7166         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7167
7168         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7169         reg_val &= 0x8cffffff;
7170         reg_val = 0x8c000000;
7171         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7172
7173         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7174         reg_val &= 0xffffff00;
7175         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7176
7177         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7178         reg_val &= 0x00ffffff;
7179         reg_val |= 0xb0000000;
7180         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7181 }
7182
7183 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7184                                          struct intel_link_m_n *m_n)
7185 {
7186         struct drm_device *dev = crtc->base.dev;
7187         struct drm_i915_private *dev_priv = to_i915(dev);
7188         int pipe = crtc->pipe;
7189
7190         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7191         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7192         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7193         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7194 }
7195
7196 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7197                                          struct intel_link_m_n *m_n,
7198                                          struct intel_link_m_n *m2_n2)
7199 {
7200         struct drm_device *dev = crtc->base.dev;
7201         struct drm_i915_private *dev_priv = to_i915(dev);
7202         int pipe = crtc->pipe;
7203         enum transcoder transcoder = crtc->config->cpu_transcoder;
7204
7205         if (INTEL_INFO(dev)->gen >= 5) {
7206                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7207                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7208                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7209                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7210                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7211                  * for gen < 8) and if DRRS is supported (to make sure the
7212                  * registers are not unnecessarily accessed).
7213                  */
7214                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7215                         crtc->config->has_drrs) {
7216                         I915_WRITE(PIPE_DATA_M2(transcoder),
7217                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7218                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7219                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7220                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7221                 }
7222         } else {
7223                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7224                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7225                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7226                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7227         }
7228 }
7229
7230 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7231 {
7232         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7233
7234         if (m_n == M1_N1) {
7235                 dp_m_n = &crtc->config->dp_m_n;
7236                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7237         } else if (m_n == M2_N2) {
7238
7239                 /*
7240                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7241                  * needs to be programmed into M1_N1.
7242                  */
7243                 dp_m_n = &crtc->config->dp_m2_n2;
7244         } else {
7245                 DRM_ERROR("Unsupported divider value\n");
7246                 return;
7247         }
7248
7249         if (crtc->config->has_pch_encoder)
7250                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7251         else
7252                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7253 }
7254
7255 static void vlv_compute_dpll(struct intel_crtc *crtc,
7256                              struct intel_crtc_state *pipe_config)
7257 {
7258         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7259                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7260         if (crtc->pipe != PIPE_A)
7261                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7262
7263         /* DPLL not used with DSI, but still need the rest set up */
7264         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7265                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7266                         DPLL_EXT_BUFFER_ENABLE_VLV;
7267
7268         pipe_config->dpll_hw_state.dpll_md =
7269                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7270 }
7271
7272 static void chv_compute_dpll(struct intel_crtc *crtc,
7273                              struct intel_crtc_state *pipe_config)
7274 {
7275         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7276                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7277         if (crtc->pipe != PIPE_A)
7278                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7279
7280         /* DPLL not used with DSI, but still need the rest set up */
7281         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7282                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7283
7284         pipe_config->dpll_hw_state.dpll_md =
7285                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7286 }
7287
7288 static void vlv_prepare_pll(struct intel_crtc *crtc,
7289                             const struct intel_crtc_state *pipe_config)
7290 {
7291         struct drm_device *dev = crtc->base.dev;
7292         struct drm_i915_private *dev_priv = to_i915(dev);
7293         enum pipe pipe = crtc->pipe;
7294         u32 mdiv;
7295         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7296         u32 coreclk, reg_val;
7297
7298         /* Enable Refclk */
7299         I915_WRITE(DPLL(pipe),
7300                    pipe_config->dpll_hw_state.dpll &
7301                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7302
7303         /* No need to actually set up the DPLL with DSI */
7304         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7305                 return;
7306
7307         mutex_lock(&dev_priv->sb_lock);
7308
7309         bestn = pipe_config->dpll.n;
7310         bestm1 = pipe_config->dpll.m1;
7311         bestm2 = pipe_config->dpll.m2;
7312         bestp1 = pipe_config->dpll.p1;
7313         bestp2 = pipe_config->dpll.p2;
7314
7315         /* See eDP HDMI DPIO driver vbios notes doc */
7316
7317         /* PLL B needs special handling */
7318         if (pipe == PIPE_B)
7319                 vlv_pllb_recal_opamp(dev_priv, pipe);
7320
7321         /* Set up Tx target for periodic Rcomp update */
7322         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7323
7324         /* Disable target IRef on PLL */
7325         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7326         reg_val &= 0x00ffffff;
7327         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7328
7329         /* Disable fast lock */
7330         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7331
7332         /* Set idtafcrecal before PLL is enabled */
7333         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7334         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7335         mdiv |= ((bestn << DPIO_N_SHIFT));
7336         mdiv |= (1 << DPIO_K_SHIFT);
7337
7338         /*
7339          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7340          * but we don't support that).
7341          * Note: don't use the DAC post divider as it seems unstable.
7342          */
7343         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7344         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7345
7346         mdiv |= DPIO_ENABLE_CALIBRATION;
7347         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7348
7349         /* Set HBR and RBR LPF coefficients */
7350         if (pipe_config->port_clock == 162000 ||
7351             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7352             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7353                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7354                                  0x009f0003);
7355         else
7356                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7357                                  0x00d0000f);
7358
7359         if (intel_crtc_has_dp_encoder(pipe_config)) {
7360                 /* Use SSC source */
7361                 if (pipe == PIPE_A)
7362                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7363                                          0x0df40000);
7364                 else
7365                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7366                                          0x0df70000);
7367         } else { /* HDMI or VGA */
7368                 /* Use bend source */
7369                 if (pipe == PIPE_A)
7370                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7371                                          0x0df70000);
7372                 else
7373                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7374                                          0x0df40000);
7375         }
7376
7377         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7378         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7379         if (intel_crtc_has_dp_encoder(crtc->config))
7380                 coreclk |= 0x01000000;
7381         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7382
7383         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7384         mutex_unlock(&dev_priv->sb_lock);
7385 }
7386
7387 static void chv_prepare_pll(struct intel_crtc *crtc,
7388                             const struct intel_crtc_state *pipe_config)
7389 {
7390         struct drm_device *dev = crtc->base.dev;
7391         struct drm_i915_private *dev_priv = to_i915(dev);
7392         enum pipe pipe = crtc->pipe;
7393         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7394         u32 loopfilter, tribuf_calcntr;
7395         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7396         u32 dpio_val;
7397         int vco;
7398
7399         /* Enable Refclk and SSC */
7400         I915_WRITE(DPLL(pipe),
7401                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7402
7403         /* No need to actually set up the DPLL with DSI */
7404         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7405                 return;
7406
7407         bestn = pipe_config->dpll.n;
7408         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7409         bestm1 = pipe_config->dpll.m1;
7410         bestm2 = pipe_config->dpll.m2 >> 22;
7411         bestp1 = pipe_config->dpll.p1;
7412         bestp2 = pipe_config->dpll.p2;
7413         vco = pipe_config->dpll.vco;
7414         dpio_val = 0;
7415         loopfilter = 0;
7416
7417         mutex_lock(&dev_priv->sb_lock);
7418
7419         /* p1 and p2 divider */
7420         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7421                         5 << DPIO_CHV_S1_DIV_SHIFT |
7422                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7423                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7424                         1 << DPIO_CHV_K_DIV_SHIFT);
7425
7426         /* Feedback post-divider - m2 */
7427         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7428
7429         /* Feedback refclk divider - n and m1 */
7430         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7431                         DPIO_CHV_M1_DIV_BY_2 |
7432                         1 << DPIO_CHV_N_DIV_SHIFT);
7433
7434         /* M2 fraction division */
7435         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7436
7437         /* M2 fraction division enable */
7438         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7439         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7440         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7441         if (bestm2_frac)
7442                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7443         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7444
7445         /* Program digital lock detect threshold */
7446         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7447         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7448                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7449         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7450         if (!bestm2_frac)
7451                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7452         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7453
7454         /* Loop filter */
7455         if (vco == 5400000) {
7456                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7457                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7458                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7459                 tribuf_calcntr = 0x9;
7460         } else if (vco <= 6200000) {
7461                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7462                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7463                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7464                 tribuf_calcntr = 0x9;
7465         } else if (vco <= 6480000) {
7466                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7467                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7468                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7469                 tribuf_calcntr = 0x8;
7470         } else {
7471                 /* Not supported. Apply the same limits as in the max case */
7472                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7473                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7474                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7475                 tribuf_calcntr = 0;
7476         }
7477         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7478
7479         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7480         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7481         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7482         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7483
7484         /* AFC Recal */
7485         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7486                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7487                         DPIO_AFC_RECAL);
7488
7489         mutex_unlock(&dev_priv->sb_lock);
7490 }
7491
7492 /**
7493  * vlv_force_pll_on - forcibly enable just the PLL
7494  * @dev_priv: i915 private structure
7495  * @pipe: pipe PLL to enable
7496  * @dpll: PLL configuration
7497  *
7498  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7499  * in cases where we need the PLL enabled even when @pipe is not going to
7500  * be enabled.
7501  */
7502 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7503                      const struct dpll *dpll)
7504 {
7505         struct intel_crtc *crtc =
7506                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7507         struct intel_crtc_state *pipe_config;
7508
7509         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7510         if (!pipe_config)
7511                 return -ENOMEM;
7512
7513         pipe_config->base.crtc = &crtc->base;
7514         pipe_config->pixel_multiplier = 1;
7515         pipe_config->dpll = *dpll;
7516
7517         if (IS_CHERRYVIEW(dev)) {
7518                 chv_compute_dpll(crtc, pipe_config);
7519                 chv_prepare_pll(crtc, pipe_config);
7520                 chv_enable_pll(crtc, pipe_config);
7521         } else {
7522                 vlv_compute_dpll(crtc, pipe_config);
7523                 vlv_prepare_pll(crtc, pipe_config);
7524                 vlv_enable_pll(crtc, pipe_config);
7525         }
7526
7527         kfree(pipe_config);
7528
7529         return 0;
7530 }
7531
7532 /**
7533  * vlv_force_pll_off - forcibly disable just the PLL
7534  * @dev_priv: i915 private structure
7535  * @pipe: pipe PLL to disable
7536  *
7537  * Disable the PLL for @pipe. To be used in cases where we need
7538  * the PLL enabled even when @pipe is not going to be enabled.
7539  */
7540 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7541 {
7542         if (IS_CHERRYVIEW(dev))
7543                 chv_disable_pll(to_i915(dev), pipe);
7544         else
7545                 vlv_disable_pll(to_i915(dev), pipe);
7546 }
7547
7548 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7549                               struct intel_crtc_state *crtc_state,
7550                               struct dpll *reduced_clock)
7551 {
7552         struct drm_device *dev = crtc->base.dev;
7553         struct drm_i915_private *dev_priv = to_i915(dev);
7554         u32 dpll;
7555         struct dpll *clock = &crtc_state->dpll;
7556
7557         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7558
7559         dpll = DPLL_VGA_MODE_DIS;
7560
7561         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7562                 dpll |= DPLLB_MODE_LVDS;
7563         else
7564                 dpll |= DPLLB_MODE_DAC_SERIAL;
7565
7566         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7567                 dpll |= (crtc_state->pixel_multiplier - 1)
7568                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7569         }
7570
7571         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7572             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7573                 dpll |= DPLL_SDVO_HIGH_SPEED;
7574
7575         if (intel_crtc_has_dp_encoder(crtc_state))
7576                 dpll |= DPLL_SDVO_HIGH_SPEED;
7577
7578         /* compute bitmask from p1 value */
7579         if (IS_PINEVIEW(dev))
7580                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7581         else {
7582                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7583                 if (IS_G4X(dev) && reduced_clock)
7584                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7585         }
7586         switch (clock->p2) {
7587         case 5:
7588                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7589                 break;
7590         case 7:
7591                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7592                 break;
7593         case 10:
7594                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7595                 break;
7596         case 14:
7597                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7598                 break;
7599         }
7600         if (INTEL_INFO(dev)->gen >= 4)
7601                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7602
7603         if (crtc_state->sdvo_tv_clock)
7604                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7605         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7606                  intel_panel_use_ssc(dev_priv))
7607                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7608         else
7609                 dpll |= PLL_REF_INPUT_DREFCLK;
7610
7611         dpll |= DPLL_VCO_ENABLE;
7612         crtc_state->dpll_hw_state.dpll = dpll;
7613
7614         if (INTEL_INFO(dev)->gen >= 4) {
7615                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7616                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7617                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7618         }
7619 }
7620
7621 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7622                               struct intel_crtc_state *crtc_state,
7623                               struct dpll *reduced_clock)
7624 {
7625         struct drm_device *dev = crtc->base.dev;
7626         struct drm_i915_private *dev_priv = to_i915(dev);
7627         u32 dpll;
7628         struct dpll *clock = &crtc_state->dpll;
7629
7630         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7631
7632         dpll = DPLL_VGA_MODE_DIS;
7633
7634         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7635                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7636         } else {
7637                 if (clock->p1 == 2)
7638                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7639                 else
7640                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7641                 if (clock->p2 == 4)
7642                         dpll |= PLL_P2_DIVIDE_BY_4;
7643         }
7644
7645         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7646                 dpll |= DPLL_DVO_2X_MODE;
7647
7648         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7649             intel_panel_use_ssc(dev_priv))
7650                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7651         else
7652                 dpll |= PLL_REF_INPUT_DREFCLK;
7653
7654         dpll |= DPLL_VCO_ENABLE;
7655         crtc_state->dpll_hw_state.dpll = dpll;
7656 }
7657
7658 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7659 {
7660         struct drm_device *dev = intel_crtc->base.dev;
7661         struct drm_i915_private *dev_priv = to_i915(dev);
7662         enum pipe pipe = intel_crtc->pipe;
7663         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7664         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7665         uint32_t crtc_vtotal, crtc_vblank_end;
7666         int vsyncshift = 0;
7667
7668         /* We need to be careful not to changed the adjusted mode, for otherwise
7669          * the hw state checker will get angry at the mismatch. */
7670         crtc_vtotal = adjusted_mode->crtc_vtotal;
7671         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7672
7673         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7674                 /* the chip adds 2 halflines automatically */
7675                 crtc_vtotal -= 1;
7676                 crtc_vblank_end -= 1;
7677
7678                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7679                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7680                 else
7681                         vsyncshift = adjusted_mode->crtc_hsync_start -
7682                                 adjusted_mode->crtc_htotal / 2;
7683                 if (vsyncshift < 0)
7684                         vsyncshift += adjusted_mode->crtc_htotal;
7685         }
7686
7687         if (INTEL_INFO(dev)->gen > 3)
7688                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7689
7690         I915_WRITE(HTOTAL(cpu_transcoder),
7691                    (adjusted_mode->crtc_hdisplay - 1) |
7692                    ((adjusted_mode->crtc_htotal - 1) << 16));
7693         I915_WRITE(HBLANK(cpu_transcoder),
7694                    (adjusted_mode->crtc_hblank_start - 1) |
7695                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7696         I915_WRITE(HSYNC(cpu_transcoder),
7697                    (adjusted_mode->crtc_hsync_start - 1) |
7698                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7699
7700         I915_WRITE(VTOTAL(cpu_transcoder),
7701                    (adjusted_mode->crtc_vdisplay - 1) |
7702                    ((crtc_vtotal - 1) << 16));
7703         I915_WRITE(VBLANK(cpu_transcoder),
7704                    (adjusted_mode->crtc_vblank_start - 1) |
7705                    ((crtc_vblank_end - 1) << 16));
7706         I915_WRITE(VSYNC(cpu_transcoder),
7707                    (adjusted_mode->crtc_vsync_start - 1) |
7708                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7709
7710         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7711          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7712          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7713          * bits. */
7714         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7715             (pipe == PIPE_B || pipe == PIPE_C))
7716                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7717
7718 }
7719
7720 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7721 {
7722         struct drm_device *dev = intel_crtc->base.dev;
7723         struct drm_i915_private *dev_priv = to_i915(dev);
7724         enum pipe pipe = intel_crtc->pipe;
7725
7726         /* pipesrc controls the size that is scaled from, which should
7727          * always be the user's requested size.
7728          */
7729         I915_WRITE(PIPESRC(pipe),
7730                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7731                    (intel_crtc->config->pipe_src_h - 1));
7732 }
7733
7734 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7735                                    struct intel_crtc_state *pipe_config)
7736 {
7737         struct drm_device *dev = crtc->base.dev;
7738         struct drm_i915_private *dev_priv = to_i915(dev);
7739         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7740         uint32_t tmp;
7741
7742         tmp = I915_READ(HTOTAL(cpu_transcoder));
7743         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7744         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7745         tmp = I915_READ(HBLANK(cpu_transcoder));
7746         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7747         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7748         tmp = I915_READ(HSYNC(cpu_transcoder));
7749         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7750         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7751
7752         tmp = I915_READ(VTOTAL(cpu_transcoder));
7753         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7754         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7755         tmp = I915_READ(VBLANK(cpu_transcoder));
7756         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7757         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7758         tmp = I915_READ(VSYNC(cpu_transcoder));
7759         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7760         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7761
7762         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7763                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7764                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7765                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7766         }
7767 }
7768
7769 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7770                                     struct intel_crtc_state *pipe_config)
7771 {
7772         struct drm_device *dev = crtc->base.dev;
7773         struct drm_i915_private *dev_priv = to_i915(dev);
7774         u32 tmp;
7775
7776         tmp = I915_READ(PIPESRC(crtc->pipe));
7777         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7778         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7779
7780         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7781         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7782 }
7783
7784 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7785                                  struct intel_crtc_state *pipe_config)
7786 {
7787         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7788         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7789         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7790         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7791
7792         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7793         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7794         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7795         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7796
7797         mode->flags = pipe_config->base.adjusted_mode.flags;
7798         mode->type = DRM_MODE_TYPE_DRIVER;
7799
7800         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7801         mode->flags |= pipe_config->base.adjusted_mode.flags;
7802
7803         mode->hsync = drm_mode_hsync(mode);
7804         mode->vrefresh = drm_mode_vrefresh(mode);
7805         drm_mode_set_name(mode);
7806 }
7807
7808 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7809 {
7810         struct drm_device *dev = intel_crtc->base.dev;
7811         struct drm_i915_private *dev_priv = to_i915(dev);
7812         uint32_t pipeconf;
7813
7814         pipeconf = 0;
7815
7816         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7817             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7818                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7819
7820         if (intel_crtc->config->double_wide)
7821                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7822
7823         /* only g4x and later have fancy bpc/dither controls */
7824         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7825                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7826                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7827                         pipeconf |= PIPECONF_DITHER_EN |
7828                                     PIPECONF_DITHER_TYPE_SP;
7829
7830                 switch (intel_crtc->config->pipe_bpp) {
7831                 case 18:
7832                         pipeconf |= PIPECONF_6BPC;
7833                         break;
7834                 case 24:
7835                         pipeconf |= PIPECONF_8BPC;
7836                         break;
7837                 case 30:
7838                         pipeconf |= PIPECONF_10BPC;
7839                         break;
7840                 default:
7841                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7842                         BUG();
7843                 }
7844         }
7845
7846         if (HAS_PIPE_CXSR(dev)) {
7847                 if (intel_crtc->lowfreq_avail) {
7848                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7849                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7850                 } else {
7851                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7852                 }
7853         }
7854
7855         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7856                 if (INTEL_INFO(dev)->gen < 4 ||
7857                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7858                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7859                 else
7860                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7861         } else
7862                 pipeconf |= PIPECONF_PROGRESSIVE;
7863
7864         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7865              intel_crtc->config->limited_color_range)
7866                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7867
7868         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7869         POSTING_READ(PIPECONF(intel_crtc->pipe));
7870 }
7871
7872 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7873                                    struct intel_crtc_state *crtc_state)
7874 {
7875         struct drm_device *dev = crtc->base.dev;
7876         struct drm_i915_private *dev_priv = to_i915(dev);
7877         const struct intel_limit *limit;
7878         int refclk = 48000;
7879
7880         memset(&crtc_state->dpll_hw_state, 0,
7881                sizeof(crtc_state->dpll_hw_state));
7882
7883         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7884                 if (intel_panel_use_ssc(dev_priv)) {
7885                         refclk = dev_priv->vbt.lvds_ssc_freq;
7886                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7887                 }
7888
7889                 limit = &intel_limits_i8xx_lvds;
7890         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7891                 limit = &intel_limits_i8xx_dvo;
7892         } else {
7893                 limit = &intel_limits_i8xx_dac;
7894         }
7895
7896         if (!crtc_state->clock_set &&
7897             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7898                                  refclk, NULL, &crtc_state->dpll)) {
7899                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7900                 return -EINVAL;
7901         }
7902
7903         i8xx_compute_dpll(crtc, crtc_state, NULL);
7904
7905         return 0;
7906 }
7907
7908 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7909                                   struct intel_crtc_state *crtc_state)
7910 {
7911         struct drm_device *dev = crtc->base.dev;
7912         struct drm_i915_private *dev_priv = to_i915(dev);
7913         const struct intel_limit *limit;
7914         int refclk = 96000;
7915
7916         memset(&crtc_state->dpll_hw_state, 0,
7917                sizeof(crtc_state->dpll_hw_state));
7918
7919         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7920                 if (intel_panel_use_ssc(dev_priv)) {
7921                         refclk = dev_priv->vbt.lvds_ssc_freq;
7922                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7923                 }
7924
7925                 if (intel_is_dual_link_lvds(dev))
7926                         limit = &intel_limits_g4x_dual_channel_lvds;
7927                 else
7928                         limit = &intel_limits_g4x_single_channel_lvds;
7929         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7930                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7931                 limit = &intel_limits_g4x_hdmi;
7932         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7933                 limit = &intel_limits_g4x_sdvo;
7934         } else {
7935                 /* The option is for other outputs */
7936                 limit = &intel_limits_i9xx_sdvo;
7937         }
7938
7939         if (!crtc_state->clock_set &&
7940             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7941                                 refclk, NULL, &crtc_state->dpll)) {
7942                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7943                 return -EINVAL;
7944         }
7945
7946         i9xx_compute_dpll(crtc, crtc_state, NULL);
7947
7948         return 0;
7949 }
7950
7951 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7952                                   struct intel_crtc_state *crtc_state)
7953 {
7954         struct drm_device *dev = crtc->base.dev;
7955         struct drm_i915_private *dev_priv = to_i915(dev);
7956         const struct intel_limit *limit;
7957         int refclk = 96000;
7958
7959         memset(&crtc_state->dpll_hw_state, 0,
7960                sizeof(crtc_state->dpll_hw_state));
7961
7962         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7963                 if (intel_panel_use_ssc(dev_priv)) {
7964                         refclk = dev_priv->vbt.lvds_ssc_freq;
7965                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7966                 }
7967
7968                 limit = &intel_limits_pineview_lvds;
7969         } else {
7970                 limit = &intel_limits_pineview_sdvo;
7971         }
7972
7973         if (!crtc_state->clock_set &&
7974             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7975                                 refclk, NULL, &crtc_state->dpll)) {
7976                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7977                 return -EINVAL;
7978         }
7979
7980         i9xx_compute_dpll(crtc, crtc_state, NULL);
7981
7982         return 0;
7983 }
7984
7985 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7986                                    struct intel_crtc_state *crtc_state)
7987 {
7988         struct drm_device *dev = crtc->base.dev;
7989         struct drm_i915_private *dev_priv = to_i915(dev);
7990         const struct intel_limit *limit;
7991         int refclk = 96000;
7992
7993         memset(&crtc_state->dpll_hw_state, 0,
7994                sizeof(crtc_state->dpll_hw_state));
7995
7996         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7997                 if (intel_panel_use_ssc(dev_priv)) {
7998                         refclk = dev_priv->vbt.lvds_ssc_freq;
7999                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8000                 }
8001
8002                 limit = &intel_limits_i9xx_lvds;
8003         } else {
8004                 limit = &intel_limits_i9xx_sdvo;
8005         }
8006
8007         if (!crtc_state->clock_set &&
8008             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8009                                  refclk, NULL, &crtc_state->dpll)) {
8010                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8011                 return -EINVAL;
8012         }
8013
8014         i9xx_compute_dpll(crtc, crtc_state, NULL);
8015
8016         return 0;
8017 }
8018
8019 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8020                                   struct intel_crtc_state *crtc_state)
8021 {
8022         int refclk = 100000;
8023         const struct intel_limit *limit = &intel_limits_chv;
8024
8025         memset(&crtc_state->dpll_hw_state, 0,
8026                sizeof(crtc_state->dpll_hw_state));
8027
8028         if (!crtc_state->clock_set &&
8029             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8030                                 refclk, NULL, &crtc_state->dpll)) {
8031                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8032                 return -EINVAL;
8033         }
8034
8035         chv_compute_dpll(crtc, crtc_state);
8036
8037         return 0;
8038 }
8039
8040 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8041                                   struct intel_crtc_state *crtc_state)
8042 {
8043         int refclk = 100000;
8044         const struct intel_limit *limit = &intel_limits_vlv;
8045
8046         memset(&crtc_state->dpll_hw_state, 0,
8047                sizeof(crtc_state->dpll_hw_state));
8048
8049         if (!crtc_state->clock_set &&
8050             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8051                                 refclk, NULL, &crtc_state->dpll)) {
8052                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8053                 return -EINVAL;
8054         }
8055
8056         vlv_compute_dpll(crtc, crtc_state);
8057
8058         return 0;
8059 }
8060
8061 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8062                                  struct intel_crtc_state *pipe_config)
8063 {
8064         struct drm_device *dev = crtc->base.dev;
8065         struct drm_i915_private *dev_priv = to_i915(dev);
8066         uint32_t tmp;
8067
8068         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8069                 return;
8070
8071         tmp = I915_READ(PFIT_CONTROL);
8072         if (!(tmp & PFIT_ENABLE))
8073                 return;
8074
8075         /* Check whether the pfit is attached to our pipe. */
8076         if (INTEL_INFO(dev)->gen < 4) {
8077                 if (crtc->pipe != PIPE_B)
8078                         return;
8079         } else {
8080                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8081                         return;
8082         }
8083
8084         pipe_config->gmch_pfit.control = tmp;
8085         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8086 }
8087
8088 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8089                                struct intel_crtc_state *pipe_config)
8090 {
8091         struct drm_device *dev = crtc->base.dev;
8092         struct drm_i915_private *dev_priv = to_i915(dev);
8093         int pipe = pipe_config->cpu_transcoder;
8094         struct dpll clock;
8095         u32 mdiv;
8096         int refclk = 100000;
8097
8098         /* In case of DSI, DPLL will not be used */
8099         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8100                 return;
8101
8102         mutex_lock(&dev_priv->sb_lock);
8103         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8104         mutex_unlock(&dev_priv->sb_lock);
8105
8106         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8107         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8108         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8109         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8110         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8111
8112         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8113 }
8114
8115 static void
8116 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8117                               struct intel_initial_plane_config *plane_config)
8118 {
8119         struct drm_device *dev = crtc->base.dev;
8120         struct drm_i915_private *dev_priv = to_i915(dev);
8121         u32 val, base, offset;
8122         int pipe = crtc->pipe, plane = crtc->plane;
8123         int fourcc, pixel_format;
8124         unsigned int aligned_height;
8125         struct drm_framebuffer *fb;
8126         struct intel_framebuffer *intel_fb;
8127
8128         val = I915_READ(DSPCNTR(plane));
8129         if (!(val & DISPLAY_PLANE_ENABLE))
8130                 return;
8131
8132         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8133         if (!intel_fb) {
8134                 DRM_DEBUG_KMS("failed to alloc fb\n");
8135                 return;
8136         }
8137
8138         fb = &intel_fb->base;
8139
8140         if (INTEL_INFO(dev)->gen >= 4) {
8141                 if (val & DISPPLANE_TILED) {
8142                         plane_config->tiling = I915_TILING_X;
8143                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8144                 }
8145         }
8146
8147         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8148         fourcc = i9xx_format_to_fourcc(pixel_format);
8149         fb->pixel_format = fourcc;
8150         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8151
8152         if (INTEL_INFO(dev)->gen >= 4) {
8153                 if (plane_config->tiling)
8154                         offset = I915_READ(DSPTILEOFF(plane));
8155                 else
8156                         offset = I915_READ(DSPLINOFF(plane));
8157                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8158         } else {
8159                 base = I915_READ(DSPADDR(plane));
8160         }
8161         plane_config->base = base;
8162
8163         val = I915_READ(PIPESRC(pipe));
8164         fb->width = ((val >> 16) & 0xfff) + 1;
8165         fb->height = ((val >> 0) & 0xfff) + 1;
8166
8167         val = I915_READ(DSPSTRIDE(pipe));
8168         fb->pitches[0] = val & 0xffffffc0;
8169
8170         aligned_height = intel_fb_align_height(dev, fb->height,
8171                                                fb->pixel_format,
8172                                                fb->modifier[0]);
8173
8174         plane_config->size = fb->pitches[0] * aligned_height;
8175
8176         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8177                       pipe_name(pipe), plane, fb->width, fb->height,
8178                       fb->bits_per_pixel, base, fb->pitches[0],
8179                       plane_config->size);
8180
8181         plane_config->fb = intel_fb;
8182 }
8183
8184 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8185                                struct intel_crtc_state *pipe_config)
8186 {
8187         struct drm_device *dev = crtc->base.dev;
8188         struct drm_i915_private *dev_priv = to_i915(dev);
8189         int pipe = pipe_config->cpu_transcoder;
8190         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8191         struct dpll clock;
8192         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8193         int refclk = 100000;
8194
8195         /* In case of DSI, DPLL will not be used */
8196         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8197                 return;
8198
8199         mutex_lock(&dev_priv->sb_lock);
8200         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8201         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8202         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8203         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8204         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8205         mutex_unlock(&dev_priv->sb_lock);
8206
8207         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8208         clock.m2 = (pll_dw0 & 0xff) << 22;
8209         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8210                 clock.m2 |= pll_dw2 & 0x3fffff;
8211         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8212         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8213         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8214
8215         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8216 }
8217
8218 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8219                                  struct intel_crtc_state *pipe_config)
8220 {
8221         struct drm_device *dev = crtc->base.dev;
8222         struct drm_i915_private *dev_priv = to_i915(dev);
8223         enum intel_display_power_domain power_domain;
8224         uint32_t tmp;
8225         bool ret;
8226
8227         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8228         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8229                 return false;
8230
8231         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8232         pipe_config->shared_dpll = NULL;
8233
8234         ret = false;
8235
8236         tmp = I915_READ(PIPECONF(crtc->pipe));
8237         if (!(tmp & PIPECONF_ENABLE))
8238                 goto out;
8239
8240         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8241                 switch (tmp & PIPECONF_BPC_MASK) {
8242                 case PIPECONF_6BPC:
8243                         pipe_config->pipe_bpp = 18;
8244                         break;
8245                 case PIPECONF_8BPC:
8246                         pipe_config->pipe_bpp = 24;
8247                         break;
8248                 case PIPECONF_10BPC:
8249                         pipe_config->pipe_bpp = 30;
8250                         break;
8251                 default:
8252                         break;
8253                 }
8254         }
8255
8256         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8257             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8258                 pipe_config->limited_color_range = true;
8259
8260         if (INTEL_INFO(dev)->gen < 4)
8261                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8262
8263         intel_get_pipe_timings(crtc, pipe_config);
8264         intel_get_pipe_src_size(crtc, pipe_config);
8265
8266         i9xx_get_pfit_config(crtc, pipe_config);
8267
8268         if (INTEL_INFO(dev)->gen >= 4) {
8269                 /* No way to read it out on pipes B and C */
8270                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8271                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8272                 else
8273                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8274                 pipe_config->pixel_multiplier =
8275                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8276                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8277                 pipe_config->dpll_hw_state.dpll_md = tmp;
8278         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8279                 tmp = I915_READ(DPLL(crtc->pipe));
8280                 pipe_config->pixel_multiplier =
8281                         ((tmp & SDVO_MULTIPLIER_MASK)
8282                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8283         } else {
8284                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8285                  * port and will be fixed up in the encoder->get_config
8286                  * function. */
8287                 pipe_config->pixel_multiplier = 1;
8288         }
8289         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8290         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8291                 /*
8292                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8293                  * on 830. Filter it out here so that we don't
8294                  * report errors due to that.
8295                  */
8296                 if (IS_I830(dev))
8297                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8298
8299                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8300                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8301         } else {
8302                 /* Mask out read-only status bits. */
8303                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8304                                                      DPLL_PORTC_READY_MASK |
8305                                                      DPLL_PORTB_READY_MASK);
8306         }
8307
8308         if (IS_CHERRYVIEW(dev))
8309                 chv_crtc_clock_get(crtc, pipe_config);
8310         else if (IS_VALLEYVIEW(dev))
8311                 vlv_crtc_clock_get(crtc, pipe_config);
8312         else
8313                 i9xx_crtc_clock_get(crtc, pipe_config);
8314
8315         /*
8316          * Normally the dotclock is filled in by the encoder .get_config()
8317          * but in case the pipe is enabled w/o any ports we need a sane
8318          * default.
8319          */
8320         pipe_config->base.adjusted_mode.crtc_clock =
8321                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8322
8323         ret = true;
8324
8325 out:
8326         intel_display_power_put(dev_priv, power_domain);
8327
8328         return ret;
8329 }
8330
8331 static void ironlake_init_pch_refclk(struct drm_device *dev)
8332 {
8333         struct drm_i915_private *dev_priv = to_i915(dev);
8334         struct intel_encoder *encoder;
8335         int i;
8336         u32 val, final;
8337         bool has_lvds = false;
8338         bool has_cpu_edp = false;
8339         bool has_panel = false;
8340         bool has_ck505 = false;
8341         bool can_ssc = false;
8342         bool using_ssc_source = false;
8343
8344         /* We need to take the global config into account */
8345         for_each_intel_encoder(dev, encoder) {
8346                 switch (encoder->type) {
8347                 case INTEL_OUTPUT_LVDS:
8348                         has_panel = true;
8349                         has_lvds = true;
8350                         break;
8351                 case INTEL_OUTPUT_EDP:
8352                         has_panel = true;
8353                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8354                                 has_cpu_edp = true;
8355                         break;
8356                 default:
8357                         break;
8358                 }
8359         }
8360
8361         if (HAS_PCH_IBX(dev)) {
8362                 has_ck505 = dev_priv->vbt.display_clock_mode;
8363                 can_ssc = has_ck505;
8364         } else {
8365                 has_ck505 = false;
8366                 can_ssc = true;
8367         }
8368
8369         /* Check if any DPLLs are using the SSC source */
8370         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8371                 u32 temp = I915_READ(PCH_DPLL(i));
8372
8373                 if (!(temp & DPLL_VCO_ENABLE))
8374                         continue;
8375
8376                 if ((temp & PLL_REF_INPUT_MASK) ==
8377                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8378                         using_ssc_source = true;
8379                         break;
8380                 }
8381         }
8382
8383         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8384                       has_panel, has_lvds, has_ck505, using_ssc_source);
8385
8386         /* Ironlake: try to setup display ref clock before DPLL
8387          * enabling. This is only under driver's control after
8388          * PCH B stepping, previous chipset stepping should be
8389          * ignoring this setting.
8390          */
8391         val = I915_READ(PCH_DREF_CONTROL);
8392
8393         /* As we must carefully and slowly disable/enable each source in turn,
8394          * compute the final state we want first and check if we need to
8395          * make any changes at all.
8396          */
8397         final = val;
8398         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8399         if (has_ck505)
8400                 final |= DREF_NONSPREAD_CK505_ENABLE;
8401         else
8402                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8403
8404         final &= ~DREF_SSC_SOURCE_MASK;
8405         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8406         final &= ~DREF_SSC1_ENABLE;
8407
8408         if (has_panel) {
8409                 final |= DREF_SSC_SOURCE_ENABLE;
8410
8411                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8412                         final |= DREF_SSC1_ENABLE;
8413
8414                 if (has_cpu_edp) {
8415                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8416                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8417                         else
8418                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8419                 } else
8420                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8421         } else if (using_ssc_source) {
8422                 final |= DREF_SSC_SOURCE_ENABLE;
8423                 final |= DREF_SSC1_ENABLE;
8424         }
8425
8426         if (final == val)
8427                 return;
8428
8429         /* Always enable nonspread source */
8430         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8431
8432         if (has_ck505)
8433                 val |= DREF_NONSPREAD_CK505_ENABLE;
8434         else
8435                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8436
8437         if (has_panel) {
8438                 val &= ~DREF_SSC_SOURCE_MASK;
8439                 val |= DREF_SSC_SOURCE_ENABLE;
8440
8441                 /* SSC must be turned on before enabling the CPU output  */
8442                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8443                         DRM_DEBUG_KMS("Using SSC on panel\n");
8444                         val |= DREF_SSC1_ENABLE;
8445                 } else
8446                         val &= ~DREF_SSC1_ENABLE;
8447
8448                 /* Get SSC going before enabling the outputs */
8449                 I915_WRITE(PCH_DREF_CONTROL, val);
8450                 POSTING_READ(PCH_DREF_CONTROL);
8451                 udelay(200);
8452
8453                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8454
8455                 /* Enable CPU source on CPU attached eDP */
8456                 if (has_cpu_edp) {
8457                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8458                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8459                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8460                         } else
8461                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8462                 } else
8463                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8464
8465                 I915_WRITE(PCH_DREF_CONTROL, val);
8466                 POSTING_READ(PCH_DREF_CONTROL);
8467                 udelay(200);
8468         } else {
8469                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8470
8471                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8472
8473                 /* Turn off CPU output */
8474                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8475
8476                 I915_WRITE(PCH_DREF_CONTROL, val);
8477                 POSTING_READ(PCH_DREF_CONTROL);
8478                 udelay(200);
8479
8480                 if (!using_ssc_source) {
8481                         DRM_DEBUG_KMS("Disabling SSC source\n");
8482
8483                         /* Turn off the SSC source */
8484                         val &= ~DREF_SSC_SOURCE_MASK;
8485                         val |= DREF_SSC_SOURCE_DISABLE;
8486
8487                         /* Turn off SSC1 */
8488                         val &= ~DREF_SSC1_ENABLE;
8489
8490                         I915_WRITE(PCH_DREF_CONTROL, val);
8491                         POSTING_READ(PCH_DREF_CONTROL);
8492                         udelay(200);
8493                 }
8494         }
8495
8496         BUG_ON(val != final);
8497 }
8498
8499 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8500 {
8501         uint32_t tmp;
8502
8503         tmp = I915_READ(SOUTH_CHICKEN2);
8504         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8505         I915_WRITE(SOUTH_CHICKEN2, tmp);
8506
8507         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8508                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8509                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8510
8511         tmp = I915_READ(SOUTH_CHICKEN2);
8512         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8513         I915_WRITE(SOUTH_CHICKEN2, tmp);
8514
8515         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8516                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8517                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8518 }
8519
8520 /* WaMPhyProgramming:hsw */
8521 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8522 {
8523         uint32_t tmp;
8524
8525         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8526         tmp &= ~(0xFF << 24);
8527         tmp |= (0x12 << 24);
8528         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8529
8530         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8531         tmp |= (1 << 11);
8532         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8533
8534         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8535         tmp |= (1 << 11);
8536         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8537
8538         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8539         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8540         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8541
8542         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8543         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8544         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8545
8546         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8547         tmp &= ~(7 << 13);
8548         tmp |= (5 << 13);
8549         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8550
8551         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8552         tmp &= ~(7 << 13);
8553         tmp |= (5 << 13);
8554         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8555
8556         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8557         tmp &= ~0xFF;
8558         tmp |= 0x1C;
8559         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8560
8561         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8562         tmp &= ~0xFF;
8563         tmp |= 0x1C;
8564         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8565
8566         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8567         tmp &= ~(0xFF << 16);
8568         tmp |= (0x1C << 16);
8569         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8570
8571         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8572         tmp &= ~(0xFF << 16);
8573         tmp |= (0x1C << 16);
8574         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8575
8576         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8577         tmp |= (1 << 27);
8578         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8579
8580         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8581         tmp |= (1 << 27);
8582         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8583
8584         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8585         tmp &= ~(0xF << 28);
8586         tmp |= (4 << 28);
8587         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8588
8589         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8590         tmp &= ~(0xF << 28);
8591         tmp |= (4 << 28);
8592         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8593 }
8594
8595 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8596  * Programming" based on the parameters passed:
8597  * - Sequence to enable CLKOUT_DP
8598  * - Sequence to enable CLKOUT_DP without spread
8599  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8600  */
8601 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8602                                  bool with_fdi)
8603 {
8604         struct drm_i915_private *dev_priv = to_i915(dev);
8605         uint32_t reg, tmp;
8606
8607         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8608                 with_spread = true;
8609         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8610                 with_fdi = false;
8611
8612         mutex_lock(&dev_priv->sb_lock);
8613
8614         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8615         tmp &= ~SBI_SSCCTL_DISABLE;
8616         tmp |= SBI_SSCCTL_PATHALT;
8617         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8618
8619         udelay(24);
8620
8621         if (with_spread) {
8622                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8623                 tmp &= ~SBI_SSCCTL_PATHALT;
8624                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8625
8626                 if (with_fdi) {
8627                         lpt_reset_fdi_mphy(dev_priv);
8628                         lpt_program_fdi_mphy(dev_priv);
8629                 }
8630         }
8631
8632         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8633         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8634         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8635         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8636
8637         mutex_unlock(&dev_priv->sb_lock);
8638 }
8639
8640 /* Sequence to disable CLKOUT_DP */
8641 static void lpt_disable_clkout_dp(struct drm_device *dev)
8642 {
8643         struct drm_i915_private *dev_priv = to_i915(dev);
8644         uint32_t reg, tmp;
8645
8646         mutex_lock(&dev_priv->sb_lock);
8647
8648         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8649         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8650         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8651         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8652
8653         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8654         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8655                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8656                         tmp |= SBI_SSCCTL_PATHALT;
8657                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8658                         udelay(32);
8659                 }
8660                 tmp |= SBI_SSCCTL_DISABLE;
8661                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8662         }
8663
8664         mutex_unlock(&dev_priv->sb_lock);
8665 }
8666
8667 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8668
8669 static const uint16_t sscdivintphase[] = {
8670         [BEND_IDX( 50)] = 0x3B23,
8671         [BEND_IDX( 45)] = 0x3B23,
8672         [BEND_IDX( 40)] = 0x3C23,
8673         [BEND_IDX( 35)] = 0x3C23,
8674         [BEND_IDX( 30)] = 0x3D23,
8675         [BEND_IDX( 25)] = 0x3D23,
8676         [BEND_IDX( 20)] = 0x3E23,
8677         [BEND_IDX( 15)] = 0x3E23,
8678         [BEND_IDX( 10)] = 0x3F23,
8679         [BEND_IDX(  5)] = 0x3F23,
8680         [BEND_IDX(  0)] = 0x0025,
8681         [BEND_IDX( -5)] = 0x0025,
8682         [BEND_IDX(-10)] = 0x0125,
8683         [BEND_IDX(-15)] = 0x0125,
8684         [BEND_IDX(-20)] = 0x0225,
8685         [BEND_IDX(-25)] = 0x0225,
8686         [BEND_IDX(-30)] = 0x0325,
8687         [BEND_IDX(-35)] = 0x0325,
8688         [BEND_IDX(-40)] = 0x0425,
8689         [BEND_IDX(-45)] = 0x0425,
8690         [BEND_IDX(-50)] = 0x0525,
8691 };
8692
8693 /*
8694  * Bend CLKOUT_DP
8695  * steps -50 to 50 inclusive, in steps of 5
8696  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8697  * change in clock period = -(steps / 10) * 5.787 ps
8698  */
8699 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8700 {
8701         uint32_t tmp;
8702         int idx = BEND_IDX(steps);
8703
8704         if (WARN_ON(steps % 5 != 0))
8705                 return;
8706
8707         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8708                 return;
8709
8710         mutex_lock(&dev_priv->sb_lock);
8711
8712         if (steps % 10 != 0)
8713                 tmp = 0xAAAAAAAB;
8714         else
8715                 tmp = 0x00000000;
8716         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8717
8718         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8719         tmp &= 0xffff0000;
8720         tmp |= sscdivintphase[idx];
8721         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8722
8723         mutex_unlock(&dev_priv->sb_lock);
8724 }
8725
8726 #undef BEND_IDX
8727
8728 static void lpt_init_pch_refclk(struct drm_device *dev)
8729 {
8730         struct intel_encoder *encoder;
8731         bool has_vga = false;
8732
8733         for_each_intel_encoder(dev, encoder) {
8734                 switch (encoder->type) {
8735                 case INTEL_OUTPUT_ANALOG:
8736                         has_vga = true;
8737                         break;
8738                 default:
8739                         break;
8740                 }
8741         }
8742
8743         if (has_vga) {
8744                 lpt_bend_clkout_dp(to_i915(dev), 0);
8745                 lpt_enable_clkout_dp(dev, true, true);
8746         } else {
8747                 lpt_disable_clkout_dp(dev);
8748         }
8749 }
8750
8751 /*
8752  * Initialize reference clocks when the driver loads
8753  */
8754 void intel_init_pch_refclk(struct drm_device *dev)
8755 {
8756         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8757                 ironlake_init_pch_refclk(dev);
8758         else if (HAS_PCH_LPT(dev))
8759                 lpt_init_pch_refclk(dev);
8760 }
8761
8762 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8763 {
8764         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8766         int pipe = intel_crtc->pipe;
8767         uint32_t val;
8768
8769         val = 0;
8770
8771         switch (intel_crtc->config->pipe_bpp) {
8772         case 18:
8773                 val |= PIPECONF_6BPC;
8774                 break;
8775         case 24:
8776                 val |= PIPECONF_8BPC;
8777                 break;
8778         case 30:
8779                 val |= PIPECONF_10BPC;
8780                 break;
8781         case 36:
8782                 val |= PIPECONF_12BPC;
8783                 break;
8784         default:
8785                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8786                 BUG();
8787         }
8788
8789         if (intel_crtc->config->dither)
8790                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8791
8792         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8793                 val |= PIPECONF_INTERLACED_ILK;
8794         else
8795                 val |= PIPECONF_PROGRESSIVE;
8796
8797         if (intel_crtc->config->limited_color_range)
8798                 val |= PIPECONF_COLOR_RANGE_SELECT;
8799
8800         I915_WRITE(PIPECONF(pipe), val);
8801         POSTING_READ(PIPECONF(pipe));
8802 }
8803
8804 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8805 {
8806         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8808         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8809         u32 val = 0;
8810
8811         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8812                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8813
8814         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8815                 val |= PIPECONF_INTERLACED_ILK;
8816         else
8817                 val |= PIPECONF_PROGRESSIVE;
8818
8819         I915_WRITE(PIPECONF(cpu_transcoder), val);
8820         POSTING_READ(PIPECONF(cpu_transcoder));
8821 }
8822
8823 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8824 {
8825         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8827
8828         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8829                 u32 val = 0;
8830
8831                 switch (intel_crtc->config->pipe_bpp) {
8832                 case 18:
8833                         val |= PIPEMISC_DITHER_6_BPC;
8834                         break;
8835                 case 24:
8836                         val |= PIPEMISC_DITHER_8_BPC;
8837                         break;
8838                 case 30:
8839                         val |= PIPEMISC_DITHER_10_BPC;
8840                         break;
8841                 case 36:
8842                         val |= PIPEMISC_DITHER_12_BPC;
8843                         break;
8844                 default:
8845                         /* Case prevented by pipe_config_set_bpp. */
8846                         BUG();
8847                 }
8848
8849                 if (intel_crtc->config->dither)
8850                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8851
8852                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8853         }
8854 }
8855
8856 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8857 {
8858         /*
8859          * Account for spread spectrum to avoid
8860          * oversubscribing the link. Max center spread
8861          * is 2.5%; use 5% for safety's sake.
8862          */
8863         u32 bps = target_clock * bpp * 21 / 20;
8864         return DIV_ROUND_UP(bps, link_bw * 8);
8865 }
8866
8867 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8868 {
8869         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8870 }
8871
8872 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8873                                   struct intel_crtc_state *crtc_state,
8874                                   struct dpll *reduced_clock)
8875 {
8876         struct drm_crtc *crtc = &intel_crtc->base;
8877         struct drm_device *dev = crtc->dev;
8878         struct drm_i915_private *dev_priv = to_i915(dev);
8879         u32 dpll, fp, fp2;
8880         int factor;
8881
8882         /* Enable autotuning of the PLL clock (if permissible) */
8883         factor = 21;
8884         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8885                 if ((intel_panel_use_ssc(dev_priv) &&
8886                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8887                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8888                         factor = 25;
8889         } else if (crtc_state->sdvo_tv_clock)
8890                 factor = 20;
8891
8892         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8893
8894         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8895                 fp |= FP_CB_TUNE;
8896
8897         if (reduced_clock) {
8898                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8899
8900                 if (reduced_clock->m < factor * reduced_clock->n)
8901                         fp2 |= FP_CB_TUNE;
8902         } else {
8903                 fp2 = fp;
8904         }
8905
8906         dpll = 0;
8907
8908         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8909                 dpll |= DPLLB_MODE_LVDS;
8910         else
8911                 dpll |= DPLLB_MODE_DAC_SERIAL;
8912
8913         dpll |= (crtc_state->pixel_multiplier - 1)
8914                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8915
8916         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8917             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8918                 dpll |= DPLL_SDVO_HIGH_SPEED;
8919
8920         if (intel_crtc_has_dp_encoder(crtc_state))
8921                 dpll |= DPLL_SDVO_HIGH_SPEED;
8922
8923         /* compute bitmask from p1 value */
8924         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8925         /* also FPA1 */
8926         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8927
8928         switch (crtc_state->dpll.p2) {
8929         case 5:
8930                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8931                 break;
8932         case 7:
8933                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8934                 break;
8935         case 10:
8936                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8937                 break;
8938         case 14:
8939                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8940                 break;
8941         }
8942
8943         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8944             intel_panel_use_ssc(dev_priv))
8945                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8946         else
8947                 dpll |= PLL_REF_INPUT_DREFCLK;
8948
8949         dpll |= DPLL_VCO_ENABLE;
8950
8951         crtc_state->dpll_hw_state.dpll = dpll;
8952         crtc_state->dpll_hw_state.fp0 = fp;
8953         crtc_state->dpll_hw_state.fp1 = fp2;
8954 }
8955
8956 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8957                                        struct intel_crtc_state *crtc_state)
8958 {
8959         struct drm_device *dev = crtc->base.dev;
8960         struct drm_i915_private *dev_priv = to_i915(dev);
8961         struct dpll reduced_clock;
8962         bool has_reduced_clock = false;
8963         struct intel_shared_dpll *pll;
8964         const struct intel_limit *limit;
8965         int refclk = 120000;
8966
8967         memset(&crtc_state->dpll_hw_state, 0,
8968                sizeof(crtc_state->dpll_hw_state));
8969
8970         crtc->lowfreq_avail = false;
8971
8972         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8973         if (!crtc_state->has_pch_encoder)
8974                 return 0;
8975
8976         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8977                 if (intel_panel_use_ssc(dev_priv)) {
8978                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8979                                       dev_priv->vbt.lvds_ssc_freq);
8980                         refclk = dev_priv->vbt.lvds_ssc_freq;
8981                 }
8982
8983                 if (intel_is_dual_link_lvds(dev)) {
8984                         if (refclk == 100000)
8985                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8986                         else
8987                                 limit = &intel_limits_ironlake_dual_lvds;
8988                 } else {
8989                         if (refclk == 100000)
8990                                 limit = &intel_limits_ironlake_single_lvds_100m;
8991                         else
8992                                 limit = &intel_limits_ironlake_single_lvds;
8993                 }
8994         } else {
8995                 limit = &intel_limits_ironlake_dac;
8996         }
8997
8998         if (!crtc_state->clock_set &&
8999             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9000                                 refclk, NULL, &crtc_state->dpll)) {
9001                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9002                 return -EINVAL;
9003         }
9004
9005         ironlake_compute_dpll(crtc, crtc_state,
9006                               has_reduced_clock ? &reduced_clock : NULL);
9007
9008         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9009         if (pll == NULL) {
9010                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9011                                  pipe_name(crtc->pipe));
9012                 return -EINVAL;
9013         }
9014
9015         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9016             has_reduced_clock)
9017                 crtc->lowfreq_avail = true;
9018
9019         return 0;
9020 }
9021
9022 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9023                                          struct intel_link_m_n *m_n)
9024 {
9025         struct drm_device *dev = crtc->base.dev;
9026         struct drm_i915_private *dev_priv = to_i915(dev);
9027         enum pipe pipe = crtc->pipe;
9028
9029         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9030         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9031         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9032                 & ~TU_SIZE_MASK;
9033         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9034         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9035                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9036 }
9037
9038 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9039                                          enum transcoder transcoder,
9040                                          struct intel_link_m_n *m_n,
9041                                          struct intel_link_m_n *m2_n2)
9042 {
9043         struct drm_device *dev = crtc->base.dev;
9044         struct drm_i915_private *dev_priv = to_i915(dev);
9045         enum pipe pipe = crtc->pipe;
9046
9047         if (INTEL_INFO(dev)->gen >= 5) {
9048                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9049                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9050                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9051                         & ~TU_SIZE_MASK;
9052                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9053                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9054                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9055                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9056                  * gen < 8) and if DRRS is supported (to make sure the
9057                  * registers are not unnecessarily read).
9058                  */
9059                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9060                         crtc->config->has_drrs) {
9061                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9062                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9063                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9064                                         & ~TU_SIZE_MASK;
9065                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9066                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9067                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9068                 }
9069         } else {
9070                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9071                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9072                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9073                         & ~TU_SIZE_MASK;
9074                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9075                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9076                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9077         }
9078 }
9079
9080 void intel_dp_get_m_n(struct intel_crtc *crtc,
9081                       struct intel_crtc_state *pipe_config)
9082 {
9083         if (pipe_config->has_pch_encoder)
9084                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9085         else
9086                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9087                                              &pipe_config->dp_m_n,
9088                                              &pipe_config->dp_m2_n2);
9089 }
9090
9091 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9092                                         struct intel_crtc_state *pipe_config)
9093 {
9094         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9095                                      &pipe_config->fdi_m_n, NULL);
9096 }
9097
9098 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9099                                     struct intel_crtc_state *pipe_config)
9100 {
9101         struct drm_device *dev = crtc->base.dev;
9102         struct drm_i915_private *dev_priv = to_i915(dev);
9103         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9104         uint32_t ps_ctrl = 0;
9105         int id = -1;
9106         int i;
9107
9108         /* find scaler attached to this pipe */
9109         for (i = 0; i < crtc->num_scalers; i++) {
9110                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9111                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9112                         id = i;
9113                         pipe_config->pch_pfit.enabled = true;
9114                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9115                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9116                         break;
9117                 }
9118         }
9119
9120         scaler_state->scaler_id = id;
9121         if (id >= 0) {
9122                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9123         } else {
9124                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9125         }
9126 }
9127
9128 static void
9129 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9130                                  struct intel_initial_plane_config *plane_config)
9131 {
9132         struct drm_device *dev = crtc->base.dev;
9133         struct drm_i915_private *dev_priv = to_i915(dev);
9134         u32 val, base, offset, stride_mult, tiling;
9135         int pipe = crtc->pipe;
9136         int fourcc, pixel_format;
9137         unsigned int aligned_height;
9138         struct drm_framebuffer *fb;
9139         struct intel_framebuffer *intel_fb;
9140
9141         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9142         if (!intel_fb) {
9143                 DRM_DEBUG_KMS("failed to alloc fb\n");
9144                 return;
9145         }
9146
9147         fb = &intel_fb->base;
9148
9149         val = I915_READ(PLANE_CTL(pipe, 0));
9150         if (!(val & PLANE_CTL_ENABLE))
9151                 goto error;
9152
9153         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9154         fourcc = skl_format_to_fourcc(pixel_format,
9155                                       val & PLANE_CTL_ORDER_RGBX,
9156                                       val & PLANE_CTL_ALPHA_MASK);
9157         fb->pixel_format = fourcc;
9158         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9159
9160         tiling = val & PLANE_CTL_TILED_MASK;
9161         switch (tiling) {
9162         case PLANE_CTL_TILED_LINEAR:
9163                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9164                 break;
9165         case PLANE_CTL_TILED_X:
9166                 plane_config->tiling = I915_TILING_X;
9167                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9168                 break;
9169         case PLANE_CTL_TILED_Y:
9170                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9171                 break;
9172         case PLANE_CTL_TILED_YF:
9173                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9174                 break;
9175         default:
9176                 MISSING_CASE(tiling);
9177                 goto error;
9178         }
9179
9180         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9181         plane_config->base = base;
9182
9183         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9184
9185         val = I915_READ(PLANE_SIZE(pipe, 0));
9186         fb->height = ((val >> 16) & 0xfff) + 1;
9187         fb->width = ((val >> 0) & 0x1fff) + 1;
9188
9189         val = I915_READ(PLANE_STRIDE(pipe, 0));
9190         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9191                                                 fb->pixel_format);
9192         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9193
9194         aligned_height = intel_fb_align_height(dev, fb->height,
9195                                                fb->pixel_format,
9196                                                fb->modifier[0]);
9197
9198         plane_config->size = fb->pitches[0] * aligned_height;
9199
9200         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9201                       pipe_name(pipe), fb->width, fb->height,
9202                       fb->bits_per_pixel, base, fb->pitches[0],
9203                       plane_config->size);
9204
9205         plane_config->fb = intel_fb;
9206         return;
9207
9208 error:
9209         kfree(fb);
9210 }
9211
9212 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9213                                      struct intel_crtc_state *pipe_config)
9214 {
9215         struct drm_device *dev = crtc->base.dev;
9216         struct drm_i915_private *dev_priv = to_i915(dev);
9217         uint32_t tmp;
9218
9219         tmp = I915_READ(PF_CTL(crtc->pipe));
9220
9221         if (tmp & PF_ENABLE) {
9222                 pipe_config->pch_pfit.enabled = true;
9223                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9224                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9225
9226                 /* We currently do not free assignements of panel fitters on
9227                  * ivb/hsw (since we don't use the higher upscaling modes which
9228                  * differentiates them) so just WARN about this case for now. */
9229                 if (IS_GEN7(dev)) {
9230                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9231                                 PF_PIPE_SEL_IVB(crtc->pipe));
9232                 }
9233         }
9234 }
9235
9236 static void
9237 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9238                                   struct intel_initial_plane_config *plane_config)
9239 {
9240         struct drm_device *dev = crtc->base.dev;
9241         struct drm_i915_private *dev_priv = to_i915(dev);
9242         u32 val, base, offset;
9243         int pipe = crtc->pipe;
9244         int fourcc, pixel_format;
9245         unsigned int aligned_height;
9246         struct drm_framebuffer *fb;
9247         struct intel_framebuffer *intel_fb;
9248
9249         val = I915_READ(DSPCNTR(pipe));
9250         if (!(val & DISPLAY_PLANE_ENABLE))
9251                 return;
9252
9253         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9254         if (!intel_fb) {
9255                 DRM_DEBUG_KMS("failed to alloc fb\n");
9256                 return;
9257         }
9258
9259         fb = &intel_fb->base;
9260
9261         if (INTEL_INFO(dev)->gen >= 4) {
9262                 if (val & DISPPLANE_TILED) {
9263                         plane_config->tiling = I915_TILING_X;
9264                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9265                 }
9266         }
9267
9268         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9269         fourcc = i9xx_format_to_fourcc(pixel_format);
9270         fb->pixel_format = fourcc;
9271         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9272
9273         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9274         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9275                 offset = I915_READ(DSPOFFSET(pipe));
9276         } else {
9277                 if (plane_config->tiling)
9278                         offset = I915_READ(DSPTILEOFF(pipe));
9279                 else
9280                         offset = I915_READ(DSPLINOFF(pipe));
9281         }
9282         plane_config->base = base;
9283
9284         val = I915_READ(PIPESRC(pipe));
9285         fb->width = ((val >> 16) & 0xfff) + 1;
9286         fb->height = ((val >> 0) & 0xfff) + 1;
9287
9288         val = I915_READ(DSPSTRIDE(pipe));
9289         fb->pitches[0] = val & 0xffffffc0;
9290
9291         aligned_height = intel_fb_align_height(dev, fb->height,
9292                                                fb->pixel_format,
9293                                                fb->modifier[0]);
9294
9295         plane_config->size = fb->pitches[0] * aligned_height;
9296
9297         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9298                       pipe_name(pipe), fb->width, fb->height,
9299                       fb->bits_per_pixel, base, fb->pitches[0],
9300                       plane_config->size);
9301
9302         plane_config->fb = intel_fb;
9303 }
9304
9305 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9306                                      struct intel_crtc_state *pipe_config)
9307 {
9308         struct drm_device *dev = crtc->base.dev;
9309         struct drm_i915_private *dev_priv = to_i915(dev);
9310         enum intel_display_power_domain power_domain;
9311         uint32_t tmp;
9312         bool ret;
9313
9314         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9315         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9316                 return false;
9317
9318         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9319         pipe_config->shared_dpll = NULL;
9320
9321         ret = false;
9322         tmp = I915_READ(PIPECONF(crtc->pipe));
9323         if (!(tmp & PIPECONF_ENABLE))
9324                 goto out;
9325
9326         switch (tmp & PIPECONF_BPC_MASK) {
9327         case PIPECONF_6BPC:
9328                 pipe_config->pipe_bpp = 18;
9329                 break;
9330         case PIPECONF_8BPC:
9331                 pipe_config->pipe_bpp = 24;
9332                 break;
9333         case PIPECONF_10BPC:
9334                 pipe_config->pipe_bpp = 30;
9335                 break;
9336         case PIPECONF_12BPC:
9337                 pipe_config->pipe_bpp = 36;
9338                 break;
9339         default:
9340                 break;
9341         }
9342
9343         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9344                 pipe_config->limited_color_range = true;
9345
9346         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9347                 struct intel_shared_dpll *pll;
9348                 enum intel_dpll_id pll_id;
9349
9350                 pipe_config->has_pch_encoder = true;
9351
9352                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9353                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9354                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9355
9356                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9357
9358                 if (HAS_PCH_IBX(dev_priv)) {
9359                         /*
9360                          * The pipe->pch transcoder and pch transcoder->pll
9361                          * mapping is fixed.
9362                          */
9363                         pll_id = (enum intel_dpll_id) crtc->pipe;
9364                 } else {
9365                         tmp = I915_READ(PCH_DPLL_SEL);
9366                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9367                                 pll_id = DPLL_ID_PCH_PLL_B;
9368                         else
9369                                 pll_id= DPLL_ID_PCH_PLL_A;
9370                 }
9371
9372                 pipe_config->shared_dpll =
9373                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9374                 pll = pipe_config->shared_dpll;
9375
9376                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9377                                                  &pipe_config->dpll_hw_state));
9378
9379                 tmp = pipe_config->dpll_hw_state.dpll;
9380                 pipe_config->pixel_multiplier =
9381                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9382                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9383
9384                 ironlake_pch_clock_get(crtc, pipe_config);
9385         } else {
9386                 pipe_config->pixel_multiplier = 1;
9387         }
9388
9389         intel_get_pipe_timings(crtc, pipe_config);
9390         intel_get_pipe_src_size(crtc, pipe_config);
9391
9392         ironlake_get_pfit_config(crtc, pipe_config);
9393
9394         ret = true;
9395
9396 out:
9397         intel_display_power_put(dev_priv, power_domain);
9398
9399         return ret;
9400 }
9401
9402 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9403 {
9404         struct drm_device *dev = &dev_priv->drm;
9405         struct intel_crtc *crtc;
9406
9407         for_each_intel_crtc(dev, crtc)
9408                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9409                      pipe_name(crtc->pipe));
9410
9411         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9412         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9413         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9414         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9415         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9416         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9417              "CPU PWM1 enabled\n");
9418         if (IS_HASWELL(dev))
9419                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9420                      "CPU PWM2 enabled\n");
9421         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9422              "PCH PWM1 enabled\n");
9423         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9424              "Utility pin enabled\n");
9425         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9426
9427         /*
9428          * In theory we can still leave IRQs enabled, as long as only the HPD
9429          * interrupts remain enabled. We used to check for that, but since it's
9430          * gen-specific and since we only disable LCPLL after we fully disable
9431          * the interrupts, the check below should be enough.
9432          */
9433         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9434 }
9435
9436 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9437 {
9438         struct drm_device *dev = &dev_priv->drm;
9439
9440         if (IS_HASWELL(dev))
9441                 return I915_READ(D_COMP_HSW);
9442         else
9443                 return I915_READ(D_COMP_BDW);
9444 }
9445
9446 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9447 {
9448         struct drm_device *dev = &dev_priv->drm;
9449
9450         if (IS_HASWELL(dev)) {
9451                 mutex_lock(&dev_priv->rps.hw_lock);
9452                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9453                                             val))
9454                         DRM_ERROR("Failed to write to D_COMP\n");
9455                 mutex_unlock(&dev_priv->rps.hw_lock);
9456         } else {
9457                 I915_WRITE(D_COMP_BDW, val);
9458                 POSTING_READ(D_COMP_BDW);
9459         }
9460 }
9461
9462 /*
9463  * This function implements pieces of two sequences from BSpec:
9464  * - Sequence for display software to disable LCPLL
9465  * - Sequence for display software to allow package C8+
9466  * The steps implemented here are just the steps that actually touch the LCPLL
9467  * register. Callers should take care of disabling all the display engine
9468  * functions, doing the mode unset, fixing interrupts, etc.
9469  */
9470 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9471                               bool switch_to_fclk, bool allow_power_down)
9472 {
9473         uint32_t val;
9474
9475         assert_can_disable_lcpll(dev_priv);
9476
9477         val = I915_READ(LCPLL_CTL);
9478
9479         if (switch_to_fclk) {
9480                 val |= LCPLL_CD_SOURCE_FCLK;
9481                 I915_WRITE(LCPLL_CTL, val);
9482
9483                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9484                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9485                         DRM_ERROR("Switching to FCLK failed\n");
9486
9487                 val = I915_READ(LCPLL_CTL);
9488         }
9489
9490         val |= LCPLL_PLL_DISABLE;
9491         I915_WRITE(LCPLL_CTL, val);
9492         POSTING_READ(LCPLL_CTL);
9493
9494         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9495                 DRM_ERROR("LCPLL still locked\n");
9496
9497         val = hsw_read_dcomp(dev_priv);
9498         val |= D_COMP_COMP_DISABLE;
9499         hsw_write_dcomp(dev_priv, val);
9500         ndelay(100);
9501
9502         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9503                      1))
9504                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9505
9506         if (allow_power_down) {
9507                 val = I915_READ(LCPLL_CTL);
9508                 val |= LCPLL_POWER_DOWN_ALLOW;
9509                 I915_WRITE(LCPLL_CTL, val);
9510                 POSTING_READ(LCPLL_CTL);
9511         }
9512 }
9513
9514 /*
9515  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9516  * source.
9517  */
9518 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9519 {
9520         uint32_t val;
9521
9522         val = I915_READ(LCPLL_CTL);
9523
9524         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9525                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9526                 return;
9527
9528         /*
9529          * Make sure we're not on PC8 state before disabling PC8, otherwise
9530          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9531          */
9532         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9533
9534         if (val & LCPLL_POWER_DOWN_ALLOW) {
9535                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9536                 I915_WRITE(LCPLL_CTL, val);
9537                 POSTING_READ(LCPLL_CTL);
9538         }
9539
9540         val = hsw_read_dcomp(dev_priv);
9541         val |= D_COMP_COMP_FORCE;
9542         val &= ~D_COMP_COMP_DISABLE;
9543         hsw_write_dcomp(dev_priv, val);
9544
9545         val = I915_READ(LCPLL_CTL);
9546         val &= ~LCPLL_PLL_DISABLE;
9547         I915_WRITE(LCPLL_CTL, val);
9548
9549         if (intel_wait_for_register(dev_priv,
9550                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9551                                     5))
9552                 DRM_ERROR("LCPLL not locked yet\n");
9553
9554         if (val & LCPLL_CD_SOURCE_FCLK) {
9555                 val = I915_READ(LCPLL_CTL);
9556                 val &= ~LCPLL_CD_SOURCE_FCLK;
9557                 I915_WRITE(LCPLL_CTL, val);
9558
9559                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9560                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9561                         DRM_ERROR("Switching back to LCPLL failed\n");
9562         }
9563
9564         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9565         intel_update_cdclk(&dev_priv->drm);
9566 }
9567
9568 /*
9569  * Package states C8 and deeper are really deep PC states that can only be
9570  * reached when all the devices on the system allow it, so even if the graphics
9571  * device allows PC8+, it doesn't mean the system will actually get to these
9572  * states. Our driver only allows PC8+ when going into runtime PM.
9573  *
9574  * The requirements for PC8+ are that all the outputs are disabled, the power
9575  * well is disabled and most interrupts are disabled, and these are also
9576  * requirements for runtime PM. When these conditions are met, we manually do
9577  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9578  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9579  * hang the machine.
9580  *
9581  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9582  * the state of some registers, so when we come back from PC8+ we need to
9583  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9584  * need to take care of the registers kept by RC6. Notice that this happens even
9585  * if we don't put the device in PCI D3 state (which is what currently happens
9586  * because of the runtime PM support).
9587  *
9588  * For more, read "Display Sequences for Package C8" on the hardware
9589  * documentation.
9590  */
9591 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9592 {
9593         struct drm_device *dev = &dev_priv->drm;
9594         uint32_t val;
9595
9596         DRM_DEBUG_KMS("Enabling package C8+\n");
9597
9598         if (HAS_PCH_LPT_LP(dev)) {
9599                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9600                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9601                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9602         }
9603
9604         lpt_disable_clkout_dp(dev);
9605         hsw_disable_lcpll(dev_priv, true, true);
9606 }
9607
9608 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9609 {
9610         struct drm_device *dev = &dev_priv->drm;
9611         uint32_t val;
9612
9613         DRM_DEBUG_KMS("Disabling package C8+\n");
9614
9615         hsw_restore_lcpll(dev_priv);
9616         lpt_init_pch_refclk(dev);
9617
9618         if (HAS_PCH_LPT_LP(dev)) {
9619                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9620                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9621                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9622         }
9623 }
9624
9625 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9626 {
9627         struct drm_device *dev = old_state->dev;
9628         struct intel_atomic_state *old_intel_state =
9629                 to_intel_atomic_state(old_state);
9630         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9631
9632         bxt_set_cdclk(to_i915(dev), req_cdclk);
9633 }
9634
9635 /* compute the max rate for new configuration */
9636 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9637 {
9638         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9639         struct drm_i915_private *dev_priv = to_i915(state->dev);
9640         struct drm_crtc *crtc;
9641         struct drm_crtc_state *cstate;
9642         struct intel_crtc_state *crtc_state;
9643         unsigned max_pixel_rate = 0, i;
9644         enum pipe pipe;
9645
9646         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9647                sizeof(intel_state->min_pixclk));
9648
9649         for_each_crtc_in_state(state, crtc, cstate, i) {
9650                 int pixel_rate;
9651
9652                 crtc_state = to_intel_crtc_state(cstate);
9653                 if (!crtc_state->base.enable) {
9654                         intel_state->min_pixclk[i] = 0;
9655                         continue;
9656                 }
9657
9658                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9659
9660                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9661                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9662                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9663
9664                 intel_state->min_pixclk[i] = pixel_rate;
9665         }
9666
9667         for_each_pipe(dev_priv, pipe)
9668                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9669
9670         return max_pixel_rate;
9671 }
9672
9673 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9674 {
9675         struct drm_i915_private *dev_priv = to_i915(dev);
9676         uint32_t val, data;
9677         int ret;
9678
9679         if (WARN((I915_READ(LCPLL_CTL) &
9680                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9681                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9682                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9683                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9684                  "trying to change cdclk frequency with cdclk not enabled\n"))
9685                 return;
9686
9687         mutex_lock(&dev_priv->rps.hw_lock);
9688         ret = sandybridge_pcode_write(dev_priv,
9689                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9690         mutex_unlock(&dev_priv->rps.hw_lock);
9691         if (ret) {
9692                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9693                 return;
9694         }
9695
9696         val = I915_READ(LCPLL_CTL);
9697         val |= LCPLL_CD_SOURCE_FCLK;
9698         I915_WRITE(LCPLL_CTL, val);
9699
9700         if (wait_for_us(I915_READ(LCPLL_CTL) &
9701                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9702                 DRM_ERROR("Switching to FCLK failed\n");
9703
9704         val = I915_READ(LCPLL_CTL);
9705         val &= ~LCPLL_CLK_FREQ_MASK;
9706
9707         switch (cdclk) {
9708         case 450000:
9709                 val |= LCPLL_CLK_FREQ_450;
9710                 data = 0;
9711                 break;
9712         case 540000:
9713                 val |= LCPLL_CLK_FREQ_54O_BDW;
9714                 data = 1;
9715                 break;
9716         case 337500:
9717                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9718                 data = 2;
9719                 break;
9720         case 675000:
9721                 val |= LCPLL_CLK_FREQ_675_BDW;
9722                 data = 3;
9723                 break;
9724         default:
9725                 WARN(1, "invalid cdclk frequency\n");
9726                 return;
9727         }
9728
9729         I915_WRITE(LCPLL_CTL, val);
9730
9731         val = I915_READ(LCPLL_CTL);
9732         val &= ~LCPLL_CD_SOURCE_FCLK;
9733         I915_WRITE(LCPLL_CTL, val);
9734
9735         if (wait_for_us((I915_READ(LCPLL_CTL) &
9736                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9737                 DRM_ERROR("Switching back to LCPLL failed\n");
9738
9739         mutex_lock(&dev_priv->rps.hw_lock);
9740         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9741         mutex_unlock(&dev_priv->rps.hw_lock);
9742
9743         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9744
9745         intel_update_cdclk(dev);
9746
9747         WARN(cdclk != dev_priv->cdclk_freq,
9748              "cdclk requested %d kHz but got %d kHz\n",
9749              cdclk, dev_priv->cdclk_freq);
9750 }
9751
9752 static int broadwell_calc_cdclk(int max_pixclk)
9753 {
9754         if (max_pixclk > 540000)
9755                 return 675000;
9756         else if (max_pixclk > 450000)
9757                 return 540000;
9758         else if (max_pixclk > 337500)
9759                 return 450000;
9760         else
9761                 return 337500;
9762 }
9763
9764 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9765 {
9766         struct drm_i915_private *dev_priv = to_i915(state->dev);
9767         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9768         int max_pixclk = ilk_max_pixel_rate(state);
9769         int cdclk;
9770
9771         /*
9772          * FIXME should also account for plane ratio
9773          * once 64bpp pixel formats are supported.
9774          */
9775         cdclk = broadwell_calc_cdclk(max_pixclk);
9776
9777         if (cdclk > dev_priv->max_cdclk_freq) {
9778                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9779                               cdclk, dev_priv->max_cdclk_freq);
9780                 return -EINVAL;
9781         }
9782
9783         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9784         if (!intel_state->active_crtcs)
9785                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9786
9787         return 0;
9788 }
9789
9790 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9791 {
9792         struct drm_device *dev = old_state->dev;
9793         struct intel_atomic_state *old_intel_state =
9794                 to_intel_atomic_state(old_state);
9795         unsigned req_cdclk = old_intel_state->dev_cdclk;
9796
9797         broadwell_set_cdclk(dev, req_cdclk);
9798 }
9799
9800 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9801 {
9802         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9803         struct drm_i915_private *dev_priv = to_i915(state->dev);
9804         const int max_pixclk = ilk_max_pixel_rate(state);
9805         int vco = intel_state->cdclk_pll_vco;
9806         int cdclk;
9807
9808         /*
9809          * FIXME should also account for plane ratio
9810          * once 64bpp pixel formats are supported.
9811          */
9812         cdclk = skl_calc_cdclk(max_pixclk, vco);
9813
9814         /*
9815          * FIXME move the cdclk caclulation to
9816          * compute_config() so we can fail gracegully.
9817          */
9818         if (cdclk > dev_priv->max_cdclk_freq) {
9819                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9820                           cdclk, dev_priv->max_cdclk_freq);
9821                 cdclk = dev_priv->max_cdclk_freq;
9822         }
9823
9824         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9825         if (!intel_state->active_crtcs)
9826                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9827
9828         return 0;
9829 }
9830
9831 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9832 {
9833         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9834         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9835         unsigned int req_cdclk = intel_state->dev_cdclk;
9836         unsigned int req_vco = intel_state->cdclk_pll_vco;
9837
9838         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9839 }
9840
9841 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9842                                       struct intel_crtc_state *crtc_state)
9843 {
9844         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9845                 if (!intel_ddi_pll_select(crtc, crtc_state))
9846                         return -EINVAL;
9847         }
9848
9849         crtc->lowfreq_avail = false;
9850
9851         return 0;
9852 }
9853
9854 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9855                                 enum port port,
9856                                 struct intel_crtc_state *pipe_config)
9857 {
9858         enum intel_dpll_id id;
9859
9860         switch (port) {
9861         case PORT_A:
9862                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9863                 id = DPLL_ID_SKL_DPLL0;
9864                 break;
9865         case PORT_B:
9866                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9867                 id = DPLL_ID_SKL_DPLL1;
9868                 break;
9869         case PORT_C:
9870                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9871                 id = DPLL_ID_SKL_DPLL2;
9872                 break;
9873         default:
9874                 DRM_ERROR("Incorrect port type\n");
9875                 return;
9876         }
9877
9878         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9879 }
9880
9881 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9882                                 enum port port,
9883                                 struct intel_crtc_state *pipe_config)
9884 {
9885         enum intel_dpll_id id;
9886         u32 temp;
9887
9888         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9889         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9890
9891         switch (pipe_config->ddi_pll_sel) {
9892         case SKL_DPLL0:
9893                 id = DPLL_ID_SKL_DPLL0;
9894                 break;
9895         case SKL_DPLL1:
9896                 id = DPLL_ID_SKL_DPLL1;
9897                 break;
9898         case SKL_DPLL2:
9899                 id = DPLL_ID_SKL_DPLL2;
9900                 break;
9901         case SKL_DPLL3:
9902                 id = DPLL_ID_SKL_DPLL3;
9903                 break;
9904         default:
9905                 MISSING_CASE(pipe_config->ddi_pll_sel);
9906                 return;
9907         }
9908
9909         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9910 }
9911
9912 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9913                                 enum port port,
9914                                 struct intel_crtc_state *pipe_config)
9915 {
9916         enum intel_dpll_id id;
9917
9918         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9919
9920         switch (pipe_config->ddi_pll_sel) {
9921         case PORT_CLK_SEL_WRPLL1:
9922                 id = DPLL_ID_WRPLL1;
9923                 break;
9924         case PORT_CLK_SEL_WRPLL2:
9925                 id = DPLL_ID_WRPLL2;
9926                 break;
9927         case PORT_CLK_SEL_SPLL:
9928                 id = DPLL_ID_SPLL;
9929                 break;
9930         case PORT_CLK_SEL_LCPLL_810:
9931                 id = DPLL_ID_LCPLL_810;
9932                 break;
9933         case PORT_CLK_SEL_LCPLL_1350:
9934                 id = DPLL_ID_LCPLL_1350;
9935                 break;
9936         case PORT_CLK_SEL_LCPLL_2700:
9937                 id = DPLL_ID_LCPLL_2700;
9938                 break;
9939         default:
9940                 MISSING_CASE(pipe_config->ddi_pll_sel);
9941                 /* fall through */
9942         case PORT_CLK_SEL_NONE:
9943                 return;
9944         }
9945
9946         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9947 }
9948
9949 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9950                                      struct intel_crtc_state *pipe_config,
9951                                      unsigned long *power_domain_mask)
9952 {
9953         struct drm_device *dev = crtc->base.dev;
9954         struct drm_i915_private *dev_priv = to_i915(dev);
9955         enum intel_display_power_domain power_domain;
9956         u32 tmp;
9957
9958         /*
9959          * The pipe->transcoder mapping is fixed with the exception of the eDP
9960          * transcoder handled below.
9961          */
9962         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9963
9964         /*
9965          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9966          * consistency and less surprising code; it's in always on power).
9967          */
9968         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9969         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9970                 enum pipe trans_edp_pipe;
9971                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9972                 default:
9973                         WARN(1, "unknown pipe linked to edp transcoder\n");
9974                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9975                 case TRANS_DDI_EDP_INPUT_A_ON:
9976                         trans_edp_pipe = PIPE_A;
9977                         break;
9978                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9979                         trans_edp_pipe = PIPE_B;
9980                         break;
9981                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9982                         trans_edp_pipe = PIPE_C;
9983                         break;
9984                 }
9985
9986                 if (trans_edp_pipe == crtc->pipe)
9987                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9988         }
9989
9990         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9991         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9992                 return false;
9993         *power_domain_mask |= BIT(power_domain);
9994
9995         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9996
9997         return tmp & PIPECONF_ENABLE;
9998 }
9999
10000 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10001                                          struct intel_crtc_state *pipe_config,
10002                                          unsigned long *power_domain_mask)
10003 {
10004         struct drm_device *dev = crtc->base.dev;
10005         struct drm_i915_private *dev_priv = to_i915(dev);
10006         enum intel_display_power_domain power_domain;
10007         enum port port;
10008         enum transcoder cpu_transcoder;
10009         u32 tmp;
10010
10011         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10012                 if (port == PORT_A)
10013                         cpu_transcoder = TRANSCODER_DSI_A;
10014                 else
10015                         cpu_transcoder = TRANSCODER_DSI_C;
10016
10017                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10018                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10019                         continue;
10020                 *power_domain_mask |= BIT(power_domain);
10021
10022                 /*
10023                  * The PLL needs to be enabled with a valid divider
10024                  * configuration, otherwise accessing DSI registers will hang
10025                  * the machine. See BSpec North Display Engine
10026                  * registers/MIPI[BXT]. We can break out here early, since we
10027                  * need the same DSI PLL to be enabled for both DSI ports.
10028                  */
10029                 if (!intel_dsi_pll_is_enabled(dev_priv))
10030                         break;
10031
10032                 /* XXX: this works for video mode only */
10033                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10034                 if (!(tmp & DPI_ENABLE))
10035                         continue;
10036
10037                 tmp = I915_READ(MIPI_CTRL(port));
10038                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10039                         continue;
10040
10041                 pipe_config->cpu_transcoder = cpu_transcoder;
10042                 break;
10043         }
10044
10045         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10046 }
10047
10048 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10049                                        struct intel_crtc_state *pipe_config)
10050 {
10051         struct drm_device *dev = crtc->base.dev;
10052         struct drm_i915_private *dev_priv = to_i915(dev);
10053         struct intel_shared_dpll *pll;
10054         enum port port;
10055         uint32_t tmp;
10056
10057         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10058
10059         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10060
10061         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10062                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10063         else if (IS_BROXTON(dev))
10064                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10065         else
10066                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10067
10068         pll = pipe_config->shared_dpll;
10069         if (pll) {
10070                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10071                                                  &pipe_config->dpll_hw_state));
10072         }
10073
10074         /*
10075          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10076          * DDI E. So just check whether this pipe is wired to DDI E and whether
10077          * the PCH transcoder is on.
10078          */
10079         if (INTEL_INFO(dev)->gen < 9 &&
10080             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10081                 pipe_config->has_pch_encoder = true;
10082
10083                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10084                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10085                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10086
10087                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10088         }
10089 }
10090
10091 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10092                                     struct intel_crtc_state *pipe_config)
10093 {
10094         struct drm_device *dev = crtc->base.dev;
10095         struct drm_i915_private *dev_priv = to_i915(dev);
10096         enum intel_display_power_domain power_domain;
10097         unsigned long power_domain_mask;
10098         bool active;
10099
10100         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10101         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10102                 return false;
10103         power_domain_mask = BIT(power_domain);
10104
10105         pipe_config->shared_dpll = NULL;
10106
10107         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10108
10109         if (IS_BROXTON(dev_priv) &&
10110             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10111                 WARN_ON(active);
10112                 active = true;
10113         }
10114
10115         if (!active)
10116                 goto out;
10117
10118         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10119                 haswell_get_ddi_port_state(crtc, pipe_config);
10120                 intel_get_pipe_timings(crtc, pipe_config);
10121         }
10122
10123         intel_get_pipe_src_size(crtc, pipe_config);
10124
10125         pipe_config->gamma_mode =
10126                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10127
10128         if (INTEL_INFO(dev)->gen >= 9) {
10129                 skl_init_scalers(dev, crtc, pipe_config);
10130         }
10131
10132         if (INTEL_INFO(dev)->gen >= 9) {
10133                 pipe_config->scaler_state.scaler_id = -1;
10134                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10135         }
10136
10137         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10138         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10139                 power_domain_mask |= BIT(power_domain);
10140                 if (INTEL_INFO(dev)->gen >= 9)
10141                         skylake_get_pfit_config(crtc, pipe_config);
10142                 else
10143                         ironlake_get_pfit_config(crtc, pipe_config);
10144         }
10145
10146         if (IS_HASWELL(dev))
10147                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10148                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10149
10150         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10151             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10152                 pipe_config->pixel_multiplier =
10153                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10154         } else {
10155                 pipe_config->pixel_multiplier = 1;
10156         }
10157
10158 out:
10159         for_each_power_domain(power_domain, power_domain_mask)
10160                 intel_display_power_put(dev_priv, power_domain);
10161
10162         return active;
10163 }
10164
10165 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10166                                const struct intel_plane_state *plane_state)
10167 {
10168         struct drm_device *dev = crtc->dev;
10169         struct drm_i915_private *dev_priv = to_i915(dev);
10170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10171         uint32_t cntl = 0, size = 0;
10172
10173         if (plane_state && plane_state->visible) {
10174                 unsigned int width = plane_state->base.crtc_w;
10175                 unsigned int height = plane_state->base.crtc_h;
10176                 unsigned int stride = roundup_pow_of_two(width) * 4;
10177
10178                 switch (stride) {
10179                 default:
10180                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10181                                   width, stride);
10182                         stride = 256;
10183                         /* fallthrough */
10184                 case 256:
10185                 case 512:
10186                 case 1024:
10187                 case 2048:
10188                         break;
10189                 }
10190
10191                 cntl |= CURSOR_ENABLE |
10192                         CURSOR_GAMMA_ENABLE |
10193                         CURSOR_FORMAT_ARGB |
10194                         CURSOR_STRIDE(stride);
10195
10196                 size = (height << 12) | width;
10197         }
10198
10199         if (intel_crtc->cursor_cntl != 0 &&
10200             (intel_crtc->cursor_base != base ||
10201              intel_crtc->cursor_size != size ||
10202              intel_crtc->cursor_cntl != cntl)) {
10203                 /* On these chipsets we can only modify the base/size/stride
10204                  * whilst the cursor is disabled.
10205                  */
10206                 I915_WRITE(CURCNTR(PIPE_A), 0);
10207                 POSTING_READ(CURCNTR(PIPE_A));
10208                 intel_crtc->cursor_cntl = 0;
10209         }
10210
10211         if (intel_crtc->cursor_base != base) {
10212                 I915_WRITE(CURBASE(PIPE_A), base);
10213                 intel_crtc->cursor_base = base;
10214         }
10215
10216         if (intel_crtc->cursor_size != size) {
10217                 I915_WRITE(CURSIZE, size);
10218                 intel_crtc->cursor_size = size;
10219         }
10220
10221         if (intel_crtc->cursor_cntl != cntl) {
10222                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10223                 POSTING_READ(CURCNTR(PIPE_A));
10224                 intel_crtc->cursor_cntl = cntl;
10225         }
10226 }
10227
10228 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10229                                const struct intel_plane_state *plane_state)
10230 {
10231         struct drm_device *dev = crtc->dev;
10232         struct drm_i915_private *dev_priv = to_i915(dev);
10233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10234         int pipe = intel_crtc->pipe;
10235         uint32_t cntl = 0;
10236
10237         if (plane_state && plane_state->visible) {
10238                 cntl = MCURSOR_GAMMA_ENABLE;
10239                 switch (plane_state->base.crtc_w) {
10240                         case 64:
10241                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10242                                 break;
10243                         case 128:
10244                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10245                                 break;
10246                         case 256:
10247                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10248                                 break;
10249                         default:
10250                                 MISSING_CASE(plane_state->base.crtc_w);
10251                                 return;
10252                 }
10253                 cntl |= pipe << 28; /* Connect to correct pipe */
10254
10255                 if (HAS_DDI(dev))
10256                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10257
10258                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10259                         cntl |= CURSOR_ROTATE_180;
10260         }
10261
10262         if (intel_crtc->cursor_cntl != cntl) {
10263                 I915_WRITE(CURCNTR(pipe), cntl);
10264                 POSTING_READ(CURCNTR(pipe));
10265                 intel_crtc->cursor_cntl = cntl;
10266         }
10267
10268         /* and commit changes on next vblank */
10269         I915_WRITE(CURBASE(pipe), base);
10270         POSTING_READ(CURBASE(pipe));
10271
10272         intel_crtc->cursor_base = base;
10273 }
10274
10275 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10276 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10277                                      const struct intel_plane_state *plane_state)
10278 {
10279         struct drm_device *dev = crtc->dev;
10280         struct drm_i915_private *dev_priv = to_i915(dev);
10281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10282         int pipe = intel_crtc->pipe;
10283         u32 base = intel_crtc->cursor_addr;
10284         u32 pos = 0;
10285
10286         if (plane_state) {
10287                 int x = plane_state->base.crtc_x;
10288                 int y = plane_state->base.crtc_y;
10289
10290                 if (x < 0) {
10291                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10292                         x = -x;
10293                 }
10294                 pos |= x << CURSOR_X_SHIFT;
10295
10296                 if (y < 0) {
10297                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10298                         y = -y;
10299                 }
10300                 pos |= y << CURSOR_Y_SHIFT;
10301
10302                 /* ILK+ do this automagically */
10303                 if (HAS_GMCH_DISPLAY(dev) &&
10304                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10305                         base += (plane_state->base.crtc_h *
10306                                  plane_state->base.crtc_w - 1) * 4;
10307                 }
10308         }
10309
10310         I915_WRITE(CURPOS(pipe), pos);
10311
10312         if (IS_845G(dev) || IS_I865G(dev))
10313                 i845_update_cursor(crtc, base, plane_state);
10314         else
10315                 i9xx_update_cursor(crtc, base, plane_state);
10316 }
10317
10318 static bool cursor_size_ok(struct drm_device *dev,
10319                            uint32_t width, uint32_t height)
10320 {
10321         if (width == 0 || height == 0)
10322                 return false;
10323
10324         /*
10325          * 845g/865g are special in that they are only limited by
10326          * the width of their cursors, the height is arbitrary up to
10327          * the precision of the register. Everything else requires
10328          * square cursors, limited to a few power-of-two sizes.
10329          */
10330         if (IS_845G(dev) || IS_I865G(dev)) {
10331                 if ((width & 63) != 0)
10332                         return false;
10333
10334                 if (width > (IS_845G(dev) ? 64 : 512))
10335                         return false;
10336
10337                 if (height > 1023)
10338                         return false;
10339         } else {
10340                 switch (width | height) {
10341                 case 256:
10342                 case 128:
10343                         if (IS_GEN2(dev))
10344                                 return false;
10345                 case 64:
10346                         break;
10347                 default:
10348                         return false;
10349                 }
10350         }
10351
10352         return true;
10353 }
10354
10355 /* VESA 640x480x72Hz mode to set on the pipe */
10356 static struct drm_display_mode load_detect_mode = {
10357         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10358                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10359 };
10360
10361 struct drm_framebuffer *
10362 __intel_framebuffer_create(struct drm_device *dev,
10363                            struct drm_mode_fb_cmd2 *mode_cmd,
10364                            struct drm_i915_gem_object *obj)
10365 {
10366         struct intel_framebuffer *intel_fb;
10367         int ret;
10368
10369         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10370         if (!intel_fb)
10371                 return ERR_PTR(-ENOMEM);
10372
10373         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10374         if (ret)
10375                 goto err;
10376
10377         return &intel_fb->base;
10378
10379 err:
10380         kfree(intel_fb);
10381         return ERR_PTR(ret);
10382 }
10383
10384 static struct drm_framebuffer *
10385 intel_framebuffer_create(struct drm_device *dev,
10386                          struct drm_mode_fb_cmd2 *mode_cmd,
10387                          struct drm_i915_gem_object *obj)
10388 {
10389         struct drm_framebuffer *fb;
10390         int ret;
10391
10392         ret = i915_mutex_lock_interruptible(dev);
10393         if (ret)
10394                 return ERR_PTR(ret);
10395         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10396         mutex_unlock(&dev->struct_mutex);
10397
10398         return fb;
10399 }
10400
10401 static u32
10402 intel_framebuffer_pitch_for_width(int width, int bpp)
10403 {
10404         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10405         return ALIGN(pitch, 64);
10406 }
10407
10408 static u32
10409 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10410 {
10411         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10412         return PAGE_ALIGN(pitch * mode->vdisplay);
10413 }
10414
10415 static struct drm_framebuffer *
10416 intel_framebuffer_create_for_mode(struct drm_device *dev,
10417                                   struct drm_display_mode *mode,
10418                                   int depth, int bpp)
10419 {
10420         struct drm_framebuffer *fb;
10421         struct drm_i915_gem_object *obj;
10422         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10423
10424         obj = i915_gem_object_create(dev,
10425                                     intel_framebuffer_size_for_mode(mode, bpp));
10426         if (IS_ERR(obj))
10427                 return ERR_CAST(obj);
10428
10429         mode_cmd.width = mode->hdisplay;
10430         mode_cmd.height = mode->vdisplay;
10431         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10432                                                                 bpp);
10433         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10434
10435         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10436         if (IS_ERR(fb))
10437                 drm_gem_object_unreference_unlocked(&obj->base);
10438
10439         return fb;
10440 }
10441
10442 static struct drm_framebuffer *
10443 mode_fits_in_fbdev(struct drm_device *dev,
10444                    struct drm_display_mode *mode)
10445 {
10446 #ifdef CONFIG_DRM_FBDEV_EMULATION
10447         struct drm_i915_private *dev_priv = to_i915(dev);
10448         struct drm_i915_gem_object *obj;
10449         struct drm_framebuffer *fb;
10450
10451         if (!dev_priv->fbdev)
10452                 return NULL;
10453
10454         if (!dev_priv->fbdev->fb)
10455                 return NULL;
10456
10457         obj = dev_priv->fbdev->fb->obj;
10458         BUG_ON(!obj);
10459
10460         fb = &dev_priv->fbdev->fb->base;
10461         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10462                                                                fb->bits_per_pixel))
10463                 return NULL;
10464
10465         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10466                 return NULL;
10467
10468         drm_framebuffer_reference(fb);
10469         return fb;
10470 #else
10471         return NULL;
10472 #endif
10473 }
10474
10475 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10476                                            struct drm_crtc *crtc,
10477                                            struct drm_display_mode *mode,
10478                                            struct drm_framebuffer *fb,
10479                                            int x, int y)
10480 {
10481         struct drm_plane_state *plane_state;
10482         int hdisplay, vdisplay;
10483         int ret;
10484
10485         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10486         if (IS_ERR(plane_state))
10487                 return PTR_ERR(plane_state);
10488
10489         if (mode)
10490                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10491         else
10492                 hdisplay = vdisplay = 0;
10493
10494         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10495         if (ret)
10496                 return ret;
10497         drm_atomic_set_fb_for_plane(plane_state, fb);
10498         plane_state->crtc_x = 0;
10499         plane_state->crtc_y = 0;
10500         plane_state->crtc_w = hdisplay;
10501         plane_state->crtc_h = vdisplay;
10502         plane_state->src_x = x << 16;
10503         plane_state->src_y = y << 16;
10504         plane_state->src_w = hdisplay << 16;
10505         plane_state->src_h = vdisplay << 16;
10506
10507         return 0;
10508 }
10509
10510 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10511                                 struct drm_display_mode *mode,
10512                                 struct intel_load_detect_pipe *old,
10513                                 struct drm_modeset_acquire_ctx *ctx)
10514 {
10515         struct intel_crtc *intel_crtc;
10516         struct intel_encoder *intel_encoder =
10517                 intel_attached_encoder(connector);
10518         struct drm_crtc *possible_crtc;
10519         struct drm_encoder *encoder = &intel_encoder->base;
10520         struct drm_crtc *crtc = NULL;
10521         struct drm_device *dev = encoder->dev;
10522         struct drm_framebuffer *fb;
10523         struct drm_mode_config *config = &dev->mode_config;
10524         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10525         struct drm_connector_state *connector_state;
10526         struct intel_crtc_state *crtc_state;
10527         int ret, i = -1;
10528
10529         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10530                       connector->base.id, connector->name,
10531                       encoder->base.id, encoder->name);
10532
10533         old->restore_state = NULL;
10534
10535 retry:
10536         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10537         if (ret)
10538                 goto fail;
10539
10540         /*
10541          * Algorithm gets a little messy:
10542          *
10543          *   - if the connector already has an assigned crtc, use it (but make
10544          *     sure it's on first)
10545          *
10546          *   - try to find the first unused crtc that can drive this connector,
10547          *     and use that if we find one
10548          */
10549
10550         /* See if we already have a CRTC for this connector */
10551         if (connector->state->crtc) {
10552                 crtc = connector->state->crtc;
10553
10554                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10555                 if (ret)
10556                         goto fail;
10557
10558                 /* Make sure the crtc and connector are running */
10559                 goto found;
10560         }
10561
10562         /* Find an unused one (if possible) */
10563         for_each_crtc(dev, possible_crtc) {
10564                 i++;
10565                 if (!(encoder->possible_crtcs & (1 << i)))
10566                         continue;
10567
10568                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10569                 if (ret)
10570                         goto fail;
10571
10572                 if (possible_crtc->state->enable) {
10573                         drm_modeset_unlock(&possible_crtc->mutex);
10574                         continue;
10575                 }
10576
10577                 crtc = possible_crtc;
10578                 break;
10579         }
10580
10581         /*
10582          * If we didn't find an unused CRTC, don't use any.
10583          */
10584         if (!crtc) {
10585                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10586                 goto fail;
10587         }
10588
10589 found:
10590         intel_crtc = to_intel_crtc(crtc);
10591
10592         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10593         if (ret)
10594                 goto fail;
10595
10596         state = drm_atomic_state_alloc(dev);
10597         restore_state = drm_atomic_state_alloc(dev);
10598         if (!state || !restore_state) {
10599                 ret = -ENOMEM;
10600                 goto fail;
10601         }
10602
10603         state->acquire_ctx = ctx;
10604         restore_state->acquire_ctx = ctx;
10605
10606         connector_state = drm_atomic_get_connector_state(state, connector);
10607         if (IS_ERR(connector_state)) {
10608                 ret = PTR_ERR(connector_state);
10609                 goto fail;
10610         }
10611
10612         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10613         if (ret)
10614                 goto fail;
10615
10616         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10617         if (IS_ERR(crtc_state)) {
10618                 ret = PTR_ERR(crtc_state);
10619                 goto fail;
10620         }
10621
10622         crtc_state->base.active = crtc_state->base.enable = true;
10623
10624         if (!mode)
10625                 mode = &load_detect_mode;
10626
10627         /* We need a framebuffer large enough to accommodate all accesses
10628          * that the plane may generate whilst we perform load detection.
10629          * We can not rely on the fbcon either being present (we get called
10630          * during its initialisation to detect all boot displays, or it may
10631          * not even exist) or that it is large enough to satisfy the
10632          * requested mode.
10633          */
10634         fb = mode_fits_in_fbdev(dev, mode);
10635         if (fb == NULL) {
10636                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10637                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10638         } else
10639                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10640         if (IS_ERR(fb)) {
10641                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10642                 goto fail;
10643         }
10644
10645         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10646         if (ret)
10647                 goto fail;
10648
10649         drm_framebuffer_unreference(fb);
10650
10651         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10652         if (ret)
10653                 goto fail;
10654
10655         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10656         if (!ret)
10657                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10658         if (!ret)
10659                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10660         if (ret) {
10661                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10662                 goto fail;
10663         }
10664
10665         ret = drm_atomic_commit(state);
10666         if (ret) {
10667                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10668                 goto fail;
10669         }
10670
10671         old->restore_state = restore_state;
10672
10673         /* let the connector get through one full cycle before testing */
10674         intel_wait_for_vblank(dev, intel_crtc->pipe);
10675         return true;
10676
10677 fail:
10678         drm_atomic_state_free(state);
10679         drm_atomic_state_free(restore_state);
10680         restore_state = state = NULL;
10681
10682         if (ret == -EDEADLK) {
10683                 drm_modeset_backoff(ctx);
10684                 goto retry;
10685         }
10686
10687         return false;
10688 }
10689
10690 void intel_release_load_detect_pipe(struct drm_connector *connector,
10691                                     struct intel_load_detect_pipe *old,
10692                                     struct drm_modeset_acquire_ctx *ctx)
10693 {
10694         struct intel_encoder *intel_encoder =
10695                 intel_attached_encoder(connector);
10696         struct drm_encoder *encoder = &intel_encoder->base;
10697         struct drm_atomic_state *state = old->restore_state;
10698         int ret;
10699
10700         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10701                       connector->base.id, connector->name,
10702                       encoder->base.id, encoder->name);
10703
10704         if (!state)
10705                 return;
10706
10707         ret = drm_atomic_commit(state);
10708         if (ret) {
10709                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10710                 drm_atomic_state_free(state);
10711         }
10712 }
10713
10714 static int i9xx_pll_refclk(struct drm_device *dev,
10715                            const struct intel_crtc_state *pipe_config)
10716 {
10717         struct drm_i915_private *dev_priv = to_i915(dev);
10718         u32 dpll = pipe_config->dpll_hw_state.dpll;
10719
10720         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10721                 return dev_priv->vbt.lvds_ssc_freq;
10722         else if (HAS_PCH_SPLIT(dev))
10723                 return 120000;
10724         else if (!IS_GEN2(dev))
10725                 return 96000;
10726         else
10727                 return 48000;
10728 }
10729
10730 /* Returns the clock of the currently programmed mode of the given pipe. */
10731 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10732                                 struct intel_crtc_state *pipe_config)
10733 {
10734         struct drm_device *dev = crtc->base.dev;
10735         struct drm_i915_private *dev_priv = to_i915(dev);
10736         int pipe = pipe_config->cpu_transcoder;
10737         u32 dpll = pipe_config->dpll_hw_state.dpll;
10738         u32 fp;
10739         struct dpll clock;
10740         int port_clock;
10741         int refclk = i9xx_pll_refclk(dev, pipe_config);
10742
10743         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10744                 fp = pipe_config->dpll_hw_state.fp0;
10745         else
10746                 fp = pipe_config->dpll_hw_state.fp1;
10747
10748         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10749         if (IS_PINEVIEW(dev)) {
10750                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10751                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10752         } else {
10753                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10754                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10755         }
10756
10757         if (!IS_GEN2(dev)) {
10758                 if (IS_PINEVIEW(dev))
10759                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10760                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10761                 else
10762                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10763                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10764
10765                 switch (dpll & DPLL_MODE_MASK) {
10766                 case DPLLB_MODE_DAC_SERIAL:
10767                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10768                                 5 : 10;
10769                         break;
10770                 case DPLLB_MODE_LVDS:
10771                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10772                                 7 : 14;
10773                         break;
10774                 default:
10775                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10776                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10777                         return;
10778                 }
10779
10780                 if (IS_PINEVIEW(dev))
10781                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10782                 else
10783                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10784         } else {
10785                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10786                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10787
10788                 if (is_lvds) {
10789                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10790                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10791
10792                         if (lvds & LVDS_CLKB_POWER_UP)
10793                                 clock.p2 = 7;
10794                         else
10795                                 clock.p2 = 14;
10796                 } else {
10797                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10798                                 clock.p1 = 2;
10799                         else {
10800                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10801                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10802                         }
10803                         if (dpll & PLL_P2_DIVIDE_BY_4)
10804                                 clock.p2 = 4;
10805                         else
10806                                 clock.p2 = 2;
10807                 }
10808
10809                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10810         }
10811
10812         /*
10813          * This value includes pixel_multiplier. We will use
10814          * port_clock to compute adjusted_mode.crtc_clock in the
10815          * encoder's get_config() function.
10816          */
10817         pipe_config->port_clock = port_clock;
10818 }
10819
10820 int intel_dotclock_calculate(int link_freq,
10821                              const struct intel_link_m_n *m_n)
10822 {
10823         /*
10824          * The calculation for the data clock is:
10825          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10826          * But we want to avoid losing precison if possible, so:
10827          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10828          *
10829          * and the link clock is simpler:
10830          * link_clock = (m * link_clock) / n
10831          */
10832
10833         if (!m_n->link_n)
10834                 return 0;
10835
10836         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10837 }
10838
10839 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10840                                    struct intel_crtc_state *pipe_config)
10841 {
10842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10843
10844         /* read out port_clock from the DPLL */
10845         i9xx_crtc_clock_get(crtc, pipe_config);
10846
10847         /*
10848          * In case there is an active pipe without active ports,
10849          * we may need some idea for the dotclock anyway.
10850          * Calculate one based on the FDI configuration.
10851          */
10852         pipe_config->base.adjusted_mode.crtc_clock =
10853                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10854                                          &pipe_config->fdi_m_n);
10855 }
10856
10857 /** Returns the currently programmed mode of the given pipe. */
10858 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10859                                              struct drm_crtc *crtc)
10860 {
10861         struct drm_i915_private *dev_priv = to_i915(dev);
10862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10863         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10864         struct drm_display_mode *mode;
10865         struct intel_crtc_state *pipe_config;
10866         int htot = I915_READ(HTOTAL(cpu_transcoder));
10867         int hsync = I915_READ(HSYNC(cpu_transcoder));
10868         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10869         int vsync = I915_READ(VSYNC(cpu_transcoder));
10870         enum pipe pipe = intel_crtc->pipe;
10871
10872         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10873         if (!mode)
10874                 return NULL;
10875
10876         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10877         if (!pipe_config) {
10878                 kfree(mode);
10879                 return NULL;
10880         }
10881
10882         /*
10883          * Construct a pipe_config sufficient for getting the clock info
10884          * back out of crtc_clock_get.
10885          *
10886          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10887          * to use a real value here instead.
10888          */
10889         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10890         pipe_config->pixel_multiplier = 1;
10891         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10892         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10893         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10894         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10895
10896         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10897         mode->hdisplay = (htot & 0xffff) + 1;
10898         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10899         mode->hsync_start = (hsync & 0xffff) + 1;
10900         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10901         mode->vdisplay = (vtot & 0xffff) + 1;
10902         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10903         mode->vsync_start = (vsync & 0xffff) + 1;
10904         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10905
10906         drm_mode_set_name(mode);
10907
10908         kfree(pipe_config);
10909
10910         return mode;
10911 }
10912
10913 static void intel_crtc_destroy(struct drm_crtc *crtc)
10914 {
10915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10916         struct drm_device *dev = crtc->dev;
10917         struct intel_flip_work *work;
10918
10919         spin_lock_irq(&dev->event_lock);
10920         work = intel_crtc->flip_work;
10921         intel_crtc->flip_work = NULL;
10922         spin_unlock_irq(&dev->event_lock);
10923
10924         if (work) {
10925                 cancel_work_sync(&work->mmio_work);
10926                 cancel_work_sync(&work->unpin_work);
10927                 kfree(work);
10928         }
10929
10930         drm_crtc_cleanup(crtc);
10931
10932         kfree(intel_crtc);
10933 }
10934
10935 static void intel_unpin_work_fn(struct work_struct *__work)
10936 {
10937         struct intel_flip_work *work =
10938                 container_of(__work, struct intel_flip_work, unpin_work);
10939         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10940         struct drm_device *dev = crtc->base.dev;
10941         struct drm_plane *primary = crtc->base.primary;
10942
10943         if (is_mmio_work(work))
10944                 flush_work(&work->mmio_work);
10945
10946         mutex_lock(&dev->struct_mutex);
10947         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10948         drm_gem_object_unreference(&work->pending_flip_obj->base);
10949
10950         if (work->flip_queued_req)
10951                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10952         mutex_unlock(&dev->struct_mutex);
10953
10954         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10955         intel_fbc_post_update(crtc);
10956         drm_framebuffer_unreference(work->old_fb);
10957
10958         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10959         atomic_dec(&crtc->unpin_work_count);
10960
10961         kfree(work);
10962 }
10963
10964 /* Is 'a' after or equal to 'b'? */
10965 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10966 {
10967         return !((a - b) & 0x80000000);
10968 }
10969
10970 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10971                                    struct intel_flip_work *work)
10972 {
10973         struct drm_device *dev = crtc->base.dev;
10974         struct drm_i915_private *dev_priv = to_i915(dev);
10975         unsigned reset_counter;
10976
10977         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10978         if (crtc->reset_counter != reset_counter)
10979                 return true;
10980
10981         /*
10982          * The relevant registers doen't exist on pre-ctg.
10983          * As the flip done interrupt doesn't trigger for mmio
10984          * flips on gmch platforms, a flip count check isn't
10985          * really needed there. But since ctg has the registers,
10986          * include it in the check anyway.
10987          */
10988         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10989                 return true;
10990
10991         /*
10992          * BDW signals flip done immediately if the plane
10993          * is disabled, even if the plane enable is already
10994          * armed to occur at the next vblank :(
10995          */
10996
10997         /*
10998          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10999          * used the same base address. In that case the mmio flip might
11000          * have completed, but the CS hasn't even executed the flip yet.
11001          *
11002          * A flip count check isn't enough as the CS might have updated
11003          * the base address just after start of vblank, but before we
11004          * managed to process the interrupt. This means we'd complete the
11005          * CS flip too soon.
11006          *
11007          * Combining both checks should get us a good enough result. It may
11008          * still happen that the CS flip has been executed, but has not
11009          * yet actually completed. But in case the base address is the same
11010          * anyway, we don't really care.
11011          */
11012         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11013                 crtc->flip_work->gtt_offset &&
11014                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11015                                     crtc->flip_work->flip_count);
11016 }
11017
11018 static bool
11019 __pageflip_finished_mmio(struct intel_crtc *crtc,
11020                                struct intel_flip_work *work)
11021 {
11022         /*
11023          * MMIO work completes when vblank is different from
11024          * flip_queued_vblank.
11025          *
11026          * Reset counter value doesn't matter, this is handled by
11027          * i915_wait_request finishing early, so no need to handle
11028          * reset here.
11029          */
11030         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11031 }
11032
11033
11034 static bool pageflip_finished(struct intel_crtc *crtc,
11035                               struct intel_flip_work *work)
11036 {
11037         if (!atomic_read(&work->pending))
11038                 return false;
11039
11040         smp_rmb();
11041
11042         if (is_mmio_work(work))
11043                 return __pageflip_finished_mmio(crtc, work);
11044         else
11045                 return __pageflip_finished_cs(crtc, work);
11046 }
11047
11048 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11049 {
11050         struct drm_device *dev = &dev_priv->drm;
11051         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053         struct intel_flip_work *work;
11054         unsigned long flags;
11055
11056         /* Ignore early vblank irqs */
11057         if (!crtc)
11058                 return;
11059
11060         /*
11061          * This is called both by irq handlers and the reset code (to complete
11062          * lost pageflips) so needs the full irqsave spinlocks.
11063          */
11064         spin_lock_irqsave(&dev->event_lock, flags);
11065         work = intel_crtc->flip_work;
11066
11067         if (work != NULL &&
11068             !is_mmio_work(work) &&
11069             pageflip_finished(intel_crtc, work))
11070                 page_flip_completed(intel_crtc);
11071
11072         spin_unlock_irqrestore(&dev->event_lock, flags);
11073 }
11074
11075 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11076 {
11077         struct drm_device *dev = &dev_priv->drm;
11078         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11080         struct intel_flip_work *work;
11081         unsigned long flags;
11082
11083         /* Ignore early vblank irqs */
11084         if (!crtc)
11085                 return;
11086
11087         /*
11088          * This is called both by irq handlers and the reset code (to complete
11089          * lost pageflips) so needs the full irqsave spinlocks.
11090          */
11091         spin_lock_irqsave(&dev->event_lock, flags);
11092         work = intel_crtc->flip_work;
11093
11094         if (work != NULL &&
11095             is_mmio_work(work) &&
11096             pageflip_finished(intel_crtc, work))
11097                 page_flip_completed(intel_crtc);
11098
11099         spin_unlock_irqrestore(&dev->event_lock, flags);
11100 }
11101
11102 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11103                                                struct intel_flip_work *work)
11104 {
11105         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11106
11107         /* Ensure that the work item is consistent when activating it ... */
11108         smp_mb__before_atomic();
11109         atomic_set(&work->pending, 1);
11110 }
11111
11112 static int intel_gen2_queue_flip(struct drm_device *dev,
11113                                  struct drm_crtc *crtc,
11114                                  struct drm_framebuffer *fb,
11115                                  struct drm_i915_gem_object *obj,
11116                                  struct drm_i915_gem_request *req,
11117                                  uint32_t flags)
11118 {
11119         struct intel_engine_cs *engine = req->engine;
11120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11121         u32 flip_mask;
11122         int ret;
11123
11124         ret = intel_ring_begin(req, 6);
11125         if (ret)
11126                 return ret;
11127
11128         /* Can't queue multiple flips, so wait for the previous
11129          * one to finish before executing the next.
11130          */
11131         if (intel_crtc->plane)
11132                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11133         else
11134                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11135         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11136         intel_ring_emit(engine, MI_NOOP);
11137         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11138                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11139         intel_ring_emit(engine, fb->pitches[0]);
11140         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11141         intel_ring_emit(engine, 0); /* aux display base address, unused */
11142
11143         return 0;
11144 }
11145
11146 static int intel_gen3_queue_flip(struct drm_device *dev,
11147                                  struct drm_crtc *crtc,
11148                                  struct drm_framebuffer *fb,
11149                                  struct drm_i915_gem_object *obj,
11150                                  struct drm_i915_gem_request *req,
11151                                  uint32_t flags)
11152 {
11153         struct intel_engine_cs *engine = req->engine;
11154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11155         u32 flip_mask;
11156         int ret;
11157
11158         ret = intel_ring_begin(req, 6);
11159         if (ret)
11160                 return ret;
11161
11162         if (intel_crtc->plane)
11163                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11164         else
11165                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11166         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11167         intel_ring_emit(engine, MI_NOOP);
11168         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11169                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11170         intel_ring_emit(engine, fb->pitches[0]);
11171         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11172         intel_ring_emit(engine, MI_NOOP);
11173
11174         return 0;
11175 }
11176
11177 static int intel_gen4_queue_flip(struct drm_device *dev,
11178                                  struct drm_crtc *crtc,
11179                                  struct drm_framebuffer *fb,
11180                                  struct drm_i915_gem_object *obj,
11181                                  struct drm_i915_gem_request *req,
11182                                  uint32_t flags)
11183 {
11184         struct intel_engine_cs *engine = req->engine;
11185         struct drm_i915_private *dev_priv = to_i915(dev);
11186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11187         uint32_t pf, pipesrc;
11188         int ret;
11189
11190         ret = intel_ring_begin(req, 4);
11191         if (ret)
11192                 return ret;
11193
11194         /* i965+ uses the linear or tiled offsets from the
11195          * Display Registers (which do not change across a page-flip)
11196          * so we need only reprogram the base address.
11197          */
11198         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11199                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11200         intel_ring_emit(engine, fb->pitches[0]);
11201         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11202                         obj->tiling_mode);
11203
11204         /* XXX Enabling the panel-fitter across page-flip is so far
11205          * untested on non-native modes, so ignore it for now.
11206          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11207          */
11208         pf = 0;
11209         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11210         intel_ring_emit(engine, pf | pipesrc);
11211
11212         return 0;
11213 }
11214
11215 static int intel_gen6_queue_flip(struct drm_device *dev,
11216                                  struct drm_crtc *crtc,
11217                                  struct drm_framebuffer *fb,
11218                                  struct drm_i915_gem_object *obj,
11219                                  struct drm_i915_gem_request *req,
11220                                  uint32_t flags)
11221 {
11222         struct intel_engine_cs *engine = req->engine;
11223         struct drm_i915_private *dev_priv = to_i915(dev);
11224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11225         uint32_t pf, pipesrc;
11226         int ret;
11227
11228         ret = intel_ring_begin(req, 4);
11229         if (ret)
11230                 return ret;
11231
11232         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11233                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11234         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11235         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11236
11237         /* Contrary to the suggestions in the documentation,
11238          * "Enable Panel Fitter" does not seem to be required when page
11239          * flipping with a non-native mode, and worse causes a normal
11240          * modeset to fail.
11241          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11242          */
11243         pf = 0;
11244         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11245         intel_ring_emit(engine, pf | pipesrc);
11246
11247         return 0;
11248 }
11249
11250 static int intel_gen7_queue_flip(struct drm_device *dev,
11251                                  struct drm_crtc *crtc,
11252                                  struct drm_framebuffer *fb,
11253                                  struct drm_i915_gem_object *obj,
11254                                  struct drm_i915_gem_request *req,
11255                                  uint32_t flags)
11256 {
11257         struct intel_engine_cs *engine = req->engine;
11258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11259         uint32_t plane_bit = 0;
11260         int len, ret;
11261
11262         switch (intel_crtc->plane) {
11263         case PLANE_A:
11264                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11265                 break;
11266         case PLANE_B:
11267                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11268                 break;
11269         case PLANE_C:
11270                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11271                 break;
11272         default:
11273                 WARN_ONCE(1, "unknown plane in flip command\n");
11274                 return -ENODEV;
11275         }
11276
11277         len = 4;
11278         if (engine->id == RCS) {
11279                 len += 6;
11280                 /*
11281                  * On Gen 8, SRM is now taking an extra dword to accommodate
11282                  * 48bits addresses, and we need a NOOP for the batch size to
11283                  * stay even.
11284                  */
11285                 if (IS_GEN8(dev))
11286                         len += 2;
11287         }
11288
11289         /*
11290          * BSpec MI_DISPLAY_FLIP for IVB:
11291          * "The full packet must be contained within the same cache line."
11292          *
11293          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11294          * cacheline, if we ever start emitting more commands before
11295          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11296          * then do the cacheline alignment, and finally emit the
11297          * MI_DISPLAY_FLIP.
11298          */
11299         ret = intel_ring_cacheline_align(req);
11300         if (ret)
11301                 return ret;
11302
11303         ret = intel_ring_begin(req, len);
11304         if (ret)
11305                 return ret;
11306
11307         /* Unmask the flip-done completion message. Note that the bspec says that
11308          * we should do this for both the BCS and RCS, and that we must not unmask
11309          * more than one flip event at any time (or ensure that one flip message
11310          * can be sent by waiting for flip-done prior to queueing new flips).
11311          * Experimentation says that BCS works despite DERRMR masking all
11312          * flip-done completion events and that unmasking all planes at once
11313          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11314          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11315          */
11316         if (engine->id == RCS) {
11317                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11318                 intel_ring_emit_reg(engine, DERRMR);
11319                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11320                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11321                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11322                 if (IS_GEN8(dev))
11323                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11324                                               MI_SRM_LRM_GLOBAL_GTT);
11325                 else
11326                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11327                                               MI_SRM_LRM_GLOBAL_GTT);
11328                 intel_ring_emit_reg(engine, DERRMR);
11329                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11330                 if (IS_GEN8(dev)) {
11331                         intel_ring_emit(engine, 0);
11332                         intel_ring_emit(engine, MI_NOOP);
11333                 }
11334         }
11335
11336         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11337         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11338         intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11339         intel_ring_emit(engine, (MI_NOOP));
11340
11341         return 0;
11342 }
11343
11344 static bool use_mmio_flip(struct intel_engine_cs *engine,
11345                           struct drm_i915_gem_object *obj)
11346 {
11347         struct reservation_object *resv;
11348
11349         /*
11350          * This is not being used for older platforms, because
11351          * non-availability of flip done interrupt forces us to use
11352          * CS flips. Older platforms derive flip done using some clever
11353          * tricks involving the flip_pending status bits and vblank irqs.
11354          * So using MMIO flips there would disrupt this mechanism.
11355          */
11356
11357         if (engine == NULL)
11358                 return true;
11359
11360         if (INTEL_GEN(engine->i915) < 5)
11361                 return false;
11362
11363         if (i915.use_mmio_flip < 0)
11364                 return false;
11365         else if (i915.use_mmio_flip > 0)
11366                 return true;
11367         else if (i915.enable_execlists)
11368                 return true;
11369
11370         resv = i915_gem_object_get_dmabuf_resv(obj);
11371         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11372                 return true;
11373
11374         return engine != i915_gem_request_get_engine(obj->last_write_req);
11375 }
11376
11377 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11378                              unsigned int rotation,
11379                              struct intel_flip_work *work)
11380 {
11381         struct drm_device *dev = intel_crtc->base.dev;
11382         struct drm_i915_private *dev_priv = to_i915(dev);
11383         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11384         const enum pipe pipe = intel_crtc->pipe;
11385         u32 ctl, stride, tile_height;
11386
11387         ctl = I915_READ(PLANE_CTL(pipe, 0));
11388         ctl &= ~PLANE_CTL_TILED_MASK;
11389         switch (fb->modifier[0]) {
11390         case DRM_FORMAT_MOD_NONE:
11391                 break;
11392         case I915_FORMAT_MOD_X_TILED:
11393                 ctl |= PLANE_CTL_TILED_X;
11394                 break;
11395         case I915_FORMAT_MOD_Y_TILED:
11396                 ctl |= PLANE_CTL_TILED_Y;
11397                 break;
11398         case I915_FORMAT_MOD_Yf_TILED:
11399                 ctl |= PLANE_CTL_TILED_YF;
11400                 break;
11401         default:
11402                 MISSING_CASE(fb->modifier[0]);
11403         }
11404
11405         /*
11406          * The stride is either expressed as a multiple of 64 bytes chunks for
11407          * linear buffers or in number of tiles for tiled buffers.
11408          */
11409         if (intel_rotation_90_or_270(rotation)) {
11410                 /* stride = Surface height in tiles */
11411                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11412                 stride = DIV_ROUND_UP(fb->height, tile_height);
11413         } else {
11414                 stride = fb->pitches[0] /
11415                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11416                                                   fb->pixel_format);
11417         }
11418
11419         /*
11420          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11421          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11422          */
11423         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11424         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11425
11426         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11427         POSTING_READ(PLANE_SURF(pipe, 0));
11428 }
11429
11430 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11431                              struct intel_flip_work *work)
11432 {
11433         struct drm_device *dev = intel_crtc->base.dev;
11434         struct drm_i915_private *dev_priv = to_i915(dev);
11435         struct intel_framebuffer *intel_fb =
11436                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11437         struct drm_i915_gem_object *obj = intel_fb->obj;
11438         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11439         u32 dspcntr;
11440
11441         dspcntr = I915_READ(reg);
11442
11443         if (obj->tiling_mode != I915_TILING_NONE)
11444                 dspcntr |= DISPPLANE_TILED;
11445         else
11446                 dspcntr &= ~DISPPLANE_TILED;
11447
11448         I915_WRITE(reg, dspcntr);
11449
11450         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11451         POSTING_READ(DSPSURF(intel_crtc->plane));
11452 }
11453
11454 static void intel_mmio_flip_work_func(struct work_struct *w)
11455 {
11456         struct intel_flip_work *work =
11457                 container_of(w, struct intel_flip_work, mmio_work);
11458         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11460         struct intel_framebuffer *intel_fb =
11461                 to_intel_framebuffer(crtc->base.primary->fb);
11462         struct drm_i915_gem_object *obj = intel_fb->obj;
11463         struct reservation_object *resv;
11464
11465         if (work->flip_queued_req)
11466                 WARN_ON(__i915_wait_request(work->flip_queued_req,
11467                                             false, NULL,
11468                                             &dev_priv->rps.mmioflips));
11469
11470         /* For framebuffer backed by dmabuf, wait for fence */
11471         resv = i915_gem_object_get_dmabuf_resv(obj);
11472         if (resv)
11473                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11474                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11475
11476         intel_pipe_update_start(crtc);
11477
11478         if (INTEL_GEN(dev_priv) >= 9)
11479                 skl_do_mmio_flip(crtc, work->rotation, work);
11480         else
11481                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11482                 ilk_do_mmio_flip(crtc, work);
11483
11484         intel_pipe_update_end(crtc, work);
11485 }
11486
11487 static int intel_default_queue_flip(struct drm_device *dev,
11488                                     struct drm_crtc *crtc,
11489                                     struct drm_framebuffer *fb,
11490                                     struct drm_i915_gem_object *obj,
11491                                     struct drm_i915_gem_request *req,
11492                                     uint32_t flags)
11493 {
11494         return -ENODEV;
11495 }
11496
11497 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11498                                       struct intel_crtc *intel_crtc,
11499                                       struct intel_flip_work *work)
11500 {
11501         u32 addr, vblank;
11502
11503         if (!atomic_read(&work->pending))
11504                 return false;
11505
11506         smp_rmb();
11507
11508         vblank = intel_crtc_get_vblank_counter(intel_crtc);
11509         if (work->flip_ready_vblank == 0) {
11510                 if (work->flip_queued_req &&
11511                     !i915_gem_request_completed(work->flip_queued_req))
11512                         return false;
11513
11514                 work->flip_ready_vblank = vblank;
11515         }
11516
11517         if (vblank - work->flip_ready_vblank < 3)
11518                 return false;
11519
11520         /* Potential stall - if we see that the flip has happened,
11521          * assume a missed interrupt. */
11522         if (INTEL_GEN(dev_priv) >= 4)
11523                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11524         else
11525                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11526
11527         /* There is a potential issue here with a false positive after a flip
11528          * to the same address. We could address this by checking for a
11529          * non-incrementing frame counter.
11530          */
11531         return addr == work->gtt_offset;
11532 }
11533
11534 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11535 {
11536         struct drm_device *dev = &dev_priv->drm;
11537         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11539         struct intel_flip_work *work;
11540
11541         WARN_ON(!in_interrupt());
11542
11543         if (crtc == NULL)
11544                 return;
11545
11546         spin_lock(&dev->event_lock);
11547         work = intel_crtc->flip_work;
11548
11549         if (work != NULL && !is_mmio_work(work) &&
11550             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11551                 WARN_ONCE(1,
11552                           "Kicking stuck page flip: queued at %d, now %d\n",
11553                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11554                 page_flip_completed(intel_crtc);
11555                 work = NULL;
11556         }
11557
11558         if (work != NULL && !is_mmio_work(work) &&
11559             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11560                 intel_queue_rps_boost_for_request(work->flip_queued_req);
11561         spin_unlock(&dev->event_lock);
11562 }
11563
11564 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11565                                 struct drm_framebuffer *fb,
11566                                 struct drm_pending_vblank_event *event,
11567                                 uint32_t page_flip_flags)
11568 {
11569         struct drm_device *dev = crtc->dev;
11570         struct drm_i915_private *dev_priv = to_i915(dev);
11571         struct drm_framebuffer *old_fb = crtc->primary->fb;
11572         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11574         struct drm_plane *primary = crtc->primary;
11575         enum pipe pipe = intel_crtc->pipe;
11576         struct intel_flip_work *work;
11577         struct intel_engine_cs *engine;
11578         bool mmio_flip;
11579         struct drm_i915_gem_request *request = NULL;
11580         int ret;
11581
11582         /*
11583          * drm_mode_page_flip_ioctl() should already catch this, but double
11584          * check to be safe.  In the future we may enable pageflipping from
11585          * a disabled primary plane.
11586          */
11587         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11588                 return -EBUSY;
11589
11590         /* Can't change pixel format via MI display flips. */
11591         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11592                 return -EINVAL;
11593
11594         /*
11595          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11596          * Note that pitch changes could also affect these register.
11597          */
11598         if (INTEL_INFO(dev)->gen > 3 &&
11599             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11600              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11601                 return -EINVAL;
11602
11603         if (i915_terminally_wedged(&dev_priv->gpu_error))
11604                 goto out_hang;
11605
11606         work = kzalloc(sizeof(*work), GFP_KERNEL);
11607         if (work == NULL)
11608                 return -ENOMEM;
11609
11610         work->event = event;
11611         work->crtc = crtc;
11612         work->old_fb = old_fb;
11613         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11614
11615         ret = drm_crtc_vblank_get(crtc);
11616         if (ret)
11617                 goto free_work;
11618
11619         /* We borrow the event spin lock for protecting flip_work */
11620         spin_lock_irq(&dev->event_lock);
11621         if (intel_crtc->flip_work) {
11622                 /* Before declaring the flip queue wedged, check if
11623                  * the hardware completed the operation behind our backs.
11624                  */
11625                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11626                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11627                         page_flip_completed(intel_crtc);
11628                 } else {
11629                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11630                         spin_unlock_irq(&dev->event_lock);
11631
11632                         drm_crtc_vblank_put(crtc);
11633                         kfree(work);
11634                         return -EBUSY;
11635                 }
11636         }
11637         intel_crtc->flip_work = work;
11638         spin_unlock_irq(&dev->event_lock);
11639
11640         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11641                 flush_workqueue(dev_priv->wq);
11642
11643         /* Reference the objects for the scheduled work. */
11644         drm_framebuffer_reference(work->old_fb);
11645         drm_gem_object_reference(&obj->base);
11646
11647         crtc->primary->fb = fb;
11648         update_state_fb(crtc->primary);
11649
11650         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11651                              to_intel_plane_state(primary->state));
11652
11653         work->pending_flip_obj = obj;
11654
11655         ret = i915_mutex_lock_interruptible(dev);
11656         if (ret)
11657                 goto cleanup;
11658
11659         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11660         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11661                 ret = -EIO;
11662                 goto cleanup;
11663         }
11664
11665         atomic_inc(&intel_crtc->unpin_work_count);
11666
11667         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11668                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11669
11670         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11671                 engine = &dev_priv->engine[BCS];
11672                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11673                         /* vlv: DISPLAY_FLIP fails to change tiling */
11674                         engine = NULL;
11675         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11676                 engine = &dev_priv->engine[BCS];
11677         } else if (INTEL_INFO(dev)->gen >= 7) {
11678                 engine = i915_gem_request_get_engine(obj->last_write_req);
11679                 if (engine == NULL || engine->id != RCS)
11680                         engine = &dev_priv->engine[BCS];
11681         } else {
11682                 engine = &dev_priv->engine[RCS];
11683         }
11684
11685         mmio_flip = use_mmio_flip(engine, obj);
11686
11687         /* When using CS flips, we want to emit semaphores between rings.
11688          * However, when using mmio flips we will create a task to do the
11689          * synchronisation, so all we want here is to pin the framebuffer
11690          * into the display plane and skip any waits.
11691          */
11692         if (!mmio_flip) {
11693                 ret = i915_gem_object_sync(obj, engine, &request);
11694                 if (!ret && !request) {
11695                         request = i915_gem_request_alloc(engine, NULL);
11696                         ret = PTR_ERR_OR_ZERO(request);
11697                 }
11698
11699                 if (ret)
11700                         goto cleanup_pending;
11701         }
11702
11703         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11704         if (ret)
11705                 goto cleanup_pending;
11706
11707         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11708                                                   obj, 0);
11709         work->gtt_offset += intel_crtc->dspaddr_offset;
11710         work->rotation = crtc->primary->state->rotation;
11711
11712         if (mmio_flip) {
11713                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11714
11715                 i915_gem_request_assign(&work->flip_queued_req,
11716                                         obj->last_write_req);
11717
11718                 schedule_work(&work->mmio_work);
11719         } else {
11720                 i915_gem_request_assign(&work->flip_queued_req, request);
11721                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11722                                                    page_flip_flags);
11723                 if (ret)
11724                         goto cleanup_unpin;
11725
11726                 intel_mark_page_flip_active(intel_crtc, work);
11727
11728                 i915_add_request_no_flush(request);
11729         }
11730
11731         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11732                           to_intel_plane(primary)->frontbuffer_bit);
11733         mutex_unlock(&dev->struct_mutex);
11734
11735         intel_frontbuffer_flip_prepare(dev,
11736                                        to_intel_plane(primary)->frontbuffer_bit);
11737
11738         trace_i915_flip_request(intel_crtc->plane, obj);
11739
11740         return 0;
11741
11742 cleanup_unpin:
11743         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11744 cleanup_pending:
11745         if (!IS_ERR_OR_NULL(request))
11746                 i915_add_request_no_flush(request);
11747         atomic_dec(&intel_crtc->unpin_work_count);
11748         mutex_unlock(&dev->struct_mutex);
11749 cleanup:
11750         crtc->primary->fb = old_fb;
11751         update_state_fb(crtc->primary);
11752
11753         drm_gem_object_unreference_unlocked(&obj->base);
11754         drm_framebuffer_unreference(work->old_fb);
11755
11756         spin_lock_irq(&dev->event_lock);
11757         intel_crtc->flip_work = NULL;
11758         spin_unlock_irq(&dev->event_lock);
11759
11760         drm_crtc_vblank_put(crtc);
11761 free_work:
11762         kfree(work);
11763
11764         if (ret == -EIO) {
11765                 struct drm_atomic_state *state;
11766                 struct drm_plane_state *plane_state;
11767
11768 out_hang:
11769                 state = drm_atomic_state_alloc(dev);
11770                 if (!state)
11771                         return -ENOMEM;
11772                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11773
11774 retry:
11775                 plane_state = drm_atomic_get_plane_state(state, primary);
11776                 ret = PTR_ERR_OR_ZERO(plane_state);
11777                 if (!ret) {
11778                         drm_atomic_set_fb_for_plane(plane_state, fb);
11779
11780                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11781                         if (!ret)
11782                                 ret = drm_atomic_commit(state);
11783                 }
11784
11785                 if (ret == -EDEADLK) {
11786                         drm_modeset_backoff(state->acquire_ctx);
11787                         drm_atomic_state_clear(state);
11788                         goto retry;
11789                 }
11790
11791                 if (ret)
11792                         drm_atomic_state_free(state);
11793
11794                 if (ret == 0 && event) {
11795                         spin_lock_irq(&dev->event_lock);
11796                         drm_crtc_send_vblank_event(crtc, event);
11797                         spin_unlock_irq(&dev->event_lock);
11798                 }
11799         }
11800         return ret;
11801 }
11802
11803
11804 /**
11805  * intel_wm_need_update - Check whether watermarks need updating
11806  * @plane: drm plane
11807  * @state: new plane state
11808  *
11809  * Check current plane state versus the new one to determine whether
11810  * watermarks need to be recalculated.
11811  *
11812  * Returns true or false.
11813  */
11814 static bool intel_wm_need_update(struct drm_plane *plane,
11815                                  struct drm_plane_state *state)
11816 {
11817         struct intel_plane_state *new = to_intel_plane_state(state);
11818         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11819
11820         /* Update watermarks on tiling or size changes. */
11821         if (new->visible != cur->visible)
11822                 return true;
11823
11824         if (!cur->base.fb || !new->base.fb)
11825                 return false;
11826
11827         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11828             cur->base.rotation != new->base.rotation ||
11829             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11830             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11831             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11832             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11833                 return true;
11834
11835         return false;
11836 }
11837
11838 static bool needs_scaling(struct intel_plane_state *state)
11839 {
11840         int src_w = drm_rect_width(&state->src) >> 16;
11841         int src_h = drm_rect_height(&state->src) >> 16;
11842         int dst_w = drm_rect_width(&state->dst);
11843         int dst_h = drm_rect_height(&state->dst);
11844
11845         return (src_w != dst_w || src_h != dst_h);
11846 }
11847
11848 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11849                                     struct drm_plane_state *plane_state)
11850 {
11851         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11852         struct drm_crtc *crtc = crtc_state->crtc;
11853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11854         struct drm_plane *plane = plane_state->plane;
11855         struct drm_device *dev = crtc->dev;
11856         struct drm_i915_private *dev_priv = to_i915(dev);
11857         struct intel_plane_state *old_plane_state =
11858                 to_intel_plane_state(plane->state);
11859         bool mode_changed = needs_modeset(crtc_state);
11860         bool was_crtc_enabled = crtc->state->active;
11861         bool is_crtc_enabled = crtc_state->active;
11862         bool turn_off, turn_on, visible, was_visible;
11863         struct drm_framebuffer *fb = plane_state->fb;
11864         int ret;
11865
11866         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
11867                 ret = skl_update_scaler_plane(
11868                         to_intel_crtc_state(crtc_state),
11869                         to_intel_plane_state(plane_state));
11870                 if (ret)
11871                         return ret;
11872         }
11873
11874         was_visible = old_plane_state->visible;
11875         visible = to_intel_plane_state(plane_state)->visible;
11876
11877         if (!was_crtc_enabled && WARN_ON(was_visible))
11878                 was_visible = false;
11879
11880         /*
11881          * Visibility is calculated as if the crtc was on, but
11882          * after scaler setup everything depends on it being off
11883          * when the crtc isn't active.
11884          *
11885          * FIXME this is wrong for watermarks. Watermarks should also
11886          * be computed as if the pipe would be active. Perhaps move
11887          * per-plane wm computation to the .check_plane() hook, and
11888          * only combine the results from all planes in the current place?
11889          */
11890         if (!is_crtc_enabled)
11891                 to_intel_plane_state(plane_state)->visible = visible = false;
11892
11893         if (!was_visible && !visible)
11894                 return 0;
11895
11896         if (fb != old_plane_state->base.fb)
11897                 pipe_config->fb_changed = true;
11898
11899         turn_off = was_visible && (!visible || mode_changed);
11900         turn_on = visible && (!was_visible || mode_changed);
11901
11902         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11903                          intel_crtc->base.base.id,
11904                          intel_crtc->base.name,
11905                          plane->base.id, plane->name,
11906                          fb ? fb->base.id : -1);
11907
11908         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11909                          plane->base.id, plane->name,
11910                          was_visible, visible,
11911                          turn_off, turn_on, mode_changed);
11912
11913         if (turn_on) {
11914                 pipe_config->update_wm_pre = true;
11915
11916                 /* must disable cxsr around plane enable/disable */
11917                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11918                         pipe_config->disable_cxsr = true;
11919         } else if (turn_off) {
11920                 pipe_config->update_wm_post = true;
11921
11922                 /* must disable cxsr around plane enable/disable */
11923                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11924                         pipe_config->disable_cxsr = true;
11925         } else if (intel_wm_need_update(plane, plane_state)) {
11926                 /* FIXME bollocks */
11927                 pipe_config->update_wm_pre = true;
11928                 pipe_config->update_wm_post = true;
11929         }
11930
11931         /* Pre-gen9 platforms need two-step watermark updates */
11932         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11933             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11934                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11935
11936         if (visible || was_visible)
11937                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11938
11939         /*
11940          * WaCxSRDisabledForSpriteScaling:ivb
11941          *
11942          * cstate->update_wm was already set above, so this flag will
11943          * take effect when we commit and program watermarks.
11944          */
11945         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11946             needs_scaling(to_intel_plane_state(plane_state)) &&
11947             !needs_scaling(old_plane_state))
11948                 pipe_config->disable_lp_wm = true;
11949
11950         return 0;
11951 }
11952
11953 static bool encoders_cloneable(const struct intel_encoder *a,
11954                                const struct intel_encoder *b)
11955 {
11956         /* masks could be asymmetric, so check both ways */
11957         return a == b || (a->cloneable & (1 << b->type) &&
11958                           b->cloneable & (1 << a->type));
11959 }
11960
11961 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11962                                          struct intel_crtc *crtc,
11963                                          struct intel_encoder *encoder)
11964 {
11965         struct intel_encoder *source_encoder;
11966         struct drm_connector *connector;
11967         struct drm_connector_state *connector_state;
11968         int i;
11969
11970         for_each_connector_in_state(state, connector, connector_state, i) {
11971                 if (connector_state->crtc != &crtc->base)
11972                         continue;
11973
11974                 source_encoder =
11975                         to_intel_encoder(connector_state->best_encoder);
11976                 if (!encoders_cloneable(encoder, source_encoder))
11977                         return false;
11978         }
11979
11980         return true;
11981 }
11982
11983 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11984                                    struct drm_crtc_state *crtc_state)
11985 {
11986         struct drm_device *dev = crtc->dev;
11987         struct drm_i915_private *dev_priv = to_i915(dev);
11988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11989         struct intel_crtc_state *pipe_config =
11990                 to_intel_crtc_state(crtc_state);
11991         struct drm_atomic_state *state = crtc_state->state;
11992         int ret;
11993         bool mode_changed = needs_modeset(crtc_state);
11994
11995         if (mode_changed && !crtc_state->active)
11996                 pipe_config->update_wm_post = true;
11997
11998         if (mode_changed && crtc_state->enable &&
11999             dev_priv->display.crtc_compute_clock &&
12000             !WARN_ON(pipe_config->shared_dpll)) {
12001                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12002                                                            pipe_config);
12003                 if (ret)
12004                         return ret;
12005         }
12006
12007         if (crtc_state->color_mgmt_changed) {
12008                 ret = intel_color_check(crtc, crtc_state);
12009                 if (ret)
12010                         return ret;
12011
12012                 /*
12013                  * Changing color management on Intel hardware is
12014                  * handled as part of planes update.
12015                  */
12016                 crtc_state->planes_changed = true;
12017         }
12018
12019         ret = 0;
12020         if (dev_priv->display.compute_pipe_wm) {
12021                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12022                 if (ret) {
12023                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12024                         return ret;
12025                 }
12026         }
12027
12028         if (dev_priv->display.compute_intermediate_wm &&
12029             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12030                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12031                         return 0;
12032
12033                 /*
12034                  * Calculate 'intermediate' watermarks that satisfy both the
12035                  * old state and the new state.  We can program these
12036                  * immediately.
12037                  */
12038                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12039                                                                 intel_crtc,
12040                                                                 pipe_config);
12041                 if (ret) {
12042                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12043                         return ret;
12044                 }
12045         } else if (dev_priv->display.compute_intermediate_wm) {
12046                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12047                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12048         }
12049
12050         if (INTEL_INFO(dev)->gen >= 9) {
12051                 if (mode_changed)
12052                         ret = skl_update_scaler_crtc(pipe_config);
12053
12054                 if (!ret)
12055                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12056                                                          pipe_config);
12057         }
12058
12059         return ret;
12060 }
12061
12062 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12063         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12064         .atomic_begin = intel_begin_crtc_commit,
12065         .atomic_flush = intel_finish_crtc_commit,
12066         .atomic_check = intel_crtc_atomic_check,
12067 };
12068
12069 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12070 {
12071         struct intel_connector *connector;
12072
12073         for_each_intel_connector(dev, connector) {
12074                 if (connector->base.state->crtc)
12075                         drm_connector_unreference(&connector->base);
12076
12077                 if (connector->base.encoder) {
12078                         connector->base.state->best_encoder =
12079                                 connector->base.encoder;
12080                         connector->base.state->crtc =
12081                                 connector->base.encoder->crtc;
12082
12083                         drm_connector_reference(&connector->base);
12084                 } else {
12085                         connector->base.state->best_encoder = NULL;
12086                         connector->base.state->crtc = NULL;
12087                 }
12088         }
12089 }
12090
12091 static void
12092 connected_sink_compute_bpp(struct intel_connector *connector,
12093                            struct intel_crtc_state *pipe_config)
12094 {
12095         int bpp = pipe_config->pipe_bpp;
12096
12097         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12098                 connector->base.base.id,
12099                 connector->base.name);
12100
12101         /* Don't use an invalid EDID bpc value */
12102         if (connector->base.display_info.bpc &&
12103             connector->base.display_info.bpc * 3 < bpp) {
12104                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12105                               bpp, connector->base.display_info.bpc*3);
12106                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12107         }
12108
12109         /* Clamp bpp to default limit on screens without EDID 1.4 */
12110         if (connector->base.display_info.bpc == 0) {
12111                 int type = connector->base.connector_type;
12112                 int clamp_bpp = 24;
12113
12114                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12115                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12116                     type == DRM_MODE_CONNECTOR_eDP)
12117                         clamp_bpp = 18;
12118
12119                 if (bpp > clamp_bpp) {
12120                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12121                                       bpp, clamp_bpp);
12122                         pipe_config->pipe_bpp = clamp_bpp;
12123                 }
12124         }
12125 }
12126
12127 static int
12128 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12129                           struct intel_crtc_state *pipe_config)
12130 {
12131         struct drm_device *dev = crtc->base.dev;
12132         struct drm_atomic_state *state;
12133         struct drm_connector *connector;
12134         struct drm_connector_state *connector_state;
12135         int bpp, i;
12136
12137         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12138                 bpp = 10*3;
12139         else if (INTEL_INFO(dev)->gen >= 5)
12140                 bpp = 12*3;
12141         else
12142                 bpp = 8*3;
12143
12144
12145         pipe_config->pipe_bpp = bpp;
12146
12147         state = pipe_config->base.state;
12148
12149         /* Clamp display bpp to EDID value */
12150         for_each_connector_in_state(state, connector, connector_state, i) {
12151                 if (connector_state->crtc != &crtc->base)
12152                         continue;
12153
12154                 connected_sink_compute_bpp(to_intel_connector(connector),
12155                                            pipe_config);
12156         }
12157
12158         return bpp;
12159 }
12160
12161 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12162 {
12163         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12164                         "type: 0x%x flags: 0x%x\n",
12165                 mode->crtc_clock,
12166                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12167                 mode->crtc_hsync_end, mode->crtc_htotal,
12168                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12169                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12170 }
12171
12172 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12173                                    struct intel_crtc_state *pipe_config,
12174                                    const char *context)
12175 {
12176         struct drm_device *dev = crtc->base.dev;
12177         struct drm_plane *plane;
12178         struct intel_plane *intel_plane;
12179         struct intel_plane_state *state;
12180         struct drm_framebuffer *fb;
12181
12182         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12183                       crtc->base.base.id, crtc->base.name,
12184                       context, pipe_config, pipe_name(crtc->pipe));
12185
12186         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12187         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12188                       pipe_config->pipe_bpp, pipe_config->dither);
12189         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12190                       pipe_config->has_pch_encoder,
12191                       pipe_config->fdi_lanes,
12192                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12193                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12194                       pipe_config->fdi_m_n.tu);
12195         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12196                       intel_crtc_has_dp_encoder(pipe_config),
12197                       pipe_config->lane_count,
12198                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12199                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12200                       pipe_config->dp_m_n.tu);
12201
12202         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12203                       intel_crtc_has_dp_encoder(pipe_config),
12204                       pipe_config->lane_count,
12205                       pipe_config->dp_m2_n2.gmch_m,
12206                       pipe_config->dp_m2_n2.gmch_n,
12207                       pipe_config->dp_m2_n2.link_m,
12208                       pipe_config->dp_m2_n2.link_n,
12209                       pipe_config->dp_m2_n2.tu);
12210
12211         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12212                       pipe_config->has_audio,
12213                       pipe_config->has_infoframe);
12214
12215         DRM_DEBUG_KMS("requested mode:\n");
12216         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12217         DRM_DEBUG_KMS("adjusted mode:\n");
12218         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12219         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12220         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12221         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12222                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12223         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12224                       crtc->num_scalers,
12225                       pipe_config->scaler_state.scaler_users,
12226                       pipe_config->scaler_state.scaler_id);
12227         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12228                       pipe_config->gmch_pfit.control,
12229                       pipe_config->gmch_pfit.pgm_ratios,
12230                       pipe_config->gmch_pfit.lvds_border_bits);
12231         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12232                       pipe_config->pch_pfit.pos,
12233                       pipe_config->pch_pfit.size,
12234                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12235         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12236         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12237
12238         if (IS_BROXTON(dev)) {
12239                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12240                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12241                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12242                               pipe_config->ddi_pll_sel,
12243                               pipe_config->dpll_hw_state.ebb0,
12244                               pipe_config->dpll_hw_state.ebb4,
12245                               pipe_config->dpll_hw_state.pll0,
12246                               pipe_config->dpll_hw_state.pll1,
12247                               pipe_config->dpll_hw_state.pll2,
12248                               pipe_config->dpll_hw_state.pll3,
12249                               pipe_config->dpll_hw_state.pll6,
12250                               pipe_config->dpll_hw_state.pll8,
12251                               pipe_config->dpll_hw_state.pll9,
12252                               pipe_config->dpll_hw_state.pll10,
12253                               pipe_config->dpll_hw_state.pcsdw12);
12254         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12255                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12256                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12257                               pipe_config->ddi_pll_sel,
12258                               pipe_config->dpll_hw_state.ctrl1,
12259                               pipe_config->dpll_hw_state.cfgcr1,
12260                               pipe_config->dpll_hw_state.cfgcr2);
12261         } else if (HAS_DDI(dev)) {
12262                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12263                               pipe_config->ddi_pll_sel,
12264                               pipe_config->dpll_hw_state.wrpll,
12265                               pipe_config->dpll_hw_state.spll);
12266         } else {
12267                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12268                               "fp0: 0x%x, fp1: 0x%x\n",
12269                               pipe_config->dpll_hw_state.dpll,
12270                               pipe_config->dpll_hw_state.dpll_md,
12271                               pipe_config->dpll_hw_state.fp0,
12272                               pipe_config->dpll_hw_state.fp1);
12273         }
12274
12275         DRM_DEBUG_KMS("planes on this crtc\n");
12276         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12277                 intel_plane = to_intel_plane(plane);
12278                 if (intel_plane->pipe != crtc->pipe)
12279                         continue;
12280
12281                 state = to_intel_plane_state(plane->state);
12282                 fb = state->base.fb;
12283                 if (!fb) {
12284                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12285                                       plane->base.id, plane->name, state->scaler_id);
12286                         continue;
12287                 }
12288
12289                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12290                               plane->base.id, plane->name);
12291                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12292                               fb->base.id, fb->width, fb->height,
12293                               drm_get_format_name(fb->pixel_format));
12294                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12295                               state->scaler_id,
12296                               state->src.x1 >> 16, state->src.y1 >> 16,
12297                               drm_rect_width(&state->src) >> 16,
12298                               drm_rect_height(&state->src) >> 16,
12299                               state->dst.x1, state->dst.y1,
12300                               drm_rect_width(&state->dst),
12301                               drm_rect_height(&state->dst));
12302         }
12303 }
12304
12305 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12306 {
12307         struct drm_device *dev = state->dev;
12308         struct drm_connector *connector;
12309         unsigned int used_ports = 0;
12310
12311         /*
12312          * Walk the connector list instead of the encoder
12313          * list to detect the problem on ddi platforms
12314          * where there's just one encoder per digital port.
12315          */
12316         drm_for_each_connector(connector, dev) {
12317                 struct drm_connector_state *connector_state;
12318                 struct intel_encoder *encoder;
12319
12320                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12321                 if (!connector_state)
12322                         connector_state = connector->state;
12323
12324                 if (!connector_state->best_encoder)
12325                         continue;
12326
12327                 encoder = to_intel_encoder(connector_state->best_encoder);
12328
12329                 WARN_ON(!connector_state->crtc);
12330
12331                 switch (encoder->type) {
12332                         unsigned int port_mask;
12333                 case INTEL_OUTPUT_UNKNOWN:
12334                         if (WARN_ON(!HAS_DDI(dev)))
12335                                 break;
12336                 case INTEL_OUTPUT_DP:
12337                 case INTEL_OUTPUT_HDMI:
12338                 case INTEL_OUTPUT_EDP:
12339                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12340
12341                         /* the same port mustn't appear more than once */
12342                         if (used_ports & port_mask)
12343                                 return false;
12344
12345                         used_ports |= port_mask;
12346                 default:
12347                         break;
12348                 }
12349         }
12350
12351         return true;
12352 }
12353
12354 static void
12355 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12356 {
12357         struct drm_crtc_state tmp_state;
12358         struct intel_crtc_scaler_state scaler_state;
12359         struct intel_dpll_hw_state dpll_hw_state;
12360         struct intel_shared_dpll *shared_dpll;
12361         uint32_t ddi_pll_sel;
12362         bool force_thru;
12363
12364         /* FIXME: before the switch to atomic started, a new pipe_config was
12365          * kzalloc'd. Code that depends on any field being zero should be
12366          * fixed, so that the crtc_state can be safely duplicated. For now,
12367          * only fields that are know to not cause problems are preserved. */
12368
12369         tmp_state = crtc_state->base;
12370         scaler_state = crtc_state->scaler_state;
12371         shared_dpll = crtc_state->shared_dpll;
12372         dpll_hw_state = crtc_state->dpll_hw_state;
12373         ddi_pll_sel = crtc_state->ddi_pll_sel;
12374         force_thru = crtc_state->pch_pfit.force_thru;
12375
12376         memset(crtc_state, 0, sizeof *crtc_state);
12377
12378         crtc_state->base = tmp_state;
12379         crtc_state->scaler_state = scaler_state;
12380         crtc_state->shared_dpll = shared_dpll;
12381         crtc_state->dpll_hw_state = dpll_hw_state;
12382         crtc_state->ddi_pll_sel = ddi_pll_sel;
12383         crtc_state->pch_pfit.force_thru = force_thru;
12384 }
12385
12386 static int
12387 intel_modeset_pipe_config(struct drm_crtc *crtc,
12388                           struct intel_crtc_state *pipe_config)
12389 {
12390         struct drm_atomic_state *state = pipe_config->base.state;
12391         struct intel_encoder *encoder;
12392         struct drm_connector *connector;
12393         struct drm_connector_state *connector_state;
12394         int base_bpp, ret = -EINVAL;
12395         int i;
12396         bool retry = true;
12397
12398         clear_intel_crtc_state(pipe_config);
12399
12400         pipe_config->cpu_transcoder =
12401                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12402
12403         /*
12404          * Sanitize sync polarity flags based on requested ones. If neither
12405          * positive or negative polarity is requested, treat this as meaning
12406          * negative polarity.
12407          */
12408         if (!(pipe_config->base.adjusted_mode.flags &
12409               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12410                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12411
12412         if (!(pipe_config->base.adjusted_mode.flags &
12413               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12414                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12415
12416         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12417                                              pipe_config);
12418         if (base_bpp < 0)
12419                 goto fail;
12420
12421         /*
12422          * Determine the real pipe dimensions. Note that stereo modes can
12423          * increase the actual pipe size due to the frame doubling and
12424          * insertion of additional space for blanks between the frame. This
12425          * is stored in the crtc timings. We use the requested mode to do this
12426          * computation to clearly distinguish it from the adjusted mode, which
12427          * can be changed by the connectors in the below retry loop.
12428          */
12429         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12430                                &pipe_config->pipe_src_w,
12431                                &pipe_config->pipe_src_h);
12432
12433         for_each_connector_in_state(state, connector, connector_state, i) {
12434                 if (connector_state->crtc != crtc)
12435                         continue;
12436
12437                 encoder = to_intel_encoder(connector_state->best_encoder);
12438
12439                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12440                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12441                         goto fail;
12442                 }
12443
12444                 /*
12445                  * Determine output_types before calling the .compute_config()
12446                  * hooks so that the hooks can use this information safely.
12447                  */
12448                 pipe_config->output_types |= 1 << encoder->type;
12449         }
12450
12451 encoder_retry:
12452         /* Ensure the port clock defaults are reset when retrying. */
12453         pipe_config->port_clock = 0;
12454         pipe_config->pixel_multiplier = 1;
12455
12456         /* Fill in default crtc timings, allow encoders to overwrite them. */
12457         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12458                               CRTC_STEREO_DOUBLE);
12459
12460         /* Pass our mode to the connectors and the CRTC to give them a chance to
12461          * adjust it according to limitations or connector properties, and also
12462          * a chance to reject the mode entirely.
12463          */
12464         for_each_connector_in_state(state, connector, connector_state, i) {
12465                 if (connector_state->crtc != crtc)
12466                         continue;
12467
12468                 encoder = to_intel_encoder(connector_state->best_encoder);
12469
12470                 if (!(encoder->compute_config(encoder, pipe_config))) {
12471                         DRM_DEBUG_KMS("Encoder config failure\n");
12472                         goto fail;
12473                 }
12474         }
12475
12476         /* Set default port clock if not overwritten by the encoder. Needs to be
12477          * done afterwards in case the encoder adjusts the mode. */
12478         if (!pipe_config->port_clock)
12479                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12480                         * pipe_config->pixel_multiplier;
12481
12482         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12483         if (ret < 0) {
12484                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12485                 goto fail;
12486         }
12487
12488         if (ret == RETRY) {
12489                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12490                         ret = -EINVAL;
12491                         goto fail;
12492                 }
12493
12494                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12495                 retry = false;
12496                 goto encoder_retry;
12497         }
12498
12499         /* Dithering seems to not pass-through bits correctly when it should, so
12500          * only enable it on 6bpc panels. */
12501         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12502         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12503                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12504
12505 fail:
12506         return ret;
12507 }
12508
12509 static void
12510 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12511 {
12512         struct drm_crtc *crtc;
12513         struct drm_crtc_state *crtc_state;
12514         int i;
12515
12516         /* Double check state. */
12517         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12518                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12519
12520                 /* Update hwmode for vblank functions */
12521                 if (crtc->state->active)
12522                         crtc->hwmode = crtc->state->adjusted_mode;
12523                 else
12524                         crtc->hwmode.crtc_clock = 0;
12525
12526                 /*
12527                  * Update legacy state to satisfy fbc code. This can
12528                  * be removed when fbc uses the atomic state.
12529                  */
12530                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12531                         struct drm_plane_state *plane_state = crtc->primary->state;
12532
12533                         crtc->primary->fb = plane_state->fb;
12534                         crtc->x = plane_state->src_x >> 16;
12535                         crtc->y = plane_state->src_y >> 16;
12536                 }
12537         }
12538 }
12539
12540 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12541 {
12542         int diff;
12543
12544         if (clock1 == clock2)
12545                 return true;
12546
12547         if (!clock1 || !clock2)
12548                 return false;
12549
12550         diff = abs(clock1 - clock2);
12551
12552         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12553                 return true;
12554
12555         return false;
12556 }
12557
12558 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12559         list_for_each_entry((intel_crtc), \
12560                             &(dev)->mode_config.crtc_list, \
12561                             base.head) \
12562                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12563
12564 static bool
12565 intel_compare_m_n(unsigned int m, unsigned int n,
12566                   unsigned int m2, unsigned int n2,
12567                   bool exact)
12568 {
12569         if (m == m2 && n == n2)
12570                 return true;
12571
12572         if (exact || !m || !n || !m2 || !n2)
12573                 return false;
12574
12575         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12576
12577         if (n > n2) {
12578                 while (n > n2) {
12579                         m2 <<= 1;
12580                         n2 <<= 1;
12581                 }
12582         } else if (n < n2) {
12583                 while (n < n2) {
12584                         m <<= 1;
12585                         n <<= 1;
12586                 }
12587         }
12588
12589         if (n != n2)
12590                 return false;
12591
12592         return intel_fuzzy_clock_check(m, m2);
12593 }
12594
12595 static bool
12596 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12597                        struct intel_link_m_n *m2_n2,
12598                        bool adjust)
12599 {
12600         if (m_n->tu == m2_n2->tu &&
12601             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12602                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12603             intel_compare_m_n(m_n->link_m, m_n->link_n,
12604                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12605                 if (adjust)
12606                         *m2_n2 = *m_n;
12607
12608                 return true;
12609         }
12610
12611         return false;
12612 }
12613
12614 static bool
12615 intel_pipe_config_compare(struct drm_device *dev,
12616                           struct intel_crtc_state *current_config,
12617                           struct intel_crtc_state *pipe_config,
12618                           bool adjust)
12619 {
12620         bool ret = true;
12621
12622 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12623         do { \
12624                 if (!adjust) \
12625                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12626                 else \
12627                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12628         } while (0)
12629
12630 #define PIPE_CONF_CHECK_X(name) \
12631         if (current_config->name != pipe_config->name) { \
12632                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12633                           "(expected 0x%08x, found 0x%08x)\n", \
12634                           current_config->name, \
12635                           pipe_config->name); \
12636                 ret = false; \
12637         }
12638
12639 #define PIPE_CONF_CHECK_I(name) \
12640         if (current_config->name != pipe_config->name) { \
12641                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12642                           "(expected %i, found %i)\n", \
12643                           current_config->name, \
12644                           pipe_config->name); \
12645                 ret = false; \
12646         }
12647
12648 #define PIPE_CONF_CHECK_P(name) \
12649         if (current_config->name != pipe_config->name) { \
12650                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12651                           "(expected %p, found %p)\n", \
12652                           current_config->name, \
12653                           pipe_config->name); \
12654                 ret = false; \
12655         }
12656
12657 #define PIPE_CONF_CHECK_M_N(name) \
12658         if (!intel_compare_link_m_n(&current_config->name, \
12659                                     &pipe_config->name,\
12660                                     adjust)) { \
12661                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12662                           "(expected tu %i gmch %i/%i link %i/%i, " \
12663                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12664                           current_config->name.tu, \
12665                           current_config->name.gmch_m, \
12666                           current_config->name.gmch_n, \
12667                           current_config->name.link_m, \
12668                           current_config->name.link_n, \
12669                           pipe_config->name.tu, \
12670                           pipe_config->name.gmch_m, \
12671                           pipe_config->name.gmch_n, \
12672                           pipe_config->name.link_m, \
12673                           pipe_config->name.link_n); \
12674                 ret = false; \
12675         }
12676
12677 /* This is required for BDW+ where there is only one set of registers for
12678  * switching between high and low RR.
12679  * This macro can be used whenever a comparison has to be made between one
12680  * hw state and multiple sw state variables.
12681  */
12682 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12683         if (!intel_compare_link_m_n(&current_config->name, \
12684                                     &pipe_config->name, adjust) && \
12685             !intel_compare_link_m_n(&current_config->alt_name, \
12686                                     &pipe_config->name, adjust)) { \
12687                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12688                           "(expected tu %i gmch %i/%i link %i/%i, " \
12689                           "or tu %i gmch %i/%i link %i/%i, " \
12690                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12691                           current_config->name.tu, \
12692                           current_config->name.gmch_m, \
12693                           current_config->name.gmch_n, \
12694                           current_config->name.link_m, \
12695                           current_config->name.link_n, \
12696                           current_config->alt_name.tu, \
12697                           current_config->alt_name.gmch_m, \
12698                           current_config->alt_name.gmch_n, \
12699                           current_config->alt_name.link_m, \
12700                           current_config->alt_name.link_n, \
12701                           pipe_config->name.tu, \
12702                           pipe_config->name.gmch_m, \
12703                           pipe_config->name.gmch_n, \
12704                           pipe_config->name.link_m, \
12705                           pipe_config->name.link_n); \
12706                 ret = false; \
12707         }
12708
12709 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12710         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12711                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12712                           "(expected %i, found %i)\n", \
12713                           current_config->name & (mask), \
12714                           pipe_config->name & (mask)); \
12715                 ret = false; \
12716         }
12717
12718 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12719         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12720                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12721                           "(expected %i, found %i)\n", \
12722                           current_config->name, \
12723                           pipe_config->name); \
12724                 ret = false; \
12725         }
12726
12727 #define PIPE_CONF_QUIRK(quirk)  \
12728         ((current_config->quirks | pipe_config->quirks) & (quirk))
12729
12730         PIPE_CONF_CHECK_I(cpu_transcoder);
12731
12732         PIPE_CONF_CHECK_I(has_pch_encoder);
12733         PIPE_CONF_CHECK_I(fdi_lanes);
12734         PIPE_CONF_CHECK_M_N(fdi_m_n);
12735
12736         PIPE_CONF_CHECK_I(lane_count);
12737         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12738
12739         if (INTEL_INFO(dev)->gen < 8) {
12740                 PIPE_CONF_CHECK_M_N(dp_m_n);
12741
12742                 if (current_config->has_drrs)
12743                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12744         } else
12745                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12746
12747         PIPE_CONF_CHECK_X(output_types);
12748
12749         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12750         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12751         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12752         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12753         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12754         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12755
12756         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12757         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12758         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12759         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12760         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12761         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12762
12763         PIPE_CONF_CHECK_I(pixel_multiplier);
12764         PIPE_CONF_CHECK_I(has_hdmi_sink);
12765         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12766             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12767                 PIPE_CONF_CHECK_I(limited_color_range);
12768         PIPE_CONF_CHECK_I(has_infoframe);
12769
12770         PIPE_CONF_CHECK_I(has_audio);
12771
12772         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12773                               DRM_MODE_FLAG_INTERLACE);
12774
12775         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12776                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12777                                       DRM_MODE_FLAG_PHSYNC);
12778                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12779                                       DRM_MODE_FLAG_NHSYNC);
12780                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12781                                       DRM_MODE_FLAG_PVSYNC);
12782                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12783                                       DRM_MODE_FLAG_NVSYNC);
12784         }
12785
12786         PIPE_CONF_CHECK_X(gmch_pfit.control);
12787         /* pfit ratios are autocomputed by the hw on gen4+ */
12788         if (INTEL_INFO(dev)->gen < 4)
12789                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12790         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12791
12792         if (!adjust) {
12793                 PIPE_CONF_CHECK_I(pipe_src_w);
12794                 PIPE_CONF_CHECK_I(pipe_src_h);
12795
12796                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12797                 if (current_config->pch_pfit.enabled) {
12798                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12799                         PIPE_CONF_CHECK_X(pch_pfit.size);
12800                 }
12801
12802                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12803         }
12804
12805         /* BDW+ don't expose a synchronous way to read the state */
12806         if (IS_HASWELL(dev))
12807                 PIPE_CONF_CHECK_I(ips_enabled);
12808
12809         PIPE_CONF_CHECK_I(double_wide);
12810
12811         PIPE_CONF_CHECK_X(ddi_pll_sel);
12812
12813         PIPE_CONF_CHECK_P(shared_dpll);
12814         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12815         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12816         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12817         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12818         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12819         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12820         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12821         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12822         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12823
12824         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12825         PIPE_CONF_CHECK_X(dsi_pll.div);
12826
12827         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12828                 PIPE_CONF_CHECK_I(pipe_bpp);
12829
12830         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12831         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12832
12833 #undef PIPE_CONF_CHECK_X
12834 #undef PIPE_CONF_CHECK_I
12835 #undef PIPE_CONF_CHECK_P
12836 #undef PIPE_CONF_CHECK_FLAGS
12837 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12838 #undef PIPE_CONF_QUIRK
12839 #undef INTEL_ERR_OR_DBG_KMS
12840
12841         return ret;
12842 }
12843
12844 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12845                                            const struct intel_crtc_state *pipe_config)
12846 {
12847         if (pipe_config->has_pch_encoder) {
12848                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12849                                                             &pipe_config->fdi_m_n);
12850                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12851
12852                 /*
12853                  * FDI already provided one idea for the dotclock.
12854                  * Yell if the encoder disagrees.
12855                  */
12856                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12857                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12858                      fdi_dotclock, dotclock);
12859         }
12860 }
12861
12862 static void verify_wm_state(struct drm_crtc *crtc,
12863                             struct drm_crtc_state *new_state)
12864 {
12865         struct drm_device *dev = crtc->dev;
12866         struct drm_i915_private *dev_priv = to_i915(dev);
12867         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12868         struct skl_ddb_entry *hw_entry, *sw_entry;
12869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12870         const enum pipe pipe = intel_crtc->pipe;
12871         int plane;
12872
12873         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12874                 return;
12875
12876         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12877         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12878
12879         /* planes */
12880         for_each_plane(dev_priv, pipe, plane) {
12881                 hw_entry = &hw_ddb.plane[pipe][plane];
12882                 sw_entry = &sw_ddb->plane[pipe][plane];
12883
12884                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12885                         continue;
12886
12887                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12888                           "(expected (%u,%u), found (%u,%u))\n",
12889                           pipe_name(pipe), plane + 1,
12890                           sw_entry->start, sw_entry->end,
12891                           hw_entry->start, hw_entry->end);
12892         }
12893
12894         /* cursor */
12895         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12896         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12897
12898         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12899                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12900                           "(expected (%u,%u), found (%u,%u))\n",
12901                           pipe_name(pipe),
12902                           sw_entry->start, sw_entry->end,
12903                           hw_entry->start, hw_entry->end);
12904         }
12905 }
12906
12907 static void
12908 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12909 {
12910         struct drm_connector *connector;
12911
12912         drm_for_each_connector(connector, dev) {
12913                 struct drm_encoder *encoder = connector->encoder;
12914                 struct drm_connector_state *state = connector->state;
12915
12916                 if (state->crtc != crtc)
12917                         continue;
12918
12919                 intel_connector_verify_state(to_intel_connector(connector));
12920
12921                 I915_STATE_WARN(state->best_encoder != encoder,
12922                      "connector's atomic encoder doesn't match legacy encoder\n");
12923         }
12924 }
12925
12926 static void
12927 verify_encoder_state(struct drm_device *dev)
12928 {
12929         struct intel_encoder *encoder;
12930         struct intel_connector *connector;
12931
12932         for_each_intel_encoder(dev, encoder) {
12933                 bool enabled = false;
12934                 enum pipe pipe;
12935
12936                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12937                               encoder->base.base.id,
12938                               encoder->base.name);
12939
12940                 for_each_intel_connector(dev, connector) {
12941                         if (connector->base.state->best_encoder != &encoder->base)
12942                                 continue;
12943                         enabled = true;
12944
12945                         I915_STATE_WARN(connector->base.state->crtc !=
12946                                         encoder->base.crtc,
12947                              "connector's crtc doesn't match encoder crtc\n");
12948                 }
12949
12950                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12951                      "encoder's enabled state mismatch "
12952                      "(expected %i, found %i)\n",
12953                      !!encoder->base.crtc, enabled);
12954
12955                 if (!encoder->base.crtc) {
12956                         bool active;
12957
12958                         active = encoder->get_hw_state(encoder, &pipe);
12959                         I915_STATE_WARN(active,
12960                              "encoder detached but still enabled on pipe %c.\n",
12961                              pipe_name(pipe));
12962                 }
12963         }
12964 }
12965
12966 static void
12967 verify_crtc_state(struct drm_crtc *crtc,
12968                   struct drm_crtc_state *old_crtc_state,
12969                   struct drm_crtc_state *new_crtc_state)
12970 {
12971         struct drm_device *dev = crtc->dev;
12972         struct drm_i915_private *dev_priv = to_i915(dev);
12973         struct intel_encoder *encoder;
12974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12975         struct intel_crtc_state *pipe_config, *sw_config;
12976         struct drm_atomic_state *old_state;
12977         bool active;
12978
12979         old_state = old_crtc_state->state;
12980         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12981         pipe_config = to_intel_crtc_state(old_crtc_state);
12982         memset(pipe_config, 0, sizeof(*pipe_config));
12983         pipe_config->base.crtc = crtc;
12984         pipe_config->base.state = old_state;
12985
12986         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12987
12988         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12989
12990         /* hw state is inconsistent with the pipe quirk */
12991         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12992             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12993                 active = new_crtc_state->active;
12994
12995         I915_STATE_WARN(new_crtc_state->active != active,
12996              "crtc active state doesn't match with hw state "
12997              "(expected %i, found %i)\n", new_crtc_state->active, active);
12998
12999         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13000              "transitional active state does not match atomic hw state "
13001              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13002
13003         for_each_encoder_on_crtc(dev, crtc, encoder) {
13004                 enum pipe pipe;
13005
13006                 active = encoder->get_hw_state(encoder, &pipe);
13007                 I915_STATE_WARN(active != new_crtc_state->active,
13008                         "[ENCODER:%i] active %i with crtc active %i\n",
13009                         encoder->base.base.id, active, new_crtc_state->active);
13010
13011                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13012                                 "Encoder connected to wrong pipe %c\n",
13013                                 pipe_name(pipe));
13014
13015                 if (active) {
13016                         pipe_config->output_types |= 1 << encoder->type;
13017                         encoder->get_config(encoder, pipe_config);
13018                 }
13019         }
13020
13021         if (!new_crtc_state->active)
13022                 return;
13023
13024         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13025
13026         sw_config = to_intel_crtc_state(crtc->state);
13027         if (!intel_pipe_config_compare(dev, sw_config,
13028                                        pipe_config, false)) {
13029                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13030                 intel_dump_pipe_config(intel_crtc, pipe_config,
13031                                        "[hw state]");
13032                 intel_dump_pipe_config(intel_crtc, sw_config,
13033                                        "[sw state]");
13034         }
13035 }
13036
13037 static void
13038 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13039                          struct intel_shared_dpll *pll,
13040                          struct drm_crtc *crtc,
13041                          struct drm_crtc_state *new_state)
13042 {
13043         struct intel_dpll_hw_state dpll_hw_state;
13044         unsigned crtc_mask;
13045         bool active;
13046
13047         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13048
13049         DRM_DEBUG_KMS("%s\n", pll->name);
13050
13051         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13052
13053         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13054                 I915_STATE_WARN(!pll->on && pll->active_mask,
13055                      "pll in active use but not on in sw tracking\n");
13056                 I915_STATE_WARN(pll->on && !pll->active_mask,
13057                      "pll is on but not used by any active crtc\n");
13058                 I915_STATE_WARN(pll->on != active,
13059                      "pll on state mismatch (expected %i, found %i)\n",
13060                      pll->on, active);
13061         }
13062
13063         if (!crtc) {
13064                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13065                                 "more active pll users than references: %x vs %x\n",
13066                                 pll->active_mask, pll->config.crtc_mask);
13067
13068                 return;
13069         }
13070
13071         crtc_mask = 1 << drm_crtc_index(crtc);
13072
13073         if (new_state->active)
13074                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13075                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13076                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13077         else
13078                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13079                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13080                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13081
13082         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13083                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13084                         crtc_mask, pll->config.crtc_mask);
13085
13086         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13087                                           &dpll_hw_state,
13088                                           sizeof(dpll_hw_state)),
13089                         "pll hw state mismatch\n");
13090 }
13091
13092 static void
13093 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13094                          struct drm_crtc_state *old_crtc_state,
13095                          struct drm_crtc_state *new_crtc_state)
13096 {
13097         struct drm_i915_private *dev_priv = to_i915(dev);
13098         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13099         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13100
13101         if (new_state->shared_dpll)
13102                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13103
13104         if (old_state->shared_dpll &&
13105             old_state->shared_dpll != new_state->shared_dpll) {
13106                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13107                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13108
13109                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13110                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13111                                 pipe_name(drm_crtc_index(crtc)));
13112                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13113                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13114                                 pipe_name(drm_crtc_index(crtc)));
13115         }
13116 }
13117
13118 static void
13119 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13120                          struct drm_crtc_state *old_state,
13121                          struct drm_crtc_state *new_state)
13122 {
13123         if (!needs_modeset(new_state) &&
13124             !to_intel_crtc_state(new_state)->update_pipe)
13125                 return;
13126
13127         verify_wm_state(crtc, new_state);
13128         verify_connector_state(crtc->dev, crtc);
13129         verify_crtc_state(crtc, old_state, new_state);
13130         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13131 }
13132
13133 static void
13134 verify_disabled_dpll_state(struct drm_device *dev)
13135 {
13136         struct drm_i915_private *dev_priv = to_i915(dev);
13137         int i;
13138
13139         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13140                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13141 }
13142
13143 static void
13144 intel_modeset_verify_disabled(struct drm_device *dev)
13145 {
13146         verify_encoder_state(dev);
13147         verify_connector_state(dev, NULL);
13148         verify_disabled_dpll_state(dev);
13149 }
13150
13151 static void update_scanline_offset(struct intel_crtc *crtc)
13152 {
13153         struct drm_device *dev = crtc->base.dev;
13154
13155         /*
13156          * The scanline counter increments at the leading edge of hsync.
13157          *
13158          * On most platforms it starts counting from vtotal-1 on the
13159          * first active line. That means the scanline counter value is
13160          * always one less than what we would expect. Ie. just after
13161          * start of vblank, which also occurs at start of hsync (on the
13162          * last active line), the scanline counter will read vblank_start-1.
13163          *
13164          * On gen2 the scanline counter starts counting from 1 instead
13165          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13166          * to keep the value positive), instead of adding one.
13167          *
13168          * On HSW+ the behaviour of the scanline counter depends on the output
13169          * type. For DP ports it behaves like most other platforms, but on HDMI
13170          * there's an extra 1 line difference. So we need to add two instead of
13171          * one to the value.
13172          */
13173         if (IS_GEN2(dev)) {
13174                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13175                 int vtotal;
13176
13177                 vtotal = adjusted_mode->crtc_vtotal;
13178                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13179                         vtotal /= 2;
13180
13181                 crtc->scanline_offset = vtotal - 1;
13182         } else if (HAS_DDI(dev) &&
13183                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13184                 crtc->scanline_offset = 2;
13185         } else
13186                 crtc->scanline_offset = 1;
13187 }
13188
13189 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13190 {
13191         struct drm_device *dev = state->dev;
13192         struct drm_i915_private *dev_priv = to_i915(dev);
13193         struct intel_shared_dpll_config *shared_dpll = NULL;
13194         struct drm_crtc *crtc;
13195         struct drm_crtc_state *crtc_state;
13196         int i;
13197
13198         if (!dev_priv->display.crtc_compute_clock)
13199                 return;
13200
13201         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13202                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13203                 struct intel_shared_dpll *old_dpll =
13204                         to_intel_crtc_state(crtc->state)->shared_dpll;
13205
13206                 if (!needs_modeset(crtc_state))
13207                         continue;
13208
13209                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13210
13211                 if (!old_dpll)
13212                         continue;
13213
13214                 if (!shared_dpll)
13215                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13216
13217                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13218         }
13219 }
13220
13221 /*
13222  * This implements the workaround described in the "notes" section of the mode
13223  * set sequence documentation. When going from no pipes or single pipe to
13224  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13225  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13226  */
13227 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13228 {
13229         struct drm_crtc_state *crtc_state;
13230         struct intel_crtc *intel_crtc;
13231         struct drm_crtc *crtc;
13232         struct intel_crtc_state *first_crtc_state = NULL;
13233         struct intel_crtc_state *other_crtc_state = NULL;
13234         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13235         int i;
13236
13237         /* look at all crtc's that are going to be enabled in during modeset */
13238         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13239                 intel_crtc = to_intel_crtc(crtc);
13240
13241                 if (!crtc_state->active || !needs_modeset(crtc_state))
13242                         continue;
13243
13244                 if (first_crtc_state) {
13245                         other_crtc_state = to_intel_crtc_state(crtc_state);
13246                         break;
13247                 } else {
13248                         first_crtc_state = to_intel_crtc_state(crtc_state);
13249                         first_pipe = intel_crtc->pipe;
13250                 }
13251         }
13252
13253         /* No workaround needed? */
13254         if (!first_crtc_state)
13255                 return 0;
13256
13257         /* w/a possibly needed, check how many crtc's are already enabled. */
13258         for_each_intel_crtc(state->dev, intel_crtc) {
13259                 struct intel_crtc_state *pipe_config;
13260
13261                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13262                 if (IS_ERR(pipe_config))
13263                         return PTR_ERR(pipe_config);
13264
13265                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13266
13267                 if (!pipe_config->base.active ||
13268                     needs_modeset(&pipe_config->base))
13269                         continue;
13270
13271                 /* 2 or more enabled crtcs means no need for w/a */
13272                 if (enabled_pipe != INVALID_PIPE)
13273                         return 0;
13274
13275                 enabled_pipe = intel_crtc->pipe;
13276         }
13277
13278         if (enabled_pipe != INVALID_PIPE)
13279                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13280         else if (other_crtc_state)
13281                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13282
13283         return 0;
13284 }
13285
13286 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13287 {
13288         struct drm_crtc *crtc;
13289         struct drm_crtc_state *crtc_state;
13290         int ret = 0;
13291
13292         /* add all active pipes to the state */
13293         for_each_crtc(state->dev, crtc) {
13294                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13295                 if (IS_ERR(crtc_state))
13296                         return PTR_ERR(crtc_state);
13297
13298                 if (!crtc_state->active || needs_modeset(crtc_state))
13299                         continue;
13300
13301                 crtc_state->mode_changed = true;
13302
13303                 ret = drm_atomic_add_affected_connectors(state, crtc);
13304                 if (ret)
13305                         break;
13306
13307                 ret = drm_atomic_add_affected_planes(state, crtc);
13308                 if (ret)
13309                         break;
13310         }
13311
13312         return ret;
13313 }
13314
13315 static int intel_modeset_checks(struct drm_atomic_state *state)
13316 {
13317         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13318         struct drm_i915_private *dev_priv = to_i915(state->dev);
13319         struct drm_crtc *crtc;
13320         struct drm_crtc_state *crtc_state;
13321         int ret = 0, i;
13322
13323         if (!check_digital_port_conflicts(state)) {
13324                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13325                 return -EINVAL;
13326         }
13327
13328         intel_state->modeset = true;
13329         intel_state->active_crtcs = dev_priv->active_crtcs;
13330
13331         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13332                 if (crtc_state->active)
13333                         intel_state->active_crtcs |= 1 << i;
13334                 else
13335                         intel_state->active_crtcs &= ~(1 << i);
13336
13337                 if (crtc_state->active != crtc->state->active)
13338                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13339         }
13340
13341         /*
13342          * See if the config requires any additional preparation, e.g.
13343          * to adjust global state with pipes off.  We need to do this
13344          * here so we can get the modeset_pipe updated config for the new
13345          * mode set on this crtc.  For other crtcs we need to use the
13346          * adjusted_mode bits in the crtc directly.
13347          */
13348         if (dev_priv->display.modeset_calc_cdclk) {
13349                 if (!intel_state->cdclk_pll_vco)
13350                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13351                 if (!intel_state->cdclk_pll_vco)
13352                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13353
13354                 ret = dev_priv->display.modeset_calc_cdclk(state);
13355                 if (ret < 0)
13356                         return ret;
13357
13358                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13359                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13360                         ret = intel_modeset_all_pipes(state);
13361
13362                 if (ret < 0)
13363                         return ret;
13364
13365                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13366                               intel_state->cdclk, intel_state->dev_cdclk);
13367         } else
13368                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13369
13370         intel_modeset_clear_plls(state);
13371
13372         if (IS_HASWELL(dev_priv))
13373                 return haswell_mode_set_planes_workaround(state);
13374
13375         return 0;
13376 }
13377
13378 /*
13379  * Handle calculation of various watermark data at the end of the atomic check
13380  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13381  * handlers to ensure that all derived state has been updated.
13382  */
13383 static int calc_watermark_data(struct drm_atomic_state *state)
13384 {
13385         struct drm_device *dev = state->dev;
13386         struct drm_i915_private *dev_priv = to_i915(dev);
13387
13388         /* Is there platform-specific watermark information to calculate? */
13389         if (dev_priv->display.compute_global_watermarks)
13390                 return dev_priv->display.compute_global_watermarks(state);
13391
13392         return 0;
13393 }
13394
13395 /**
13396  * intel_atomic_check - validate state object
13397  * @dev: drm device
13398  * @state: state to validate
13399  */
13400 static int intel_atomic_check(struct drm_device *dev,
13401                               struct drm_atomic_state *state)
13402 {
13403         struct drm_i915_private *dev_priv = to_i915(dev);
13404         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13405         struct drm_crtc *crtc;
13406         struct drm_crtc_state *crtc_state;
13407         int ret, i;
13408         bool any_ms = false;
13409
13410         ret = drm_atomic_helper_check_modeset(dev, state);
13411         if (ret)
13412                 return ret;
13413
13414         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13415                 struct intel_crtc_state *pipe_config =
13416                         to_intel_crtc_state(crtc_state);
13417
13418                 /* Catch I915_MODE_FLAG_INHERITED */
13419                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13420                         crtc_state->mode_changed = true;
13421
13422                 if (!needs_modeset(crtc_state))
13423                         continue;
13424
13425                 if (!crtc_state->enable) {
13426                         any_ms = true;
13427                         continue;
13428                 }
13429
13430                 /* FIXME: For only active_changed we shouldn't need to do any
13431                  * state recomputation at all. */
13432
13433                 ret = drm_atomic_add_affected_connectors(state, crtc);
13434                 if (ret)
13435                         return ret;
13436
13437                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13438                 if (ret) {
13439                         intel_dump_pipe_config(to_intel_crtc(crtc),
13440                                                pipe_config, "[failed]");
13441                         return ret;
13442                 }
13443
13444                 if (i915.fastboot &&
13445                     intel_pipe_config_compare(dev,
13446                                         to_intel_crtc_state(crtc->state),
13447                                         pipe_config, true)) {
13448                         crtc_state->mode_changed = false;
13449                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13450                 }
13451
13452                 if (needs_modeset(crtc_state))
13453                         any_ms = true;
13454
13455                 ret = drm_atomic_add_affected_planes(state, crtc);
13456                 if (ret)
13457                         return ret;
13458
13459                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13460                                        needs_modeset(crtc_state) ?
13461                                        "[modeset]" : "[fastset]");
13462         }
13463
13464         if (any_ms) {
13465                 ret = intel_modeset_checks(state);
13466
13467                 if (ret)
13468                         return ret;
13469         } else
13470                 intel_state->cdclk = dev_priv->cdclk_freq;
13471
13472         ret = drm_atomic_helper_check_planes(dev, state);
13473         if (ret)
13474                 return ret;
13475
13476         intel_fbc_choose_crtc(dev_priv, state);
13477         return calc_watermark_data(state);
13478 }
13479
13480 static int intel_atomic_prepare_commit(struct drm_device *dev,
13481                                        struct drm_atomic_state *state,
13482                                        bool nonblock)
13483 {
13484         struct drm_i915_private *dev_priv = to_i915(dev);
13485         struct drm_plane_state *plane_state;
13486         struct drm_crtc_state *crtc_state;
13487         struct drm_plane *plane;
13488         struct drm_crtc *crtc;
13489         int i, ret;
13490
13491         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13492                 if (state->legacy_cursor_update)
13493                         continue;
13494
13495                 ret = intel_crtc_wait_for_pending_flips(crtc);
13496                 if (ret)
13497                         return ret;
13498
13499                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13500                         flush_workqueue(dev_priv->wq);
13501         }
13502
13503         ret = mutex_lock_interruptible(&dev->struct_mutex);
13504         if (ret)
13505                 return ret;
13506
13507         ret = drm_atomic_helper_prepare_planes(dev, state);
13508         mutex_unlock(&dev->struct_mutex);
13509
13510         if (!ret && !nonblock) {
13511                 for_each_plane_in_state(state, plane, plane_state, i) {
13512                         struct intel_plane_state *intel_plane_state =
13513                                 to_intel_plane_state(plane_state);
13514
13515                         if (!intel_plane_state->wait_req)
13516                                 continue;
13517
13518                         ret = __i915_wait_request(intel_plane_state->wait_req,
13519                                                   true, NULL, NULL);
13520                         if (ret) {
13521                                 /* Any hang should be swallowed by the wait */
13522                                 WARN_ON(ret == -EIO);
13523                                 mutex_lock(&dev->struct_mutex);
13524                                 drm_atomic_helper_cleanup_planes(dev, state);
13525                                 mutex_unlock(&dev->struct_mutex);
13526                                 break;
13527                         }
13528                 }
13529         }
13530
13531         return ret;
13532 }
13533
13534 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13535 {
13536         struct drm_device *dev = crtc->base.dev;
13537
13538         if (!dev->max_vblank_count)
13539                 return drm_accurate_vblank_count(&crtc->base);
13540
13541         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13542 }
13543
13544 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13545                                           struct drm_i915_private *dev_priv,
13546                                           unsigned crtc_mask)
13547 {
13548         unsigned last_vblank_count[I915_MAX_PIPES];
13549         enum pipe pipe;
13550         int ret;
13551
13552         if (!crtc_mask)
13553                 return;
13554
13555         for_each_pipe(dev_priv, pipe) {
13556                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13557
13558                 if (!((1 << pipe) & crtc_mask))
13559                         continue;
13560
13561                 ret = drm_crtc_vblank_get(crtc);
13562                 if (WARN_ON(ret != 0)) {
13563                         crtc_mask &= ~(1 << pipe);
13564                         continue;
13565                 }
13566
13567                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13568         }
13569
13570         for_each_pipe(dev_priv, pipe) {
13571                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13572                 long lret;
13573
13574                 if (!((1 << pipe) & crtc_mask))
13575                         continue;
13576
13577                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13578                                 last_vblank_count[pipe] !=
13579                                         drm_crtc_vblank_count(crtc),
13580                                 msecs_to_jiffies(50));
13581
13582                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13583
13584                 drm_crtc_vblank_put(crtc);
13585         }
13586 }
13587
13588 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13589 {
13590         /* fb updated, need to unpin old fb */
13591         if (crtc_state->fb_changed)
13592                 return true;
13593
13594         /* wm changes, need vblank before final wm's */
13595         if (crtc_state->update_wm_post)
13596                 return true;
13597
13598         /*
13599          * cxsr is re-enabled after vblank.
13600          * This is already handled by crtc_state->update_wm_post,
13601          * but added for clarity.
13602          */
13603         if (crtc_state->disable_cxsr)
13604                 return true;
13605
13606         return false;
13607 }
13608
13609 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13610 {
13611         struct drm_device *dev = state->dev;
13612         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13613         struct drm_i915_private *dev_priv = to_i915(dev);
13614         struct drm_crtc_state *old_crtc_state;
13615         struct drm_crtc *crtc;
13616         struct intel_crtc_state *intel_cstate;
13617         struct drm_plane *plane;
13618         struct drm_plane_state *plane_state;
13619         bool hw_check = intel_state->modeset;
13620         unsigned long put_domains[I915_MAX_PIPES] = {};
13621         unsigned crtc_vblank_mask = 0;
13622         int i, ret;
13623
13624         for_each_plane_in_state(state, plane, plane_state, i) {
13625                 struct intel_plane_state *intel_plane_state =
13626                         to_intel_plane_state(plane_state);
13627
13628                 if (!intel_plane_state->wait_req)
13629                         continue;
13630
13631                 ret = __i915_wait_request(intel_plane_state->wait_req,
13632                                           true, NULL, NULL);
13633                 /* EIO should be eaten, and we can't get interrupted in the
13634                  * worker, and blocking commits have waited already. */
13635                 WARN_ON(ret);
13636         }
13637
13638         drm_atomic_helper_wait_for_dependencies(state);
13639
13640         if (intel_state->modeset) {
13641                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13642                        sizeof(intel_state->min_pixclk));
13643                 dev_priv->active_crtcs = intel_state->active_crtcs;
13644                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13645
13646                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13647         }
13648
13649         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13650                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13651
13652                 if (needs_modeset(crtc->state) ||
13653                     to_intel_crtc_state(crtc->state)->update_pipe) {
13654                         hw_check = true;
13655
13656                         put_domains[to_intel_crtc(crtc)->pipe] =
13657                                 modeset_get_crtc_power_domains(crtc,
13658                                         to_intel_crtc_state(crtc->state));
13659                 }
13660
13661                 if (!needs_modeset(crtc->state))
13662                         continue;
13663
13664                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13665
13666                 if (old_crtc_state->active) {
13667                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13668                         dev_priv->display.crtc_disable(crtc);
13669                         intel_crtc->active = false;
13670                         intel_fbc_disable(intel_crtc);
13671                         intel_disable_shared_dpll(intel_crtc);
13672
13673                         /*
13674                          * Underruns don't always raise
13675                          * interrupts, so check manually.
13676                          */
13677                         intel_check_cpu_fifo_underruns(dev_priv);
13678                         intel_check_pch_fifo_underruns(dev_priv);
13679
13680                         if (!crtc->state->active)
13681                                 intel_update_watermarks(crtc);
13682                 }
13683         }
13684
13685         /* Only after disabling all output pipelines that will be changed can we
13686          * update the the output configuration. */
13687         intel_modeset_update_crtc_state(state);
13688
13689         if (intel_state->modeset) {
13690                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13691
13692                 if (dev_priv->display.modeset_commit_cdclk &&
13693                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13694                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13695                         dev_priv->display.modeset_commit_cdclk(state);
13696
13697                 intel_modeset_verify_disabled(dev);
13698         }
13699
13700         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13701         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13702                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13703                 bool modeset = needs_modeset(crtc->state);
13704                 struct intel_crtc_state *pipe_config =
13705                         to_intel_crtc_state(crtc->state);
13706
13707                 if (modeset && crtc->state->active) {
13708                         update_scanline_offset(to_intel_crtc(crtc));
13709                         dev_priv->display.crtc_enable(crtc);
13710                 }
13711
13712                 /* Complete events for now disable pipes here. */
13713                 if (modeset && !crtc->state->active && crtc->state->event) {
13714                         spin_lock_irq(&dev->event_lock);
13715                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
13716                         spin_unlock_irq(&dev->event_lock);
13717
13718                         crtc->state->event = NULL;
13719                 }
13720
13721                 if (!modeset)
13722                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13723
13724                 if (crtc->state->active &&
13725                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13726                         intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13727
13728                 if (crtc->state->active)
13729                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13730
13731                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13732                         crtc_vblank_mask |= 1 << i;
13733         }
13734
13735         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13736          * already, but still need the state for the delayed optimization. To
13737          * fix this:
13738          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13739          * - schedule that vblank worker _before_ calling hw_done
13740          * - at the start of commit_tail, cancel it _synchrously
13741          * - switch over to the vblank wait helper in the core after that since
13742          *   we don't need out special handling any more.
13743          */
13744         if (!state->legacy_cursor_update)
13745                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13746
13747         /*
13748          * Now that the vblank has passed, we can go ahead and program the
13749          * optimal watermarks on platforms that need two-step watermark
13750          * programming.
13751          *
13752          * TODO: Move this (and other cleanup) to an async worker eventually.
13753          */
13754         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13755                 intel_cstate = to_intel_crtc_state(crtc->state);
13756
13757                 if (dev_priv->display.optimize_watermarks)
13758                         dev_priv->display.optimize_watermarks(intel_cstate);
13759         }
13760
13761         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13762                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13763
13764                 if (put_domains[i])
13765                         modeset_put_power_domains(dev_priv, put_domains[i]);
13766
13767                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13768         }
13769
13770         drm_atomic_helper_commit_hw_done(state);
13771
13772         if (intel_state->modeset)
13773                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13774
13775         mutex_lock(&dev->struct_mutex);
13776         drm_atomic_helper_cleanup_planes(dev, state);
13777         mutex_unlock(&dev->struct_mutex);
13778
13779         drm_atomic_helper_commit_cleanup_done(state);
13780
13781         drm_atomic_state_free(state);
13782
13783         /* As one of the primary mmio accessors, KMS has a high likelihood
13784          * of triggering bugs in unclaimed access. After we finish
13785          * modesetting, see if an error has been flagged, and if so
13786          * enable debugging for the next modeset - and hope we catch
13787          * the culprit.
13788          *
13789          * XXX note that we assume display power is on at this point.
13790          * This might hold true now but we need to add pm helper to check
13791          * unclaimed only when the hardware is on, as atomic commits
13792          * can happen also when the device is completely off.
13793          */
13794         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13795 }
13796
13797 static void intel_atomic_commit_work(struct work_struct *work)
13798 {
13799         struct drm_atomic_state *state = container_of(work,
13800                                                       struct drm_atomic_state,
13801                                                       commit_work);
13802         intel_atomic_commit_tail(state);
13803 }
13804
13805 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13806 {
13807         struct drm_plane_state *old_plane_state;
13808         struct drm_plane *plane;
13809         struct drm_i915_gem_object *obj, *old_obj;
13810         struct intel_plane *intel_plane;
13811         int i;
13812
13813         mutex_lock(&state->dev->struct_mutex);
13814         for_each_plane_in_state(state, plane, old_plane_state, i) {
13815                 obj = intel_fb_obj(plane->state->fb);
13816                 old_obj = intel_fb_obj(old_plane_state->fb);
13817                 intel_plane = to_intel_plane(plane);
13818
13819                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13820         }
13821         mutex_unlock(&state->dev->struct_mutex);
13822 }
13823
13824 /**
13825  * intel_atomic_commit - commit validated state object
13826  * @dev: DRM device
13827  * @state: the top-level driver state object
13828  * @nonblock: nonblocking commit
13829  *
13830  * This function commits a top-level state object that has been validated
13831  * with drm_atomic_helper_check().
13832  *
13833  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13834  * nonblocking commits are only safe for pure plane updates. Everything else
13835  * should work though.
13836  *
13837  * RETURNS
13838  * Zero for success or -errno.
13839  */
13840 static int intel_atomic_commit(struct drm_device *dev,
13841                                struct drm_atomic_state *state,
13842                                bool nonblock)
13843 {
13844         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13845         struct drm_i915_private *dev_priv = to_i915(dev);
13846         int ret = 0;
13847
13848         if (intel_state->modeset && nonblock) {
13849                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13850                 return -EINVAL;
13851         }
13852
13853         ret = drm_atomic_helper_setup_commit(state, nonblock);
13854         if (ret)
13855                 return ret;
13856
13857         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13858
13859         ret = intel_atomic_prepare_commit(dev, state, nonblock);
13860         if (ret) {
13861                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13862                 return ret;
13863         }
13864
13865         drm_atomic_helper_swap_state(state, true);
13866         dev_priv->wm.distrust_bios_wm = false;
13867         dev_priv->wm.skl_results = intel_state->wm_results;
13868         intel_shared_dpll_commit(state);
13869         intel_atomic_track_fbs(state);
13870
13871         if (nonblock)
13872                 queue_work(system_unbound_wq, &state->commit_work);
13873         else
13874                 intel_atomic_commit_tail(state);
13875
13876         return 0;
13877 }
13878
13879 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13880 {
13881         struct drm_device *dev = crtc->dev;
13882         struct drm_atomic_state *state;
13883         struct drm_crtc_state *crtc_state;
13884         int ret;
13885
13886         state = drm_atomic_state_alloc(dev);
13887         if (!state) {
13888                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13889                               crtc->base.id, crtc->name);
13890                 return;
13891         }
13892
13893         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13894
13895 retry:
13896         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13897         ret = PTR_ERR_OR_ZERO(crtc_state);
13898         if (!ret) {
13899                 if (!crtc_state->active)
13900                         goto out;
13901
13902                 crtc_state->mode_changed = true;
13903                 ret = drm_atomic_commit(state);
13904         }
13905
13906         if (ret == -EDEADLK) {
13907                 drm_atomic_state_clear(state);
13908                 drm_modeset_backoff(state->acquire_ctx);
13909                 goto retry;
13910         }
13911
13912         if (ret)
13913 out:
13914                 drm_atomic_state_free(state);
13915 }
13916
13917 #undef for_each_intel_crtc_masked
13918
13919 /*
13920  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13921  *        drm_atomic_helper_legacy_gamma_set() directly.
13922  */
13923 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13924                                          u16 *red, u16 *green, u16 *blue,
13925                                          uint32_t size)
13926 {
13927         struct drm_device *dev = crtc->dev;
13928         struct drm_mode_config *config = &dev->mode_config;
13929         struct drm_crtc_state *state;
13930         int ret;
13931
13932         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13933         if (ret)
13934                 return ret;
13935
13936         /*
13937          * Make sure we update the legacy properties so this works when
13938          * atomic is not enabled.
13939          */
13940
13941         state = crtc->state;
13942
13943         drm_object_property_set_value(&crtc->base,
13944                                       config->degamma_lut_property,
13945                                       (state->degamma_lut) ?
13946                                       state->degamma_lut->base.id : 0);
13947
13948         drm_object_property_set_value(&crtc->base,
13949                                       config->ctm_property,
13950                                       (state->ctm) ?
13951                                       state->ctm->base.id : 0);
13952
13953         drm_object_property_set_value(&crtc->base,
13954                                       config->gamma_lut_property,
13955                                       (state->gamma_lut) ?
13956                                       state->gamma_lut->base.id : 0);
13957
13958         return 0;
13959 }
13960
13961 static const struct drm_crtc_funcs intel_crtc_funcs = {
13962         .gamma_set = intel_atomic_legacy_gamma_set,
13963         .set_config = drm_atomic_helper_set_config,
13964         .set_property = drm_atomic_helper_crtc_set_property,
13965         .destroy = intel_crtc_destroy,
13966         .page_flip = intel_crtc_page_flip,
13967         .atomic_duplicate_state = intel_crtc_duplicate_state,
13968         .atomic_destroy_state = intel_crtc_destroy_state,
13969 };
13970
13971 /**
13972  * intel_prepare_plane_fb - Prepare fb for usage on plane
13973  * @plane: drm plane to prepare for
13974  * @fb: framebuffer to prepare for presentation
13975  *
13976  * Prepares a framebuffer for usage on a display plane.  Generally this
13977  * involves pinning the underlying object and updating the frontbuffer tracking
13978  * bits.  Some older platforms need special physical address handling for
13979  * cursor planes.
13980  *
13981  * Must be called with struct_mutex held.
13982  *
13983  * Returns 0 on success, negative error code on failure.
13984  */
13985 int
13986 intel_prepare_plane_fb(struct drm_plane *plane,
13987                        const struct drm_plane_state *new_state)
13988 {
13989         struct drm_device *dev = plane->dev;
13990         struct drm_framebuffer *fb = new_state->fb;
13991         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13992         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13993         struct reservation_object *resv;
13994         int ret = 0;
13995
13996         if (!obj && !old_obj)
13997                 return 0;
13998
13999         if (old_obj) {
14000                 struct drm_crtc_state *crtc_state =
14001                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14002
14003                 /* Big Hammer, we also need to ensure that any pending
14004                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14005                  * current scanout is retired before unpinning the old
14006                  * framebuffer. Note that we rely on userspace rendering
14007                  * into the buffer attached to the pipe they are waiting
14008                  * on. If not, userspace generates a GPU hang with IPEHR
14009                  * point to the MI_WAIT_FOR_EVENT.
14010                  *
14011                  * This should only fail upon a hung GPU, in which case we
14012                  * can safely continue.
14013                  */
14014                 if (needs_modeset(crtc_state))
14015                         ret = i915_gem_object_wait_rendering(old_obj, true);
14016                 if (ret) {
14017                         /* GPU hangs should have been swallowed by the wait */
14018                         WARN_ON(ret == -EIO);
14019                         return ret;
14020                 }
14021         }
14022
14023         if (!obj)
14024                 return 0;
14025
14026         /* For framebuffer backed by dmabuf, wait for fence */
14027         resv = i915_gem_object_get_dmabuf_resv(obj);
14028         if (resv) {
14029                 long lret;
14030
14031                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14032                                                            MAX_SCHEDULE_TIMEOUT);
14033                 if (lret == -ERESTARTSYS)
14034                         return lret;
14035
14036                 WARN(lret < 0, "waiting returns %li\n", lret);
14037         }
14038
14039         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14040             INTEL_INFO(dev)->cursor_needs_physical) {
14041                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14042                 ret = i915_gem_object_attach_phys(obj, align);
14043                 if (ret)
14044                         DRM_DEBUG_KMS("failed to attach phys object\n");
14045         } else {
14046                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14047         }
14048
14049         if (ret == 0) {
14050                 struct intel_plane_state *plane_state =
14051                         to_intel_plane_state(new_state);
14052
14053                 i915_gem_request_assign(&plane_state->wait_req,
14054                                         obj->last_write_req);
14055         }
14056
14057         return ret;
14058 }
14059
14060 /**
14061  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14062  * @plane: drm plane to clean up for
14063  * @fb: old framebuffer that was on plane
14064  *
14065  * Cleans up a framebuffer that has just been removed from a plane.
14066  *
14067  * Must be called with struct_mutex held.
14068  */
14069 void
14070 intel_cleanup_plane_fb(struct drm_plane *plane,
14071                        const struct drm_plane_state *old_state)
14072 {
14073         struct drm_device *dev = plane->dev;
14074         struct intel_plane_state *old_intel_state;
14075         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14076         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14077
14078         old_intel_state = to_intel_plane_state(old_state);
14079
14080         if (!obj && !old_obj)
14081                 return;
14082
14083         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14084             !INTEL_INFO(dev)->cursor_needs_physical))
14085                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14086
14087         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14088 }
14089
14090 int
14091 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14092 {
14093         int max_scale;
14094         int crtc_clock, cdclk;
14095
14096         if (!intel_crtc || !crtc_state->base.enable)
14097                 return DRM_PLANE_HELPER_NO_SCALING;
14098
14099         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14100         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14101
14102         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14103                 return DRM_PLANE_HELPER_NO_SCALING;
14104
14105         /*
14106          * skl max scale is lower of:
14107          *    close to 3 but not 3, -1 is for that purpose
14108          *            or
14109          *    cdclk/crtc_clock
14110          */
14111         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14112
14113         return max_scale;
14114 }
14115
14116 static int
14117 intel_check_primary_plane(struct drm_plane *plane,
14118                           struct intel_crtc_state *crtc_state,
14119                           struct intel_plane_state *state)
14120 {
14121         struct drm_crtc *crtc = state->base.crtc;
14122         struct drm_framebuffer *fb = state->base.fb;
14123         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14124         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14125         bool can_position = false;
14126
14127         if (INTEL_INFO(plane->dev)->gen >= 9) {
14128                 /* use scaler when colorkey is not required */
14129                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14130                         min_scale = 1;
14131                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14132                 }
14133                 can_position = true;
14134         }
14135
14136         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14137                                              &state->dst, &state->clip,
14138                                              state->base.rotation,
14139                                              min_scale, max_scale,
14140                                              can_position, true,
14141                                              &state->visible);
14142 }
14143
14144 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14145                                     struct drm_crtc_state *old_crtc_state)
14146 {
14147         struct drm_device *dev = crtc->dev;
14148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14149         struct intel_crtc_state *old_intel_state =
14150                 to_intel_crtc_state(old_crtc_state);
14151         bool modeset = needs_modeset(crtc->state);
14152
14153         /* Perform vblank evasion around commit operation */
14154         intel_pipe_update_start(intel_crtc);
14155
14156         if (modeset)
14157                 return;
14158
14159         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14160                 intel_color_set_csc(crtc->state);
14161                 intel_color_load_luts(crtc->state);
14162         }
14163
14164         if (to_intel_crtc_state(crtc->state)->update_pipe)
14165                 intel_update_pipe_config(intel_crtc, old_intel_state);
14166         else if (INTEL_INFO(dev)->gen >= 9)
14167                 skl_detach_scalers(intel_crtc);
14168 }
14169
14170 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14171                                      struct drm_crtc_state *old_crtc_state)
14172 {
14173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14174
14175         intel_pipe_update_end(intel_crtc, NULL);
14176 }
14177
14178 /**
14179  * intel_plane_destroy - destroy a plane
14180  * @plane: plane to destroy
14181  *
14182  * Common destruction function for all types of planes (primary, cursor,
14183  * sprite).
14184  */
14185 void intel_plane_destroy(struct drm_plane *plane)
14186 {
14187         if (!plane)
14188                 return;
14189
14190         drm_plane_cleanup(plane);
14191         kfree(to_intel_plane(plane));
14192 }
14193
14194 const struct drm_plane_funcs intel_plane_funcs = {
14195         .update_plane = drm_atomic_helper_update_plane,
14196         .disable_plane = drm_atomic_helper_disable_plane,
14197         .destroy = intel_plane_destroy,
14198         .set_property = drm_atomic_helper_plane_set_property,
14199         .atomic_get_property = intel_plane_atomic_get_property,
14200         .atomic_set_property = intel_plane_atomic_set_property,
14201         .atomic_duplicate_state = intel_plane_duplicate_state,
14202         .atomic_destroy_state = intel_plane_destroy_state,
14203
14204 };
14205
14206 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14207                                                     int pipe)
14208 {
14209         struct intel_plane *primary = NULL;
14210         struct intel_plane_state *state = NULL;
14211         const uint32_t *intel_primary_formats;
14212         unsigned int num_formats;
14213         int ret;
14214
14215         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14216         if (!primary)
14217                 goto fail;
14218
14219         state = intel_create_plane_state(&primary->base);
14220         if (!state)
14221                 goto fail;
14222         primary->base.state = &state->base;
14223
14224         primary->can_scale = false;
14225         primary->max_downscale = 1;
14226         if (INTEL_INFO(dev)->gen >= 9) {
14227                 primary->can_scale = true;
14228                 state->scaler_id = -1;
14229         }
14230         primary->pipe = pipe;
14231         primary->plane = pipe;
14232         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14233         primary->check_plane = intel_check_primary_plane;
14234         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14235                 primary->plane = !pipe;
14236
14237         if (INTEL_INFO(dev)->gen >= 9) {
14238                 intel_primary_formats = skl_primary_formats;
14239                 num_formats = ARRAY_SIZE(skl_primary_formats);
14240
14241                 primary->update_plane = skylake_update_primary_plane;
14242                 primary->disable_plane = skylake_disable_primary_plane;
14243         } else if (HAS_PCH_SPLIT(dev)) {
14244                 intel_primary_formats = i965_primary_formats;
14245                 num_formats = ARRAY_SIZE(i965_primary_formats);
14246
14247                 primary->update_plane = ironlake_update_primary_plane;
14248                 primary->disable_plane = i9xx_disable_primary_plane;
14249         } else if (INTEL_INFO(dev)->gen >= 4) {
14250                 intel_primary_formats = i965_primary_formats;
14251                 num_formats = ARRAY_SIZE(i965_primary_formats);
14252
14253                 primary->update_plane = i9xx_update_primary_plane;
14254                 primary->disable_plane = i9xx_disable_primary_plane;
14255         } else {
14256                 intel_primary_formats = i8xx_primary_formats;
14257                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14258
14259                 primary->update_plane = i9xx_update_primary_plane;
14260                 primary->disable_plane = i9xx_disable_primary_plane;
14261         }
14262
14263         if (INTEL_INFO(dev)->gen >= 9)
14264                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14265                                                &intel_plane_funcs,
14266                                                intel_primary_formats, num_formats,
14267                                                DRM_PLANE_TYPE_PRIMARY,
14268                                                "plane 1%c", pipe_name(pipe));
14269         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14270                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14271                                                &intel_plane_funcs,
14272                                                intel_primary_formats, num_formats,
14273                                                DRM_PLANE_TYPE_PRIMARY,
14274                                                "primary %c", pipe_name(pipe));
14275         else
14276                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14277                                                &intel_plane_funcs,
14278                                                intel_primary_formats, num_formats,
14279                                                DRM_PLANE_TYPE_PRIMARY,
14280                                                "plane %c", plane_name(primary->plane));
14281         if (ret)
14282                 goto fail;
14283
14284         if (INTEL_INFO(dev)->gen >= 4)
14285                 intel_create_rotation_property(dev, primary);
14286
14287         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14288
14289         return &primary->base;
14290
14291 fail:
14292         kfree(state);
14293         kfree(primary);
14294
14295         return NULL;
14296 }
14297
14298 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14299 {
14300         if (!dev->mode_config.rotation_property) {
14301                 unsigned long flags = BIT(DRM_ROTATE_0) |
14302                         BIT(DRM_ROTATE_180);
14303
14304                 if (INTEL_INFO(dev)->gen >= 9)
14305                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14306
14307                 dev->mode_config.rotation_property =
14308                         drm_mode_create_rotation_property(dev, flags);
14309         }
14310         if (dev->mode_config.rotation_property)
14311                 drm_object_attach_property(&plane->base.base,
14312                                 dev->mode_config.rotation_property,
14313                                 plane->base.state->rotation);
14314 }
14315
14316 static int
14317 intel_check_cursor_plane(struct drm_plane *plane,
14318                          struct intel_crtc_state *crtc_state,
14319                          struct intel_plane_state *state)
14320 {
14321         struct drm_crtc *crtc = crtc_state->base.crtc;
14322         struct drm_framebuffer *fb = state->base.fb;
14323         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14324         enum pipe pipe = to_intel_plane(plane)->pipe;
14325         unsigned stride;
14326         int ret;
14327
14328         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14329                                             &state->dst, &state->clip,
14330                                             state->base.rotation,
14331                                             DRM_PLANE_HELPER_NO_SCALING,
14332                                             DRM_PLANE_HELPER_NO_SCALING,
14333                                             true, true, &state->visible);
14334         if (ret)
14335                 return ret;
14336
14337         /* if we want to turn off the cursor ignore width and height */
14338         if (!obj)
14339                 return 0;
14340
14341         /* Check for which cursor types we support */
14342         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14343                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14344                           state->base.crtc_w, state->base.crtc_h);
14345                 return -EINVAL;
14346         }
14347
14348         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14349         if (obj->base.size < stride * state->base.crtc_h) {
14350                 DRM_DEBUG_KMS("buffer is too small\n");
14351                 return -ENOMEM;
14352         }
14353
14354         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14355                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14356                 return -EINVAL;
14357         }
14358
14359         /*
14360          * There's something wrong with the cursor on CHV pipe C.
14361          * If it straddles the left edge of the screen then
14362          * moving it away from the edge or disabling it often
14363          * results in a pipe underrun, and often that can lead to
14364          * dead pipe (constant underrun reported, and it scans
14365          * out just a solid color). To recover from that, the
14366          * display power well must be turned off and on again.
14367          * Refuse the put the cursor into that compromised position.
14368          */
14369         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14370             state->visible && state->base.crtc_x < 0) {
14371                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14372                 return -EINVAL;
14373         }
14374
14375         return 0;
14376 }
14377
14378 static void
14379 intel_disable_cursor_plane(struct drm_plane *plane,
14380                            struct drm_crtc *crtc)
14381 {
14382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14383
14384         intel_crtc->cursor_addr = 0;
14385         intel_crtc_update_cursor(crtc, NULL);
14386 }
14387
14388 static void
14389 intel_update_cursor_plane(struct drm_plane *plane,
14390                           const struct intel_crtc_state *crtc_state,
14391                           const struct intel_plane_state *state)
14392 {
14393         struct drm_crtc *crtc = crtc_state->base.crtc;
14394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14395         struct drm_device *dev = plane->dev;
14396         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14397         uint32_t addr;
14398
14399         if (!obj)
14400                 addr = 0;
14401         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14402                 addr = i915_gem_obj_ggtt_offset(obj);
14403         else
14404                 addr = obj->phys_handle->busaddr;
14405
14406         intel_crtc->cursor_addr = addr;
14407         intel_crtc_update_cursor(crtc, state);
14408 }
14409
14410 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14411                                                    int pipe)
14412 {
14413         struct intel_plane *cursor = NULL;
14414         struct intel_plane_state *state = NULL;
14415         int ret;
14416
14417         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14418         if (!cursor)
14419                 goto fail;
14420
14421         state = intel_create_plane_state(&cursor->base);
14422         if (!state)
14423                 goto fail;
14424         cursor->base.state = &state->base;
14425
14426         cursor->can_scale = false;
14427         cursor->max_downscale = 1;
14428         cursor->pipe = pipe;
14429         cursor->plane = pipe;
14430         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14431         cursor->check_plane = intel_check_cursor_plane;
14432         cursor->update_plane = intel_update_cursor_plane;
14433         cursor->disable_plane = intel_disable_cursor_plane;
14434
14435         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14436                                        &intel_plane_funcs,
14437                                        intel_cursor_formats,
14438                                        ARRAY_SIZE(intel_cursor_formats),
14439                                        DRM_PLANE_TYPE_CURSOR,
14440                                        "cursor %c", pipe_name(pipe));
14441         if (ret)
14442                 goto fail;
14443
14444         if (INTEL_INFO(dev)->gen >= 4) {
14445                 if (!dev->mode_config.rotation_property)
14446                         dev->mode_config.rotation_property =
14447                                 drm_mode_create_rotation_property(dev,
14448                                                         BIT(DRM_ROTATE_0) |
14449                                                         BIT(DRM_ROTATE_180));
14450                 if (dev->mode_config.rotation_property)
14451                         drm_object_attach_property(&cursor->base.base,
14452                                 dev->mode_config.rotation_property,
14453                                 state->base.rotation);
14454         }
14455
14456         if (INTEL_INFO(dev)->gen >=9)
14457                 state->scaler_id = -1;
14458
14459         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14460
14461         return &cursor->base;
14462
14463 fail:
14464         kfree(state);
14465         kfree(cursor);
14466
14467         return NULL;
14468 }
14469
14470 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14471         struct intel_crtc_state *crtc_state)
14472 {
14473         int i;
14474         struct intel_scaler *intel_scaler;
14475         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14476
14477         for (i = 0; i < intel_crtc->num_scalers; i++) {
14478                 intel_scaler = &scaler_state->scalers[i];
14479                 intel_scaler->in_use = 0;
14480                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14481         }
14482
14483         scaler_state->scaler_id = -1;
14484 }
14485
14486 static void intel_crtc_init(struct drm_device *dev, int pipe)
14487 {
14488         struct drm_i915_private *dev_priv = to_i915(dev);
14489         struct intel_crtc *intel_crtc;
14490         struct intel_crtc_state *crtc_state = NULL;
14491         struct drm_plane *primary = NULL;
14492         struct drm_plane *cursor = NULL;
14493         int ret;
14494
14495         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14496         if (intel_crtc == NULL)
14497                 return;
14498
14499         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14500         if (!crtc_state)
14501                 goto fail;
14502         intel_crtc->config = crtc_state;
14503         intel_crtc->base.state = &crtc_state->base;
14504         crtc_state->base.crtc = &intel_crtc->base;
14505
14506         /* initialize shared scalers */
14507         if (INTEL_INFO(dev)->gen >= 9) {
14508                 if (pipe == PIPE_C)
14509                         intel_crtc->num_scalers = 1;
14510                 else
14511                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14512
14513                 skl_init_scalers(dev, intel_crtc, crtc_state);
14514         }
14515
14516         primary = intel_primary_plane_create(dev, pipe);
14517         if (!primary)
14518                 goto fail;
14519
14520         cursor = intel_cursor_plane_create(dev, pipe);
14521         if (!cursor)
14522                 goto fail;
14523
14524         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14525                                         cursor, &intel_crtc_funcs,
14526                                         "pipe %c", pipe_name(pipe));
14527         if (ret)
14528                 goto fail;
14529
14530         /*
14531          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14532          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14533          */
14534         intel_crtc->pipe = pipe;
14535         intel_crtc->plane = pipe;
14536         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14537                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14538                 intel_crtc->plane = !pipe;
14539         }
14540
14541         intel_crtc->cursor_base = ~0;
14542         intel_crtc->cursor_cntl = ~0;
14543         intel_crtc->cursor_size = ~0;
14544
14545         intel_crtc->wm.cxsr_allowed = true;
14546
14547         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14548                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14549         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14550         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14551
14552         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14553
14554         intel_color_init(&intel_crtc->base);
14555
14556         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14557         return;
14558
14559 fail:
14560         intel_plane_destroy(primary);
14561         intel_plane_destroy(cursor);
14562         kfree(crtc_state);
14563         kfree(intel_crtc);
14564 }
14565
14566 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14567 {
14568         struct drm_encoder *encoder = connector->base.encoder;
14569         struct drm_device *dev = connector->base.dev;
14570
14571         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14572
14573         if (!encoder || WARN_ON(!encoder->crtc))
14574                 return INVALID_PIPE;
14575
14576         return to_intel_crtc(encoder->crtc)->pipe;
14577 }
14578
14579 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14580                                 struct drm_file *file)
14581 {
14582         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14583         struct drm_crtc *drmmode_crtc;
14584         struct intel_crtc *crtc;
14585
14586         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14587         if (!drmmode_crtc)
14588                 return -ENOENT;
14589
14590         crtc = to_intel_crtc(drmmode_crtc);
14591         pipe_from_crtc_id->pipe = crtc->pipe;
14592
14593         return 0;
14594 }
14595
14596 static int intel_encoder_clones(struct intel_encoder *encoder)
14597 {
14598         struct drm_device *dev = encoder->base.dev;
14599         struct intel_encoder *source_encoder;
14600         int index_mask = 0;
14601         int entry = 0;
14602
14603         for_each_intel_encoder(dev, source_encoder) {
14604                 if (encoders_cloneable(encoder, source_encoder))
14605                         index_mask |= (1 << entry);
14606
14607                 entry++;
14608         }
14609
14610         return index_mask;
14611 }
14612
14613 static bool has_edp_a(struct drm_device *dev)
14614 {
14615         struct drm_i915_private *dev_priv = to_i915(dev);
14616
14617         if (!IS_MOBILE(dev))
14618                 return false;
14619
14620         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14621                 return false;
14622
14623         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14624                 return false;
14625
14626         return true;
14627 }
14628
14629 static bool intel_crt_present(struct drm_device *dev)
14630 {
14631         struct drm_i915_private *dev_priv = to_i915(dev);
14632
14633         if (INTEL_INFO(dev)->gen >= 9)
14634                 return false;
14635
14636         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14637                 return false;
14638
14639         if (IS_CHERRYVIEW(dev))
14640                 return false;
14641
14642         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14643                 return false;
14644
14645         /* DDI E can't be used if DDI A requires 4 lanes */
14646         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14647                 return false;
14648
14649         if (!dev_priv->vbt.int_crt_support)
14650                 return false;
14651
14652         return true;
14653 }
14654
14655 static void intel_setup_outputs(struct drm_device *dev)
14656 {
14657         struct drm_i915_private *dev_priv = to_i915(dev);
14658         struct intel_encoder *encoder;
14659         bool dpd_is_edp = false;
14660
14661         /*
14662          * intel_edp_init_connector() depends on this completing first, to
14663          * prevent the registeration of both eDP and LVDS and the incorrect
14664          * sharing of the PPS.
14665          */
14666         intel_lvds_init(dev);
14667
14668         if (intel_crt_present(dev))
14669                 intel_crt_init(dev);
14670
14671         if (IS_BROXTON(dev)) {
14672                 /*
14673                  * FIXME: Broxton doesn't support port detection via the
14674                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14675                  * detect the ports.
14676                  */
14677                 intel_ddi_init(dev, PORT_A);
14678                 intel_ddi_init(dev, PORT_B);
14679                 intel_ddi_init(dev, PORT_C);
14680
14681                 intel_dsi_init(dev);
14682         } else if (HAS_DDI(dev)) {
14683                 int found;
14684
14685                 /*
14686                  * Haswell uses DDI functions to detect digital outputs.
14687                  * On SKL pre-D0 the strap isn't connected, so we assume
14688                  * it's there.
14689                  */
14690                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14691                 /* WaIgnoreDDIAStrap: skl */
14692                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14693                         intel_ddi_init(dev, PORT_A);
14694
14695                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14696                  * register */
14697                 found = I915_READ(SFUSE_STRAP);
14698
14699                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14700                         intel_ddi_init(dev, PORT_B);
14701                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14702                         intel_ddi_init(dev, PORT_C);
14703                 if (found & SFUSE_STRAP_DDID_DETECTED)
14704                         intel_ddi_init(dev, PORT_D);
14705                 /*
14706                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14707                  */
14708                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14709                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14710                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14711                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14712                         intel_ddi_init(dev, PORT_E);
14713
14714         } else if (HAS_PCH_SPLIT(dev)) {
14715                 int found;
14716                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14717
14718                 if (has_edp_a(dev))
14719                         intel_dp_init(dev, DP_A, PORT_A);
14720
14721                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14722                         /* PCH SDVOB multiplex with HDMIB */
14723                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14724                         if (!found)
14725                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14726                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14727                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14728                 }
14729
14730                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14731                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14732
14733                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14734                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14735
14736                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14737                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14738
14739                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14740                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14741         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14742                 bool has_edp, has_port;
14743
14744                 /*
14745                  * The DP_DETECTED bit is the latched state of the DDC
14746                  * SDA pin at boot. However since eDP doesn't require DDC
14747                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14748                  * eDP ports may have been muxed to an alternate function.
14749                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14750                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14751                  * detect eDP ports.
14752                  *
14753                  * Sadly the straps seem to be missing sometimes even for HDMI
14754                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14755                  * and VBT for the presence of the port. Additionally we can't
14756                  * trust the port type the VBT declares as we've seen at least
14757                  * HDMI ports that the VBT claim are DP or eDP.
14758                  */
14759                 has_edp = intel_dp_is_edp(dev, PORT_B);
14760                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14761                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14762                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14763                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14764                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14765
14766                 has_edp = intel_dp_is_edp(dev, PORT_C);
14767                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14768                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14769                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14770                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14771                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14772
14773                 if (IS_CHERRYVIEW(dev)) {
14774                         /*
14775                          * eDP not supported on port D,
14776                          * so no need to worry about it
14777                          */
14778                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14779                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14780                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14781                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14782                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14783                 }
14784
14785                 intel_dsi_init(dev);
14786         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14787                 bool found = false;
14788
14789                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14790                         DRM_DEBUG_KMS("probing SDVOB\n");
14791                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14792                         if (!found && IS_G4X(dev)) {
14793                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14794                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14795                         }
14796
14797                         if (!found && IS_G4X(dev))
14798                                 intel_dp_init(dev, DP_B, PORT_B);
14799                 }
14800
14801                 /* Before G4X SDVOC doesn't have its own detect register */
14802
14803                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14804                         DRM_DEBUG_KMS("probing SDVOC\n");
14805                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14806                 }
14807
14808                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14809
14810                         if (IS_G4X(dev)) {
14811                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14812                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14813                         }
14814                         if (IS_G4X(dev))
14815                                 intel_dp_init(dev, DP_C, PORT_C);
14816                 }
14817
14818                 if (IS_G4X(dev) &&
14819                     (I915_READ(DP_D) & DP_DETECTED))
14820                         intel_dp_init(dev, DP_D, PORT_D);
14821         } else if (IS_GEN2(dev))
14822                 intel_dvo_init(dev);
14823
14824         if (SUPPORTS_TV(dev))
14825                 intel_tv_init(dev);
14826
14827         intel_psr_init(dev);
14828
14829         for_each_intel_encoder(dev, encoder) {
14830                 encoder->base.possible_crtcs = encoder->crtc_mask;
14831                 encoder->base.possible_clones =
14832                         intel_encoder_clones(encoder);
14833         }
14834
14835         intel_init_pch_refclk(dev);
14836
14837         drm_helper_move_panel_connectors_to_head(dev);
14838 }
14839
14840 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14841 {
14842         struct drm_device *dev = fb->dev;
14843         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14844
14845         drm_framebuffer_cleanup(fb);
14846         mutex_lock(&dev->struct_mutex);
14847         WARN_ON(!intel_fb->obj->framebuffer_references--);
14848         drm_gem_object_unreference(&intel_fb->obj->base);
14849         mutex_unlock(&dev->struct_mutex);
14850         kfree(intel_fb);
14851 }
14852
14853 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14854                                                 struct drm_file *file,
14855                                                 unsigned int *handle)
14856 {
14857         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14858         struct drm_i915_gem_object *obj = intel_fb->obj;
14859
14860         if (obj->userptr.mm) {
14861                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14862                 return -EINVAL;
14863         }
14864
14865         return drm_gem_handle_create(file, &obj->base, handle);
14866 }
14867
14868 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14869                                         struct drm_file *file,
14870                                         unsigned flags, unsigned color,
14871                                         struct drm_clip_rect *clips,
14872                                         unsigned num_clips)
14873 {
14874         struct drm_device *dev = fb->dev;
14875         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14876         struct drm_i915_gem_object *obj = intel_fb->obj;
14877
14878         mutex_lock(&dev->struct_mutex);
14879         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14880         mutex_unlock(&dev->struct_mutex);
14881
14882         return 0;
14883 }
14884
14885 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14886         .destroy = intel_user_framebuffer_destroy,
14887         .create_handle = intel_user_framebuffer_create_handle,
14888         .dirty = intel_user_framebuffer_dirty,
14889 };
14890
14891 static
14892 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14893                          uint32_t pixel_format)
14894 {
14895         u32 gen = INTEL_INFO(dev)->gen;
14896
14897         if (gen >= 9) {
14898                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14899
14900                 /* "The stride in bytes must not exceed the of the size of 8K
14901                  *  pixels and 32K bytes."
14902                  */
14903                 return min(8192 * cpp, 32768);
14904         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14905                 return 32*1024;
14906         } else if (gen >= 4) {
14907                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14908                         return 16*1024;
14909                 else
14910                         return 32*1024;
14911         } else if (gen >= 3) {
14912                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14913                         return 8*1024;
14914                 else
14915                         return 16*1024;
14916         } else {
14917                 /* XXX DSPC is limited to 4k tiled */
14918                 return 8*1024;
14919         }
14920 }
14921
14922 static int intel_framebuffer_init(struct drm_device *dev,
14923                                   struct intel_framebuffer *intel_fb,
14924                                   struct drm_mode_fb_cmd2 *mode_cmd,
14925                                   struct drm_i915_gem_object *obj)
14926 {
14927         struct drm_i915_private *dev_priv = to_i915(dev);
14928         unsigned int aligned_height;
14929         int ret;
14930         u32 pitch_limit, stride_alignment;
14931
14932         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14933
14934         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14935                 /* Enforce that fb modifier and tiling mode match, but only for
14936                  * X-tiled. This is needed for FBC. */
14937                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14938                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14939                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14940                         return -EINVAL;
14941                 }
14942         } else {
14943                 if (obj->tiling_mode == I915_TILING_X)
14944                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14945                 else if (obj->tiling_mode == I915_TILING_Y) {
14946                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14947                         return -EINVAL;
14948                 }
14949         }
14950
14951         /* Passed in modifier sanity checking. */
14952         switch (mode_cmd->modifier[0]) {
14953         case I915_FORMAT_MOD_Y_TILED:
14954         case I915_FORMAT_MOD_Yf_TILED:
14955                 if (INTEL_INFO(dev)->gen < 9) {
14956                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14957                                   mode_cmd->modifier[0]);
14958                         return -EINVAL;
14959                 }
14960         case DRM_FORMAT_MOD_NONE:
14961         case I915_FORMAT_MOD_X_TILED:
14962                 break;
14963         default:
14964                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14965                           mode_cmd->modifier[0]);
14966                 return -EINVAL;
14967         }
14968
14969         stride_alignment = intel_fb_stride_alignment(dev_priv,
14970                                                      mode_cmd->modifier[0],
14971                                                      mode_cmd->pixel_format);
14972         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14973                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14974                           mode_cmd->pitches[0], stride_alignment);
14975                 return -EINVAL;
14976         }
14977
14978         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14979                                            mode_cmd->pixel_format);
14980         if (mode_cmd->pitches[0] > pitch_limit) {
14981                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14982                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14983                           "tiled" : "linear",
14984                           mode_cmd->pitches[0], pitch_limit);
14985                 return -EINVAL;
14986         }
14987
14988         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14989             mode_cmd->pitches[0] != obj->stride) {
14990                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14991                           mode_cmd->pitches[0], obj->stride);
14992                 return -EINVAL;
14993         }
14994
14995         /* Reject formats not supported by any plane early. */
14996         switch (mode_cmd->pixel_format) {
14997         case DRM_FORMAT_C8:
14998         case DRM_FORMAT_RGB565:
14999         case DRM_FORMAT_XRGB8888:
15000         case DRM_FORMAT_ARGB8888:
15001                 break;
15002         case DRM_FORMAT_XRGB1555:
15003                 if (INTEL_INFO(dev)->gen > 3) {
15004                         DRM_DEBUG("unsupported pixel format: %s\n",
15005                                   drm_get_format_name(mode_cmd->pixel_format));
15006                         return -EINVAL;
15007                 }
15008                 break;
15009         case DRM_FORMAT_ABGR8888:
15010                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15011                     INTEL_INFO(dev)->gen < 9) {
15012                         DRM_DEBUG("unsupported pixel format: %s\n",
15013                                   drm_get_format_name(mode_cmd->pixel_format));
15014                         return -EINVAL;
15015                 }
15016                 break;
15017         case DRM_FORMAT_XBGR8888:
15018         case DRM_FORMAT_XRGB2101010:
15019         case DRM_FORMAT_XBGR2101010:
15020                 if (INTEL_INFO(dev)->gen < 4) {
15021                         DRM_DEBUG("unsupported pixel format: %s\n",
15022                                   drm_get_format_name(mode_cmd->pixel_format));
15023                         return -EINVAL;
15024                 }
15025                 break;
15026         case DRM_FORMAT_ABGR2101010:
15027                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15028                         DRM_DEBUG("unsupported pixel format: %s\n",
15029                                   drm_get_format_name(mode_cmd->pixel_format));
15030                         return -EINVAL;
15031                 }
15032                 break;
15033         case DRM_FORMAT_YUYV:
15034         case DRM_FORMAT_UYVY:
15035         case DRM_FORMAT_YVYU:
15036         case DRM_FORMAT_VYUY:
15037                 if (INTEL_INFO(dev)->gen < 5) {
15038                         DRM_DEBUG("unsupported pixel format: %s\n",
15039                                   drm_get_format_name(mode_cmd->pixel_format));
15040                         return -EINVAL;
15041                 }
15042                 break;
15043         default:
15044                 DRM_DEBUG("unsupported pixel format: %s\n",
15045                           drm_get_format_name(mode_cmd->pixel_format));
15046                 return -EINVAL;
15047         }
15048
15049         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15050         if (mode_cmd->offsets[0] != 0)
15051                 return -EINVAL;
15052
15053         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15054                                                mode_cmd->pixel_format,
15055                                                mode_cmd->modifier[0]);
15056         /* FIXME drm helper for size checks (especially planar formats)? */
15057         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15058                 return -EINVAL;
15059
15060         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15061         intel_fb->obj = obj;
15062
15063         intel_fill_fb_info(dev_priv, &intel_fb->base);
15064
15065         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15066         if (ret) {
15067                 DRM_ERROR("framebuffer init failed %d\n", ret);
15068                 return ret;
15069         }
15070
15071         intel_fb->obj->framebuffer_references++;
15072
15073         return 0;
15074 }
15075
15076 static struct drm_framebuffer *
15077 intel_user_framebuffer_create(struct drm_device *dev,
15078                               struct drm_file *filp,
15079                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15080 {
15081         struct drm_framebuffer *fb;
15082         struct drm_i915_gem_object *obj;
15083         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15084
15085         obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15086         if (&obj->base == NULL)
15087                 return ERR_PTR(-ENOENT);
15088
15089         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15090         if (IS_ERR(fb))
15091                 drm_gem_object_unreference_unlocked(&obj->base);
15092
15093         return fb;
15094 }
15095
15096 #ifndef CONFIG_DRM_FBDEV_EMULATION
15097 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15098 {
15099 }
15100 #endif
15101
15102 static const struct drm_mode_config_funcs intel_mode_funcs = {
15103         .fb_create = intel_user_framebuffer_create,
15104         .output_poll_changed = intel_fbdev_output_poll_changed,
15105         .atomic_check = intel_atomic_check,
15106         .atomic_commit = intel_atomic_commit,
15107         .atomic_state_alloc = intel_atomic_state_alloc,
15108         .atomic_state_clear = intel_atomic_state_clear,
15109 };
15110
15111 /**
15112  * intel_init_display_hooks - initialize the display modesetting hooks
15113  * @dev_priv: device private
15114  */
15115 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15116 {
15117         if (INTEL_INFO(dev_priv)->gen >= 9) {
15118                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15119                 dev_priv->display.get_initial_plane_config =
15120                         skylake_get_initial_plane_config;
15121                 dev_priv->display.crtc_compute_clock =
15122                         haswell_crtc_compute_clock;
15123                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15124                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15125         } else if (HAS_DDI(dev_priv)) {
15126                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15127                 dev_priv->display.get_initial_plane_config =
15128                         ironlake_get_initial_plane_config;
15129                 dev_priv->display.crtc_compute_clock =
15130                         haswell_crtc_compute_clock;
15131                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15132                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15133         } else if (HAS_PCH_SPLIT(dev_priv)) {
15134                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15135                 dev_priv->display.get_initial_plane_config =
15136                         ironlake_get_initial_plane_config;
15137                 dev_priv->display.crtc_compute_clock =
15138                         ironlake_crtc_compute_clock;
15139                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15140                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15141         } else if (IS_CHERRYVIEW(dev_priv)) {
15142                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15143                 dev_priv->display.get_initial_plane_config =
15144                         i9xx_get_initial_plane_config;
15145                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15146                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15147                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15148         } else if (IS_VALLEYVIEW(dev_priv)) {
15149                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15150                 dev_priv->display.get_initial_plane_config =
15151                         i9xx_get_initial_plane_config;
15152                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15153                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15154                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15155         } else if (IS_G4X(dev_priv)) {
15156                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15157                 dev_priv->display.get_initial_plane_config =
15158                         i9xx_get_initial_plane_config;
15159                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15160                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15161                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15162         } else if (IS_PINEVIEW(dev_priv)) {
15163                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15164                 dev_priv->display.get_initial_plane_config =
15165                         i9xx_get_initial_plane_config;
15166                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15167                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15168                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15169         } else if (!IS_GEN2(dev_priv)) {
15170                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15171                 dev_priv->display.get_initial_plane_config =
15172                         i9xx_get_initial_plane_config;
15173                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15174                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15175                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15176         } else {
15177                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15178                 dev_priv->display.get_initial_plane_config =
15179                         i9xx_get_initial_plane_config;
15180                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15181                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15182                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15183         }
15184
15185         /* Returns the core display clock speed */
15186         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15187                 dev_priv->display.get_display_clock_speed =
15188                         skylake_get_display_clock_speed;
15189         else if (IS_BROXTON(dev_priv))
15190                 dev_priv->display.get_display_clock_speed =
15191                         broxton_get_display_clock_speed;
15192         else if (IS_BROADWELL(dev_priv))
15193                 dev_priv->display.get_display_clock_speed =
15194                         broadwell_get_display_clock_speed;
15195         else if (IS_HASWELL(dev_priv))
15196                 dev_priv->display.get_display_clock_speed =
15197                         haswell_get_display_clock_speed;
15198         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15199                 dev_priv->display.get_display_clock_speed =
15200                         valleyview_get_display_clock_speed;
15201         else if (IS_GEN5(dev_priv))
15202                 dev_priv->display.get_display_clock_speed =
15203                         ilk_get_display_clock_speed;
15204         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15205                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15206                 dev_priv->display.get_display_clock_speed =
15207                         i945_get_display_clock_speed;
15208         else if (IS_GM45(dev_priv))
15209                 dev_priv->display.get_display_clock_speed =
15210                         gm45_get_display_clock_speed;
15211         else if (IS_CRESTLINE(dev_priv))
15212                 dev_priv->display.get_display_clock_speed =
15213                         i965gm_get_display_clock_speed;
15214         else if (IS_PINEVIEW(dev_priv))
15215                 dev_priv->display.get_display_clock_speed =
15216                         pnv_get_display_clock_speed;
15217         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15218                 dev_priv->display.get_display_clock_speed =
15219                         g33_get_display_clock_speed;
15220         else if (IS_I915G(dev_priv))
15221                 dev_priv->display.get_display_clock_speed =
15222                         i915_get_display_clock_speed;
15223         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15224                 dev_priv->display.get_display_clock_speed =
15225                         i9xx_misc_get_display_clock_speed;
15226         else if (IS_I915GM(dev_priv))
15227                 dev_priv->display.get_display_clock_speed =
15228                         i915gm_get_display_clock_speed;
15229         else if (IS_I865G(dev_priv))
15230                 dev_priv->display.get_display_clock_speed =
15231                         i865_get_display_clock_speed;
15232         else if (IS_I85X(dev_priv))
15233                 dev_priv->display.get_display_clock_speed =
15234                         i85x_get_display_clock_speed;
15235         else { /* 830 */
15236                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15237                 dev_priv->display.get_display_clock_speed =
15238                         i830_get_display_clock_speed;
15239         }
15240
15241         if (IS_GEN5(dev_priv)) {
15242                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15243         } else if (IS_GEN6(dev_priv)) {
15244                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15245         } else if (IS_IVYBRIDGE(dev_priv)) {
15246                 /* FIXME: detect B0+ stepping and use auto training */
15247                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15248         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15249                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15250         }
15251
15252         if (IS_BROADWELL(dev_priv)) {
15253                 dev_priv->display.modeset_commit_cdclk =
15254                         broadwell_modeset_commit_cdclk;
15255                 dev_priv->display.modeset_calc_cdclk =
15256                         broadwell_modeset_calc_cdclk;
15257         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15258                 dev_priv->display.modeset_commit_cdclk =
15259                         valleyview_modeset_commit_cdclk;
15260                 dev_priv->display.modeset_calc_cdclk =
15261                         valleyview_modeset_calc_cdclk;
15262         } else if (IS_BROXTON(dev_priv)) {
15263                 dev_priv->display.modeset_commit_cdclk =
15264                         bxt_modeset_commit_cdclk;
15265                 dev_priv->display.modeset_calc_cdclk =
15266                         bxt_modeset_calc_cdclk;
15267         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15268                 dev_priv->display.modeset_commit_cdclk =
15269                         skl_modeset_commit_cdclk;
15270                 dev_priv->display.modeset_calc_cdclk =
15271                         skl_modeset_calc_cdclk;
15272         }
15273
15274         switch (INTEL_INFO(dev_priv)->gen) {
15275         case 2:
15276                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15277                 break;
15278
15279         case 3:
15280                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15281                 break;
15282
15283         case 4:
15284         case 5:
15285                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15286                 break;
15287
15288         case 6:
15289                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15290                 break;
15291         case 7:
15292         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15293                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15294                 break;
15295         case 9:
15296                 /* Drop through - unsupported since execlist only. */
15297         default:
15298                 /* Default just returns -ENODEV to indicate unsupported */
15299                 dev_priv->display.queue_flip = intel_default_queue_flip;
15300         }
15301 }
15302
15303 /*
15304  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15305  * resume, or other times.  This quirk makes sure that's the case for
15306  * affected systems.
15307  */
15308 static void quirk_pipea_force(struct drm_device *dev)
15309 {
15310         struct drm_i915_private *dev_priv = to_i915(dev);
15311
15312         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15313         DRM_INFO("applying pipe a force quirk\n");
15314 }
15315
15316 static void quirk_pipeb_force(struct drm_device *dev)
15317 {
15318         struct drm_i915_private *dev_priv = to_i915(dev);
15319
15320         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15321         DRM_INFO("applying pipe b force quirk\n");
15322 }
15323
15324 /*
15325  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15326  */
15327 static void quirk_ssc_force_disable(struct drm_device *dev)
15328 {
15329         struct drm_i915_private *dev_priv = to_i915(dev);
15330         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15331         DRM_INFO("applying lvds SSC disable quirk\n");
15332 }
15333
15334 /*
15335  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15336  * brightness value
15337  */
15338 static void quirk_invert_brightness(struct drm_device *dev)
15339 {
15340         struct drm_i915_private *dev_priv = to_i915(dev);
15341         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15342         DRM_INFO("applying inverted panel brightness quirk\n");
15343 }
15344
15345 /* Some VBT's incorrectly indicate no backlight is present */
15346 static void quirk_backlight_present(struct drm_device *dev)
15347 {
15348         struct drm_i915_private *dev_priv = to_i915(dev);
15349         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15350         DRM_INFO("applying backlight present quirk\n");
15351 }
15352
15353 struct intel_quirk {
15354         int device;
15355         int subsystem_vendor;
15356         int subsystem_device;
15357         void (*hook)(struct drm_device *dev);
15358 };
15359
15360 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15361 struct intel_dmi_quirk {
15362         void (*hook)(struct drm_device *dev);
15363         const struct dmi_system_id (*dmi_id_list)[];
15364 };
15365
15366 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15367 {
15368         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15369         return 1;
15370 }
15371
15372 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15373         {
15374                 .dmi_id_list = &(const struct dmi_system_id[]) {
15375                         {
15376                                 .callback = intel_dmi_reverse_brightness,
15377                                 .ident = "NCR Corporation",
15378                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15379                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15380                                 },
15381                         },
15382                         { }  /* terminating entry */
15383                 },
15384                 .hook = quirk_invert_brightness,
15385         },
15386 };
15387
15388 static struct intel_quirk intel_quirks[] = {
15389         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15390         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15391
15392         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15393         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15394
15395         /* 830 needs to leave pipe A & dpll A up */
15396         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15397
15398         /* 830 needs to leave pipe B & dpll B up */
15399         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15400
15401         /* Lenovo U160 cannot use SSC on LVDS */
15402         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15403
15404         /* Sony Vaio Y cannot use SSC on LVDS */
15405         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15406
15407         /* Acer Aspire 5734Z must invert backlight brightness */
15408         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15409
15410         /* Acer/eMachines G725 */
15411         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15412
15413         /* Acer/eMachines e725 */
15414         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15415
15416         /* Acer/Packard Bell NCL20 */
15417         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15418
15419         /* Acer Aspire 4736Z */
15420         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15421
15422         /* Acer Aspire 5336 */
15423         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15424
15425         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15426         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15427
15428         /* Acer C720 Chromebook (Core i3 4005U) */
15429         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15430
15431         /* Apple Macbook 2,1 (Core 2 T7400) */
15432         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15433
15434         /* Apple Macbook 4,1 */
15435         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15436
15437         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15438         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15439
15440         /* HP Chromebook 14 (Celeron 2955U) */
15441         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15442
15443         /* Dell Chromebook 11 */
15444         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15445
15446         /* Dell Chromebook 11 (2015 version) */
15447         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15448 };
15449
15450 static void intel_init_quirks(struct drm_device *dev)
15451 {
15452         struct pci_dev *d = dev->pdev;
15453         int i;
15454
15455         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15456                 struct intel_quirk *q = &intel_quirks[i];
15457
15458                 if (d->device == q->device &&
15459                     (d->subsystem_vendor == q->subsystem_vendor ||
15460                      q->subsystem_vendor == PCI_ANY_ID) &&
15461                     (d->subsystem_device == q->subsystem_device ||
15462                      q->subsystem_device == PCI_ANY_ID))
15463                         q->hook(dev);
15464         }
15465         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15466                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15467                         intel_dmi_quirks[i].hook(dev);
15468         }
15469 }
15470
15471 /* Disable the VGA plane that we never use */
15472 static void i915_disable_vga(struct drm_device *dev)
15473 {
15474         struct drm_i915_private *dev_priv = to_i915(dev);
15475         u8 sr1;
15476         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15477
15478         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15479         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15480         outb(SR01, VGA_SR_INDEX);
15481         sr1 = inb(VGA_SR_DATA);
15482         outb(sr1 | 1<<5, VGA_SR_DATA);
15483         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15484         udelay(300);
15485
15486         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15487         POSTING_READ(vga_reg);
15488 }
15489
15490 void intel_modeset_init_hw(struct drm_device *dev)
15491 {
15492         struct drm_i915_private *dev_priv = to_i915(dev);
15493
15494         intel_update_cdclk(dev);
15495
15496         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15497
15498         intel_init_clock_gating(dev);
15499         intel_enable_gt_powersave(dev_priv);
15500 }
15501
15502 /*
15503  * Calculate what we think the watermarks should be for the state we've read
15504  * out of the hardware and then immediately program those watermarks so that
15505  * we ensure the hardware settings match our internal state.
15506  *
15507  * We can calculate what we think WM's should be by creating a duplicate of the
15508  * current state (which was constructed during hardware readout) and running it
15509  * through the atomic check code to calculate new watermark values in the
15510  * state object.
15511  */
15512 static void sanitize_watermarks(struct drm_device *dev)
15513 {
15514         struct drm_i915_private *dev_priv = to_i915(dev);
15515         struct drm_atomic_state *state;
15516         struct drm_crtc *crtc;
15517         struct drm_crtc_state *cstate;
15518         struct drm_modeset_acquire_ctx ctx;
15519         int ret;
15520         int i;
15521
15522         /* Only supported on platforms that use atomic watermark design */
15523         if (!dev_priv->display.optimize_watermarks)
15524                 return;
15525
15526         /*
15527          * We need to hold connection_mutex before calling duplicate_state so
15528          * that the connector loop is protected.
15529          */
15530         drm_modeset_acquire_init(&ctx, 0);
15531 retry:
15532         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15533         if (ret == -EDEADLK) {
15534                 drm_modeset_backoff(&ctx);
15535                 goto retry;
15536         } else if (WARN_ON(ret)) {
15537                 goto fail;
15538         }
15539
15540         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15541         if (WARN_ON(IS_ERR(state)))
15542                 goto fail;
15543
15544         /*
15545          * Hardware readout is the only time we don't want to calculate
15546          * intermediate watermarks (since we don't trust the current
15547          * watermarks).
15548          */
15549         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15550
15551         ret = intel_atomic_check(dev, state);
15552         if (ret) {
15553                 /*
15554                  * If we fail here, it means that the hardware appears to be
15555                  * programmed in a way that shouldn't be possible, given our
15556                  * understanding of watermark requirements.  This might mean a
15557                  * mistake in the hardware readout code or a mistake in the
15558                  * watermark calculations for a given platform.  Raise a WARN
15559                  * so that this is noticeable.
15560                  *
15561                  * If this actually happens, we'll have to just leave the
15562                  * BIOS-programmed watermarks untouched and hope for the best.
15563                  */
15564                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15565                 goto fail;
15566         }
15567
15568         /* Write calculated watermark values back */
15569         for_each_crtc_in_state(state, crtc, cstate, i) {
15570                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15571
15572                 cs->wm.need_postvbl_update = true;
15573                 dev_priv->display.optimize_watermarks(cs);
15574         }
15575
15576         drm_atomic_state_free(state);
15577 fail:
15578         drm_modeset_drop_locks(&ctx);
15579         drm_modeset_acquire_fini(&ctx);
15580 }
15581
15582 void intel_modeset_init(struct drm_device *dev)
15583 {
15584         struct drm_i915_private *dev_priv = to_i915(dev);
15585         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15586         int sprite, ret;
15587         enum pipe pipe;
15588         struct intel_crtc *crtc;
15589
15590         drm_mode_config_init(dev);
15591
15592         dev->mode_config.min_width = 0;
15593         dev->mode_config.min_height = 0;
15594
15595         dev->mode_config.preferred_depth = 24;
15596         dev->mode_config.prefer_shadow = 1;
15597
15598         dev->mode_config.allow_fb_modifiers = true;
15599
15600         dev->mode_config.funcs = &intel_mode_funcs;
15601
15602         intel_init_quirks(dev);
15603
15604         intel_init_pm(dev);
15605
15606         if (INTEL_INFO(dev)->num_pipes == 0)
15607                 return;
15608
15609         /*
15610          * There may be no VBT; and if the BIOS enabled SSC we can
15611          * just keep using it to avoid unnecessary flicker.  Whereas if the
15612          * BIOS isn't using it, don't assume it will work even if the VBT
15613          * indicates as much.
15614          */
15615         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15616                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15617                                             DREF_SSC1_ENABLE);
15618
15619                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15620                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15621                                      bios_lvds_use_ssc ? "en" : "dis",
15622                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15623                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15624                 }
15625         }
15626
15627         if (IS_GEN2(dev)) {
15628                 dev->mode_config.max_width = 2048;
15629                 dev->mode_config.max_height = 2048;
15630         } else if (IS_GEN3(dev)) {
15631                 dev->mode_config.max_width = 4096;
15632                 dev->mode_config.max_height = 4096;
15633         } else {
15634                 dev->mode_config.max_width = 8192;
15635                 dev->mode_config.max_height = 8192;
15636         }
15637
15638         if (IS_845G(dev) || IS_I865G(dev)) {
15639                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15640                 dev->mode_config.cursor_height = 1023;
15641         } else if (IS_GEN2(dev)) {
15642                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15643                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15644         } else {
15645                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15646                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15647         }
15648
15649         dev->mode_config.fb_base = ggtt->mappable_base;
15650
15651         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15652                       INTEL_INFO(dev)->num_pipes,
15653                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15654
15655         for_each_pipe(dev_priv, pipe) {
15656                 intel_crtc_init(dev, pipe);
15657                 for_each_sprite(dev_priv, pipe, sprite) {
15658                         ret = intel_plane_init(dev, pipe, sprite);
15659                         if (ret)
15660                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15661                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15662                 }
15663         }
15664
15665         intel_update_czclk(dev_priv);
15666         intel_update_cdclk(dev);
15667
15668         intel_shared_dpll_init(dev);
15669
15670         if (dev_priv->max_cdclk_freq == 0)
15671                 intel_update_max_cdclk(dev);
15672
15673         /* Just disable it once at startup */
15674         i915_disable_vga(dev);
15675         intel_setup_outputs(dev);
15676
15677         drm_modeset_lock_all(dev);
15678         intel_modeset_setup_hw_state(dev);
15679         drm_modeset_unlock_all(dev);
15680
15681         for_each_intel_crtc(dev, crtc) {
15682                 struct intel_initial_plane_config plane_config = {};
15683
15684                 if (!crtc->active)
15685                         continue;
15686
15687                 /*
15688                  * Note that reserving the BIOS fb up front prevents us
15689                  * from stuffing other stolen allocations like the ring
15690                  * on top.  This prevents some ugliness at boot time, and
15691                  * can even allow for smooth boot transitions if the BIOS
15692                  * fb is large enough for the active pipe configuration.
15693                  */
15694                 dev_priv->display.get_initial_plane_config(crtc,
15695                                                            &plane_config);
15696
15697                 /*
15698                  * If the fb is shared between multiple heads, we'll
15699                  * just get the first one.
15700                  */
15701                 intel_find_initial_plane_obj(crtc, &plane_config);
15702         }
15703
15704         /*
15705          * Make sure hardware watermarks really match the state we read out.
15706          * Note that we need to do this after reconstructing the BIOS fb's
15707          * since the watermark calculation done here will use pstate->fb.
15708          */
15709         sanitize_watermarks(dev);
15710 }
15711
15712 static void intel_enable_pipe_a(struct drm_device *dev)
15713 {
15714         struct intel_connector *connector;
15715         struct drm_connector *crt = NULL;
15716         struct intel_load_detect_pipe load_detect_temp;
15717         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15718
15719         /* We can't just switch on the pipe A, we need to set things up with a
15720          * proper mode and output configuration. As a gross hack, enable pipe A
15721          * by enabling the load detect pipe once. */
15722         for_each_intel_connector(dev, connector) {
15723                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15724                         crt = &connector->base;
15725                         break;
15726                 }
15727         }
15728
15729         if (!crt)
15730                 return;
15731
15732         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15733                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15734 }
15735
15736 static bool
15737 intel_check_plane_mapping(struct intel_crtc *crtc)
15738 {
15739         struct drm_device *dev = crtc->base.dev;
15740         struct drm_i915_private *dev_priv = to_i915(dev);
15741         u32 val;
15742
15743         if (INTEL_INFO(dev)->num_pipes == 1)
15744                 return true;
15745
15746         val = I915_READ(DSPCNTR(!crtc->plane));
15747
15748         if ((val & DISPLAY_PLANE_ENABLE) &&
15749             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15750                 return false;
15751
15752         return true;
15753 }
15754
15755 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15756 {
15757         struct drm_device *dev = crtc->base.dev;
15758         struct intel_encoder *encoder;
15759
15760         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15761                 return true;
15762
15763         return false;
15764 }
15765
15766 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15767 {
15768         struct drm_device *dev = encoder->base.dev;
15769         struct intel_connector *connector;
15770
15771         for_each_connector_on_encoder(dev, &encoder->base, connector)
15772                 return true;
15773
15774         return false;
15775 }
15776
15777 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15778 {
15779         struct drm_device *dev = crtc->base.dev;
15780         struct drm_i915_private *dev_priv = to_i915(dev);
15781         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15782
15783         /* Clear any frame start delays used for debugging left by the BIOS */
15784         if (!transcoder_is_dsi(cpu_transcoder)) {
15785                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15786
15787                 I915_WRITE(reg,
15788                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15789         }
15790
15791         /* restore vblank interrupts to correct state */
15792         drm_crtc_vblank_reset(&crtc->base);
15793         if (crtc->active) {
15794                 struct intel_plane *plane;
15795
15796                 drm_crtc_vblank_on(&crtc->base);
15797
15798                 /* Disable everything but the primary plane */
15799                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15800                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15801                                 continue;
15802
15803                         plane->disable_plane(&plane->base, &crtc->base);
15804                 }
15805         }
15806
15807         /* We need to sanitize the plane -> pipe mapping first because this will
15808          * disable the crtc (and hence change the state) if it is wrong. Note
15809          * that gen4+ has a fixed plane -> pipe mapping.  */
15810         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15811                 bool plane;
15812
15813                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15814                               crtc->base.base.id, crtc->base.name);
15815
15816                 /* Pipe has the wrong plane attached and the plane is active.
15817                  * Temporarily change the plane mapping and disable everything
15818                  * ...  */
15819                 plane = crtc->plane;
15820                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15821                 crtc->plane = !plane;
15822                 intel_crtc_disable_noatomic(&crtc->base);
15823                 crtc->plane = plane;
15824         }
15825
15826         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15827             crtc->pipe == PIPE_A && !crtc->active) {
15828                 /* BIOS forgot to enable pipe A, this mostly happens after
15829                  * resume. Force-enable the pipe to fix this, the update_dpms
15830                  * call below we restore the pipe to the right state, but leave
15831                  * the required bits on. */
15832                 intel_enable_pipe_a(dev);
15833         }
15834
15835         /* Adjust the state of the output pipe according to whether we
15836          * have active connectors/encoders. */
15837         if (crtc->active && !intel_crtc_has_encoders(crtc))
15838                 intel_crtc_disable_noatomic(&crtc->base);
15839
15840         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15841                 /*
15842                  * We start out with underrun reporting disabled to avoid races.
15843                  * For correct bookkeeping mark this on active crtcs.
15844                  *
15845                  * Also on gmch platforms we dont have any hardware bits to
15846                  * disable the underrun reporting. Which means we need to start
15847                  * out with underrun reporting disabled also on inactive pipes,
15848                  * since otherwise we'll complain about the garbage we read when
15849                  * e.g. coming up after runtime pm.
15850                  *
15851                  * No protection against concurrent access is required - at
15852                  * worst a fifo underrun happens which also sets this to false.
15853                  */
15854                 crtc->cpu_fifo_underrun_disabled = true;
15855                 crtc->pch_fifo_underrun_disabled = true;
15856         }
15857 }
15858
15859 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15860 {
15861         struct intel_connector *connector;
15862         struct drm_device *dev = encoder->base.dev;
15863
15864         /* We need to check both for a crtc link (meaning that the
15865          * encoder is active and trying to read from a pipe) and the
15866          * pipe itself being active. */
15867         bool has_active_crtc = encoder->base.crtc &&
15868                 to_intel_crtc(encoder->base.crtc)->active;
15869
15870         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15871                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15872                               encoder->base.base.id,
15873                               encoder->base.name);
15874
15875                 /* Connector is active, but has no active pipe. This is
15876                  * fallout from our resume register restoring. Disable
15877                  * the encoder manually again. */
15878                 if (encoder->base.crtc) {
15879                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15880                                       encoder->base.base.id,
15881                                       encoder->base.name);
15882                         encoder->disable(encoder);
15883                         if (encoder->post_disable)
15884                                 encoder->post_disable(encoder);
15885                 }
15886                 encoder->base.crtc = NULL;
15887
15888                 /* Inconsistent output/port/pipe state happens presumably due to
15889                  * a bug in one of the get_hw_state functions. Or someplace else
15890                  * in our code, like the register restore mess on resume. Clamp
15891                  * things to off as a safer default. */
15892                 for_each_intel_connector(dev, connector) {
15893                         if (connector->encoder != encoder)
15894                                 continue;
15895                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15896                         connector->base.encoder = NULL;
15897                 }
15898         }
15899         /* Enabled encoders without active connectors will be fixed in
15900          * the crtc fixup. */
15901 }
15902
15903 void i915_redisable_vga_power_on(struct drm_device *dev)
15904 {
15905         struct drm_i915_private *dev_priv = to_i915(dev);
15906         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15907
15908         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15909                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15910                 i915_disable_vga(dev);
15911         }
15912 }
15913
15914 void i915_redisable_vga(struct drm_device *dev)
15915 {
15916         struct drm_i915_private *dev_priv = to_i915(dev);
15917
15918         /* This function can be called both from intel_modeset_setup_hw_state or
15919          * at a very early point in our resume sequence, where the power well
15920          * structures are not yet restored. Since this function is at a very
15921          * paranoid "someone might have enabled VGA while we were not looking"
15922          * level, just check if the power well is enabled instead of trying to
15923          * follow the "don't touch the power well if we don't need it" policy
15924          * the rest of the driver uses. */
15925         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15926                 return;
15927
15928         i915_redisable_vga_power_on(dev);
15929
15930         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15931 }
15932
15933 static bool primary_get_hw_state(struct intel_plane *plane)
15934 {
15935         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15936
15937         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15938 }
15939
15940 /* FIXME read out full plane state for all planes */
15941 static void readout_plane_state(struct intel_crtc *crtc)
15942 {
15943         struct drm_plane *primary = crtc->base.primary;
15944         struct intel_plane_state *plane_state =
15945                 to_intel_plane_state(primary->state);
15946
15947         plane_state->visible = crtc->active &&
15948                 primary_get_hw_state(to_intel_plane(primary));
15949
15950         if (plane_state->visible)
15951                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15952 }
15953
15954 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15955 {
15956         struct drm_i915_private *dev_priv = to_i915(dev);
15957         enum pipe pipe;
15958         struct intel_crtc *crtc;
15959         struct intel_encoder *encoder;
15960         struct intel_connector *connector;
15961         int i;
15962
15963         dev_priv->active_crtcs = 0;
15964
15965         for_each_intel_crtc(dev, crtc) {
15966                 struct intel_crtc_state *crtc_state = crtc->config;
15967                 int pixclk = 0;
15968
15969                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15970                 memset(crtc_state, 0, sizeof(*crtc_state));
15971                 crtc_state->base.crtc = &crtc->base;
15972
15973                 crtc_state->base.active = crtc_state->base.enable =
15974                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15975
15976                 crtc->base.enabled = crtc_state->base.enable;
15977                 crtc->active = crtc_state->base.active;
15978
15979                 if (crtc_state->base.active) {
15980                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15981
15982                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15983                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15984                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15985                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15986                         else
15987                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15988
15989                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15990                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15991                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15992                 }
15993
15994                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15995
15996                 readout_plane_state(crtc);
15997
15998                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15999                               crtc->base.base.id, crtc->base.name,
16000                               crtc->active ? "enabled" : "disabled");
16001         }
16002
16003         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16004                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16005
16006                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16007                                                   &pll->config.hw_state);
16008                 pll->config.crtc_mask = 0;
16009                 for_each_intel_crtc(dev, crtc) {
16010                         if (crtc->active && crtc->config->shared_dpll == pll)
16011                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16012                 }
16013                 pll->active_mask = pll->config.crtc_mask;
16014
16015                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16016                               pll->name, pll->config.crtc_mask, pll->on);
16017         }
16018
16019         for_each_intel_encoder(dev, encoder) {
16020                 pipe = 0;
16021
16022                 if (encoder->get_hw_state(encoder, &pipe)) {
16023                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16024                         encoder->base.crtc = &crtc->base;
16025                         crtc->config->output_types |= 1 << encoder->type;
16026                         encoder->get_config(encoder, crtc->config);
16027                 } else {
16028                         encoder->base.crtc = NULL;
16029                 }
16030
16031                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16032                               encoder->base.base.id,
16033                               encoder->base.name,
16034                               encoder->base.crtc ? "enabled" : "disabled",
16035                               pipe_name(pipe));
16036         }
16037
16038         for_each_intel_connector(dev, connector) {
16039                 if (connector->get_hw_state(connector)) {
16040                         connector->base.dpms = DRM_MODE_DPMS_ON;
16041
16042                         encoder = connector->encoder;
16043                         connector->base.encoder = &encoder->base;
16044
16045                         if (encoder->base.crtc &&
16046                             encoder->base.crtc->state->active) {
16047                                 /*
16048                                  * This has to be done during hardware readout
16049                                  * because anything calling .crtc_disable may
16050                                  * rely on the connector_mask being accurate.
16051                                  */
16052                                 encoder->base.crtc->state->connector_mask |=
16053                                         1 << drm_connector_index(&connector->base);
16054                                 encoder->base.crtc->state->encoder_mask |=
16055                                         1 << drm_encoder_index(&encoder->base);
16056                         }
16057
16058                 } else {
16059                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16060                         connector->base.encoder = NULL;
16061                 }
16062                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16063                               connector->base.base.id,
16064                               connector->base.name,
16065                               connector->base.encoder ? "enabled" : "disabled");
16066         }
16067
16068         for_each_intel_crtc(dev, crtc) {
16069                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16070
16071                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16072                 if (crtc->base.state->active) {
16073                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16074                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16075                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16076
16077                         /*
16078                          * The initial mode needs to be set in order to keep
16079                          * the atomic core happy. It wants a valid mode if the
16080                          * crtc's enabled, so we do the above call.
16081                          *
16082                          * At this point some state updated by the connectors
16083                          * in their ->detect() callback has not run yet, so
16084                          * no recalculation can be done yet.
16085                          *
16086                          * Even if we could do a recalculation and modeset
16087                          * right now it would cause a double modeset if
16088                          * fbdev or userspace chooses a different initial mode.
16089                          *
16090                          * If that happens, someone indicated they wanted a
16091                          * mode change, which means it's safe to do a full
16092                          * recalculation.
16093                          */
16094                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16095
16096                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16097                         update_scanline_offset(crtc);
16098                 }
16099
16100                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16101         }
16102 }
16103
16104 /* Scan out the current hw modeset state,
16105  * and sanitizes it to the current state
16106  */
16107 static void
16108 intel_modeset_setup_hw_state(struct drm_device *dev)
16109 {
16110         struct drm_i915_private *dev_priv = to_i915(dev);
16111         enum pipe pipe;
16112         struct intel_crtc *crtc;
16113         struct intel_encoder *encoder;
16114         int i;
16115
16116         intel_modeset_readout_hw_state(dev);
16117
16118         /* HW state is read out, now we need to sanitize this mess. */
16119         for_each_intel_encoder(dev, encoder) {
16120                 intel_sanitize_encoder(encoder);
16121         }
16122
16123         for_each_pipe(dev_priv, pipe) {
16124                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16125                 intel_sanitize_crtc(crtc);
16126                 intel_dump_pipe_config(crtc, crtc->config,
16127                                        "[setup_hw_state]");
16128         }
16129
16130         intel_modeset_update_connector_atomic_state(dev);
16131
16132         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16133                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16134
16135                 if (!pll->on || pll->active_mask)
16136                         continue;
16137
16138                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16139
16140                 pll->funcs.disable(dev_priv, pll);
16141                 pll->on = false;
16142         }
16143
16144         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16145                 vlv_wm_get_hw_state(dev);
16146         else if (IS_GEN9(dev))
16147                 skl_wm_get_hw_state(dev);
16148         else if (HAS_PCH_SPLIT(dev))
16149                 ilk_wm_get_hw_state(dev);
16150
16151         for_each_intel_crtc(dev, crtc) {
16152                 unsigned long put_domains;
16153
16154                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16155                 if (WARN_ON(put_domains))
16156                         modeset_put_power_domains(dev_priv, put_domains);
16157         }
16158         intel_display_set_init_power(dev_priv, false);
16159
16160         intel_fbc_init_pipe_state(dev_priv);
16161 }
16162
16163 void intel_display_resume(struct drm_device *dev)
16164 {
16165         struct drm_i915_private *dev_priv = to_i915(dev);
16166         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16167         struct drm_modeset_acquire_ctx ctx;
16168         int ret;
16169         bool setup = false;
16170
16171         dev_priv->modeset_restore_state = NULL;
16172
16173         /*
16174          * This is a cludge because with real atomic modeset mode_config.mutex
16175          * won't be taken. Unfortunately some probed state like
16176          * audio_codec_enable is still protected by mode_config.mutex, so lock
16177          * it here for now.
16178          */
16179         mutex_lock(&dev->mode_config.mutex);
16180         drm_modeset_acquire_init(&ctx, 0);
16181
16182 retry:
16183         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16184
16185         if (ret == 0 && !setup) {
16186                 setup = true;
16187
16188                 intel_modeset_setup_hw_state(dev);
16189                 i915_redisable_vga(dev);
16190         }
16191
16192         if (ret == 0 && state) {
16193                 struct drm_crtc_state *crtc_state;
16194                 struct drm_crtc *crtc;
16195                 int i;
16196
16197                 state->acquire_ctx = &ctx;
16198
16199                 /* ignore any reset values/BIOS leftovers in the WM registers */
16200                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16201
16202                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16203                         /*
16204                          * Force recalculation even if we restore
16205                          * current state. With fast modeset this may not result
16206                          * in a modeset when the state is compatible.
16207                          */
16208                         crtc_state->mode_changed = true;
16209                 }
16210
16211                 ret = drm_atomic_commit(state);
16212         }
16213
16214         if (ret == -EDEADLK) {
16215                 drm_modeset_backoff(&ctx);
16216                 goto retry;
16217         }
16218
16219         drm_modeset_drop_locks(&ctx);
16220         drm_modeset_acquire_fini(&ctx);
16221         mutex_unlock(&dev->mode_config.mutex);
16222
16223         if (ret) {
16224                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16225                 drm_atomic_state_free(state);
16226         }
16227 }
16228
16229 void intel_modeset_gem_init(struct drm_device *dev)
16230 {
16231         struct drm_i915_private *dev_priv = to_i915(dev);
16232         struct drm_crtc *c;
16233         struct drm_i915_gem_object *obj;
16234         int ret;
16235
16236         intel_init_gt_powersave(dev_priv);
16237
16238         intel_modeset_init_hw(dev);
16239
16240         intel_setup_overlay(dev_priv);
16241
16242         /*
16243          * Make sure any fbs we allocated at startup are properly
16244          * pinned & fenced.  When we do the allocation it's too early
16245          * for this.
16246          */
16247         for_each_crtc(dev, c) {
16248                 obj = intel_fb_obj(c->primary->fb);
16249                 if (obj == NULL)
16250                         continue;
16251
16252                 mutex_lock(&dev->struct_mutex);
16253                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16254                                                  c->primary->state->rotation);
16255                 mutex_unlock(&dev->struct_mutex);
16256                 if (ret) {
16257                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16258                                   to_intel_crtc(c)->pipe);
16259                         drm_framebuffer_unreference(c->primary->fb);
16260                         c->primary->fb = NULL;
16261                         c->primary->crtc = c->primary->state->crtc = NULL;
16262                         update_state_fb(c->primary);
16263                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16264                 }
16265         }
16266 }
16267
16268 int intel_connector_register(struct drm_connector *connector)
16269 {
16270         struct intel_connector *intel_connector = to_intel_connector(connector);
16271         int ret;
16272
16273         ret = intel_backlight_device_register(intel_connector);
16274         if (ret)
16275                 goto err;
16276
16277         return 0;
16278
16279 err:
16280         return ret;
16281 }
16282
16283 void intel_connector_unregister(struct drm_connector *connector)
16284 {
16285         struct intel_connector *intel_connector = to_intel_connector(connector);
16286
16287         intel_backlight_device_unregister(intel_connector);
16288         intel_panel_destroy_backlight(connector);
16289 }
16290
16291 void intel_modeset_cleanup(struct drm_device *dev)
16292 {
16293         struct drm_i915_private *dev_priv = to_i915(dev);
16294
16295         intel_disable_gt_powersave(dev_priv);
16296
16297         /*
16298          * Interrupts and polling as the first thing to avoid creating havoc.
16299          * Too much stuff here (turning of connectors, ...) would
16300          * experience fancy races otherwise.
16301          */
16302         intel_irq_uninstall(dev_priv);
16303
16304         /*
16305          * Due to the hpd irq storm handling the hotplug work can re-arm the
16306          * poll handlers. Hence disable polling after hpd handling is shut down.
16307          */
16308         drm_kms_helper_poll_fini(dev);
16309
16310         intel_unregister_dsm_handler();
16311
16312         intel_fbc_global_disable(dev_priv);
16313
16314         /* flush any delayed tasks or pending work */
16315         flush_scheduled_work();
16316
16317         drm_mode_config_cleanup(dev);
16318
16319         intel_cleanup_overlay(dev_priv);
16320
16321         intel_cleanup_gt_powersave(dev_priv);
16322
16323         intel_teardown_gmbus(dev);
16324 }
16325
16326 void intel_connector_attach_encoder(struct intel_connector *connector,
16327                                     struct intel_encoder *encoder)
16328 {
16329         connector->encoder = encoder;
16330         drm_mode_connector_attach_encoder(&connector->base,
16331                                           &encoder->base);
16332 }
16333
16334 /*
16335  * set vga decode state - true == enable VGA decode
16336  */
16337 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16338 {
16339         struct drm_i915_private *dev_priv = to_i915(dev);
16340         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16341         u16 gmch_ctrl;
16342
16343         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16344                 DRM_ERROR("failed to read control word\n");
16345                 return -EIO;
16346         }
16347
16348         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16349                 return 0;
16350
16351         if (state)
16352                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16353         else
16354                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16355
16356         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16357                 DRM_ERROR("failed to write control word\n");
16358                 return -EIO;
16359         }
16360
16361         return 0;
16362 }
16363
16364 struct intel_display_error_state {
16365
16366         u32 power_well_driver;
16367
16368         int num_transcoders;
16369
16370         struct intel_cursor_error_state {
16371                 u32 control;
16372                 u32 position;
16373                 u32 base;
16374                 u32 size;
16375         } cursor[I915_MAX_PIPES];
16376
16377         struct intel_pipe_error_state {
16378                 bool power_domain_on;
16379                 u32 source;
16380                 u32 stat;
16381         } pipe[I915_MAX_PIPES];
16382
16383         struct intel_plane_error_state {
16384                 u32 control;
16385                 u32 stride;
16386                 u32 size;
16387                 u32 pos;
16388                 u32 addr;
16389                 u32 surface;
16390                 u32 tile_offset;
16391         } plane[I915_MAX_PIPES];
16392
16393         struct intel_transcoder_error_state {
16394                 bool power_domain_on;
16395                 enum transcoder cpu_transcoder;
16396
16397                 u32 conf;
16398
16399                 u32 htotal;
16400                 u32 hblank;
16401                 u32 hsync;
16402                 u32 vtotal;
16403                 u32 vblank;
16404                 u32 vsync;
16405         } transcoder[4];
16406 };
16407
16408 struct intel_display_error_state *
16409 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16410 {
16411         struct intel_display_error_state *error;
16412         int transcoders[] = {
16413                 TRANSCODER_A,
16414                 TRANSCODER_B,
16415                 TRANSCODER_C,
16416                 TRANSCODER_EDP,
16417         };
16418         int i;
16419
16420         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16421                 return NULL;
16422
16423         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16424         if (error == NULL)
16425                 return NULL;
16426
16427         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16428                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16429
16430         for_each_pipe(dev_priv, i) {
16431                 error->pipe[i].power_domain_on =
16432                         __intel_display_power_is_enabled(dev_priv,
16433                                                          POWER_DOMAIN_PIPE(i));
16434                 if (!error->pipe[i].power_domain_on)
16435                         continue;
16436
16437                 error->cursor[i].control = I915_READ(CURCNTR(i));
16438                 error->cursor[i].position = I915_READ(CURPOS(i));
16439                 error->cursor[i].base = I915_READ(CURBASE(i));
16440
16441                 error->plane[i].control = I915_READ(DSPCNTR(i));
16442                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16443                 if (INTEL_GEN(dev_priv) <= 3) {
16444                         error->plane[i].size = I915_READ(DSPSIZE(i));
16445                         error->plane[i].pos = I915_READ(DSPPOS(i));
16446                 }
16447                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16448                         error->plane[i].addr = I915_READ(DSPADDR(i));
16449                 if (INTEL_GEN(dev_priv) >= 4) {
16450                         error->plane[i].surface = I915_READ(DSPSURF(i));
16451                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16452                 }
16453
16454                 error->pipe[i].source = I915_READ(PIPESRC(i));
16455
16456                 if (HAS_GMCH_DISPLAY(dev_priv))
16457                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16458         }
16459
16460         /* Note: this does not include DSI transcoders. */
16461         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16462         if (HAS_DDI(dev_priv))
16463                 error->num_transcoders++; /* Account for eDP. */
16464
16465         for (i = 0; i < error->num_transcoders; i++) {
16466                 enum transcoder cpu_transcoder = transcoders[i];
16467
16468                 error->transcoder[i].power_domain_on =
16469                         __intel_display_power_is_enabled(dev_priv,
16470                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16471                 if (!error->transcoder[i].power_domain_on)
16472                         continue;
16473
16474                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16475
16476                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16477                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16478                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16479                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16480                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16481                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16482                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16483         }
16484
16485         return error;
16486 }
16487
16488 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16489
16490 void
16491 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16492                                 struct drm_device *dev,
16493                                 struct intel_display_error_state *error)
16494 {
16495         struct drm_i915_private *dev_priv = to_i915(dev);
16496         int i;
16497
16498         if (!error)
16499                 return;
16500
16501         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16502         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16503                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16504                            error->power_well_driver);
16505         for_each_pipe(dev_priv, i) {
16506                 err_printf(m, "Pipe [%d]:\n", i);
16507                 err_printf(m, "  Power: %s\n",
16508                            onoff(error->pipe[i].power_domain_on));
16509                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16510                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16511
16512                 err_printf(m, "Plane [%d]:\n", i);
16513                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16514                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16515                 if (INTEL_INFO(dev)->gen <= 3) {
16516                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16517                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16518                 }
16519                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16520                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16521                 if (INTEL_INFO(dev)->gen >= 4) {
16522                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16523                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16524                 }
16525
16526                 err_printf(m, "Cursor [%d]:\n", i);
16527                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16528                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16529                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16530         }
16531
16532         for (i = 0; i < error->num_transcoders; i++) {
16533                 err_printf(m, "CPU transcoder: %s\n",
16534                            transcoder_name(error->transcoder[i].cpu_transcoder));
16535                 err_printf(m, "  Power: %s\n",
16536                            onoff(error->transcoder[i].power_domain_on));
16537                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16538                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16539                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16540                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16541                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16542                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16543                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16544         }
16545 }