drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 void
 113 intel_edp_link_config(struct intel_encoder *intel_encoder,
 114                        int *lane_num, int *link_bw)
 115 {
 116         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 117
 118         *lane_num = intel_dp->lane_count;
 119         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 127         struct intel_connector *intel_connector = intel_dp->attached_connector;
 128
 129         if (intel_connector->panel.fixed_mode)
 130                 return intel_connector->panel.fixed_mode->clock;
 131         else
 132                 return mode->clock;
 133 }
 134
 135 static int
 136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 137 {
 138         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 139
 140         switch (max_link_bw) {
 141         case DP_LINK_BW_1_62:
 142         case DP_LINK_BW_2_7:
 143                 break;
 144         default:
 145                 max_link_bw = DP_LINK_BW_1_62;
 146                 break;
 147         }
 148         return max_link_bw;
 149 }
 150
 151 /*
 152  * The units on the numbers in the next two are... bizarre.  Examples will
 153  * make it clearer; this one parallels an example in the eDP spec.
 154  *
 155  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 156  *
 157  *     270000 * 1 * 8 / 10 == 216000
 158  *
 159  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 160  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 161  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 162  * 119000.  At 18bpp that's 2142000 kilobits per second.
 163  *
 164  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 165  * get the result in decakilobits instead of kilobits.
 166  */
 167
 168 static int
 169 intel_dp_link_required(int pixel_clock, int bpp)
 170 {
 171         return (pixel_clock * bpp + 9) / 10;
 172 }
 173
 174 static int
 175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 176 {
 177         return (max_link_clock * max_lanes * 8) / 10;
 178 }
 179
 180 static int
 181 intel_dp_mode_valid(struct drm_connector *connector,
 182                     struct drm_display_mode *mode)
 183 {
 184         struct intel_dp *intel_dp = intel_attached_dp(connector);
 185         struct intel_connector *intel_connector = to_intel_connector(connector);
 186         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 187         int target_clock = mode->clock;
 188         int max_rate, mode_rate, max_lanes, max_link_clock;
 189
 190         if (is_edp(intel_dp) && fixed_mode) {
 191                 if (mode->hdisplay > fixed_mode->hdisplay)
 192                         return MODE_PANEL;
 193
 194                 if (mode->vdisplay > fixed_mode->vdisplay)
 195                         return MODE_PANEL;
 196         }
 197
 198         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 199         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 200
 201         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 202         mode_rate = intel_dp_link_required(target_clock, 18);
 203
 204         if (mode_rate > max_rate)
 205                 return MODE_CLOCK_HIGH;
 206
 207         if (mode->clock < 10000)
 208                 return MODE_CLOCK_LOW;
 209
 210         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 211                 return MODE_H_ILLEGAL;
 212
 213         return MODE_OK;
 214 }
 215
 216 static uint32_t
 217 pack_aux(uint8_t *src, int src_bytes)
 218 {
 219         int     i;
 220         uint32_t v = 0;
 221
 222         if (src_bytes > 4)
 223                 src_bytes = 4;
 224         for (i = 0; i < src_bytes; i++)
 225                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 226         return v;
 227 }
 228
 229 static void
 230 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 231 {
 232         int i;
 233         if (dst_bytes > 4)
 234                 dst_bytes = 4;
 235         for (i = 0; i < dst_bytes; i++)
 236                 dst[i] = src >> ((3-i) * 8);
 237 }
 238
 239 /* hrawclock is 1/4 the FSB frequency */
 240 static int
 241 intel_hrawclk(struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244         uint32_t clkcfg;
 245
 246         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 247         if (IS_VALLEYVIEW(dev))
 248                 return 200;
 249
 250         clkcfg = I915_READ(CLKCFG);
 251         switch (clkcfg & CLKCFG_FSB_MASK) {
 252         case CLKCFG_FSB_400:
 253                 return 100;
 254         case CLKCFG_FSB_533:
 255                 return 133;
 256         case CLKCFG_FSB_667:
 257                 return 166;
 258         case CLKCFG_FSB_800:
 259                 return 200;
 260         case CLKCFG_FSB_1067:
 261                 return 266;
 262         case CLKCFG_FSB_1333:
 263                 return 333;
 264         /* these two are just a guess; one of them might be right */
 265         case CLKCFG_FSB_1600:
 266         case CLKCFG_FSB_1600_ALT:
 267                 return 400;
 268         default:
 269                 return 133;
 270         }
 271 }
 272
 273 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 274 {
 275         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         u32 pp_stat_reg;
 278
 279         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 280         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 281 }
 282
 283 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 284 {
 285         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         u32 pp_ctrl_reg;
 288
 289         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 290         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 291 }
 292
 293 static void
 294 intel_dp_check_edp(struct intel_dp *intel_dp)
 295 {
 296         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         u32 pp_stat_reg, pp_ctrl_reg;
 299
 300         if (!is_edp(intel_dp))
 301                 return;
 302
 303         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 304         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 305
 306         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 307                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 308                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 309                                 I915_READ(pp_stat_reg),
 310                                 I915_READ(pp_ctrl_reg));
 311         }
 312 }
 313
 314 static uint32_t
 315 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 316 {
 317         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 318         struct drm_device *dev = intel_dig_port->base.base.dev;
 319         struct drm_i915_private *dev_priv = dev->dev_private;
 320         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 321         uint32_t status;
 322         bool done;
 323
 324 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 325         if (has_aux_irq)
 326                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 327                                           msecs_to_jiffies(10));
 328         else
 329                 done = wait_for_atomic(C, 10) == 0;
 330         if (!done)
 331                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 332                           has_aux_irq);
 333 #undef C
 334
 335         return status;
 336 }
 337
 338 static int
 339 intel_dp_aux_ch(struct intel_dp *intel_dp,
 340                 uint8_t *send, int send_bytes,
 341                 uint8_t *recv, int recv_size)
 342 {
 343         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 344         struct drm_device *dev = intel_dig_port->base.base.dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 347         uint32_t ch_data = ch_ctl + 4;
 348         int i, ret, recv_bytes;
 349         uint32_t status;
 350         uint32_t aux_clock_divider;
 351         int try, precharge;
 352         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 353
 354         /* dp aux is extremely sensitive to irq latency, hence request the
 355          * lowest possible wakeup latency and so prevent the cpu from going into
 356          * deep sleep states.
 357          */
 358         pm_qos_update_request(&dev_priv->pm_qos, 0);
 359
 360         intel_dp_check_edp(intel_dp);
 361         /* The clock divider is based off the hrawclk,
 362          * and would like to run at 2MHz. So, take the
 363          * hrawclk value and divide by 2 and use that
 364          *
 365          * Note that PCH attached eDP panels should use a 125MHz input
 366          * clock divider.
 367          */
 368         if (is_cpu_edp(intel_dp)) {
 369                 if (HAS_DDI(dev))
 370                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 371                 else if (IS_VALLEYVIEW(dev))
 372                         aux_clock_divider = 100;
 373                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 374                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 375                 else
 376                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 377         } else if (HAS_PCH_SPLIT(dev))
 378                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 379         else
 380                 aux_clock_divider = intel_hrawclk(dev) / 2;
 381
 382         if (IS_GEN6(dev))
 383                 precharge = 3;
 384         else
 385                 precharge = 5;
 386
 387         /* Try to wait for any previous AUX channel activity */
 388         for (try = 0; try < 3; try++) {
 389                 status = I915_READ_NOTRACE(ch_ctl);
 390                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 391                         break;
 392                 msleep(1);
 393         }
 394
 395         if (try == 3) {
 396                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 397                      I915_READ(ch_ctl));
 398                 ret = -EBUSY;
 399                 goto out;
 400         }
 401
 402         /* Must try at least 3 times according to DP spec */
 403         for (try = 0; try < 5; try++) {
 404                 /* Load the send data into the aux channel data registers */
 405                 for (i = 0; i < send_bytes; i += 4)
 406                         I915_WRITE(ch_data + i,
 407                                    pack_aux(send + i, send_bytes - i));
 408
 409                 /* Send the command and wait for it to complete */
 410                 I915_WRITE(ch_ctl,
 411                            DP_AUX_CH_CTL_SEND_BUSY |
 412                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 413                            DP_AUX_CH_CTL_TIME_OUT_400us |
 414                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 415                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 416                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 417                            DP_AUX_CH_CTL_DONE |
 418                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 419                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 420
 421                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 422
 423                 /* Clear done status and any errors */
 424                 I915_WRITE(ch_ctl,
 425                            status |
 426                            DP_AUX_CH_CTL_DONE |
 427                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 428                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 429
 430                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 431                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 432                         continue;
 433                 if (status & DP_AUX_CH_CTL_DONE)
 434                         break;
 435         }
 436
 437         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 438                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 439                 ret = -EBUSY;
 440                 goto out;
 441         }
 442
 443         /* Check for timeout or receive error.
 444          * Timeouts occur when the sink is not connected
 445          */
 446         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 447                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 448                 ret = -EIO;
 449                 goto out;
 450         }
 451
 452         /* Timeouts occur when the device isn't connected, so they're
 453          * "normal" -- don't fill the kernel log with these */
 454         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 455                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 456                 ret = -ETIMEDOUT;
 457                 goto out;
 458         }
 459
 460         /* Unload any bytes sent back from the other side */
 461         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 462                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 463         if (recv_bytes > recv_size)
 464                 recv_bytes = recv_size;
 465
 466         for (i = 0; i < recv_bytes; i += 4)
 467                 unpack_aux(I915_READ(ch_data + i),
 468                            recv + i, recv_bytes - i);
 469
 470         ret = recv_bytes;
 471 out:
 472         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 473
 474         return ret;
 475 }
 476
 477 /* Write data to the aux channel in native mode */
 478 static int
 479 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 480                           uint16_t address, uint8_t *send, int send_bytes)
 481 {
 482         int ret;
 483         uint8_t msg[20];
 484         int msg_bytes;
 485         uint8_t ack;
 486
 487         intel_dp_check_edp(intel_dp);
 488         if (send_bytes > 16)
 489                 return -1;
 490         msg[0] = AUX_NATIVE_WRITE << 4;
 491         msg[1] = address >> 8;
 492         msg[2] = address & 0xff;
 493         msg[3] = send_bytes - 1;
 494         memcpy(&msg[4], send, send_bytes);
 495         msg_bytes = send_bytes + 4;
 496         for (;;) {
 497                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 498                 if (ret < 0)
 499                         return ret;
 500                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 501                         break;
 502                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 503                         udelay(100);
 504                 else
 505                         return -EIO;
 506         }
 507         return send_bytes;
 508 }
 509
 510 /* Write a single byte to the aux channel in native mode */
 511 static int
 512 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 513                             uint16_t address, uint8_t byte)
 514 {
 515         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 516 }
 517
 518 /* read bytes from a native aux channel */
 519 static int
 520 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 521                          uint16_t address, uint8_t *recv, int recv_bytes)
 522 {
 523         uint8_t msg[4];
 524         int msg_bytes;
 525         uint8_t reply[20];
 526         int reply_bytes;
 527         uint8_t ack;
 528         int ret;
 529
 530         intel_dp_check_edp(intel_dp);
 531         msg[0] = AUX_NATIVE_READ << 4;
 532         msg[1] = address >> 8;
 533         msg[2] = address & 0xff;
 534         msg[3] = recv_bytes - 1;
 535
 536         msg_bytes = 4;
 537         reply_bytes = recv_bytes + 1;
 538
 539         for (;;) {
 540                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 541                                       reply, reply_bytes);
 542                 if (ret == 0)
 543                         return -EPROTO;
 544                 if (ret < 0)
 545                         return ret;
 546                 ack = reply[0];
 547                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 548                         memcpy(recv, reply + 1, ret - 1);
 549                         return ret - 1;
 550                 }
 551                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 552                         udelay(100);
 553                 else
 554                         return -EIO;
 555         }
 556 }
 557
 558 static int
 559 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 560                     uint8_t write_byte, uint8_t *read_byte)
 561 {
 562         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 563         struct intel_dp *intel_dp = container_of(adapter,
 564                                                 struct intel_dp,
 565                                                 adapter);
 566         uint16_t address = algo_data->address;
 567         uint8_t msg[5];
 568         uint8_t reply[2];
 569         unsigned retry;
 570         int msg_bytes;
 571         int reply_bytes;
 572         int ret;
 573
 574         intel_dp_check_edp(intel_dp);
 575         /* Set up the command byte */
 576         if (mode & MODE_I2C_READ)
 577                 msg[0] = AUX_I2C_READ << 4;
 578         else
 579                 msg[0] = AUX_I2C_WRITE << 4;
 580
 581         if (!(mode & MODE_I2C_STOP))
 582                 msg[0] |= AUX_I2C_MOT << 4;
 583
 584         msg[1] = address >> 8;
 585         msg[2] = address;
 586
 587         switch (mode) {
 588         case MODE_I2C_WRITE:
 589                 msg[3] = 0;
 590                 msg[4] = write_byte;
 591                 msg_bytes = 5;
 592                 reply_bytes = 1;
 593                 break;
 594         case MODE_I2C_READ:
 595                 msg[3] = 0;
 596                 msg_bytes = 4;
 597                 reply_bytes = 2;
 598                 break;
 599         default:
 600                 msg_bytes = 3;
 601                 reply_bytes = 1;
 602                 break;
 603         }
 604
 605         for (retry = 0; retry < 5; retry++) {
 606                 ret = intel_dp_aux_ch(intel_dp,
 607                                       msg, msg_bytes,
 608                                       reply, reply_bytes);
 609                 if (ret < 0) {
 610                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 611                         return ret;
 612                 }
 613
 614                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 615                 case AUX_NATIVE_REPLY_ACK:
 616                         /* I2C-over-AUX Reply field is only valid
 617                          * when paired with AUX ACK.
 618                          */
 619                         break;
 620                 case AUX_NATIVE_REPLY_NACK:
 621                         DRM_DEBUG_KMS("aux_ch native nack\n");
 622                         return -EREMOTEIO;
 623                 case AUX_NATIVE_REPLY_DEFER:
 624                         udelay(100);
 625                         continue;
 626                 default:
 627                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 628                                   reply[0]);
 629                         return -EREMOTEIO;
 630                 }
 631
 632                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 633                 case AUX_I2C_REPLY_ACK:
 634                         if (mode == MODE_I2C_READ) {
 635                                 *read_byte = reply[1];
 636                         }
 637                         return reply_bytes - 1;
 638                 case AUX_I2C_REPLY_NACK:
 639                         DRM_DEBUG_KMS("aux_i2c nack\n");
 640                         return -EREMOTEIO;
 641                 case AUX_I2C_REPLY_DEFER:
 642                         DRM_DEBUG_KMS("aux_i2c defer\n");
 643                         udelay(100);
 644                         break;
 645                 default:
 646                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 647                         return -EREMOTEIO;
 648                 }
 649         }
 650
 651         DRM_ERROR("too many retries, giving up\n");
 652         return -EREMOTEIO;
 653 }
 654
 655 static int
 656 intel_dp_i2c_init(struct intel_dp *intel_dp,
 657                   struct intel_connector *intel_connector, const char *name)
 658 {
 659         int     ret;
 660
 661         DRM_DEBUG_KMS("i2c_init %s\n", name);
 662         intel_dp->algo.running = false;
 663         intel_dp->algo.address = 0;
 664         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 665
 666         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 667         intel_dp->adapter.owner = THIS_MODULE;
 668         intel_dp->adapter.class = I2C_CLASS_DDC;
 669         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 670         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 671         intel_dp->adapter.algo_data = &intel_dp->algo;
 672         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 673
 674         ironlake_edp_panel_vdd_on(intel_dp);
 675         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 676         ironlake_edp_panel_vdd_off(intel_dp, false);
 677         return ret;
 678 }
 679
 680 bool
 681 intel_dp_compute_config(struct intel_encoder *encoder,
 682                         struct intel_crtc_config *pipe_config)
 683 {
 684         struct drm_device *dev = encoder->base.dev;
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 687         struct drm_display_mode *mode = &pipe_config->requested_mode;
 688         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 689         struct intel_connector *intel_connector = intel_dp->attached_connector;
 690         int lane_count, clock;
 691         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 692         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 693         int bpp, mode_rate;
 694         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 695         int target_clock, link_avail, link_clock;
 696
 697         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 698                 pipe_config->has_pch_encoder = true;
 699
 700         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 701                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 702                                        adjusted_mode);
 703                 intel_pch_panel_fitting(dev,
 704                                         intel_connector->panel.fitting_mode,
 705                                         mode, adjusted_mode);
 706         }
 707         /* We need to take the panel's fixed mode into account. */
 708         target_clock = adjusted_mode->clock;
 709
 710         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 711                 return false;
 712
 713         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 714                       "max bw %02x pixel clock %iKHz\n",
 715                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 716
 717         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 718          * bpc in between. */
 719         bpp = 8*3;
 720         if (is_edp(intel_dp) && dev_priv->edp.bpp)
 721                 bpp = min_t(int, bpp, dev_priv->edp.bpp);
 722
 723         for (; bpp >= 6*3; bpp -= 2*3) {
 724                 mode_rate = intel_dp_link_required(target_clock, bpp);
 725
 726                 for (clock = 0; clock <= max_clock; clock++) {
 727                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 728                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 729                                 link_avail = intel_dp_max_data_rate(link_clock,
 730                                                                     lane_count);
 731
 732                                 if (mode_rate <= link_avail) {
 733                                         goto found;
 734                                 }
 735                         }
 736                 }
 737         }
 738
 739         return false;
 740
 741 found:
 742         if (intel_dp->color_range_auto) {
 743                 /*
 744                  * See:
 745                  * CEA-861-E - 5.1 Default Encoding Parameters
 746                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 747                  */
 748                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 749                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 750                 else
 751                         intel_dp->color_range = 0;
 752         }
 753
 754         if (intel_dp->color_range)
 755                 pipe_config->limited_color_range = true;
 756
 757         intel_dp->link_bw = bws[clock];
 758         intel_dp->lane_count = lane_count;
 759         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 760         pipe_config->pipe_bpp = bpp;
 761
 762         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 763                       intel_dp->link_bw, intel_dp->lane_count,
 764                       adjusted_mode->clock, bpp);
 765         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 766                       mode_rate, link_avail);
 767
 768         return true;
 769 }
 770
 771 void
 772 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 773                  struct drm_display_mode *adjusted_mode)
 774 {
 775         struct drm_device *dev = crtc->dev;
 776         struct intel_encoder *intel_encoder;
 777         struct intel_dp *intel_dp;
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 780         int lane_count = 4;
 781         struct intel_link_m_n m_n;
 782         int pipe = intel_crtc->pipe;
 783         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 784
 785         /*
 786          * Find the lane count in the intel_encoder private
 787          */
 788         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 789                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
 790
 791                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 792                     intel_encoder->type == INTEL_OUTPUT_EDP)
 793                 {
 794                         lane_count = intel_dp->lane_count;
 795                         break;
 796                 }
 797         }
 798
 799         /*
 800          * Compute the GMCH and Link ratios. The '3' here is
 801          * the number of bytes_per_pixel post-LUT, which we always
 802          * set up for 8-bits of R/G/B, or 3 bytes total.
 803          */
 804         intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count,
 805                                mode->clock, adjusted_mode->clock, &m_n);
 806
 807         if (HAS_DDI(dev)) {
 808                 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
 809                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 810                 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
 811                 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
 812                 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 813         } else if (HAS_PCH_SPLIT(dev)) {
 814                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 815                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 816                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 817                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 818         } else if (IS_VALLEYVIEW(dev)) {
 819                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 820                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 821                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 822                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 823         } else {
 824                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 825                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 826                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 827                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 828                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 829         }
 830 }
 831
 832 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 833 {
 834         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 835         intel_dp->link_configuration[0] = intel_dp->link_bw;
 836         intel_dp->link_configuration[1] = intel_dp->lane_count;
 837         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 838         /*
 839          * Check for DPCD version > 1.1 and enhanced framing support
 840          */
 841         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 842             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 843                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 844         }
 845 }
 846
 847 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 848 {
 849         struct drm_device *dev = crtc->dev;
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         u32 dpa_ctl;
 852
 853         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 854         dpa_ctl = I915_READ(DP_A);
 855         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 856
 857         if (clock < 200000) {
 858                 /* For a long time we've carried around a ILK-DevA w/a for the
 859                  * 160MHz clock. If we're really unlucky, it's still required.
 860                  */
 861                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 862                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 863         } else {
 864                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 865         }
 866
 867         I915_WRITE(DP_A, dpa_ctl);
 868
 869         POSTING_READ(DP_A);
 870         udelay(500);
 871 }
 872
 873 static void
 874 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 875                   struct drm_display_mode *adjusted_mode)
 876 {
 877         struct drm_device *dev = encoder->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 880         struct drm_crtc *crtc = encoder->crtc;
 881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 882
 883         /*
 884          * There are four kinds of DP registers:
 885          *
 886          *      IBX PCH
 887          *      SNB CPU
 888          *      IVB CPU
 889          *      CPT PCH
 890          *
 891          * IBX PCH and CPU are the same for almost everything,
 892          * except that the CPU DP PLL is configured in this
 893          * register
 894          *
 895          * CPT PCH is quite different, having many bits moved
 896          * to the TRANS_DP_CTL register instead. That
 897          * configuration happens (oddly) in ironlake_pch_enable
 898          */
 899
 900         /* Preserve the BIOS-computed detected bit. This is
 901          * supposed to be read-only.
 902          */
 903         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 904
 905         /* Handle DP bits in common between all three register formats */
 906         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 907
 908         switch (intel_dp->lane_count) {
 909         case 1:
 910                 intel_dp->DP |= DP_PORT_WIDTH_1;
 911                 break;
 912         case 2:
 913                 intel_dp->DP |= DP_PORT_WIDTH_2;
 914                 break;
 915         case 4:
 916                 intel_dp->DP |= DP_PORT_WIDTH_4;
 917                 break;
 918         }
 919         if (intel_dp->has_audio) {
 920                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 921                                  pipe_name(intel_crtc->pipe));
 922                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 923                 intel_write_eld(encoder, adjusted_mode);
 924         }
 925
 926         intel_dp_init_link_config(intel_dp);
 927
 928         /* Split out the IBX/CPU vs CPT settings */
 929
 930         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 931                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 932                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 933                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 934                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 935                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 936
 937                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 938                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 939
 940                 intel_dp->DP |= intel_crtc->pipe << 29;
 941
 942                 /* don't miss out required setting for eDP */
 943                 if (adjusted_mode->clock < 200000)
 944                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 945                 else
 946                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 947         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 948                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 949                         intel_dp->DP |= intel_dp->color_range;
 950
 951                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 952                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 953                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 954                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 955                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 956
 957                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 958                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 959
 960                 if (intel_crtc->pipe == 1)
 961                         intel_dp->DP |= DP_PIPEB_SELECT;
 962
 963                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 964                         /* don't miss out required setting for eDP */
 965                         if (adjusted_mode->clock < 200000)
 966                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 967                         else
 968                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 969                 }
 970         } else {
 971                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 972         }
 973
 974         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 975                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 976 }
 977
 978 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 979 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 980
 981 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 982 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 983
 984 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 985 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 986
 987 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 988                                        u32 mask,
 989                                        u32 value)
 990 {
 991         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 992         struct drm_i915_private *dev_priv = dev->dev_private;
 993         u32 pp_stat_reg, pp_ctrl_reg;
 994
 995         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 996         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 997
 998         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 999                         mask, value,
1000                         I915_READ(pp_stat_reg),
1001                         I915_READ(pp_ctrl_reg));
1002
1003         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1004                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1005                                 I915_READ(pp_stat_reg),
1006                                 I915_READ(pp_ctrl_reg));
1007         }
1008 }
1009
1010 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1011 {
1012         DRM_DEBUG_KMS("Wait for panel power on\n");
1013         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1014 }
1015
1016 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1017 {
1018         DRM_DEBUG_KMS("Wait for panel power off time\n");
1019         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1020 }
1021
1022 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1023 {
1024         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1025         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1026 }
1027
1028
1029 /* Read the current pp_control value, unlocking the register if it
1030  * is locked
1031  */
1032
1033 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1034 {
1035         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         u32 control;
1038         u32 pp_ctrl_reg;
1039
1040         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1041         control = I915_READ(pp_ctrl_reg);
1042
1043         control &= ~PANEL_UNLOCK_MASK;
1044         control |= PANEL_UNLOCK_REGS;
1045         return control;
1046 }
1047
1048 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1049 {
1050         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1051         struct drm_i915_private *dev_priv = dev->dev_private;
1052         u32 pp;
1053         u32 pp_stat_reg, pp_ctrl_reg;
1054
1055         if (!is_edp(intel_dp))
1056                 return;
1057         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1058
1059         WARN(intel_dp->want_panel_vdd,
1060              "eDP VDD already requested on\n");
1061
1062         intel_dp->want_panel_vdd = true;
1063
1064         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1065                 DRM_DEBUG_KMS("eDP VDD already on\n");
1066                 return;
1067         }
1068
1069         if (!ironlake_edp_have_panel_power(intel_dp))
1070                 ironlake_wait_panel_power_cycle(intel_dp);
1071
1072         pp = ironlake_get_pp_control(intel_dp);
1073         pp |= EDP_FORCE_VDD;
1074
1075         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1076         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1077
1078         I915_WRITE(pp_ctrl_reg, pp);
1079         POSTING_READ(pp_ctrl_reg);
1080         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1081                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1082         /*
1083          * If the panel wasn't on, delay before accessing aux channel
1084          */
1085         if (!ironlake_edp_have_panel_power(intel_dp)) {
1086                 DRM_DEBUG_KMS("eDP was not running\n");
1087                 msleep(intel_dp->panel_power_up_delay);
1088         }
1089 }
1090
1091 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1092 {
1093         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         u32 pp;
1096         u32 pp_stat_reg, pp_ctrl_reg;
1097
1098         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1099
1100         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1101                 pp = ironlake_get_pp_control(intel_dp);
1102                 pp &= ~EDP_FORCE_VDD;
1103
1104                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1105                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1106
1107                 I915_WRITE(pp_ctrl_reg, pp);
1108                 POSTING_READ(pp_ctrl_reg);
1109
1110                 /* Make sure sequencer is idle before allowing subsequent activity */
1111                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1112                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1113                 msleep(intel_dp->panel_power_down_delay);
1114         }
1115 }
1116
1117 static void ironlake_panel_vdd_work(struct work_struct *__work)
1118 {
1119         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1120                                                  struct intel_dp, panel_vdd_work);
1121         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122
1123         mutex_lock(&dev->mode_config.mutex);
1124         ironlake_panel_vdd_off_sync(intel_dp);
1125         mutex_unlock(&dev->mode_config.mutex);
1126 }
1127
1128 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1129 {
1130         if (!is_edp(intel_dp))
1131                 return;
1132
1133         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1134         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1135
1136         intel_dp->want_panel_vdd = false;
1137
1138         if (sync) {
1139                 ironlake_panel_vdd_off_sync(intel_dp);
1140         } else {
1141                 /*
1142                  * Queue the timer to fire a long
1143                  * time from now (relative to the power down delay)
1144                  * to keep the panel power up across a sequence of operations
1145                  */
1146                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1147                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1148         }
1149 }
1150
1151 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1152 {
1153         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1154         struct drm_i915_private *dev_priv = dev->dev_private;
1155         u32 pp;
1156         u32 pp_ctrl_reg;
1157
1158         if (!is_edp(intel_dp))
1159                 return;
1160
1161         DRM_DEBUG_KMS("Turn eDP power on\n");
1162
1163         if (ironlake_edp_have_panel_power(intel_dp)) {
1164                 DRM_DEBUG_KMS("eDP power already on\n");
1165                 return;
1166         }
1167
1168         ironlake_wait_panel_power_cycle(intel_dp);
1169
1170         pp = ironlake_get_pp_control(intel_dp);
1171         if (IS_GEN5(dev)) {
1172                 /* ILK workaround: disable reset around power sequence */
1173                 pp &= ~PANEL_POWER_RESET;
1174                 I915_WRITE(PCH_PP_CONTROL, pp);
1175                 POSTING_READ(PCH_PP_CONTROL);
1176         }
1177
1178         pp |= POWER_TARGET_ON;
1179         if (!IS_GEN5(dev))
1180                 pp |= PANEL_POWER_RESET;
1181
1182         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1183
1184         I915_WRITE(pp_ctrl_reg, pp);
1185         POSTING_READ(pp_ctrl_reg);
1186
1187         ironlake_wait_panel_on(intel_dp);
1188
1189         if (IS_GEN5(dev)) {
1190                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1191                 I915_WRITE(PCH_PP_CONTROL, pp);
1192                 POSTING_READ(PCH_PP_CONTROL);
1193         }
1194 }
1195
1196 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1197 {
1198         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         u32 pp;
1201         u32 pp_ctrl_reg;
1202
1203         if (!is_edp(intel_dp))
1204                 return;
1205
1206         DRM_DEBUG_KMS("Turn eDP power off\n");
1207
1208         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1209
1210         pp = ironlake_get_pp_control(intel_dp);
1211         /* We need to switch off panel power _and_ force vdd, for otherwise some
1212          * panels get very unhappy and cease to work. */
1213         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1214
1215         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1216
1217         I915_WRITE(pp_ctrl_reg, pp);
1218         POSTING_READ(pp_ctrl_reg);
1219
1220         intel_dp->want_panel_vdd = false;
1221
1222         ironlake_wait_panel_off(intel_dp);
1223 }
1224
1225 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1226 {
1227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1228         struct drm_device *dev = intel_dig_port->base.base.dev;
1229         struct drm_i915_private *dev_priv = dev->dev_private;
1230         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1231         u32 pp;
1232         u32 pp_ctrl_reg;
1233
1234         if (!is_edp(intel_dp))
1235                 return;
1236
1237         DRM_DEBUG_KMS("\n");
1238         /*
1239          * If we enable the backlight right away following a panel power
1240          * on, we may see slight flicker as the panel syncs with the eDP
1241          * link.  So delay a bit to make sure the image is solid before
1242          * allowing it to appear.
1243          */
1244         msleep(intel_dp->backlight_on_delay);
1245         pp = ironlake_get_pp_control(intel_dp);
1246         pp |= EDP_BLC_ENABLE;
1247
1248         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1249
1250         I915_WRITE(pp_ctrl_reg, pp);
1251         POSTING_READ(pp_ctrl_reg);
1252
1253         intel_panel_enable_backlight(dev, pipe);
1254 }
1255
1256 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1257 {
1258         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1259         struct drm_i915_private *dev_priv = dev->dev_private;
1260         u32 pp;
1261         u32 pp_ctrl_reg;
1262
1263         if (!is_edp(intel_dp))
1264                 return;
1265
1266         intel_panel_disable_backlight(dev);
1267
1268         DRM_DEBUG_KMS("\n");
1269         pp = ironlake_get_pp_control(intel_dp);
1270         pp &= ~EDP_BLC_ENABLE;
1271
1272         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1273
1274         I915_WRITE(pp_ctrl_reg, pp);
1275         POSTING_READ(pp_ctrl_reg);
1276         msleep(intel_dp->backlight_off_delay);
1277 }
1278
1279 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1280 {
1281         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1282         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1283         struct drm_device *dev = crtc->dev;
1284         struct drm_i915_private *dev_priv = dev->dev_private;
1285         u32 dpa_ctl;
1286
1287         assert_pipe_disabled(dev_priv,
1288                              to_intel_crtc(crtc)->pipe);
1289
1290         DRM_DEBUG_KMS("\n");
1291         dpa_ctl = I915_READ(DP_A);
1292         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1293         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1294
1295         /* We don't adjust intel_dp->DP while tearing down the link, to
1296          * facilitate link retraining (e.g. after hotplug). Hence clear all
1297          * enable bits here to ensure that we don't enable too much. */
1298         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1299         intel_dp->DP |= DP_PLL_ENABLE;
1300         I915_WRITE(DP_A, intel_dp->DP);
1301         POSTING_READ(DP_A);
1302         udelay(200);
1303 }
1304
1305 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1306 {
1307         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1308         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1309         struct drm_device *dev = crtc->dev;
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         u32 dpa_ctl;
1312
1313         assert_pipe_disabled(dev_priv,
1314                              to_intel_crtc(crtc)->pipe);
1315
1316         dpa_ctl = I915_READ(DP_A);
1317         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1318              "dp pll off, should be on\n");
1319         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1320
1321         /* We can't rely on the value tracked for the DP register in
1322          * intel_dp->DP because link_down must not change that (otherwise link
1323          * re-training will fail. */
1324         dpa_ctl &= ~DP_PLL_ENABLE;
1325         I915_WRITE(DP_A, dpa_ctl);
1326         POSTING_READ(DP_A);
1327         udelay(200);
1328 }
1329
1330 /* If the sink supports it, try to set the power state appropriately */
1331 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1332 {
1333         int ret, i;
1334
1335         /* Should have a valid DPCD by this point */
1336         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1337                 return;
1338
1339         if (mode != DRM_MODE_DPMS_ON) {
1340                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1341                                                   DP_SET_POWER_D3);
1342                 if (ret != 1)
1343                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1344         } else {
1345                 /*
1346                  * When turning on, we need to retry for 1ms to give the sink
1347                  * time to wake up.
1348                  */
1349                 for (i = 0; i < 3; i++) {
1350                         ret = intel_dp_aux_native_write_1(intel_dp,
1351                                                           DP_SET_POWER,
1352                                                           DP_SET_POWER_D0);
1353                         if (ret == 1)
1354                                 break;
1355                         msleep(1);
1356                 }
1357         }
1358 }
1359
1360 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1361                                   enum pipe *pipe)
1362 {
1363         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1364         struct drm_device *dev = encoder->base.dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         u32 tmp = I915_READ(intel_dp->output_reg);
1367
1368         if (!(tmp & DP_PORT_EN))
1369                 return false;
1370
1371         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1372                 *pipe = PORT_TO_PIPE_CPT(tmp);
1373         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1374                 *pipe = PORT_TO_PIPE(tmp);
1375         } else {
1376                 u32 trans_sel;
1377                 u32 trans_dp;
1378                 int i;
1379
1380                 switch (intel_dp->output_reg) {
1381                 case PCH_DP_B:
1382                         trans_sel = TRANS_DP_PORT_SEL_B;
1383                         break;
1384                 case PCH_DP_C:
1385                         trans_sel = TRANS_DP_PORT_SEL_C;
1386                         break;
1387                 case PCH_DP_D:
1388                         trans_sel = TRANS_DP_PORT_SEL_D;
1389                         break;
1390                 default:
1391                         return true;
1392                 }
1393
1394                 for_each_pipe(i) {
1395                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1396                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1397                                 *pipe = i;
1398                                 return true;
1399                         }
1400                 }
1401
1402                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1403                               intel_dp->output_reg);
1404         }
1405
1406         return false;
1407 }
1408
1409 static void intel_disable_dp(struct intel_encoder *encoder)
1410 {
1411         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1412
1413         /* Make sure the panel is off before trying to change the mode. But also
1414          * ensure that we have vdd while we switch off the panel. */
1415         ironlake_edp_panel_vdd_on(intel_dp);
1416         ironlake_edp_backlight_off(intel_dp);
1417         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1418         ironlake_edp_panel_off(intel_dp);
1419
1420         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1421         if (!is_cpu_edp(intel_dp))
1422                 intel_dp_link_down(intel_dp);
1423 }
1424
1425 static void intel_post_disable_dp(struct intel_encoder *encoder)
1426 {
1427         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1428         struct drm_device *dev = encoder->base.dev;
1429
1430         if (is_cpu_edp(intel_dp)) {
1431                 intel_dp_link_down(intel_dp);
1432                 if (!IS_VALLEYVIEW(dev))
1433                         ironlake_edp_pll_off(intel_dp);
1434         }
1435 }
1436
1437 static void intel_enable_dp(struct intel_encoder *encoder)
1438 {
1439         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1440         struct drm_device *dev = encoder->base.dev;
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1443
1444         if (WARN_ON(dp_reg & DP_PORT_EN))
1445                 return;
1446
1447         ironlake_edp_panel_vdd_on(intel_dp);
1448         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1449         intel_dp_start_link_train(intel_dp);
1450         ironlake_edp_panel_on(intel_dp);
1451         ironlake_edp_panel_vdd_off(intel_dp, true);
1452         intel_dp_complete_link_train(intel_dp);
1453         ironlake_edp_backlight_on(intel_dp);
1454 }
1455
1456 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1457 {
1458         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1459         struct drm_device *dev = encoder->base.dev;
1460
1461         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1462                 ironlake_edp_pll_on(intel_dp);
1463 }
1464
1465 /*
1466  * Native read with retry for link status and receiver capability reads for
1467  * cases where the sink may still be asleep.
1468  */
1469 static bool
1470 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1471                                uint8_t *recv, int recv_bytes)
1472 {
1473         int ret, i;
1474
1475         /*
1476          * Sinks are *supposed* to come up within 1ms from an off state,
1477          * but we're also supposed to retry 3 times per the spec.
1478          */
1479         for (i = 0; i < 3; i++) {
1480                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1481                                                recv_bytes);
1482                 if (ret == recv_bytes)
1483                         return true;
1484                 msleep(1);
1485         }
1486
1487         return false;
1488 }
1489
1490 /*
1491  * Fetch AUX CH registers 0x202 - 0x207 which contain
1492  * link status information
1493  */
1494 static bool
1495 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1496 {
1497         return intel_dp_aux_native_read_retry(intel_dp,
1498                                               DP_LANE0_1_STATUS,
1499                                               link_status,
1500                                               DP_LINK_STATUS_SIZE);
1501 }
1502
1503 #if 0
1504 static char     *voltage_names[] = {
1505         "0.4V", "0.6V", "0.8V", "1.2V"
1506 };
1507 static char     *pre_emph_names[] = {
1508         "0dB", "3.5dB", "6dB", "9.5dB"
1509 };
1510 static char     *link_train_names[] = {
1511         "pattern 1", "pattern 2", "idle", "off"
1512 };
1513 #endif
1514
1515 /*
1516  * These are source-specific values; current Intel hardware supports
1517  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1518  */
1519
1520 static uint8_t
1521 intel_dp_voltage_max(struct intel_dp *intel_dp)
1522 {
1523         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1524
1525         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1526                 return DP_TRAIN_VOLTAGE_SWING_800;
1527         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1528                 return DP_TRAIN_VOLTAGE_SWING_1200;
1529         else
1530                 return DP_TRAIN_VOLTAGE_SWING_800;
1531 }
1532
1533 static uint8_t
1534 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1535 {
1536         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1537
1538         if (HAS_DDI(dev)) {
1539                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1540                 case DP_TRAIN_VOLTAGE_SWING_400:
1541                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1542                 case DP_TRAIN_VOLTAGE_SWING_600:
1543                         return DP_TRAIN_PRE_EMPHASIS_6;
1544                 case DP_TRAIN_VOLTAGE_SWING_800:
1545                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1546                 case DP_TRAIN_VOLTAGE_SWING_1200:
1547                 default:
1548                         return DP_TRAIN_PRE_EMPHASIS_0;
1549                 }
1550         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1551                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1552                 case DP_TRAIN_VOLTAGE_SWING_400:
1553                         return DP_TRAIN_PRE_EMPHASIS_6;
1554                 case DP_TRAIN_VOLTAGE_SWING_600:
1555                 case DP_TRAIN_VOLTAGE_SWING_800:
1556                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1557                 default:
1558                         return DP_TRAIN_PRE_EMPHASIS_0;
1559                 }
1560         } else {
1561                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1562                 case DP_TRAIN_VOLTAGE_SWING_400:
1563                         return DP_TRAIN_PRE_EMPHASIS_6;
1564                 case DP_TRAIN_VOLTAGE_SWING_600:
1565                         return DP_TRAIN_PRE_EMPHASIS_6;
1566                 case DP_TRAIN_VOLTAGE_SWING_800:
1567                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1568                 case DP_TRAIN_VOLTAGE_SWING_1200:
1569                 default:
1570                         return DP_TRAIN_PRE_EMPHASIS_0;
1571                 }
1572         }
1573 }
1574
1575 static void
1576 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1577 {
1578         uint8_t v = 0;
1579         uint8_t p = 0;
1580         int lane;
1581         uint8_t voltage_max;
1582         uint8_t preemph_max;
1583
1584         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1585                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1586                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1587
1588                 if (this_v > v)
1589                         v = this_v;
1590                 if (this_p > p)
1591                         p = this_p;
1592         }
1593
1594         voltage_max = intel_dp_voltage_max(intel_dp);
1595         if (v >= voltage_max)
1596                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1597
1598         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1599         if (p >= preemph_max)
1600                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1601
1602         for (lane = 0; lane < 4; lane++)
1603                 intel_dp->train_set[lane] = v | p;
1604 }
1605
1606 static uint32_t
1607 intel_gen4_signal_levels(uint8_t train_set)
1608 {
1609         uint32_t        signal_levels = 0;
1610
1611         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1612         case DP_TRAIN_VOLTAGE_SWING_400:
1613         default:
1614                 signal_levels |= DP_VOLTAGE_0_4;
1615                 break;
1616         case DP_TRAIN_VOLTAGE_SWING_600:
1617                 signal_levels |= DP_VOLTAGE_0_6;
1618                 break;
1619         case DP_TRAIN_VOLTAGE_SWING_800:
1620                 signal_levels |= DP_VOLTAGE_0_8;
1621                 break;
1622         case DP_TRAIN_VOLTAGE_SWING_1200:
1623                 signal_levels |= DP_VOLTAGE_1_2;
1624                 break;
1625         }
1626         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1627         case DP_TRAIN_PRE_EMPHASIS_0:
1628         default:
1629                 signal_levels |= DP_PRE_EMPHASIS_0;
1630                 break;
1631         case DP_TRAIN_PRE_EMPHASIS_3_5:
1632                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1633                 break;
1634         case DP_TRAIN_PRE_EMPHASIS_6:
1635                 signal_levels |= DP_PRE_EMPHASIS_6;
1636                 break;
1637         case DP_TRAIN_PRE_EMPHASIS_9_5:
1638                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1639                 break;
1640         }
1641         return signal_levels;
1642 }
1643
1644 /* Gen6's DP voltage swing and pre-emphasis control */
1645 static uint32_t
1646 intel_gen6_edp_signal_levels(uint8_t train_set)
1647 {
1648         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1649                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1650         switch (signal_levels) {
1651         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1652         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1653                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1654         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1655                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1656         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1657         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1658                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1659         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1660         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1662         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1663         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1664                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1665         default:
1666                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1667                               "0x%x\n", signal_levels);
1668                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1669         }
1670 }
1671
1672 /* Gen7's DP voltage swing and pre-emphasis control */
1673 static uint32_t
1674 intel_gen7_edp_signal_levels(uint8_t train_set)
1675 {
1676         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1677                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1678         switch (signal_levels) {
1679         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1680                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1681         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1682                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1683         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1684                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1685
1686         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1687                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1688         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1689                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1690
1691         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1692                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1693         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1694                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1695
1696         default:
1697                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1698                               "0x%x\n", signal_levels);
1699                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1700         }
1701 }
1702
1703 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1704 static uint32_t
1705 intel_hsw_signal_levels(uint8_t train_set)
1706 {
1707         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1708                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1709         switch (signal_levels) {
1710         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1711                 return DDI_BUF_EMP_400MV_0DB_HSW;
1712         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1713                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1714         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1715                 return DDI_BUF_EMP_400MV_6DB_HSW;
1716         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1717                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1718
1719         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1720                 return DDI_BUF_EMP_600MV_0DB_HSW;
1721         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1722                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1723         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1724                 return DDI_BUF_EMP_600MV_6DB_HSW;
1725
1726         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1727                 return DDI_BUF_EMP_800MV_0DB_HSW;
1728         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1729                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1730         default:
1731                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1732                               "0x%x\n", signal_levels);
1733                 return DDI_BUF_EMP_400MV_0DB_HSW;
1734         }
1735 }
1736
1737 /* Properly updates "DP" with the correct signal levels. */
1738 static void
1739 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1740 {
1741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1742         struct drm_device *dev = intel_dig_port->base.base.dev;
1743         uint32_t signal_levels, mask;
1744         uint8_t train_set = intel_dp->train_set[0];
1745
1746         if (HAS_DDI(dev)) {
1747                 signal_levels = intel_hsw_signal_levels(train_set);
1748                 mask = DDI_BUF_EMP_MASK;
1749         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1750                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1751                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1752         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1753                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1754                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1755         } else {
1756                 signal_levels = intel_gen4_signal_levels(train_set);
1757                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1758         }
1759
1760         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1761
1762         *DP = (*DP & ~mask) | signal_levels;
1763 }
1764
1765 static bool
1766 intel_dp_set_link_train(struct intel_dp *intel_dp,
1767                         uint32_t dp_reg_value,
1768                         uint8_t dp_train_pat)
1769 {
1770         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1771         struct drm_device *dev = intel_dig_port->base.base.dev;
1772         struct drm_i915_private *dev_priv = dev->dev_private;
1773         enum port port = intel_dig_port->port;
1774         int ret;
1775         uint32_t temp;
1776
1777         if (HAS_DDI(dev)) {
1778                 temp = I915_READ(DP_TP_CTL(port));
1779
1780                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1781                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1782                 else
1783                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1784
1785                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1786                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1787                 case DP_TRAINING_PATTERN_DISABLE:
1788
1789                         if (port != PORT_A) {
1790                                 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1791                                 I915_WRITE(DP_TP_CTL(port), temp);
1792
1793                                 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1794                                               DP_TP_STATUS_IDLE_DONE), 1))
1795                                         DRM_ERROR("Timed out waiting for DP idle patterns\n");
1796
1797                                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1798                         }
1799
1800                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1801
1802                         break;
1803                 case DP_TRAINING_PATTERN_1:
1804                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1805                         break;
1806                 case DP_TRAINING_PATTERN_2:
1807                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1808                         break;
1809                 case DP_TRAINING_PATTERN_3:
1810                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1811                         break;
1812                 }
1813                 I915_WRITE(DP_TP_CTL(port), temp);
1814
1815         } else if (HAS_PCH_CPT(dev) &&
1816                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1817                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1818
1819                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1820                 case DP_TRAINING_PATTERN_DISABLE:
1821                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1822                         break;
1823                 case DP_TRAINING_PATTERN_1:
1824                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1825                         break;
1826                 case DP_TRAINING_PATTERN_2:
1827                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1828                         break;
1829                 case DP_TRAINING_PATTERN_3:
1830                         DRM_ERROR("DP training pattern 3 not supported\n");
1831                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1832                         break;
1833                 }
1834
1835         } else {
1836                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1837
1838                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1839                 case DP_TRAINING_PATTERN_DISABLE:
1840                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1841                         break;
1842                 case DP_TRAINING_PATTERN_1:
1843                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1844                         break;
1845                 case DP_TRAINING_PATTERN_2:
1846                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1847                         break;
1848                 case DP_TRAINING_PATTERN_3:
1849                         DRM_ERROR("DP training pattern 3 not supported\n");
1850                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1851                         break;
1852                 }
1853         }
1854
1855         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1856         POSTING_READ(intel_dp->output_reg);
1857
1858         intel_dp_aux_native_write_1(intel_dp,
1859                                     DP_TRAINING_PATTERN_SET,
1860                                     dp_train_pat);
1861
1862         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1863             DP_TRAINING_PATTERN_DISABLE) {
1864                 ret = intel_dp_aux_native_write(intel_dp,
1865                                                 DP_TRAINING_LANE0_SET,
1866                                                 intel_dp->train_set,
1867                                                 intel_dp->lane_count);
1868                 if (ret != intel_dp->lane_count)
1869                         return false;
1870         }
1871
1872         return true;
1873 }
1874
1875 /* Enable corresponding port and start training pattern 1 */
1876 void
1877 intel_dp_start_link_train(struct intel_dp *intel_dp)
1878 {
1879         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1880         struct drm_device *dev = encoder->dev;
1881         int i;
1882         uint8_t voltage;
1883         bool clock_recovery = false;
1884         int voltage_tries, loop_tries;
1885         uint32_t DP = intel_dp->DP;
1886
1887         if (HAS_DDI(dev))
1888                 intel_ddi_prepare_link_retrain(encoder);
1889
1890         /* Write the link configuration data */
1891         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1892                                   intel_dp->link_configuration,
1893                                   DP_LINK_CONFIGURATION_SIZE);
1894
1895         DP |= DP_PORT_EN;
1896
1897         memset(intel_dp->train_set, 0, 4);
1898         voltage = 0xff;
1899         voltage_tries = 0;
1900         loop_tries = 0;
1901         clock_recovery = false;
1902         for (;;) {
1903                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1904                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1905
1906                 intel_dp_set_signal_levels(intel_dp, &DP);
1907
1908                 /* Set training pattern 1 */
1909                 if (!intel_dp_set_link_train(intel_dp, DP,
1910                                              DP_TRAINING_PATTERN_1 |
1911                                              DP_LINK_SCRAMBLING_DISABLE))
1912                         break;
1913
1914                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1915                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1916                         DRM_ERROR("failed to get link status\n");
1917                         break;
1918                 }
1919
1920                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1921                         DRM_DEBUG_KMS("clock recovery OK\n");
1922                         clock_recovery = true;
1923                         break;
1924                 }
1925
1926                 /* Check to see if we've tried the max voltage */
1927                 for (i = 0; i < intel_dp->lane_count; i++)
1928                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1929                                 break;
1930                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1931                         ++loop_tries;
1932                         if (loop_tries == 5) {
1933                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1934                                 break;
1935                         }
1936                         memset(intel_dp->train_set, 0, 4);
1937                         voltage_tries = 0;
1938                         continue;
1939                 }
1940
1941                 /* Check to see if we've tried the same voltage 5 times */
1942                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1943                         ++voltage_tries;
1944                         if (voltage_tries == 5) {
1945                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1946                                 break;
1947                         }
1948                 } else
1949                         voltage_tries = 0;
1950                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1951
1952                 /* Compute new intel_dp->train_set as requested by target */
1953                 intel_get_adjust_train(intel_dp, link_status);
1954         }
1955
1956         intel_dp->DP = DP;
1957 }
1958
1959 void
1960 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1961 {
1962         bool channel_eq = false;
1963         int tries, cr_tries;
1964         uint32_t DP = intel_dp->DP;
1965
1966         /* channel equalization */
1967         tries = 0;
1968         cr_tries = 0;
1969         channel_eq = false;
1970         for (;;) {
1971                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1972
1973                 if (cr_tries > 5) {
1974                         DRM_ERROR("failed to train DP, aborting\n");
1975                         intel_dp_link_down(intel_dp);
1976                         break;
1977                 }
1978
1979                 intel_dp_set_signal_levels(intel_dp, &DP);
1980
1981                 /* channel eq pattern */
1982                 if (!intel_dp_set_link_train(intel_dp, DP,
1983                                              DP_TRAINING_PATTERN_2 |
1984                                              DP_LINK_SCRAMBLING_DISABLE))
1985                         break;
1986
1987                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1988                 if (!intel_dp_get_link_status(intel_dp, link_status))
1989                         break;
1990
1991                 /* Make sure clock is still ok */
1992                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1993                         intel_dp_start_link_train(intel_dp);
1994                         cr_tries++;
1995                         continue;
1996                 }
1997
1998                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1999                         channel_eq = true;
2000                         break;
2001                 }
2002
2003                 /* Try 5 times, then try clock recovery if that fails */
2004                 if (tries > 5) {
2005                         intel_dp_link_down(intel_dp);
2006                         intel_dp_start_link_train(intel_dp);
2007                         tries = 0;
2008                         cr_tries++;
2009                         continue;
2010                 }
2011
2012                 /* Compute new intel_dp->train_set as requested by target */
2013                 intel_get_adjust_train(intel_dp, link_status);
2014                 ++tries;
2015         }
2016
2017         if (channel_eq)
2018                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2019
2020         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2021 }
2022
2023 static void
2024 intel_dp_link_down(struct intel_dp *intel_dp)
2025 {
2026         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2027         struct drm_device *dev = intel_dig_port->base.base.dev;
2028         struct drm_i915_private *dev_priv = dev->dev_private;
2029         struct intel_crtc *intel_crtc =
2030                 to_intel_crtc(intel_dig_port->base.base.crtc);
2031         uint32_t DP = intel_dp->DP;
2032
2033         /*
2034          * DDI code has a strict mode set sequence and we should try to respect
2035          * it, otherwise we might hang the machine in many different ways. So we
2036          * really should be disabling the port only on a complete crtc_disable
2037          * sequence. This function is just called under two conditions on DDI
2038          * code:
2039          * - Link train failed while doing crtc_enable, and on this case we
2040          *   really should respect the mode set sequence and wait for a
2041          *   crtc_disable.
2042          * - Someone turned the monitor off and intel_dp_check_link_status
2043          *   called us. We don't need to disable the whole port on this case, so
2044          *   when someone turns the monitor on again,
2045          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2046          *   train.
2047          */
2048         if (HAS_DDI(dev))
2049                 return;
2050
2051         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2052                 return;
2053
2054         DRM_DEBUG_KMS("\n");
2055
2056         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2057                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2058                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2059         } else {
2060                 DP &= ~DP_LINK_TRAIN_MASK;
2061                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2062         }
2063         POSTING_READ(intel_dp->output_reg);
2064
2065         /* We don't really know why we're doing this */
2066         intel_wait_for_vblank(dev, intel_crtc->pipe);
2067
2068         if (HAS_PCH_IBX(dev) &&
2069             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2070                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2071
2072                 /* Hardware workaround: leaving our transcoder select
2073                  * set to transcoder B while it's off will prevent the
2074                  * corresponding HDMI output on transcoder A.
2075                  *
2076                  * Combine this with another hardware workaround:
2077                  * transcoder select bit can only be cleared while the
2078                  * port is enabled.
2079                  */
2080                 DP &= ~DP_PIPEB_SELECT;
2081                 I915_WRITE(intel_dp->output_reg, DP);
2082
2083                 /* Changes to enable or select take place the vblank
2084                  * after being written.
2085                  */
2086                 if (WARN_ON(crtc == NULL)) {
2087                         /* We should never try to disable a port without a crtc
2088                          * attached. For paranoia keep the code around for a
2089                          * bit. */
2090                         POSTING_READ(intel_dp->output_reg);
2091                         msleep(50);
2092                 } else
2093                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2094         }
2095
2096         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2097         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2098         POSTING_READ(intel_dp->output_reg);
2099         msleep(intel_dp->panel_power_down_delay);
2100 }
2101
2102 static bool
2103 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2104 {
2105         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2106
2107         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2108                                            sizeof(intel_dp->dpcd)) == 0)
2109                 return false; /* aux transfer failed */
2110
2111         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2112                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2113         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2114
2115         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2116                 return false; /* DPCD not present */
2117
2118         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2119               DP_DWN_STRM_PORT_PRESENT))
2120                 return true; /* native DP sink */
2121
2122         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2123                 return true; /* no per-port downstream info */
2124
2125         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2126                                            intel_dp->downstream_ports,
2127                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2128                 return false; /* downstream port status fetch failed */
2129
2130         return true;
2131 }
2132
2133 static void
2134 intel_dp_probe_oui(struct intel_dp *intel_dp)
2135 {
2136         u8 buf[3];
2137
2138         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2139                 return;
2140
2141         ironlake_edp_panel_vdd_on(intel_dp);
2142
2143         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2144                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2145                               buf[0], buf[1], buf[2]);
2146
2147         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2148                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2149                               buf[0], buf[1], buf[2]);
2150
2151         ironlake_edp_panel_vdd_off(intel_dp, false);
2152 }
2153
2154 static bool
2155 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2156 {
2157         int ret;
2158
2159         ret = intel_dp_aux_native_read_retry(intel_dp,
2160                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2161                                              sink_irq_vector, 1);
2162         if (!ret)
2163                 return false;
2164
2165         return true;
2166 }
2167
2168 static void
2169 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2170 {
2171         /* NAK by default */
2172         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2173 }
2174
2175 /*
2176  * According to DP spec
2177  * 5.1.2:
2178  *  1. Read DPCD
2179  *  2. Configure link according to Receiver Capabilities
2180  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2181  *  4. Check link status on receipt of hot-plug interrupt
2182  */
2183
2184 void
2185 intel_dp_check_link_status(struct intel_dp *intel_dp)
2186 {
2187         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2188         u8 sink_irq_vector;
2189         u8 link_status[DP_LINK_STATUS_SIZE];
2190
2191         if (!intel_encoder->connectors_active)
2192                 return;
2193
2194         if (WARN_ON(!intel_encoder->base.crtc))
2195                 return;
2196
2197         /* Try to read receiver status if the link appears to be up */
2198         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2199                 intel_dp_link_down(intel_dp);
2200                 return;
2201         }
2202
2203         /* Now read the DPCD to see if it's actually running */
2204         if (!intel_dp_get_dpcd(intel_dp)) {
2205                 intel_dp_link_down(intel_dp);
2206                 return;
2207         }
2208
2209         /* Try to read the source of the interrupt */
2210         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2211             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2212                 /* Clear interrupt source */
2213                 intel_dp_aux_native_write_1(intel_dp,
2214                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2215                                             sink_irq_vector);
2216
2217                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2218                         intel_dp_handle_test_request(intel_dp);
2219                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2220                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2221         }
2222
2223         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2224                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2225                               drm_get_encoder_name(&intel_encoder->base));
2226                 intel_dp_start_link_train(intel_dp);
2227                 intel_dp_complete_link_train(intel_dp);
2228         }
2229 }
2230
2231 /* XXX this is probably wrong for multiple downstream ports */
2232 static enum drm_connector_status
2233 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2234 {
2235         uint8_t *dpcd = intel_dp->dpcd;
2236         bool hpd;
2237         uint8_t type;
2238
2239         if (!intel_dp_get_dpcd(intel_dp))
2240                 return connector_status_disconnected;
2241
2242         /* if there's no downstream port, we're done */
2243         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2244                 return connector_status_connected;
2245
2246         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2247         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2248         if (hpd) {
2249                 uint8_t reg;
2250                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2251                                                     &reg, 1))
2252                         return connector_status_unknown;
2253                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2254                                               : connector_status_disconnected;
2255         }
2256
2257         /* If no HPD, poke DDC gently */
2258         if (drm_probe_ddc(&intel_dp->adapter))
2259                 return connector_status_connected;
2260
2261         /* Well we tried, say unknown for unreliable port types */
2262         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2263         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2264                 return connector_status_unknown;
2265
2266         /* Anything else is out of spec, warn and ignore */
2267         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2268         return connector_status_disconnected;
2269 }
2270
2271 static enum drm_connector_status
2272 ironlake_dp_detect(struct intel_dp *intel_dp)
2273 {
2274         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2277         enum drm_connector_status status;
2278
2279         /* Can't disconnect eDP, but you can close the lid... */
2280         if (is_edp(intel_dp)) {
2281                 status = intel_panel_detect(dev);
2282                 if (status == connector_status_unknown)
2283                         status = connector_status_connected;
2284                 return status;
2285         }
2286
2287         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2288                 return connector_status_disconnected;
2289
2290         return intel_dp_detect_dpcd(intel_dp);
2291 }
2292
2293 static enum drm_connector_status
2294 g4x_dp_detect(struct intel_dp *intel_dp)
2295 {
2296         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2297         struct drm_i915_private *dev_priv = dev->dev_private;
2298         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2299         uint32_t bit;
2300
2301         /* Can't disconnect eDP, but you can close the lid... */
2302         if (is_edp(intel_dp)) {
2303                 enum drm_connector_status status;
2304
2305                 status = intel_panel_detect(dev);
2306                 if (status == connector_status_unknown)
2307                         status = connector_status_connected;
2308                 return status;
2309         }
2310
2311         switch (intel_dig_port->port) {
2312         case PORT_B:
2313                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2314                 break;
2315         case PORT_C:
2316                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2317                 break;
2318         case PORT_D:
2319                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2320                 break;
2321         default:
2322                 return connector_status_unknown;
2323         }
2324
2325         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2326                 return connector_status_disconnected;
2327
2328         return intel_dp_detect_dpcd(intel_dp);
2329 }
2330
2331 static struct edid *
2332 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2333 {
2334         struct intel_connector *intel_connector = to_intel_connector(connector);
2335
2336         /* use cached edid if we have one */
2337         if (intel_connector->edid) {
2338                 struct edid *edid;
2339                 int size;
2340
2341                 /* invalid edid */
2342                 if (IS_ERR(intel_connector->edid))
2343                         return NULL;
2344
2345                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2346                 edid = kmalloc(size, GFP_KERNEL);
2347                 if (!edid)
2348                         return NULL;
2349
2350                 memcpy(edid, intel_connector->edid, size);
2351                 return edid;
2352         }
2353
2354         return drm_get_edid(connector, adapter);
2355 }
2356
2357 static int
2358 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2359 {
2360         struct intel_connector *intel_connector = to_intel_connector(connector);
2361
2362         /* use cached edid if we have one */
2363         if (intel_connector->edid) {
2364                 /* invalid edid */
2365                 if (IS_ERR(intel_connector->edid))
2366                         return 0;
2367
2368                 return intel_connector_update_modes(connector,
2369                                                     intel_connector->edid);
2370         }
2371
2372         return intel_ddc_get_modes(connector, adapter);
2373 }
2374
2375 static enum drm_connector_status
2376 intel_dp_detect(struct drm_connector *connector, bool force)
2377 {
2378         struct intel_dp *intel_dp = intel_attached_dp(connector);
2379         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2380         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2381         struct drm_device *dev = connector->dev;
2382         enum drm_connector_status status;
2383         struct edid *edid = NULL;
2384
2385         intel_dp->has_audio = false;
2386
2387         if (HAS_PCH_SPLIT(dev))
2388                 status = ironlake_dp_detect(intel_dp);
2389         else
2390                 status = g4x_dp_detect(intel_dp);
2391
2392         if (status != connector_status_connected)
2393                 return status;
2394
2395         intel_dp_probe_oui(intel_dp);
2396
2397         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2398                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2399         } else {
2400                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2401                 if (edid) {
2402                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2403                         kfree(edid);
2404                 }
2405         }
2406
2407         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2408                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2409         return connector_status_connected;
2410 }
2411
2412 static int intel_dp_get_modes(struct drm_connector *connector)
2413 {
2414         struct intel_dp *intel_dp = intel_attached_dp(connector);
2415         struct intel_connector *intel_connector = to_intel_connector(connector);
2416         struct drm_device *dev = connector->dev;
2417         int ret;
2418
2419         /* We should parse the EDID data and find out if it has an audio sink
2420          */
2421
2422         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2423         if (ret)
2424                 return ret;
2425
2426         /* if eDP has no EDID, fall back to fixed mode */
2427         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2428                 struct drm_display_mode *mode;
2429                 mode = drm_mode_duplicate(dev,
2430                                           intel_connector->panel.fixed_mode);
2431                 if (mode) {
2432                         drm_mode_probed_add(connector, mode);
2433                         return 1;
2434                 }
2435         }
2436         return 0;
2437 }
2438
2439 static bool
2440 intel_dp_detect_audio(struct drm_connector *connector)
2441 {
2442         struct intel_dp *intel_dp = intel_attached_dp(connector);
2443         struct edid *edid;
2444         bool has_audio = false;
2445
2446         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2447         if (edid) {
2448                 has_audio = drm_detect_monitor_audio(edid);
2449                 kfree(edid);
2450         }
2451
2452         return has_audio;
2453 }
2454
2455 static int
2456 intel_dp_set_property(struct drm_connector *connector,
2457                       struct drm_property *property,
2458                       uint64_t val)
2459 {
2460         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2461         struct intel_connector *intel_connector = to_intel_connector(connector);
2462         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2463         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2464         int ret;
2465
2466         ret = drm_object_property_set_value(&connector->base, property, val);
2467         if (ret)
2468                 return ret;
2469
2470         if (property == dev_priv->force_audio_property) {
2471                 int i = val;
2472                 bool has_audio;
2473
2474                 if (i == intel_dp->force_audio)
2475                         return 0;
2476
2477                 intel_dp->force_audio = i;
2478
2479                 if (i == HDMI_AUDIO_AUTO)
2480                         has_audio = intel_dp_detect_audio(connector);
2481                 else
2482                         has_audio = (i == HDMI_AUDIO_ON);
2483
2484                 if (has_audio == intel_dp->has_audio)
2485                         return 0;
2486
2487                 intel_dp->has_audio = has_audio;
2488                 goto done;
2489         }
2490
2491         if (property == dev_priv->broadcast_rgb_property) {
2492                 switch (val) {
2493                 case INTEL_BROADCAST_RGB_AUTO:
2494                         intel_dp->color_range_auto = true;
2495                         break;
2496                 case INTEL_BROADCAST_RGB_FULL:
2497                         intel_dp->color_range_auto = false;
2498                         intel_dp->color_range = 0;
2499                         break;
2500                 case INTEL_BROADCAST_RGB_LIMITED:
2501                         intel_dp->color_range_auto = false;
2502                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2503                         break;
2504                 default:
2505                         return -EINVAL;
2506                 }
2507                 goto done;
2508         }
2509
2510         if (is_edp(intel_dp) &&
2511             property == connector->dev->mode_config.scaling_mode_property) {
2512                 if (val == DRM_MODE_SCALE_NONE) {
2513                         DRM_DEBUG_KMS("no scaling not supported\n");
2514                         return -EINVAL;
2515                 }
2516
2517                 if (intel_connector->panel.fitting_mode == val) {
2518                         /* the eDP scaling property is not changed */
2519                         return 0;
2520                 }
2521                 intel_connector->panel.fitting_mode = val;
2522
2523                 goto done;
2524         }
2525
2526         return -EINVAL;
2527
2528 done:
2529         if (intel_encoder->base.crtc)
2530                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2531
2532         return 0;
2533 }
2534
2535 static void
2536 intel_dp_destroy(struct drm_connector *connector)
2537 {
2538         struct drm_device *dev = connector->dev;
2539         struct intel_dp *intel_dp = intel_attached_dp(connector);
2540         struct intel_connector *intel_connector = to_intel_connector(connector);
2541
2542         if (!IS_ERR_OR_NULL(intel_connector->edid))
2543                 kfree(intel_connector->edid);
2544
2545         if (is_edp(intel_dp)) {
2546                 intel_panel_destroy_backlight(dev);
2547                 intel_panel_fini(&intel_connector->panel);
2548         }
2549
2550         drm_sysfs_connector_remove(connector);
2551         drm_connector_cleanup(connector);
2552         kfree(connector);
2553 }
2554
2555 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2556 {
2557         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2558         struct intel_dp *intel_dp = &intel_dig_port->dp;
2559
2560         i2c_del_adapter(&intel_dp->adapter);
2561         drm_encoder_cleanup(encoder);
2562         if (is_edp(intel_dp)) {
2563                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2564                 ironlake_panel_vdd_off_sync(intel_dp);
2565         }
2566         kfree(intel_dig_port);
2567 }
2568
2569 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2570         .mode_set = intel_dp_mode_set,
2571 };
2572
2573 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2574         .dpms = intel_connector_dpms,
2575         .detect = intel_dp_detect,
2576         .fill_modes = drm_helper_probe_single_connector_modes,
2577         .set_property = intel_dp_set_property,
2578         .destroy = intel_dp_destroy,
2579 };
2580
2581 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2582         .get_modes = intel_dp_get_modes,
2583         .mode_valid = intel_dp_mode_valid,
2584         .best_encoder = intel_best_encoder,
2585 };
2586
2587 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2588         .destroy = intel_dp_encoder_destroy,
2589 };
2590
2591 static void
2592 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2593 {
2594         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2595
2596         intel_dp_check_link_status(intel_dp);
2597 }
2598
2599 /* Return which DP Port should be selected for Transcoder DP control */
2600 int
2601 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2602 {
2603         struct drm_device *dev = crtc->dev;
2604         struct intel_encoder *intel_encoder;
2605         struct intel_dp *intel_dp;
2606
2607         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2608                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2609
2610                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2611                     intel_encoder->type == INTEL_OUTPUT_EDP)
2612                         return intel_dp->output_reg;
2613         }
2614
2615         return -1;
2616 }
2617
2618 /* check the VBT to see whether the eDP is on DP-D port */
2619 bool intel_dpd_is_edp(struct drm_device *dev)
2620 {
2621         struct drm_i915_private *dev_priv = dev->dev_private;
2622         struct child_device_config *p_child;
2623         int i;
2624
2625         if (!dev_priv->child_dev_num)
2626                 return false;
2627
2628         for (i = 0; i < dev_priv->child_dev_num; i++) {
2629                 p_child = dev_priv->child_dev + i;
2630
2631                 if (p_child->dvo_port == PORT_IDPD &&
2632                     p_child->device_type == DEVICE_TYPE_eDP)
2633                         return true;
2634         }
2635         return false;
2636 }
2637
2638 static void
2639 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2640 {
2641         struct intel_connector *intel_connector = to_intel_connector(connector);
2642
2643         intel_attach_force_audio_property(connector);
2644         intel_attach_broadcast_rgb_property(connector);
2645         intel_dp->color_range_auto = true;
2646
2647         if (is_edp(intel_dp)) {
2648                 drm_mode_create_scaling_mode_property(connector->dev);
2649                 drm_object_attach_property(
2650                         &connector->base,
2651                         connector->dev->mode_config.scaling_mode_property,
2652                         DRM_MODE_SCALE_ASPECT);
2653                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2654         }
2655 }
2656
2657 static void
2658 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2659                                     struct intel_dp *intel_dp,
2660                                     struct edp_power_seq *out)
2661 {
2662         struct drm_i915_private *dev_priv = dev->dev_private;
2663         struct edp_power_seq cur, vbt, spec, final;
2664         u32 pp_on, pp_off, pp_div, pp;
2665         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2666
2667         if (HAS_PCH_SPLIT(dev)) {
2668                 pp_control_reg = PCH_PP_CONTROL;
2669                 pp_on_reg = PCH_PP_ON_DELAYS;
2670                 pp_off_reg = PCH_PP_OFF_DELAYS;
2671                 pp_div_reg = PCH_PP_DIVISOR;
2672         } else {
2673                 pp_control_reg = PIPEA_PP_CONTROL;
2674                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2675                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2676                 pp_div_reg = PIPEA_PP_DIVISOR;
2677         }
2678
2679         /* Workaround: Need to write PP_CONTROL with the unlock key as
2680          * the very first thing. */
2681         pp = ironlake_get_pp_control(intel_dp);
2682         I915_WRITE(pp_control_reg, pp);
2683
2684         pp_on = I915_READ(pp_on_reg);
2685         pp_off = I915_READ(pp_off_reg);
2686         pp_div = I915_READ(pp_div_reg);
2687
2688         /* Pull timing values out of registers */
2689         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2690                 PANEL_POWER_UP_DELAY_SHIFT;
2691
2692         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2693                 PANEL_LIGHT_ON_DELAY_SHIFT;
2694
2695         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2696                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2697
2698         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2699                 PANEL_POWER_DOWN_DELAY_SHIFT;
2700
2701         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2702                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2703
2704         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2705                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2706
2707         vbt = dev_priv->edp.pps;
2708
2709         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2710          * our hw here, which are all in 100usec. */
2711         spec.t1_t3 = 210 * 10;
2712         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2713         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2714         spec.t10 = 500 * 10;
2715         /* This one is special and actually in units of 100ms, but zero
2716          * based in the hw (so we need to add 100 ms). But the sw vbt
2717          * table multiplies it with 1000 to make it in units of 100usec,
2718          * too. */
2719         spec.t11_t12 = (510 + 100) * 10;
2720
2721         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2722                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2723
2724         /* Use the max of the register settings and vbt. If both are
2725          * unset, fall back to the spec limits. */
2726 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2727                                        spec.field : \
2728                                        max(cur.field, vbt.field))
2729         assign_final(t1_t3);
2730         assign_final(t8);
2731         assign_final(t9);
2732         assign_final(t10);
2733         assign_final(t11_t12);
2734 #undef assign_final
2735
2736 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2737         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2738         intel_dp->backlight_on_delay = get_delay(t8);
2739         intel_dp->backlight_off_delay = get_delay(t9);
2740         intel_dp->panel_power_down_delay = get_delay(t10);
2741         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2742 #undef get_delay
2743
2744         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2745                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2746                       intel_dp->panel_power_cycle_delay);
2747
2748         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2749                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2750
2751         if (out)
2752                 *out = final;
2753 }
2754
2755 static void
2756 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2757                                               struct intel_dp *intel_dp,
2758                                               struct edp_power_seq *seq)
2759 {
2760         struct drm_i915_private *dev_priv = dev->dev_private;
2761         u32 pp_on, pp_off, pp_div, port_sel = 0;
2762         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2763         int pp_on_reg, pp_off_reg, pp_div_reg;
2764
2765         if (HAS_PCH_SPLIT(dev)) {
2766                 pp_on_reg = PCH_PP_ON_DELAYS;
2767                 pp_off_reg = PCH_PP_OFF_DELAYS;
2768                 pp_div_reg = PCH_PP_DIVISOR;
2769         } else {
2770                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2771                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2772                 pp_div_reg = PIPEA_PP_DIVISOR;
2773         }
2774
2775         if (IS_VALLEYVIEW(dev))
2776                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2777
2778         /* And finally store the new values in the power sequencer. */
2779         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2780                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2781         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2782                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2783         /* Compute the divisor for the pp clock, simply match the Bspec
2784          * formula. */
2785         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2786         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2787                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2788
2789         /* Haswell doesn't have any port selection bits for the panel
2790          * power sequencer any more. */
2791         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2792                 if (is_cpu_edp(intel_dp))
2793                         port_sel = PANEL_POWER_PORT_DP_A;
2794                 else
2795                         port_sel = PANEL_POWER_PORT_DP_D;
2796         }
2797
2798         pp_on |= port_sel;
2799
2800         I915_WRITE(pp_on_reg, pp_on);
2801         I915_WRITE(pp_off_reg, pp_off);
2802         I915_WRITE(pp_div_reg, pp_div);
2803
2804         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2805                       I915_READ(pp_on_reg),
2806                       I915_READ(pp_off_reg),
2807                       I915_READ(pp_div_reg));
2808 }
2809
2810 void
2811 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2812                         struct intel_connector *intel_connector)
2813 {
2814         struct drm_connector *connector = &intel_connector->base;
2815         struct intel_dp *intel_dp = &intel_dig_port->dp;
2816         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2817         struct drm_device *dev = intel_encoder->base.dev;
2818         struct drm_i915_private *dev_priv = dev->dev_private;
2819         struct drm_display_mode *fixed_mode = NULL;
2820         struct edp_power_seq power_seq = { 0 };
2821         enum port port = intel_dig_port->port;
2822         const char *name = NULL;
2823         int type;
2824
2825         /* Preserve the current hw state. */
2826         intel_dp->DP = I915_READ(intel_dp->output_reg);
2827         intel_dp->attached_connector = intel_connector;
2828
2829         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2830                 if (intel_dpd_is_edp(dev))
2831                         intel_dp->is_pch_edp = true;
2832
2833         /*
2834          * FIXME : We need to initialize built-in panels before external panels.
2835          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2836          */
2837         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2838                 type = DRM_MODE_CONNECTOR_eDP;
2839                 intel_encoder->type = INTEL_OUTPUT_EDP;
2840         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2841                 type = DRM_MODE_CONNECTOR_eDP;
2842                 intel_encoder->type = INTEL_OUTPUT_EDP;
2843         } else {
2844                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2845                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2846                  * rewrite it.
2847                  */
2848                 type = DRM_MODE_CONNECTOR_DisplayPort;
2849         }
2850
2851         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2852         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2853
2854         connector->polled = DRM_CONNECTOR_POLL_HPD;
2855         connector->interlace_allowed = true;
2856         connector->doublescan_allowed = 0;
2857
2858         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2859                           ironlake_panel_vdd_work);
2860
2861         intel_connector_attach_encoder(intel_connector, intel_encoder);
2862         drm_sysfs_connector_add(connector);
2863
2864         if (HAS_DDI(dev))
2865                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2866         else
2867                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2868
2869         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2870         if (HAS_DDI(dev)) {
2871                 switch (intel_dig_port->port) {
2872                 case PORT_A:
2873                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2874                         break;
2875                 case PORT_B:
2876                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2877                         break;
2878                 case PORT_C:
2879                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2880                         break;
2881                 case PORT_D:
2882                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2883                         break;
2884                 default:
2885                         BUG();
2886                 }
2887         }
2888
2889         /* Set up the DDC bus. */
2890         switch (port) {
2891         case PORT_A:
2892                 intel_encoder->hpd_pin = HPD_PORT_A;
2893                 name = "DPDDC-A";
2894                 break;
2895         case PORT_B:
2896                 intel_encoder->hpd_pin = HPD_PORT_B;
2897                 name = "DPDDC-B";
2898                 break;
2899         case PORT_C:
2900                 intel_encoder->hpd_pin = HPD_PORT_C;
2901                 name = "DPDDC-C";
2902                 break;
2903         case PORT_D:
2904                 intel_encoder->hpd_pin = HPD_PORT_D;
2905                 name = "DPDDC-D";
2906                 break;
2907         default:
2908                 BUG();
2909         }
2910
2911         if (is_edp(intel_dp))
2912                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2913
2914         intel_dp_i2c_init(intel_dp, intel_connector, name);
2915
2916         /* Cache DPCD and EDID for edp. */
2917         if (is_edp(intel_dp)) {
2918                 bool ret;
2919                 struct drm_display_mode *scan;
2920                 struct edid *edid;
2921
2922                 ironlake_edp_panel_vdd_on(intel_dp);
2923                 ret = intel_dp_get_dpcd(intel_dp);
2924                 ironlake_edp_panel_vdd_off(intel_dp, false);
2925
2926                 if (ret) {
2927                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2928                                 dev_priv->no_aux_handshake =
2929                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2930                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2931                 } else {
2932                         /* if this fails, presume the device is a ghost */
2933                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2934                         intel_dp_encoder_destroy(&intel_encoder->base);
2935                         intel_dp_destroy(connector);
2936                         return;
2937                 }
2938
2939                 /* We now know it's not a ghost, init power sequence regs. */
2940                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2941                                                               &power_seq);
2942
2943                 ironlake_edp_panel_vdd_on(intel_dp);
2944                 edid = drm_get_edid(connector, &intel_dp->adapter);
2945                 if (edid) {
2946                         if (drm_add_edid_modes(connector, edid)) {
2947                                 drm_mode_connector_update_edid_property(connector, edid);
2948                                 drm_edid_to_eld(connector, edid);
2949                         } else {
2950                                 kfree(edid);
2951                                 edid = ERR_PTR(-EINVAL);
2952                         }
2953                 } else {
2954                         edid = ERR_PTR(-ENOENT);
2955                 }
2956                 intel_connector->edid = edid;
2957
2958                 /* prefer fixed mode from EDID if available */
2959                 list_for_each_entry(scan, &connector->probed_modes, head) {
2960                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2961                                 fixed_mode = drm_mode_duplicate(dev, scan);
2962                                 break;
2963                         }
2964                 }
2965
2966                 /* fallback to VBT if available for eDP */
2967                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2968                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2969                         if (fixed_mode)
2970                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2971                 }
2972
2973                 ironlake_edp_panel_vdd_off(intel_dp, false);
2974         }
2975
2976         if (is_edp(intel_dp)) {
2977                 intel_panel_init(&intel_connector->panel, fixed_mode);
2978                 intel_panel_setup_backlight(connector);
2979         }
2980
2981         intel_dp_add_properties(intel_dp, connector);
2982
2983         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2984          * 0xd.  Failure to do so will result in spurious interrupts being
2985          * generated on the port when a cable is not attached.
2986          */
2987         if (IS_G4X(dev) && !IS_GM45(dev)) {
2988                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2989                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2990         }
2991 }
2992
2993 void
2994 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2995 {
2996         struct intel_digital_port *intel_dig_port;
2997         struct intel_encoder *intel_encoder;
2998         struct drm_encoder *encoder;
2999         struct intel_connector *intel_connector;
3000
3001         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3002         if (!intel_dig_port)
3003                 return;
3004
3005         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3006         if (!intel_connector) {
3007                 kfree(intel_dig_port);
3008                 return;
3009         }
3010
3011         intel_encoder = &intel_dig_port->base;
3012         encoder = &intel_encoder->base;
3013
3014         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3015                          DRM_MODE_ENCODER_TMDS);
3016         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3017
3018         intel_encoder->compute_config = intel_dp_compute_config;
3019         intel_encoder->enable = intel_enable_dp;
3020         intel_encoder->pre_enable = intel_pre_enable_dp;
3021         intel_encoder->disable = intel_disable_dp;
3022         intel_encoder->post_disable = intel_post_disable_dp;
3023         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3024
3025         intel_dig_port->port = port;
3026         intel_dig_port->dp.output_reg = output_reg;
3027
3028         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3029         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3030         intel_encoder->cloneable = false;
3031         intel_encoder->hot_plug = intel_dp_hot_plug;
3032
3033         intel_dp_init_connector(intel_dig_port, intel_connector);
3034 }