drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int dpms_mode;
  52         uint8_t link_bw;
  53         uint8_t lane_count;
  54         uint8_t dpcd[4];
  55         struct i2c_adapter adapter;
  56         struct i2c_algo_dp_aux_data algo;
  57         bool is_pch_edp;
  58         uint8_t train_set[4];
  59         uint8_t link_status[DP_LINK_STATUS_SIZE];
  60 };
  61
  62 /**
  63  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  64  * @intel_dp: DP struct
  65  *
  66  * If a CPU or PCH DP output is attached to an eDP panel, this function
  67  * will return true, and false otherwise.
  68  */
  69 static bool is_edp(struct intel_dp *intel_dp)
  70 {
  71         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  72 }
  73
  74 /**
  75  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  76  * @intel_dp: DP struct
  77  *
  78  * Returns true if the given DP struct corresponds to a PCH DP port attached
  79  * to an eDP panel, false otherwise.  Helpful for determining whether we
  80  * may need FDI resources for a given DP output or not.
  81  */
  82 static bool is_pch_edp(struct intel_dp *intel_dp)
  83 {
  84         return intel_dp->is_pch_edp;
  85 }
  86
  87 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  88 {
  89         return container_of(encoder, struct intel_dp, base.base);
  90 }
  91
  92 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  93 {
  94         return container_of(intel_attached_encoder(connector),
  95                             struct intel_dp, base);
  96 }
  97
  98 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
  99 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 100 static void intel_dp_link_down(struct intel_dp *intel_dp);
 101
 102 void
 103 intel_edp_link_config (struct intel_encoder *intel_encoder,
 104                        int *lane_num, int *link_bw)
 105 {
 106         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 107
 108         *lane_num = intel_dp->lane_count;
 109         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 110                 *link_bw = 162000;
 111         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 112                 *link_bw = 270000;
 113 }
 114
 115 static int
 116 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 117 {
 118         int max_lane_count = 4;
 119
 120         if (intel_dp->dpcd[0] >= 0x11) {
 121                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
 122                 switch (max_lane_count) {
 123                 case 1: case 2: case 4:
 124                         break;
 125                 default:
 126                         max_lane_count = 4;
 127                 }
 128         }
 129         return max_lane_count;
 130 }
 131
 132 static int
 133 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 134 {
 135         int max_link_bw = intel_dp->dpcd[1];
 136
 137         switch (max_link_bw) {
 138         case DP_LINK_BW_1_62:
 139         case DP_LINK_BW_2_7:
 140                 break;
 141         default:
 142                 max_link_bw = DP_LINK_BW_1_62;
 143                 break;
 144         }
 145         return max_link_bw;
 146 }
 147
 148 static int
 149 intel_dp_link_clock(uint8_t link_bw)
 150 {
 151         if (link_bw == DP_LINK_BW_2_7)
 152                 return 270000;
 153         else
 154                 return 162000;
 155 }
 156
 157 /* I think this is a fiction */
 158 static int
 159 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 160 {
 161         struct drm_i915_private *dev_priv = dev->dev_private;
 162
 163         if (is_edp(intel_dp))
 164                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 165         else
 166                 return pixel_clock * 3;
 167 }
 168
 169 static int
 170 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 171 {
 172         return (max_link_clock * max_lanes * 8) / 10;
 173 }
 174
 175 static int
 176 intel_dp_mode_valid(struct drm_connector *connector,
 177                     struct drm_display_mode *mode)
 178 {
 179         struct intel_dp *intel_dp = intel_attached_dp(connector);
 180         struct drm_device *dev = connector->dev;
 181         struct drm_i915_private *dev_priv = dev->dev_private;
 182         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 183         int max_lanes = intel_dp_max_lane_count(intel_dp);
 184
 185         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 186                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 187                         return MODE_PANEL;
 188
 189                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 190                         return MODE_PANEL;
 191         }
 192
 193         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 194            which are outside spec tolerances but somehow work by magic */
 195         if (!is_edp(intel_dp) &&
 196             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 197              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 198                 return MODE_CLOCK_HIGH;
 199
 200         if (mode->clock < 10000)
 201                 return MODE_CLOCK_LOW;
 202
 203         return MODE_OK;
 204 }
 205
 206 static uint32_t
 207 pack_aux(uint8_t *src, int src_bytes)
 208 {
 209         int     i;
 210         uint32_t v = 0;
 211
 212         if (src_bytes > 4)
 213                 src_bytes = 4;
 214         for (i = 0; i < src_bytes; i++)
 215                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 216         return v;
 217 }
 218
 219 static void
 220 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 221 {
 222         int i;
 223         if (dst_bytes > 4)
 224                 dst_bytes = 4;
 225         for (i = 0; i < dst_bytes; i++)
 226                 dst[i] = src >> ((3-i) * 8);
 227 }
 228
 229 /* hrawclock is 1/4 the FSB frequency */
 230 static int
 231 intel_hrawclk(struct drm_device *dev)
 232 {
 233         struct drm_i915_private *dev_priv = dev->dev_private;
 234         uint32_t clkcfg;
 235
 236         clkcfg = I915_READ(CLKCFG);
 237         switch (clkcfg & CLKCFG_FSB_MASK) {
 238         case CLKCFG_FSB_400:
 239                 return 100;
 240         case CLKCFG_FSB_533:
 241                 return 133;
 242         case CLKCFG_FSB_667:
 243                 return 166;
 244         case CLKCFG_FSB_800:
 245                 return 200;
 246         case CLKCFG_FSB_1067:
 247                 return 266;
 248         case CLKCFG_FSB_1333:
 249                 return 333;
 250         /* these two are just a guess; one of them might be right */
 251         case CLKCFG_FSB_1600:
 252         case CLKCFG_FSB_1600_ALT:
 253                 return 400;
 254         default:
 255                 return 133;
 256         }
 257 }
 258
 259 static int
 260 intel_dp_aux_ch(struct intel_dp *intel_dp,
 261                 uint8_t *send, int send_bytes,
 262                 uint8_t *recv, int recv_size)
 263 {
 264         uint32_t output_reg = intel_dp->output_reg;
 265         struct drm_device *dev = intel_dp->base.base.dev;
 266         struct drm_i915_private *dev_priv = dev->dev_private;
 267         uint32_t ch_ctl = output_reg + 0x10;
 268         uint32_t ch_data = ch_ctl + 4;
 269         int i;
 270         int recv_bytes;
 271         uint32_t status;
 272         uint32_t aux_clock_divider;
 273         int try, precharge;
 274
 275         /* The clock divider is based off the hrawclk,
 276          * and would like to run at 2MHz. So, take the
 277          * hrawclk value and divide by 2 and use that
 278          *
 279          * Note that PCH attached eDP panels should use a 125MHz input
 280          * clock divider.
 281          */
 282         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 283                 if (IS_GEN6(dev))
 284                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 285                 else
 286                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 287         } else if (HAS_PCH_SPLIT(dev))
 288                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 289         else
 290                 aux_clock_divider = intel_hrawclk(dev) / 2;
 291
 292         if (IS_GEN6(dev))
 293                 precharge = 3;
 294         else
 295                 precharge = 5;
 296
 297         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 298                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 299                           I915_READ(ch_ctl));
 300                 return -EBUSY;
 301         }
 302
 303         /* Must try at least 3 times according to DP spec */
 304         for (try = 0; try < 5; try++) {
 305                 /* Load the send data into the aux channel data registers */
 306                 for (i = 0; i < send_bytes; i += 4)
 307                         I915_WRITE(ch_data + i,
 308                                    pack_aux(send + i, send_bytes - i));
 309
 310                 /* Send the command and wait for it to complete */
 311                 I915_WRITE(ch_ctl,
 312                            DP_AUX_CH_CTL_SEND_BUSY |
 313                            DP_AUX_CH_CTL_TIME_OUT_400us |
 314                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 315                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 316                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 317                            DP_AUX_CH_CTL_DONE |
 318                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 319                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 320                 for (;;) {
 321                         status = I915_READ(ch_ctl);
 322                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 323                                 break;
 324                         udelay(100);
 325                 }
 326
 327                 /* Clear done status and any errors */
 328                 I915_WRITE(ch_ctl,
 329                            status |
 330                            DP_AUX_CH_CTL_DONE |
 331                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 332                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 333                 if (status & DP_AUX_CH_CTL_DONE)
 334                         break;
 335         }
 336
 337         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 338                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 339                 return -EBUSY;
 340         }
 341
 342         /* Check for timeout or receive error.
 343          * Timeouts occur when the sink is not connected
 344          */
 345         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 346                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 347                 return -EIO;
 348         }
 349
 350         /* Timeouts occur when the device isn't connected, so they're
 351          * "normal" -- don't fill the kernel log with these */
 352         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 353                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 354                 return -ETIMEDOUT;
 355         }
 356
 357         /* Unload any bytes sent back from the other side */
 358         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 359                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 360         if (recv_bytes > recv_size)
 361                 recv_bytes = recv_size;
 362
 363         for (i = 0; i < recv_bytes; i += 4)
 364                 unpack_aux(I915_READ(ch_data + i),
 365                            recv + i, recv_bytes - i);
 366
 367         return recv_bytes;
 368 }
 369
 370 /* Write data to the aux channel in native mode */
 371 static int
 372 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 373                           uint16_t address, uint8_t *send, int send_bytes)
 374 {
 375         int ret;
 376         uint8_t msg[20];
 377         int msg_bytes;
 378         uint8_t ack;
 379
 380         if (send_bytes > 16)
 381                 return -1;
 382         msg[0] = AUX_NATIVE_WRITE << 4;
 383         msg[1] = address >> 8;
 384         msg[2] = address & 0xff;
 385         msg[3] = send_bytes - 1;
 386         memcpy(&msg[4], send, send_bytes);
 387         msg_bytes = send_bytes + 4;
 388         for (;;) {
 389                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 390                 if (ret < 0)
 391                         return ret;
 392                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 393                         break;
 394                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 395                         udelay(100);
 396                 else
 397                         return -EIO;
 398         }
 399         return send_bytes;
 400 }
 401
 402 /* Write a single byte to the aux channel in native mode */
 403 static int
 404 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 405                             uint16_t address, uint8_t byte)
 406 {
 407         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 408 }
 409
 410 /* read bytes from a native aux channel */
 411 static int
 412 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 413                          uint16_t address, uint8_t *recv, int recv_bytes)
 414 {
 415         uint8_t msg[4];
 416         int msg_bytes;
 417         uint8_t reply[20];
 418         int reply_bytes;
 419         uint8_t ack;
 420         int ret;
 421
 422         msg[0] = AUX_NATIVE_READ << 4;
 423         msg[1] = address >> 8;
 424         msg[2] = address & 0xff;
 425         msg[3] = recv_bytes - 1;
 426
 427         msg_bytes = 4;
 428         reply_bytes = recv_bytes + 1;
 429
 430         for (;;) {
 431                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 432                                       reply, reply_bytes);
 433                 if (ret == 0)
 434                         return -EPROTO;
 435                 if (ret < 0)
 436                         return ret;
 437                 ack = reply[0];
 438                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 439                         memcpy(recv, reply + 1, ret - 1);
 440                         return ret - 1;
 441                 }
 442                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 443                         udelay(100);
 444                 else
 445                         return -EIO;
 446         }
 447 }
 448
 449 static int
 450 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 451                     uint8_t write_byte, uint8_t *read_byte)
 452 {
 453         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 454         struct intel_dp *intel_dp = container_of(adapter,
 455                                                 struct intel_dp,
 456                                                 adapter);
 457         uint16_t address = algo_data->address;
 458         uint8_t msg[5];
 459         uint8_t reply[2];
 460         int msg_bytes;
 461         int reply_bytes;
 462         int ret;
 463
 464         /* Set up the command byte */
 465         if (mode & MODE_I2C_READ)
 466                 msg[0] = AUX_I2C_READ << 4;
 467         else
 468                 msg[0] = AUX_I2C_WRITE << 4;
 469
 470         if (!(mode & MODE_I2C_STOP))
 471                 msg[0] |= AUX_I2C_MOT << 4;
 472
 473         msg[1] = address >> 8;
 474         msg[2] = address;
 475
 476         switch (mode) {
 477         case MODE_I2C_WRITE:
 478                 msg[3] = 0;
 479                 msg[4] = write_byte;
 480                 msg_bytes = 5;
 481                 reply_bytes = 1;
 482                 break;
 483         case MODE_I2C_READ:
 484                 msg[3] = 0;
 485                 msg_bytes = 4;
 486                 reply_bytes = 2;
 487                 break;
 488         default:
 489                 msg_bytes = 3;
 490                 reply_bytes = 1;
 491                 break;
 492         }
 493
 494         for (;;) {
 495           ret = intel_dp_aux_ch(intel_dp,
 496                                 msg, msg_bytes,
 497                                 reply, reply_bytes);
 498                 if (ret < 0) {
 499                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 500                         return ret;
 501                 }
 502                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 503                 case AUX_I2C_REPLY_ACK:
 504                         if (mode == MODE_I2C_READ) {
 505                                 *read_byte = reply[1];
 506                         }
 507                         return reply_bytes - 1;
 508                 case AUX_I2C_REPLY_NACK:
 509                         DRM_DEBUG_KMS("aux_ch nack\n");
 510                         return -EREMOTEIO;
 511                 case AUX_I2C_REPLY_DEFER:
 512                         DRM_DEBUG_KMS("aux_ch defer\n");
 513                         udelay(100);
 514                         break;
 515                 default:
 516                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 517                         return -EREMOTEIO;
 518                 }
 519         }
 520 }
 521
 522 static int
 523 intel_dp_i2c_init(struct intel_dp *intel_dp,
 524                   struct intel_connector *intel_connector, const char *name)
 525 {
 526         DRM_DEBUG_KMS("i2c_init %s\n", name);
 527         intel_dp->algo.running = false;
 528         intel_dp->algo.address = 0;
 529         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 530
 531         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 532         intel_dp->adapter.owner = THIS_MODULE;
 533         intel_dp->adapter.class = I2C_CLASS_DDC;
 534         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 535         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 536         intel_dp->adapter.algo_data = &intel_dp->algo;
 537         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 538
 539         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 540 }
 541
 542 static bool
 543 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 544                     struct drm_display_mode *adjusted_mode)
 545 {
 546         struct drm_device *dev = encoder->dev;
 547         struct drm_i915_private *dev_priv = dev->dev_private;
 548         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 549         int lane_count, clock;
 550         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 551         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 552         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 553
 554         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 555                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 556                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 557                                         mode, adjusted_mode);
 558                 /*
 559                  * the mode->clock is used to calculate the Data&Link M/N
 560                  * of the pipe. For the eDP the fixed clock should be used.
 561                  */
 562                 mode->clock = dev_priv->panel_fixed_mode->clock;
 563         }
 564
 565         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 566                 for (clock = 0; clock <= max_clock; clock++) {
 567                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 568
 569                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 570                                         <= link_avail) {
 571                                 intel_dp->link_bw = bws[clock];
 572                                 intel_dp->lane_count = lane_count;
 573                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 574                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 575                                                 "count %d clock %d\n",
 576                                        intel_dp->link_bw, intel_dp->lane_count,
 577                                        adjusted_mode->clock);
 578                                 return true;
 579                         }
 580                 }
 581         }
 582
 583         if (is_edp(intel_dp)) {
 584                 /* okay we failed just pick the highest */
 585                 intel_dp->lane_count = max_lane_count;
 586                 intel_dp->link_bw = bws[max_clock];
 587                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 588                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 589                               "count %d clock %d\n",
 590                               intel_dp->link_bw, intel_dp->lane_count,
 591                               adjusted_mode->clock);
 592
 593                 return true;
 594         }
 595
 596         return false;
 597 }
 598
 599 struct intel_dp_m_n {
 600         uint32_t        tu;
 601         uint32_t        gmch_m;
 602         uint32_t        gmch_n;
 603         uint32_t        link_m;
 604         uint32_t        link_n;
 605 };
 606
 607 static void
 608 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 609 {
 610         while (*num > 0xffffff || *den > 0xffffff) {
 611                 *num >>= 1;
 612                 *den >>= 1;
 613         }
 614 }
 615
 616 static void
 617 intel_dp_compute_m_n(int bpp,
 618                      int nlanes,
 619                      int pixel_clock,
 620                      int link_clock,
 621                      struct intel_dp_m_n *m_n)
 622 {
 623         m_n->tu = 64;
 624         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 625         m_n->gmch_n = link_clock * nlanes;
 626         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 627         m_n->link_m = pixel_clock;
 628         m_n->link_n = link_clock;
 629         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 630 }
 631
 632 bool intel_pch_has_edp(struct drm_crtc *crtc)
 633 {
 634         struct drm_device *dev = crtc->dev;
 635         struct drm_mode_config *mode_config = &dev->mode_config;
 636         struct drm_encoder *encoder;
 637
 638         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 639                 struct intel_dp *intel_dp;
 640
 641                 if (encoder->crtc != crtc)
 642                         continue;
 643
 644                 intel_dp = enc_to_intel_dp(encoder);
 645                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
 646                         return intel_dp->is_pch_edp;
 647         }
 648         return false;
 649 }
 650
 651 void
 652 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 653                  struct drm_display_mode *adjusted_mode)
 654 {
 655         struct drm_device *dev = crtc->dev;
 656         struct drm_mode_config *mode_config = &dev->mode_config;
 657         struct drm_encoder *encoder;
 658         struct drm_i915_private *dev_priv = dev->dev_private;
 659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 660         int lane_count = 4, bpp = 24;
 661         struct intel_dp_m_n m_n;
 662
 663         /*
 664          * Find the lane count in the intel_encoder private
 665          */
 666         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 667                 struct intel_dp *intel_dp;
 668
 669                 if (encoder->crtc != crtc)
 670                         continue;
 671
 672                 intel_dp = enc_to_intel_dp(encoder);
 673                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 674                         lane_count = intel_dp->lane_count;
 675                         break;
 676                 } else if (is_edp(intel_dp)) {
 677                         lane_count = dev_priv->edp.lanes;
 678                         bpp = dev_priv->edp.bpp;
 679                         break;
 680                 }
 681         }
 682
 683         /*
 684          * Compute the GMCH and Link ratios. The '3' here is
 685          * the number of bytes_per_pixel post-LUT, which we always
 686          * set up for 8-bits of R/G/B, or 3 bytes total.
 687          */
 688         intel_dp_compute_m_n(bpp, lane_count,
 689                              mode->clock, adjusted_mode->clock, &m_n);
 690
 691         if (HAS_PCH_SPLIT(dev)) {
 692                 if (intel_crtc->pipe == 0) {
 693                         I915_WRITE(TRANSA_DATA_M1,
 694                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 695                                    m_n.gmch_m);
 696                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 697                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 698                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 699                 } else {
 700                         I915_WRITE(TRANSB_DATA_M1,
 701                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 702                                    m_n.gmch_m);
 703                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 704                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 705                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 706                 }
 707         } else {
 708                 if (intel_crtc->pipe == 0) {
 709                         I915_WRITE(PIPEA_GMCH_DATA_M,
 710                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 711                                    m_n.gmch_m);
 712                         I915_WRITE(PIPEA_GMCH_DATA_N,
 713                                    m_n.gmch_n);
 714                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 715                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 716                 } else {
 717                         I915_WRITE(PIPEB_GMCH_DATA_M,
 718                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 719                                    m_n.gmch_m);
 720                         I915_WRITE(PIPEB_GMCH_DATA_N,
 721                                         m_n.gmch_n);
 722                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 723                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 724                 }
 725         }
 726 }
 727
 728 static void
 729 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 730                   struct drm_display_mode *adjusted_mode)
 731 {
 732         struct drm_device *dev = encoder->dev;
 733         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 734         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 736
 737         intel_dp->DP = (DP_VOLTAGE_0_4 |
 738                        DP_PRE_EMPHASIS_0);
 739
 740         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 741                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 742         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 743                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 744
 745         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 746                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 747         else
 748                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 749
 750         switch (intel_dp->lane_count) {
 751         case 1:
 752                 intel_dp->DP |= DP_PORT_WIDTH_1;
 753                 break;
 754         case 2:
 755                 intel_dp->DP |= DP_PORT_WIDTH_2;
 756                 break;
 757         case 4:
 758                 intel_dp->DP |= DP_PORT_WIDTH_4;
 759                 break;
 760         }
 761         if (intel_dp->has_audio)
 762                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 763
 764         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 765         intel_dp->link_configuration[0] = intel_dp->link_bw;
 766         intel_dp->link_configuration[1] = intel_dp->lane_count;
 767
 768         /*
 769          * Check for DPCD version > 1.1 and enhanced framing support
 770          */
 771         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 772                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 773                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 774         }
 775
 776         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 777         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 778                 intel_dp->DP |= DP_PIPEB_SELECT;
 779
 780         if (is_edp(intel_dp)) {
 781                 /* don't miss out required setting for eDP */
 782                 intel_dp->DP |= DP_PLL_ENABLE;
 783                 if (adjusted_mode->clock < 200000)
 784                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 785                 else
 786                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 787         }
 788 }
 789
 790 /* Returns true if the panel was already on when called */
 791 static bool ironlake_edp_panel_on (struct drm_device *dev)
 792 {
 793         struct drm_i915_private *dev_priv = dev->dev_private;
 794         u32 pp;
 795
 796         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 797                 return true;
 798
 799         pp = I915_READ(PCH_PP_CONTROL);
 800
 801         /* ILK workaround: disable reset around power sequence */
 802         pp &= ~PANEL_POWER_RESET;
 803         I915_WRITE(PCH_PP_CONTROL, pp);
 804         POSTING_READ(PCH_PP_CONTROL);
 805
 806         pp |= POWER_TARGET_ON;
 807         I915_WRITE(PCH_PP_CONTROL, pp);
 808
 809         /* Ouch. We need to wait here for some panels, like Dell e6510
 810          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
 811          */
 812         msleep(300);
 813
 814         if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000))
 815                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 816                           I915_READ(PCH_PP_STATUS));
 817
 818         pp &= ~(PANEL_UNLOCK_REGS);
 819         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 820         I915_WRITE(PCH_PP_CONTROL, pp);
 821         POSTING_READ(PCH_PP_CONTROL);
 822
 823         return false;
 824 }
 825
 826 static void ironlake_edp_panel_off (struct drm_device *dev)
 827 {
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829         u32 pp;
 830
 831         pp = I915_READ(PCH_PP_CONTROL);
 832
 833         /* ILK workaround: disable reset around power sequence */
 834         pp &= ~PANEL_POWER_RESET;
 835         I915_WRITE(PCH_PP_CONTROL, pp);
 836         POSTING_READ(PCH_PP_CONTROL);
 837
 838         pp &= ~POWER_TARGET_ON;
 839         I915_WRITE(PCH_PP_CONTROL, pp);
 840
 841         if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000))
 842                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 843                           I915_READ(PCH_PP_STATUS));
 844
 845         /* Make sure VDD is enabled so DP AUX will work */
 846         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 847         I915_WRITE(PCH_PP_CONTROL, pp);
 848         POSTING_READ(PCH_PP_CONTROL);
 849
 850         /* Ouch. We need to wait here for some panels, like Dell e6510
 851          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
 852          */
 853         msleep(300);
 854 }
 855
 856 static void ironlake_edp_panel_vdd_on(struct drm_device *dev)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859         u32 pp;
 860
 861         pp = I915_READ(PCH_PP_CONTROL);
 862         pp |= EDP_FORCE_VDD;
 863         I915_WRITE(PCH_PP_CONTROL, pp);
 864         POSTING_READ(PCH_PP_CONTROL);
 865         msleep(300);
 866 }
 867
 868 static void ironlake_edp_panel_vdd_off(struct drm_device *dev)
 869 {
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         u32 pp;
 872
 873         pp = I915_READ(PCH_PP_CONTROL);
 874         pp &= ~EDP_FORCE_VDD;
 875         I915_WRITE(PCH_PP_CONTROL, pp);
 876         POSTING_READ(PCH_PP_CONTROL);
 877         msleep(300);
 878 }
 879
 880 static void ironlake_edp_backlight_on (struct drm_device *dev)
 881 {
 882         struct drm_i915_private *dev_priv = dev->dev_private;
 883         u32 pp;
 884
 885         DRM_DEBUG_KMS("\n");
 886         pp = I915_READ(PCH_PP_CONTROL);
 887         pp |= EDP_BLC_ENABLE;
 888         I915_WRITE(PCH_PP_CONTROL, pp);
 889 }
 890
 891 static void ironlake_edp_backlight_off (struct drm_device *dev)
 892 {
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894         u32 pp;
 895
 896         DRM_DEBUG_KMS("\n");
 897         pp = I915_READ(PCH_PP_CONTROL);
 898         pp &= ~EDP_BLC_ENABLE;
 899         I915_WRITE(PCH_PP_CONTROL, pp);
 900 }
 901
 902 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 903 {
 904         struct drm_device *dev = encoder->dev;
 905         struct drm_i915_private *dev_priv = dev->dev_private;
 906         u32 dpa_ctl;
 907
 908         DRM_DEBUG_KMS("\n");
 909         dpa_ctl = I915_READ(DP_A);
 910         dpa_ctl &= ~DP_PLL_ENABLE;
 911         I915_WRITE(DP_A, dpa_ctl);
 912 }
 913
 914 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 915 {
 916         struct drm_device *dev = encoder->dev;
 917         struct drm_i915_private *dev_priv = dev->dev_private;
 918         u32 dpa_ctl;
 919
 920         dpa_ctl = I915_READ(DP_A);
 921         dpa_ctl |= DP_PLL_ENABLE;
 922         I915_WRITE(DP_A, dpa_ctl);
 923         POSTING_READ(DP_A);
 924         udelay(200);
 925 }
 926
 927 static void intel_dp_prepare(struct drm_encoder *encoder)
 928 {
 929         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 930         struct drm_device *dev = encoder->dev;
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 933
 934         if (is_edp(intel_dp)) {
 935                 ironlake_edp_panel_off(dev);
 936                 ironlake_edp_backlight_off(dev);
 937                 ironlake_edp_panel_vdd_on(dev);
 938                 ironlake_edp_pll_on(encoder);
 939         }
 940         if (dp_reg & DP_PORT_EN)
 941                 intel_dp_link_down(intel_dp);
 942 }
 943
 944 static void intel_dp_commit(struct drm_encoder *encoder)
 945 {
 946         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 947         struct drm_device *dev = encoder->dev;
 948
 949         intel_dp_start_link_train(intel_dp);
 950
 951         if (is_edp(intel_dp))
 952                 ironlake_edp_panel_on(dev);
 953
 954         intel_dp_complete_link_train(intel_dp);
 955
 956         if (is_edp(intel_dp))
 957                 ironlake_edp_backlight_on(dev);
 958 }
 959
 960 static void
 961 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 962 {
 963         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 964         struct drm_device *dev = encoder->dev;
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 967
 968         if (mode != DRM_MODE_DPMS_ON) {
 969                 if (is_edp(intel_dp)) {
 970                         ironlake_edp_backlight_off(dev);
 971                         ironlake_edp_panel_off(dev);
 972                 }
 973                 if (dp_reg & DP_PORT_EN)
 974                         intel_dp_link_down(intel_dp);
 975                 if (is_edp(intel_dp))
 976                         ironlake_edp_pll_off(encoder);
 977         } else {
 978                 if (!(dp_reg & DP_PORT_EN)) {
 979                         intel_dp_start_link_train(intel_dp);
 980                         if (is_edp(intel_dp))
 981                                 ironlake_edp_panel_on(dev);
 982                         intel_dp_complete_link_train(intel_dp);
 983                         if (is_edp(intel_dp))
 984                                 ironlake_edp_backlight_on(dev);
 985                 }
 986         }
 987         intel_dp->dpms_mode = mode;
 988 }
 989
 990 /*
 991  * Fetch AUX CH registers 0x202 - 0x207 which contain
 992  * link status information
 993  */
 994 static bool
 995 intel_dp_get_link_status(struct intel_dp *intel_dp)
 996 {
 997         int ret;
 998
 999         ret = intel_dp_aux_native_read(intel_dp,
1000                                        DP_LANE0_1_STATUS,
1001                                        intel_dp->link_status, DP_LINK_STATUS_SIZE);
1002         if (ret != DP_LINK_STATUS_SIZE)
1003                 return false;
1004         return true;
1005 }
1006
1007 static uint8_t
1008 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1009                      int r)
1010 {
1011         return link_status[r - DP_LANE0_1_STATUS];
1012 }
1013
1014 static uint8_t
1015 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1016                                  int lane)
1017 {
1018         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1019         int         s = ((lane & 1) ?
1020                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1021                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1022         uint8_t l = intel_dp_link_status(link_status, i);
1023
1024         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1025 }
1026
1027 static uint8_t
1028 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1029                                       int lane)
1030 {
1031         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1032         int         s = ((lane & 1) ?
1033                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1034                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1035         uint8_t l = intel_dp_link_status(link_status, i);
1036
1037         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1038 }
1039
1040
1041 #if 0
1042 static char     *voltage_names[] = {
1043         "0.4V", "0.6V", "0.8V", "1.2V"
1044 };
1045 static char     *pre_emph_names[] = {
1046         "0dB", "3.5dB", "6dB", "9.5dB"
1047 };
1048 static char     *link_train_names[] = {
1049         "pattern 1", "pattern 2", "idle", "off"
1050 };
1051 #endif
1052
1053 /*
1054  * These are source-specific values; current Intel hardware supports
1055  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1056  */
1057 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1058
1059 static uint8_t
1060 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1061 {
1062         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1063         case DP_TRAIN_VOLTAGE_SWING_400:
1064                 return DP_TRAIN_PRE_EMPHASIS_6;
1065         case DP_TRAIN_VOLTAGE_SWING_600:
1066                 return DP_TRAIN_PRE_EMPHASIS_6;
1067         case DP_TRAIN_VOLTAGE_SWING_800:
1068                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1069         case DP_TRAIN_VOLTAGE_SWING_1200:
1070         default:
1071                 return DP_TRAIN_PRE_EMPHASIS_0;
1072         }
1073 }
1074
1075 static void
1076 intel_get_adjust_train(struct intel_dp *intel_dp)
1077 {
1078         uint8_t v = 0;
1079         uint8_t p = 0;
1080         int lane;
1081
1082         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1083                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1084                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1085
1086                 if (this_v > v)
1087                         v = this_v;
1088                 if (this_p > p)
1089                         p = this_p;
1090         }
1091
1092         if (v >= I830_DP_VOLTAGE_MAX)
1093                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1094
1095         if (p >= intel_dp_pre_emphasis_max(v))
1096                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1097
1098         for (lane = 0; lane < 4; lane++)
1099                 intel_dp->train_set[lane] = v | p;
1100 }
1101
1102 static uint32_t
1103 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1104 {
1105         uint32_t        signal_levels = 0;
1106
1107         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1108         case DP_TRAIN_VOLTAGE_SWING_400:
1109         default:
1110                 signal_levels |= DP_VOLTAGE_0_4;
1111                 break;
1112         case DP_TRAIN_VOLTAGE_SWING_600:
1113                 signal_levels |= DP_VOLTAGE_0_6;
1114                 break;
1115         case DP_TRAIN_VOLTAGE_SWING_800:
1116                 signal_levels |= DP_VOLTAGE_0_8;
1117                 break;
1118         case DP_TRAIN_VOLTAGE_SWING_1200:
1119                 signal_levels |= DP_VOLTAGE_1_2;
1120                 break;
1121         }
1122         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1123         case DP_TRAIN_PRE_EMPHASIS_0:
1124         default:
1125                 signal_levels |= DP_PRE_EMPHASIS_0;
1126                 break;
1127         case DP_TRAIN_PRE_EMPHASIS_3_5:
1128                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1129                 break;
1130         case DP_TRAIN_PRE_EMPHASIS_6:
1131                 signal_levels |= DP_PRE_EMPHASIS_6;
1132                 break;
1133         case DP_TRAIN_PRE_EMPHASIS_9_5:
1134                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1135                 break;
1136         }
1137         return signal_levels;
1138 }
1139
1140 /* Gen6's DP voltage swing and pre-emphasis control */
1141 static uint32_t
1142 intel_gen6_edp_signal_levels(uint8_t train_set)
1143 {
1144         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1145         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1146                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1147         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1148                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1149         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1150                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1151         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1152                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1153         default:
1154                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1155                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1156         }
1157 }
1158
1159 static uint8_t
1160 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1161                       int lane)
1162 {
1163         int i = DP_LANE0_1_STATUS + (lane >> 1);
1164         int s = (lane & 1) * 4;
1165         uint8_t l = intel_dp_link_status(link_status, i);
1166
1167         return (l >> s) & 0xf;
1168 }
1169
1170 /* Check for clock recovery is done on all channels */
1171 static bool
1172 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1173 {
1174         int lane;
1175         uint8_t lane_status;
1176
1177         for (lane = 0; lane < lane_count; lane++) {
1178                 lane_status = intel_get_lane_status(link_status, lane);
1179                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1180                         return false;
1181         }
1182         return true;
1183 }
1184
1185 /* Check to see if channel eq is done on all channels */
1186 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1187                          DP_LANE_CHANNEL_EQ_DONE|\
1188                          DP_LANE_SYMBOL_LOCKED)
1189 static bool
1190 intel_channel_eq_ok(struct intel_dp *intel_dp)
1191 {
1192         uint8_t lane_align;
1193         uint8_t lane_status;
1194         int lane;
1195
1196         lane_align = intel_dp_link_status(intel_dp->link_status,
1197                                           DP_LANE_ALIGN_STATUS_UPDATED);
1198         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1199                 return false;
1200         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1201                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1202                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1203                         return false;
1204         }
1205         return true;
1206 }
1207
1208 static bool
1209 intel_dp_set_link_train(struct intel_dp *intel_dp,
1210                         uint32_t dp_reg_value,
1211                         uint8_t dp_train_pat)
1212 {
1213         struct drm_device *dev = intel_dp->base.base.dev;
1214         struct drm_i915_private *dev_priv = dev->dev_private;
1215         int ret;
1216
1217         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1218         POSTING_READ(intel_dp->output_reg);
1219
1220         intel_dp_aux_native_write_1(intel_dp,
1221                                     DP_TRAINING_PATTERN_SET,
1222                                     dp_train_pat);
1223
1224         ret = intel_dp_aux_native_write(intel_dp,
1225                                         DP_TRAINING_LANE0_SET,
1226                                         intel_dp->train_set, 4);
1227         if (ret != 4)
1228                 return false;
1229
1230         return true;
1231 }
1232
1233 /* Enable corresponding port and start training pattern 1 */
1234 static void
1235 intel_dp_start_link_train(struct intel_dp *intel_dp)
1236 {
1237         struct drm_device *dev = intel_dp->base.base.dev;
1238         struct drm_i915_private *dev_priv = dev->dev_private;
1239         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1240         int i;
1241         uint8_t voltage;
1242         bool clock_recovery = false;
1243         int tries;
1244         u32 reg;
1245         uint32_t DP = intel_dp->DP;
1246
1247         /* Enable output, wait for it to become active */
1248         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1249         POSTING_READ(intel_dp->output_reg);
1250         intel_wait_for_vblank(dev, intel_crtc->pipe);
1251
1252         /* Write the link configuration data */
1253         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1254                                   intel_dp->link_configuration,
1255                                   DP_LINK_CONFIGURATION_SIZE);
1256
1257         DP |= DP_PORT_EN;
1258         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1259                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1260         else
1261                 DP &= ~DP_LINK_TRAIN_MASK;
1262         memset(intel_dp->train_set, 0, 4);
1263         voltage = 0xff;
1264         tries = 0;
1265         clock_recovery = false;
1266         for (;;) {
1267                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1268                 uint32_t    signal_levels;
1269                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1270                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1271                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1272                 } else {
1273                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1274                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1275                 }
1276
1277                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1278                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1279                 else
1280                         reg = DP | DP_LINK_TRAIN_PAT_1;
1281
1282                 if (!intel_dp_set_link_train(intel_dp, reg,
1283                                              DP_TRAINING_PATTERN_1))
1284                         break;
1285                 /* Set training pattern 1 */
1286
1287                 udelay(100);
1288                 if (!intel_dp_get_link_status(intel_dp))
1289                         break;
1290
1291                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1292                         clock_recovery = true;
1293                         break;
1294                 }
1295
1296                 /* Check to see if we've tried the max voltage */
1297                 for (i = 0; i < intel_dp->lane_count; i++)
1298                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1299                                 break;
1300                 if (i == intel_dp->lane_count)
1301                         break;
1302
1303                 /* Check to see if we've tried the same voltage 5 times */
1304                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1305                         ++tries;
1306                         if (tries == 5)
1307                                 break;
1308                 } else
1309                         tries = 0;
1310                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1311
1312                 /* Compute new intel_dp->train_set as requested by target */
1313                 intel_get_adjust_train(intel_dp);
1314         }
1315
1316         intel_dp->DP = DP;
1317 }
1318
1319 static void
1320 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1321 {
1322         struct drm_device *dev = intel_dp->base.base.dev;
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         bool channel_eq = false;
1325         int tries;
1326         u32 reg;
1327         uint32_t DP = intel_dp->DP;
1328
1329         /* channel equalization */
1330         tries = 0;
1331         channel_eq = false;
1332         for (;;) {
1333                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1334                 uint32_t    signal_levels;
1335
1336                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1337                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1338                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1339                 } else {
1340                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1341                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1342                 }
1343
1344                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1345                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1346                 else
1347                         reg = DP | DP_LINK_TRAIN_PAT_2;
1348
1349                 /* channel eq pattern */
1350                 if (!intel_dp_set_link_train(intel_dp, reg,
1351                                              DP_TRAINING_PATTERN_2))
1352                         break;
1353
1354                 udelay(400);
1355                 if (!intel_dp_get_link_status(intel_dp))
1356                         break;
1357
1358                 if (intel_channel_eq_ok(intel_dp)) {
1359                         channel_eq = true;
1360                         break;
1361                 }
1362
1363                 /* Try 5 times */
1364                 if (tries > 5)
1365                         break;
1366
1367                 /* Compute new intel_dp->train_set as requested by target */
1368                 intel_get_adjust_train(intel_dp);
1369                 ++tries;
1370         }
1371
1372         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1373                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1374         else
1375                 reg = DP | DP_LINK_TRAIN_OFF;
1376
1377         I915_WRITE(intel_dp->output_reg, reg);
1378         POSTING_READ(intel_dp->output_reg);
1379         intel_dp_aux_native_write_1(intel_dp,
1380                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1381 }
1382
1383 static void
1384 intel_dp_link_down(struct intel_dp *intel_dp)
1385 {
1386         struct drm_device *dev = intel_dp->base.base.dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         uint32_t DP = intel_dp->DP;
1389
1390         DRM_DEBUG_KMS("\n");
1391
1392         if (is_edp(intel_dp)) {
1393                 DP &= ~DP_PLL_ENABLE;
1394                 I915_WRITE(intel_dp->output_reg, DP);
1395                 POSTING_READ(intel_dp->output_reg);
1396                 udelay(100);
1397         }
1398
1399         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1400                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1401                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1402         } else {
1403                 DP &= ~DP_LINK_TRAIN_MASK;
1404                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1405         }
1406         POSTING_READ(intel_dp->output_reg);
1407
1408         msleep(17);
1409
1410         if (is_edp(intel_dp))
1411                 DP |= DP_LINK_TRAIN_OFF;
1412         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1413         POSTING_READ(intel_dp->output_reg);
1414 }
1415
1416 /*
1417  * According to DP spec
1418  * 5.1.2:
1419  *  1. Read DPCD
1420  *  2. Configure link according to Receiver Capabilities
1421  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1422  *  4. Check link status on receipt of hot-plug interrupt
1423  */
1424
1425 static void
1426 intel_dp_check_link_status(struct intel_dp *intel_dp)
1427 {
1428         if (!intel_dp->base.base.crtc)
1429                 return;
1430
1431         if (!intel_dp_get_link_status(intel_dp)) {
1432                 intel_dp_link_down(intel_dp);
1433                 return;
1434         }
1435
1436         if (!intel_channel_eq_ok(intel_dp)) {
1437                 intel_dp_start_link_train(intel_dp);
1438                 intel_dp_complete_link_train(intel_dp);
1439         }
1440 }
1441
1442 static enum drm_connector_status
1443 ironlake_dp_detect(struct drm_connector *connector)
1444 {
1445         struct intel_dp *intel_dp = intel_attached_dp(connector);
1446         enum drm_connector_status status;
1447
1448         /* Panel needs power for AUX to work */
1449         if (is_edp(intel_dp))
1450                 ironlake_edp_panel_vdd_on(connector->dev);
1451         status = connector_status_disconnected;
1452         if (intel_dp_aux_native_read(intel_dp,
1453                                      0x000, intel_dp->dpcd,
1454                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1455         {
1456                 if (intel_dp->dpcd[0] != 0)
1457                         status = connector_status_connected;
1458         }
1459         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1460                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1461         if (is_edp(intel_dp))
1462                 ironlake_edp_panel_vdd_off(connector->dev);
1463         return status;
1464 }
1465
1466 /**
1467  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1468  *
1469  * \return true if DP port is connected.
1470  * \return false if DP port is disconnected.
1471  */
1472 static enum drm_connector_status
1473 intel_dp_detect(struct drm_connector *connector, bool force)
1474 {
1475         struct intel_dp *intel_dp = intel_attached_dp(connector);
1476         struct drm_device *dev = intel_dp->base.base.dev;
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478         uint32_t temp, bit;
1479         enum drm_connector_status status;
1480
1481         intel_dp->has_audio = false;
1482
1483         if (HAS_PCH_SPLIT(dev))
1484                 return ironlake_dp_detect(connector);
1485
1486         switch (intel_dp->output_reg) {
1487         case DP_B:
1488                 bit = DPB_HOTPLUG_INT_STATUS;
1489                 break;
1490         case DP_C:
1491                 bit = DPC_HOTPLUG_INT_STATUS;
1492                 break;
1493         case DP_D:
1494                 bit = DPD_HOTPLUG_INT_STATUS;
1495                 break;
1496         default:
1497                 return connector_status_unknown;
1498         }
1499
1500         temp = I915_READ(PORT_HOTPLUG_STAT);
1501
1502         if ((temp & bit) == 0)
1503                 return connector_status_disconnected;
1504
1505         status = connector_status_disconnected;
1506         if (intel_dp_aux_native_read(intel_dp,
1507                                      0x000, intel_dp->dpcd,
1508                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1509         {
1510                 if (intel_dp->dpcd[0] != 0)
1511                         status = connector_status_connected;
1512         }
1513         return status;
1514 }
1515
1516 static int intel_dp_get_modes(struct drm_connector *connector)
1517 {
1518         struct intel_dp *intel_dp = intel_attached_dp(connector);
1519         struct drm_device *dev = intel_dp->base.base.dev;
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         int ret;
1522
1523         /* We should parse the EDID data and find out if it has an audio sink
1524          */
1525
1526         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1527         if (ret) {
1528                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1529                         struct drm_display_mode *newmode;
1530                         list_for_each_entry(newmode, &connector->probed_modes,
1531                                             head) {
1532                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1533                                         dev_priv->panel_fixed_mode =
1534                                                 drm_mode_duplicate(dev, newmode);
1535                                         break;
1536                                 }
1537                         }
1538                 }
1539
1540                 return ret;
1541         }
1542
1543         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1544         if (is_edp(intel_dp)) {
1545                 if (dev_priv->panel_fixed_mode != NULL) {
1546                         struct drm_display_mode *mode;
1547                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1548                         drm_mode_probed_add(connector, mode);
1549                         return 1;
1550                 }
1551         }
1552         return 0;
1553 }
1554
1555 static void
1556 intel_dp_destroy (struct drm_connector *connector)
1557 {
1558         drm_sysfs_connector_remove(connector);
1559         drm_connector_cleanup(connector);
1560         kfree(connector);
1561 }
1562
1563 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1564 {
1565         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1566
1567         i2c_del_adapter(&intel_dp->adapter);
1568         drm_encoder_cleanup(encoder);
1569         kfree(intel_dp);
1570 }
1571
1572 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1573         .dpms = intel_dp_dpms,
1574         .mode_fixup = intel_dp_mode_fixup,
1575         .prepare = intel_dp_prepare,
1576         .mode_set = intel_dp_mode_set,
1577         .commit = intel_dp_commit,
1578 };
1579
1580 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1581         .dpms = drm_helper_connector_dpms,
1582         .detect = intel_dp_detect,
1583         .fill_modes = drm_helper_probe_single_connector_modes,
1584         .destroy = intel_dp_destroy,
1585 };
1586
1587 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1588         .get_modes = intel_dp_get_modes,
1589         .mode_valid = intel_dp_mode_valid,
1590         .best_encoder = intel_best_encoder,
1591 };
1592
1593 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1594         .destroy = intel_dp_encoder_destroy,
1595 };
1596
1597 static void
1598 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1599 {
1600         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1601
1602         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1603                 intel_dp_check_link_status(intel_dp);
1604 }
1605
1606 /* Return which DP Port should be selected for Transcoder DP control */
1607 int
1608 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1609 {
1610         struct drm_device *dev = crtc->dev;
1611         struct drm_mode_config *mode_config = &dev->mode_config;
1612         struct drm_encoder *encoder;
1613
1614         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1615                 struct intel_dp *intel_dp;
1616
1617                 if (encoder->crtc != crtc)
1618                         continue;
1619
1620                 intel_dp = enc_to_intel_dp(encoder);
1621                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1622                         return intel_dp->output_reg;
1623         }
1624
1625         return -1;
1626 }
1627
1628 /* check the VBT to see whether the eDP is on DP-D port */
1629 bool intel_dpd_is_edp(struct drm_device *dev)
1630 {
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct child_device_config *p_child;
1633         int i;
1634
1635         if (!dev_priv->child_dev_num)
1636                 return false;
1637
1638         for (i = 0; i < dev_priv->child_dev_num; i++) {
1639                 p_child = dev_priv->child_dev + i;
1640
1641                 if (p_child->dvo_port == PORT_IDPD &&
1642                     p_child->device_type == DEVICE_TYPE_eDP)
1643                         return true;
1644         }
1645         return false;
1646 }
1647
1648 void
1649 intel_dp_init(struct drm_device *dev, int output_reg)
1650 {
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         struct drm_connector *connector;
1653         struct intel_dp *intel_dp;
1654         struct intel_encoder *intel_encoder;
1655         struct intel_connector *intel_connector;
1656         const char *name = NULL;
1657         int type;
1658
1659         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1660         if (!intel_dp)
1661                 return;
1662
1663         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1664         if (!intel_connector) {
1665                 kfree(intel_dp);
1666                 return;
1667         }
1668         intel_encoder = &intel_dp->base;
1669
1670         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1671                 if (intel_dpd_is_edp(dev))
1672                         intel_dp->is_pch_edp = true;
1673
1674         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1675                 type = DRM_MODE_CONNECTOR_eDP;
1676                 intel_encoder->type = INTEL_OUTPUT_EDP;
1677         } else {
1678                 type = DRM_MODE_CONNECTOR_DisplayPort;
1679                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1680         }
1681
1682         connector = &intel_connector->base;
1683         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1684         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1685
1686         connector->polled = DRM_CONNECTOR_POLL_HPD;
1687
1688         if (output_reg == DP_B || output_reg == PCH_DP_B)
1689                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1690         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1691                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1692         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1693                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1694
1695         if (is_edp(intel_dp))
1696                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1697
1698         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1699         connector->interlace_allowed = true;
1700         connector->doublescan_allowed = 0;
1701
1702         intel_dp->output_reg = output_reg;
1703         intel_dp->has_audio = false;
1704         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1705
1706         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1707                          DRM_MODE_ENCODER_TMDS);
1708         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1709
1710         intel_connector_attach_encoder(intel_connector, intel_encoder);
1711         drm_sysfs_connector_add(connector);
1712
1713         /* Set up the DDC bus. */
1714         switch (output_reg) {
1715                 case DP_A:
1716                         name = "DPDDC-A";
1717                         break;
1718                 case DP_B:
1719                 case PCH_DP_B:
1720                         dev_priv->hotplug_supported_mask |=
1721                                 HDMIB_HOTPLUG_INT_STATUS;
1722                         name = "DPDDC-B";
1723                         break;
1724                 case DP_C:
1725                 case PCH_DP_C:
1726                         dev_priv->hotplug_supported_mask |=
1727                                 HDMIC_HOTPLUG_INT_STATUS;
1728                         name = "DPDDC-C";
1729                         break;
1730                 case DP_D:
1731                 case PCH_DP_D:
1732                         dev_priv->hotplug_supported_mask |=
1733                                 HDMID_HOTPLUG_INT_STATUS;
1734                         name = "DPDDC-D";
1735                         break;
1736         }
1737
1738         intel_dp_i2c_init(intel_dp, intel_connector, name);
1739
1740         intel_encoder->hot_plug = intel_dp_hot_plug;
1741
1742         if (is_edp(intel_dp)) {
1743                 /* initialize panel mode from VBT if available for eDP */
1744                 if (dev_priv->lfp_lvds_vbt_mode) {
1745                         dev_priv->panel_fixed_mode =
1746                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1747                         if (dev_priv->panel_fixed_mode) {
1748                                 dev_priv->panel_fixed_mode->type |=
1749                                         DRM_MODE_TYPE_PREFERRED;
1750                         }
1751                 }
1752         }
1753
1754         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1755          * 0xd.  Failure to do so will result in spurious interrupts being
1756          * generated on the port when a cable is not attached.
1757          */
1758         if (IS_G4X(dev) && !IS_GM45(dev)) {
1759                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1760                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1761         }
1762 }