drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
  95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  96
  97 static int
  98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  99 {
 100         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 101         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 102
 103         switch (max_link_bw) {
 104         case DP_LINK_BW_1_62:
 105         case DP_LINK_BW_2_7:
 106                 break;
 107         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 108                 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
 109                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 110                         max_link_bw = DP_LINK_BW_5_4;
 111                 else
 112                         max_link_bw = DP_LINK_BW_2_7;
 113                 break;
 114         default:
 115                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 116                      max_link_bw);
 117                 max_link_bw = DP_LINK_BW_1_62;
 118                 break;
 119         }
 120         return max_link_bw;
 121 }
 122
 123 /*
 124  * The units on the numbers in the next two are... bizarre.  Examples will
 125  * make it clearer; this one parallels an example in the eDP spec.
 126  *
 127  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 128  *
 129  *     270000 * 1 * 8 / 10 == 216000
 130  *
 131  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 132  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 133  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 134  * 119000.  At 18bpp that's 2142000 kilobits per second.
 135  *
 136  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 137  * get the result in decakilobits instead of kilobits.
 138  */
 139
 140 static int
 141 intel_dp_link_required(int pixel_clock, int bpp)
 142 {
 143         return (pixel_clock * bpp + 9) / 10;
 144 }
 145
 146 static int
 147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 148 {
 149         return (max_link_clock * max_lanes * 8) / 10;
 150 }
 151
 152 static enum drm_mode_status
 153 intel_dp_mode_valid(struct drm_connector *connector,
 154                     struct drm_display_mode *mode)
 155 {
 156         struct intel_dp *intel_dp = intel_attached_dp(connector);
 157         struct intel_connector *intel_connector = to_intel_connector(connector);
 158         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 159         int target_clock = mode->clock;
 160         int max_rate, mode_rate, max_lanes, max_link_clock;
 161
 162         if (is_edp(intel_dp) && fixed_mode) {
 163                 if (mode->hdisplay > fixed_mode->hdisplay)
 164                         return MODE_PANEL;
 165
 166                 if (mode->vdisplay > fixed_mode->vdisplay)
 167                         return MODE_PANEL;
 168
 169                 target_clock = fixed_mode->clock;
 170         }
 171
 172         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 173         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 174
 175         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 176         mode_rate = intel_dp_link_required(target_clock, 18);
 177
 178         if (mode_rate > max_rate)
 179                 return MODE_CLOCK_HIGH;
 180
 181         if (mode->clock < 10000)
 182                 return MODE_CLOCK_LOW;
 183
 184         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 185                 return MODE_H_ILLEGAL;
 186
 187         return MODE_OK;
 188 }
 189
 190 static uint32_t
 191 pack_aux(uint8_t *src, int src_bytes)
 192 {
 193         int     i;
 194         uint32_t v = 0;
 195
 196         if (src_bytes > 4)
 197                 src_bytes = 4;
 198         for (i = 0; i < src_bytes; i++)
 199                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 200         return v;
 201 }
 202
 203 static void
 204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 205 {
 206         int i;
 207         if (dst_bytes > 4)
 208                 dst_bytes = 4;
 209         for (i = 0; i < dst_bytes; i++)
 210                 dst[i] = src >> ((3-i) * 8);
 211 }
 212
 213 /* hrawclock is 1/4 the FSB frequency */
 214 static int
 215 intel_hrawclk(struct drm_device *dev)
 216 {
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         uint32_t clkcfg;
 219
 220         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 221         if (IS_VALLEYVIEW(dev))
 222                 return 200;
 223
 224         clkcfg = I915_READ(CLKCFG);
 225         switch (clkcfg & CLKCFG_FSB_MASK) {
 226         case CLKCFG_FSB_400:
 227                 return 100;
 228         case CLKCFG_FSB_533:
 229                 return 133;
 230         case CLKCFG_FSB_667:
 231                 return 166;
 232         case CLKCFG_FSB_800:
 233                 return 200;
 234         case CLKCFG_FSB_1067:
 235                 return 266;
 236         case CLKCFG_FSB_1333:
 237                 return 333;
 238         /* these two are just a guess; one of them might be right */
 239         case CLKCFG_FSB_1600:
 240         case CLKCFG_FSB_1600_ALT:
 241                 return 400;
 242         default:
 243                 return 133;
 244         }
 245 }
 246
 247 static void
 248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 249                                     struct intel_dp *intel_dp,
 250                                     struct edp_power_seq *out);
 251 static void
 252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 253                                               struct intel_dp *intel_dp,
 254                                               struct edp_power_seq *out);
 255
 256 static enum pipe
 257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 261         struct drm_device *dev = intel_dig_port->base.base.dev;
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263         enum port port = intel_dig_port->port;
 264         enum pipe pipe;
 265
 266         /* modeset should have pipe */
 267         if (crtc)
 268                 return to_intel_crtc(crtc)->pipe;
 269
 270         /* init time, try to find a pipe with this port selected */
 271         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 272                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 273                         PANEL_PORT_SELECT_MASK;
 274                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 275                         return pipe;
 276                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 277                         return pipe;
 278         }
 279
 280         /* shrug */
 281         return PIPE_A;
 282 }
 283
 284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 285 {
 286         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 287
 288         if (HAS_PCH_SPLIT(dev))
 289                 return PCH_PP_CONTROL;
 290         else
 291                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 292 }
 293
 294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 295 {
 296         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 297
 298         if (HAS_PCH_SPLIT(dev))
 299                 return PCH_PP_STATUS;
 300         else
 301                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 302 }
 303
 304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 305 {
 306         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 307         struct drm_i915_private *dev_priv = dev->dev_private;
 308
 309         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 310 }
 311
 312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 313 {
 314         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         return !dev_priv->pm.suspended &&
 318                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 319 }
 320
 321 static void
 322 intel_dp_check_edp(struct intel_dp *intel_dp)
 323 {
 324         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         if (!is_edp(intel_dp))
 328                 return;
 329
 330         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 331                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 332                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 333                               I915_READ(_pp_stat_reg(intel_dp)),
 334                               I915_READ(_pp_ctrl_reg(intel_dp)));
 335         }
 336 }
 337
 338 static uint32_t
 339 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 340 {
 341         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 342         struct drm_device *dev = intel_dig_port->base.base.dev;
 343         struct drm_i915_private *dev_priv = dev->dev_private;
 344         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 345         uint32_t status;
 346         bool done;
 347
 348 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 349         if (has_aux_irq)
 350                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 351                                           msecs_to_jiffies_timeout(10));
 352         else
 353                 done = wait_for_atomic(C, 10) == 0;
 354         if (!done)
 355                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 356                           has_aux_irq);
 357 #undef C
 358
 359         return status;
 360 }
 361
 362 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 363 {
 364         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 365         struct drm_device *dev = intel_dig_port->base.base.dev;
 366
 367         /*
 368          * The clock divider is based off the hrawclk, and would like to run at
 369          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 370          */
 371         return index ? 0 : intel_hrawclk(dev) / 2;
 372 }
 373
 374 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 375 {
 376         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 377         struct drm_device *dev = intel_dig_port->base.base.dev;
 378
 379         if (index)
 380                 return 0;
 381
 382         if (intel_dig_port->port == PORT_A) {
 383                 if (IS_GEN6(dev) || IS_GEN7(dev))
 384                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 385                 else
 386                         return 225; /* eDP input clock at 450Mhz */
 387         } else {
 388                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 389         }
 390 }
 391
 392 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 393 {
 394         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 395         struct drm_device *dev = intel_dig_port->base.base.dev;
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397
 398         if (intel_dig_port->port == PORT_A) {
 399                 if (index)
 400                         return 0;
 401                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 402         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 403                 /* Workaround for non-ULT HSW */
 404                 switch (index) {
 405                 case 0: return 63;
 406                 case 1: return 72;
 407                 default: return 0;
 408                 }
 409         } else  {
 410                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 411         }
 412 }
 413
 414 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 415 {
 416         return index ? 0 : 100;
 417 }
 418
 419 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 420                                       bool has_aux_irq,
 421                                       int send_bytes,
 422                                       uint32_t aux_clock_divider)
 423 {
 424         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 425         struct drm_device *dev = intel_dig_port->base.base.dev;
 426         uint32_t precharge, timeout;
 427
 428         if (IS_GEN6(dev))
 429                 precharge = 3;
 430         else
 431                 precharge = 5;
 432
 433         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 434                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 435         else
 436                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 437
 438         return DP_AUX_CH_CTL_SEND_BUSY |
 439                DP_AUX_CH_CTL_DONE |
 440                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 441                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 442                timeout |
 443                DP_AUX_CH_CTL_RECEIVE_ERROR |
 444                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 445                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 446                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 447 }
 448
 449 static int
 450 intel_dp_aux_ch(struct intel_dp *intel_dp,
 451                 uint8_t *send, int send_bytes,
 452                 uint8_t *recv, int recv_size)
 453 {
 454         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 455         struct drm_device *dev = intel_dig_port->base.base.dev;
 456         struct drm_i915_private *dev_priv = dev->dev_private;
 457         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 458         uint32_t ch_data = ch_ctl + 4;
 459         uint32_t aux_clock_divider;
 460         int i, ret, recv_bytes;
 461         uint32_t status;
 462         int try, clock = 0;
 463         bool has_aux_irq = HAS_AUX_IRQ(dev);
 464         bool vdd;
 465
 466         vdd = _edp_panel_vdd_on(intel_dp);
 467
 468         /* dp aux is extremely sensitive to irq latency, hence request the
 469          * lowest possible wakeup latency and so prevent the cpu from going into
 470          * deep sleep states.
 471          */
 472         pm_qos_update_request(&dev_priv->pm_qos, 0);
 473
 474         intel_dp_check_edp(intel_dp);
 475
 476         intel_aux_display_runtime_get(dev_priv);
 477
 478         /* Try to wait for any previous AUX channel activity */
 479         for (try = 0; try < 3; try++) {
 480                 status = I915_READ_NOTRACE(ch_ctl);
 481                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 482                         break;
 483                 msleep(1);
 484         }
 485
 486         if (try == 3) {
 487                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 488                      I915_READ(ch_ctl));
 489                 ret = -EBUSY;
 490                 goto out;
 491         }
 492
 493         /* Only 5 data registers! */
 494         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 495                 ret = -E2BIG;
 496                 goto out;
 497         }
 498
 499         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 500                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 501                                                           has_aux_irq,
 502                                                           send_bytes,
 503                                                           aux_clock_divider);
 504
 505                 /* Must try at least 3 times according to DP spec */
 506                 for (try = 0; try < 5; try++) {
 507                         /* Load the send data into the aux channel data registers */
 508                         for (i = 0; i < send_bytes; i += 4)
 509                                 I915_WRITE(ch_data + i,
 510                                            pack_aux(send + i, send_bytes - i));
 511
 512                         /* Send the command and wait for it to complete */
 513                         I915_WRITE(ch_ctl, send_ctl);
 514
 515                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 516
 517                         /* Clear done status and any errors */
 518                         I915_WRITE(ch_ctl,
 519                                    status |
 520                                    DP_AUX_CH_CTL_DONE |
 521                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 522                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 523
 524                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 525                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 526                                 continue;
 527                         if (status & DP_AUX_CH_CTL_DONE)
 528                                 break;
 529                 }
 530                 if (status & DP_AUX_CH_CTL_DONE)
 531                         break;
 532         }
 533
 534         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 535                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 536                 ret = -EBUSY;
 537                 goto out;
 538         }
 539
 540         /* Check for timeout or receive error.
 541          * Timeouts occur when the sink is not connected
 542          */
 543         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 544                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 545                 ret = -EIO;
 546                 goto out;
 547         }
 548
 549         /* Timeouts occur when the device isn't connected, so they're
 550          * "normal" -- don't fill the kernel log with these */
 551         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 552                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 553                 ret = -ETIMEDOUT;
 554                 goto out;
 555         }
 556
 557         /* Unload any bytes sent back from the other side */
 558         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 559                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 560         if (recv_bytes > recv_size)
 561                 recv_bytes = recv_size;
 562
 563         for (i = 0; i < recv_bytes; i += 4)
 564                 unpack_aux(I915_READ(ch_data + i),
 565                            recv + i, recv_bytes - i);
 566
 567         ret = recv_bytes;
 568 out:
 569         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 570         intel_aux_display_runtime_put(dev_priv);
 571
 572         if (vdd)
 573                 edp_panel_vdd_off(intel_dp, false);
 574
 575         return ret;
 576 }
 577
 578 #define HEADER_SIZE     4
 579 static ssize_t
 580 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 581 {
 582         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 583         uint8_t txbuf[20], rxbuf[20];
 584         size_t txsize, rxsize;
 585         int ret;
 586
 587         txbuf[0] = msg->request << 4;
 588         txbuf[1] = msg->address >> 8;
 589         txbuf[2] = msg->address & 0xff;
 590         txbuf[3] = msg->size - 1;
 591
 592         switch (msg->request & ~DP_AUX_I2C_MOT) {
 593         case DP_AUX_NATIVE_WRITE:
 594         case DP_AUX_I2C_WRITE:
 595                 txsize = HEADER_SIZE + msg->size;
 596                 rxsize = 1;
 597
 598                 if (WARN_ON(txsize > 20))
 599                         return -E2BIG;
 600
 601                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 602
 603                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 604                 if (ret > 0) {
 605                         msg->reply = rxbuf[0] >> 4;
 606
 607                         /* Return payload size. */
 608                         ret = msg->size;
 609                 }
 610                 break;
 611
 612         case DP_AUX_NATIVE_READ:
 613         case DP_AUX_I2C_READ:
 614                 txsize = HEADER_SIZE;
 615                 rxsize = msg->size + 1;
 616
 617                 if (WARN_ON(rxsize > 20))
 618                         return -E2BIG;
 619
 620                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 621                 if (ret > 0) {
 622                         msg->reply = rxbuf[0] >> 4;
 623                         /*
 624                          * Assume happy day, and copy the data. The caller is
 625                          * expected to check msg->reply before touching it.
 626                          *
 627                          * Return payload size.
 628                          */
 629                         ret--;
 630                         memcpy(msg->buffer, rxbuf + 1, ret);
 631                 }
 632                 break;
 633
 634         default:
 635                 ret = -EINVAL;
 636                 break;
 637         }
 638
 639         return ret;
 640 }
 641
 642 static void
 643 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 644 {
 645         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 646         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 647         enum port port = intel_dig_port->port;
 648         const char *name = NULL;
 649         int ret;
 650
 651         switch (port) {
 652         case PORT_A:
 653                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 654                 name = "DPDDC-A";
 655                 break;
 656         case PORT_B:
 657                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 658                 name = "DPDDC-B";
 659                 break;
 660         case PORT_C:
 661                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 662                 name = "DPDDC-C";
 663                 break;
 664         case PORT_D:
 665                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 666                 name = "DPDDC-D";
 667                 break;
 668         default:
 669                 BUG();
 670         }
 671
 672         if (!HAS_DDI(dev))
 673                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 674
 675         intel_dp->aux.name = name;
 676         intel_dp->aux.dev = dev->dev;
 677         intel_dp->aux.transfer = intel_dp_aux_transfer;
 678
 679         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 680                       connector->base.kdev->kobj.name);
 681
 682         ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
 683         if (ret < 0) {
 684                 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
 685                           name, ret);
 686                 return;
 687         }
 688
 689         ret = sysfs_create_link(&connector->base.kdev->kobj,
 690                                 &intel_dp->aux.ddc.dev.kobj,
 691                                 intel_dp->aux.ddc.dev.kobj.name);
 692         if (ret < 0) {
 693                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 694                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
 695         }
 696 }
 697
 698 static void
 699 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 700 {
 701         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 702
 703         sysfs_remove_link(&intel_connector->base.kdev->kobj,
 704                           intel_dp->aux.ddc.dev.kobj.name);
 705         intel_connector_unregister(intel_connector);
 706 }
 707
 708 static void
 709 intel_dp_set_clock(struct intel_encoder *encoder,
 710                    struct intel_crtc_config *pipe_config, int link_bw)
 711 {
 712         struct drm_device *dev = encoder->base.dev;
 713         const struct dp_link_dpll *divisor = NULL;
 714         int i, count = 0;
 715
 716         if (IS_G4X(dev)) {
 717                 divisor = gen4_dpll;
 718                 count = ARRAY_SIZE(gen4_dpll);
 719         } else if (IS_HASWELL(dev)) {
 720                 /* Haswell has special-purpose DP DDI clocks. */
 721         } else if (HAS_PCH_SPLIT(dev)) {
 722                 divisor = pch_dpll;
 723                 count = ARRAY_SIZE(pch_dpll);
 724         } else if (IS_VALLEYVIEW(dev)) {
 725                 divisor = vlv_dpll;
 726                 count = ARRAY_SIZE(vlv_dpll);
 727         }
 728
 729         if (divisor && count) {
 730                 for (i = 0; i < count; i++) {
 731                         if (link_bw == divisor[i].link_bw) {
 732                                 pipe_config->dpll = divisor[i].dpll;
 733                                 pipe_config->clock_set = true;
 734                                 break;
 735                         }
 736                 }
 737         }
 738 }
 739
 740 bool
 741 intel_dp_compute_config(struct intel_encoder *encoder,
 742                         struct intel_crtc_config *pipe_config)
 743 {
 744         struct drm_device *dev = encoder->base.dev;
 745         struct drm_i915_private *dev_priv = dev->dev_private;
 746         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 747         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 748         enum port port = dp_to_dig_port(intel_dp)->port;
 749         struct intel_crtc *intel_crtc = encoder->new_crtc;
 750         struct intel_connector *intel_connector = intel_dp->attached_connector;
 751         int lane_count, clock;
 752         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 753         /* Conveniently, the link BW constants become indices with a shift...*/
 754         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 755         int bpp, mode_rate;
 756         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 757         int link_avail, link_clock;
 758
 759         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 760                 pipe_config->has_pch_encoder = true;
 761
 762         pipe_config->has_dp_encoder = true;
 763
 764         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 765                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 766                                        adjusted_mode);
 767                 if (!HAS_PCH_SPLIT(dev))
 768                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 769                                                  intel_connector->panel.fitting_mode);
 770                 else
 771                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 772                                                 intel_connector->panel.fitting_mode);
 773         }
 774
 775         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 776                 return false;
 777
 778         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 779                       "max bw %02x pixel clock %iKHz\n",
 780                       max_lane_count, bws[max_clock],
 781                       adjusted_mode->crtc_clock);
 782
 783         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 784          * bpc in between. */
 785         bpp = pipe_config->pipe_bpp;
 786         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 787             dev_priv->vbt.edp_bpp < bpp) {
 788                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 789                               dev_priv->vbt.edp_bpp);
 790                 bpp = dev_priv->vbt.edp_bpp;
 791         }
 792
 793         for (; bpp >= 6*3; bpp -= 2*3) {
 794                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 795                                                    bpp);
 796
 797                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 798                         for (clock = 0; clock <= max_clock; clock++) {
 799                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 800                                 link_avail = intel_dp_max_data_rate(link_clock,
 801                                                                     lane_count);
 802
 803                                 if (mode_rate <= link_avail) {
 804                                         goto found;
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return false;
 811
 812 found:
 813         if (intel_dp->color_range_auto) {
 814                 /*
 815                  * See:
 816                  * CEA-861-E - 5.1 Default Encoding Parameters
 817                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 818                  */
 819                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 820                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 821                 else
 822                         intel_dp->color_range = 0;
 823         }
 824
 825         if (intel_dp->color_range)
 826                 pipe_config->limited_color_range = true;
 827
 828         intel_dp->link_bw = bws[clock];
 829         intel_dp->lane_count = lane_count;
 830         pipe_config->pipe_bpp = bpp;
 831         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 832
 833         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 834                       intel_dp->link_bw, intel_dp->lane_count,
 835                       pipe_config->port_clock, bpp);
 836         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 837                       mode_rate, link_avail);
 838
 839         intel_link_compute_m_n(bpp, lane_count,
 840                                adjusted_mode->crtc_clock,
 841                                pipe_config->port_clock,
 842                                &pipe_config->dp_m_n);
 843
 844         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 845
 846         return true;
 847 }
 848
 849 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 850 {
 851         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 852         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 853         struct drm_device *dev = crtc->base.dev;
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         u32 dpa_ctl;
 856
 857         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 858         dpa_ctl = I915_READ(DP_A);
 859         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 860
 861         if (crtc->config.port_clock == 162000) {
 862                 /* For a long time we've carried around a ILK-DevA w/a for the
 863                  * 160MHz clock. If we're really unlucky, it's still required.
 864                  */
 865                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 866                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 867                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 868         } else {
 869                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 870                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 871         }
 872
 873         I915_WRITE(DP_A, dpa_ctl);
 874
 875         POSTING_READ(DP_A);
 876         udelay(500);
 877 }
 878
 879 static void intel_dp_mode_set(struct intel_encoder *encoder)
 880 {
 881         struct drm_device *dev = encoder->base.dev;
 882         struct drm_i915_private *dev_priv = dev->dev_private;
 883         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 884         enum port port = dp_to_dig_port(intel_dp)->port;
 885         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 886         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 887
 888         /*
 889          * There are four kinds of DP registers:
 890          *
 891          *      IBX PCH
 892          *      SNB CPU
 893          *      IVB CPU
 894          *      CPT PCH
 895          *
 896          * IBX PCH and CPU are the same for almost everything,
 897          * except that the CPU DP PLL is configured in this
 898          * register
 899          *
 900          * CPT PCH is quite different, having many bits moved
 901          * to the TRANS_DP_CTL register instead. That
 902          * configuration happens (oddly) in ironlake_pch_enable
 903          */
 904
 905         /* Preserve the BIOS-computed detected bit. This is
 906          * supposed to be read-only.
 907          */
 908         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 909
 910         /* Handle DP bits in common between all three register formats */
 911         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 912         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 913
 914         if (intel_dp->has_audio) {
 915                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 916                                  pipe_name(crtc->pipe));
 917                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 918                 intel_write_eld(&encoder->base, adjusted_mode);
 919         }
 920
 921         /* Split out the IBX/CPU vs CPT settings */
 922
 923         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 924                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 925                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 926                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 927                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 928                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 929
 930                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 931                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 932
 933                 intel_dp->DP |= crtc->pipe << 29;
 934         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 935                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 936                         intel_dp->DP |= intel_dp->color_range;
 937
 938                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 939                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 940                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 941                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 942                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 943
 944                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 945                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 946
 947                 if (crtc->pipe == 1)
 948                         intel_dp->DP |= DP_PIPEB_SELECT;
 949         } else {
 950                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 951         }
 952
 953         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 954                 ironlake_set_pll_cpu_edp(intel_dp);
 955 }
 956
 957 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 958 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 959
 960 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
 961 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
 962
 963 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 964 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 965
 966 static void wait_panel_status(struct intel_dp *intel_dp,
 967                                        u32 mask,
 968                                        u32 value)
 969 {
 970         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 971         struct drm_i915_private *dev_priv = dev->dev_private;
 972         u32 pp_stat_reg, pp_ctrl_reg;
 973
 974         pp_stat_reg = _pp_stat_reg(intel_dp);
 975         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 976
 977         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 978                         mask, value,
 979                         I915_READ(pp_stat_reg),
 980                         I915_READ(pp_ctrl_reg));
 981
 982         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 983                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 984                                 I915_READ(pp_stat_reg),
 985                                 I915_READ(pp_ctrl_reg));
 986         }
 987
 988         DRM_DEBUG_KMS("Wait complete\n");
 989 }
 990
 991 static void wait_panel_on(struct intel_dp *intel_dp)
 992 {
 993         DRM_DEBUG_KMS("Wait for panel power on\n");
 994         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 995 }
 996
 997 static void wait_panel_off(struct intel_dp *intel_dp)
 998 {
 999         DRM_DEBUG_KMS("Wait for panel power off time\n");
1000         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1001 }
1002
1003 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1004 {
1005         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1006
1007         /* When we disable the VDD override bit last we have to do the manual
1008          * wait. */
1009         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1010                                        intel_dp->panel_power_cycle_delay);
1011
1012         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1013 }
1014
1015 static void wait_backlight_on(struct intel_dp *intel_dp)
1016 {
1017         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1018                                        intel_dp->backlight_on_delay);
1019 }
1020
1021 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1022 {
1023         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1024                                        intel_dp->backlight_off_delay);
1025 }
1026
1027 /* Read the current pp_control value, unlocking the register if it
1028  * is locked
1029  */
1030
1031 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1032 {
1033         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         u32 control;
1036
1037         control = I915_READ(_pp_ctrl_reg(intel_dp));
1038         control &= ~PANEL_UNLOCK_MASK;
1039         control |= PANEL_UNLOCK_REGS;
1040         return control;
1041 }
1042
1043 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1044 {
1045         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         u32 pp;
1048         u32 pp_stat_reg, pp_ctrl_reg;
1049         bool need_to_disable = !intel_dp->want_panel_vdd;
1050
1051         if (!is_edp(intel_dp))
1052                 return false;
1053
1054         intel_dp->want_panel_vdd = true;
1055
1056         if (edp_have_panel_vdd(intel_dp))
1057                 return need_to_disable;
1058
1059         intel_runtime_pm_get(dev_priv);
1060
1061         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1062
1063         if (!edp_have_panel_power(intel_dp))
1064                 wait_panel_power_cycle(intel_dp);
1065
1066         pp = ironlake_get_pp_control(intel_dp);
1067         pp |= EDP_FORCE_VDD;
1068
1069         pp_stat_reg = _pp_stat_reg(intel_dp);
1070         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1071
1072         I915_WRITE(pp_ctrl_reg, pp);
1073         POSTING_READ(pp_ctrl_reg);
1074         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1075                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1076         /*
1077          * If the panel wasn't on, delay before accessing aux channel
1078          */
1079         if (!edp_have_panel_power(intel_dp)) {
1080                 DRM_DEBUG_KMS("eDP was not running\n");
1081                 msleep(intel_dp->panel_power_up_delay);
1082         }
1083
1084         return need_to_disable;
1085 }
1086
1087 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1088 {
1089         if (is_edp(intel_dp)) {
1090                 bool vdd = _edp_panel_vdd_on(intel_dp);
1091
1092                 WARN(!vdd, "eDP VDD already requested on\n");
1093         }
1094 }
1095
1096 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1097 {
1098         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         u32 pp;
1101         u32 pp_stat_reg, pp_ctrl_reg;
1102
1103         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1104
1105         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1106                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1107
1108                 pp = ironlake_get_pp_control(intel_dp);
1109                 pp &= ~EDP_FORCE_VDD;
1110
1111                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1112                 pp_stat_reg = _pp_stat_reg(intel_dp);
1113
1114                 I915_WRITE(pp_ctrl_reg, pp);
1115                 POSTING_READ(pp_ctrl_reg);
1116
1117                 /* Make sure sequencer is idle before allowing subsequent activity */
1118                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1119                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1120
1121                 if ((pp & POWER_TARGET_ON) == 0)
1122                         intel_dp->last_power_cycle = jiffies;
1123
1124                 intel_runtime_pm_put(dev_priv);
1125         }
1126 }
1127
1128 static void edp_panel_vdd_work(struct work_struct *__work)
1129 {
1130         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1131                                                  struct intel_dp, panel_vdd_work);
1132         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1133
1134         mutex_lock(&dev->mode_config.mutex);
1135         edp_panel_vdd_off_sync(intel_dp);
1136         mutex_unlock(&dev->mode_config.mutex);
1137 }
1138
1139 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1140 {
1141         if (!is_edp(intel_dp))
1142                 return;
1143
1144         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1145
1146         intel_dp->want_panel_vdd = false;
1147
1148         if (sync) {
1149                 edp_panel_vdd_off_sync(intel_dp);
1150         } else {
1151                 /*
1152                  * Queue the timer to fire a long
1153                  * time from now (relative to the power down delay)
1154                  * to keep the panel power up across a sequence of operations
1155                  */
1156                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1157                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1158         }
1159 }
1160
1161 void intel_edp_panel_on(struct intel_dp *intel_dp)
1162 {
1163         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1164         struct drm_i915_private *dev_priv = dev->dev_private;
1165         u32 pp;
1166         u32 pp_ctrl_reg;
1167
1168         if (!is_edp(intel_dp))
1169                 return;
1170
1171         DRM_DEBUG_KMS("Turn eDP power on\n");
1172
1173         if (edp_have_panel_power(intel_dp)) {
1174                 DRM_DEBUG_KMS("eDP power already on\n");
1175                 return;
1176         }
1177
1178         wait_panel_power_cycle(intel_dp);
1179
1180         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1181         pp = ironlake_get_pp_control(intel_dp);
1182         if (IS_GEN5(dev)) {
1183                 /* ILK workaround: disable reset around power sequence */
1184                 pp &= ~PANEL_POWER_RESET;
1185                 I915_WRITE(pp_ctrl_reg, pp);
1186                 POSTING_READ(pp_ctrl_reg);
1187         }
1188
1189         pp |= POWER_TARGET_ON;
1190         if (!IS_GEN5(dev))
1191                 pp |= PANEL_POWER_RESET;
1192
1193         I915_WRITE(pp_ctrl_reg, pp);
1194         POSTING_READ(pp_ctrl_reg);
1195
1196         wait_panel_on(intel_dp);
1197         intel_dp->last_power_on = jiffies;
1198
1199         if (IS_GEN5(dev)) {
1200                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1201                 I915_WRITE(pp_ctrl_reg, pp);
1202                 POSTING_READ(pp_ctrl_reg);
1203         }
1204 }
1205
1206 void intel_edp_panel_off(struct intel_dp *intel_dp)
1207 {
1208         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210         u32 pp;
1211         u32 pp_ctrl_reg;
1212
1213         if (!is_edp(intel_dp))
1214                 return;
1215
1216         DRM_DEBUG_KMS("Turn eDP power off\n");
1217
1218         edp_wait_backlight_off(intel_dp);
1219
1220         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1221
1222         pp = ironlake_get_pp_control(intel_dp);
1223         /* We need to switch off panel power _and_ force vdd, for otherwise some
1224          * panels get very unhappy and cease to work. */
1225         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1226                 EDP_BLC_ENABLE);
1227
1228         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1229
1230         intel_dp->want_panel_vdd = false;
1231
1232         I915_WRITE(pp_ctrl_reg, pp);
1233         POSTING_READ(pp_ctrl_reg);
1234
1235         intel_dp->last_power_cycle = jiffies;
1236         wait_panel_off(intel_dp);
1237
1238         /* We got a reference when we enabled the VDD. */
1239         intel_runtime_pm_put(dev_priv);
1240 }
1241
1242 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1243 {
1244         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1245         struct drm_device *dev = intel_dig_port->base.base.dev;
1246         struct drm_i915_private *dev_priv = dev->dev_private;
1247         u32 pp;
1248         u32 pp_ctrl_reg;
1249
1250         if (!is_edp(intel_dp))
1251                 return;
1252
1253         DRM_DEBUG_KMS("\n");
1254         /*
1255          * If we enable the backlight right away following a panel power
1256          * on, we may see slight flicker as the panel syncs with the eDP
1257          * link.  So delay a bit to make sure the image is solid before
1258          * allowing it to appear.
1259          */
1260         wait_backlight_on(intel_dp);
1261         pp = ironlake_get_pp_control(intel_dp);
1262         pp |= EDP_BLC_ENABLE;
1263
1264         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1265
1266         I915_WRITE(pp_ctrl_reg, pp);
1267         POSTING_READ(pp_ctrl_reg);
1268
1269         intel_panel_enable_backlight(intel_dp->attached_connector);
1270 }
1271
1272 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1273 {
1274         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1275         struct drm_i915_private *dev_priv = dev->dev_private;
1276         u32 pp;
1277         u32 pp_ctrl_reg;
1278
1279         if (!is_edp(intel_dp))
1280                 return;
1281
1282         intel_panel_disable_backlight(intel_dp->attached_connector);
1283
1284         DRM_DEBUG_KMS("\n");
1285         pp = ironlake_get_pp_control(intel_dp);
1286         pp &= ~EDP_BLC_ENABLE;
1287
1288         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1289
1290         I915_WRITE(pp_ctrl_reg, pp);
1291         POSTING_READ(pp_ctrl_reg);
1292         intel_dp->last_backlight_off = jiffies;
1293 }
1294
1295 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1296 {
1297         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1298         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1299         struct drm_device *dev = crtc->dev;
1300         struct drm_i915_private *dev_priv = dev->dev_private;
1301         u32 dpa_ctl;
1302
1303         assert_pipe_disabled(dev_priv,
1304                              to_intel_crtc(crtc)->pipe);
1305
1306         DRM_DEBUG_KMS("\n");
1307         dpa_ctl = I915_READ(DP_A);
1308         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1309         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1310
1311         /* We don't adjust intel_dp->DP while tearing down the link, to
1312          * facilitate link retraining (e.g. after hotplug). Hence clear all
1313          * enable bits here to ensure that we don't enable too much. */
1314         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1315         intel_dp->DP |= DP_PLL_ENABLE;
1316         I915_WRITE(DP_A, intel_dp->DP);
1317         POSTING_READ(DP_A);
1318         udelay(200);
1319 }
1320
1321 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1322 {
1323         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1324         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1325         struct drm_device *dev = crtc->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         u32 dpa_ctl;
1328
1329         assert_pipe_disabled(dev_priv,
1330                              to_intel_crtc(crtc)->pipe);
1331
1332         dpa_ctl = I915_READ(DP_A);
1333         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1334              "dp pll off, should be on\n");
1335         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1336
1337         /* We can't rely on the value tracked for the DP register in
1338          * intel_dp->DP because link_down must not change that (otherwise link
1339          * re-training will fail. */
1340         dpa_ctl &= ~DP_PLL_ENABLE;
1341         I915_WRITE(DP_A, dpa_ctl);
1342         POSTING_READ(DP_A);
1343         udelay(200);
1344 }
1345
1346 /* If the sink supports it, try to set the power state appropriately */
1347 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1348 {
1349         int ret, i;
1350
1351         /* Should have a valid DPCD by this point */
1352         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1353                 return;
1354
1355         if (mode != DRM_MODE_DPMS_ON) {
1356                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1357                                          DP_SET_POWER_D3);
1358                 if (ret != 1)
1359                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1360         } else {
1361                 /*
1362                  * When turning on, we need to retry for 1ms to give the sink
1363                  * time to wake up.
1364                  */
1365                 for (i = 0; i < 3; i++) {
1366                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1367                                                  DP_SET_POWER_D0);
1368                         if (ret == 1)
1369                                 break;
1370                         msleep(1);
1371                 }
1372         }
1373 }
1374
1375 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1376                                   enum pipe *pipe)
1377 {
1378         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379         enum port port = dp_to_dig_port(intel_dp)->port;
1380         struct drm_device *dev = encoder->base.dev;
1381         struct drm_i915_private *dev_priv = dev->dev_private;
1382         enum intel_display_power_domain power_domain;
1383         u32 tmp;
1384
1385         power_domain = intel_display_port_power_domain(encoder);
1386         if (!intel_display_power_enabled(dev_priv, power_domain))
1387                 return false;
1388
1389         tmp = I915_READ(intel_dp->output_reg);
1390
1391         if (!(tmp & DP_PORT_EN))
1392                 return false;
1393
1394         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1395                 *pipe = PORT_TO_PIPE_CPT(tmp);
1396         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1397                 *pipe = PORT_TO_PIPE(tmp);
1398         } else {
1399                 u32 trans_sel;
1400                 u32 trans_dp;
1401                 int i;
1402
1403                 switch (intel_dp->output_reg) {
1404                 case PCH_DP_B:
1405                         trans_sel = TRANS_DP_PORT_SEL_B;
1406                         break;
1407                 case PCH_DP_C:
1408                         trans_sel = TRANS_DP_PORT_SEL_C;
1409                         break;
1410                 case PCH_DP_D:
1411                         trans_sel = TRANS_DP_PORT_SEL_D;
1412                         break;
1413                 default:
1414                         return true;
1415                 }
1416
1417                 for_each_pipe(i) {
1418                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1419                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1420                                 *pipe = i;
1421                                 return true;
1422                         }
1423                 }
1424
1425                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1426                               intel_dp->output_reg);
1427         }
1428
1429         return true;
1430 }
1431
1432 static void intel_dp_get_config(struct intel_encoder *encoder,
1433                                 struct intel_crtc_config *pipe_config)
1434 {
1435         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1436         u32 tmp, flags = 0;
1437         struct drm_device *dev = encoder->base.dev;
1438         struct drm_i915_private *dev_priv = dev->dev_private;
1439         enum port port = dp_to_dig_port(intel_dp)->port;
1440         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1441         int dotclock;
1442
1443         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1444                 tmp = I915_READ(intel_dp->output_reg);
1445                 if (tmp & DP_SYNC_HS_HIGH)
1446                         flags |= DRM_MODE_FLAG_PHSYNC;
1447                 else
1448                         flags |= DRM_MODE_FLAG_NHSYNC;
1449
1450                 if (tmp & DP_SYNC_VS_HIGH)
1451                         flags |= DRM_MODE_FLAG_PVSYNC;
1452                 else
1453                         flags |= DRM_MODE_FLAG_NVSYNC;
1454         } else {
1455                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1456                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1457                         flags |= DRM_MODE_FLAG_PHSYNC;
1458                 else
1459                         flags |= DRM_MODE_FLAG_NHSYNC;
1460
1461                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1462                         flags |= DRM_MODE_FLAG_PVSYNC;
1463                 else
1464                         flags |= DRM_MODE_FLAG_NVSYNC;
1465         }
1466
1467         pipe_config->adjusted_mode.flags |= flags;
1468
1469         pipe_config->has_dp_encoder = true;
1470
1471         intel_dp_get_m_n(crtc, pipe_config);
1472
1473         if (port == PORT_A) {
1474                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1475                         pipe_config->port_clock = 162000;
1476                 else
1477                         pipe_config->port_clock = 270000;
1478         }
1479
1480         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1481                                             &pipe_config->dp_m_n);
1482
1483         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1484                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1485
1486         pipe_config->adjusted_mode.crtc_clock = dotclock;
1487
1488         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1489             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1490                 /*
1491                  * This is a big fat ugly hack.
1492                  *
1493                  * Some machines in UEFI boot mode provide us a VBT that has 18
1494                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1495                  * unknown we fail to light up. Yet the same BIOS boots up with
1496                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1497                  * max, not what it tells us to use.
1498                  *
1499                  * Note: This will still be broken if the eDP panel is not lit
1500                  * up by the BIOS, and thus we can't get the mode at module
1501                  * load.
1502                  */
1503                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1504                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1505                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1506         }
1507 }
1508
1509 static bool is_edp_psr(struct drm_device *dev)
1510 {
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513         return dev_priv->psr.sink_support;
1514 }
1515
1516 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520         if (!HAS_PSR(dev))
1521                 return false;
1522
1523         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1524 }
1525
1526 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1527                                     struct edp_vsc_psr *vsc_psr)
1528 {
1529         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1530         struct drm_device *dev = dig_port->base.base.dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1533         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1534         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1535         uint32_t *data = (uint32_t *) vsc_psr;
1536         unsigned int i;
1537
1538         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1539            the video DIP being updated before program video DIP data buffer
1540            registers for DIP being updated. */
1541         I915_WRITE(ctl_reg, 0);
1542         POSTING_READ(ctl_reg);
1543
1544         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1545                 if (i < sizeof(struct edp_vsc_psr))
1546                         I915_WRITE(data_reg + i, *data++);
1547                 else
1548                         I915_WRITE(data_reg + i, 0);
1549         }
1550
1551         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1552         POSTING_READ(ctl_reg);
1553 }
1554
1555 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1556 {
1557         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         struct edp_vsc_psr psr_vsc;
1560
1561         if (intel_dp->psr_setup_done)
1562                 return;
1563
1564         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1565         memset(&psr_vsc, 0, sizeof(psr_vsc));
1566         psr_vsc.sdp_header.HB0 = 0;
1567         psr_vsc.sdp_header.HB1 = 0x7;
1568         psr_vsc.sdp_header.HB2 = 0x2;
1569         psr_vsc.sdp_header.HB3 = 0x8;
1570         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1571
1572         /* Avoid continuous PSR exit by masking memup and hpd */
1573         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1574                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1575
1576         intel_dp->psr_setup_done = true;
1577 }
1578
1579 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1580 {
1581         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         uint32_t aux_clock_divider;
1584         int precharge = 0x3;
1585         int msg_size = 5;       /* Header(4) + Message(1) */
1586
1587         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1588
1589         /* Enable PSR in sink */
1590         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1591                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1592                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1593         else
1594                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1595                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1596
1597         /* Setup AUX registers */
1598         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1599         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1600         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1601                    DP_AUX_CH_CTL_TIME_OUT_400us |
1602                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1603                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1604                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1605 }
1606
1607 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1608 {
1609         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         uint32_t max_sleep_time = 0x1f;
1612         uint32_t idle_frames = 1;
1613         uint32_t val = 0x0;
1614         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1615
1616         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1617                 val |= EDP_PSR_LINK_STANDBY;
1618                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1619                 val |= EDP_PSR_TP1_TIME_0us;
1620                 val |= EDP_PSR_SKIP_AUX_EXIT;
1621         } else
1622                 val |= EDP_PSR_LINK_DISABLE;
1623
1624         I915_WRITE(EDP_PSR_CTL(dev), val |
1625                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1626                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1627                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1628                    EDP_PSR_ENABLE);
1629 }
1630
1631 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1632 {
1633         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1634         struct drm_device *dev = dig_port->base.base.dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         struct drm_crtc *crtc = dig_port->base.base.crtc;
1637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1638         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1639         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1640
1641         dev_priv->psr.source_ok = false;
1642
1643         if (!HAS_PSR(dev)) {
1644                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1645                 return false;
1646         }
1647
1648         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1649             (dig_port->port != PORT_A)) {
1650                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1651                 return false;
1652         }
1653
1654         if (!i915.enable_psr) {
1655                 DRM_DEBUG_KMS("PSR disable by flag\n");
1656                 return false;
1657         }
1658
1659         crtc = dig_port->base.base.crtc;
1660         if (crtc == NULL) {
1661                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1662                 return false;
1663         }
1664
1665         intel_crtc = to_intel_crtc(crtc);
1666         if (!intel_crtc_active(crtc)) {
1667                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1668                 return false;
1669         }
1670
1671         obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1672         if (obj->tiling_mode != I915_TILING_X ||
1673             obj->fence_reg == I915_FENCE_REG_NONE) {
1674                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1675                 return false;
1676         }
1677
1678         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1679                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1680                 return false;
1681         }
1682
1683         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1684             S3D_ENABLE) {
1685                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1686                 return false;
1687         }
1688
1689         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1690                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1691                 return false;
1692         }
1693
1694         dev_priv->psr.source_ok = true;
1695         return true;
1696 }
1697
1698 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1699 {
1700         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1701
1702         if (!intel_edp_psr_match_conditions(intel_dp) ||
1703             intel_edp_is_psr_enabled(dev))
1704                 return;
1705
1706         /* Setup PSR once */
1707         intel_edp_psr_setup(intel_dp);
1708
1709         /* Enable PSR on the panel */
1710         intel_edp_psr_enable_sink(intel_dp);
1711
1712         /* Enable PSR on the host */
1713         intel_edp_psr_enable_source(intel_dp);
1714 }
1715
1716 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1717 {
1718         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1719
1720         if (intel_edp_psr_match_conditions(intel_dp) &&
1721             !intel_edp_is_psr_enabled(dev))
1722                 intel_edp_psr_do_enable(intel_dp);
1723 }
1724
1725 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1726 {
1727         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1728         struct drm_i915_private *dev_priv = dev->dev_private;
1729
1730         if (!intel_edp_is_psr_enabled(dev))
1731                 return;
1732
1733         I915_WRITE(EDP_PSR_CTL(dev),
1734                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1735
1736         /* Wait till PSR is idle */
1737         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1738                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1739                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1740 }
1741
1742 void intel_edp_psr_update(struct drm_device *dev)
1743 {
1744         struct intel_encoder *encoder;
1745         struct intel_dp *intel_dp = NULL;
1746
1747         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1748                 if (encoder->type == INTEL_OUTPUT_EDP) {
1749                         intel_dp = enc_to_intel_dp(&encoder->base);
1750
1751                         if (!is_edp_psr(dev))
1752                                 return;
1753
1754                         if (!intel_edp_psr_match_conditions(intel_dp))
1755                                 intel_edp_psr_disable(intel_dp);
1756                         else
1757                                 if (!intel_edp_is_psr_enabled(dev))
1758                                         intel_edp_psr_do_enable(intel_dp);
1759                 }
1760 }
1761
1762 static void intel_disable_dp(struct intel_encoder *encoder)
1763 {
1764         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1765         enum port port = dp_to_dig_port(intel_dp)->port;
1766         struct drm_device *dev = encoder->base.dev;
1767
1768         /* Make sure the panel is off before trying to change the mode. But also
1769          * ensure that we have vdd while we switch off the panel. */
1770         intel_edp_panel_vdd_on(intel_dp);
1771         intel_edp_backlight_off(intel_dp);
1772         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1773         intel_edp_panel_off(intel_dp);
1774
1775         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1776         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1777                 intel_dp_link_down(intel_dp);
1778 }
1779
1780 static void intel_post_disable_dp(struct intel_encoder *encoder)
1781 {
1782         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1783         enum port port = dp_to_dig_port(intel_dp)->port;
1784         struct drm_device *dev = encoder->base.dev;
1785
1786         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1787                 intel_dp_link_down(intel_dp);
1788                 if (!IS_VALLEYVIEW(dev))
1789                         ironlake_edp_pll_off(intel_dp);
1790         }
1791 }
1792
1793 static void intel_enable_dp(struct intel_encoder *encoder)
1794 {
1795         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1796         struct drm_device *dev = encoder->base.dev;
1797         struct drm_i915_private *dev_priv = dev->dev_private;
1798         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1799
1800         if (WARN_ON(dp_reg & DP_PORT_EN))
1801                 return;
1802
1803         intel_edp_panel_vdd_on(intel_dp);
1804         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1805         intel_dp_start_link_train(intel_dp);
1806         intel_edp_panel_on(intel_dp);
1807         edp_panel_vdd_off(intel_dp, true);
1808         intel_dp_complete_link_train(intel_dp);
1809         intel_dp_stop_link_train(intel_dp);
1810 }
1811
1812 static void g4x_enable_dp(struct intel_encoder *encoder)
1813 {
1814         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815
1816         intel_enable_dp(encoder);
1817         intel_edp_backlight_on(intel_dp);
1818 }
1819
1820 static void vlv_enable_dp(struct intel_encoder *encoder)
1821 {
1822         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1823
1824         intel_edp_backlight_on(intel_dp);
1825 }
1826
1827 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1828 {
1829         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1830         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1831
1832         if (dport->port == PORT_A)
1833                 ironlake_edp_pll_on(intel_dp);
1834 }
1835
1836 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1837 {
1838         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1839         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1840         struct drm_device *dev = encoder->base.dev;
1841         struct drm_i915_private *dev_priv = dev->dev_private;
1842         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1843         enum dpio_channel port = vlv_dport_to_channel(dport);
1844         int pipe = intel_crtc->pipe;
1845         struct edp_power_seq power_seq;
1846         u32 val;
1847
1848         mutex_lock(&dev_priv->dpio_lock);
1849
1850         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1851         val = 0;
1852         if (pipe)
1853                 val |= (1<<21);
1854         else
1855                 val &= ~(1<<21);
1856         val |= 0x001000c4;
1857         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1858         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1859         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1860
1861         mutex_unlock(&dev_priv->dpio_lock);
1862
1863         if (is_edp(intel_dp)) {
1864                 /* init power sequencer on this pipe and port */
1865                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1866                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1867                                                               &power_seq);
1868         }
1869
1870         intel_enable_dp(encoder);
1871
1872         vlv_wait_port_ready(dev_priv, dport);
1873 }
1874
1875 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1876 {
1877         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1878         struct drm_device *dev = encoder->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         struct intel_crtc *intel_crtc =
1881                 to_intel_crtc(encoder->base.crtc);
1882         enum dpio_channel port = vlv_dport_to_channel(dport);
1883         int pipe = intel_crtc->pipe;
1884
1885         /* Program Tx lane resets to default */
1886         mutex_lock(&dev_priv->dpio_lock);
1887         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1888                          DPIO_PCS_TX_LANE2_RESET |
1889                          DPIO_PCS_TX_LANE1_RESET);
1890         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1891                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1892                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1893                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1894                                  DPIO_PCS_CLK_SOFT_RESET);
1895
1896         /* Fix up inter-pair skew failure */
1897         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1898         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1899         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1900         mutex_unlock(&dev_priv->dpio_lock);
1901 }
1902
1903 /*
1904  * Native read with retry for link status and receiver capability reads for
1905  * cases where the sink may still be asleep.
1906  *
1907  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1908  * supposed to retry 3 times per the spec.
1909  */
1910 static ssize_t
1911 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1912                         void *buffer, size_t size)
1913 {
1914         ssize_t ret;
1915         int i;
1916
1917         for (i = 0; i < 3; i++) {
1918                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1919                 if (ret == size)
1920                         return ret;
1921                 msleep(1);
1922         }
1923
1924         return ret;
1925 }
1926
1927 /*
1928  * Fetch AUX CH registers 0x202 - 0x207 which contain
1929  * link status information
1930  */
1931 static bool
1932 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1933 {
1934         return intel_dp_dpcd_read_wake(&intel_dp->aux,
1935                                        DP_LANE0_1_STATUS,
1936                                        link_status,
1937                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1938 }
1939
1940 /*
1941  * These are source-specific values; current Intel hardware supports
1942  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1943  */
1944
1945 static uint8_t
1946 intel_dp_voltage_max(struct intel_dp *intel_dp)
1947 {
1948         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1949         enum port port = dp_to_dig_port(intel_dp)->port;
1950
1951         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1952                 return DP_TRAIN_VOLTAGE_SWING_1200;
1953         else if (IS_GEN7(dev) && port == PORT_A)
1954                 return DP_TRAIN_VOLTAGE_SWING_800;
1955         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1956                 return DP_TRAIN_VOLTAGE_SWING_1200;
1957         else
1958                 return DP_TRAIN_VOLTAGE_SWING_800;
1959 }
1960
1961 static uint8_t
1962 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1963 {
1964         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1965         enum port port = dp_to_dig_port(intel_dp)->port;
1966
1967         if (IS_BROADWELL(dev)) {
1968                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1969                 case DP_TRAIN_VOLTAGE_SWING_400:
1970                 case DP_TRAIN_VOLTAGE_SWING_600:
1971                         return DP_TRAIN_PRE_EMPHASIS_6;
1972                 case DP_TRAIN_VOLTAGE_SWING_800:
1973                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1974                 case DP_TRAIN_VOLTAGE_SWING_1200:
1975                 default:
1976                         return DP_TRAIN_PRE_EMPHASIS_0;
1977                 }
1978         } else if (IS_HASWELL(dev)) {
1979                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1980                 case DP_TRAIN_VOLTAGE_SWING_400:
1981                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1982                 case DP_TRAIN_VOLTAGE_SWING_600:
1983                         return DP_TRAIN_PRE_EMPHASIS_6;
1984                 case DP_TRAIN_VOLTAGE_SWING_800:
1985                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1986                 case DP_TRAIN_VOLTAGE_SWING_1200:
1987                 default:
1988                         return DP_TRAIN_PRE_EMPHASIS_0;
1989                 }
1990         } else if (IS_VALLEYVIEW(dev)) {
1991                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1992                 case DP_TRAIN_VOLTAGE_SWING_400:
1993                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1994                 case DP_TRAIN_VOLTAGE_SWING_600:
1995                         return DP_TRAIN_PRE_EMPHASIS_6;
1996                 case DP_TRAIN_VOLTAGE_SWING_800:
1997                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1998                 case DP_TRAIN_VOLTAGE_SWING_1200:
1999                 default:
2000                         return DP_TRAIN_PRE_EMPHASIS_0;
2001                 }
2002         } else if (IS_GEN7(dev) && port == PORT_A) {
2003                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2004                 case DP_TRAIN_VOLTAGE_SWING_400:
2005                         return DP_TRAIN_PRE_EMPHASIS_6;
2006                 case DP_TRAIN_VOLTAGE_SWING_600:
2007                 case DP_TRAIN_VOLTAGE_SWING_800:
2008                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2009                 default:
2010                         return DP_TRAIN_PRE_EMPHASIS_0;
2011                 }
2012         } else {
2013                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2014                 case DP_TRAIN_VOLTAGE_SWING_400:
2015                         return DP_TRAIN_PRE_EMPHASIS_6;
2016                 case DP_TRAIN_VOLTAGE_SWING_600:
2017                         return DP_TRAIN_PRE_EMPHASIS_6;
2018                 case DP_TRAIN_VOLTAGE_SWING_800:
2019                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2020                 case DP_TRAIN_VOLTAGE_SWING_1200:
2021                 default:
2022                         return DP_TRAIN_PRE_EMPHASIS_0;
2023                 }
2024         }
2025 }
2026
2027 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2028 {
2029         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2032         struct intel_crtc *intel_crtc =
2033                 to_intel_crtc(dport->base.base.crtc);
2034         unsigned long demph_reg_value, preemph_reg_value,
2035                 uniqtranscale_reg_value;
2036         uint8_t train_set = intel_dp->train_set[0];
2037         enum dpio_channel port = vlv_dport_to_channel(dport);
2038         int pipe = intel_crtc->pipe;
2039
2040         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2041         case DP_TRAIN_PRE_EMPHASIS_0:
2042                 preemph_reg_value = 0x0004000;
2043                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2044                 case DP_TRAIN_VOLTAGE_SWING_400:
2045                         demph_reg_value = 0x2B405555;
2046                         uniqtranscale_reg_value = 0x552AB83A;
2047                         break;
2048                 case DP_TRAIN_VOLTAGE_SWING_600:
2049                         demph_reg_value = 0x2B404040;
2050                         uniqtranscale_reg_value = 0x5548B83A;
2051                         break;
2052                 case DP_TRAIN_VOLTAGE_SWING_800:
2053                         demph_reg_value = 0x2B245555;
2054                         uniqtranscale_reg_value = 0x5560B83A;
2055                         break;
2056                 case DP_TRAIN_VOLTAGE_SWING_1200:
2057                         demph_reg_value = 0x2B405555;
2058                         uniqtranscale_reg_value = 0x5598DA3A;
2059                         break;
2060                 default:
2061                         return 0;
2062                 }
2063                 break;
2064         case DP_TRAIN_PRE_EMPHASIS_3_5:
2065                 preemph_reg_value = 0x0002000;
2066                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2067                 case DP_TRAIN_VOLTAGE_SWING_400:
2068                         demph_reg_value = 0x2B404040;
2069                         uniqtranscale_reg_value = 0x5552B83A;
2070                         break;
2071                 case DP_TRAIN_VOLTAGE_SWING_600:
2072                         demph_reg_value = 0x2B404848;
2073                         uniqtranscale_reg_value = 0x5580B83A;
2074                         break;
2075                 case DP_TRAIN_VOLTAGE_SWING_800:
2076                         demph_reg_value = 0x2B404040;
2077                         uniqtranscale_reg_value = 0x55ADDA3A;
2078                         break;
2079                 default:
2080                         return 0;
2081                 }
2082                 break;
2083         case DP_TRAIN_PRE_EMPHASIS_6:
2084                 preemph_reg_value = 0x0000000;
2085                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2086                 case DP_TRAIN_VOLTAGE_SWING_400:
2087                         demph_reg_value = 0x2B305555;
2088                         uniqtranscale_reg_value = 0x5570B83A;
2089                         break;
2090                 case DP_TRAIN_VOLTAGE_SWING_600:
2091                         demph_reg_value = 0x2B2B4040;
2092                         uniqtranscale_reg_value = 0x55ADDA3A;
2093                         break;
2094                 default:
2095                         return 0;
2096                 }
2097                 break;
2098         case DP_TRAIN_PRE_EMPHASIS_9_5:
2099                 preemph_reg_value = 0x0006000;
2100                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2101                 case DP_TRAIN_VOLTAGE_SWING_400:
2102                         demph_reg_value = 0x1B405555;
2103                         uniqtranscale_reg_value = 0x55ADDA3A;
2104                         break;
2105                 default:
2106                         return 0;
2107                 }
2108                 break;
2109         default:
2110                 return 0;
2111         }
2112
2113         mutex_lock(&dev_priv->dpio_lock);
2114         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2115         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2116         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2117                          uniqtranscale_reg_value);
2118         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2119         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2120         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2121         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2122         mutex_unlock(&dev_priv->dpio_lock);
2123
2124         return 0;
2125 }
2126
2127 static void
2128 intel_get_adjust_train(struct intel_dp *intel_dp,
2129                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2130 {
2131         uint8_t v = 0;
2132         uint8_t p = 0;
2133         int lane;
2134         uint8_t voltage_max;
2135         uint8_t preemph_max;
2136
2137         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2138                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2139                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2140
2141                 if (this_v > v)
2142                         v = this_v;
2143                 if (this_p > p)
2144                         p = this_p;
2145         }
2146
2147         voltage_max = intel_dp_voltage_max(intel_dp);
2148         if (v >= voltage_max)
2149                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2150
2151         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2152         if (p >= preemph_max)
2153                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2154
2155         for (lane = 0; lane < 4; lane++)
2156                 intel_dp->train_set[lane] = v | p;
2157 }
2158
2159 static uint32_t
2160 intel_gen4_signal_levels(uint8_t train_set)
2161 {
2162         uint32_t        signal_levels = 0;
2163
2164         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2165         case DP_TRAIN_VOLTAGE_SWING_400:
2166         default:
2167                 signal_levels |= DP_VOLTAGE_0_4;
2168                 break;
2169         case DP_TRAIN_VOLTAGE_SWING_600:
2170                 signal_levels |= DP_VOLTAGE_0_6;
2171                 break;
2172         case DP_TRAIN_VOLTAGE_SWING_800:
2173                 signal_levels |= DP_VOLTAGE_0_8;
2174                 break;
2175         case DP_TRAIN_VOLTAGE_SWING_1200:
2176                 signal_levels |= DP_VOLTAGE_1_2;
2177                 break;
2178         }
2179         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2180         case DP_TRAIN_PRE_EMPHASIS_0:
2181         default:
2182                 signal_levels |= DP_PRE_EMPHASIS_0;
2183                 break;
2184         case DP_TRAIN_PRE_EMPHASIS_3_5:
2185                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2186                 break;
2187         case DP_TRAIN_PRE_EMPHASIS_6:
2188                 signal_levels |= DP_PRE_EMPHASIS_6;
2189                 break;
2190         case DP_TRAIN_PRE_EMPHASIS_9_5:
2191                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2192                 break;
2193         }
2194         return signal_levels;
2195 }
2196
2197 /* Gen6's DP voltage swing and pre-emphasis control */
2198 static uint32_t
2199 intel_gen6_edp_signal_levels(uint8_t train_set)
2200 {
2201         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2202                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2203         switch (signal_levels) {
2204         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2205         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2206                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2207         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2208                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2209         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2210         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2211                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2212         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2213         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2214                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2215         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2216         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2217                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2218         default:
2219                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2220                               "0x%x\n", signal_levels);
2221                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2222         }
2223 }
2224
2225 /* Gen7's DP voltage swing and pre-emphasis control */
2226 static uint32_t
2227 intel_gen7_edp_signal_levels(uint8_t train_set)
2228 {
2229         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2230                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2231         switch (signal_levels) {
2232         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2233                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2234         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2235                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2236         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2237                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2238
2239         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2240                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2241         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2242                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2243
2244         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2245                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2246         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2247                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2248
2249         default:
2250                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2251                               "0x%x\n", signal_levels);
2252                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2253         }
2254 }
2255
2256 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2257 static uint32_t
2258 intel_hsw_signal_levels(uint8_t train_set)
2259 {
2260         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2261                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2262         switch (signal_levels) {
2263         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2264                 return DDI_BUF_EMP_400MV_0DB_HSW;
2265         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2266                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2267         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2268                 return DDI_BUF_EMP_400MV_6DB_HSW;
2269         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2270                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2271
2272         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2273                 return DDI_BUF_EMP_600MV_0DB_HSW;
2274         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2275                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2276         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2277                 return DDI_BUF_EMP_600MV_6DB_HSW;
2278
2279         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2280                 return DDI_BUF_EMP_800MV_0DB_HSW;
2281         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2283         default:
2284                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2285                               "0x%x\n", signal_levels);
2286                 return DDI_BUF_EMP_400MV_0DB_HSW;
2287         }
2288 }
2289
2290 static uint32_t
2291 intel_bdw_signal_levels(uint8_t train_set)
2292 {
2293         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2294                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2295         switch (signal_levels) {
2296         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2297                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2298         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2299                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2300         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2301                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2302
2303         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2304                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2305         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2306                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2307         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2308                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2309
2310         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2311                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2312         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2314
2315         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2316                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2317
2318         default:
2319                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2320                               "0x%x\n", signal_levels);
2321                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2322         }
2323 }
2324
2325 /* Properly updates "DP" with the correct signal levels. */
2326 static void
2327 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2328 {
2329         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2330         enum port port = intel_dig_port->port;
2331         struct drm_device *dev = intel_dig_port->base.base.dev;
2332         uint32_t signal_levels, mask;
2333         uint8_t train_set = intel_dp->train_set[0];
2334
2335         if (IS_BROADWELL(dev)) {
2336                 signal_levels = intel_bdw_signal_levels(train_set);
2337                 mask = DDI_BUF_EMP_MASK;
2338         } else if (IS_HASWELL(dev)) {
2339                 signal_levels = intel_hsw_signal_levels(train_set);
2340                 mask = DDI_BUF_EMP_MASK;
2341         } else if (IS_VALLEYVIEW(dev)) {
2342                 signal_levels = intel_vlv_signal_levels(intel_dp);
2343                 mask = 0;
2344         } else if (IS_GEN7(dev) && port == PORT_A) {
2345                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2346                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2347         } else if (IS_GEN6(dev) && port == PORT_A) {
2348                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2349                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2350         } else {
2351                 signal_levels = intel_gen4_signal_levels(train_set);
2352                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2353         }
2354
2355         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2356
2357         *DP = (*DP & ~mask) | signal_levels;
2358 }
2359
2360 static bool
2361 intel_dp_set_link_train(struct intel_dp *intel_dp,
2362                         uint32_t *DP,
2363                         uint8_t dp_train_pat)
2364 {
2365         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2366         struct drm_device *dev = intel_dig_port->base.base.dev;
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         enum port port = intel_dig_port->port;
2369         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2370         int ret, len;
2371
2372         if (HAS_DDI(dev)) {
2373                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2374
2375                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2376                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2377                 else
2378                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2379
2380                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2381                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2382                 case DP_TRAINING_PATTERN_DISABLE:
2383                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2384
2385                         break;
2386                 case DP_TRAINING_PATTERN_1:
2387                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2388                         break;
2389                 case DP_TRAINING_PATTERN_2:
2390                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2391                         break;
2392                 case DP_TRAINING_PATTERN_3:
2393                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2394                         break;
2395                 }
2396                 I915_WRITE(DP_TP_CTL(port), temp);
2397
2398         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2399                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2400
2401                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2402                 case DP_TRAINING_PATTERN_DISABLE:
2403                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2404                         break;
2405                 case DP_TRAINING_PATTERN_1:
2406                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2407                         break;
2408                 case DP_TRAINING_PATTERN_2:
2409                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2410                         break;
2411                 case DP_TRAINING_PATTERN_3:
2412                         DRM_ERROR("DP training pattern 3 not supported\n");
2413                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2414                         break;
2415                 }
2416
2417         } else {
2418                 *DP &= ~DP_LINK_TRAIN_MASK;
2419
2420                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2421                 case DP_TRAINING_PATTERN_DISABLE:
2422                         *DP |= DP_LINK_TRAIN_OFF;
2423                         break;
2424                 case DP_TRAINING_PATTERN_1:
2425                         *DP |= DP_LINK_TRAIN_PAT_1;
2426                         break;
2427                 case DP_TRAINING_PATTERN_2:
2428                         *DP |= DP_LINK_TRAIN_PAT_2;
2429                         break;
2430                 case DP_TRAINING_PATTERN_3:
2431                         DRM_ERROR("DP training pattern 3 not supported\n");
2432                         *DP |= DP_LINK_TRAIN_PAT_2;
2433                         break;
2434                 }
2435         }
2436
2437         I915_WRITE(intel_dp->output_reg, *DP);
2438         POSTING_READ(intel_dp->output_reg);
2439
2440         buf[0] = dp_train_pat;
2441         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2442             DP_TRAINING_PATTERN_DISABLE) {
2443                 /* don't write DP_TRAINING_LANEx_SET on disable */
2444                 len = 1;
2445         } else {
2446                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2447                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2448                 len = intel_dp->lane_count + 1;
2449         }
2450
2451         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2452                                 buf, len);
2453
2454         return ret == len;
2455 }
2456
2457 static bool
2458 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2459                         uint8_t dp_train_pat)
2460 {
2461         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2462         intel_dp_set_signal_levels(intel_dp, DP);
2463         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2464 }
2465
2466 static bool
2467 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2468                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2469 {
2470         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2471         struct drm_device *dev = intel_dig_port->base.base.dev;
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         int ret;
2474
2475         intel_get_adjust_train(intel_dp, link_status);
2476         intel_dp_set_signal_levels(intel_dp, DP);
2477
2478         I915_WRITE(intel_dp->output_reg, *DP);
2479         POSTING_READ(intel_dp->output_reg);
2480
2481         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2482                                 intel_dp->train_set, intel_dp->lane_count);
2483
2484         return ret == intel_dp->lane_count;
2485 }
2486
2487 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2488 {
2489         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2490         struct drm_device *dev = intel_dig_port->base.base.dev;
2491         struct drm_i915_private *dev_priv = dev->dev_private;
2492         enum port port = intel_dig_port->port;
2493         uint32_t val;
2494
2495         if (!HAS_DDI(dev))
2496                 return;
2497
2498         val = I915_READ(DP_TP_CTL(port));
2499         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2500         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2501         I915_WRITE(DP_TP_CTL(port), val);
2502
2503         /*
2504          * On PORT_A we can have only eDP in SST mode. There the only reason
2505          * we need to set idle transmission mode is to work around a HW issue
2506          * where we enable the pipe while not in idle link-training mode.
2507          * In this case there is requirement to wait for a minimum number of
2508          * idle patterns to be sent.
2509          */
2510         if (port == PORT_A)
2511                 return;
2512
2513         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2514                      1))
2515                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2516 }
2517
2518 /* Enable corresponding port and start training pattern 1 */
2519 void
2520 intel_dp_start_link_train(struct intel_dp *intel_dp)
2521 {
2522         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2523         struct drm_device *dev = encoder->dev;
2524         int i;
2525         uint8_t voltage;
2526         int voltage_tries, loop_tries;
2527         uint32_t DP = intel_dp->DP;
2528         uint8_t link_config[2];
2529
2530         if (HAS_DDI(dev))
2531                 intel_ddi_prepare_link_retrain(encoder);
2532
2533         /* Write the link configuration data */
2534         link_config[0] = intel_dp->link_bw;
2535         link_config[1] = intel_dp->lane_count;
2536         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2537                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2538         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2539
2540         link_config[0] = 0;
2541         link_config[1] = DP_SET_ANSI_8B10B;
2542         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2543
2544         DP |= DP_PORT_EN;
2545
2546         /* clock recovery */
2547         if (!intel_dp_reset_link_train(intel_dp, &DP,
2548                                        DP_TRAINING_PATTERN_1 |
2549                                        DP_LINK_SCRAMBLING_DISABLE)) {
2550                 DRM_ERROR("failed to enable link training\n");
2551                 return;
2552         }
2553
2554         voltage = 0xff;
2555         voltage_tries = 0;
2556         loop_tries = 0;
2557         for (;;) {
2558                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2559
2560                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2561                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2562                         DRM_ERROR("failed to get link status\n");
2563                         break;
2564                 }
2565
2566                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2567                         DRM_DEBUG_KMS("clock recovery OK\n");
2568                         break;
2569                 }
2570
2571                 /* Check to see if we've tried the max voltage */
2572                 for (i = 0; i < intel_dp->lane_count; i++)
2573                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2574                                 break;
2575                 if (i == intel_dp->lane_count) {
2576                         ++loop_tries;
2577                         if (loop_tries == 5) {
2578                                 DRM_ERROR("too many full retries, give up\n");
2579                                 break;
2580                         }
2581                         intel_dp_reset_link_train(intel_dp, &DP,
2582                                                   DP_TRAINING_PATTERN_1 |
2583                                                   DP_LINK_SCRAMBLING_DISABLE);
2584                         voltage_tries = 0;
2585                         continue;
2586                 }
2587
2588                 /* Check to see if we've tried the same voltage 5 times */
2589                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2590                         ++voltage_tries;
2591                         if (voltage_tries == 5) {
2592                                 DRM_ERROR("too many voltage retries, give up\n");
2593                                 break;
2594                         }
2595                 } else
2596                         voltage_tries = 0;
2597                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2598
2599                 /* Update training set as requested by target */
2600                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2601                         DRM_ERROR("failed to update link training\n");
2602                         break;
2603                 }
2604         }
2605
2606         intel_dp->DP = DP;
2607 }
2608
2609 void
2610 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2611 {
2612         bool channel_eq = false;
2613         int tries, cr_tries;
2614         uint32_t DP = intel_dp->DP;
2615         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2616
2617         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2618         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2619                 training_pattern = DP_TRAINING_PATTERN_3;
2620
2621         /* channel equalization */
2622         if (!intel_dp_set_link_train(intel_dp, &DP,
2623                                      training_pattern |
2624                                      DP_LINK_SCRAMBLING_DISABLE)) {
2625                 DRM_ERROR("failed to start channel equalization\n");
2626                 return;
2627         }
2628
2629         tries = 0;
2630         cr_tries = 0;
2631         channel_eq = false;
2632         for (;;) {
2633                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2634
2635                 if (cr_tries > 5) {
2636                         DRM_ERROR("failed to train DP, aborting\n");
2637                         break;
2638                 }
2639
2640                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2641                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2642                         DRM_ERROR("failed to get link status\n");
2643                         break;
2644                 }
2645
2646                 /* Make sure clock is still ok */
2647                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2648                         intel_dp_start_link_train(intel_dp);
2649                         intel_dp_set_link_train(intel_dp, &DP,
2650                                                 training_pattern |
2651                                                 DP_LINK_SCRAMBLING_DISABLE);
2652                         cr_tries++;
2653                         continue;
2654                 }
2655
2656                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2657                         channel_eq = true;
2658                         break;
2659                 }
2660
2661                 /* Try 5 times, then try clock recovery if that fails */
2662                 if (tries > 5) {
2663                         intel_dp_link_down(intel_dp);
2664                         intel_dp_start_link_train(intel_dp);
2665                         intel_dp_set_link_train(intel_dp, &DP,
2666                                                 training_pattern |
2667                                                 DP_LINK_SCRAMBLING_DISABLE);
2668                         tries = 0;
2669                         cr_tries++;
2670                         continue;
2671                 }
2672
2673                 /* Update training set as requested by target */
2674                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2675                         DRM_ERROR("failed to update link training\n");
2676                         break;
2677                 }
2678                 ++tries;
2679         }
2680
2681         intel_dp_set_idle_link_train(intel_dp);
2682
2683         intel_dp->DP = DP;
2684
2685         if (channel_eq)
2686                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2687
2688 }
2689
2690 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2691 {
2692         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2693                                 DP_TRAINING_PATTERN_DISABLE);
2694 }
2695
2696 static void
2697 intel_dp_link_down(struct intel_dp *intel_dp)
2698 {
2699         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2700         enum port port = intel_dig_port->port;
2701         struct drm_device *dev = intel_dig_port->base.base.dev;
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_crtc *intel_crtc =
2704                 to_intel_crtc(intel_dig_port->base.base.crtc);
2705         uint32_t DP = intel_dp->DP;
2706
2707         /*
2708          * DDI code has a strict mode set sequence and we should try to respect
2709          * it, otherwise we might hang the machine in many different ways. So we
2710          * really should be disabling the port only on a complete crtc_disable
2711          * sequence. This function is just called under two conditions on DDI
2712          * code:
2713          * - Link train failed while doing crtc_enable, and on this case we
2714          *   really should respect the mode set sequence and wait for a
2715          *   crtc_disable.
2716          * - Someone turned the monitor off and intel_dp_check_link_status
2717          *   called us. We don't need to disable the whole port on this case, so
2718          *   when someone turns the monitor on again,
2719          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2720          *   train.
2721          */
2722         if (HAS_DDI(dev))
2723                 return;
2724
2725         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2726                 return;
2727
2728         DRM_DEBUG_KMS("\n");
2729
2730         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2731                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2732                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2733         } else {
2734                 DP &= ~DP_LINK_TRAIN_MASK;
2735                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2736         }
2737         POSTING_READ(intel_dp->output_reg);
2738
2739         /* We don't really know why we're doing this */
2740         intel_wait_for_vblank(dev, intel_crtc->pipe);
2741
2742         if (HAS_PCH_IBX(dev) &&
2743             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2744                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2745
2746                 /* Hardware workaround: leaving our transcoder select
2747                  * set to transcoder B while it's off will prevent the
2748                  * corresponding HDMI output on transcoder A.
2749                  *
2750                  * Combine this with another hardware workaround:
2751                  * transcoder select bit can only be cleared while the
2752                  * port is enabled.
2753                  */
2754                 DP &= ~DP_PIPEB_SELECT;
2755                 I915_WRITE(intel_dp->output_reg, DP);
2756
2757                 /* Changes to enable or select take place the vblank
2758                  * after being written.
2759                  */
2760                 if (WARN_ON(crtc == NULL)) {
2761                         /* We should never try to disable a port without a crtc
2762                          * attached. For paranoia keep the code around for a
2763                          * bit. */
2764                         POSTING_READ(intel_dp->output_reg);
2765                         msleep(50);
2766                 } else
2767                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2768         }
2769
2770         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2771         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2772         POSTING_READ(intel_dp->output_reg);
2773         msleep(intel_dp->panel_power_down_delay);
2774 }
2775
2776 static bool
2777 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2778 {
2779         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2780         struct drm_device *dev = dig_port->base.base.dev;
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782
2783         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2784
2785         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2786                                     sizeof(intel_dp->dpcd)) < 0)
2787                 return false; /* aux transfer failed */
2788
2789         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2790                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2791         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2792
2793         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2794                 return false; /* DPCD not present */
2795
2796         /* Check if the panel supports PSR */
2797         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2798         if (is_edp(intel_dp)) {
2799                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2800                                         intel_dp->psr_dpcd,
2801                                         sizeof(intel_dp->psr_dpcd));
2802                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2803                         dev_priv->psr.sink_support = true;
2804                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2805                 }
2806         }
2807
2808         /* Training Pattern 3 support */
2809         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2810             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2811                 intel_dp->use_tps3 = true;
2812                 DRM_DEBUG_KMS("Displayport TPS3 supported");
2813         } else
2814                 intel_dp->use_tps3 = false;
2815
2816         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2817               DP_DWN_STRM_PORT_PRESENT))
2818                 return true; /* native DP sink */
2819
2820         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2821                 return true; /* no per-port downstream info */
2822
2823         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2824                                     intel_dp->downstream_ports,
2825                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
2826                 return false; /* downstream port status fetch failed */
2827
2828         return true;
2829 }
2830
2831 static void
2832 intel_dp_probe_oui(struct intel_dp *intel_dp)
2833 {
2834         u8 buf[3];
2835
2836         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2837                 return;
2838
2839         intel_edp_panel_vdd_on(intel_dp);
2840
2841         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2842                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2843                               buf[0], buf[1], buf[2]);
2844
2845         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2846                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2847                               buf[0], buf[1], buf[2]);
2848
2849         edp_panel_vdd_off(intel_dp, false);
2850 }
2851
2852 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2853 {
2854         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2855         struct drm_device *dev = intel_dig_port->base.base.dev;
2856         struct intel_crtc *intel_crtc =
2857                 to_intel_crtc(intel_dig_port->base.base.crtc);
2858         u8 buf[1];
2859
2860         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2861                 return -EAGAIN;
2862
2863         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2864                 return -ENOTTY;
2865
2866         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2867                                DP_TEST_SINK_START) < 0)
2868                 return -EAGAIN;
2869
2870         /* Wait 2 vblanks to be sure we will have the correct CRC value */
2871         intel_wait_for_vblank(dev, intel_crtc->pipe);
2872         intel_wait_for_vblank(dev, intel_crtc->pipe);
2873
2874         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2875                 return -EAGAIN;
2876
2877         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2878         return 0;
2879 }
2880
2881 static bool
2882 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2883 {
2884         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2885                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
2886                                        sink_irq_vector, 1) == 1;
2887 }
2888
2889 static void
2890 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2891 {
2892         /* NAK by default */
2893         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2894 }
2895
2896 /*
2897  * According to DP spec
2898  * 5.1.2:
2899  *  1. Read DPCD
2900  *  2. Configure link according to Receiver Capabilities
2901  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2902  *  4. Check link status on receipt of hot-plug interrupt
2903  */
2904
2905 void
2906 intel_dp_check_link_status(struct intel_dp *intel_dp)
2907 {
2908         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2909         u8 sink_irq_vector;
2910         u8 link_status[DP_LINK_STATUS_SIZE];
2911
2912         if (!intel_encoder->connectors_active)
2913                 return;
2914
2915         if (WARN_ON(!intel_encoder->base.crtc))
2916                 return;
2917
2918         /* Try to read receiver status if the link appears to be up */
2919         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2920                 return;
2921         }
2922
2923         /* Now read the DPCD to see if it's actually running */
2924         if (!intel_dp_get_dpcd(intel_dp)) {
2925                 return;
2926         }
2927
2928         /* Try to read the source of the interrupt */
2929         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2930             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2931                 /* Clear interrupt source */
2932                 drm_dp_dpcd_writeb(&intel_dp->aux,
2933                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
2934                                    sink_irq_vector);
2935
2936                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2937                         intel_dp_handle_test_request(intel_dp);
2938                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2939                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2940         }
2941
2942         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2943                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2944                               drm_get_encoder_name(&intel_encoder->base));
2945                 intel_dp_start_link_train(intel_dp);
2946                 intel_dp_complete_link_train(intel_dp);
2947                 intel_dp_stop_link_train(intel_dp);
2948         }
2949 }
2950
2951 /* XXX this is probably wrong for multiple downstream ports */
2952 static enum drm_connector_status
2953 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2954 {
2955         uint8_t *dpcd = intel_dp->dpcd;
2956         uint8_t type;
2957
2958         if (!intel_dp_get_dpcd(intel_dp))
2959                 return connector_status_disconnected;
2960
2961         /* if there's no downstream port, we're done */
2962         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2963                 return connector_status_connected;
2964
2965         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2966         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2967             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2968                 uint8_t reg;
2969
2970                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2971                                             &reg, 1) < 0)
2972                         return connector_status_unknown;
2973
2974                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2975                                               : connector_status_disconnected;
2976         }
2977
2978         /* If no HPD, poke DDC gently */
2979         if (drm_probe_ddc(&intel_dp->aux.ddc))
2980                 return connector_status_connected;
2981
2982         /* Well we tried, say unknown for unreliable port types */
2983         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2984                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2985                 if (type == DP_DS_PORT_TYPE_VGA ||
2986                     type == DP_DS_PORT_TYPE_NON_EDID)
2987                         return connector_status_unknown;
2988         } else {
2989                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2990                         DP_DWN_STRM_PORT_TYPE_MASK;
2991                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2992                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
2993                         return connector_status_unknown;
2994         }
2995
2996         /* Anything else is out of spec, warn and ignore */
2997         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2998         return connector_status_disconnected;
2999 }
3000
3001 static enum drm_connector_status
3002 ironlake_dp_detect(struct intel_dp *intel_dp)
3003 {
3004         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3005         struct drm_i915_private *dev_priv = dev->dev_private;
3006         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3007         enum drm_connector_status status;
3008
3009         /* Can't disconnect eDP, but you can close the lid... */
3010         if (is_edp(intel_dp)) {
3011                 status = intel_panel_detect(dev);
3012                 if (status == connector_status_unknown)
3013                         status = connector_status_connected;
3014                 return status;
3015         }
3016
3017         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3018                 return connector_status_disconnected;
3019
3020         return intel_dp_detect_dpcd(intel_dp);
3021 }
3022
3023 static enum drm_connector_status
3024 g4x_dp_detect(struct intel_dp *intel_dp)
3025 {
3026         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3029         uint32_t bit;
3030
3031         /* Can't disconnect eDP, but you can close the lid... */
3032         if (is_edp(intel_dp)) {
3033                 enum drm_connector_status status;
3034
3035                 status = intel_panel_detect(dev);
3036                 if (status == connector_status_unknown)
3037                         status = connector_status_connected;
3038                 return status;
3039         }
3040
3041         if (IS_VALLEYVIEW(dev)) {
3042                 switch (intel_dig_port->port) {
3043                 case PORT_B:
3044                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3045                         break;
3046                 case PORT_C:
3047                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3048                         break;
3049                 case PORT_D:
3050                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3051                         break;
3052                 default:
3053                         return connector_status_unknown;
3054                 }
3055         } else {
3056                 switch (intel_dig_port->port) {
3057                 case PORT_B:
3058                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3059                         break;
3060                 case PORT_C:
3061                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3062                         break;
3063                 case PORT_D:
3064                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3065                         break;
3066                 default:
3067                         return connector_status_unknown;
3068                 }
3069         }
3070
3071         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3072                 return connector_status_disconnected;
3073
3074         return intel_dp_detect_dpcd(intel_dp);
3075 }
3076
3077 static struct edid *
3078 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3079 {
3080         struct intel_connector *intel_connector = to_intel_connector(connector);
3081
3082         /* use cached edid if we have one */
3083         if (intel_connector->edid) {
3084                 /* invalid edid */
3085                 if (IS_ERR(intel_connector->edid))
3086                         return NULL;
3087
3088                 return drm_edid_duplicate(intel_connector->edid);
3089         }
3090
3091         return drm_get_edid(connector, adapter);
3092 }
3093
3094 static int
3095 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3096 {
3097         struct intel_connector *intel_connector = to_intel_connector(connector);
3098
3099         /* use cached edid if we have one */
3100         if (intel_connector->edid) {
3101                 /* invalid edid */
3102                 if (IS_ERR(intel_connector->edid))
3103                         return 0;
3104
3105                 return intel_connector_update_modes(connector,
3106                                                     intel_connector->edid);
3107         }
3108
3109         return intel_ddc_get_modes(connector, adapter);
3110 }
3111
3112 static enum drm_connector_status
3113 intel_dp_detect(struct drm_connector *connector, bool force)
3114 {
3115         struct intel_dp *intel_dp = intel_attached_dp(connector);
3116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3117         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3118         struct drm_device *dev = connector->dev;
3119         struct drm_i915_private *dev_priv = dev->dev_private;
3120         enum drm_connector_status status;
3121         enum intel_display_power_domain power_domain;
3122         struct edid *edid = NULL;
3123
3124         intel_runtime_pm_get(dev_priv);
3125
3126         power_domain = intel_display_port_power_domain(intel_encoder);
3127         intel_display_power_get(dev_priv, power_domain);
3128
3129         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3130                       connector->base.id, drm_get_connector_name(connector));
3131
3132         intel_dp->has_audio = false;
3133
3134         if (HAS_PCH_SPLIT(dev))
3135                 status = ironlake_dp_detect(intel_dp);
3136         else
3137                 status = g4x_dp_detect(intel_dp);
3138
3139         if (status != connector_status_connected)
3140                 goto out;
3141
3142         intel_dp_probe_oui(intel_dp);
3143
3144         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3145                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3146         } else {
3147                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3148                 if (edid) {
3149                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3150                         kfree(edid);
3151                 }
3152         }
3153
3154         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3155                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3156         status = connector_status_connected;
3157
3158 out:
3159         intel_display_power_put(dev_priv, power_domain);
3160
3161         intel_runtime_pm_put(dev_priv);
3162
3163         return status;
3164 }
3165
3166 static int intel_dp_get_modes(struct drm_connector *connector)
3167 {
3168         struct intel_dp *intel_dp = intel_attached_dp(connector);
3169         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3170         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3171         struct intel_connector *intel_connector = to_intel_connector(connector);
3172         struct drm_device *dev = connector->dev;
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         enum intel_display_power_domain power_domain;
3175         int ret;
3176
3177         /* We should parse the EDID data and find out if it has an audio sink
3178          */
3179
3180         power_domain = intel_display_port_power_domain(intel_encoder);
3181         intel_display_power_get(dev_priv, power_domain);
3182
3183         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3184         intel_display_power_put(dev_priv, power_domain);
3185         if (ret)
3186                 return ret;
3187
3188         /* if eDP has no EDID, fall back to fixed mode */
3189         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3190                 struct drm_display_mode *mode;
3191                 mode = drm_mode_duplicate(dev,
3192                                           intel_connector->panel.fixed_mode);
3193                 if (mode) {
3194                         drm_mode_probed_add(connector, mode);
3195                         return 1;
3196                 }
3197         }
3198         return 0;
3199 }
3200
3201 static bool
3202 intel_dp_detect_audio(struct drm_connector *connector)
3203 {
3204         struct intel_dp *intel_dp = intel_attached_dp(connector);
3205         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3206         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3207         struct drm_device *dev = connector->dev;
3208         struct drm_i915_private *dev_priv = dev->dev_private;
3209         enum intel_display_power_domain power_domain;
3210         struct edid *edid;
3211         bool has_audio = false;
3212
3213         power_domain = intel_display_port_power_domain(intel_encoder);
3214         intel_display_power_get(dev_priv, power_domain);
3215
3216         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3217         if (edid) {
3218                 has_audio = drm_detect_monitor_audio(edid);
3219                 kfree(edid);
3220         }
3221
3222         intel_display_power_put(dev_priv, power_domain);
3223
3224         return has_audio;
3225 }
3226
3227 static int
3228 intel_dp_set_property(struct drm_connector *connector,
3229                       struct drm_property *property,
3230                       uint64_t val)
3231 {
3232         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3233         struct intel_connector *intel_connector = to_intel_connector(connector);
3234         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3235         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3236         int ret;
3237
3238         ret = drm_object_property_set_value(&connector->base, property, val);
3239         if (ret)
3240                 return ret;
3241
3242         if (property == dev_priv->force_audio_property) {
3243                 int i = val;
3244                 bool has_audio;
3245
3246                 if (i == intel_dp->force_audio)
3247                         return 0;
3248
3249                 intel_dp->force_audio = i;
3250
3251                 if (i == HDMI_AUDIO_AUTO)
3252                         has_audio = intel_dp_detect_audio(connector);
3253                 else
3254                         has_audio = (i == HDMI_AUDIO_ON);
3255
3256                 if (has_audio == intel_dp->has_audio)
3257                         return 0;
3258
3259                 intel_dp->has_audio = has_audio;
3260                 goto done;
3261         }
3262
3263         if (property == dev_priv->broadcast_rgb_property) {
3264                 bool old_auto = intel_dp->color_range_auto;
3265                 uint32_t old_range = intel_dp->color_range;
3266
3267                 switch (val) {
3268                 case INTEL_BROADCAST_RGB_AUTO:
3269                         intel_dp->color_range_auto = true;
3270                         break;
3271                 case INTEL_BROADCAST_RGB_FULL:
3272                         intel_dp->color_range_auto = false;
3273                         intel_dp->color_range = 0;
3274                         break;
3275                 case INTEL_BROADCAST_RGB_LIMITED:
3276                         intel_dp->color_range_auto = false;
3277                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3278                         break;
3279                 default:
3280                         return -EINVAL;
3281                 }
3282
3283                 if (old_auto == intel_dp->color_range_auto &&
3284                     old_range == intel_dp->color_range)
3285                         return 0;
3286
3287                 goto done;
3288         }
3289
3290         if (is_edp(intel_dp) &&
3291             property == connector->dev->mode_config.scaling_mode_property) {
3292                 if (val == DRM_MODE_SCALE_NONE) {
3293                         DRM_DEBUG_KMS("no scaling not supported\n");
3294                         return -EINVAL;
3295                 }
3296
3297                 if (intel_connector->panel.fitting_mode == val) {
3298                         /* the eDP scaling property is not changed */
3299                         return 0;
3300                 }
3301                 intel_connector->panel.fitting_mode = val;
3302
3303                 goto done;
3304         }
3305
3306         return -EINVAL;
3307
3308 done:
3309         if (intel_encoder->base.crtc)
3310                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3311
3312         return 0;
3313 }
3314
3315 static void
3316 intel_dp_connector_destroy(struct drm_connector *connector)
3317 {
3318         struct intel_connector *intel_connector = to_intel_connector(connector);
3319
3320         if (!IS_ERR_OR_NULL(intel_connector->edid))
3321                 kfree(intel_connector->edid);
3322
3323         /* Can't call is_edp() since the encoder may have been destroyed
3324          * already. */
3325         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3326                 intel_panel_fini(&intel_connector->panel);
3327
3328         drm_connector_cleanup(connector);
3329         kfree(connector);
3330 }
3331
3332 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3333 {
3334         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3335         struct intel_dp *intel_dp = &intel_dig_port->dp;
3336         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3337
3338         drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3339         drm_encoder_cleanup(encoder);
3340         if (is_edp(intel_dp)) {
3341                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3342                 mutex_lock(&dev->mode_config.mutex);
3343                 edp_panel_vdd_off_sync(intel_dp);
3344                 mutex_unlock(&dev->mode_config.mutex);
3345         }
3346         kfree(intel_dig_port);
3347 }
3348
3349 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3350         .dpms = intel_connector_dpms,
3351         .detect = intel_dp_detect,
3352         .fill_modes = drm_helper_probe_single_connector_modes,
3353         .set_property = intel_dp_set_property,
3354         .destroy = intel_dp_connector_destroy,
3355 };
3356
3357 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3358         .get_modes = intel_dp_get_modes,
3359         .mode_valid = intel_dp_mode_valid,
3360         .best_encoder = intel_best_encoder,
3361 };
3362
3363 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3364         .destroy = intel_dp_encoder_destroy,
3365 };
3366
3367 static void
3368 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3369 {
3370         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3371
3372         intel_dp_check_link_status(intel_dp);
3373 }
3374
3375 /* Return which DP Port should be selected for Transcoder DP control */
3376 int
3377 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3378 {
3379         struct drm_device *dev = crtc->dev;
3380         struct intel_encoder *intel_encoder;
3381         struct intel_dp *intel_dp;
3382
3383         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3384                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3385
3386                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3387                     intel_encoder->type == INTEL_OUTPUT_EDP)
3388                         return intel_dp->output_reg;
3389         }
3390
3391         return -1;
3392 }
3393
3394 /* check the VBT to see whether the eDP is on DP-D port */
3395 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3396 {
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         union child_device_config *p_child;
3399         int i;
3400         static const short port_mapping[] = {
3401                 [PORT_B] = PORT_IDPB,
3402                 [PORT_C] = PORT_IDPC,
3403                 [PORT_D] = PORT_IDPD,
3404         };
3405
3406         if (port == PORT_A)
3407                 return true;
3408
3409         if (!dev_priv->vbt.child_dev_num)
3410                 return false;
3411
3412         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3413                 p_child = dev_priv->vbt.child_dev + i;
3414
3415                 if (p_child->common.dvo_port == port_mapping[port] &&
3416                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3417                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3418                         return true;
3419         }
3420         return false;
3421 }
3422
3423 static void
3424 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3425 {
3426         struct intel_connector *intel_connector = to_intel_connector(connector);
3427
3428         intel_attach_force_audio_property(connector);
3429         intel_attach_broadcast_rgb_property(connector);
3430         intel_dp->color_range_auto = true;
3431
3432         if (is_edp(intel_dp)) {
3433                 drm_mode_create_scaling_mode_property(connector->dev);
3434                 drm_object_attach_property(
3435                         &connector->base,
3436                         connector->dev->mode_config.scaling_mode_property,
3437                         DRM_MODE_SCALE_ASPECT);
3438                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3439         }
3440 }
3441
3442 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3443 {
3444         intel_dp->last_power_cycle = jiffies;
3445         intel_dp->last_power_on = jiffies;
3446         intel_dp->last_backlight_off = jiffies;
3447 }
3448
3449 static void
3450 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3451                                     struct intel_dp *intel_dp,
3452                                     struct edp_power_seq *out)
3453 {
3454         struct drm_i915_private *dev_priv = dev->dev_private;
3455         struct edp_power_seq cur, vbt, spec, final;
3456         u32 pp_on, pp_off, pp_div, pp;
3457         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3458
3459         if (HAS_PCH_SPLIT(dev)) {
3460                 pp_ctrl_reg = PCH_PP_CONTROL;
3461                 pp_on_reg = PCH_PP_ON_DELAYS;
3462                 pp_off_reg = PCH_PP_OFF_DELAYS;
3463                 pp_div_reg = PCH_PP_DIVISOR;
3464         } else {
3465                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3466
3467                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3468                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3469                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3470                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3471         }
3472
3473         /* Workaround: Need to write PP_CONTROL with the unlock key as
3474          * the very first thing. */
3475         pp = ironlake_get_pp_control(intel_dp);
3476         I915_WRITE(pp_ctrl_reg, pp);
3477
3478         pp_on = I915_READ(pp_on_reg);
3479         pp_off = I915_READ(pp_off_reg);
3480         pp_div = I915_READ(pp_div_reg);
3481
3482         /* Pull timing values out of registers */
3483         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3484                 PANEL_POWER_UP_DELAY_SHIFT;
3485
3486         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3487                 PANEL_LIGHT_ON_DELAY_SHIFT;
3488
3489         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3490                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3491
3492         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3493                 PANEL_POWER_DOWN_DELAY_SHIFT;
3494
3495         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3496                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3497
3498         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3499                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3500
3501         vbt = dev_priv->vbt.edp_pps;
3502
3503         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3504          * our hw here, which are all in 100usec. */
3505         spec.t1_t3 = 210 * 10;
3506         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3507         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3508         spec.t10 = 500 * 10;
3509         /* This one is special and actually in units of 100ms, but zero
3510          * based in the hw (so we need to add 100 ms). But the sw vbt
3511          * table multiplies it with 1000 to make it in units of 100usec,
3512          * too. */
3513         spec.t11_t12 = (510 + 100) * 10;
3514
3515         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3516                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3517
3518         /* Use the max of the register settings and vbt. If both are
3519          * unset, fall back to the spec limits. */
3520 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3521                                        spec.field : \
3522                                        max(cur.field, vbt.field))
3523         assign_final(t1_t3);
3524         assign_final(t8);
3525         assign_final(t9);
3526         assign_final(t10);
3527         assign_final(t11_t12);
3528 #undef assign_final
3529
3530 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3531         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3532         intel_dp->backlight_on_delay = get_delay(t8);
3533         intel_dp->backlight_off_delay = get_delay(t9);
3534         intel_dp->panel_power_down_delay = get_delay(t10);
3535         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3536 #undef get_delay
3537
3538         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3539                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3540                       intel_dp->panel_power_cycle_delay);
3541
3542         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3543                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3544
3545         if (out)
3546                 *out = final;
3547 }
3548
3549 static void
3550 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3551                                               struct intel_dp *intel_dp,
3552                                               struct edp_power_seq *seq)
3553 {
3554         struct drm_i915_private *dev_priv = dev->dev_private;
3555         u32 pp_on, pp_off, pp_div, port_sel = 0;
3556         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3557         int pp_on_reg, pp_off_reg, pp_div_reg;
3558
3559         if (HAS_PCH_SPLIT(dev)) {
3560                 pp_on_reg = PCH_PP_ON_DELAYS;
3561                 pp_off_reg = PCH_PP_OFF_DELAYS;
3562                 pp_div_reg = PCH_PP_DIVISOR;
3563         } else {
3564                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3565
3566                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3567                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3568                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3569         }
3570
3571         /*
3572          * And finally store the new values in the power sequencer. The
3573          * backlight delays are set to 1 because we do manual waits on them. For
3574          * T8, even BSpec recommends doing it. For T9, if we don't do this,
3575          * we'll end up waiting for the backlight off delay twice: once when we
3576          * do the manual sleep, and once when we disable the panel and wait for
3577          * the PP_STATUS bit to become zero.
3578          */
3579         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3580                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3581         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3582                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3583         /* Compute the divisor for the pp clock, simply match the Bspec
3584          * formula. */
3585         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3586         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3587                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3588
3589         /* Haswell doesn't have any port selection bits for the panel
3590          * power sequencer any more. */
3591         if (IS_VALLEYVIEW(dev)) {
3592                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3593                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3594                 else
3595                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3596         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3597                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3598                         port_sel = PANEL_PORT_SELECT_DPA;
3599                 else
3600                         port_sel = PANEL_PORT_SELECT_DPD;
3601         }
3602
3603         pp_on |= port_sel;
3604
3605         I915_WRITE(pp_on_reg, pp_on);
3606         I915_WRITE(pp_off_reg, pp_off);
3607         I915_WRITE(pp_div_reg, pp_div);
3608
3609         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3610                       I915_READ(pp_on_reg),
3611                       I915_READ(pp_off_reg),
3612                       I915_READ(pp_div_reg));
3613 }
3614
3615 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3616                                      struct intel_connector *intel_connector,
3617                                      struct edp_power_seq *power_seq)
3618 {
3619         struct drm_connector *connector = &intel_connector->base;
3620         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3621         struct drm_device *dev = intel_dig_port->base.base.dev;
3622         struct drm_i915_private *dev_priv = dev->dev_private;
3623         struct drm_display_mode *fixed_mode = NULL;
3624         bool has_dpcd;
3625         struct drm_display_mode *scan;
3626         struct edid *edid;
3627
3628         if (!is_edp(intel_dp))
3629                 return true;
3630
3631         /* Cache DPCD and EDID for edp. */
3632         intel_edp_panel_vdd_on(intel_dp);
3633         has_dpcd = intel_dp_get_dpcd(intel_dp);
3634         edp_panel_vdd_off(intel_dp, false);
3635
3636         if (has_dpcd) {
3637                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3638                         dev_priv->no_aux_handshake =
3639                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3640                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3641         } else {
3642                 /* if this fails, presume the device is a ghost */
3643                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3644                 return false;
3645         }
3646
3647         /* We now know it's not a ghost, init power sequence regs. */
3648         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3649
3650         mutex_lock(&dev->mode_config.mutex);
3651         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3652         if (edid) {
3653                 if (drm_add_edid_modes(connector, edid)) {
3654                         drm_mode_connector_update_edid_property(connector,
3655                                                                 edid);
3656                         drm_edid_to_eld(connector, edid);
3657                 } else {
3658                         kfree(edid);
3659                         edid = ERR_PTR(-EINVAL);
3660                 }
3661         } else {
3662                 edid = ERR_PTR(-ENOENT);
3663         }
3664         intel_connector->edid = edid;
3665
3666         /* prefer fixed mode from EDID if available */
3667         list_for_each_entry(scan, &connector->probed_modes, head) {
3668                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3669                         fixed_mode = drm_mode_duplicate(dev, scan);
3670                         break;
3671                 }
3672         }
3673
3674         /* fallback to VBT if available for eDP */
3675         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3676                 fixed_mode = drm_mode_duplicate(dev,
3677                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3678                 if (fixed_mode)
3679                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3680         }
3681         mutex_unlock(&dev->mode_config.mutex);
3682
3683         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3684         intel_panel_setup_backlight(connector);
3685
3686         return true;
3687 }
3688
3689 bool
3690 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3691                         struct intel_connector *intel_connector)
3692 {
3693         struct drm_connector *connector = &intel_connector->base;
3694         struct intel_dp *intel_dp = &intel_dig_port->dp;
3695         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3696         struct drm_device *dev = intel_encoder->base.dev;
3697         struct drm_i915_private *dev_priv = dev->dev_private;
3698         enum port port = intel_dig_port->port;
3699         struct edp_power_seq power_seq = { 0 };
3700         int type;
3701
3702         /* intel_dp vfuncs */
3703         if (IS_VALLEYVIEW(dev))
3704                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3705         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3706                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3707         else if (HAS_PCH_SPLIT(dev))
3708                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3709         else
3710                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3711
3712         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3713
3714         /* Preserve the current hw state. */
3715         intel_dp->DP = I915_READ(intel_dp->output_reg);
3716         intel_dp->attached_connector = intel_connector;
3717
3718         if (intel_dp_is_edp(dev, port))
3719                 type = DRM_MODE_CONNECTOR_eDP;
3720         else
3721                 type = DRM_MODE_CONNECTOR_DisplayPort;
3722
3723         /*
3724          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3725          * for DP the encoder type can be set by the caller to
3726          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3727          */
3728         if (type == DRM_MODE_CONNECTOR_eDP)
3729                 intel_encoder->type = INTEL_OUTPUT_EDP;
3730
3731         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3732                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3733                         port_name(port));
3734
3735         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3736         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3737
3738         connector->interlace_allowed = true;
3739         connector->doublescan_allowed = 0;
3740
3741         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3742                           edp_panel_vdd_work);
3743
3744         intel_connector_attach_encoder(intel_connector, intel_encoder);
3745         drm_sysfs_connector_add(connector);
3746
3747         if (HAS_DDI(dev))
3748                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3749         else
3750                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3751         intel_connector->unregister = intel_dp_connector_unregister;
3752
3753         /* Set up the hotplug pin. */
3754         switch (port) {
3755         case PORT_A:
3756                 intel_encoder->hpd_pin = HPD_PORT_A;
3757                 break;
3758         case PORT_B:
3759                 intel_encoder->hpd_pin = HPD_PORT_B;
3760                 break;
3761         case PORT_C:
3762                 intel_encoder->hpd_pin = HPD_PORT_C;
3763                 break;
3764         case PORT_D:
3765                 intel_encoder->hpd_pin = HPD_PORT_D;
3766                 break;
3767         default:
3768                 BUG();
3769         }
3770
3771         if (is_edp(intel_dp)) {
3772                 intel_dp_init_panel_power_timestamps(intel_dp);
3773                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3774         }
3775
3776         intel_dp_aux_init(intel_dp, intel_connector);
3777
3778         intel_dp->psr_setup_done = false;
3779
3780         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3781                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3782                 if (is_edp(intel_dp)) {
3783                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3784                         mutex_lock(&dev->mode_config.mutex);
3785                         edp_panel_vdd_off_sync(intel_dp);
3786                         mutex_unlock(&dev->mode_config.mutex);
3787                 }
3788                 drm_sysfs_connector_remove(connector);
3789                 drm_connector_cleanup(connector);
3790                 return false;
3791         }
3792
3793         intel_dp_add_properties(intel_dp, connector);
3794
3795         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3796          * 0xd.  Failure to do so will result in spurious interrupts being
3797          * generated on the port when a cable is not attached.
3798          */
3799         if (IS_G4X(dev) && !IS_GM45(dev)) {
3800                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3801                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3802         }
3803
3804         return true;
3805 }
3806
3807 void
3808 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3809 {
3810         struct intel_digital_port *intel_dig_port;
3811         struct intel_encoder *intel_encoder;
3812         struct drm_encoder *encoder;
3813         struct intel_connector *intel_connector;
3814
3815         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3816         if (!intel_dig_port)
3817                 return;
3818
3819         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3820         if (!intel_connector) {
3821                 kfree(intel_dig_port);
3822                 return;
3823         }
3824
3825         intel_encoder = &intel_dig_port->base;
3826         encoder = &intel_encoder->base;
3827
3828         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3829                          DRM_MODE_ENCODER_TMDS);
3830
3831         intel_encoder->compute_config = intel_dp_compute_config;
3832         intel_encoder->mode_set = intel_dp_mode_set;
3833         intel_encoder->disable = intel_disable_dp;
3834         intel_encoder->post_disable = intel_post_disable_dp;
3835         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3836         intel_encoder->get_config = intel_dp_get_config;
3837         if (IS_VALLEYVIEW(dev)) {
3838                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3839                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3840                 intel_encoder->enable = vlv_enable_dp;
3841         } else {
3842                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3843                 intel_encoder->enable = g4x_enable_dp;
3844         }
3845
3846         intel_dig_port->port = port;
3847         intel_dig_port->dp.output_reg = output_reg;
3848
3849         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3850         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3851         intel_encoder->cloneable = 0;
3852         intel_encoder->hot_plug = intel_dp_hot_plug;
3853
3854         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3855                 drm_encoder_cleanup(encoder);
3856                 kfree(intel_dig_port);
3857                 kfree(intel_connector);
3858         }
3859 }