drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116
 117 int
 118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 119 {
 120         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 121         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 122
 123         switch (max_link_bw) {
 124         case DP_LINK_BW_1_62:
 125         case DP_LINK_BW_2_7:
 126                 break;
 127         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 128                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 129                      INTEL_INFO(dev)->gen >= 8) &&
 130                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 131                         max_link_bw = DP_LINK_BW_5_4;
 132                 else
 133                         max_link_bw = DP_LINK_BW_2_7;
 134                 break;
 135         default:
 136                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 137                      max_link_bw);
 138                 max_link_bw = DP_LINK_BW_1_62;
 139                 break;
 140         }
 141         return max_link_bw;
 142 }
 143
 144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 145 {
 146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 147         struct drm_device *dev = intel_dig_port->base.base.dev;
 148         u8 source_max, sink_max;
 149
 150         source_max = 4;
 151         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 152             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 153                 source_max = 2;
 154
 155         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 156
 157         return min(source_max, sink_max);
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static enum drm_mode_status
 190 intel_dp_mode_valid(struct drm_connector *connector,
 191                     struct drm_display_mode *mode)
 192 {
 193         struct intel_dp *intel_dp = intel_attached_dp(connector);
 194         struct intel_connector *intel_connector = to_intel_connector(connector);
 195         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 196         int target_clock = mode->clock;
 197         int max_rate, mode_rate, max_lanes, max_link_clock;
 198
 199         if (is_edp(intel_dp) && fixed_mode) {
 200                 if (mode->hdisplay > fixed_mode->hdisplay)
 201                         return MODE_PANEL;
 202
 203                 if (mode->vdisplay > fixed_mode->vdisplay)
 204                         return MODE_PANEL;
 205
 206                 target_clock = fixed_mode->clock;
 207         }
 208
 209         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 210         max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 213         mode_rate = intel_dp_link_required(target_clock, 18);
 214
 215         if (mode_rate > max_rate)
 216                 return MODE_CLOCK_HIGH;
 217
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 258         if (IS_VALLEYVIEW(dev))
 259                 return 200;
 260
 261         clkcfg = I915_READ(CLKCFG);
 262         switch (clkcfg & CLKCFG_FSB_MASK) {
 263         case CLKCFG_FSB_400:
 264                 return 100;
 265         case CLKCFG_FSB_533:
 266                 return 133;
 267         case CLKCFG_FSB_667:
 268                 return 166;
 269         case CLKCFG_FSB_800:
 270                 return 200;
 271         case CLKCFG_FSB_1067:
 272                 return 266;
 273         case CLKCFG_FSB_1333:
 274                 return 333;
 275         /* these two are just a guess; one of them might be right */
 276         case CLKCFG_FSB_1600:
 277         case CLKCFG_FSB_1600_ALT:
 278                 return 400;
 279         default:
 280                 return 133;
 281         }
 282 }
 283
 284 static void
 285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 286                                     struct intel_dp *intel_dp,
 287                                     struct edp_power_seq *out);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp,
 291                                               struct edp_power_seq *out);
 292
 293 static enum pipe
 294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 298         struct drm_device *dev = intel_dig_port->base.base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         enum port port = intel_dig_port->port;
 301         enum pipe pipe;
 302
 303         /* modeset should have pipe */
 304         if (crtc)
 305                 return to_intel_crtc(crtc)->pipe;
 306
 307         /* init time, try to find a pipe with this port selected */
 308         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 309                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 310                         PANEL_PORT_SELECT_MASK;
 311                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 312                         return pipe;
 313                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 314                         return pipe;
 315         }
 316
 317         /* shrug */
 318         return PIPE_A;
 319 }
 320
 321 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 322 {
 323         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 324
 325         if (HAS_PCH_SPLIT(dev))
 326                 return PCH_PP_CONTROL;
 327         else
 328                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 329 }
 330
 331 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 332 {
 333         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 334
 335         if (HAS_PCH_SPLIT(dev))
 336                 return PCH_PP_STATUS;
 337         else
 338                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 339 }
 340
 341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 342    This function only applicable when panel PM state is not to be tracked */
 343 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 344                               void *unused)
 345 {
 346         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 347                                                  edp_notifier);
 348         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         u32 pp_div;
 351         u32 pp_ctrl_reg, pp_div_reg;
 352         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 353
 354         if (!is_edp(intel_dp) || code != SYS_RESTART)
 355                 return 0;
 356
 357         if (IS_VALLEYVIEW(dev)) {
 358                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 359                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 360                 pp_div = I915_READ(pp_div_reg);
 361                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 362
 363                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 364                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 365                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 366                 msleep(intel_dp->panel_power_cycle_delay);
 367         }
 368
 369         return 0;
 370 }
 371
 372 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 373 {
 374         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 378 }
 379
 380 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 381 {
 382         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 385         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 386         enum intel_display_power_domain power_domain;
 387
 388         power_domain = intel_display_port_power_domain(intel_encoder);
 389         return intel_display_power_enabled(dev_priv, power_domain) &&
 390                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 391 }
 392
 393 static void
 394 intel_dp_check_edp(struct intel_dp *intel_dp)
 395 {
 396         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398
 399         if (!is_edp(intel_dp))
 400                 return;
 401
 402         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 403                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 404                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 405                               I915_READ(_pp_stat_reg(intel_dp)),
 406                               I915_READ(_pp_ctrl_reg(intel_dp)));
 407         }
 408 }
 409
 410 static uint32_t
 411 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 412 {
 413         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 414         struct drm_device *dev = intel_dig_port->base.base.dev;
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 417         uint32_t status;
 418         bool done;
 419
 420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 421         if (has_aux_irq)
 422                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 423                                           msecs_to_jiffies_timeout(10));
 424         else
 425                 done = wait_for_atomic(C, 10) == 0;
 426         if (!done)
 427                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 428                           has_aux_irq);
 429 #undef C
 430
 431         return status;
 432 }
 433
 434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 435 {
 436         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 437         struct drm_device *dev = intel_dig_port->base.base.dev;
 438
 439         /*
 440          * The clock divider is based off the hrawclk, and would like to run at
 441          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 442          */
 443         return index ? 0 : intel_hrawclk(dev) / 2;
 444 }
 445
 446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 447 {
 448         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 449         struct drm_device *dev = intel_dig_port->base.base.dev;
 450
 451         if (index)
 452                 return 0;
 453
 454         if (intel_dig_port->port == PORT_A) {
 455                 if (IS_GEN6(dev) || IS_GEN7(dev))
 456                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 457                 else
 458                         return 225; /* eDP input clock at 450Mhz */
 459         } else {
 460                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 461         }
 462 }
 463
 464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 465 {
 466         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 467         struct drm_device *dev = intel_dig_port->base.base.dev;
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         if (intel_dig_port->port == PORT_A) {
 471                 if (index)
 472                         return 0;
 473                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 474         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 475                 /* Workaround for non-ULT HSW */
 476                 switch (index) {
 477                 case 0: return 63;
 478                 case 1: return 72;
 479                 default: return 0;
 480                 }
 481         } else  {
 482                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 483         }
 484 }
 485
 486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 487 {
 488         return index ? 0 : 100;
 489 }
 490
 491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 492                                       bool has_aux_irq,
 493                                       int send_bytes,
 494                                       uint32_t aux_clock_divider)
 495 {
 496         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 497         struct drm_device *dev = intel_dig_port->base.base.dev;
 498         uint32_t precharge, timeout;
 499
 500         if (IS_GEN6(dev))
 501                 precharge = 3;
 502         else
 503                 precharge = 5;
 504
 505         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 506                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 507         else
 508                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 509
 510         return DP_AUX_CH_CTL_SEND_BUSY |
 511                DP_AUX_CH_CTL_DONE |
 512                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 513                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 514                timeout |
 515                DP_AUX_CH_CTL_RECEIVE_ERROR |
 516                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 517                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 518                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 519 }
 520
 521 static int
 522 intel_dp_aux_ch(struct intel_dp *intel_dp,
 523                 uint8_t *send, int send_bytes,
 524                 uint8_t *recv, int recv_size)
 525 {
 526         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 527         struct drm_device *dev = intel_dig_port->base.base.dev;
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 530         uint32_t ch_data = ch_ctl + 4;
 531         uint32_t aux_clock_divider;
 532         int i, ret, recv_bytes;
 533         uint32_t status;
 534         int try, clock = 0;
 535         bool has_aux_irq = HAS_AUX_IRQ(dev);
 536         bool vdd;
 537
 538         vdd = _edp_panel_vdd_on(intel_dp);
 539
 540         /* dp aux is extremely sensitive to irq latency, hence request the
 541          * lowest possible wakeup latency and so prevent the cpu from going into
 542          * deep sleep states.
 543          */
 544         pm_qos_update_request(&dev_priv->pm_qos, 0);
 545
 546         intel_dp_check_edp(intel_dp);
 547
 548         intel_aux_display_runtime_get(dev_priv);
 549
 550         /* Try to wait for any previous AUX channel activity */
 551         for (try = 0; try < 3; try++) {
 552                 status = I915_READ_NOTRACE(ch_ctl);
 553                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 554                         break;
 555                 msleep(1);
 556         }
 557
 558         if (try == 3) {
 559                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 560                      I915_READ(ch_ctl));
 561                 ret = -EBUSY;
 562                 goto out;
 563         }
 564
 565         /* Only 5 data registers! */
 566         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 567                 ret = -E2BIG;
 568                 goto out;
 569         }
 570
 571         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 572                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 573                                                           has_aux_irq,
 574                                                           send_bytes,
 575                                                           aux_clock_divider);
 576
 577                 /* Must try at least 3 times according to DP spec */
 578                 for (try = 0; try < 5; try++) {
 579                         /* Load the send data into the aux channel data registers */
 580                         for (i = 0; i < send_bytes; i += 4)
 581                                 I915_WRITE(ch_data + i,
 582                                            pack_aux(send + i, send_bytes - i));
 583
 584                         /* Send the command and wait for it to complete */
 585                         I915_WRITE(ch_ctl, send_ctl);
 586
 587                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 588
 589                         /* Clear done status and any errors */
 590                         I915_WRITE(ch_ctl,
 591                                    status |
 592                                    DP_AUX_CH_CTL_DONE |
 593                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 594                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 595
 596                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 597                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 598                                 continue;
 599                         if (status & DP_AUX_CH_CTL_DONE)
 600                                 break;
 601                 }
 602                 if (status & DP_AUX_CH_CTL_DONE)
 603                         break;
 604         }
 605
 606         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 607                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 608                 ret = -EBUSY;
 609                 goto out;
 610         }
 611
 612         /* Check for timeout or receive error.
 613          * Timeouts occur when the sink is not connected
 614          */
 615         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 616                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 617                 ret = -EIO;
 618                 goto out;
 619         }
 620
 621         /* Timeouts occur when the device isn't connected, so they're
 622          * "normal" -- don't fill the kernel log with these */
 623         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 624                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 625                 ret = -ETIMEDOUT;
 626                 goto out;
 627         }
 628
 629         /* Unload any bytes sent back from the other side */
 630         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 631                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 632         if (recv_bytes > recv_size)
 633                 recv_bytes = recv_size;
 634
 635         for (i = 0; i < recv_bytes; i += 4)
 636                 unpack_aux(I915_READ(ch_data + i),
 637                            recv + i, recv_bytes - i);
 638
 639         ret = recv_bytes;
 640 out:
 641         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 642         intel_aux_display_runtime_put(dev_priv);
 643
 644         if (vdd)
 645                 edp_panel_vdd_off(intel_dp, false);
 646
 647         return ret;
 648 }
 649
 650 #define BARE_ADDRESS_SIZE       3
 651 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 652 static ssize_t
 653 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 654 {
 655         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 656         uint8_t txbuf[20], rxbuf[20];
 657         size_t txsize, rxsize;
 658         int ret;
 659
 660         txbuf[0] = msg->request << 4;
 661         txbuf[1] = msg->address >> 8;
 662         txbuf[2] = msg->address & 0xff;
 663         txbuf[3] = msg->size - 1;
 664
 665         switch (msg->request & ~DP_AUX_I2C_MOT) {
 666         case DP_AUX_NATIVE_WRITE:
 667         case DP_AUX_I2C_WRITE:
 668                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 669                 rxsize = 1;
 670
 671                 if (WARN_ON(txsize > 20))
 672                         return -E2BIG;
 673
 674                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 675
 676                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 677                 if (ret > 0) {
 678                         msg->reply = rxbuf[0] >> 4;
 679
 680                         /* Return payload size. */
 681                         ret = msg->size;
 682                 }
 683                 break;
 684
 685         case DP_AUX_NATIVE_READ:
 686         case DP_AUX_I2C_READ:
 687                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 688                 rxsize = msg->size + 1;
 689
 690                 if (WARN_ON(rxsize > 20))
 691                         return -E2BIG;
 692
 693                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 694                 if (ret > 0) {
 695                         msg->reply = rxbuf[0] >> 4;
 696                         /*
 697                          * Assume happy day, and copy the data. The caller is
 698                          * expected to check msg->reply before touching it.
 699                          *
 700                          * Return payload size.
 701                          */
 702                         ret--;
 703                         memcpy(msg->buffer, rxbuf + 1, ret);
 704                 }
 705                 break;
 706
 707         default:
 708                 ret = -EINVAL;
 709                 break;
 710         }
 711
 712         return ret;
 713 }
 714
 715 static void
 716 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 717 {
 718         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 720         enum port port = intel_dig_port->port;
 721         const char *name = NULL;
 722         int ret;
 723
 724         switch (port) {
 725         case PORT_A:
 726                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 727                 name = "DPDDC-A";
 728                 break;
 729         case PORT_B:
 730                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 731                 name = "DPDDC-B";
 732                 break;
 733         case PORT_C:
 734                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 735                 name = "DPDDC-C";
 736                 break;
 737         case PORT_D:
 738                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 739                 name = "DPDDC-D";
 740                 break;
 741         default:
 742                 BUG();
 743         }
 744
 745         if (!HAS_DDI(dev))
 746                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 747
 748         intel_dp->aux.name = name;
 749         intel_dp->aux.dev = dev->dev;
 750         intel_dp->aux.transfer = intel_dp_aux_transfer;
 751
 752         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 753                       connector->base.kdev->kobj.name);
 754
 755         ret = drm_dp_aux_register(&intel_dp->aux);
 756         if (ret < 0) {
 757                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 758                           name, ret);
 759                 return;
 760         }
 761
 762         ret = sysfs_create_link(&connector->base.kdev->kobj,
 763                                 &intel_dp->aux.ddc.dev.kobj,
 764                                 intel_dp->aux.ddc.dev.kobj.name);
 765         if (ret < 0) {
 766                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 767                 drm_dp_aux_unregister(&intel_dp->aux);
 768         }
 769 }
 770
 771 static void
 772 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 773 {
 774         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 775
 776         if (!intel_connector->mst_port)
 777                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
 778                                   intel_dp->aux.ddc.dev.kobj.name);
 779         intel_connector_unregister(intel_connector);
 780 }
 781
 782 static void
 783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
 784 {
 785         switch (link_bw) {
 786         case DP_LINK_BW_1_62:
 787                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 788                 break;
 789         case DP_LINK_BW_2_7:
 790                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 791                 break;
 792         case DP_LINK_BW_5_4:
 793                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 794                 break;
 795         }
 796 }
 797
 798 static void
 799 intel_dp_set_clock(struct intel_encoder *encoder,
 800                    struct intel_crtc_config *pipe_config, int link_bw)
 801 {
 802         struct drm_device *dev = encoder->base.dev;
 803         const struct dp_link_dpll *divisor = NULL;
 804         int i, count = 0;
 805
 806         if (IS_G4X(dev)) {
 807                 divisor = gen4_dpll;
 808                 count = ARRAY_SIZE(gen4_dpll);
 809         } else if (HAS_PCH_SPLIT(dev)) {
 810                 divisor = pch_dpll;
 811                 count = ARRAY_SIZE(pch_dpll);
 812         } else if (IS_CHERRYVIEW(dev)) {
 813                 divisor = chv_dpll;
 814                 count = ARRAY_SIZE(chv_dpll);
 815         } else if (IS_VALLEYVIEW(dev)) {
 816                 divisor = vlv_dpll;
 817                 count = ARRAY_SIZE(vlv_dpll);
 818         }
 819
 820         if (divisor && count) {
 821                 for (i = 0; i < count; i++) {
 822                         if (link_bw == divisor[i].link_bw) {
 823                                 pipe_config->dpll = divisor[i].dpll;
 824                                 pipe_config->clock_set = true;
 825                                 break;
 826                         }
 827                 }
 828         }
 829 }
 830
 831 static void
 832 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 833 {
 834         struct drm_device *dev = crtc->base.dev;
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         enum transcoder transcoder = crtc->config.cpu_transcoder;
 837
 838         I915_WRITE(PIPE_DATA_M2(transcoder),
 839                 TU_SIZE(m_n->tu) | m_n->gmch_m);
 840         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
 841         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
 842         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 843 }
 844
 845 bool
 846 intel_dp_compute_config(struct intel_encoder *encoder,
 847                         struct intel_crtc_config *pipe_config)
 848 {
 849         struct drm_device *dev = encoder->base.dev;
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 852         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 853         enum port port = dp_to_dig_port(intel_dp)->port;
 854         struct intel_crtc *intel_crtc = encoder->new_crtc;
 855         struct intel_connector *intel_connector = intel_dp->attached_connector;
 856         int lane_count, clock;
 857         int min_lane_count = 1;
 858         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 859         /* Conveniently, the link BW constants become indices with a shift...*/
 860         int min_clock = 0;
 861         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 862         int bpp, mode_rate;
 863         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 864         int link_avail, link_clock;
 865
 866         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 867                 pipe_config->has_pch_encoder = true;
 868
 869         pipe_config->has_dp_encoder = true;
 870         pipe_config->has_audio = intel_dp->has_audio;
 871
 872         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 873                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 874                                        adjusted_mode);
 875                 if (!HAS_PCH_SPLIT(dev))
 876                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 877                                                  intel_connector->panel.fitting_mode);
 878                 else
 879                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 880                                                 intel_connector->panel.fitting_mode);
 881         }
 882
 883         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 884                 return false;
 885
 886         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 887                       "max bw %02x pixel clock %iKHz\n",
 888                       max_lane_count, bws[max_clock],
 889                       adjusted_mode->crtc_clock);
 890
 891         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 892          * bpc in between. */
 893         bpp = pipe_config->pipe_bpp;
 894         if (is_edp(intel_dp)) {
 895                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 896                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 897                                       dev_priv->vbt.edp_bpp);
 898                         bpp = dev_priv->vbt.edp_bpp;
 899                 }
 900
 901                 if (IS_BROADWELL(dev)) {
 902                         /* Yes, it's an ugly hack. */
 903                         min_lane_count = max_lane_count;
 904                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 905                                       min_lane_count);
 906                 } else if (dev_priv->vbt.edp_lanes) {
 907                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 908                                              max_lane_count);
 909                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 910                                       min_lane_count);
 911                 }
 912
 913                 if (dev_priv->vbt.edp_rate) {
 914                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 915                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 916                                       bws[min_clock]);
 917                 }
 918         }
 919
 920         for (; bpp >= 6*3; bpp -= 2*3) {
 921                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 922                                                    bpp);
 923
 924                 for (clock = min_clock; clock <= max_clock; clock++) {
 925                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 926                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 927                                 link_avail = intel_dp_max_data_rate(link_clock,
 928                                                                     lane_count);
 929
 930                                 if (mode_rate <= link_avail) {
 931                                         goto found;
 932                                 }
 933                         }
 934                 }
 935         }
 936
 937         return false;
 938
 939 found:
 940         if (intel_dp->color_range_auto) {
 941                 /*
 942                  * See:
 943                  * CEA-861-E - 5.1 Default Encoding Parameters
 944                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 945                  */
 946                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 947                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 948                 else
 949                         intel_dp->color_range = 0;
 950         }
 951
 952         if (intel_dp->color_range)
 953                 pipe_config->limited_color_range = true;
 954
 955         intel_dp->link_bw = bws[clock];
 956         intel_dp->lane_count = lane_count;
 957         pipe_config->pipe_bpp = bpp;
 958         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 959
 960         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 961                       intel_dp->link_bw, intel_dp->lane_count,
 962                       pipe_config->port_clock, bpp);
 963         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 964                       mode_rate, link_avail);
 965
 966         intel_link_compute_m_n(bpp, lane_count,
 967                                adjusted_mode->crtc_clock,
 968                                pipe_config->port_clock,
 969                                &pipe_config->dp_m_n);
 970
 971         if (intel_connector->panel.downclock_mode != NULL &&
 972                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 973                         intel_link_compute_m_n(bpp, lane_count,
 974                                 intel_connector->panel.downclock_mode->clock,
 975                                 pipe_config->port_clock,
 976                                 &pipe_config->dp_m2_n2);
 977         }
 978
 979         if (HAS_DDI(dev))
 980                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 981         else
 982                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 983
 984         return true;
 985 }
 986
 987 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 988 {
 989         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 990         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 991         struct drm_device *dev = crtc->base.dev;
 992         struct drm_i915_private *dev_priv = dev->dev_private;
 993         u32 dpa_ctl;
 994
 995         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 996         dpa_ctl = I915_READ(DP_A);
 997         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 998
 999         if (crtc->config.port_clock == 162000) {
1000                 /* For a long time we've carried around a ILK-DevA w/a for the
1001                  * 160MHz clock. If we're really unlucky, it's still required.
1002                  */
1003                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1004                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1005                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1006         } else {
1007                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1008                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1009         }
1010
1011         I915_WRITE(DP_A, dpa_ctl);
1012
1013         POSTING_READ(DP_A);
1014         udelay(500);
1015 }
1016
1017 static void intel_dp_prepare(struct intel_encoder *encoder)
1018 {
1019         struct drm_device *dev = encoder->base.dev;
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1022         enum port port = dp_to_dig_port(intel_dp)->port;
1023         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1024         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1025
1026         /*
1027          * There are four kinds of DP registers:
1028          *
1029          *      IBX PCH
1030          *      SNB CPU
1031          *      IVB CPU
1032          *      CPT PCH
1033          *
1034          * IBX PCH and CPU are the same for almost everything,
1035          * except that the CPU DP PLL is configured in this
1036          * register
1037          *
1038          * CPT PCH is quite different, having many bits moved
1039          * to the TRANS_DP_CTL register instead. That
1040          * configuration happens (oddly) in ironlake_pch_enable
1041          */
1042
1043         /* Preserve the BIOS-computed detected bit. This is
1044          * supposed to be read-only.
1045          */
1046         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1047
1048         /* Handle DP bits in common between all three register formats */
1049         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1050         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1051
1052         if (crtc->config.has_audio) {
1053                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1054                                  pipe_name(crtc->pipe));
1055                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1056                 intel_write_eld(&encoder->base, adjusted_mode);
1057         }
1058
1059         /* Split out the IBX/CPU vs CPT settings */
1060
1061         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1062                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1063                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1064                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1065                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1066                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1067
1068                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1069                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1070
1071                 intel_dp->DP |= crtc->pipe << 29;
1072         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1073                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1074                         intel_dp->DP |= intel_dp->color_range;
1075
1076                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1077                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1078                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1079                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1080                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1081
1082                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1083                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1084
1085                 if (!IS_CHERRYVIEW(dev)) {
1086                         if (crtc->pipe == 1)
1087                                 intel_dp->DP |= DP_PIPEB_SELECT;
1088                 } else {
1089                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1090                 }
1091         } else {
1092                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1093         }
1094 }
1095
1096 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1097 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1098
1099 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1100 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1101
1102 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1103 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1104
1105 static void wait_panel_status(struct intel_dp *intel_dp,
1106                                        u32 mask,
1107                                        u32 value)
1108 {
1109         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 pp_stat_reg, pp_ctrl_reg;
1112
1113         pp_stat_reg = _pp_stat_reg(intel_dp);
1114         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1115
1116         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1117                         mask, value,
1118                         I915_READ(pp_stat_reg),
1119                         I915_READ(pp_ctrl_reg));
1120
1121         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1122                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1123                                 I915_READ(pp_stat_reg),
1124                                 I915_READ(pp_ctrl_reg));
1125         }
1126
1127         DRM_DEBUG_KMS("Wait complete\n");
1128 }
1129
1130 static void wait_panel_on(struct intel_dp *intel_dp)
1131 {
1132         DRM_DEBUG_KMS("Wait for panel power on\n");
1133         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1134 }
1135
1136 static void wait_panel_off(struct intel_dp *intel_dp)
1137 {
1138         DRM_DEBUG_KMS("Wait for panel power off time\n");
1139         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1140 }
1141
1142 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1143 {
1144         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1145
1146         /* When we disable the VDD override bit last we have to do the manual
1147          * wait. */
1148         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1149                                        intel_dp->panel_power_cycle_delay);
1150
1151         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1152 }
1153
1154 static void wait_backlight_on(struct intel_dp *intel_dp)
1155 {
1156         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1157                                        intel_dp->backlight_on_delay);
1158 }
1159
1160 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1161 {
1162         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1163                                        intel_dp->backlight_off_delay);
1164 }
1165
1166 /* Read the current pp_control value, unlocking the register if it
1167  * is locked
1168  */
1169
1170 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1171 {
1172         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173         struct drm_i915_private *dev_priv = dev->dev_private;
1174         u32 control;
1175
1176         control = I915_READ(_pp_ctrl_reg(intel_dp));
1177         control &= ~PANEL_UNLOCK_MASK;
1178         control |= PANEL_UNLOCK_REGS;
1179         return control;
1180 }
1181
1182 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1183 {
1184         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1185         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1186         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188         enum intel_display_power_domain power_domain;
1189         u32 pp;
1190         u32 pp_stat_reg, pp_ctrl_reg;
1191         bool need_to_disable = !intel_dp->want_panel_vdd;
1192
1193         if (!is_edp(intel_dp))
1194                 return false;
1195
1196         intel_dp->want_panel_vdd = true;
1197
1198         if (edp_have_panel_vdd(intel_dp))
1199                 return need_to_disable;
1200
1201         power_domain = intel_display_port_power_domain(intel_encoder);
1202         intel_display_power_get(dev_priv, power_domain);
1203
1204         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1205
1206         if (!edp_have_panel_power(intel_dp))
1207                 wait_panel_power_cycle(intel_dp);
1208
1209         pp = ironlake_get_pp_control(intel_dp);
1210         pp |= EDP_FORCE_VDD;
1211
1212         pp_stat_reg = _pp_stat_reg(intel_dp);
1213         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1214
1215         I915_WRITE(pp_ctrl_reg, pp);
1216         POSTING_READ(pp_ctrl_reg);
1217         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1218                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1219         /*
1220          * If the panel wasn't on, delay before accessing aux channel
1221          */
1222         if (!edp_have_panel_power(intel_dp)) {
1223                 DRM_DEBUG_KMS("eDP was not running\n");
1224                 msleep(intel_dp->panel_power_up_delay);
1225         }
1226
1227         return need_to_disable;
1228 }
1229
1230 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1231 {
1232         if (is_edp(intel_dp)) {
1233                 bool vdd = _edp_panel_vdd_on(intel_dp);
1234
1235                 WARN(!vdd, "eDP VDD already requested on\n");
1236         }
1237 }
1238
1239 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1240 {
1241         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         u32 pp;
1244         u32 pp_stat_reg, pp_ctrl_reg;
1245
1246         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1247
1248         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1249                 struct intel_digital_port *intel_dig_port =
1250                                                 dp_to_dig_port(intel_dp);
1251                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1252                 enum intel_display_power_domain power_domain;
1253
1254                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1255
1256                 pp = ironlake_get_pp_control(intel_dp);
1257                 pp &= ~EDP_FORCE_VDD;
1258
1259                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1260                 pp_stat_reg = _pp_stat_reg(intel_dp);
1261
1262                 I915_WRITE(pp_ctrl_reg, pp);
1263                 POSTING_READ(pp_ctrl_reg);
1264
1265                 /* Make sure sequencer is idle before allowing subsequent activity */
1266                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1267                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1268
1269                 if ((pp & POWER_TARGET_ON) == 0)
1270                         intel_dp->last_power_cycle = jiffies;
1271
1272                 power_domain = intel_display_port_power_domain(intel_encoder);
1273                 intel_display_power_put(dev_priv, power_domain);
1274         }
1275 }
1276
1277 static void edp_panel_vdd_work(struct work_struct *__work)
1278 {
1279         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1280                                                  struct intel_dp, panel_vdd_work);
1281         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1282
1283         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1284         edp_panel_vdd_off_sync(intel_dp);
1285         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1286 }
1287
1288 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1289 {
1290         unsigned long delay;
1291
1292         /*
1293          * Queue the timer to fire a long time from now (relative to the power
1294          * down delay) to keep the panel power up across a sequence of
1295          * operations.
1296          */
1297         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1298         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1299 }
1300
1301 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1302 {
1303         if (!is_edp(intel_dp))
1304                 return;
1305
1306         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1307
1308         intel_dp->want_panel_vdd = false;
1309
1310         if (sync)
1311                 edp_panel_vdd_off_sync(intel_dp);
1312         else
1313                 edp_panel_vdd_schedule_off(intel_dp);
1314 }
1315
1316 void intel_edp_panel_on(struct intel_dp *intel_dp)
1317 {
1318         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1319         struct drm_i915_private *dev_priv = dev->dev_private;
1320         u32 pp;
1321         u32 pp_ctrl_reg;
1322
1323         if (!is_edp(intel_dp))
1324                 return;
1325
1326         DRM_DEBUG_KMS("Turn eDP power on\n");
1327
1328         if (edp_have_panel_power(intel_dp)) {
1329                 DRM_DEBUG_KMS("eDP power already on\n");
1330                 return;
1331         }
1332
1333         wait_panel_power_cycle(intel_dp);
1334
1335         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1336         pp = ironlake_get_pp_control(intel_dp);
1337         if (IS_GEN5(dev)) {
1338                 /* ILK workaround: disable reset around power sequence */
1339                 pp &= ~PANEL_POWER_RESET;
1340                 I915_WRITE(pp_ctrl_reg, pp);
1341                 POSTING_READ(pp_ctrl_reg);
1342         }
1343
1344         pp |= POWER_TARGET_ON;
1345         if (!IS_GEN5(dev))
1346                 pp |= PANEL_POWER_RESET;
1347
1348         I915_WRITE(pp_ctrl_reg, pp);
1349         POSTING_READ(pp_ctrl_reg);
1350
1351         wait_panel_on(intel_dp);
1352         intel_dp->last_power_on = jiffies;
1353
1354         if (IS_GEN5(dev)) {
1355                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1356                 I915_WRITE(pp_ctrl_reg, pp);
1357                 POSTING_READ(pp_ctrl_reg);
1358         }
1359 }
1360
1361 void intel_edp_panel_off(struct intel_dp *intel_dp)
1362 {
1363         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1364         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1365         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         enum intel_display_power_domain power_domain;
1368         u32 pp;
1369         u32 pp_ctrl_reg;
1370
1371         if (!is_edp(intel_dp))
1372                 return;
1373
1374         DRM_DEBUG_KMS("Turn eDP power off\n");
1375
1376         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1377
1378         pp = ironlake_get_pp_control(intel_dp);
1379         /* We need to switch off panel power _and_ force vdd, for otherwise some
1380          * panels get very unhappy and cease to work. */
1381         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1382                 EDP_BLC_ENABLE);
1383
1384         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1385
1386         intel_dp->want_panel_vdd = false;
1387
1388         I915_WRITE(pp_ctrl_reg, pp);
1389         POSTING_READ(pp_ctrl_reg);
1390
1391         intel_dp->last_power_cycle = jiffies;
1392         wait_panel_off(intel_dp);
1393
1394         /* We got a reference when we enabled the VDD. */
1395         power_domain = intel_display_port_power_domain(intel_encoder);
1396         intel_display_power_put(dev_priv, power_domain);
1397 }
1398
1399 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1400 {
1401         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1402         struct drm_device *dev = intel_dig_port->base.base.dev;
1403         struct drm_i915_private *dev_priv = dev->dev_private;
1404         u32 pp;
1405         u32 pp_ctrl_reg;
1406
1407         if (!is_edp(intel_dp))
1408                 return;
1409
1410         DRM_DEBUG_KMS("\n");
1411
1412         intel_panel_enable_backlight(intel_dp->attached_connector);
1413
1414         /*
1415          * If we enable the backlight right away following a panel power
1416          * on, we may see slight flicker as the panel syncs with the eDP
1417          * link.  So delay a bit to make sure the image is solid before
1418          * allowing it to appear.
1419          */
1420         wait_backlight_on(intel_dp);
1421         pp = ironlake_get_pp_control(intel_dp);
1422         pp |= EDP_BLC_ENABLE;
1423
1424         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1425
1426         I915_WRITE(pp_ctrl_reg, pp);
1427         POSTING_READ(pp_ctrl_reg);
1428 }
1429
1430 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1431 {
1432         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         u32 pp;
1435         u32 pp_ctrl_reg;
1436
1437         if (!is_edp(intel_dp))
1438                 return;
1439
1440         DRM_DEBUG_KMS("\n");
1441         pp = ironlake_get_pp_control(intel_dp);
1442         pp &= ~EDP_BLC_ENABLE;
1443
1444         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1445
1446         I915_WRITE(pp_ctrl_reg, pp);
1447         POSTING_READ(pp_ctrl_reg);
1448         intel_dp->last_backlight_off = jiffies;
1449
1450         edp_wait_backlight_off(intel_dp);
1451
1452         intel_panel_disable_backlight(intel_dp->attached_connector);
1453 }
1454
1455 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1456 {
1457         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1458         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1459         struct drm_device *dev = crtc->dev;
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461         u32 dpa_ctl;
1462
1463         assert_pipe_disabled(dev_priv,
1464                              to_intel_crtc(crtc)->pipe);
1465
1466         DRM_DEBUG_KMS("\n");
1467         dpa_ctl = I915_READ(DP_A);
1468         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1469         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1470
1471         /* We don't adjust intel_dp->DP while tearing down the link, to
1472          * facilitate link retraining (e.g. after hotplug). Hence clear all
1473          * enable bits here to ensure that we don't enable too much. */
1474         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1475         intel_dp->DP |= DP_PLL_ENABLE;
1476         I915_WRITE(DP_A, intel_dp->DP);
1477         POSTING_READ(DP_A);
1478         udelay(200);
1479 }
1480
1481 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1482 {
1483         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1484         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1485         struct drm_device *dev = crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         u32 dpa_ctl;
1488
1489         assert_pipe_disabled(dev_priv,
1490                              to_intel_crtc(crtc)->pipe);
1491
1492         dpa_ctl = I915_READ(DP_A);
1493         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1494              "dp pll off, should be on\n");
1495         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1496
1497         /* We can't rely on the value tracked for the DP register in
1498          * intel_dp->DP because link_down must not change that (otherwise link
1499          * re-training will fail. */
1500         dpa_ctl &= ~DP_PLL_ENABLE;
1501         I915_WRITE(DP_A, dpa_ctl);
1502         POSTING_READ(DP_A);
1503         udelay(200);
1504 }
1505
1506 /* If the sink supports it, try to set the power state appropriately */
1507 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1508 {
1509         int ret, i;
1510
1511         /* Should have a valid DPCD by this point */
1512         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1513                 return;
1514
1515         if (mode != DRM_MODE_DPMS_ON) {
1516                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1517                                          DP_SET_POWER_D3);
1518                 if (ret != 1)
1519                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1520         } else {
1521                 /*
1522                  * When turning on, we need to retry for 1ms to give the sink
1523                  * time to wake up.
1524                  */
1525                 for (i = 0; i < 3; i++) {
1526                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1527                                                  DP_SET_POWER_D0);
1528                         if (ret == 1)
1529                                 break;
1530                         msleep(1);
1531                 }
1532         }
1533 }
1534
1535 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1536                                   enum pipe *pipe)
1537 {
1538         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1539         enum port port = dp_to_dig_port(intel_dp)->port;
1540         struct drm_device *dev = encoder->base.dev;
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         enum intel_display_power_domain power_domain;
1543         u32 tmp;
1544
1545         power_domain = intel_display_port_power_domain(encoder);
1546         if (!intel_display_power_enabled(dev_priv, power_domain))
1547                 return false;
1548
1549         tmp = I915_READ(intel_dp->output_reg);
1550
1551         if (!(tmp & DP_PORT_EN))
1552                 return false;
1553
1554         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1555                 *pipe = PORT_TO_PIPE_CPT(tmp);
1556         } else if (IS_CHERRYVIEW(dev)) {
1557                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1558         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1559                 *pipe = PORT_TO_PIPE(tmp);
1560         } else {
1561                 u32 trans_sel;
1562                 u32 trans_dp;
1563                 int i;
1564
1565                 switch (intel_dp->output_reg) {
1566                 case PCH_DP_B:
1567                         trans_sel = TRANS_DP_PORT_SEL_B;
1568                         break;
1569                 case PCH_DP_C:
1570                         trans_sel = TRANS_DP_PORT_SEL_C;
1571                         break;
1572                 case PCH_DP_D:
1573                         trans_sel = TRANS_DP_PORT_SEL_D;
1574                         break;
1575                 default:
1576                         return true;
1577                 }
1578
1579                 for_each_pipe(i) {
1580                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1581                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1582                                 *pipe = i;
1583                                 return true;
1584                         }
1585                 }
1586
1587                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1588                               intel_dp->output_reg);
1589         }
1590
1591         return true;
1592 }
1593
1594 static void intel_dp_get_config(struct intel_encoder *encoder,
1595                                 struct intel_crtc_config *pipe_config)
1596 {
1597         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1598         u32 tmp, flags = 0;
1599         struct drm_device *dev = encoder->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         enum port port = dp_to_dig_port(intel_dp)->port;
1602         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1603         int dotclock;
1604
1605         tmp = I915_READ(intel_dp->output_reg);
1606         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1607                 pipe_config->has_audio = true;
1608
1609         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1610                 if (tmp & DP_SYNC_HS_HIGH)
1611                         flags |= DRM_MODE_FLAG_PHSYNC;
1612                 else
1613                         flags |= DRM_MODE_FLAG_NHSYNC;
1614
1615                 if (tmp & DP_SYNC_VS_HIGH)
1616                         flags |= DRM_MODE_FLAG_PVSYNC;
1617                 else
1618                         flags |= DRM_MODE_FLAG_NVSYNC;
1619         } else {
1620                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1621                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1622                         flags |= DRM_MODE_FLAG_PHSYNC;
1623                 else
1624                         flags |= DRM_MODE_FLAG_NHSYNC;
1625
1626                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1627                         flags |= DRM_MODE_FLAG_PVSYNC;
1628                 else
1629                         flags |= DRM_MODE_FLAG_NVSYNC;
1630         }
1631
1632         pipe_config->adjusted_mode.flags |= flags;
1633
1634         pipe_config->has_dp_encoder = true;
1635
1636         intel_dp_get_m_n(crtc, pipe_config);
1637
1638         if (port == PORT_A) {
1639                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1640                         pipe_config->port_clock = 162000;
1641                 else
1642                         pipe_config->port_clock = 270000;
1643         }
1644
1645         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1646                                             &pipe_config->dp_m_n);
1647
1648         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1649                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1650
1651         pipe_config->adjusted_mode.crtc_clock = dotclock;
1652
1653         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1654             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1655                 /*
1656                  * This is a big fat ugly hack.
1657                  *
1658                  * Some machines in UEFI boot mode provide us a VBT that has 18
1659                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1660                  * unknown we fail to light up. Yet the same BIOS boots up with
1661                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1662                  * max, not what it tells us to use.
1663                  *
1664                  * Note: This will still be broken if the eDP panel is not lit
1665                  * up by the BIOS, and thus we can't get the mode at module
1666                  * load.
1667                  */
1668                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1669                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1670                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1671         }
1672 }
1673
1674 static bool is_edp_psr(struct intel_dp *intel_dp)
1675 {
1676         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1677 }
1678
1679 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1680 {
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683         if (!HAS_PSR(dev))
1684                 return false;
1685
1686         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1687 }
1688
1689 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1690                                     struct edp_vsc_psr *vsc_psr)
1691 {
1692         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1693         struct drm_device *dev = dig_port->base.base.dev;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1696         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1697         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1698         uint32_t *data = (uint32_t *) vsc_psr;
1699         unsigned int i;
1700
1701         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1702            the video DIP being updated before program video DIP data buffer
1703            registers for DIP being updated. */
1704         I915_WRITE(ctl_reg, 0);
1705         POSTING_READ(ctl_reg);
1706
1707         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1708                 if (i < sizeof(struct edp_vsc_psr))
1709                         I915_WRITE(data_reg + i, *data++);
1710                 else
1711                         I915_WRITE(data_reg + i, 0);
1712         }
1713
1714         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1715         POSTING_READ(ctl_reg);
1716 }
1717
1718 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1719 {
1720         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         struct edp_vsc_psr psr_vsc;
1723
1724         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1725         memset(&psr_vsc, 0, sizeof(psr_vsc));
1726         psr_vsc.sdp_header.HB0 = 0;
1727         psr_vsc.sdp_header.HB1 = 0x7;
1728         psr_vsc.sdp_header.HB2 = 0x2;
1729         psr_vsc.sdp_header.HB3 = 0x8;
1730         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1731
1732         /* Avoid continuous PSR exit by masking memup and hpd */
1733         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1734                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1735 }
1736
1737 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1738 {
1739         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1740         struct drm_device *dev = dig_port->base.base.dev;
1741         struct drm_i915_private *dev_priv = dev->dev_private;
1742         uint32_t aux_clock_divider;
1743         int precharge = 0x3;
1744         int msg_size = 5;       /* Header(4) + Message(1) */
1745         bool only_standby = false;
1746
1747         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1748
1749         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1750                 only_standby = true;
1751
1752         /* Enable PSR in sink */
1753         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1754                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1755                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1756         else
1757                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1758                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1759
1760         /* Setup AUX registers */
1761         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1762         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1763         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1764                    DP_AUX_CH_CTL_TIME_OUT_400us |
1765                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1766                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1767                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1768 }
1769
1770 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1771 {
1772         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1773         struct drm_device *dev = dig_port->base.base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         uint32_t max_sleep_time = 0x1f;
1776         uint32_t idle_frames = 1;
1777         uint32_t val = 0x0;
1778         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1779         bool only_standby = false;
1780
1781         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1782                 only_standby = true;
1783
1784         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1785                 val |= EDP_PSR_LINK_STANDBY;
1786                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1787                 val |= EDP_PSR_TP1_TIME_0us;
1788                 val |= EDP_PSR_SKIP_AUX_EXIT;
1789                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1790         } else
1791                 val |= EDP_PSR_LINK_DISABLE;
1792
1793         I915_WRITE(EDP_PSR_CTL(dev), val |
1794                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1795                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1796                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1797                    EDP_PSR_ENABLE);
1798 }
1799
1800 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1801 {
1802         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1803         struct drm_device *dev = dig_port->base.base.dev;
1804         struct drm_i915_private *dev_priv = dev->dev_private;
1805         struct drm_crtc *crtc = dig_port->base.base.crtc;
1806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1807
1808         lockdep_assert_held(&dev_priv->psr.lock);
1809         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1810         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1811
1812         dev_priv->psr.source_ok = false;
1813
1814         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1815                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1816                 return false;
1817         }
1818
1819         if (!i915.enable_psr) {
1820                 DRM_DEBUG_KMS("PSR disable by flag\n");
1821                 return false;
1822         }
1823
1824         /* Below limitations aren't valid for Broadwell */
1825         if (IS_BROADWELL(dev))
1826                 goto out;
1827
1828         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1829             S3D_ENABLE) {
1830                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1831                 return false;
1832         }
1833
1834         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1835                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1836                 return false;
1837         }
1838
1839  out:
1840         dev_priv->psr.source_ok = true;
1841         return true;
1842 }
1843
1844 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1845 {
1846         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1847         struct drm_device *dev = intel_dig_port->base.base.dev;
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849
1850         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1851         WARN_ON(dev_priv->psr.active);
1852         lockdep_assert_held(&dev_priv->psr.lock);
1853
1854         /* Enable PSR on the panel */
1855         intel_edp_psr_enable_sink(intel_dp);
1856
1857         /* Enable PSR on the host */
1858         intel_edp_psr_enable_source(intel_dp);
1859
1860         dev_priv->psr.active = true;
1861 }
1862
1863 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1864 {
1865         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867
1868         if (!HAS_PSR(dev)) {
1869                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1870                 return;
1871         }
1872
1873         if (!is_edp_psr(intel_dp)) {
1874                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1875                 return;
1876         }
1877
1878         mutex_lock(&dev_priv->psr.lock);
1879         if (dev_priv->psr.enabled) {
1880                 DRM_DEBUG_KMS("PSR already in use\n");
1881                 mutex_unlock(&dev_priv->psr.lock);
1882                 return;
1883         }
1884
1885         dev_priv->psr.busy_frontbuffer_bits = 0;
1886
1887         /* Setup PSR once */
1888         intel_edp_psr_setup(intel_dp);
1889
1890         if (intel_edp_psr_match_conditions(intel_dp))
1891                 dev_priv->psr.enabled = intel_dp;
1892         mutex_unlock(&dev_priv->psr.lock);
1893 }
1894
1895 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1896 {
1897         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899
1900         mutex_lock(&dev_priv->psr.lock);
1901         if (!dev_priv->psr.enabled) {
1902                 mutex_unlock(&dev_priv->psr.lock);
1903                 return;
1904         }
1905
1906         if (dev_priv->psr.active) {
1907                 I915_WRITE(EDP_PSR_CTL(dev),
1908                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1909
1910                 /* Wait till PSR is idle */
1911                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1912                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1913                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
1914
1915                 dev_priv->psr.active = false;
1916         } else {
1917                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1918         }
1919
1920         dev_priv->psr.enabled = NULL;
1921         mutex_unlock(&dev_priv->psr.lock);
1922
1923         cancel_delayed_work_sync(&dev_priv->psr.work);
1924 }
1925
1926 static void intel_edp_psr_work(struct work_struct *work)
1927 {
1928         struct drm_i915_private *dev_priv =
1929                 container_of(work, typeof(*dev_priv), psr.work.work);
1930         struct intel_dp *intel_dp = dev_priv->psr.enabled;
1931
1932         mutex_lock(&dev_priv->psr.lock);
1933         intel_dp = dev_priv->psr.enabled;
1934
1935         if (!intel_dp)
1936                 goto unlock;
1937
1938         /*
1939          * The delayed work can race with an invalidate hence we need to
1940          * recheck. Since psr_flush first clears this and then reschedules we
1941          * won't ever miss a flush when bailing out here.
1942          */
1943         if (dev_priv->psr.busy_frontbuffer_bits)
1944                 goto unlock;
1945
1946         intel_edp_psr_do_enable(intel_dp);
1947 unlock:
1948         mutex_unlock(&dev_priv->psr.lock);
1949 }
1950
1951 static void intel_edp_psr_do_exit(struct drm_device *dev)
1952 {
1953         struct drm_i915_private *dev_priv = dev->dev_private;
1954
1955         if (dev_priv->psr.active) {
1956                 u32 val = I915_READ(EDP_PSR_CTL(dev));
1957
1958                 WARN_ON(!(val & EDP_PSR_ENABLE));
1959
1960                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1961
1962                 dev_priv->psr.active = false;
1963         }
1964
1965 }
1966
1967 void intel_edp_psr_invalidate(struct drm_device *dev,
1968                               unsigned frontbuffer_bits)
1969 {
1970         struct drm_i915_private *dev_priv = dev->dev_private;
1971         struct drm_crtc *crtc;
1972         enum pipe pipe;
1973
1974         mutex_lock(&dev_priv->psr.lock);
1975         if (!dev_priv->psr.enabled) {
1976                 mutex_unlock(&dev_priv->psr.lock);
1977                 return;
1978         }
1979
1980         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1981         pipe = to_intel_crtc(crtc)->pipe;
1982
1983         intel_edp_psr_do_exit(dev);
1984
1985         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1986
1987         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1988         mutex_unlock(&dev_priv->psr.lock);
1989 }
1990
1991 void intel_edp_psr_flush(struct drm_device *dev,
1992                          unsigned frontbuffer_bits)
1993 {
1994         struct drm_i915_private *dev_priv = dev->dev_private;
1995         struct drm_crtc *crtc;
1996         enum pipe pipe;
1997
1998         mutex_lock(&dev_priv->psr.lock);
1999         if (!dev_priv->psr.enabled) {
2000                 mutex_unlock(&dev_priv->psr.lock);
2001                 return;
2002         }
2003
2004         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2005         pipe = to_intel_crtc(crtc)->pipe;
2006         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2007
2008         /*
2009          * On Haswell sprite plane updates don't result in a psr invalidating
2010          * signal in the hardware. Which means we need to manually fake this in
2011          * software for all flushes, not just when we've seen a preceding
2012          * invalidation through frontbuffer rendering.
2013          */
2014         if (IS_HASWELL(dev) &&
2015             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2016                 intel_edp_psr_do_exit(dev);
2017
2018         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2019                 schedule_delayed_work(&dev_priv->psr.work,
2020                                       msecs_to_jiffies(100));
2021         mutex_unlock(&dev_priv->psr.lock);
2022 }
2023
2024 void intel_edp_psr_init(struct drm_device *dev)
2025 {
2026         struct drm_i915_private *dev_priv = dev->dev_private;
2027
2028         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2029         mutex_init(&dev_priv->psr.lock);
2030 }
2031
2032 static void intel_disable_dp(struct intel_encoder *encoder)
2033 {
2034         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2035         enum port port = dp_to_dig_port(intel_dp)->port;
2036         struct drm_device *dev = encoder->base.dev;
2037
2038         /* Make sure the panel is off before trying to change the mode. But also
2039          * ensure that we have vdd while we switch off the panel. */
2040         intel_edp_panel_vdd_on(intel_dp);
2041         intel_edp_backlight_off(intel_dp);
2042         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2043         intel_edp_panel_off(intel_dp);
2044
2045         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2046         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2047                 intel_dp_link_down(intel_dp);
2048 }
2049
2050 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2051 {
2052         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2053         enum port port = dp_to_dig_port(intel_dp)->port;
2054
2055         if (port != PORT_A)
2056                 return;
2057
2058         intel_dp_link_down(intel_dp);
2059         ironlake_edp_pll_off(intel_dp);
2060 }
2061
2062 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2063 {
2064         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2065
2066         intel_dp_link_down(intel_dp);
2067 }
2068
2069 static void chv_post_disable_dp(struct intel_encoder *encoder)
2070 {
2071         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2072         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2073         struct drm_device *dev = encoder->base.dev;
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075         struct intel_crtc *intel_crtc =
2076                 to_intel_crtc(encoder->base.crtc);
2077         enum dpio_channel ch = vlv_dport_to_channel(dport);
2078         enum pipe pipe = intel_crtc->pipe;
2079         u32 val;
2080
2081         intel_dp_link_down(intel_dp);
2082
2083         mutex_lock(&dev_priv->dpio_lock);
2084
2085         /* Propagate soft reset to data lane reset */
2086         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2087         val |= CHV_PCS_REQ_SOFTRESET_EN;
2088         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2089
2090         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2091         val |= CHV_PCS_REQ_SOFTRESET_EN;
2092         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2093
2094         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2095         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2096         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2097
2098         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2099         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2100         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2101
2102         mutex_unlock(&dev_priv->dpio_lock);
2103 }
2104
2105 static void intel_enable_dp(struct intel_encoder *encoder)
2106 {
2107         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2108         struct drm_device *dev = encoder->base.dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2111
2112         if (WARN_ON(dp_reg & DP_PORT_EN))
2113                 return;
2114
2115         intel_edp_panel_vdd_on(intel_dp);
2116         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2117         intel_dp_start_link_train(intel_dp);
2118         intel_edp_panel_on(intel_dp);
2119         edp_panel_vdd_off(intel_dp, true);
2120         intel_dp_complete_link_train(intel_dp);
2121         intel_dp_stop_link_train(intel_dp);
2122 }
2123
2124 static void g4x_enable_dp(struct intel_encoder *encoder)
2125 {
2126         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2127
2128         intel_enable_dp(encoder);
2129         intel_edp_backlight_on(intel_dp);
2130 }
2131
2132 static void vlv_enable_dp(struct intel_encoder *encoder)
2133 {
2134         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2135
2136         intel_edp_backlight_on(intel_dp);
2137 }
2138
2139 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2140 {
2141         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2142         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2143
2144         intel_dp_prepare(encoder);
2145
2146         /* Only ilk+ has port A */
2147         if (dport->port == PORT_A) {
2148                 ironlake_set_pll_cpu_edp(intel_dp);
2149                 ironlake_edp_pll_on(intel_dp);
2150         }
2151 }
2152
2153 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2154 {
2155         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2156         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2157         struct drm_device *dev = encoder->base.dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2160         enum dpio_channel port = vlv_dport_to_channel(dport);
2161         int pipe = intel_crtc->pipe;
2162         struct edp_power_seq power_seq;
2163         u32 val;
2164
2165         mutex_lock(&dev_priv->dpio_lock);
2166
2167         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2168         val = 0;
2169         if (pipe)
2170                 val |= (1<<21);
2171         else
2172                 val &= ~(1<<21);
2173         val |= 0x001000c4;
2174         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2175         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2176         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2177
2178         mutex_unlock(&dev_priv->dpio_lock);
2179
2180         if (is_edp(intel_dp)) {
2181                 /* init power sequencer on this pipe and port */
2182                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2183                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2184                                                               &power_seq);
2185         }
2186
2187         intel_enable_dp(encoder);
2188
2189         vlv_wait_port_ready(dev_priv, dport);
2190 }
2191
2192 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2193 {
2194         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2195         struct drm_device *dev = encoder->base.dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         struct intel_crtc *intel_crtc =
2198                 to_intel_crtc(encoder->base.crtc);
2199         enum dpio_channel port = vlv_dport_to_channel(dport);
2200         int pipe = intel_crtc->pipe;
2201
2202         intel_dp_prepare(encoder);
2203
2204         /* Program Tx lane resets to default */
2205         mutex_lock(&dev_priv->dpio_lock);
2206         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2207                          DPIO_PCS_TX_LANE2_RESET |
2208                          DPIO_PCS_TX_LANE1_RESET);
2209         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2210                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2211                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2212                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2213                                  DPIO_PCS_CLK_SOFT_RESET);
2214
2215         /* Fix up inter-pair skew failure */
2216         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2217         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2218         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2219         mutex_unlock(&dev_priv->dpio_lock);
2220 }
2221
2222 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2223 {
2224         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2225         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2226         struct drm_device *dev = encoder->base.dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         struct edp_power_seq power_seq;
2229         struct intel_crtc *intel_crtc =
2230                 to_intel_crtc(encoder->base.crtc);
2231         enum dpio_channel ch = vlv_dport_to_channel(dport);
2232         int pipe = intel_crtc->pipe;
2233         int data, i;
2234         u32 val;
2235
2236         mutex_lock(&dev_priv->dpio_lock);
2237
2238         /* Deassert soft data lane reset*/
2239         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2240         val |= CHV_PCS_REQ_SOFTRESET_EN;
2241         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2242
2243         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2244         val |= CHV_PCS_REQ_SOFTRESET_EN;
2245         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2246
2247         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2248         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2249         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2250
2251         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2252         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2253         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2254
2255         /* Program Tx lane latency optimal setting*/
2256         for (i = 0; i < 4; i++) {
2257                 /* Set the latency optimal bit */
2258                 data = (i == 1) ? 0x0 : 0x6;
2259                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2260                                 data << DPIO_FRC_LATENCY_SHFIT);
2261
2262                 /* Set the upar bit */
2263                 data = (i == 1) ? 0x0 : 0x1;
2264                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2265                                 data << DPIO_UPAR_SHIFT);
2266         }
2267
2268         /* Data lane stagger programming */
2269         /* FIXME: Fix up value only after power analysis */
2270
2271         mutex_unlock(&dev_priv->dpio_lock);
2272
2273         if (is_edp(intel_dp)) {
2274                 /* init power sequencer on this pipe and port */
2275                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2276                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2277                                                               &power_seq);
2278         }
2279
2280         intel_enable_dp(encoder);
2281
2282         vlv_wait_port_ready(dev_priv, dport);
2283 }
2284
2285 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2286 {
2287         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2288         struct drm_device *dev = encoder->base.dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         struct intel_crtc *intel_crtc =
2291                 to_intel_crtc(encoder->base.crtc);
2292         enum dpio_channel ch = vlv_dport_to_channel(dport);
2293         enum pipe pipe = intel_crtc->pipe;
2294         u32 val;
2295
2296         mutex_lock(&dev_priv->dpio_lock);
2297
2298         /* program left/right clock distribution */
2299         if (pipe != PIPE_B) {
2300                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2301                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2302                 if (ch == DPIO_CH0)
2303                         val |= CHV_BUFLEFTENA1_FORCE;
2304                 if (ch == DPIO_CH1)
2305                         val |= CHV_BUFRIGHTENA1_FORCE;
2306                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2307         } else {
2308                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2309                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2310                 if (ch == DPIO_CH0)
2311                         val |= CHV_BUFLEFTENA2_FORCE;
2312                 if (ch == DPIO_CH1)
2313                         val |= CHV_BUFRIGHTENA2_FORCE;
2314                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2315         }
2316
2317         /* program clock channel usage */
2318         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2319         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2320         if (pipe != PIPE_B)
2321                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2322         else
2323                 val |= CHV_PCS_USEDCLKCHANNEL;
2324         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2325
2326         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2327         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2328         if (pipe != PIPE_B)
2329                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2330         else
2331                 val |= CHV_PCS_USEDCLKCHANNEL;
2332         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2333
2334         /*
2335          * This a a bit weird since generally CL
2336          * matches the pipe, but here we need to
2337          * pick the CL based on the port.
2338          */
2339         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2340         if (pipe != PIPE_B)
2341                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2342         else
2343                 val |= CHV_CMN_USEDCLKCHANNEL;
2344         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2345
2346         mutex_unlock(&dev_priv->dpio_lock);
2347 }
2348
2349 /*
2350  * Native read with retry for link status and receiver capability reads for
2351  * cases where the sink may still be asleep.
2352  *
2353  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2354  * supposed to retry 3 times per the spec.
2355  */
2356 static ssize_t
2357 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2358                         void *buffer, size_t size)
2359 {
2360         ssize_t ret;
2361         int i;
2362
2363         for (i = 0; i < 3; i++) {
2364                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2365                 if (ret == size)
2366                         return ret;
2367                 msleep(1);
2368         }
2369
2370         return ret;
2371 }
2372
2373 /*
2374  * Fetch AUX CH registers 0x202 - 0x207 which contain
2375  * link status information
2376  */
2377 static bool
2378 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2379 {
2380         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2381                                        DP_LANE0_1_STATUS,
2382                                        link_status,
2383                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2384 }
2385
2386 /* These are source-specific values. */
2387 static uint8_t
2388 intel_dp_voltage_max(struct intel_dp *intel_dp)
2389 {
2390         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2391         enum port port = dp_to_dig_port(intel_dp)->port;
2392
2393         if (IS_VALLEYVIEW(dev))
2394                 return DP_TRAIN_VOLTAGE_SWING_1200;
2395         else if (IS_GEN7(dev) && port == PORT_A)
2396                 return DP_TRAIN_VOLTAGE_SWING_800;
2397         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2398                 return DP_TRAIN_VOLTAGE_SWING_1200;
2399         else
2400                 return DP_TRAIN_VOLTAGE_SWING_800;
2401 }
2402
2403 static uint8_t
2404 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2405 {
2406         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2407         enum port port = dp_to_dig_port(intel_dp)->port;
2408
2409         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2410                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2411                 case DP_TRAIN_VOLTAGE_SWING_400:
2412                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2413                 case DP_TRAIN_VOLTAGE_SWING_600:
2414                         return DP_TRAIN_PRE_EMPHASIS_6;
2415                 case DP_TRAIN_VOLTAGE_SWING_800:
2416                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2417                 case DP_TRAIN_VOLTAGE_SWING_1200:
2418                 default:
2419                         return DP_TRAIN_PRE_EMPHASIS_0;
2420                 }
2421         } else if (IS_VALLEYVIEW(dev)) {
2422                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2423                 case DP_TRAIN_VOLTAGE_SWING_400:
2424                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2425                 case DP_TRAIN_VOLTAGE_SWING_600:
2426                         return DP_TRAIN_PRE_EMPHASIS_6;
2427                 case DP_TRAIN_VOLTAGE_SWING_800:
2428                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2429                 case DP_TRAIN_VOLTAGE_SWING_1200:
2430                 default:
2431                         return DP_TRAIN_PRE_EMPHASIS_0;
2432                 }
2433         } else if (IS_GEN7(dev) && port == PORT_A) {
2434                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2435                 case DP_TRAIN_VOLTAGE_SWING_400:
2436                         return DP_TRAIN_PRE_EMPHASIS_6;
2437                 case DP_TRAIN_VOLTAGE_SWING_600:
2438                 case DP_TRAIN_VOLTAGE_SWING_800:
2439                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2440                 default:
2441                         return DP_TRAIN_PRE_EMPHASIS_0;
2442                 }
2443         } else {
2444                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2445                 case DP_TRAIN_VOLTAGE_SWING_400:
2446                         return DP_TRAIN_PRE_EMPHASIS_6;
2447                 case DP_TRAIN_VOLTAGE_SWING_600:
2448                         return DP_TRAIN_PRE_EMPHASIS_6;
2449                 case DP_TRAIN_VOLTAGE_SWING_800:
2450                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2451                 case DP_TRAIN_VOLTAGE_SWING_1200:
2452                 default:
2453                         return DP_TRAIN_PRE_EMPHASIS_0;
2454                 }
2455         }
2456 }
2457
2458 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2459 {
2460         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2461         struct drm_i915_private *dev_priv = dev->dev_private;
2462         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2463         struct intel_crtc *intel_crtc =
2464                 to_intel_crtc(dport->base.base.crtc);
2465         unsigned long demph_reg_value, preemph_reg_value,
2466                 uniqtranscale_reg_value;
2467         uint8_t train_set = intel_dp->train_set[0];
2468         enum dpio_channel port = vlv_dport_to_channel(dport);
2469         int pipe = intel_crtc->pipe;
2470
2471         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2472         case DP_TRAIN_PRE_EMPHASIS_0:
2473                 preemph_reg_value = 0x0004000;
2474                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2475                 case DP_TRAIN_VOLTAGE_SWING_400:
2476                         demph_reg_value = 0x2B405555;
2477                         uniqtranscale_reg_value = 0x552AB83A;
2478                         break;
2479                 case DP_TRAIN_VOLTAGE_SWING_600:
2480                         demph_reg_value = 0x2B404040;
2481                         uniqtranscale_reg_value = 0x5548B83A;
2482                         break;
2483                 case DP_TRAIN_VOLTAGE_SWING_800:
2484                         demph_reg_value = 0x2B245555;
2485                         uniqtranscale_reg_value = 0x5560B83A;
2486                         break;
2487                 case DP_TRAIN_VOLTAGE_SWING_1200:
2488                         demph_reg_value = 0x2B405555;
2489                         uniqtranscale_reg_value = 0x5598DA3A;
2490                         break;
2491                 default:
2492                         return 0;
2493                 }
2494                 break;
2495         case DP_TRAIN_PRE_EMPHASIS_3_5:
2496                 preemph_reg_value = 0x0002000;
2497                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2498                 case DP_TRAIN_VOLTAGE_SWING_400:
2499                         demph_reg_value = 0x2B404040;
2500                         uniqtranscale_reg_value = 0x5552B83A;
2501                         break;
2502                 case DP_TRAIN_VOLTAGE_SWING_600:
2503                         demph_reg_value = 0x2B404848;
2504                         uniqtranscale_reg_value = 0x5580B83A;
2505                         break;
2506                 case DP_TRAIN_VOLTAGE_SWING_800:
2507                         demph_reg_value = 0x2B404040;
2508                         uniqtranscale_reg_value = 0x55ADDA3A;
2509                         break;
2510                 default:
2511                         return 0;
2512                 }
2513                 break;
2514         case DP_TRAIN_PRE_EMPHASIS_6:
2515                 preemph_reg_value = 0x0000000;
2516                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2517                 case DP_TRAIN_VOLTAGE_SWING_400:
2518                         demph_reg_value = 0x2B305555;
2519                         uniqtranscale_reg_value = 0x5570B83A;
2520                         break;
2521                 case DP_TRAIN_VOLTAGE_SWING_600:
2522                         demph_reg_value = 0x2B2B4040;
2523                         uniqtranscale_reg_value = 0x55ADDA3A;
2524                         break;
2525                 default:
2526                         return 0;
2527                 }
2528                 break;
2529         case DP_TRAIN_PRE_EMPHASIS_9_5:
2530                 preemph_reg_value = 0x0006000;
2531                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2532                 case DP_TRAIN_VOLTAGE_SWING_400:
2533                         demph_reg_value = 0x1B405555;
2534                         uniqtranscale_reg_value = 0x55ADDA3A;
2535                         break;
2536                 default:
2537                         return 0;
2538                 }
2539                 break;
2540         default:
2541                 return 0;
2542         }
2543
2544         mutex_lock(&dev_priv->dpio_lock);
2545         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2546         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2547         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2548                          uniqtranscale_reg_value);
2549         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2550         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2551         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2552         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2553         mutex_unlock(&dev_priv->dpio_lock);
2554
2555         return 0;
2556 }
2557
2558 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2559 {
2560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2563         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2564         u32 deemph_reg_value, margin_reg_value, val;
2565         uint8_t train_set = intel_dp->train_set[0];
2566         enum dpio_channel ch = vlv_dport_to_channel(dport);
2567         enum pipe pipe = intel_crtc->pipe;
2568         int i;
2569
2570         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2571         case DP_TRAIN_PRE_EMPHASIS_0:
2572                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2573                 case DP_TRAIN_VOLTAGE_SWING_400:
2574                         deemph_reg_value = 128;
2575                         margin_reg_value = 52;
2576                         break;
2577                 case DP_TRAIN_VOLTAGE_SWING_600:
2578                         deemph_reg_value = 128;
2579                         margin_reg_value = 77;
2580                         break;
2581                 case DP_TRAIN_VOLTAGE_SWING_800:
2582                         deemph_reg_value = 128;
2583                         margin_reg_value = 102;
2584                         break;
2585                 case DP_TRAIN_VOLTAGE_SWING_1200:
2586                         deemph_reg_value = 128;
2587                         margin_reg_value = 154;
2588                         /* FIXME extra to set for 1200 */
2589                         break;
2590                 default:
2591                         return 0;
2592                 }
2593                 break;
2594         case DP_TRAIN_PRE_EMPHASIS_3_5:
2595                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2596                 case DP_TRAIN_VOLTAGE_SWING_400:
2597                         deemph_reg_value = 85;
2598                         margin_reg_value = 78;
2599                         break;
2600                 case DP_TRAIN_VOLTAGE_SWING_600:
2601                         deemph_reg_value = 85;
2602                         margin_reg_value = 116;
2603                         break;
2604                 case DP_TRAIN_VOLTAGE_SWING_800:
2605                         deemph_reg_value = 85;
2606                         margin_reg_value = 154;
2607                         break;
2608                 default:
2609                         return 0;
2610                 }
2611                 break;
2612         case DP_TRAIN_PRE_EMPHASIS_6:
2613                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2614                 case DP_TRAIN_VOLTAGE_SWING_400:
2615                         deemph_reg_value = 64;
2616                         margin_reg_value = 104;
2617                         break;
2618                 case DP_TRAIN_VOLTAGE_SWING_600:
2619                         deemph_reg_value = 64;
2620                         margin_reg_value = 154;
2621                         break;
2622                 default:
2623                         return 0;
2624                 }
2625                 break;
2626         case DP_TRAIN_PRE_EMPHASIS_9_5:
2627                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2628                 case DP_TRAIN_VOLTAGE_SWING_400:
2629                         deemph_reg_value = 43;
2630                         margin_reg_value = 154;
2631                         break;
2632                 default:
2633                         return 0;
2634                 }
2635                 break;
2636         default:
2637                 return 0;
2638         }
2639
2640         mutex_lock(&dev_priv->dpio_lock);
2641
2642         /* Clear calc init */
2643         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2644         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2645         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2646
2647         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2648         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2649         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2650
2651         /* Program swing deemph */
2652         for (i = 0; i < 4; i++) {
2653                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2654                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2655                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2656                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2657         }
2658
2659         /* Program swing margin */
2660         for (i = 0; i < 4; i++) {
2661                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2662                 val &= ~DPIO_SWING_MARGIN_MASK;
2663                 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2664                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2665         }
2666
2667         /* Disable unique transition scale */
2668         for (i = 0; i < 4; i++) {
2669                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2670                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2671                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2672         }
2673
2674         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2675                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2676                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2677                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2678
2679                 /*
2680                  * The document said it needs to set bit 27 for ch0 and bit 26
2681                  * for ch1. Might be a typo in the doc.
2682                  * For now, for this unique transition scale selection, set bit
2683                  * 27 for ch0 and ch1.
2684                  */
2685                 for (i = 0; i < 4; i++) {
2686                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2687                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2688                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2689                 }
2690
2691                 for (i = 0; i < 4; i++) {
2692                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2693                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2694                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2695                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2696                 }
2697         }
2698
2699         /* Start swing calculation */
2700         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2701         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2702         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2703
2704         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2705         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2706         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2707
2708         /* LRC Bypass */
2709         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2710         val |= DPIO_LRC_BYPASS;
2711         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2712
2713         mutex_unlock(&dev_priv->dpio_lock);
2714
2715         return 0;
2716 }
2717
2718 static void
2719 intel_get_adjust_train(struct intel_dp *intel_dp,
2720                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2721 {
2722         uint8_t v = 0;
2723         uint8_t p = 0;
2724         int lane;
2725         uint8_t voltage_max;
2726         uint8_t preemph_max;
2727
2728         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2729                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2730                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2731
2732                 if (this_v > v)
2733                         v = this_v;
2734                 if (this_p > p)
2735                         p = this_p;
2736         }
2737
2738         voltage_max = intel_dp_voltage_max(intel_dp);
2739         if (v >= voltage_max)
2740                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2741
2742         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2743         if (p >= preemph_max)
2744                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2745
2746         for (lane = 0; lane < 4; lane++)
2747                 intel_dp->train_set[lane] = v | p;
2748 }
2749
2750 static uint32_t
2751 intel_gen4_signal_levels(uint8_t train_set)
2752 {
2753         uint32_t        signal_levels = 0;
2754
2755         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2756         case DP_TRAIN_VOLTAGE_SWING_400:
2757         default:
2758                 signal_levels |= DP_VOLTAGE_0_4;
2759                 break;
2760         case DP_TRAIN_VOLTAGE_SWING_600:
2761                 signal_levels |= DP_VOLTAGE_0_6;
2762                 break;
2763         case DP_TRAIN_VOLTAGE_SWING_800:
2764                 signal_levels |= DP_VOLTAGE_0_8;
2765                 break;
2766         case DP_TRAIN_VOLTAGE_SWING_1200:
2767                 signal_levels |= DP_VOLTAGE_1_2;
2768                 break;
2769         }
2770         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2771         case DP_TRAIN_PRE_EMPHASIS_0:
2772         default:
2773                 signal_levels |= DP_PRE_EMPHASIS_0;
2774                 break;
2775         case DP_TRAIN_PRE_EMPHASIS_3_5:
2776                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2777                 break;
2778         case DP_TRAIN_PRE_EMPHASIS_6:
2779                 signal_levels |= DP_PRE_EMPHASIS_6;
2780                 break;
2781         case DP_TRAIN_PRE_EMPHASIS_9_5:
2782                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2783                 break;
2784         }
2785         return signal_levels;
2786 }
2787
2788 /* Gen6's DP voltage swing and pre-emphasis control */
2789 static uint32_t
2790 intel_gen6_edp_signal_levels(uint8_t train_set)
2791 {
2792         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2793                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2794         switch (signal_levels) {
2795         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2796         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2797                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2798         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2799                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2800         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2801         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2802                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2803         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2804         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2805                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2806         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2807         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2808                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2809         default:
2810                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2811                               "0x%x\n", signal_levels);
2812                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2813         }
2814 }
2815
2816 /* Gen7's DP voltage swing and pre-emphasis control */
2817 static uint32_t
2818 intel_gen7_edp_signal_levels(uint8_t train_set)
2819 {
2820         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2821                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2822         switch (signal_levels) {
2823         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2824                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2825         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2826                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2827         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2828                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2829
2830         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2831                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2832         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2833                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2834
2835         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2836                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2837         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2838                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2839
2840         default:
2841                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2842                               "0x%x\n", signal_levels);
2843                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2844         }
2845 }
2846
2847 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2848 static uint32_t
2849 intel_hsw_signal_levels(uint8_t train_set)
2850 {
2851         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2852                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2853         switch (signal_levels) {
2854         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2855                 return DDI_BUF_EMP_400MV_0DB_HSW;
2856         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2857                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2858         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2859                 return DDI_BUF_EMP_400MV_6DB_HSW;
2860         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2861                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2862
2863         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2864                 return DDI_BUF_EMP_600MV_0DB_HSW;
2865         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2866                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2867         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2868                 return DDI_BUF_EMP_600MV_6DB_HSW;
2869
2870         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2871                 return DDI_BUF_EMP_800MV_0DB_HSW;
2872         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2873                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2874         default:
2875                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2876                               "0x%x\n", signal_levels);
2877                 return DDI_BUF_EMP_400MV_0DB_HSW;
2878         }
2879 }
2880
2881 /* Properly updates "DP" with the correct signal levels. */
2882 static void
2883 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2884 {
2885         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2886         enum port port = intel_dig_port->port;
2887         struct drm_device *dev = intel_dig_port->base.base.dev;
2888         uint32_t signal_levels, mask;
2889         uint8_t train_set = intel_dp->train_set[0];
2890
2891         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2892                 signal_levels = intel_hsw_signal_levels(train_set);
2893                 mask = DDI_BUF_EMP_MASK;
2894         } else if (IS_CHERRYVIEW(dev)) {
2895                 signal_levels = intel_chv_signal_levels(intel_dp);
2896                 mask = 0;
2897         } else if (IS_VALLEYVIEW(dev)) {
2898                 signal_levels = intel_vlv_signal_levels(intel_dp);
2899                 mask = 0;
2900         } else if (IS_GEN7(dev) && port == PORT_A) {
2901                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2902                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2903         } else if (IS_GEN6(dev) && port == PORT_A) {
2904                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2905                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2906         } else {
2907                 signal_levels = intel_gen4_signal_levels(train_set);
2908                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2909         }
2910
2911         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2912
2913         *DP = (*DP & ~mask) | signal_levels;
2914 }
2915
2916 static bool
2917 intel_dp_set_link_train(struct intel_dp *intel_dp,
2918                         uint32_t *DP,
2919                         uint8_t dp_train_pat)
2920 {
2921         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2922         struct drm_device *dev = intel_dig_port->base.base.dev;
2923         struct drm_i915_private *dev_priv = dev->dev_private;
2924         enum port port = intel_dig_port->port;
2925         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2926         int ret, len;
2927
2928         if (HAS_DDI(dev)) {
2929                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2930
2931                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2932                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2933                 else
2934                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2935
2936                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2937                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2938                 case DP_TRAINING_PATTERN_DISABLE:
2939                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2940
2941                         break;
2942                 case DP_TRAINING_PATTERN_1:
2943                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2944                         break;
2945                 case DP_TRAINING_PATTERN_2:
2946                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2947                         break;
2948                 case DP_TRAINING_PATTERN_3:
2949                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2950                         break;
2951                 }
2952                 I915_WRITE(DP_TP_CTL(port), temp);
2953
2954         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2955                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2956
2957                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2958                 case DP_TRAINING_PATTERN_DISABLE:
2959                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2960                         break;
2961                 case DP_TRAINING_PATTERN_1:
2962                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2963                         break;
2964                 case DP_TRAINING_PATTERN_2:
2965                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2966                         break;
2967                 case DP_TRAINING_PATTERN_3:
2968                         DRM_ERROR("DP training pattern 3 not supported\n");
2969                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2970                         break;
2971                 }
2972
2973         } else {
2974                 *DP &= ~DP_LINK_TRAIN_MASK;
2975
2976                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2977                 case DP_TRAINING_PATTERN_DISABLE:
2978                         *DP |= DP_LINK_TRAIN_OFF;
2979                         break;
2980                 case DP_TRAINING_PATTERN_1:
2981                         *DP |= DP_LINK_TRAIN_PAT_1;
2982                         break;
2983                 case DP_TRAINING_PATTERN_2:
2984                         *DP |= DP_LINK_TRAIN_PAT_2;
2985                         break;
2986                 case DP_TRAINING_PATTERN_3:
2987                         DRM_ERROR("DP training pattern 3 not supported\n");
2988                         *DP |= DP_LINK_TRAIN_PAT_2;
2989                         break;
2990                 }
2991         }
2992
2993         I915_WRITE(intel_dp->output_reg, *DP);
2994         POSTING_READ(intel_dp->output_reg);
2995
2996         buf[0] = dp_train_pat;
2997         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2998             DP_TRAINING_PATTERN_DISABLE) {
2999                 /* don't write DP_TRAINING_LANEx_SET on disable */
3000                 len = 1;
3001         } else {
3002                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3003                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3004                 len = intel_dp->lane_count + 1;
3005         }
3006
3007         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3008                                 buf, len);
3009
3010         return ret == len;
3011 }
3012
3013 static bool
3014 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3015                         uint8_t dp_train_pat)
3016 {
3017         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3018         intel_dp_set_signal_levels(intel_dp, DP);
3019         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3020 }
3021
3022 static bool
3023 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3024                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3025 {
3026         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3027         struct drm_device *dev = intel_dig_port->base.base.dev;
3028         struct drm_i915_private *dev_priv = dev->dev_private;
3029         int ret;
3030
3031         intel_get_adjust_train(intel_dp, link_status);
3032         intel_dp_set_signal_levels(intel_dp, DP);
3033
3034         I915_WRITE(intel_dp->output_reg, *DP);
3035         POSTING_READ(intel_dp->output_reg);
3036
3037         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3038                                 intel_dp->train_set, intel_dp->lane_count);
3039
3040         return ret == intel_dp->lane_count;
3041 }
3042
3043 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3044 {
3045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3046         struct drm_device *dev = intel_dig_port->base.base.dev;
3047         struct drm_i915_private *dev_priv = dev->dev_private;
3048         enum port port = intel_dig_port->port;
3049         uint32_t val;
3050
3051         if (!HAS_DDI(dev))
3052                 return;
3053
3054         val = I915_READ(DP_TP_CTL(port));
3055         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3056         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3057         I915_WRITE(DP_TP_CTL(port), val);
3058
3059         /*
3060          * On PORT_A we can have only eDP in SST mode. There the only reason
3061          * we need to set idle transmission mode is to work around a HW issue
3062          * where we enable the pipe while not in idle link-training mode.
3063          * In this case there is requirement to wait for a minimum number of
3064          * idle patterns to be sent.
3065          */
3066         if (port == PORT_A)
3067                 return;
3068
3069         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3070                      1))
3071                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3072 }
3073
3074 /* Enable corresponding port and start training pattern 1 */
3075 void
3076 intel_dp_start_link_train(struct intel_dp *intel_dp)
3077 {
3078         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3079         struct drm_device *dev = encoder->dev;
3080         int i;
3081         uint8_t voltage;
3082         int voltage_tries, loop_tries;
3083         uint32_t DP = intel_dp->DP;
3084         uint8_t link_config[2];
3085
3086         if (HAS_DDI(dev))
3087                 intel_ddi_prepare_link_retrain(encoder);
3088
3089         /* Write the link configuration data */
3090         link_config[0] = intel_dp->link_bw;
3091         link_config[1] = intel_dp->lane_count;
3092         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3093                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3094         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3095
3096         link_config[0] = 0;
3097         link_config[1] = DP_SET_ANSI_8B10B;
3098         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3099
3100         DP |= DP_PORT_EN;
3101
3102         /* clock recovery */
3103         if (!intel_dp_reset_link_train(intel_dp, &DP,
3104                                        DP_TRAINING_PATTERN_1 |
3105                                        DP_LINK_SCRAMBLING_DISABLE)) {
3106                 DRM_ERROR("failed to enable link training\n");
3107                 return;
3108         }
3109
3110         voltage = 0xff;
3111         voltage_tries = 0;
3112         loop_tries = 0;
3113         for (;;) {
3114                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3115
3116                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3117                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3118                         DRM_ERROR("failed to get link status\n");
3119                         break;
3120                 }
3121
3122                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3123                         DRM_DEBUG_KMS("clock recovery OK\n");
3124                         break;
3125                 }
3126
3127                 /* Check to see if we've tried the max voltage */
3128                 for (i = 0; i < intel_dp->lane_count; i++)
3129                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3130                                 break;
3131                 if (i == intel_dp->lane_count) {
3132                         ++loop_tries;
3133                         if (loop_tries == 5) {
3134                                 DRM_ERROR("too many full retries, give up\n");
3135                                 break;
3136                         }
3137                         intel_dp_reset_link_train(intel_dp, &DP,
3138                                                   DP_TRAINING_PATTERN_1 |
3139                                                   DP_LINK_SCRAMBLING_DISABLE);
3140                         voltage_tries = 0;
3141                         continue;
3142                 }
3143
3144                 /* Check to see if we've tried the same voltage 5 times */
3145                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3146                         ++voltage_tries;
3147                         if (voltage_tries == 5) {
3148                                 DRM_ERROR("too many voltage retries, give up\n");
3149                                 break;
3150                         }
3151                 } else
3152                         voltage_tries = 0;
3153                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3154
3155                 /* Update training set as requested by target */
3156                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3157                         DRM_ERROR("failed to update link training\n");
3158                         break;
3159                 }
3160         }
3161
3162         intel_dp->DP = DP;
3163 }
3164
3165 void
3166 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3167 {
3168         bool channel_eq = false;
3169         int tries, cr_tries;
3170         uint32_t DP = intel_dp->DP;
3171         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3172
3173         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3174         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3175                 training_pattern = DP_TRAINING_PATTERN_3;
3176
3177         /* channel equalization */
3178         if (!intel_dp_set_link_train(intel_dp, &DP,
3179                                      training_pattern |
3180                                      DP_LINK_SCRAMBLING_DISABLE)) {
3181                 DRM_ERROR("failed to start channel equalization\n");
3182                 return;
3183         }
3184
3185         tries = 0;
3186         cr_tries = 0;
3187         channel_eq = false;
3188         for (;;) {
3189                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3190
3191                 if (cr_tries > 5) {
3192                         DRM_ERROR("failed to train DP, aborting\n");
3193                         break;
3194                 }
3195
3196                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3197                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3198                         DRM_ERROR("failed to get link status\n");
3199                         break;
3200                 }
3201
3202                 /* Make sure clock is still ok */
3203                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3204                         intel_dp_start_link_train(intel_dp);
3205                         intel_dp_set_link_train(intel_dp, &DP,
3206                                                 training_pattern |
3207                                                 DP_LINK_SCRAMBLING_DISABLE);
3208                         cr_tries++;
3209                         continue;
3210                 }
3211
3212                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3213                         channel_eq = true;
3214                         break;
3215                 }
3216
3217                 /* Try 5 times, then try clock recovery if that fails */
3218                 if (tries > 5) {
3219                         intel_dp_link_down(intel_dp);
3220                         intel_dp_start_link_train(intel_dp);
3221                         intel_dp_set_link_train(intel_dp, &DP,
3222                                                 training_pattern |
3223                                                 DP_LINK_SCRAMBLING_DISABLE);
3224                         tries = 0;
3225                         cr_tries++;
3226                         continue;
3227                 }
3228
3229                 /* Update training set as requested by target */
3230                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3231                         DRM_ERROR("failed to update link training\n");
3232                         break;
3233                 }
3234                 ++tries;
3235         }
3236
3237         intel_dp_set_idle_link_train(intel_dp);
3238
3239         intel_dp->DP = DP;
3240
3241         if (channel_eq)
3242                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3243
3244 }
3245
3246 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3247 {
3248         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3249                                 DP_TRAINING_PATTERN_DISABLE);
3250 }
3251
3252 static void
3253 intel_dp_link_down(struct intel_dp *intel_dp)
3254 {
3255         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3256         enum port port = intel_dig_port->port;
3257         struct drm_device *dev = intel_dig_port->base.base.dev;
3258         struct drm_i915_private *dev_priv = dev->dev_private;
3259         struct intel_crtc *intel_crtc =
3260                 to_intel_crtc(intel_dig_port->base.base.crtc);
3261         uint32_t DP = intel_dp->DP;
3262
3263         if (WARN_ON(HAS_DDI(dev)))
3264                 return;
3265
3266         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3267                 return;
3268
3269         DRM_DEBUG_KMS("\n");
3270
3271         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3272                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3273                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3274         } else {
3275                 DP &= ~DP_LINK_TRAIN_MASK;
3276                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3277         }
3278         POSTING_READ(intel_dp->output_reg);
3279
3280         if (HAS_PCH_IBX(dev) &&
3281             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3282                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3283
3284                 /* Hardware workaround: leaving our transcoder select
3285                  * set to transcoder B while it's off will prevent the
3286                  * corresponding HDMI output on transcoder A.
3287                  *
3288                  * Combine this with another hardware workaround:
3289                  * transcoder select bit can only be cleared while the
3290                  * port is enabled.
3291                  */
3292                 DP &= ~DP_PIPEB_SELECT;
3293                 I915_WRITE(intel_dp->output_reg, DP);
3294
3295                 /* Changes to enable or select take place the vblank
3296                  * after being written.
3297                  */
3298                 if (WARN_ON(crtc == NULL)) {
3299                         /* We should never try to disable a port without a crtc
3300                          * attached. For paranoia keep the code around for a
3301                          * bit. */
3302                         POSTING_READ(intel_dp->output_reg);
3303                         msleep(50);
3304                 } else
3305                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3306         }
3307
3308         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3309         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3310         POSTING_READ(intel_dp->output_reg);
3311         msleep(intel_dp->panel_power_down_delay);
3312 }
3313
3314 static bool
3315 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3316 {
3317         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3318         struct drm_device *dev = dig_port->base.base.dev;
3319         struct drm_i915_private *dev_priv = dev->dev_private;
3320
3321         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3322
3323         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3324                                     sizeof(intel_dp->dpcd)) < 0)
3325                 return false; /* aux transfer failed */
3326
3327         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3328                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3329         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3330
3331         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3332                 return false; /* DPCD not present */
3333
3334         /* Check if the panel supports PSR */
3335         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3336         if (is_edp(intel_dp)) {
3337                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3338                                         intel_dp->psr_dpcd,
3339                                         sizeof(intel_dp->psr_dpcd));
3340                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3341                         dev_priv->psr.sink_support = true;
3342                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3343                 }
3344         }
3345
3346         /* Training Pattern 3 support */
3347         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3348             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3349                 intel_dp->use_tps3 = true;
3350                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3351         } else
3352                 intel_dp->use_tps3 = false;
3353
3354         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3355               DP_DWN_STRM_PORT_PRESENT))
3356                 return true; /* native DP sink */
3357
3358         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3359                 return true; /* no per-port downstream info */
3360
3361         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3362                                     intel_dp->downstream_ports,
3363                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3364                 return false; /* downstream port status fetch failed */
3365
3366         return true;
3367 }
3368
3369 static void
3370 intel_dp_probe_oui(struct intel_dp *intel_dp)
3371 {
3372         u8 buf[3];
3373
3374         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3375                 return;
3376
3377         intel_edp_panel_vdd_on(intel_dp);
3378
3379         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3380                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3381                               buf[0], buf[1], buf[2]);
3382
3383         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3384                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385                               buf[0], buf[1], buf[2]);
3386
3387         edp_panel_vdd_off(intel_dp, false);
3388 }
3389
3390 static bool
3391 intel_dp_probe_mst(struct intel_dp *intel_dp)
3392 {
3393         u8 buf[1];
3394
3395         if (!intel_dp->can_mst)
3396                 return false;
3397
3398         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3399                 return false;
3400
3401         _edp_panel_vdd_on(intel_dp);
3402         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3403                 if (buf[0] & DP_MST_CAP) {
3404                         DRM_DEBUG_KMS("Sink is MST capable\n");
3405                         intel_dp->is_mst = true;
3406                 } else {
3407                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3408                         intel_dp->is_mst = false;
3409                 }
3410         }
3411         edp_panel_vdd_off(intel_dp, false);
3412
3413         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3414         return intel_dp->is_mst;
3415 }
3416
3417 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3418 {
3419         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3420         struct drm_device *dev = intel_dig_port->base.base.dev;
3421         struct intel_crtc *intel_crtc =
3422                 to_intel_crtc(intel_dig_port->base.base.crtc);
3423         u8 buf[1];
3424
3425         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3426                 return -EAGAIN;
3427
3428         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3429                 return -ENOTTY;
3430
3431         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3432                                DP_TEST_SINK_START) < 0)
3433                 return -EAGAIN;
3434
3435         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3436         intel_wait_for_vblank(dev, intel_crtc->pipe);
3437         intel_wait_for_vblank(dev, intel_crtc->pipe);
3438
3439         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3440                 return -EAGAIN;
3441
3442         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3443         return 0;
3444 }
3445
3446 static bool
3447 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3448 {
3449         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3450                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3451                                        sink_irq_vector, 1) == 1;
3452 }
3453
3454 static bool
3455 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3456 {
3457         int ret;
3458
3459         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3460                                              DP_SINK_COUNT_ESI,
3461                                              sink_irq_vector, 14);
3462         if (ret != 14)
3463                 return false;
3464
3465         return true;
3466 }
3467
3468 static void
3469 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3470 {
3471         /* NAK by default */
3472         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3473 }
3474
3475 static int
3476 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3477 {
3478         bool bret;
3479
3480         if (intel_dp->is_mst) {
3481                 u8 esi[16] = { 0 };
3482                 int ret = 0;
3483                 int retry;
3484                 bool handled;
3485                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3486 go_again:
3487                 if (bret == true) {
3488
3489                         /* check link status - esi[10] = 0x200c */
3490                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3491                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3492                                 intel_dp_start_link_train(intel_dp);
3493                                 intel_dp_complete_link_train(intel_dp);
3494                                 intel_dp_stop_link_train(intel_dp);
3495                         }
3496
3497                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3498                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3499
3500                         if (handled) {
3501                                 for (retry = 0; retry < 3; retry++) {
3502                                         int wret;
3503                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3504                                                                  DP_SINK_COUNT_ESI+1,
3505                                                                  &esi[1], 3);
3506                                         if (wret == 3) {
3507                                                 break;
3508                                         }
3509                                 }
3510
3511                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3512                                 if (bret == true) {
3513                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3514                                         goto go_again;
3515                                 }
3516                         } else
3517                                 ret = 0;
3518
3519                         return ret;
3520                 } else {
3521                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3522                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3523                         intel_dp->is_mst = false;
3524                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3525                         /* send a hotplug event */
3526                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3527                 }
3528         }
3529         return -EINVAL;
3530 }
3531
3532 /*
3533  * According to DP spec
3534  * 5.1.2:
3535  *  1. Read DPCD
3536  *  2. Configure link according to Receiver Capabilities
3537  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3538  *  4. Check link status on receipt of hot-plug interrupt
3539  */
3540 void
3541 intel_dp_check_link_status(struct intel_dp *intel_dp)
3542 {
3543         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3544         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3545         u8 sink_irq_vector;
3546         u8 link_status[DP_LINK_STATUS_SIZE];
3547
3548         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3549
3550         if (!intel_encoder->connectors_active)
3551                 return;
3552
3553         if (WARN_ON(!intel_encoder->base.crtc))
3554                 return;
3555
3556         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3557                 return;
3558
3559         /* Try to read receiver status if the link appears to be up */
3560         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3561                 return;
3562         }
3563
3564         /* Now read the DPCD to see if it's actually running */
3565         if (!intel_dp_get_dpcd(intel_dp)) {
3566                 return;
3567         }
3568
3569         /* Try to read the source of the interrupt */
3570         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3571             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3572                 /* Clear interrupt source */
3573                 drm_dp_dpcd_writeb(&intel_dp->aux,
3574                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3575                                    sink_irq_vector);
3576
3577                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3578                         intel_dp_handle_test_request(intel_dp);
3579                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3580                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3581         }
3582
3583         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3584                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3585                               intel_encoder->base.name);
3586                 intel_dp_start_link_train(intel_dp);
3587                 intel_dp_complete_link_train(intel_dp);
3588                 intel_dp_stop_link_train(intel_dp);
3589         }
3590 }
3591
3592 /* XXX this is probably wrong for multiple downstream ports */
3593 static enum drm_connector_status
3594 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3595 {
3596         uint8_t *dpcd = intel_dp->dpcd;
3597         uint8_t type;
3598
3599         if (!intel_dp_get_dpcd(intel_dp))
3600                 return connector_status_disconnected;
3601
3602         /* if there's no downstream port, we're done */
3603         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3604                 return connector_status_connected;
3605
3606         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3607         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3608             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3609                 uint8_t reg;
3610
3611                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3612                                             &reg, 1) < 0)
3613                         return connector_status_unknown;
3614
3615                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3616                                               : connector_status_disconnected;
3617         }
3618
3619         /* If no HPD, poke DDC gently */
3620         if (drm_probe_ddc(&intel_dp->aux.ddc))
3621                 return connector_status_connected;
3622
3623         /* Well we tried, say unknown for unreliable port types */
3624         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3625                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3626                 if (type == DP_DS_PORT_TYPE_VGA ||
3627                     type == DP_DS_PORT_TYPE_NON_EDID)
3628                         return connector_status_unknown;
3629         } else {
3630                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3631                         DP_DWN_STRM_PORT_TYPE_MASK;
3632                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3633                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3634                         return connector_status_unknown;
3635         }
3636
3637         /* Anything else is out of spec, warn and ignore */
3638         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3639         return connector_status_disconnected;
3640 }
3641
3642 static enum drm_connector_status
3643 ironlake_dp_detect(struct intel_dp *intel_dp)
3644 {
3645         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3648         enum drm_connector_status status;
3649
3650         /* Can't disconnect eDP, but you can close the lid... */
3651         if (is_edp(intel_dp)) {
3652                 status = intel_panel_detect(dev);
3653                 if (status == connector_status_unknown)
3654                         status = connector_status_connected;
3655                 return status;
3656         }
3657
3658         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3659                 return connector_status_disconnected;
3660
3661         return intel_dp_detect_dpcd(intel_dp);
3662 }
3663
3664 static enum drm_connector_status
3665 g4x_dp_detect(struct intel_dp *intel_dp)
3666 {
3667         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3670         uint32_t bit;
3671
3672         /* Can't disconnect eDP, but you can close the lid... */
3673         if (is_edp(intel_dp)) {
3674                 enum drm_connector_status status;
3675
3676                 status = intel_panel_detect(dev);
3677                 if (status == connector_status_unknown)
3678                         status = connector_status_connected;
3679                 return status;
3680         }
3681
3682         if (IS_VALLEYVIEW(dev)) {
3683                 switch (intel_dig_port->port) {
3684                 case PORT_B:
3685                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3686                         break;
3687                 case PORT_C:
3688                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3689                         break;
3690                 case PORT_D:
3691                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3692                         break;
3693                 default:
3694                         return connector_status_unknown;
3695                 }
3696         } else {
3697                 switch (intel_dig_port->port) {
3698                 case PORT_B:
3699                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3700                         break;
3701                 case PORT_C:
3702                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3703                         break;
3704                 case PORT_D:
3705                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3706                         break;
3707                 default:
3708                         return connector_status_unknown;
3709                 }
3710         }
3711
3712         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3713                 return connector_status_disconnected;
3714
3715         return intel_dp_detect_dpcd(intel_dp);
3716 }
3717
3718 static struct edid *
3719 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3720 {
3721         struct intel_connector *intel_connector = to_intel_connector(connector);
3722
3723         /* use cached edid if we have one */
3724         if (intel_connector->edid) {
3725                 /* invalid edid */
3726                 if (IS_ERR(intel_connector->edid))
3727                         return NULL;
3728
3729                 return drm_edid_duplicate(intel_connector->edid);
3730         }
3731
3732         return drm_get_edid(connector, adapter);
3733 }
3734
3735 static int
3736 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3737 {
3738         struct intel_connector *intel_connector = to_intel_connector(connector);
3739
3740         /* use cached edid if we have one */
3741         if (intel_connector->edid) {
3742                 /* invalid edid */
3743                 if (IS_ERR(intel_connector->edid))
3744                         return 0;
3745
3746                 return intel_connector_update_modes(connector,
3747                                                     intel_connector->edid);
3748         }
3749
3750         return intel_ddc_get_modes(connector, adapter);
3751 }
3752
3753 static enum drm_connector_status
3754 intel_dp_detect(struct drm_connector *connector, bool force)
3755 {
3756         struct intel_dp *intel_dp = intel_attached_dp(connector);
3757         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3758         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3759         struct drm_device *dev = connector->dev;
3760         struct drm_i915_private *dev_priv = dev->dev_private;
3761         enum drm_connector_status status;
3762         enum intel_display_power_domain power_domain;
3763         struct edid *edid = NULL;
3764         bool ret;
3765
3766         power_domain = intel_display_port_power_domain(intel_encoder);
3767         intel_display_power_get(dev_priv, power_domain);
3768
3769         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3770                       connector->base.id, connector->name);
3771
3772         if (intel_dp->is_mst) {
3773                 /* MST devices are disconnected from a monitor POV */
3774                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3775                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3776                 status = connector_status_disconnected;
3777                 goto out;
3778         }
3779
3780         intel_dp->has_audio = false;
3781
3782         if (HAS_PCH_SPLIT(dev))
3783                 status = ironlake_dp_detect(intel_dp);
3784         else
3785                 status = g4x_dp_detect(intel_dp);
3786
3787         if (status != connector_status_connected)
3788                 goto out;
3789
3790         intel_dp_probe_oui(intel_dp);
3791
3792         ret = intel_dp_probe_mst(intel_dp);
3793         if (ret) {
3794                 /* if we are in MST mode then this connector
3795                    won't appear connected or have anything with EDID on it */
3796                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3797                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3798                 status = connector_status_disconnected;
3799                 goto out;
3800         }
3801
3802         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3803                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3804         } else {
3805                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3806                 if (edid) {
3807                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3808                         kfree(edid);
3809                 }
3810         }
3811
3812         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3813                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3814         status = connector_status_connected;
3815
3816 out:
3817         intel_display_power_put(dev_priv, power_domain);
3818         return status;
3819 }
3820
3821 static int intel_dp_get_modes(struct drm_connector *connector)
3822 {
3823         struct intel_dp *intel_dp = intel_attached_dp(connector);
3824         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3825         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3826         struct intel_connector *intel_connector = to_intel_connector(connector);
3827         struct drm_device *dev = connector->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         enum intel_display_power_domain power_domain;
3830         int ret;
3831
3832         /* We should parse the EDID data and find out if it has an audio sink
3833          */
3834
3835         power_domain = intel_display_port_power_domain(intel_encoder);
3836         intel_display_power_get(dev_priv, power_domain);
3837
3838         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3839         intel_display_power_put(dev_priv, power_domain);
3840         if (ret)
3841                 return ret;
3842
3843         /* if eDP has no EDID, fall back to fixed mode */
3844         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3845                 struct drm_display_mode *mode;
3846                 mode = drm_mode_duplicate(dev,
3847                                           intel_connector->panel.fixed_mode);
3848                 if (mode) {
3849                         drm_mode_probed_add(connector, mode);
3850                         return 1;
3851                 }
3852         }
3853         return 0;
3854 }
3855
3856 static bool
3857 intel_dp_detect_audio(struct drm_connector *connector)
3858 {
3859         struct intel_dp *intel_dp = intel_attached_dp(connector);
3860         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3861         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3862         struct drm_device *dev = connector->dev;
3863         struct drm_i915_private *dev_priv = dev->dev_private;
3864         enum intel_display_power_domain power_domain;
3865         struct edid *edid;
3866         bool has_audio = false;
3867
3868         power_domain = intel_display_port_power_domain(intel_encoder);
3869         intel_display_power_get(dev_priv, power_domain);
3870
3871         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3872         if (edid) {
3873                 has_audio = drm_detect_monitor_audio(edid);
3874                 kfree(edid);
3875         }
3876
3877         intel_display_power_put(dev_priv, power_domain);
3878
3879         return has_audio;
3880 }
3881
3882 static int
3883 intel_dp_set_property(struct drm_connector *connector,
3884                       struct drm_property *property,
3885                       uint64_t val)
3886 {
3887         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3888         struct intel_connector *intel_connector = to_intel_connector(connector);
3889         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3890         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3891         int ret;
3892
3893         ret = drm_object_property_set_value(&connector->base, property, val);
3894         if (ret)
3895                 return ret;
3896
3897         if (property == dev_priv->force_audio_property) {
3898                 int i = val;
3899                 bool has_audio;
3900
3901                 if (i == intel_dp->force_audio)
3902                         return 0;
3903
3904                 intel_dp->force_audio = i;
3905
3906                 if (i == HDMI_AUDIO_AUTO)
3907                         has_audio = intel_dp_detect_audio(connector);
3908                 else
3909                         has_audio = (i == HDMI_AUDIO_ON);
3910
3911                 if (has_audio == intel_dp->has_audio)
3912                         return 0;
3913
3914                 intel_dp->has_audio = has_audio;
3915                 goto done;
3916         }
3917
3918         if (property == dev_priv->broadcast_rgb_property) {
3919                 bool old_auto = intel_dp->color_range_auto;
3920                 uint32_t old_range = intel_dp->color_range;
3921
3922                 switch (val) {
3923                 case INTEL_BROADCAST_RGB_AUTO:
3924                         intel_dp->color_range_auto = true;
3925                         break;
3926                 case INTEL_BROADCAST_RGB_FULL:
3927                         intel_dp->color_range_auto = false;
3928                         intel_dp->color_range = 0;
3929                         break;
3930                 case INTEL_BROADCAST_RGB_LIMITED:
3931                         intel_dp->color_range_auto = false;
3932                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3933                         break;
3934                 default:
3935                         return -EINVAL;
3936                 }
3937
3938                 if (old_auto == intel_dp->color_range_auto &&
3939                     old_range == intel_dp->color_range)
3940                         return 0;
3941
3942                 goto done;
3943         }
3944
3945         if (is_edp(intel_dp) &&
3946             property == connector->dev->mode_config.scaling_mode_property) {
3947                 if (val == DRM_MODE_SCALE_NONE) {
3948                         DRM_DEBUG_KMS("no scaling not supported\n");
3949                         return -EINVAL;
3950                 }
3951
3952                 if (intel_connector->panel.fitting_mode == val) {
3953                         /* the eDP scaling property is not changed */
3954                         return 0;
3955                 }
3956                 intel_connector->panel.fitting_mode = val;
3957
3958                 goto done;
3959         }
3960
3961         return -EINVAL;
3962
3963 done:
3964         if (intel_encoder->base.crtc)
3965                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3966
3967         return 0;
3968 }
3969
3970 static void
3971 intel_dp_connector_destroy(struct drm_connector *connector)
3972 {
3973         struct intel_connector *intel_connector = to_intel_connector(connector);
3974
3975         if (!IS_ERR_OR_NULL(intel_connector->edid))
3976                 kfree(intel_connector->edid);
3977
3978         /* Can't call is_edp() since the encoder may have been destroyed
3979          * already. */
3980         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3981                 intel_panel_fini(&intel_connector->panel);
3982
3983         drm_connector_cleanup(connector);
3984         kfree(connector);
3985 }
3986
3987 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3988 {
3989         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3990         struct intel_dp *intel_dp = &intel_dig_port->dp;
3991         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3992
3993         drm_dp_aux_unregister(&intel_dp->aux);
3994         intel_dp_mst_encoder_cleanup(intel_dig_port);
3995         drm_encoder_cleanup(encoder);
3996         if (is_edp(intel_dp)) {
3997                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3998                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3999                 edp_panel_vdd_off_sync(intel_dp);
4000                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4001                 if (intel_dp->edp_notifier.notifier_call) {
4002                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4003                         intel_dp->edp_notifier.notifier_call = NULL;
4004                 }
4005         }
4006         kfree(intel_dig_port);
4007 }
4008
4009 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4010 {
4011         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4012
4013         if (!is_edp(intel_dp))
4014                 return;
4015
4016         edp_panel_vdd_off_sync(intel_dp);
4017 }
4018
4019 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4020 {
4021         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4022 }
4023
4024 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4025         .dpms = intel_connector_dpms,
4026         .detect = intel_dp_detect,
4027         .fill_modes = drm_helper_probe_single_connector_modes,
4028         .set_property = intel_dp_set_property,
4029         .destroy = intel_dp_connector_destroy,
4030 };
4031
4032 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4033         .get_modes = intel_dp_get_modes,
4034         .mode_valid = intel_dp_mode_valid,
4035         .best_encoder = intel_best_encoder,
4036 };
4037
4038 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4039         .reset = intel_dp_encoder_reset,
4040         .destroy = intel_dp_encoder_destroy,
4041 };
4042
4043 void
4044 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4045 {
4046         return;
4047 }
4048
4049 bool
4050 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4051 {
4052         struct intel_dp *intel_dp = &intel_dig_port->dp;
4053         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4054         struct drm_device *dev = intel_dig_port->base.base.dev;
4055         struct drm_i915_private *dev_priv = dev->dev_private;
4056         enum intel_display_power_domain power_domain;
4057         bool ret = true;
4058
4059         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4060                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4061
4062         DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4063                       long_hpd ? "long" : "short");
4064
4065         power_domain = intel_display_port_power_domain(intel_encoder);
4066         intel_display_power_get(dev_priv, power_domain);
4067
4068         if (long_hpd) {
4069                 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4070                         goto mst_fail;
4071
4072                 if (!intel_dp_get_dpcd(intel_dp)) {
4073                         goto mst_fail;
4074                 }
4075
4076                 intel_dp_probe_oui(intel_dp);
4077
4078                 if (!intel_dp_probe_mst(intel_dp))
4079                         goto mst_fail;
4080
4081         } else {
4082                 if (intel_dp->is_mst) {
4083                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4084                                 goto mst_fail;
4085                 }
4086
4087                 if (!intel_dp->is_mst) {
4088                         /*
4089                          * we'll check the link status via the normal hot plug path later -
4090                          * but for short hpds we should check it now
4091                          */
4092                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4093                         intel_dp_check_link_status(intel_dp);
4094                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4095                 }
4096         }
4097         ret = false;
4098         goto put_power;
4099 mst_fail:
4100         /* if we were in MST mode, and device is not there get out of MST mode */
4101         if (intel_dp->is_mst) {
4102                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4103                 intel_dp->is_mst = false;
4104                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4105         }
4106 put_power:
4107         intel_display_power_put(dev_priv, power_domain);
4108
4109         return ret;
4110 }
4111
4112 /* Return which DP Port should be selected for Transcoder DP control */
4113 int
4114 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct intel_encoder *intel_encoder;
4118         struct intel_dp *intel_dp;
4119
4120         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4121                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4122
4123                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4124                     intel_encoder->type == INTEL_OUTPUT_EDP)
4125                         return intel_dp->output_reg;
4126         }
4127
4128         return -1;
4129 }
4130
4131 /* check the VBT to see whether the eDP is on DP-D port */
4132 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4133 {
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         union child_device_config *p_child;
4136         int i;
4137         static const short port_mapping[] = {
4138                 [PORT_B] = PORT_IDPB,
4139                 [PORT_C] = PORT_IDPC,
4140                 [PORT_D] = PORT_IDPD,
4141         };
4142
4143         if (port == PORT_A)
4144                 return true;
4145
4146         if (!dev_priv->vbt.child_dev_num)
4147                 return false;
4148
4149         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4150                 p_child = dev_priv->vbt.child_dev + i;
4151
4152                 if (p_child->common.dvo_port == port_mapping[port] &&
4153                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4154                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4155                         return true;
4156         }
4157         return false;
4158 }
4159
4160 void
4161 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4162 {
4163         struct intel_connector *intel_connector = to_intel_connector(connector);
4164
4165         intel_attach_force_audio_property(connector);
4166         intel_attach_broadcast_rgb_property(connector);
4167         intel_dp->color_range_auto = true;
4168
4169         if (is_edp(intel_dp)) {
4170                 drm_mode_create_scaling_mode_property(connector->dev);
4171                 drm_object_attach_property(
4172                         &connector->base,
4173                         connector->dev->mode_config.scaling_mode_property,
4174                         DRM_MODE_SCALE_ASPECT);
4175                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4176         }
4177 }
4178
4179 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4180 {
4181         intel_dp->last_power_cycle = jiffies;
4182         intel_dp->last_power_on = jiffies;
4183         intel_dp->last_backlight_off = jiffies;
4184 }
4185
4186 static void
4187 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4188                                     struct intel_dp *intel_dp,
4189                                     struct edp_power_seq *out)
4190 {
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         struct edp_power_seq cur, vbt, spec, final;
4193         u32 pp_on, pp_off, pp_div, pp;
4194         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4195
4196         if (HAS_PCH_SPLIT(dev)) {
4197                 pp_ctrl_reg = PCH_PP_CONTROL;
4198                 pp_on_reg = PCH_PP_ON_DELAYS;
4199                 pp_off_reg = PCH_PP_OFF_DELAYS;
4200                 pp_div_reg = PCH_PP_DIVISOR;
4201         } else {
4202                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4203
4204                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4205                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4206                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4207                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4208         }
4209
4210         /* Workaround: Need to write PP_CONTROL with the unlock key as
4211          * the very first thing. */
4212         pp = ironlake_get_pp_control(intel_dp);
4213         I915_WRITE(pp_ctrl_reg, pp);
4214
4215         pp_on = I915_READ(pp_on_reg);
4216         pp_off = I915_READ(pp_off_reg);
4217         pp_div = I915_READ(pp_div_reg);
4218
4219         /* Pull timing values out of registers */
4220         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4221                 PANEL_POWER_UP_DELAY_SHIFT;
4222
4223         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4224                 PANEL_LIGHT_ON_DELAY_SHIFT;
4225
4226         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4227                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4228
4229         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4230                 PANEL_POWER_DOWN_DELAY_SHIFT;
4231
4232         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4233                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4234
4235         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4236                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4237
4238         vbt = dev_priv->vbt.edp_pps;
4239
4240         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4241          * our hw here, which are all in 100usec. */
4242         spec.t1_t3 = 210 * 10;
4243         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4244         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4245         spec.t10 = 500 * 10;
4246         /* This one is special and actually in units of 100ms, but zero
4247          * based in the hw (so we need to add 100 ms). But the sw vbt
4248          * table multiplies it with 1000 to make it in units of 100usec,
4249          * too. */
4250         spec.t11_t12 = (510 + 100) * 10;
4251
4252         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4253                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4254
4255         /* Use the max of the register settings and vbt. If both are
4256          * unset, fall back to the spec limits. */
4257 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4258                                        spec.field : \
4259                                        max(cur.field, vbt.field))
4260         assign_final(t1_t3);
4261         assign_final(t8);
4262         assign_final(t9);
4263         assign_final(t10);
4264         assign_final(t11_t12);
4265 #undef assign_final
4266
4267 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4268         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4269         intel_dp->backlight_on_delay = get_delay(t8);
4270         intel_dp->backlight_off_delay = get_delay(t9);
4271         intel_dp->panel_power_down_delay = get_delay(t10);
4272         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4273 #undef get_delay
4274
4275         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4276                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4277                       intel_dp->panel_power_cycle_delay);
4278
4279         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4280                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4281
4282         if (out)
4283                 *out = final;
4284 }
4285
4286 static void
4287 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4288                                               struct intel_dp *intel_dp,
4289                                               struct edp_power_seq *seq)
4290 {
4291         struct drm_i915_private *dev_priv = dev->dev_private;
4292         u32 pp_on, pp_off, pp_div, port_sel = 0;
4293         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4294         int pp_on_reg, pp_off_reg, pp_div_reg;
4295
4296         if (HAS_PCH_SPLIT(dev)) {
4297                 pp_on_reg = PCH_PP_ON_DELAYS;
4298                 pp_off_reg = PCH_PP_OFF_DELAYS;
4299                 pp_div_reg = PCH_PP_DIVISOR;
4300         } else {
4301                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4302
4303                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4304                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4305                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4306         }
4307
4308         /*
4309          * And finally store the new values in the power sequencer. The
4310          * backlight delays are set to 1 because we do manual waits on them. For
4311          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4312          * we'll end up waiting for the backlight off delay twice: once when we
4313          * do the manual sleep, and once when we disable the panel and wait for
4314          * the PP_STATUS bit to become zero.
4315          */
4316         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4317                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4318         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4319                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4320         /* Compute the divisor for the pp clock, simply match the Bspec
4321          * formula. */
4322         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4323         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4324                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4325
4326         /* Haswell doesn't have any port selection bits for the panel
4327          * power sequencer any more. */
4328         if (IS_VALLEYVIEW(dev)) {
4329                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4330                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
4331                 else
4332                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
4333         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4334                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4335                         port_sel = PANEL_PORT_SELECT_DPA;
4336                 else
4337                         port_sel = PANEL_PORT_SELECT_DPD;
4338         }
4339
4340         pp_on |= port_sel;
4341
4342         I915_WRITE(pp_on_reg, pp_on);
4343         I915_WRITE(pp_off_reg, pp_off);
4344         I915_WRITE(pp_div_reg, pp_div);
4345
4346         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4347                       I915_READ(pp_on_reg),
4348                       I915_READ(pp_off_reg),
4349                       I915_READ(pp_div_reg));
4350 }
4351
4352 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4353 {
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         struct intel_encoder *encoder;
4356         struct intel_dp *intel_dp = NULL;
4357         struct intel_crtc_config *config = NULL;
4358         struct intel_crtc *intel_crtc = NULL;
4359         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4360         u32 reg, val;
4361         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4362
4363         if (refresh_rate <= 0) {
4364                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4365                 return;
4366         }
4367
4368         if (intel_connector == NULL) {
4369                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4370                 return;
4371         }
4372
4373         /*
4374          * FIXME: This needs proper synchronization with psr state. But really
4375          * hard to tell without seeing the user of this function of this code.
4376          * Check locking and ordering once that lands.
4377          */
4378         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4379                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4380                 return;
4381         }
4382
4383         encoder = intel_attached_encoder(&intel_connector->base);
4384         intel_dp = enc_to_intel_dp(&encoder->base);
4385         intel_crtc = encoder->new_crtc;
4386
4387         if (!intel_crtc) {
4388                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4389                 return;
4390         }
4391
4392         config = &intel_crtc->config;
4393
4394         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4395                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4396                 return;
4397         }
4398
4399         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4400                 index = DRRS_LOW_RR;
4401
4402         if (index == intel_dp->drrs_state.refresh_rate_type) {
4403                 DRM_DEBUG_KMS(
4404                         "DRRS requested for previously set RR...ignoring\n");
4405                 return;
4406         }
4407
4408         if (!intel_crtc->active) {
4409                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4410                 return;
4411         }
4412
4413         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4414                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4415                 val = I915_READ(reg);
4416                 if (index > DRRS_HIGH_RR) {
4417                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4418                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4419                 } else {
4420                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4421                 }
4422                 I915_WRITE(reg, val);
4423         }
4424
4425         /*
4426          * mutex taken to ensure that there is no race between differnt
4427          * drrs calls trying to update refresh rate. This scenario may occur
4428          * in future when idleness detection based DRRS in kernel and
4429          * possible calls from user space to set differnt RR are made.
4430          */
4431
4432         mutex_lock(&intel_dp->drrs_state.mutex);
4433
4434         intel_dp->drrs_state.refresh_rate_type = index;
4435
4436         mutex_unlock(&intel_dp->drrs_state.mutex);
4437
4438         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4439 }
4440
4441 static struct drm_display_mode *
4442 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4443                         struct intel_connector *intel_connector,
4444                         struct drm_display_mode *fixed_mode)
4445 {
4446         struct drm_connector *connector = &intel_connector->base;
4447         struct intel_dp *intel_dp = &intel_dig_port->dp;
4448         struct drm_device *dev = intel_dig_port->base.base.dev;
4449         struct drm_i915_private *dev_priv = dev->dev_private;
4450         struct drm_display_mode *downclock_mode = NULL;
4451
4452         if (INTEL_INFO(dev)->gen <= 6) {
4453                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4454                 return NULL;
4455         }
4456
4457         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4458                 DRM_INFO("VBT doesn't support DRRS\n");
4459                 return NULL;
4460         }
4461
4462         downclock_mode = intel_find_panel_downclock
4463                                         (dev, fixed_mode, connector);
4464
4465         if (!downclock_mode) {
4466                 DRM_INFO("DRRS not supported\n");
4467                 return NULL;
4468         }
4469
4470         dev_priv->drrs.connector = intel_connector;
4471
4472         mutex_init(&intel_dp->drrs_state.mutex);
4473
4474         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4475
4476         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4477         DRM_INFO("seamless DRRS supported for eDP panel.\n");
4478         return downclock_mode;
4479 }
4480
4481 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4482 {
4483         struct drm_device *dev = intel_encoder->base.dev;
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485         struct intel_dp *intel_dp;
4486         enum intel_display_power_domain power_domain;
4487
4488         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4489                 return;
4490
4491         intel_dp = enc_to_intel_dp(&intel_encoder->base);
4492         if (!edp_have_panel_vdd(intel_dp))
4493                 return;
4494         /*
4495          * The VDD bit needs a power domain reference, so if the bit is
4496          * already enabled when we boot or resume, grab this reference and
4497          * schedule a vdd off, so we don't hold on to the reference
4498          * indefinitely.
4499          */
4500         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4501         power_domain = intel_display_port_power_domain(intel_encoder);
4502         intel_display_power_get(dev_priv, power_domain);
4503
4504         edp_panel_vdd_schedule_off(intel_dp);
4505 }
4506
4507 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4508                                      struct intel_connector *intel_connector,
4509                                      struct edp_power_seq *power_seq)
4510 {
4511         struct drm_connector *connector = &intel_connector->base;
4512         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4513         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4514         struct drm_device *dev = intel_encoder->base.dev;
4515         struct drm_i915_private *dev_priv = dev->dev_private;
4516         struct drm_display_mode *fixed_mode = NULL;
4517         struct drm_display_mode *downclock_mode = NULL;
4518         bool has_dpcd;
4519         struct drm_display_mode *scan;
4520         struct edid *edid;
4521
4522         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4523
4524         if (!is_edp(intel_dp))
4525                 return true;
4526
4527         intel_edp_panel_vdd_sanitize(intel_encoder);
4528
4529         /* Cache DPCD and EDID for edp. */
4530         intel_edp_panel_vdd_on(intel_dp);
4531         has_dpcd = intel_dp_get_dpcd(intel_dp);
4532         edp_panel_vdd_off(intel_dp, false);
4533
4534         if (has_dpcd) {
4535                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4536                         dev_priv->no_aux_handshake =
4537                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4538                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4539         } else {
4540                 /* if this fails, presume the device is a ghost */
4541                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4542                 return false;
4543         }
4544
4545         /* We now know it's not a ghost, init power sequence regs. */
4546         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4547
4548         mutex_lock(&dev->mode_config.mutex);
4549         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4550         if (edid) {
4551                 if (drm_add_edid_modes(connector, edid)) {
4552                         drm_mode_connector_update_edid_property(connector,
4553                                                                 edid);
4554                         drm_edid_to_eld(connector, edid);
4555                 } else {
4556                         kfree(edid);
4557                         edid = ERR_PTR(-EINVAL);
4558                 }
4559         } else {
4560                 edid = ERR_PTR(-ENOENT);
4561         }
4562         intel_connector->edid = edid;
4563
4564         /* prefer fixed mode from EDID if available */
4565         list_for_each_entry(scan, &connector->probed_modes, head) {
4566                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4567                         fixed_mode = drm_mode_duplicate(dev, scan);
4568                         downclock_mode = intel_dp_drrs_init(
4569                                                 intel_dig_port,
4570                                                 intel_connector, fixed_mode);
4571                         break;
4572                 }
4573         }
4574
4575         /* fallback to VBT if available for eDP */
4576         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4577                 fixed_mode = drm_mode_duplicate(dev,
4578                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4579                 if (fixed_mode)
4580                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4581         }
4582         mutex_unlock(&dev->mode_config.mutex);
4583
4584         if (IS_VALLEYVIEW(dev)) {
4585                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4586                 register_reboot_notifier(&intel_dp->edp_notifier);
4587         }
4588
4589         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4590         intel_panel_setup_backlight(connector);
4591
4592         return true;
4593 }
4594
4595 bool
4596 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4597                         struct intel_connector *intel_connector)
4598 {
4599         struct drm_connector *connector = &intel_connector->base;
4600         struct intel_dp *intel_dp = &intel_dig_port->dp;
4601         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4602         struct drm_device *dev = intel_encoder->base.dev;
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         enum port port = intel_dig_port->port;
4605         struct edp_power_seq power_seq = { 0 };
4606         int type;
4607
4608         /* intel_dp vfuncs */
4609         if (IS_VALLEYVIEW(dev))
4610                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4611         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4612                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4613         else if (HAS_PCH_SPLIT(dev))
4614                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4615         else
4616                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4617
4618         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4619
4620         /* Preserve the current hw state. */
4621         intel_dp->DP = I915_READ(intel_dp->output_reg);
4622         intel_dp->attached_connector = intel_connector;
4623
4624         if (intel_dp_is_edp(dev, port))
4625                 type = DRM_MODE_CONNECTOR_eDP;
4626         else
4627                 type = DRM_MODE_CONNECTOR_DisplayPort;
4628
4629         /*
4630          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4631          * for DP the encoder type can be set by the caller to
4632          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4633          */
4634         if (type == DRM_MODE_CONNECTOR_eDP)
4635                 intel_encoder->type = INTEL_OUTPUT_EDP;
4636
4637         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4638                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4639                         port_name(port));
4640
4641         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4642         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4643
4644         connector->interlace_allowed = true;
4645         connector->doublescan_allowed = 0;
4646
4647         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4648                           edp_panel_vdd_work);
4649
4650         intel_connector_attach_encoder(intel_connector, intel_encoder);
4651         drm_connector_register(connector);
4652
4653         if (HAS_DDI(dev))
4654                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4655         else
4656                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4657         intel_connector->unregister = intel_dp_connector_unregister;
4658
4659         /* Set up the hotplug pin. */
4660         switch (port) {
4661         case PORT_A:
4662                 intel_encoder->hpd_pin = HPD_PORT_A;
4663                 break;
4664         case PORT_B:
4665                 intel_encoder->hpd_pin = HPD_PORT_B;
4666                 break;
4667         case PORT_C:
4668                 intel_encoder->hpd_pin = HPD_PORT_C;
4669                 break;
4670         case PORT_D:
4671                 intel_encoder->hpd_pin = HPD_PORT_D;
4672                 break;
4673         default:
4674                 BUG();
4675         }
4676
4677         if (is_edp(intel_dp)) {
4678                 intel_dp_init_panel_power_timestamps(intel_dp);
4679                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4680         }
4681
4682         intel_dp_aux_init(intel_dp, intel_connector);
4683
4684         /* init MST on ports that can support it */
4685         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4686                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4687                         intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4688                 }
4689         }
4690
4691         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4692                 drm_dp_aux_unregister(&intel_dp->aux);
4693                 if (is_edp(intel_dp)) {
4694                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4695                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4696                         edp_panel_vdd_off_sync(intel_dp);
4697                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4698                 }
4699                 drm_connector_unregister(connector);
4700                 drm_connector_cleanup(connector);
4701                 return false;
4702         }
4703
4704         intel_dp_add_properties(intel_dp, connector);
4705
4706         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4707          * 0xd.  Failure to do so will result in spurious interrupts being
4708          * generated on the port when a cable is not attached.
4709          */
4710         if (IS_G4X(dev) && !IS_GM45(dev)) {
4711                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4712                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4713         }
4714
4715         return true;
4716 }
4717
4718 void
4719 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4720 {
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         struct intel_digital_port *intel_dig_port;
4723         struct intel_encoder *intel_encoder;
4724         struct drm_encoder *encoder;
4725         struct intel_connector *intel_connector;
4726
4727         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4728         if (!intel_dig_port)
4729                 return;
4730
4731         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4732         if (!intel_connector) {
4733                 kfree(intel_dig_port);
4734                 return;
4735         }
4736
4737         intel_encoder = &intel_dig_port->base;
4738         encoder = &intel_encoder->base;
4739
4740         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4741                          DRM_MODE_ENCODER_TMDS);
4742
4743         intel_encoder->compute_config = intel_dp_compute_config;
4744         intel_encoder->disable = intel_disable_dp;
4745         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4746         intel_encoder->get_config = intel_dp_get_config;
4747         intel_encoder->suspend = intel_dp_encoder_suspend;
4748         if (IS_CHERRYVIEW(dev)) {
4749                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4750                 intel_encoder->pre_enable = chv_pre_enable_dp;
4751                 intel_encoder->enable = vlv_enable_dp;
4752                 intel_encoder->post_disable = chv_post_disable_dp;
4753         } else if (IS_VALLEYVIEW(dev)) {
4754                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4755                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4756                 intel_encoder->enable = vlv_enable_dp;
4757                 intel_encoder->post_disable = vlv_post_disable_dp;
4758         } else {
4759                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4760                 intel_encoder->enable = g4x_enable_dp;
4761                 intel_encoder->post_disable = g4x_post_disable_dp;
4762         }
4763
4764         intel_dig_port->port = port;
4765         intel_dig_port->dp.output_reg = output_reg;
4766
4767         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4768         if (IS_CHERRYVIEW(dev)) {
4769                 if (port == PORT_D)
4770                         intel_encoder->crtc_mask = 1 << 2;
4771                 else
4772                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4773         } else {
4774                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4775         }
4776         intel_encoder->cloneable = 0;
4777         intel_encoder->hot_plug = intel_dp_hot_plug;
4778
4779         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4780         dev_priv->hpd_irq_port[port] = intel_dig_port;
4781
4782         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4783                 drm_encoder_cleanup(encoder);
4784                 kfree(intel_dig_port);
4785                 kfree(intel_connector);
4786         }
4787 }
4788
4789 void intel_dp_mst_suspend(struct drm_device *dev)
4790 {
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         int i;
4793
4794         /* disable MST */
4795         for (i = 0; i < I915_MAX_PORTS; i++) {
4796                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4797                 if (!intel_dig_port)
4798                         continue;
4799
4800                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4801                         if (!intel_dig_port->dp.can_mst)
4802                                 continue;
4803                         if (intel_dig_port->dp.is_mst)
4804                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4805                 }
4806         }
4807 }
4808
4809 void intel_dp_mst_resume(struct drm_device *dev)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812         int i;
4813
4814         for (i = 0; i < I915_MAX_PORTS; i++) {
4815                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4816                 if (!intel_dig_port)
4817                         continue;
4818                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4819                         int ret;
4820
4821                         if (!intel_dig_port->dp.can_mst)
4822                                 continue;
4823
4824                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4825                         if (ret != 0) {
4826                                 intel_dp_check_mst_status(&intel_dig_port->dp);
4827                         }
4828                 }
4829         }
4830 }