drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
  95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  96
  97 static int
  98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  99 {
 100         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 101         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 102
 103         switch (max_link_bw) {
 104         case DP_LINK_BW_1_62:
 105         case DP_LINK_BW_2_7:
 106                 break;
 107         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 108                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 109                      INTEL_INFO(dev)->gen >= 8) &&
 110                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 111                         max_link_bw = DP_LINK_BW_5_4;
 112                 else
 113                         max_link_bw = DP_LINK_BW_2_7;
 114                 break;
 115         default:
 116                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 117                      max_link_bw);
 118                 max_link_bw = DP_LINK_BW_1_62;
 119                 break;
 120         }
 121         return max_link_bw;
 122 }
 123
 124 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 125 {
 126         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 127         struct drm_device *dev = intel_dig_port->base.base.dev;
 128         u8 source_max, sink_max;
 129
 130         source_max = 4;
 131         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 132             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 133                 source_max = 2;
 134
 135         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 136
 137         return min(source_max, sink_max);
 138 }
 139
 140 /*
 141  * The units on the numbers in the next two are... bizarre.  Examples will
 142  * make it clearer; this one parallels an example in the eDP spec.
 143  *
 144  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 145  *
 146  *     270000 * 1 * 8 / 10 == 216000
 147  *
 148  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 149  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 150  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 151  * 119000.  At 18bpp that's 2142000 kilobits per second.
 152  *
 153  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 154  * get the result in decakilobits instead of kilobits.
 155  */
 156
 157 static int
 158 intel_dp_link_required(int pixel_clock, int bpp)
 159 {
 160         return (pixel_clock * bpp + 9) / 10;
 161 }
 162
 163 static int
 164 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 165 {
 166         return (max_link_clock * max_lanes * 8) / 10;
 167 }
 168
 169 static enum drm_mode_status
 170 intel_dp_mode_valid(struct drm_connector *connector,
 171                     struct drm_display_mode *mode)
 172 {
 173         struct intel_dp *intel_dp = intel_attached_dp(connector);
 174         struct intel_connector *intel_connector = to_intel_connector(connector);
 175         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 176         int target_clock = mode->clock;
 177         int max_rate, mode_rate, max_lanes, max_link_clock;
 178
 179         if (is_edp(intel_dp) && fixed_mode) {
 180                 if (mode->hdisplay > fixed_mode->hdisplay)
 181                         return MODE_PANEL;
 182
 183                 if (mode->vdisplay > fixed_mode->vdisplay)
 184                         return MODE_PANEL;
 185
 186                 target_clock = fixed_mode->clock;
 187         }
 188
 189         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 190         max_lanes = intel_dp_max_lane_count(intel_dp);
 191
 192         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 193         mode_rate = intel_dp_link_required(target_clock, 18);
 194
 195         if (mode_rate > max_rate)
 196                 return MODE_CLOCK_HIGH;
 197
 198         if (mode->clock < 10000)
 199                 return MODE_CLOCK_LOW;
 200
 201         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 202                 return MODE_H_ILLEGAL;
 203
 204         return MODE_OK;
 205 }
 206
 207 static uint32_t
 208 pack_aux(uint8_t *src, int src_bytes)
 209 {
 210         int     i;
 211         uint32_t v = 0;
 212
 213         if (src_bytes > 4)
 214                 src_bytes = 4;
 215         for (i = 0; i < src_bytes; i++)
 216                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 217         return v;
 218 }
 219
 220 static void
 221 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 222 {
 223         int i;
 224         if (dst_bytes > 4)
 225                 dst_bytes = 4;
 226         for (i = 0; i < dst_bytes; i++)
 227                 dst[i] = src >> ((3-i) * 8);
 228 }
 229
 230 /* hrawclock is 1/4 the FSB frequency */
 231 static int
 232 intel_hrawclk(struct drm_device *dev)
 233 {
 234         struct drm_i915_private *dev_priv = dev->dev_private;
 235         uint32_t clkcfg;
 236
 237         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 238         if (IS_VALLEYVIEW(dev))
 239                 return 200;
 240
 241         clkcfg = I915_READ(CLKCFG);
 242         switch (clkcfg & CLKCFG_FSB_MASK) {
 243         case CLKCFG_FSB_400:
 244                 return 100;
 245         case CLKCFG_FSB_533:
 246                 return 133;
 247         case CLKCFG_FSB_667:
 248                 return 166;
 249         case CLKCFG_FSB_800:
 250                 return 200;
 251         case CLKCFG_FSB_1067:
 252                 return 266;
 253         case CLKCFG_FSB_1333:
 254                 return 333;
 255         /* these two are just a guess; one of them might be right */
 256         case CLKCFG_FSB_1600:
 257         case CLKCFG_FSB_1600_ALT:
 258                 return 400;
 259         default:
 260                 return 133;
 261         }
 262 }
 263
 264 static void
 265 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 266                                     struct intel_dp *intel_dp,
 267                                     struct edp_power_seq *out);
 268 static void
 269 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 270                                               struct intel_dp *intel_dp,
 271                                               struct edp_power_seq *out);
 272
 273 static enum pipe
 274 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 275 {
 276         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 277         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 278         struct drm_device *dev = intel_dig_port->base.base.dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         enum port port = intel_dig_port->port;
 281         enum pipe pipe;
 282
 283         /* modeset should have pipe */
 284         if (crtc)
 285                 return to_intel_crtc(crtc)->pipe;
 286
 287         /* init time, try to find a pipe with this port selected */
 288         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 289                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 290                         PANEL_PORT_SELECT_MASK;
 291                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 292                         return pipe;
 293                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 294                         return pipe;
 295         }
 296
 297         /* shrug */
 298         return PIPE_A;
 299 }
 300
 301 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 304
 305         if (HAS_PCH_SPLIT(dev))
 306                 return PCH_PP_CONTROL;
 307         else
 308                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 309 }
 310
 311 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 312 {
 313         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 314
 315         if (HAS_PCH_SPLIT(dev))
 316                 return PCH_PP_STATUS;
 317         else
 318                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 319 }
 320
 321 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 322 {
 323         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325
 326         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 327 }
 328
 329 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 330 {
 331         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         return !dev_priv->pm.suspended &&
 335                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 336 }
 337
 338 static void
 339 intel_dp_check_edp(struct intel_dp *intel_dp)
 340 {
 341         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 342         struct drm_i915_private *dev_priv = dev->dev_private;
 343
 344         if (!is_edp(intel_dp))
 345                 return;
 346
 347         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 348                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 349                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 350                               I915_READ(_pp_stat_reg(intel_dp)),
 351                               I915_READ(_pp_ctrl_reg(intel_dp)));
 352         }
 353 }
 354
 355 static uint32_t
 356 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 357 {
 358         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 359         struct drm_device *dev = intel_dig_port->base.base.dev;
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 362         uint32_t status;
 363         bool done;
 364
 365 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 366         if (has_aux_irq)
 367                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 368                                           msecs_to_jiffies_timeout(10));
 369         else
 370                 done = wait_for_atomic(C, 10) == 0;
 371         if (!done)
 372                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 373                           has_aux_irq);
 374 #undef C
 375
 376         return status;
 377 }
 378
 379 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 380 {
 381         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 382         struct drm_device *dev = intel_dig_port->base.base.dev;
 383
 384         /*
 385          * The clock divider is based off the hrawclk, and would like to run at
 386          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 387          */
 388         return index ? 0 : intel_hrawclk(dev) / 2;
 389 }
 390
 391 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 392 {
 393         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 394         struct drm_device *dev = intel_dig_port->base.base.dev;
 395
 396         if (index)
 397                 return 0;
 398
 399         if (intel_dig_port->port == PORT_A) {
 400                 if (IS_GEN6(dev) || IS_GEN7(dev))
 401                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 402                 else
 403                         return 225; /* eDP input clock at 450Mhz */
 404         } else {
 405                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 406         }
 407 }
 408
 409 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 410 {
 411         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 412         struct drm_device *dev = intel_dig_port->base.base.dev;
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         if (intel_dig_port->port == PORT_A) {
 416                 if (index)
 417                         return 0;
 418                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 419         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 420                 /* Workaround for non-ULT HSW */
 421                 switch (index) {
 422                 case 0: return 63;
 423                 case 1: return 72;
 424                 default: return 0;
 425                 }
 426         } else  {
 427                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 428         }
 429 }
 430
 431 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 432 {
 433         return index ? 0 : 100;
 434 }
 435
 436 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 437                                       bool has_aux_irq,
 438                                       int send_bytes,
 439                                       uint32_t aux_clock_divider)
 440 {
 441         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 442         struct drm_device *dev = intel_dig_port->base.base.dev;
 443         uint32_t precharge, timeout;
 444
 445         if (IS_GEN6(dev))
 446                 precharge = 3;
 447         else
 448                 precharge = 5;
 449
 450         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 451                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 452         else
 453                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 454
 455         return DP_AUX_CH_CTL_SEND_BUSY |
 456                DP_AUX_CH_CTL_DONE |
 457                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 458                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 459                timeout |
 460                DP_AUX_CH_CTL_RECEIVE_ERROR |
 461                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 462                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 463                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 464 }
 465
 466 static int
 467 intel_dp_aux_ch(struct intel_dp *intel_dp,
 468                 uint8_t *send, int send_bytes,
 469                 uint8_t *recv, int recv_size)
 470 {
 471         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 472         struct drm_device *dev = intel_dig_port->base.base.dev;
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 475         uint32_t ch_data = ch_ctl + 4;
 476         uint32_t aux_clock_divider;
 477         int i, ret, recv_bytes;
 478         uint32_t status;
 479         int try, clock = 0;
 480         bool has_aux_irq = HAS_AUX_IRQ(dev);
 481         bool vdd;
 482
 483         vdd = _edp_panel_vdd_on(intel_dp);
 484
 485         /* dp aux is extremely sensitive to irq latency, hence request the
 486          * lowest possible wakeup latency and so prevent the cpu from going into
 487          * deep sleep states.
 488          */
 489         pm_qos_update_request(&dev_priv->pm_qos, 0);
 490
 491         intel_dp_check_edp(intel_dp);
 492
 493         intel_aux_display_runtime_get(dev_priv);
 494
 495         /* Try to wait for any previous AUX channel activity */
 496         for (try = 0; try < 3; try++) {
 497                 status = I915_READ_NOTRACE(ch_ctl);
 498                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 499                         break;
 500                 msleep(1);
 501         }
 502
 503         if (try == 3) {
 504                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 505                      I915_READ(ch_ctl));
 506                 ret = -EBUSY;
 507                 goto out;
 508         }
 509
 510         /* Only 5 data registers! */
 511         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 512                 ret = -E2BIG;
 513                 goto out;
 514         }
 515
 516         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 517                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 518                                                           has_aux_irq,
 519                                                           send_bytes,
 520                                                           aux_clock_divider);
 521
 522                 /* Must try at least 3 times according to DP spec */
 523                 for (try = 0; try < 5; try++) {
 524                         /* Load the send data into the aux channel data registers */
 525                         for (i = 0; i < send_bytes; i += 4)
 526                                 I915_WRITE(ch_data + i,
 527                                            pack_aux(send + i, send_bytes - i));
 528
 529                         /* Send the command and wait for it to complete */
 530                         I915_WRITE(ch_ctl, send_ctl);
 531
 532                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 533
 534                         /* Clear done status and any errors */
 535                         I915_WRITE(ch_ctl,
 536                                    status |
 537                                    DP_AUX_CH_CTL_DONE |
 538                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 539                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 540
 541                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 542                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 543                                 continue;
 544                         if (status & DP_AUX_CH_CTL_DONE)
 545                                 break;
 546                 }
 547                 if (status & DP_AUX_CH_CTL_DONE)
 548                         break;
 549         }
 550
 551         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 552                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 553                 ret = -EBUSY;
 554                 goto out;
 555         }
 556
 557         /* Check for timeout or receive error.
 558          * Timeouts occur when the sink is not connected
 559          */
 560         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 561                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 562                 ret = -EIO;
 563                 goto out;
 564         }
 565
 566         /* Timeouts occur when the device isn't connected, so they're
 567          * "normal" -- don't fill the kernel log with these */
 568         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 569                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 570                 ret = -ETIMEDOUT;
 571                 goto out;
 572         }
 573
 574         /* Unload any bytes sent back from the other side */
 575         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 576                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 577         if (recv_bytes > recv_size)
 578                 recv_bytes = recv_size;
 579
 580         for (i = 0; i < recv_bytes; i += 4)
 581                 unpack_aux(I915_READ(ch_data + i),
 582                            recv + i, recv_bytes - i);
 583
 584         ret = recv_bytes;
 585 out:
 586         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 587         intel_aux_display_runtime_put(dev_priv);
 588
 589         if (vdd)
 590                 edp_panel_vdd_off(intel_dp, false);
 591
 592         return ret;
 593 }
 594
 595 #define BARE_ADDRESS_SIZE       3
 596 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 597 static ssize_t
 598 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 599 {
 600         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 601         uint8_t txbuf[20], rxbuf[20];
 602         size_t txsize, rxsize;
 603         int ret;
 604
 605         txbuf[0] = msg->request << 4;
 606         txbuf[1] = msg->address >> 8;
 607         txbuf[2] = msg->address & 0xff;
 608         txbuf[3] = msg->size - 1;
 609
 610         switch (msg->request & ~DP_AUX_I2C_MOT) {
 611         case DP_AUX_NATIVE_WRITE:
 612         case DP_AUX_I2C_WRITE:
 613                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 614                 rxsize = 1;
 615
 616                 if (WARN_ON(txsize > 20))
 617                         return -E2BIG;
 618
 619                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 620
 621                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 622                 if (ret > 0) {
 623                         msg->reply = rxbuf[0] >> 4;
 624
 625                         /* Return payload size. */
 626                         ret = msg->size;
 627                 }
 628                 break;
 629
 630         case DP_AUX_NATIVE_READ:
 631         case DP_AUX_I2C_READ:
 632                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 633                 rxsize = msg->size + 1;
 634
 635                 if (WARN_ON(rxsize > 20))
 636                         return -E2BIG;
 637
 638                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 639                 if (ret > 0) {
 640                         msg->reply = rxbuf[0] >> 4;
 641                         /*
 642                          * Assume happy day, and copy the data. The caller is
 643                          * expected to check msg->reply before touching it.
 644                          *
 645                          * Return payload size.
 646                          */
 647                         ret--;
 648                         memcpy(msg->buffer, rxbuf + 1, ret);
 649                 }
 650                 break;
 651
 652         default:
 653                 ret = -EINVAL;
 654                 break;
 655         }
 656
 657         return ret;
 658 }
 659
 660 static void
 661 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 662 {
 663         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 664         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 665         enum port port = intel_dig_port->port;
 666         const char *name = NULL;
 667         int ret;
 668
 669         switch (port) {
 670         case PORT_A:
 671                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 672                 name = "DPDDC-A";
 673                 break;
 674         case PORT_B:
 675                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 676                 name = "DPDDC-B";
 677                 break;
 678         case PORT_C:
 679                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 680                 name = "DPDDC-C";
 681                 break;
 682         case PORT_D:
 683                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 684                 name = "DPDDC-D";
 685                 break;
 686         default:
 687                 BUG();
 688         }
 689
 690         if (!HAS_DDI(dev))
 691                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 692
 693         intel_dp->aux.name = name;
 694         intel_dp->aux.dev = dev->dev;
 695         intel_dp->aux.transfer = intel_dp_aux_transfer;
 696
 697         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 698                       connector->base.kdev->kobj.name);
 699
 700         ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
 701         if (ret < 0) {
 702                 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
 703                           name, ret);
 704                 return;
 705         }
 706
 707         ret = sysfs_create_link(&connector->base.kdev->kobj,
 708                                 &intel_dp->aux.ddc.dev.kobj,
 709                                 intel_dp->aux.ddc.dev.kobj.name);
 710         if (ret < 0) {
 711                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 712                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
 713         }
 714 }
 715
 716 static void
 717 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 718 {
 719         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 720
 721         sysfs_remove_link(&intel_connector->base.kdev->kobj,
 722                           intel_dp->aux.ddc.dev.kobj.name);
 723         intel_connector_unregister(intel_connector);
 724 }
 725
 726 static void
 727 intel_dp_set_clock(struct intel_encoder *encoder,
 728                    struct intel_crtc_config *pipe_config, int link_bw)
 729 {
 730         struct drm_device *dev = encoder->base.dev;
 731         const struct dp_link_dpll *divisor = NULL;
 732         int i, count = 0;
 733
 734         if (IS_G4X(dev)) {
 735                 divisor = gen4_dpll;
 736                 count = ARRAY_SIZE(gen4_dpll);
 737         } else if (IS_HASWELL(dev)) {
 738                 /* Haswell has special-purpose DP DDI clocks. */
 739         } else if (HAS_PCH_SPLIT(dev)) {
 740                 divisor = pch_dpll;
 741                 count = ARRAY_SIZE(pch_dpll);
 742         } else if (IS_VALLEYVIEW(dev)) {
 743                 divisor = vlv_dpll;
 744                 count = ARRAY_SIZE(vlv_dpll);
 745         }
 746
 747         if (divisor && count) {
 748                 for (i = 0; i < count; i++) {
 749                         if (link_bw == divisor[i].link_bw) {
 750                                 pipe_config->dpll = divisor[i].dpll;
 751                                 pipe_config->clock_set = true;
 752                                 break;
 753                         }
 754                 }
 755         }
 756 }
 757
 758 bool
 759 intel_dp_compute_config(struct intel_encoder *encoder,
 760                         struct intel_crtc_config *pipe_config)
 761 {
 762         struct drm_device *dev = encoder->base.dev;
 763         struct drm_i915_private *dev_priv = dev->dev_private;
 764         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 765         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 766         enum port port = dp_to_dig_port(intel_dp)->port;
 767         struct intel_crtc *intel_crtc = encoder->new_crtc;
 768         struct intel_connector *intel_connector = intel_dp->attached_connector;
 769         int lane_count, clock;
 770         int min_lane_count = 1;
 771         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 772         /* Conveniently, the link BW constants become indices with a shift...*/
 773         int min_clock = 0;
 774         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 775         int bpp, mode_rate;
 776         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 777         int link_avail, link_clock;
 778
 779         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 780                 pipe_config->has_pch_encoder = true;
 781
 782         pipe_config->has_dp_encoder = true;
 783
 784         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 785                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 786                                        adjusted_mode);
 787                 if (!HAS_PCH_SPLIT(dev))
 788                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 789                                                  intel_connector->panel.fitting_mode);
 790                 else
 791                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 792                                                 intel_connector->panel.fitting_mode);
 793         }
 794
 795         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 796                 return false;
 797
 798         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 799                       "max bw %02x pixel clock %iKHz\n",
 800                       max_lane_count, bws[max_clock],
 801                       adjusted_mode->crtc_clock);
 802
 803         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 804          * bpc in between. */
 805         bpp = pipe_config->pipe_bpp;
 806         if (is_edp(intel_dp)) {
 807                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 808                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 809                                       dev_priv->vbt.edp_bpp);
 810                         bpp = dev_priv->vbt.edp_bpp;
 811                 }
 812
 813                 if (IS_BROADWELL(dev)) {
 814                         /* Yes, it's an ugly hack. */
 815                         min_lane_count = max_lane_count;
 816                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 817                                       min_lane_count);
 818                 } else if (dev_priv->vbt.edp_lanes) {
 819                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 820                                              max_lane_count);
 821                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 822                                       min_lane_count);
 823                 }
 824
 825                 if (dev_priv->vbt.edp_rate) {
 826                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 827                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 828                                       bws[min_clock]);
 829                 }
 830         }
 831
 832         for (; bpp >= 6*3; bpp -= 2*3) {
 833                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 834                                                    bpp);
 835
 836                 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 837                         for (clock = min_clock; clock <= max_clock; clock++) {
 838                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 839                                 link_avail = intel_dp_max_data_rate(link_clock,
 840                                                                     lane_count);
 841
 842                                 if (mode_rate <= link_avail) {
 843                                         goto found;
 844                                 }
 845                         }
 846                 }
 847         }
 848
 849         return false;
 850
 851 found:
 852         if (intel_dp->color_range_auto) {
 853                 /*
 854                  * See:
 855                  * CEA-861-E - 5.1 Default Encoding Parameters
 856                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 857                  */
 858                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 859                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 860                 else
 861                         intel_dp->color_range = 0;
 862         }
 863
 864         if (intel_dp->color_range)
 865                 pipe_config->limited_color_range = true;
 866
 867         intel_dp->link_bw = bws[clock];
 868         intel_dp->lane_count = lane_count;
 869         pipe_config->pipe_bpp = bpp;
 870         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 871
 872         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 873                       intel_dp->link_bw, intel_dp->lane_count,
 874                       pipe_config->port_clock, bpp);
 875         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 876                       mode_rate, link_avail);
 877
 878         intel_link_compute_m_n(bpp, lane_count,
 879                                adjusted_mode->crtc_clock,
 880                                pipe_config->port_clock,
 881                                &pipe_config->dp_m_n);
 882
 883         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 884
 885         return true;
 886 }
 887
 888 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 889 {
 890         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 891         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 892         struct drm_device *dev = crtc->base.dev;
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894         u32 dpa_ctl;
 895
 896         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 897         dpa_ctl = I915_READ(DP_A);
 898         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 899
 900         if (crtc->config.port_clock == 162000) {
 901                 /* For a long time we've carried around a ILK-DevA w/a for the
 902                  * 160MHz clock. If we're really unlucky, it's still required.
 903                  */
 904                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 905                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 906                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 907         } else {
 908                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 909                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 910         }
 911
 912         I915_WRITE(DP_A, dpa_ctl);
 913
 914         POSTING_READ(DP_A);
 915         udelay(500);
 916 }
 917
 918 static void intel_dp_mode_set(struct intel_encoder *encoder)
 919 {
 920         struct drm_device *dev = encoder->base.dev;
 921         struct drm_i915_private *dev_priv = dev->dev_private;
 922         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 923         enum port port = dp_to_dig_port(intel_dp)->port;
 924         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 925         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 926
 927         /*
 928          * There are four kinds of DP registers:
 929          *
 930          *      IBX PCH
 931          *      SNB CPU
 932          *      IVB CPU
 933          *      CPT PCH
 934          *
 935          * IBX PCH and CPU are the same for almost everything,
 936          * except that the CPU DP PLL is configured in this
 937          * register
 938          *
 939          * CPT PCH is quite different, having many bits moved
 940          * to the TRANS_DP_CTL register instead. That
 941          * configuration happens (oddly) in ironlake_pch_enable
 942          */
 943
 944         /* Preserve the BIOS-computed detected bit. This is
 945          * supposed to be read-only.
 946          */
 947         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 948
 949         /* Handle DP bits in common between all three register formats */
 950         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 951         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 952
 953         if (intel_dp->has_audio) {
 954                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 955                                  pipe_name(crtc->pipe));
 956                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 957                 intel_write_eld(&encoder->base, adjusted_mode);
 958         }
 959
 960         /* Split out the IBX/CPU vs CPT settings */
 961
 962         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 963                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 964                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 965                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 966                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 967                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 968
 969                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 970                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 971
 972                 intel_dp->DP |= crtc->pipe << 29;
 973         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 974                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 975                         intel_dp->DP |= intel_dp->color_range;
 976
 977                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 978                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 979                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 980                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 981                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 982
 983                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 984                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 985
 986                 if (crtc->pipe == 1)
 987                         intel_dp->DP |= DP_PIPEB_SELECT;
 988         } else {
 989                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 990         }
 991
 992         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 993                 ironlake_set_pll_cpu_edp(intel_dp);
 994 }
 995
 996 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 997 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 998
 999 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1000 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1001
1002 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1003 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1004
1005 static void wait_panel_status(struct intel_dp *intel_dp,
1006                                        u32 mask,
1007                                        u32 value)
1008 {
1009         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 pp_stat_reg, pp_ctrl_reg;
1012
1013         pp_stat_reg = _pp_stat_reg(intel_dp);
1014         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1015
1016         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1017                         mask, value,
1018                         I915_READ(pp_stat_reg),
1019                         I915_READ(pp_ctrl_reg));
1020
1021         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1022                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1023                                 I915_READ(pp_stat_reg),
1024                                 I915_READ(pp_ctrl_reg));
1025         }
1026
1027         DRM_DEBUG_KMS("Wait complete\n");
1028 }
1029
1030 static void wait_panel_on(struct intel_dp *intel_dp)
1031 {
1032         DRM_DEBUG_KMS("Wait for panel power on\n");
1033         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1034 }
1035
1036 static void wait_panel_off(struct intel_dp *intel_dp)
1037 {
1038         DRM_DEBUG_KMS("Wait for panel power off time\n");
1039         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1040 }
1041
1042 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1043 {
1044         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1045
1046         /* When we disable the VDD override bit last we have to do the manual
1047          * wait. */
1048         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1049                                        intel_dp->panel_power_cycle_delay);
1050
1051         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1052 }
1053
1054 static void wait_backlight_on(struct intel_dp *intel_dp)
1055 {
1056         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1057                                        intel_dp->backlight_on_delay);
1058 }
1059
1060 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1061 {
1062         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1063                                        intel_dp->backlight_off_delay);
1064 }
1065
1066 /* Read the current pp_control value, unlocking the register if it
1067  * is locked
1068  */
1069
1070 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1071 {
1072         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         u32 control;
1075
1076         control = I915_READ(_pp_ctrl_reg(intel_dp));
1077         control &= ~PANEL_UNLOCK_MASK;
1078         control |= PANEL_UNLOCK_REGS;
1079         return control;
1080 }
1081
1082 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1083 {
1084         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086         u32 pp;
1087         u32 pp_stat_reg, pp_ctrl_reg;
1088         bool need_to_disable = !intel_dp->want_panel_vdd;
1089
1090         if (!is_edp(intel_dp))
1091                 return false;
1092
1093         intel_dp->want_panel_vdd = true;
1094
1095         if (edp_have_panel_vdd(intel_dp))
1096                 return need_to_disable;
1097
1098         intel_runtime_pm_get(dev_priv);
1099
1100         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1101
1102         if (!edp_have_panel_power(intel_dp))
1103                 wait_panel_power_cycle(intel_dp);
1104
1105         pp = ironlake_get_pp_control(intel_dp);
1106         pp |= EDP_FORCE_VDD;
1107
1108         pp_stat_reg = _pp_stat_reg(intel_dp);
1109         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1110
1111         I915_WRITE(pp_ctrl_reg, pp);
1112         POSTING_READ(pp_ctrl_reg);
1113         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1115         /*
1116          * If the panel wasn't on, delay before accessing aux channel
1117          */
1118         if (!edp_have_panel_power(intel_dp)) {
1119                 DRM_DEBUG_KMS("eDP was not running\n");
1120                 msleep(intel_dp->panel_power_up_delay);
1121         }
1122
1123         return need_to_disable;
1124 }
1125
1126 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1127 {
1128         if (is_edp(intel_dp)) {
1129                 bool vdd = _edp_panel_vdd_on(intel_dp);
1130
1131                 WARN(!vdd, "eDP VDD already requested on\n");
1132         }
1133 }
1134
1135 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1136 {
1137         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         u32 pp;
1140         u32 pp_stat_reg, pp_ctrl_reg;
1141
1142         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1143
1144         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1145                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1146
1147                 pp = ironlake_get_pp_control(intel_dp);
1148                 pp &= ~EDP_FORCE_VDD;
1149
1150                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1151                 pp_stat_reg = _pp_stat_reg(intel_dp);
1152
1153                 I915_WRITE(pp_ctrl_reg, pp);
1154                 POSTING_READ(pp_ctrl_reg);
1155
1156                 /* Make sure sequencer is idle before allowing subsequent activity */
1157                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1158                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1159
1160                 if ((pp & POWER_TARGET_ON) == 0)
1161                         intel_dp->last_power_cycle = jiffies;
1162
1163                 intel_runtime_pm_put(dev_priv);
1164         }
1165 }
1166
1167 static void edp_panel_vdd_work(struct work_struct *__work)
1168 {
1169         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1170                                                  struct intel_dp, panel_vdd_work);
1171         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1172
1173         mutex_lock(&dev->mode_config.mutex);
1174         edp_panel_vdd_off_sync(intel_dp);
1175         mutex_unlock(&dev->mode_config.mutex);
1176 }
1177
1178 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1179 {
1180         if (!is_edp(intel_dp))
1181                 return;
1182
1183         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1184
1185         intel_dp->want_panel_vdd = false;
1186
1187         if (sync) {
1188                 edp_panel_vdd_off_sync(intel_dp);
1189         } else {
1190                 /*
1191                  * Queue the timer to fire a long
1192                  * time from now (relative to the power down delay)
1193                  * to keep the panel power up across a sequence of operations
1194                  */
1195                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1196                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1197         }
1198 }
1199
1200 void intel_edp_panel_on(struct intel_dp *intel_dp)
1201 {
1202         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204         u32 pp;
1205         u32 pp_ctrl_reg;
1206
1207         if (!is_edp(intel_dp))
1208                 return;
1209
1210         DRM_DEBUG_KMS("Turn eDP power on\n");
1211
1212         if (edp_have_panel_power(intel_dp)) {
1213                 DRM_DEBUG_KMS("eDP power already on\n");
1214                 return;
1215         }
1216
1217         wait_panel_power_cycle(intel_dp);
1218
1219         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1220         pp = ironlake_get_pp_control(intel_dp);
1221         if (IS_GEN5(dev)) {
1222                 /* ILK workaround: disable reset around power sequence */
1223                 pp &= ~PANEL_POWER_RESET;
1224                 I915_WRITE(pp_ctrl_reg, pp);
1225                 POSTING_READ(pp_ctrl_reg);
1226         }
1227
1228         pp |= POWER_TARGET_ON;
1229         if (!IS_GEN5(dev))
1230                 pp |= PANEL_POWER_RESET;
1231
1232         I915_WRITE(pp_ctrl_reg, pp);
1233         POSTING_READ(pp_ctrl_reg);
1234
1235         wait_panel_on(intel_dp);
1236         intel_dp->last_power_on = jiffies;
1237
1238         if (IS_GEN5(dev)) {
1239                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1240                 I915_WRITE(pp_ctrl_reg, pp);
1241                 POSTING_READ(pp_ctrl_reg);
1242         }
1243 }
1244
1245 void intel_edp_panel_off(struct intel_dp *intel_dp)
1246 {
1247         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         u32 pp;
1250         u32 pp_ctrl_reg;
1251
1252         if (!is_edp(intel_dp))
1253                 return;
1254
1255         DRM_DEBUG_KMS("Turn eDP power off\n");
1256
1257         edp_wait_backlight_off(intel_dp);
1258
1259         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1260
1261         pp = ironlake_get_pp_control(intel_dp);
1262         /* We need to switch off panel power _and_ force vdd, for otherwise some
1263          * panels get very unhappy and cease to work. */
1264         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1265                 EDP_BLC_ENABLE);
1266
1267         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1268
1269         intel_dp->want_panel_vdd = false;
1270
1271         I915_WRITE(pp_ctrl_reg, pp);
1272         POSTING_READ(pp_ctrl_reg);
1273
1274         intel_dp->last_power_cycle = jiffies;
1275         wait_panel_off(intel_dp);
1276
1277         /* We got a reference when we enabled the VDD. */
1278         intel_runtime_pm_put(dev_priv);
1279 }
1280
1281 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1282 {
1283         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1284         struct drm_device *dev = intel_dig_port->base.base.dev;
1285         struct drm_i915_private *dev_priv = dev->dev_private;
1286         u32 pp;
1287         u32 pp_ctrl_reg;
1288
1289         if (!is_edp(intel_dp))
1290                 return;
1291
1292         DRM_DEBUG_KMS("\n");
1293         /*
1294          * If we enable the backlight right away following a panel power
1295          * on, we may see slight flicker as the panel syncs with the eDP
1296          * link.  So delay a bit to make sure the image is solid before
1297          * allowing it to appear.
1298          */
1299         wait_backlight_on(intel_dp);
1300         pp = ironlake_get_pp_control(intel_dp);
1301         pp |= EDP_BLC_ENABLE;
1302
1303         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1304
1305         I915_WRITE(pp_ctrl_reg, pp);
1306         POSTING_READ(pp_ctrl_reg);
1307
1308         intel_panel_enable_backlight(intel_dp->attached_connector);
1309 }
1310
1311 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1312 {
1313         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         u32 pp;
1316         u32 pp_ctrl_reg;
1317
1318         if (!is_edp(intel_dp))
1319                 return;
1320
1321         intel_panel_disable_backlight(intel_dp->attached_connector);
1322
1323         DRM_DEBUG_KMS("\n");
1324         pp = ironlake_get_pp_control(intel_dp);
1325         pp &= ~EDP_BLC_ENABLE;
1326
1327         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1328
1329         I915_WRITE(pp_ctrl_reg, pp);
1330         POSTING_READ(pp_ctrl_reg);
1331         intel_dp->last_backlight_off = jiffies;
1332 }
1333
1334 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1335 {
1336         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1337         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1338         struct drm_device *dev = crtc->dev;
1339         struct drm_i915_private *dev_priv = dev->dev_private;
1340         u32 dpa_ctl;
1341
1342         assert_pipe_disabled(dev_priv,
1343                              to_intel_crtc(crtc)->pipe);
1344
1345         DRM_DEBUG_KMS("\n");
1346         dpa_ctl = I915_READ(DP_A);
1347         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1348         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1349
1350         /* We don't adjust intel_dp->DP while tearing down the link, to
1351          * facilitate link retraining (e.g. after hotplug). Hence clear all
1352          * enable bits here to ensure that we don't enable too much. */
1353         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1354         intel_dp->DP |= DP_PLL_ENABLE;
1355         I915_WRITE(DP_A, intel_dp->DP);
1356         POSTING_READ(DP_A);
1357         udelay(200);
1358 }
1359
1360 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1361 {
1362         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1363         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1364         struct drm_device *dev = crtc->dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         u32 dpa_ctl;
1367
1368         assert_pipe_disabled(dev_priv,
1369                              to_intel_crtc(crtc)->pipe);
1370
1371         dpa_ctl = I915_READ(DP_A);
1372         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1373              "dp pll off, should be on\n");
1374         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1375
1376         /* We can't rely on the value tracked for the DP register in
1377          * intel_dp->DP because link_down must not change that (otherwise link
1378          * re-training will fail. */
1379         dpa_ctl &= ~DP_PLL_ENABLE;
1380         I915_WRITE(DP_A, dpa_ctl);
1381         POSTING_READ(DP_A);
1382         udelay(200);
1383 }
1384
1385 /* If the sink supports it, try to set the power state appropriately */
1386 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1387 {
1388         int ret, i;
1389
1390         /* Should have a valid DPCD by this point */
1391         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1392                 return;
1393
1394         if (mode != DRM_MODE_DPMS_ON) {
1395                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1396                                          DP_SET_POWER_D3);
1397                 if (ret != 1)
1398                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1399         } else {
1400                 /*
1401                  * When turning on, we need to retry for 1ms to give the sink
1402                  * time to wake up.
1403                  */
1404                 for (i = 0; i < 3; i++) {
1405                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1406                                                  DP_SET_POWER_D0);
1407                         if (ret == 1)
1408                                 break;
1409                         msleep(1);
1410                 }
1411         }
1412 }
1413
1414 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1415                                   enum pipe *pipe)
1416 {
1417         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1418         enum port port = dp_to_dig_port(intel_dp)->port;
1419         struct drm_device *dev = encoder->base.dev;
1420         struct drm_i915_private *dev_priv = dev->dev_private;
1421         enum intel_display_power_domain power_domain;
1422         u32 tmp;
1423
1424         power_domain = intel_display_port_power_domain(encoder);
1425         if (!intel_display_power_enabled(dev_priv, power_domain))
1426                 return false;
1427
1428         tmp = I915_READ(intel_dp->output_reg);
1429
1430         if (!(tmp & DP_PORT_EN))
1431                 return false;
1432
1433         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1434                 *pipe = PORT_TO_PIPE_CPT(tmp);
1435         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1436                 *pipe = PORT_TO_PIPE(tmp);
1437         } else {
1438                 u32 trans_sel;
1439                 u32 trans_dp;
1440                 int i;
1441
1442                 switch (intel_dp->output_reg) {
1443                 case PCH_DP_B:
1444                         trans_sel = TRANS_DP_PORT_SEL_B;
1445                         break;
1446                 case PCH_DP_C:
1447                         trans_sel = TRANS_DP_PORT_SEL_C;
1448                         break;
1449                 case PCH_DP_D:
1450                         trans_sel = TRANS_DP_PORT_SEL_D;
1451                         break;
1452                 default:
1453                         return true;
1454                 }
1455
1456                 for_each_pipe(i) {
1457                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1458                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1459                                 *pipe = i;
1460                                 return true;
1461                         }
1462                 }
1463
1464                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1465                               intel_dp->output_reg);
1466         }
1467
1468         return true;
1469 }
1470
1471 static void intel_dp_get_config(struct intel_encoder *encoder,
1472                                 struct intel_crtc_config *pipe_config)
1473 {
1474         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1475         u32 tmp, flags = 0;
1476         struct drm_device *dev = encoder->base.dev;
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478         enum port port = dp_to_dig_port(intel_dp)->port;
1479         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1480         int dotclock;
1481
1482         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1483                 tmp = I915_READ(intel_dp->output_reg);
1484                 if (tmp & DP_SYNC_HS_HIGH)
1485                         flags |= DRM_MODE_FLAG_PHSYNC;
1486                 else
1487                         flags |= DRM_MODE_FLAG_NHSYNC;
1488
1489                 if (tmp & DP_SYNC_VS_HIGH)
1490                         flags |= DRM_MODE_FLAG_PVSYNC;
1491                 else
1492                         flags |= DRM_MODE_FLAG_NVSYNC;
1493         } else {
1494                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1495                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1496                         flags |= DRM_MODE_FLAG_PHSYNC;
1497                 else
1498                         flags |= DRM_MODE_FLAG_NHSYNC;
1499
1500                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1501                         flags |= DRM_MODE_FLAG_PVSYNC;
1502                 else
1503                         flags |= DRM_MODE_FLAG_NVSYNC;
1504         }
1505
1506         pipe_config->adjusted_mode.flags |= flags;
1507
1508         pipe_config->has_dp_encoder = true;
1509
1510         intel_dp_get_m_n(crtc, pipe_config);
1511
1512         if (port == PORT_A) {
1513                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1514                         pipe_config->port_clock = 162000;
1515                 else
1516                         pipe_config->port_clock = 270000;
1517         }
1518
1519         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1520                                             &pipe_config->dp_m_n);
1521
1522         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1523                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1524
1525         pipe_config->adjusted_mode.crtc_clock = dotclock;
1526
1527         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1528             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1529                 /*
1530                  * This is a big fat ugly hack.
1531                  *
1532                  * Some machines in UEFI boot mode provide us a VBT that has 18
1533                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1534                  * unknown we fail to light up. Yet the same BIOS boots up with
1535                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1536                  * max, not what it tells us to use.
1537                  *
1538                  * Note: This will still be broken if the eDP panel is not lit
1539                  * up by the BIOS, and thus we can't get the mode at module
1540                  * load.
1541                  */
1542                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1543                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1544                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1545         }
1546 }
1547
1548 static bool is_edp_psr(struct drm_device *dev)
1549 {
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551
1552         return dev_priv->psr.sink_support;
1553 }
1554
1555 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1556 {
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558
1559         if (!HAS_PSR(dev))
1560                 return false;
1561
1562         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1563 }
1564
1565 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1566                                     struct edp_vsc_psr *vsc_psr)
1567 {
1568         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1569         struct drm_device *dev = dig_port->base.base.dev;
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1572         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1573         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1574         uint32_t *data = (uint32_t *) vsc_psr;
1575         unsigned int i;
1576
1577         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1578            the video DIP being updated before program video DIP data buffer
1579            registers for DIP being updated. */
1580         I915_WRITE(ctl_reg, 0);
1581         POSTING_READ(ctl_reg);
1582
1583         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1584                 if (i < sizeof(struct edp_vsc_psr))
1585                         I915_WRITE(data_reg + i, *data++);
1586                 else
1587                         I915_WRITE(data_reg + i, 0);
1588         }
1589
1590         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1591         POSTING_READ(ctl_reg);
1592 }
1593
1594 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1595 {
1596         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         struct edp_vsc_psr psr_vsc;
1599
1600         if (intel_dp->psr_setup_done)
1601                 return;
1602
1603         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1604         memset(&psr_vsc, 0, sizeof(psr_vsc));
1605         psr_vsc.sdp_header.HB0 = 0;
1606         psr_vsc.sdp_header.HB1 = 0x7;
1607         psr_vsc.sdp_header.HB2 = 0x2;
1608         psr_vsc.sdp_header.HB3 = 0x8;
1609         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1610
1611         /* Avoid continuous PSR exit by masking memup and hpd */
1612         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1613                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1614
1615         intel_dp->psr_setup_done = true;
1616 }
1617
1618 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1619 {
1620         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         uint32_t aux_clock_divider;
1623         int precharge = 0x3;
1624         int msg_size = 5;       /* Header(4) + Message(1) */
1625
1626         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1627
1628         /* Enable PSR in sink */
1629         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1630                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1631                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1632         else
1633                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1634                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1635
1636         /* Setup AUX registers */
1637         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1638         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1639         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1640                    DP_AUX_CH_CTL_TIME_OUT_400us |
1641                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1642                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1643                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1644 }
1645
1646 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1647 {
1648         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         uint32_t max_sleep_time = 0x1f;
1651         uint32_t idle_frames = 1;
1652         uint32_t val = 0x0;
1653         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1654
1655         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1656                 val |= EDP_PSR_LINK_STANDBY;
1657                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1658                 val |= EDP_PSR_TP1_TIME_0us;
1659                 val |= EDP_PSR_SKIP_AUX_EXIT;
1660         } else
1661                 val |= EDP_PSR_LINK_DISABLE;
1662
1663         I915_WRITE(EDP_PSR_CTL(dev), val |
1664                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1665                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1666                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1667                    EDP_PSR_ENABLE);
1668 }
1669
1670 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1671 {
1672         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1673         struct drm_device *dev = dig_port->base.base.dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         struct drm_crtc *crtc = dig_port->base.base.crtc;
1676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1677         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1678         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1679
1680         dev_priv->psr.source_ok = false;
1681
1682         if (!HAS_PSR(dev)) {
1683                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1684                 return false;
1685         }
1686
1687         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1688             (dig_port->port != PORT_A)) {
1689                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1690                 return false;
1691         }
1692
1693         if (!i915.enable_psr) {
1694                 DRM_DEBUG_KMS("PSR disable by flag\n");
1695                 return false;
1696         }
1697
1698         crtc = dig_port->base.base.crtc;
1699         if (crtc == NULL) {
1700                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1701                 return false;
1702         }
1703
1704         intel_crtc = to_intel_crtc(crtc);
1705         if (!intel_crtc_active(crtc)) {
1706                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1707                 return false;
1708         }
1709
1710         obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1711         if (obj->tiling_mode != I915_TILING_X ||
1712             obj->fence_reg == I915_FENCE_REG_NONE) {
1713                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1714                 return false;
1715         }
1716
1717         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1718                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1719                 return false;
1720         }
1721
1722         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1723             S3D_ENABLE) {
1724                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1725                 return false;
1726         }
1727
1728         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1729                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1730                 return false;
1731         }
1732
1733         dev_priv->psr.source_ok = true;
1734         return true;
1735 }
1736
1737 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1738 {
1739         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1740
1741         if (!intel_edp_psr_match_conditions(intel_dp) ||
1742             intel_edp_is_psr_enabled(dev))
1743                 return;
1744
1745         /* Setup PSR once */
1746         intel_edp_psr_setup(intel_dp);
1747
1748         /* Enable PSR on the panel */
1749         intel_edp_psr_enable_sink(intel_dp);
1750
1751         /* Enable PSR on the host */
1752         intel_edp_psr_enable_source(intel_dp);
1753 }
1754
1755 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1756 {
1757         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1758
1759         if (intel_edp_psr_match_conditions(intel_dp) &&
1760             !intel_edp_is_psr_enabled(dev))
1761                 intel_edp_psr_do_enable(intel_dp);
1762 }
1763
1764 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1765 {
1766         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768
1769         if (!intel_edp_is_psr_enabled(dev))
1770                 return;
1771
1772         I915_WRITE(EDP_PSR_CTL(dev),
1773                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1774
1775         /* Wait till PSR is idle */
1776         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1777                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1778                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1779 }
1780
1781 void intel_edp_psr_update(struct drm_device *dev)
1782 {
1783         struct intel_encoder *encoder;
1784         struct intel_dp *intel_dp = NULL;
1785
1786         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1787                 if (encoder->type == INTEL_OUTPUT_EDP) {
1788                         intel_dp = enc_to_intel_dp(&encoder->base);
1789
1790                         if (!is_edp_psr(dev))
1791                                 return;
1792
1793                         if (!intel_edp_psr_match_conditions(intel_dp))
1794                                 intel_edp_psr_disable(intel_dp);
1795                         else
1796                                 if (!intel_edp_is_psr_enabled(dev))
1797                                         intel_edp_psr_do_enable(intel_dp);
1798                 }
1799 }
1800
1801 static void intel_disable_dp(struct intel_encoder *encoder)
1802 {
1803         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1804         enum port port = dp_to_dig_port(intel_dp)->port;
1805         struct drm_device *dev = encoder->base.dev;
1806
1807         /* Make sure the panel is off before trying to change the mode. But also
1808          * ensure that we have vdd while we switch off the panel. */
1809         intel_edp_panel_vdd_on(intel_dp);
1810         intel_edp_backlight_off(intel_dp);
1811         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1812         intel_edp_panel_off(intel_dp);
1813
1814         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1815         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1816                 intel_dp_link_down(intel_dp);
1817 }
1818
1819 static void intel_post_disable_dp(struct intel_encoder *encoder)
1820 {
1821         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1822         enum port port = dp_to_dig_port(intel_dp)->port;
1823         struct drm_device *dev = encoder->base.dev;
1824
1825         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1826                 intel_dp_link_down(intel_dp);
1827                 if (!IS_VALLEYVIEW(dev))
1828                         ironlake_edp_pll_off(intel_dp);
1829         }
1830 }
1831
1832 static void intel_enable_dp(struct intel_encoder *encoder)
1833 {
1834         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1835         struct drm_device *dev = encoder->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1838
1839         if (WARN_ON(dp_reg & DP_PORT_EN))
1840                 return;
1841
1842         intel_edp_panel_vdd_on(intel_dp);
1843         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1844         intel_dp_start_link_train(intel_dp);
1845         intel_edp_panel_on(intel_dp);
1846         edp_panel_vdd_off(intel_dp, true);
1847         intel_dp_complete_link_train(intel_dp);
1848         intel_dp_stop_link_train(intel_dp);
1849 }
1850
1851 static void g4x_enable_dp(struct intel_encoder *encoder)
1852 {
1853         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1854
1855         intel_enable_dp(encoder);
1856         intel_edp_backlight_on(intel_dp);
1857 }
1858
1859 static void vlv_enable_dp(struct intel_encoder *encoder)
1860 {
1861         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1862
1863         intel_edp_backlight_on(intel_dp);
1864 }
1865
1866 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1867 {
1868         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1869         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1870
1871         if (dport->port == PORT_A)
1872                 ironlake_edp_pll_on(intel_dp);
1873 }
1874
1875 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1876 {
1877         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1878         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1879         struct drm_device *dev = encoder->base.dev;
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1882         enum dpio_channel port = vlv_dport_to_channel(dport);
1883         int pipe = intel_crtc->pipe;
1884         struct edp_power_seq power_seq;
1885         u32 val;
1886
1887         mutex_lock(&dev_priv->dpio_lock);
1888
1889         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1890         val = 0;
1891         if (pipe)
1892                 val |= (1<<21);
1893         else
1894                 val &= ~(1<<21);
1895         val |= 0x001000c4;
1896         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1897         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1898         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1899
1900         mutex_unlock(&dev_priv->dpio_lock);
1901
1902         if (is_edp(intel_dp)) {
1903                 /* init power sequencer on this pipe and port */
1904                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1905                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1906                                                               &power_seq);
1907         }
1908
1909         intel_enable_dp(encoder);
1910
1911         vlv_wait_port_ready(dev_priv, dport);
1912 }
1913
1914 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1915 {
1916         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1917         struct drm_device *dev = encoder->base.dev;
1918         struct drm_i915_private *dev_priv = dev->dev_private;
1919         struct intel_crtc *intel_crtc =
1920                 to_intel_crtc(encoder->base.crtc);
1921         enum dpio_channel port = vlv_dport_to_channel(dport);
1922         int pipe = intel_crtc->pipe;
1923
1924         /* Program Tx lane resets to default */
1925         mutex_lock(&dev_priv->dpio_lock);
1926         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1927                          DPIO_PCS_TX_LANE2_RESET |
1928                          DPIO_PCS_TX_LANE1_RESET);
1929         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1930                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1931                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1932                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1933                                  DPIO_PCS_CLK_SOFT_RESET);
1934
1935         /* Fix up inter-pair skew failure */
1936         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1937         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1938         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1939         mutex_unlock(&dev_priv->dpio_lock);
1940 }
1941
1942 /*
1943  * Native read with retry for link status and receiver capability reads for
1944  * cases where the sink may still be asleep.
1945  *
1946  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1947  * supposed to retry 3 times per the spec.
1948  */
1949 static ssize_t
1950 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1951                         void *buffer, size_t size)
1952 {
1953         ssize_t ret;
1954         int i;
1955
1956         for (i = 0; i < 3; i++) {
1957                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1958                 if (ret == size)
1959                         return ret;
1960                 msleep(1);
1961         }
1962
1963         return ret;
1964 }
1965
1966 /*
1967  * Fetch AUX CH registers 0x202 - 0x207 which contain
1968  * link status information
1969  */
1970 static bool
1971 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1972 {
1973         return intel_dp_dpcd_read_wake(&intel_dp->aux,
1974                                        DP_LANE0_1_STATUS,
1975                                        link_status,
1976                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1977 }
1978
1979 /*
1980  * These are source-specific values; current Intel hardware supports
1981  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1982  */
1983
1984 static uint8_t
1985 intel_dp_voltage_max(struct intel_dp *intel_dp)
1986 {
1987         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1988         enum port port = dp_to_dig_port(intel_dp)->port;
1989
1990         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1991                 return DP_TRAIN_VOLTAGE_SWING_1200;
1992         else if (IS_GEN7(dev) && port == PORT_A)
1993                 return DP_TRAIN_VOLTAGE_SWING_800;
1994         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1995                 return DP_TRAIN_VOLTAGE_SWING_1200;
1996         else
1997                 return DP_TRAIN_VOLTAGE_SWING_800;
1998 }
1999
2000 static uint8_t
2001 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2002 {
2003         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2004         enum port port = dp_to_dig_port(intel_dp)->port;
2005
2006         if (IS_BROADWELL(dev)) {
2007                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2008                 case DP_TRAIN_VOLTAGE_SWING_400:
2009                 case DP_TRAIN_VOLTAGE_SWING_600:
2010                         return DP_TRAIN_PRE_EMPHASIS_6;
2011                 case DP_TRAIN_VOLTAGE_SWING_800:
2012                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2013                 case DP_TRAIN_VOLTAGE_SWING_1200:
2014                 default:
2015                         return DP_TRAIN_PRE_EMPHASIS_0;
2016                 }
2017         } else if (IS_HASWELL(dev)) {
2018                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2019                 case DP_TRAIN_VOLTAGE_SWING_400:
2020                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2021                 case DP_TRAIN_VOLTAGE_SWING_600:
2022                         return DP_TRAIN_PRE_EMPHASIS_6;
2023                 case DP_TRAIN_VOLTAGE_SWING_800:
2024                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2025                 case DP_TRAIN_VOLTAGE_SWING_1200:
2026                 default:
2027                         return DP_TRAIN_PRE_EMPHASIS_0;
2028                 }
2029         } else if (IS_VALLEYVIEW(dev)) {
2030                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2031                 case DP_TRAIN_VOLTAGE_SWING_400:
2032                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2033                 case DP_TRAIN_VOLTAGE_SWING_600:
2034                         return DP_TRAIN_PRE_EMPHASIS_6;
2035                 case DP_TRAIN_VOLTAGE_SWING_800:
2036                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2037                 case DP_TRAIN_VOLTAGE_SWING_1200:
2038                 default:
2039                         return DP_TRAIN_PRE_EMPHASIS_0;
2040                 }
2041         } else if (IS_GEN7(dev) && port == PORT_A) {
2042                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2043                 case DP_TRAIN_VOLTAGE_SWING_400:
2044                         return DP_TRAIN_PRE_EMPHASIS_6;
2045                 case DP_TRAIN_VOLTAGE_SWING_600:
2046                 case DP_TRAIN_VOLTAGE_SWING_800:
2047                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2048                 default:
2049                         return DP_TRAIN_PRE_EMPHASIS_0;
2050                 }
2051         } else {
2052                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2053                 case DP_TRAIN_VOLTAGE_SWING_400:
2054                         return DP_TRAIN_PRE_EMPHASIS_6;
2055                 case DP_TRAIN_VOLTAGE_SWING_600:
2056                         return DP_TRAIN_PRE_EMPHASIS_6;
2057                 case DP_TRAIN_VOLTAGE_SWING_800:
2058                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2059                 case DP_TRAIN_VOLTAGE_SWING_1200:
2060                 default:
2061                         return DP_TRAIN_PRE_EMPHASIS_0;
2062                 }
2063         }
2064 }
2065
2066 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2067 {
2068         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2069         struct drm_i915_private *dev_priv = dev->dev_private;
2070         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2071         struct intel_crtc *intel_crtc =
2072                 to_intel_crtc(dport->base.base.crtc);
2073         unsigned long demph_reg_value, preemph_reg_value,
2074                 uniqtranscale_reg_value;
2075         uint8_t train_set = intel_dp->train_set[0];
2076         enum dpio_channel port = vlv_dport_to_channel(dport);
2077         int pipe = intel_crtc->pipe;
2078
2079         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2080         case DP_TRAIN_PRE_EMPHASIS_0:
2081                 preemph_reg_value = 0x0004000;
2082                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2083                 case DP_TRAIN_VOLTAGE_SWING_400:
2084                         demph_reg_value = 0x2B405555;
2085                         uniqtranscale_reg_value = 0x552AB83A;
2086                         break;
2087                 case DP_TRAIN_VOLTAGE_SWING_600:
2088                         demph_reg_value = 0x2B404040;
2089                         uniqtranscale_reg_value = 0x5548B83A;
2090                         break;
2091                 case DP_TRAIN_VOLTAGE_SWING_800:
2092                         demph_reg_value = 0x2B245555;
2093                         uniqtranscale_reg_value = 0x5560B83A;
2094                         break;
2095                 case DP_TRAIN_VOLTAGE_SWING_1200:
2096                         demph_reg_value = 0x2B405555;
2097                         uniqtranscale_reg_value = 0x5598DA3A;
2098                         break;
2099                 default:
2100                         return 0;
2101                 }
2102                 break;
2103         case DP_TRAIN_PRE_EMPHASIS_3_5:
2104                 preemph_reg_value = 0x0002000;
2105                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2106                 case DP_TRAIN_VOLTAGE_SWING_400:
2107                         demph_reg_value = 0x2B404040;
2108                         uniqtranscale_reg_value = 0x5552B83A;
2109                         break;
2110                 case DP_TRAIN_VOLTAGE_SWING_600:
2111                         demph_reg_value = 0x2B404848;
2112                         uniqtranscale_reg_value = 0x5580B83A;
2113                         break;
2114                 case DP_TRAIN_VOLTAGE_SWING_800:
2115                         demph_reg_value = 0x2B404040;
2116                         uniqtranscale_reg_value = 0x55ADDA3A;
2117                         break;
2118                 default:
2119                         return 0;
2120                 }
2121                 break;
2122         case DP_TRAIN_PRE_EMPHASIS_6:
2123                 preemph_reg_value = 0x0000000;
2124                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2125                 case DP_TRAIN_VOLTAGE_SWING_400:
2126                         demph_reg_value = 0x2B305555;
2127                         uniqtranscale_reg_value = 0x5570B83A;
2128                         break;
2129                 case DP_TRAIN_VOLTAGE_SWING_600:
2130                         demph_reg_value = 0x2B2B4040;
2131                         uniqtranscale_reg_value = 0x55ADDA3A;
2132                         break;
2133                 default:
2134                         return 0;
2135                 }
2136                 break;
2137         case DP_TRAIN_PRE_EMPHASIS_9_5:
2138                 preemph_reg_value = 0x0006000;
2139                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2140                 case DP_TRAIN_VOLTAGE_SWING_400:
2141                         demph_reg_value = 0x1B405555;
2142                         uniqtranscale_reg_value = 0x55ADDA3A;
2143                         break;
2144                 default:
2145                         return 0;
2146                 }
2147                 break;
2148         default:
2149                 return 0;
2150         }
2151
2152         mutex_lock(&dev_priv->dpio_lock);
2153         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2154         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2155         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2156                          uniqtranscale_reg_value);
2157         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2158         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2159         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2160         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2161         mutex_unlock(&dev_priv->dpio_lock);
2162
2163         return 0;
2164 }
2165
2166 static void
2167 intel_get_adjust_train(struct intel_dp *intel_dp,
2168                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2169 {
2170         uint8_t v = 0;
2171         uint8_t p = 0;
2172         int lane;
2173         uint8_t voltage_max;
2174         uint8_t preemph_max;
2175
2176         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2177                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2178                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2179
2180                 if (this_v > v)
2181                         v = this_v;
2182                 if (this_p > p)
2183                         p = this_p;
2184         }
2185
2186         voltage_max = intel_dp_voltage_max(intel_dp);
2187         if (v >= voltage_max)
2188                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2189
2190         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2191         if (p >= preemph_max)
2192                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2193
2194         for (lane = 0; lane < 4; lane++)
2195                 intel_dp->train_set[lane] = v | p;
2196 }
2197
2198 static uint32_t
2199 intel_gen4_signal_levels(uint8_t train_set)
2200 {
2201         uint32_t        signal_levels = 0;
2202
2203         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2204         case DP_TRAIN_VOLTAGE_SWING_400:
2205         default:
2206                 signal_levels |= DP_VOLTAGE_0_4;
2207                 break;
2208         case DP_TRAIN_VOLTAGE_SWING_600:
2209                 signal_levels |= DP_VOLTAGE_0_6;
2210                 break;
2211         case DP_TRAIN_VOLTAGE_SWING_800:
2212                 signal_levels |= DP_VOLTAGE_0_8;
2213                 break;
2214         case DP_TRAIN_VOLTAGE_SWING_1200:
2215                 signal_levels |= DP_VOLTAGE_1_2;
2216                 break;
2217         }
2218         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2219         case DP_TRAIN_PRE_EMPHASIS_0:
2220         default:
2221                 signal_levels |= DP_PRE_EMPHASIS_0;
2222                 break;
2223         case DP_TRAIN_PRE_EMPHASIS_3_5:
2224                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2225                 break;
2226         case DP_TRAIN_PRE_EMPHASIS_6:
2227                 signal_levels |= DP_PRE_EMPHASIS_6;
2228                 break;
2229         case DP_TRAIN_PRE_EMPHASIS_9_5:
2230                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2231                 break;
2232         }
2233         return signal_levels;
2234 }
2235
2236 /* Gen6's DP voltage swing and pre-emphasis control */
2237 static uint32_t
2238 intel_gen6_edp_signal_levels(uint8_t train_set)
2239 {
2240         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2241                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2242         switch (signal_levels) {
2243         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2244         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2245                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2246         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2247                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2248         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2249         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2250                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2251         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2252         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2253                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2254         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2255         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2256                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2257         default:
2258                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2259                               "0x%x\n", signal_levels);
2260                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2261         }
2262 }
2263
2264 /* Gen7's DP voltage swing and pre-emphasis control */
2265 static uint32_t
2266 intel_gen7_edp_signal_levels(uint8_t train_set)
2267 {
2268         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2269                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2270         switch (signal_levels) {
2271         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2272                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2273         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2274                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2275         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2276                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2277
2278         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2279                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2280         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2282
2283         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2284                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2285         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2286                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2287
2288         default:
2289                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2290                               "0x%x\n", signal_levels);
2291                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2292         }
2293 }
2294
2295 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2296 static uint32_t
2297 intel_hsw_signal_levels(uint8_t train_set)
2298 {
2299         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2300                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2301         switch (signal_levels) {
2302         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2303                 return DDI_BUF_EMP_400MV_0DB_HSW;
2304         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2305                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2306         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2307                 return DDI_BUF_EMP_400MV_6DB_HSW;
2308         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2309                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2310
2311         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2312                 return DDI_BUF_EMP_600MV_0DB_HSW;
2313         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2315         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2316                 return DDI_BUF_EMP_600MV_6DB_HSW;
2317
2318         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2319                 return DDI_BUF_EMP_800MV_0DB_HSW;
2320         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2321                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2322         default:
2323                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2324                               "0x%x\n", signal_levels);
2325                 return DDI_BUF_EMP_400MV_0DB_HSW;
2326         }
2327 }
2328
2329 static uint32_t
2330 intel_bdw_signal_levels(uint8_t train_set)
2331 {
2332         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2333                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2334         switch (signal_levels) {
2335         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2336                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2337         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2338                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2339         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2340                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2341
2342         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2343                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2344         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2345                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2346         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2347                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2348
2349         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2350                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2351         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2352                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2353
2354         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2355                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2356
2357         default:
2358                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2359                               "0x%x\n", signal_levels);
2360                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2361         }
2362 }
2363
2364 /* Properly updates "DP" with the correct signal levels. */
2365 static void
2366 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2367 {
2368         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2369         enum port port = intel_dig_port->port;
2370         struct drm_device *dev = intel_dig_port->base.base.dev;
2371         uint32_t signal_levels, mask;
2372         uint8_t train_set = intel_dp->train_set[0];
2373
2374         if (IS_BROADWELL(dev)) {
2375                 signal_levels = intel_bdw_signal_levels(train_set);
2376                 mask = DDI_BUF_EMP_MASK;
2377         } else if (IS_HASWELL(dev)) {
2378                 signal_levels = intel_hsw_signal_levels(train_set);
2379                 mask = DDI_BUF_EMP_MASK;
2380         } else if (IS_VALLEYVIEW(dev)) {
2381                 signal_levels = intel_vlv_signal_levels(intel_dp);
2382                 mask = 0;
2383         } else if (IS_GEN7(dev) && port == PORT_A) {
2384                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2385                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2386         } else if (IS_GEN6(dev) && port == PORT_A) {
2387                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2388                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2389         } else {
2390                 signal_levels = intel_gen4_signal_levels(train_set);
2391                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2392         }
2393
2394         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2395
2396         *DP = (*DP & ~mask) | signal_levels;
2397 }
2398
2399 static bool
2400 intel_dp_set_link_train(struct intel_dp *intel_dp,
2401                         uint32_t *DP,
2402                         uint8_t dp_train_pat)
2403 {
2404         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2405         struct drm_device *dev = intel_dig_port->base.base.dev;
2406         struct drm_i915_private *dev_priv = dev->dev_private;
2407         enum port port = intel_dig_port->port;
2408         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2409         int ret, len;
2410
2411         if (HAS_DDI(dev)) {
2412                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2413
2414                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2415                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2416                 else
2417                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2418
2419                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2420                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2421                 case DP_TRAINING_PATTERN_DISABLE:
2422                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2423
2424                         break;
2425                 case DP_TRAINING_PATTERN_1:
2426                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2427                         break;
2428                 case DP_TRAINING_PATTERN_2:
2429                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2430                         break;
2431                 case DP_TRAINING_PATTERN_3:
2432                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2433                         break;
2434                 }
2435                 I915_WRITE(DP_TP_CTL(port), temp);
2436
2437         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2438                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2439
2440                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2441                 case DP_TRAINING_PATTERN_DISABLE:
2442                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2443                         break;
2444                 case DP_TRAINING_PATTERN_1:
2445                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2446                         break;
2447                 case DP_TRAINING_PATTERN_2:
2448                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2449                         break;
2450                 case DP_TRAINING_PATTERN_3:
2451                         DRM_ERROR("DP training pattern 3 not supported\n");
2452                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2453                         break;
2454                 }
2455
2456         } else {
2457                 *DP &= ~DP_LINK_TRAIN_MASK;
2458
2459                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2460                 case DP_TRAINING_PATTERN_DISABLE:
2461                         *DP |= DP_LINK_TRAIN_OFF;
2462                         break;
2463                 case DP_TRAINING_PATTERN_1:
2464                         *DP |= DP_LINK_TRAIN_PAT_1;
2465                         break;
2466                 case DP_TRAINING_PATTERN_2:
2467                         *DP |= DP_LINK_TRAIN_PAT_2;
2468                         break;
2469                 case DP_TRAINING_PATTERN_3:
2470                         DRM_ERROR("DP training pattern 3 not supported\n");
2471                         *DP |= DP_LINK_TRAIN_PAT_2;
2472                         break;
2473                 }
2474         }
2475
2476         I915_WRITE(intel_dp->output_reg, *DP);
2477         POSTING_READ(intel_dp->output_reg);
2478
2479         buf[0] = dp_train_pat;
2480         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2481             DP_TRAINING_PATTERN_DISABLE) {
2482                 /* don't write DP_TRAINING_LANEx_SET on disable */
2483                 len = 1;
2484         } else {
2485                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2486                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2487                 len = intel_dp->lane_count + 1;
2488         }
2489
2490         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2491                                 buf, len);
2492
2493         return ret == len;
2494 }
2495
2496 static bool
2497 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2498                         uint8_t dp_train_pat)
2499 {
2500         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2501         intel_dp_set_signal_levels(intel_dp, DP);
2502         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2503 }
2504
2505 static bool
2506 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2507                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2508 {
2509         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2510         struct drm_device *dev = intel_dig_port->base.base.dev;
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512         int ret;
2513
2514         intel_get_adjust_train(intel_dp, link_status);
2515         intel_dp_set_signal_levels(intel_dp, DP);
2516
2517         I915_WRITE(intel_dp->output_reg, *DP);
2518         POSTING_READ(intel_dp->output_reg);
2519
2520         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2521                                 intel_dp->train_set, intel_dp->lane_count);
2522
2523         return ret == intel_dp->lane_count;
2524 }
2525
2526 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2527 {
2528         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2529         struct drm_device *dev = intel_dig_port->base.base.dev;
2530         struct drm_i915_private *dev_priv = dev->dev_private;
2531         enum port port = intel_dig_port->port;
2532         uint32_t val;
2533
2534         if (!HAS_DDI(dev))
2535                 return;
2536
2537         val = I915_READ(DP_TP_CTL(port));
2538         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2539         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2540         I915_WRITE(DP_TP_CTL(port), val);
2541
2542         /*
2543          * On PORT_A we can have only eDP in SST mode. There the only reason
2544          * we need to set idle transmission mode is to work around a HW issue
2545          * where we enable the pipe while not in idle link-training mode.
2546          * In this case there is requirement to wait for a minimum number of
2547          * idle patterns to be sent.
2548          */
2549         if (port == PORT_A)
2550                 return;
2551
2552         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2553                      1))
2554                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2555 }
2556
2557 /* Enable corresponding port and start training pattern 1 */
2558 void
2559 intel_dp_start_link_train(struct intel_dp *intel_dp)
2560 {
2561         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2562         struct drm_device *dev = encoder->dev;
2563         int i;
2564         uint8_t voltage;
2565         int voltage_tries, loop_tries;
2566         uint32_t DP = intel_dp->DP;
2567         uint8_t link_config[2];
2568
2569         if (HAS_DDI(dev))
2570                 intel_ddi_prepare_link_retrain(encoder);
2571
2572         /* Write the link configuration data */
2573         link_config[0] = intel_dp->link_bw;
2574         link_config[1] = intel_dp->lane_count;
2575         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2576                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2577         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2578
2579         link_config[0] = 0;
2580         link_config[1] = DP_SET_ANSI_8B10B;
2581         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2582
2583         DP |= DP_PORT_EN;
2584
2585         /* clock recovery */
2586         if (!intel_dp_reset_link_train(intel_dp, &DP,
2587                                        DP_TRAINING_PATTERN_1 |
2588                                        DP_LINK_SCRAMBLING_DISABLE)) {
2589                 DRM_ERROR("failed to enable link training\n");
2590                 return;
2591         }
2592
2593         voltage = 0xff;
2594         voltage_tries = 0;
2595         loop_tries = 0;
2596         for (;;) {
2597                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2598
2599                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2600                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2601                         DRM_ERROR("failed to get link status\n");
2602                         break;
2603                 }
2604
2605                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2606                         DRM_DEBUG_KMS("clock recovery OK\n");
2607                         break;
2608                 }
2609
2610                 /* Check to see if we've tried the max voltage */
2611                 for (i = 0; i < intel_dp->lane_count; i++)
2612                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2613                                 break;
2614                 if (i == intel_dp->lane_count) {
2615                         ++loop_tries;
2616                         if (loop_tries == 5) {
2617                                 DRM_ERROR("too many full retries, give up\n");
2618                                 break;
2619                         }
2620                         intel_dp_reset_link_train(intel_dp, &DP,
2621                                                   DP_TRAINING_PATTERN_1 |
2622                                                   DP_LINK_SCRAMBLING_DISABLE);
2623                         voltage_tries = 0;
2624                         continue;
2625                 }
2626
2627                 /* Check to see if we've tried the same voltage 5 times */
2628                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2629                         ++voltage_tries;
2630                         if (voltage_tries == 5) {
2631                                 DRM_ERROR("too many voltage retries, give up\n");
2632                                 break;
2633                         }
2634                 } else
2635                         voltage_tries = 0;
2636                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2637
2638                 /* Update training set as requested by target */
2639                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2640                         DRM_ERROR("failed to update link training\n");
2641                         break;
2642                 }
2643         }
2644
2645         intel_dp->DP = DP;
2646 }
2647
2648 void
2649 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2650 {
2651         bool channel_eq = false;
2652         int tries, cr_tries;
2653         uint32_t DP = intel_dp->DP;
2654         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2655
2656         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2657         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2658                 training_pattern = DP_TRAINING_PATTERN_3;
2659
2660         /* channel equalization */
2661         if (!intel_dp_set_link_train(intel_dp, &DP,
2662                                      training_pattern |
2663                                      DP_LINK_SCRAMBLING_DISABLE)) {
2664                 DRM_ERROR("failed to start channel equalization\n");
2665                 return;
2666         }
2667
2668         tries = 0;
2669         cr_tries = 0;
2670         channel_eq = false;
2671         for (;;) {
2672                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2673
2674                 if (cr_tries > 5) {
2675                         DRM_ERROR("failed to train DP, aborting\n");
2676                         break;
2677                 }
2678
2679                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2680                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2681                         DRM_ERROR("failed to get link status\n");
2682                         break;
2683                 }
2684
2685                 /* Make sure clock is still ok */
2686                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2687                         intel_dp_start_link_train(intel_dp);
2688                         intel_dp_set_link_train(intel_dp, &DP,
2689                                                 training_pattern |
2690                                                 DP_LINK_SCRAMBLING_DISABLE);
2691                         cr_tries++;
2692                         continue;
2693                 }
2694
2695                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2696                         channel_eq = true;
2697                         break;
2698                 }
2699
2700                 /* Try 5 times, then try clock recovery if that fails */
2701                 if (tries > 5) {
2702                         intel_dp_link_down(intel_dp);
2703                         intel_dp_start_link_train(intel_dp);
2704                         intel_dp_set_link_train(intel_dp, &DP,
2705                                                 training_pattern |
2706                                                 DP_LINK_SCRAMBLING_DISABLE);
2707                         tries = 0;
2708                         cr_tries++;
2709                         continue;
2710                 }
2711
2712                 /* Update training set as requested by target */
2713                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2714                         DRM_ERROR("failed to update link training\n");
2715                         break;
2716                 }
2717                 ++tries;
2718         }
2719
2720         intel_dp_set_idle_link_train(intel_dp);
2721
2722         intel_dp->DP = DP;
2723
2724         if (channel_eq)
2725                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2726
2727 }
2728
2729 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2730 {
2731         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2732                                 DP_TRAINING_PATTERN_DISABLE);
2733 }
2734
2735 static void
2736 intel_dp_link_down(struct intel_dp *intel_dp)
2737 {
2738         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2739         enum port port = intel_dig_port->port;
2740         struct drm_device *dev = intel_dig_port->base.base.dev;
2741         struct drm_i915_private *dev_priv = dev->dev_private;
2742         struct intel_crtc *intel_crtc =
2743                 to_intel_crtc(intel_dig_port->base.base.crtc);
2744         uint32_t DP = intel_dp->DP;
2745
2746         /*
2747          * DDI code has a strict mode set sequence and we should try to respect
2748          * it, otherwise we might hang the machine in many different ways. So we
2749          * really should be disabling the port only on a complete crtc_disable
2750          * sequence. This function is just called under two conditions on DDI
2751          * code:
2752          * - Link train failed while doing crtc_enable, and on this case we
2753          *   really should respect the mode set sequence and wait for a
2754          *   crtc_disable.
2755          * - Someone turned the monitor off and intel_dp_check_link_status
2756          *   called us. We don't need to disable the whole port on this case, so
2757          *   when someone turns the monitor on again,
2758          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2759          *   train.
2760          */
2761         if (HAS_DDI(dev))
2762                 return;
2763
2764         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2765                 return;
2766
2767         DRM_DEBUG_KMS("\n");
2768
2769         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2770                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2771                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2772         } else {
2773                 DP &= ~DP_LINK_TRAIN_MASK;
2774                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2775         }
2776         POSTING_READ(intel_dp->output_reg);
2777
2778         /* We don't really know why we're doing this */
2779         intel_wait_for_vblank(dev, intel_crtc->pipe);
2780
2781         if (HAS_PCH_IBX(dev) &&
2782             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2783                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2784
2785                 /* Hardware workaround: leaving our transcoder select
2786                  * set to transcoder B while it's off will prevent the
2787                  * corresponding HDMI output on transcoder A.
2788                  *
2789                  * Combine this with another hardware workaround:
2790                  * transcoder select bit can only be cleared while the
2791                  * port is enabled.
2792                  */
2793                 DP &= ~DP_PIPEB_SELECT;
2794                 I915_WRITE(intel_dp->output_reg, DP);
2795
2796                 /* Changes to enable or select take place the vblank
2797                  * after being written.
2798                  */
2799                 if (WARN_ON(crtc == NULL)) {
2800                         /* We should never try to disable a port without a crtc
2801                          * attached. For paranoia keep the code around for a
2802                          * bit. */
2803                         POSTING_READ(intel_dp->output_reg);
2804                         msleep(50);
2805                 } else
2806                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2807         }
2808
2809         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2810         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2811         POSTING_READ(intel_dp->output_reg);
2812         msleep(intel_dp->panel_power_down_delay);
2813 }
2814
2815 static bool
2816 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2817 {
2818         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2819         struct drm_device *dev = dig_port->base.base.dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821
2822         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2823
2824         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2825                                     sizeof(intel_dp->dpcd)) < 0)
2826                 return false; /* aux transfer failed */
2827
2828         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2829                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2830         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2831
2832         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2833                 return false; /* DPCD not present */
2834
2835         /* Check if the panel supports PSR */
2836         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2837         if (is_edp(intel_dp)) {
2838                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2839                                         intel_dp->psr_dpcd,
2840                                         sizeof(intel_dp->psr_dpcd));
2841                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2842                         dev_priv->psr.sink_support = true;
2843                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2844                 }
2845         }
2846
2847         /* Training Pattern 3 support */
2848         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2849             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2850                 intel_dp->use_tps3 = true;
2851                 DRM_DEBUG_KMS("Displayport TPS3 supported");
2852         } else
2853                 intel_dp->use_tps3 = false;
2854
2855         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2856               DP_DWN_STRM_PORT_PRESENT))
2857                 return true; /* native DP sink */
2858
2859         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2860                 return true; /* no per-port downstream info */
2861
2862         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2863                                     intel_dp->downstream_ports,
2864                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
2865                 return false; /* downstream port status fetch failed */
2866
2867         return true;
2868 }
2869
2870 static void
2871 intel_dp_probe_oui(struct intel_dp *intel_dp)
2872 {
2873         u8 buf[3];
2874
2875         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2876                 return;
2877
2878         intel_edp_panel_vdd_on(intel_dp);
2879
2880         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2881                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2882                               buf[0], buf[1], buf[2]);
2883
2884         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2885                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2886                               buf[0], buf[1], buf[2]);
2887
2888         edp_panel_vdd_off(intel_dp, false);
2889 }
2890
2891 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2892 {
2893         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2894         struct drm_device *dev = intel_dig_port->base.base.dev;
2895         struct intel_crtc *intel_crtc =
2896                 to_intel_crtc(intel_dig_port->base.base.crtc);
2897         u8 buf[1];
2898
2899         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2900                 return -EAGAIN;
2901
2902         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2903                 return -ENOTTY;
2904
2905         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2906                                DP_TEST_SINK_START) < 0)
2907                 return -EAGAIN;
2908
2909         /* Wait 2 vblanks to be sure we will have the correct CRC value */
2910         intel_wait_for_vblank(dev, intel_crtc->pipe);
2911         intel_wait_for_vblank(dev, intel_crtc->pipe);
2912
2913         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2914                 return -EAGAIN;
2915
2916         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2917         return 0;
2918 }
2919
2920 static bool
2921 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2922 {
2923         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2924                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
2925                                        sink_irq_vector, 1) == 1;
2926 }
2927
2928 static void
2929 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2930 {
2931         /* NAK by default */
2932         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2933 }
2934
2935 /*
2936  * According to DP spec
2937  * 5.1.2:
2938  *  1. Read DPCD
2939  *  2. Configure link according to Receiver Capabilities
2940  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2941  *  4. Check link status on receipt of hot-plug interrupt
2942  */
2943
2944 void
2945 intel_dp_check_link_status(struct intel_dp *intel_dp)
2946 {
2947         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2948         u8 sink_irq_vector;
2949         u8 link_status[DP_LINK_STATUS_SIZE];
2950
2951         if (!intel_encoder->connectors_active)
2952                 return;
2953
2954         if (WARN_ON(!intel_encoder->base.crtc))
2955                 return;
2956
2957         /* Try to read receiver status if the link appears to be up */
2958         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2959                 return;
2960         }
2961
2962         /* Now read the DPCD to see if it's actually running */
2963         if (!intel_dp_get_dpcd(intel_dp)) {
2964                 return;
2965         }
2966
2967         /* Try to read the source of the interrupt */
2968         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2969             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2970                 /* Clear interrupt source */
2971                 drm_dp_dpcd_writeb(&intel_dp->aux,
2972                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
2973                                    sink_irq_vector);
2974
2975                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2976                         intel_dp_handle_test_request(intel_dp);
2977                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2978                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2979         }
2980
2981         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2982                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2983                               drm_get_encoder_name(&intel_encoder->base));
2984                 intel_dp_start_link_train(intel_dp);
2985                 intel_dp_complete_link_train(intel_dp);
2986                 intel_dp_stop_link_train(intel_dp);
2987         }
2988 }
2989
2990 /* XXX this is probably wrong for multiple downstream ports */
2991 static enum drm_connector_status
2992 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2993 {
2994         uint8_t *dpcd = intel_dp->dpcd;
2995         uint8_t type;
2996
2997         if (!intel_dp_get_dpcd(intel_dp))
2998                 return connector_status_disconnected;
2999
3000         /* if there's no downstream port, we're done */
3001         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3002                 return connector_status_connected;
3003
3004         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3005         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3006             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3007                 uint8_t reg;
3008
3009                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3010                                             &reg, 1) < 0)
3011                         return connector_status_unknown;
3012
3013                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3014                                               : connector_status_disconnected;
3015         }
3016
3017         /* If no HPD, poke DDC gently */
3018         if (drm_probe_ddc(&intel_dp->aux.ddc))
3019                 return connector_status_connected;
3020
3021         /* Well we tried, say unknown for unreliable port types */
3022         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3023                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3024                 if (type == DP_DS_PORT_TYPE_VGA ||
3025                     type == DP_DS_PORT_TYPE_NON_EDID)
3026                         return connector_status_unknown;
3027         } else {
3028                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3029                         DP_DWN_STRM_PORT_TYPE_MASK;
3030                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3031                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3032                         return connector_status_unknown;
3033         }
3034
3035         /* Anything else is out of spec, warn and ignore */
3036         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3037         return connector_status_disconnected;
3038 }
3039
3040 static enum drm_connector_status
3041 ironlake_dp_detect(struct intel_dp *intel_dp)
3042 {
3043         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3046         enum drm_connector_status status;
3047
3048         /* Can't disconnect eDP, but you can close the lid... */
3049         if (is_edp(intel_dp)) {
3050                 status = intel_panel_detect(dev);
3051                 if (status == connector_status_unknown)
3052                         status = connector_status_connected;
3053                 return status;
3054         }
3055
3056         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3057                 return connector_status_disconnected;
3058
3059         return intel_dp_detect_dpcd(intel_dp);
3060 }
3061
3062 static enum drm_connector_status
3063 g4x_dp_detect(struct intel_dp *intel_dp)
3064 {
3065         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3066         struct drm_i915_private *dev_priv = dev->dev_private;
3067         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3068         uint32_t bit;
3069
3070         /* Can't disconnect eDP, but you can close the lid... */
3071         if (is_edp(intel_dp)) {
3072                 enum drm_connector_status status;
3073
3074                 status = intel_panel_detect(dev);
3075                 if (status == connector_status_unknown)
3076                         status = connector_status_connected;
3077                 return status;
3078         }
3079
3080         if (IS_VALLEYVIEW(dev)) {
3081                 switch (intel_dig_port->port) {
3082                 case PORT_B:
3083                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3084                         break;
3085                 case PORT_C:
3086                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3087                         break;
3088                 case PORT_D:
3089                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3090                         break;
3091                 default:
3092                         return connector_status_unknown;
3093                 }
3094         } else {
3095                 switch (intel_dig_port->port) {
3096                 case PORT_B:
3097                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3098                         break;
3099                 case PORT_C:
3100                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3101                         break;
3102                 case PORT_D:
3103                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3104                         break;
3105                 default:
3106                         return connector_status_unknown;
3107                 }
3108         }
3109
3110         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3111                 return connector_status_disconnected;
3112
3113         return intel_dp_detect_dpcd(intel_dp);
3114 }
3115
3116 static struct edid *
3117 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3118 {
3119         struct intel_connector *intel_connector = to_intel_connector(connector);
3120
3121         /* use cached edid if we have one */
3122         if (intel_connector->edid) {
3123                 /* invalid edid */
3124                 if (IS_ERR(intel_connector->edid))
3125                         return NULL;
3126
3127                 return drm_edid_duplicate(intel_connector->edid);
3128         }
3129
3130         return drm_get_edid(connector, adapter);
3131 }
3132
3133 static int
3134 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3135 {
3136         struct intel_connector *intel_connector = to_intel_connector(connector);
3137
3138         /* use cached edid if we have one */
3139         if (intel_connector->edid) {
3140                 /* invalid edid */
3141                 if (IS_ERR(intel_connector->edid))
3142                         return 0;
3143
3144                 return intel_connector_update_modes(connector,
3145                                                     intel_connector->edid);
3146         }
3147
3148         return intel_ddc_get_modes(connector, adapter);
3149 }
3150
3151 static enum drm_connector_status
3152 intel_dp_detect(struct drm_connector *connector, bool force)
3153 {
3154         struct intel_dp *intel_dp = intel_attached_dp(connector);
3155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3156         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3157         struct drm_device *dev = connector->dev;
3158         struct drm_i915_private *dev_priv = dev->dev_private;
3159         enum drm_connector_status status;
3160         enum intel_display_power_domain power_domain;
3161         struct edid *edid = NULL;
3162
3163         intel_runtime_pm_get(dev_priv);
3164
3165         power_domain = intel_display_port_power_domain(intel_encoder);
3166         intel_display_power_get(dev_priv, power_domain);
3167
3168         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3169                       connector->base.id, drm_get_connector_name(connector));
3170
3171         intel_dp->has_audio = false;
3172
3173         if (HAS_PCH_SPLIT(dev))
3174                 status = ironlake_dp_detect(intel_dp);
3175         else
3176                 status = g4x_dp_detect(intel_dp);
3177
3178         if (status != connector_status_connected)
3179                 goto out;
3180
3181         intel_dp_probe_oui(intel_dp);
3182
3183         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3184                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3185         } else {
3186                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3187                 if (edid) {
3188                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3189                         kfree(edid);
3190                 }
3191         }
3192
3193         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3194                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3195         status = connector_status_connected;
3196
3197 out:
3198         intel_display_power_put(dev_priv, power_domain);
3199
3200         intel_runtime_pm_put(dev_priv);
3201
3202         return status;
3203 }
3204
3205 static int intel_dp_get_modes(struct drm_connector *connector)
3206 {
3207         struct intel_dp *intel_dp = intel_attached_dp(connector);
3208         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3209         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3210         struct intel_connector *intel_connector = to_intel_connector(connector);
3211         struct drm_device *dev = connector->dev;
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         enum intel_display_power_domain power_domain;
3214         int ret;
3215
3216         /* We should parse the EDID data and find out if it has an audio sink
3217          */
3218
3219         power_domain = intel_display_port_power_domain(intel_encoder);
3220         intel_display_power_get(dev_priv, power_domain);
3221
3222         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3223         intel_display_power_put(dev_priv, power_domain);
3224         if (ret)
3225                 return ret;
3226
3227         /* if eDP has no EDID, fall back to fixed mode */
3228         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3229                 struct drm_display_mode *mode;
3230                 mode = drm_mode_duplicate(dev,
3231                                           intel_connector->panel.fixed_mode);
3232                 if (mode) {
3233                         drm_mode_probed_add(connector, mode);
3234                         return 1;
3235                 }
3236         }
3237         return 0;
3238 }
3239
3240 static bool
3241 intel_dp_detect_audio(struct drm_connector *connector)
3242 {
3243         struct intel_dp *intel_dp = intel_attached_dp(connector);
3244         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3245         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3246         struct drm_device *dev = connector->dev;
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         enum intel_display_power_domain power_domain;
3249         struct edid *edid;
3250         bool has_audio = false;
3251
3252         power_domain = intel_display_port_power_domain(intel_encoder);
3253         intel_display_power_get(dev_priv, power_domain);
3254
3255         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3256         if (edid) {
3257                 has_audio = drm_detect_monitor_audio(edid);
3258                 kfree(edid);
3259         }
3260
3261         intel_display_power_put(dev_priv, power_domain);
3262
3263         return has_audio;
3264 }
3265
3266 static int
3267 intel_dp_set_property(struct drm_connector *connector,
3268                       struct drm_property *property,
3269                       uint64_t val)
3270 {
3271         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3272         struct intel_connector *intel_connector = to_intel_connector(connector);
3273         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3274         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3275         int ret;
3276
3277         ret = drm_object_property_set_value(&connector->base, property, val);
3278         if (ret)
3279                 return ret;
3280
3281         if (property == dev_priv->force_audio_property) {
3282                 int i = val;
3283                 bool has_audio;
3284
3285                 if (i == intel_dp->force_audio)
3286                         return 0;
3287
3288                 intel_dp->force_audio = i;
3289
3290                 if (i == HDMI_AUDIO_AUTO)
3291                         has_audio = intel_dp_detect_audio(connector);
3292                 else
3293                         has_audio = (i == HDMI_AUDIO_ON);
3294
3295                 if (has_audio == intel_dp->has_audio)
3296                         return 0;
3297
3298                 intel_dp->has_audio = has_audio;
3299                 goto done;
3300         }
3301
3302         if (property == dev_priv->broadcast_rgb_property) {
3303                 bool old_auto = intel_dp->color_range_auto;
3304                 uint32_t old_range = intel_dp->color_range;
3305
3306                 switch (val) {
3307                 case INTEL_BROADCAST_RGB_AUTO:
3308                         intel_dp->color_range_auto = true;
3309                         break;
3310                 case INTEL_BROADCAST_RGB_FULL:
3311                         intel_dp->color_range_auto = false;
3312                         intel_dp->color_range = 0;
3313                         break;
3314                 case INTEL_BROADCAST_RGB_LIMITED:
3315                         intel_dp->color_range_auto = false;
3316                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3317                         break;
3318                 default:
3319                         return -EINVAL;
3320                 }
3321
3322                 if (old_auto == intel_dp->color_range_auto &&
3323                     old_range == intel_dp->color_range)
3324                         return 0;
3325
3326                 goto done;
3327         }
3328
3329         if (is_edp(intel_dp) &&
3330             property == connector->dev->mode_config.scaling_mode_property) {
3331                 if (val == DRM_MODE_SCALE_NONE) {
3332                         DRM_DEBUG_KMS("no scaling not supported\n");
3333                         return -EINVAL;
3334                 }
3335
3336                 if (intel_connector->panel.fitting_mode == val) {
3337                         /* the eDP scaling property is not changed */
3338                         return 0;
3339                 }
3340                 intel_connector->panel.fitting_mode = val;
3341
3342                 goto done;
3343         }
3344
3345         return -EINVAL;
3346
3347 done:
3348         if (intel_encoder->base.crtc)
3349                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3350
3351         return 0;
3352 }
3353
3354 static void
3355 intel_dp_connector_destroy(struct drm_connector *connector)
3356 {
3357         struct intel_connector *intel_connector = to_intel_connector(connector);
3358
3359         if (!IS_ERR_OR_NULL(intel_connector->edid))
3360                 kfree(intel_connector->edid);
3361
3362         /* Can't call is_edp() since the encoder may have been destroyed
3363          * already. */
3364         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3365                 intel_panel_fini(&intel_connector->panel);
3366
3367         drm_connector_cleanup(connector);
3368         kfree(connector);
3369 }
3370
3371 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3372 {
3373         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3374         struct intel_dp *intel_dp = &intel_dig_port->dp;
3375         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3376
3377         drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3378         drm_encoder_cleanup(encoder);
3379         if (is_edp(intel_dp)) {
3380                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3381                 mutex_lock(&dev->mode_config.mutex);
3382                 edp_panel_vdd_off_sync(intel_dp);
3383                 mutex_unlock(&dev->mode_config.mutex);
3384         }
3385         kfree(intel_dig_port);
3386 }
3387
3388 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3389         .dpms = intel_connector_dpms,
3390         .detect = intel_dp_detect,
3391         .fill_modes = drm_helper_probe_single_connector_modes,
3392         .set_property = intel_dp_set_property,
3393         .destroy = intel_dp_connector_destroy,
3394 };
3395
3396 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3397         .get_modes = intel_dp_get_modes,
3398         .mode_valid = intel_dp_mode_valid,
3399         .best_encoder = intel_best_encoder,
3400 };
3401
3402 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3403         .destroy = intel_dp_encoder_destroy,
3404 };
3405
3406 static void
3407 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3408 {
3409         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3410
3411         intel_dp_check_link_status(intel_dp);
3412 }
3413
3414 /* Return which DP Port should be selected for Transcoder DP control */
3415 int
3416 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3417 {
3418         struct drm_device *dev = crtc->dev;
3419         struct intel_encoder *intel_encoder;
3420         struct intel_dp *intel_dp;
3421
3422         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3423                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3424
3425                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3426                     intel_encoder->type == INTEL_OUTPUT_EDP)
3427                         return intel_dp->output_reg;
3428         }
3429
3430         return -1;
3431 }
3432
3433 /* check the VBT to see whether the eDP is on DP-D port */
3434 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3435 {
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         union child_device_config *p_child;
3438         int i;
3439         static const short port_mapping[] = {
3440                 [PORT_B] = PORT_IDPB,
3441                 [PORT_C] = PORT_IDPC,
3442                 [PORT_D] = PORT_IDPD,
3443         };
3444
3445         if (port == PORT_A)
3446                 return true;
3447
3448         if (!dev_priv->vbt.child_dev_num)
3449                 return false;
3450
3451         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3452                 p_child = dev_priv->vbt.child_dev + i;
3453
3454                 if (p_child->common.dvo_port == port_mapping[port] &&
3455                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3456                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3457                         return true;
3458         }
3459         return false;
3460 }
3461
3462 static void
3463 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3464 {
3465         struct intel_connector *intel_connector = to_intel_connector(connector);
3466
3467         intel_attach_force_audio_property(connector);
3468         intel_attach_broadcast_rgb_property(connector);
3469         intel_dp->color_range_auto = true;
3470
3471         if (is_edp(intel_dp)) {
3472                 drm_mode_create_scaling_mode_property(connector->dev);
3473                 drm_object_attach_property(
3474                         &connector->base,
3475                         connector->dev->mode_config.scaling_mode_property,
3476                         DRM_MODE_SCALE_ASPECT);
3477                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3478         }
3479 }
3480
3481 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3482 {
3483         intel_dp->last_power_cycle = jiffies;
3484         intel_dp->last_power_on = jiffies;
3485         intel_dp->last_backlight_off = jiffies;
3486 }
3487
3488 static void
3489 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3490                                     struct intel_dp *intel_dp,
3491                                     struct edp_power_seq *out)
3492 {
3493         struct drm_i915_private *dev_priv = dev->dev_private;
3494         struct edp_power_seq cur, vbt, spec, final;
3495         u32 pp_on, pp_off, pp_div, pp;
3496         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3497
3498         if (HAS_PCH_SPLIT(dev)) {
3499                 pp_ctrl_reg = PCH_PP_CONTROL;
3500                 pp_on_reg = PCH_PP_ON_DELAYS;
3501                 pp_off_reg = PCH_PP_OFF_DELAYS;
3502                 pp_div_reg = PCH_PP_DIVISOR;
3503         } else {
3504                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3505
3506                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3507                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3508                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3509                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3510         }
3511
3512         /* Workaround: Need to write PP_CONTROL with the unlock key as
3513          * the very first thing. */
3514         pp = ironlake_get_pp_control(intel_dp);
3515         I915_WRITE(pp_ctrl_reg, pp);
3516
3517         pp_on = I915_READ(pp_on_reg);
3518         pp_off = I915_READ(pp_off_reg);
3519         pp_div = I915_READ(pp_div_reg);
3520
3521         /* Pull timing values out of registers */
3522         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3523                 PANEL_POWER_UP_DELAY_SHIFT;
3524
3525         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3526                 PANEL_LIGHT_ON_DELAY_SHIFT;
3527
3528         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3529                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3530
3531         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3532                 PANEL_POWER_DOWN_DELAY_SHIFT;
3533
3534         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3535                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3536
3537         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3538                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3539
3540         vbt = dev_priv->vbt.edp_pps;
3541
3542         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3543          * our hw here, which are all in 100usec. */
3544         spec.t1_t3 = 210 * 10;
3545         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3546         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3547         spec.t10 = 500 * 10;
3548         /* This one is special and actually in units of 100ms, but zero
3549          * based in the hw (so we need to add 100 ms). But the sw vbt
3550          * table multiplies it with 1000 to make it in units of 100usec,
3551          * too. */
3552         spec.t11_t12 = (510 + 100) * 10;
3553
3554         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3555                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3556
3557         /* Use the max of the register settings and vbt. If both are
3558          * unset, fall back to the spec limits. */
3559 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3560                                        spec.field : \
3561                                        max(cur.field, vbt.field))
3562         assign_final(t1_t3);
3563         assign_final(t8);
3564         assign_final(t9);
3565         assign_final(t10);
3566         assign_final(t11_t12);
3567 #undef assign_final
3568
3569 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3570         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3571         intel_dp->backlight_on_delay = get_delay(t8);
3572         intel_dp->backlight_off_delay = get_delay(t9);
3573         intel_dp->panel_power_down_delay = get_delay(t10);
3574         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3575 #undef get_delay
3576
3577         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3578                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3579                       intel_dp->panel_power_cycle_delay);
3580
3581         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3582                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3583
3584         if (out)
3585                 *out = final;
3586 }
3587
3588 static void
3589 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3590                                               struct intel_dp *intel_dp,
3591                                               struct edp_power_seq *seq)
3592 {
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594         u32 pp_on, pp_off, pp_div, port_sel = 0;
3595         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3596         int pp_on_reg, pp_off_reg, pp_div_reg;
3597
3598         if (HAS_PCH_SPLIT(dev)) {
3599                 pp_on_reg = PCH_PP_ON_DELAYS;
3600                 pp_off_reg = PCH_PP_OFF_DELAYS;
3601                 pp_div_reg = PCH_PP_DIVISOR;
3602         } else {
3603                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3604
3605                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3606                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3607                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3608         }
3609
3610         /*
3611          * And finally store the new values in the power sequencer. The
3612          * backlight delays are set to 1 because we do manual waits on them. For
3613          * T8, even BSpec recommends doing it. For T9, if we don't do this,
3614          * we'll end up waiting for the backlight off delay twice: once when we
3615          * do the manual sleep, and once when we disable the panel and wait for
3616          * the PP_STATUS bit to become zero.
3617          */
3618         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3619                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3620         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3621                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3622         /* Compute the divisor for the pp clock, simply match the Bspec
3623          * formula. */
3624         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3625         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3626                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3627
3628         /* Haswell doesn't have any port selection bits for the panel
3629          * power sequencer any more. */
3630         if (IS_VALLEYVIEW(dev)) {
3631                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3632                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3633                 else
3634                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3635         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3636                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3637                         port_sel = PANEL_PORT_SELECT_DPA;
3638                 else
3639                         port_sel = PANEL_PORT_SELECT_DPD;
3640         }
3641
3642         pp_on |= port_sel;
3643
3644         I915_WRITE(pp_on_reg, pp_on);
3645         I915_WRITE(pp_off_reg, pp_off);
3646         I915_WRITE(pp_div_reg, pp_div);
3647
3648         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3649                       I915_READ(pp_on_reg),
3650                       I915_READ(pp_off_reg),
3651                       I915_READ(pp_div_reg));
3652 }
3653
3654 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3655                                      struct intel_connector *intel_connector,
3656                                      struct edp_power_seq *power_seq)
3657 {
3658         struct drm_connector *connector = &intel_connector->base;
3659         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3660         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3661         struct drm_device *dev = intel_encoder->base.dev;
3662         struct drm_i915_private *dev_priv = dev->dev_private;
3663         struct drm_display_mode *fixed_mode = NULL;
3664         bool has_dpcd;
3665         struct drm_display_mode *scan;
3666         struct edid *edid;
3667
3668         if (!is_edp(intel_dp))
3669                 return true;
3670
3671         /* The VDD bit needs a power domain reference, so if the bit is already
3672          * enabled when we boot, grab this reference. */
3673         if (edp_have_panel_vdd(intel_dp)) {
3674                 enum intel_display_power_domain power_domain;
3675                 power_domain = intel_display_port_power_domain(intel_encoder);
3676                 intel_display_power_get(dev_priv, power_domain);
3677         }
3678
3679         /* Cache DPCD and EDID for edp. */
3680         intel_edp_panel_vdd_on(intel_dp);
3681         has_dpcd = intel_dp_get_dpcd(intel_dp);
3682         edp_panel_vdd_off(intel_dp, false);
3683
3684         if (has_dpcd) {
3685                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3686                         dev_priv->no_aux_handshake =
3687                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3688                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3689         } else {
3690                 /* if this fails, presume the device is a ghost */
3691                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3692                 return false;
3693         }
3694
3695         /* We now know it's not a ghost, init power sequence regs. */
3696         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3697
3698         mutex_lock(&dev->mode_config.mutex);
3699         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3700         if (edid) {
3701                 if (drm_add_edid_modes(connector, edid)) {
3702                         drm_mode_connector_update_edid_property(connector,
3703                                                                 edid);
3704                         drm_edid_to_eld(connector, edid);
3705                 } else {
3706                         kfree(edid);
3707                         edid = ERR_PTR(-EINVAL);
3708                 }
3709         } else {
3710                 edid = ERR_PTR(-ENOENT);
3711         }
3712         intel_connector->edid = edid;
3713
3714         /* prefer fixed mode from EDID if available */
3715         list_for_each_entry(scan, &connector->probed_modes, head) {
3716                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3717                         fixed_mode = drm_mode_duplicate(dev, scan);
3718                         break;
3719                 }
3720         }
3721
3722         /* fallback to VBT if available for eDP */
3723         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3724                 fixed_mode = drm_mode_duplicate(dev,
3725                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3726                 if (fixed_mode)
3727                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3728         }
3729         mutex_unlock(&dev->mode_config.mutex);
3730
3731         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3732         intel_panel_setup_backlight(connector);
3733
3734         return true;
3735 }
3736
3737 bool
3738 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3739                         struct intel_connector *intel_connector)
3740 {
3741         struct drm_connector *connector = &intel_connector->base;
3742         struct intel_dp *intel_dp = &intel_dig_port->dp;
3743         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3744         struct drm_device *dev = intel_encoder->base.dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         enum port port = intel_dig_port->port;
3747         struct edp_power_seq power_seq = { 0 };
3748         int type;
3749
3750         /* intel_dp vfuncs */
3751         if (IS_VALLEYVIEW(dev))
3752                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3753         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3754                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3755         else if (HAS_PCH_SPLIT(dev))
3756                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3757         else
3758                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3759
3760         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3761
3762         /* Preserve the current hw state. */
3763         intel_dp->DP = I915_READ(intel_dp->output_reg);
3764         intel_dp->attached_connector = intel_connector;
3765
3766         if (intel_dp_is_edp(dev, port))
3767                 type = DRM_MODE_CONNECTOR_eDP;
3768         else
3769                 type = DRM_MODE_CONNECTOR_DisplayPort;
3770
3771         /*
3772          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3773          * for DP the encoder type can be set by the caller to
3774          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3775          */
3776         if (type == DRM_MODE_CONNECTOR_eDP)
3777                 intel_encoder->type = INTEL_OUTPUT_EDP;
3778
3779         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3780                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3781                         port_name(port));
3782
3783         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3784         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3785
3786         connector->interlace_allowed = true;
3787         connector->doublescan_allowed = 0;
3788
3789         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3790                           edp_panel_vdd_work);
3791
3792         intel_connector_attach_encoder(intel_connector, intel_encoder);
3793         drm_sysfs_connector_add(connector);
3794
3795         if (HAS_DDI(dev))
3796                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3797         else
3798                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3799         intel_connector->unregister = intel_dp_connector_unregister;
3800
3801         /* Set up the hotplug pin. */
3802         switch (port) {
3803         case PORT_A:
3804                 intel_encoder->hpd_pin = HPD_PORT_A;
3805                 break;
3806         case PORT_B:
3807                 intel_encoder->hpd_pin = HPD_PORT_B;
3808                 break;
3809         case PORT_C:
3810                 intel_encoder->hpd_pin = HPD_PORT_C;
3811                 break;
3812         case PORT_D:
3813                 intel_encoder->hpd_pin = HPD_PORT_D;
3814                 break;
3815         default:
3816                 BUG();
3817         }
3818
3819         if (is_edp(intel_dp)) {
3820                 intel_dp_init_panel_power_timestamps(intel_dp);
3821                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3822         }
3823
3824         intel_dp_aux_init(intel_dp, intel_connector);
3825
3826         intel_dp->psr_setup_done = false;
3827
3828         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3829                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3830                 if (is_edp(intel_dp)) {
3831                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3832                         mutex_lock(&dev->mode_config.mutex);
3833                         edp_panel_vdd_off_sync(intel_dp);
3834                         mutex_unlock(&dev->mode_config.mutex);
3835                 }
3836                 drm_sysfs_connector_remove(connector);
3837                 drm_connector_cleanup(connector);
3838                 return false;
3839         }
3840
3841         intel_dp_add_properties(intel_dp, connector);
3842
3843         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3844          * 0xd.  Failure to do so will result in spurious interrupts being
3845          * generated on the port when a cable is not attached.
3846          */
3847         if (IS_G4X(dev) && !IS_GM45(dev)) {
3848                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3849                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3850         }
3851
3852         return true;
3853 }
3854
3855 void
3856 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3857 {
3858         struct intel_digital_port *intel_dig_port;
3859         struct intel_encoder *intel_encoder;
3860         struct drm_encoder *encoder;
3861         struct intel_connector *intel_connector;
3862
3863         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3864         if (!intel_dig_port)
3865                 return;
3866
3867         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3868         if (!intel_connector) {
3869                 kfree(intel_dig_port);
3870                 return;
3871         }
3872
3873         intel_encoder = &intel_dig_port->base;
3874         encoder = &intel_encoder->base;
3875
3876         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3877                          DRM_MODE_ENCODER_TMDS);
3878
3879         intel_encoder->compute_config = intel_dp_compute_config;
3880         intel_encoder->mode_set = intel_dp_mode_set;
3881         intel_encoder->disable = intel_disable_dp;
3882         intel_encoder->post_disable = intel_post_disable_dp;
3883         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3884         intel_encoder->get_config = intel_dp_get_config;
3885         if (IS_VALLEYVIEW(dev)) {
3886                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3887                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3888                 intel_encoder->enable = vlv_enable_dp;
3889         } else {
3890                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3891                 intel_encoder->enable = g4x_enable_dp;
3892         }
3893
3894         intel_dig_port->port = port;
3895         intel_dig_port->dp.output_reg = output_reg;
3896
3897         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3898         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3899         intel_encoder->cloneable = 0;
3900         intel_encoder->hot_plug = intel_dp_hot_plug;
3901
3902         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3903                 drm_encoder_cleanup(encoder);
3904                 kfree(intel_dig_port);
3905                 kfree(intel_connector);
3906         }
3907 }