drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116
 117 int
 118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 119 {
 120         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 121         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 122
 123         switch (max_link_bw) {
 124         case DP_LINK_BW_1_62:
 125         case DP_LINK_BW_2_7:
 126                 break;
 127         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 128                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 129                      INTEL_INFO(dev)->gen >= 8) &&
 130                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 131                         max_link_bw = DP_LINK_BW_5_4;
 132                 else
 133                         max_link_bw = DP_LINK_BW_2_7;
 134                 break;
 135         default:
 136                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 137                      max_link_bw);
 138                 max_link_bw = DP_LINK_BW_1_62;
 139                 break;
 140         }
 141         return max_link_bw;
 142 }
 143
 144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 145 {
 146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 147         struct drm_device *dev = intel_dig_port->base.base.dev;
 148         u8 source_max, sink_max;
 149
 150         source_max = 4;
 151         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 152             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 153                 source_max = 2;
 154
 155         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 156
 157         return min(source_max, sink_max);
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static enum drm_mode_status
 190 intel_dp_mode_valid(struct drm_connector *connector,
 191                     struct drm_display_mode *mode)
 192 {
 193         struct intel_dp *intel_dp = intel_attached_dp(connector);
 194         struct intel_connector *intel_connector = to_intel_connector(connector);
 195         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 196         int target_clock = mode->clock;
 197         int max_rate, mode_rate, max_lanes, max_link_clock;
 198
 199         if (is_edp(intel_dp) && fixed_mode) {
 200                 if (mode->hdisplay > fixed_mode->hdisplay)
 201                         return MODE_PANEL;
 202
 203                 if (mode->vdisplay > fixed_mode->vdisplay)
 204                         return MODE_PANEL;
 205
 206                 target_clock = fixed_mode->clock;
 207         }
 208
 209         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 210         max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 213         mode_rate = intel_dp_link_required(target_clock, 18);
 214
 215         if (mode_rate > max_rate)
 216                 return MODE_CLOCK_HIGH;
 217
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 258         if (IS_VALLEYVIEW(dev))
 259                 return 200;
 260
 261         clkcfg = I915_READ(CLKCFG);
 262         switch (clkcfg & CLKCFG_FSB_MASK) {
 263         case CLKCFG_FSB_400:
 264                 return 100;
 265         case CLKCFG_FSB_533:
 266                 return 133;
 267         case CLKCFG_FSB_667:
 268                 return 166;
 269         case CLKCFG_FSB_800:
 270                 return 200;
 271         case CLKCFG_FSB_1067:
 272                 return 266;
 273         case CLKCFG_FSB_1333:
 274                 return 333;
 275         /* these two are just a guess; one of them might be right */
 276         case CLKCFG_FSB_1600:
 277         case CLKCFG_FSB_1600_ALT:
 278                 return 400;
 279         default:
 280                 return 133;
 281         }
 282 }
 283
 284 static void
 285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 286                                     struct intel_dp *intel_dp,
 287                                     struct edp_power_seq *out);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp,
 291                                               struct edp_power_seq *out);
 292
 293 static void pps_lock(struct intel_dp *intel_dp)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct intel_encoder *encoder = &intel_dig_port->base;
 297         struct drm_device *dev = encoder->base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         enum intel_display_power_domain power_domain;
 300
 301         /*
 302          * See vlv_power_sequencer_reset() why we need
 303          * a power domain reference here.
 304          */
 305         power_domain = intel_display_port_power_domain(encoder);
 306         intel_display_power_get(dev_priv, power_domain);
 307
 308         mutex_lock(&dev_priv->pps_mutex);
 309 }
 310
 311 static void pps_unlock(struct intel_dp *intel_dp)
 312 {
 313         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 314         struct intel_encoder *encoder = &intel_dig_port->base;
 315         struct drm_device *dev = encoder->base.dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         enum intel_display_power_domain power_domain;
 318
 319         mutex_unlock(&dev_priv->pps_mutex);
 320
 321         power_domain = intel_display_port_power_domain(encoder);
 322         intel_display_power_put(dev_priv, power_domain);
 323 }
 324
 325 static enum pipe
 326 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 327 {
 328         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 329         struct drm_device *dev = intel_dig_port->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331         struct intel_encoder *encoder;
 332         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 333         struct edp_power_seq power_seq;
 334
 335         lockdep_assert_held(&dev_priv->pps_mutex);
 336
 337         if (intel_dp->pps_pipe != INVALID_PIPE)
 338                 return intel_dp->pps_pipe;
 339
 340         /*
 341          * We don't have power sequencer currently.
 342          * Pick one that's not used by other ports.
 343          */
 344         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 345                             base.head) {
 346                 struct intel_dp *tmp;
 347
 348                 if (encoder->type != INTEL_OUTPUT_EDP)
 349                         continue;
 350
 351                 tmp = enc_to_intel_dp(&encoder->base);
 352
 353                 if (tmp->pps_pipe != INVALID_PIPE)
 354                         pipes &= ~(1 << tmp->pps_pipe);
 355         }
 356
 357         /*
 358          * Didn't find one. This should not happen since there
 359          * are two power sequencers and up to two eDP ports.
 360          */
 361         if (WARN_ON(pipes == 0))
 362                 return PIPE_A;
 363
 364         intel_dp->pps_pipe = ffs(pipes) - 1;
 365
 366         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 367                       pipe_name(intel_dp->pps_pipe),
 368                       port_name(intel_dig_port->port));
 369
 370         /* init power sequencer on this pipe and port */
 371         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
 372         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
 373                                                       &power_seq);
 374
 375         return intel_dp->pps_pipe;
 376 }
 377
 378 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 379                                enum pipe pipe);
 380
 381 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 382                                enum pipe pipe)
 383 {
 384         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 385 }
 386
 387 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 388                                 enum pipe pipe)
 389 {
 390         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 391 }
 392
 393 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 394                          enum pipe pipe)
 395 {
 396         return true;
 397 }
 398
 399 static enum pipe
 400 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 401                      enum port port,
 402                      vlv_pipe_check pipe_check)
 403 {
 404         enum pipe pipe;
 405
 406         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 407                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 408                         PANEL_PORT_SELECT_MASK;
 409
 410                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 411                         continue;
 412
 413                 if (!pipe_check(dev_priv, pipe))
 414                         continue;
 415
 416                 return pipe;
 417         }
 418
 419         return INVALID_PIPE;
 420 }
 421
 422 static void
 423 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 424 {
 425         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 426         struct drm_device *dev = intel_dig_port->base.base.dev;
 427         struct drm_i915_private *dev_priv = dev->dev_private;
 428         struct edp_power_seq power_seq;
 429         enum port port = intel_dig_port->port;
 430
 431         lockdep_assert_held(&dev_priv->pps_mutex);
 432
 433         /* try to find a pipe with this port selected */
 434         /* first pick one where the panel is on */
 435         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 436                                                   vlv_pipe_has_pp_on);
 437         /* didn't find one? pick one where vdd is on */
 438         if (intel_dp->pps_pipe == INVALID_PIPE)
 439                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 440                                                           vlv_pipe_has_vdd_on);
 441         /* didn't find one? pick one with just the correct port */
 442         if (intel_dp->pps_pipe == INVALID_PIPE)
 443                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 444                                                           vlv_pipe_any);
 445
 446         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 447         if (intel_dp->pps_pipe == INVALID_PIPE) {
 448                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 449                               port_name(port));
 450                 return;
 451         }
 452
 453         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 454                       port_name(port), pipe_name(intel_dp->pps_pipe));
 455
 456         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
 457         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
 458                                                       &power_seq);
 459 }
 460
 461 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 462 {
 463         struct drm_device *dev = dev_priv->dev;
 464         struct intel_encoder *encoder;
 465
 466         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 467                 return;
 468
 469         /*
 470          * We can't grab pps_mutex here due to deadlock with power_domain
 471          * mutex when power_domain functions are called while holding pps_mutex.
 472          * That also means that in order to use pps_pipe the code needs to
 473          * hold both a power domain reference and pps_mutex, and the power domain
 474          * reference get/put must be done while _not_ holding pps_mutex.
 475          * pps_{lock,unlock}() do these steps in the correct order, so one
 476          * should use them always.
 477          */
 478
 479         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 480                 struct intel_dp *intel_dp;
 481
 482                 if (encoder->type != INTEL_OUTPUT_EDP)
 483                         continue;
 484
 485                 intel_dp = enc_to_intel_dp(&encoder->base);
 486                 intel_dp->pps_pipe = INVALID_PIPE;
 487         }
 488 }
 489
 490 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 491 {
 492         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 return PCH_PP_CONTROL;
 496         else
 497                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 498 }
 499
 500 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 501 {
 502         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 503
 504         if (HAS_PCH_SPLIT(dev))
 505                 return PCH_PP_STATUS;
 506         else
 507                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 508 }
 509
 510 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 511    This function only applicable when panel PM state is not to be tracked */
 512 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 513                               void *unused)
 514 {
 515         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 516                                                  edp_notifier);
 517         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 518         struct drm_i915_private *dev_priv = dev->dev_private;
 519         u32 pp_div;
 520         u32 pp_ctrl_reg, pp_div_reg;
 521
 522         if (!is_edp(intel_dp) || code != SYS_RESTART)
 523                 return 0;
 524
 525         pps_lock(intel_dp);
 526
 527         if (IS_VALLEYVIEW(dev)) {
 528                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 529
 530                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 531                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 532                 pp_div = I915_READ(pp_div_reg);
 533                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 534
 535                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 536                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 537                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 538                 msleep(intel_dp->panel_power_cycle_delay);
 539         }
 540
 541         pps_unlock(intel_dp);
 542
 543         return 0;
 544 }
 545
 546 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 547 {
 548         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 549         struct drm_i915_private *dev_priv = dev->dev_private;
 550
 551         lockdep_assert_held(&dev_priv->pps_mutex);
 552
 553         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 554 }
 555
 556 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 557 {
 558         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 559         struct drm_i915_private *dev_priv = dev->dev_private;
 560
 561         lockdep_assert_held(&dev_priv->pps_mutex);
 562
 563         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 564 }
 565
 566 static void
 567 intel_dp_check_edp(struct intel_dp *intel_dp)
 568 {
 569         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 570         struct drm_i915_private *dev_priv = dev->dev_private;
 571
 572         if (!is_edp(intel_dp))
 573                 return;
 574
 575         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 576                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 577                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 578                               I915_READ(_pp_stat_reg(intel_dp)),
 579                               I915_READ(_pp_ctrl_reg(intel_dp)));
 580         }
 581 }
 582
 583 static uint32_t
 584 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 585 {
 586         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 587         struct drm_device *dev = intel_dig_port->base.base.dev;
 588         struct drm_i915_private *dev_priv = dev->dev_private;
 589         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 590         uint32_t status;
 591         bool done;
 592
 593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 594         if (has_aux_irq)
 595                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 596                                           msecs_to_jiffies_timeout(10));
 597         else
 598                 done = wait_for_atomic(C, 10) == 0;
 599         if (!done)
 600                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 601                           has_aux_irq);
 602 #undef C
 603
 604         return status;
 605 }
 606
 607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 608 {
 609         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 610         struct drm_device *dev = intel_dig_port->base.base.dev;
 611
 612         /*
 613          * The clock divider is based off the hrawclk, and would like to run at
 614          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 615          */
 616         return index ? 0 : intel_hrawclk(dev) / 2;
 617 }
 618
 619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 620 {
 621         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 622         struct drm_device *dev = intel_dig_port->base.base.dev;
 623
 624         if (index)
 625                 return 0;
 626
 627         if (intel_dig_port->port == PORT_A) {
 628                 if (IS_GEN6(dev) || IS_GEN7(dev))
 629                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 630                 else
 631                         return 225; /* eDP input clock at 450Mhz */
 632         } else {
 633                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 634         }
 635 }
 636
 637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 638 {
 639         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 640         struct drm_device *dev = intel_dig_port->base.base.dev;
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642
 643         if (intel_dig_port->port == PORT_A) {
 644                 if (index)
 645                         return 0;
 646                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 647         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 648                 /* Workaround for non-ULT HSW */
 649                 switch (index) {
 650                 case 0: return 63;
 651                 case 1: return 72;
 652                 default: return 0;
 653                 }
 654         } else  {
 655                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 656         }
 657 }
 658
 659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 660 {
 661         return index ? 0 : 100;
 662 }
 663
 664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 665                                       bool has_aux_irq,
 666                                       int send_bytes,
 667                                       uint32_t aux_clock_divider)
 668 {
 669         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 670         struct drm_device *dev = intel_dig_port->base.base.dev;
 671         uint32_t precharge, timeout;
 672
 673         if (IS_GEN6(dev))
 674                 precharge = 3;
 675         else
 676                 precharge = 5;
 677
 678         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 679                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 680         else
 681                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 682
 683         return DP_AUX_CH_CTL_SEND_BUSY |
 684                DP_AUX_CH_CTL_DONE |
 685                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 686                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 687                timeout |
 688                DP_AUX_CH_CTL_RECEIVE_ERROR |
 689                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 690                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 691                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 692 }
 693
 694 static int
 695 intel_dp_aux_ch(struct intel_dp *intel_dp,
 696                 uint8_t *send, int send_bytes,
 697                 uint8_t *recv, int recv_size)
 698 {
 699         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 700         struct drm_device *dev = intel_dig_port->base.base.dev;
 701         struct drm_i915_private *dev_priv = dev->dev_private;
 702         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 703         uint32_t ch_data = ch_ctl + 4;
 704         uint32_t aux_clock_divider;
 705         int i, ret, recv_bytes;
 706         uint32_t status;
 707         int try, clock = 0;
 708         bool has_aux_irq = HAS_AUX_IRQ(dev);
 709         bool vdd;
 710
 711         pps_lock(intel_dp);
 712
 713         /*
 714          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 715          * In such cases we want to leave VDD enabled and it's up to upper layers
 716          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 717          * ourselves.
 718          */
 719         vdd = edp_panel_vdd_on(intel_dp);
 720
 721         /* dp aux is extremely sensitive to irq latency, hence request the
 722          * lowest possible wakeup latency and so prevent the cpu from going into
 723          * deep sleep states.
 724          */
 725         pm_qos_update_request(&dev_priv->pm_qos, 0);
 726
 727         intel_dp_check_edp(intel_dp);
 728
 729         intel_aux_display_runtime_get(dev_priv);
 730
 731         /* Try to wait for any previous AUX channel activity */
 732         for (try = 0; try < 3; try++) {
 733                 status = I915_READ_NOTRACE(ch_ctl);
 734                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 735                         break;
 736                 msleep(1);
 737         }
 738
 739         if (try == 3) {
 740                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 741                      I915_READ(ch_ctl));
 742                 ret = -EBUSY;
 743                 goto out;
 744         }
 745
 746         /* Only 5 data registers! */
 747         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 748                 ret = -E2BIG;
 749                 goto out;
 750         }
 751
 752         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 753                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 754                                                           has_aux_irq,
 755                                                           send_bytes,
 756                                                           aux_clock_divider);
 757
 758                 /* Must try at least 3 times according to DP spec */
 759                 for (try = 0; try < 5; try++) {
 760                         /* Load the send data into the aux channel data registers */
 761                         for (i = 0; i < send_bytes; i += 4)
 762                                 I915_WRITE(ch_data + i,
 763                                            pack_aux(send + i, send_bytes - i));
 764
 765                         /* Send the command and wait for it to complete */
 766                         I915_WRITE(ch_ctl, send_ctl);
 767
 768                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 769
 770                         /* Clear done status and any errors */
 771                         I915_WRITE(ch_ctl,
 772                                    status |
 773                                    DP_AUX_CH_CTL_DONE |
 774                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 775                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 776
 777                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 778                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 779                                 continue;
 780                         if (status & DP_AUX_CH_CTL_DONE)
 781                                 break;
 782                 }
 783                 if (status & DP_AUX_CH_CTL_DONE)
 784                         break;
 785         }
 786
 787         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 788                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 789                 ret = -EBUSY;
 790                 goto out;
 791         }
 792
 793         /* Check for timeout or receive error.
 794          * Timeouts occur when the sink is not connected
 795          */
 796         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 797                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 798                 ret = -EIO;
 799                 goto out;
 800         }
 801
 802         /* Timeouts occur when the device isn't connected, so they're
 803          * "normal" -- don't fill the kernel log with these */
 804         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 805                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 806                 ret = -ETIMEDOUT;
 807                 goto out;
 808         }
 809
 810         /* Unload any bytes sent back from the other side */
 811         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 812                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 813         if (recv_bytes > recv_size)
 814                 recv_bytes = recv_size;
 815
 816         for (i = 0; i < recv_bytes; i += 4)
 817                 unpack_aux(I915_READ(ch_data + i),
 818                            recv + i, recv_bytes - i);
 819
 820         ret = recv_bytes;
 821 out:
 822         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 823         intel_aux_display_runtime_put(dev_priv);
 824
 825         if (vdd)
 826                 edp_panel_vdd_off(intel_dp, false);
 827
 828         pps_unlock(intel_dp);
 829
 830         return ret;
 831 }
 832
 833 #define BARE_ADDRESS_SIZE       3
 834 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 835 static ssize_t
 836 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 837 {
 838         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 839         uint8_t txbuf[20], rxbuf[20];
 840         size_t txsize, rxsize;
 841         int ret;
 842
 843         txbuf[0] = msg->request << 4;
 844         txbuf[1] = msg->address >> 8;
 845         txbuf[2] = msg->address & 0xff;
 846         txbuf[3] = msg->size - 1;
 847
 848         switch (msg->request & ~DP_AUX_I2C_MOT) {
 849         case DP_AUX_NATIVE_WRITE:
 850         case DP_AUX_I2C_WRITE:
 851                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 852                 rxsize = 1;
 853
 854                 if (WARN_ON(txsize > 20))
 855                         return -E2BIG;
 856
 857                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 858
 859                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 860                 if (ret > 0) {
 861                         msg->reply = rxbuf[0] >> 4;
 862
 863                         /* Return payload size. */
 864                         ret = msg->size;
 865                 }
 866                 break;
 867
 868         case DP_AUX_NATIVE_READ:
 869         case DP_AUX_I2C_READ:
 870                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 871                 rxsize = msg->size + 1;
 872
 873                 if (WARN_ON(rxsize > 20))
 874                         return -E2BIG;
 875
 876                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 877                 if (ret > 0) {
 878                         msg->reply = rxbuf[0] >> 4;
 879                         /*
 880                          * Assume happy day, and copy the data. The caller is
 881                          * expected to check msg->reply before touching it.
 882                          *
 883                          * Return payload size.
 884                          */
 885                         ret--;
 886                         memcpy(msg->buffer, rxbuf + 1, ret);
 887                 }
 888                 break;
 889
 890         default:
 891                 ret = -EINVAL;
 892                 break;
 893         }
 894
 895         return ret;
 896 }
 897
 898 static void
 899 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 900 {
 901         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 902         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 903         enum port port = intel_dig_port->port;
 904         const char *name = NULL;
 905         int ret;
 906
 907         switch (port) {
 908         case PORT_A:
 909                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 910                 name = "DPDDC-A";
 911                 break;
 912         case PORT_B:
 913                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 914                 name = "DPDDC-B";
 915                 break;
 916         case PORT_C:
 917                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 918                 name = "DPDDC-C";
 919                 break;
 920         case PORT_D:
 921                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 922                 name = "DPDDC-D";
 923                 break;
 924         default:
 925                 BUG();
 926         }
 927
 928         if (!HAS_DDI(dev))
 929                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 930
 931         intel_dp->aux.name = name;
 932         intel_dp->aux.dev = dev->dev;
 933         intel_dp->aux.transfer = intel_dp_aux_transfer;
 934
 935         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 936                       connector->base.kdev->kobj.name);
 937
 938         ret = drm_dp_aux_register(&intel_dp->aux);
 939         if (ret < 0) {
 940                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 941                           name, ret);
 942                 return;
 943         }
 944
 945         ret = sysfs_create_link(&connector->base.kdev->kobj,
 946                                 &intel_dp->aux.ddc.dev.kobj,
 947                                 intel_dp->aux.ddc.dev.kobj.name);
 948         if (ret < 0) {
 949                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 950                 drm_dp_aux_unregister(&intel_dp->aux);
 951         }
 952 }
 953
 954 static void
 955 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 956 {
 957         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 958
 959         if (!intel_connector->mst_port)
 960                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
 961                                   intel_dp->aux.ddc.dev.kobj.name);
 962         intel_connector_unregister(intel_connector);
 963 }
 964
 965 static void
 966 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
 967 {
 968         switch (link_bw) {
 969         case DP_LINK_BW_1_62:
 970                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 971                 break;
 972         case DP_LINK_BW_2_7:
 973                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 974                 break;
 975         case DP_LINK_BW_5_4:
 976                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 977                 break;
 978         }
 979 }
 980
 981 static void
 982 intel_dp_set_clock(struct intel_encoder *encoder,
 983                    struct intel_crtc_config *pipe_config, int link_bw)
 984 {
 985         struct drm_device *dev = encoder->base.dev;
 986         const struct dp_link_dpll *divisor = NULL;
 987         int i, count = 0;
 988
 989         if (IS_G4X(dev)) {
 990                 divisor = gen4_dpll;
 991                 count = ARRAY_SIZE(gen4_dpll);
 992         } else if (HAS_PCH_SPLIT(dev)) {
 993                 divisor = pch_dpll;
 994                 count = ARRAY_SIZE(pch_dpll);
 995         } else if (IS_CHERRYVIEW(dev)) {
 996                 divisor = chv_dpll;
 997                 count = ARRAY_SIZE(chv_dpll);
 998         } else if (IS_VALLEYVIEW(dev)) {
 999                 divisor = vlv_dpll;
1000                 count = ARRAY_SIZE(vlv_dpll);
1001         }
1002
1003         if (divisor && count) {
1004                 for (i = 0; i < count; i++) {
1005                         if (link_bw == divisor[i].link_bw) {
1006                                 pipe_config->dpll = divisor[i].dpll;
1007                                 pipe_config->clock_set = true;
1008                                 break;
1009                         }
1010                 }
1011         }
1012 }
1013
1014 bool
1015 intel_dp_compute_config(struct intel_encoder *encoder,
1016                         struct intel_crtc_config *pipe_config)
1017 {
1018         struct drm_device *dev = encoder->base.dev;
1019         struct drm_i915_private *dev_priv = dev->dev_private;
1020         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1021         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1022         enum port port = dp_to_dig_port(intel_dp)->port;
1023         struct intel_crtc *intel_crtc = encoder->new_crtc;
1024         struct intel_connector *intel_connector = intel_dp->attached_connector;
1025         int lane_count, clock;
1026         int min_lane_count = 1;
1027         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1028         /* Conveniently, the link BW constants become indices with a shift...*/
1029         int min_clock = 0;
1030         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1031         int bpp, mode_rate;
1032         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1033         int link_avail, link_clock;
1034
1035         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1036                 pipe_config->has_pch_encoder = true;
1037
1038         pipe_config->has_dp_encoder = true;
1039         pipe_config->has_drrs = false;
1040         pipe_config->has_audio = intel_dp->has_audio;
1041
1042         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044                                        adjusted_mode);
1045                 if (!HAS_PCH_SPLIT(dev))
1046                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047                                                  intel_connector->panel.fitting_mode);
1048                 else
1049                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1050                                                 intel_connector->panel.fitting_mode);
1051         }
1052
1053         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1054                 return false;
1055
1056         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057                       "max bw %02x pixel clock %iKHz\n",
1058                       max_lane_count, bws[max_clock],
1059                       adjusted_mode->crtc_clock);
1060
1061         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062          * bpc in between. */
1063         bpp = pipe_config->pipe_bpp;
1064         if (is_edp(intel_dp)) {
1065                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067                                       dev_priv->vbt.edp_bpp);
1068                         bpp = dev_priv->vbt.edp_bpp;
1069                 }
1070
1071                 /*
1072                  * Use the maximum clock and number of lanes the eDP panel
1073                  * advertizes being capable of. The panels are generally
1074                  * designed to support only a single clock and lane
1075                  * configuration, and typically these values correspond to the
1076                  * native resolution of the panel.
1077                  */
1078                 min_lane_count = max_lane_count;
1079                 min_clock = max_clock;
1080         }
1081
1082         for (; bpp >= 6*3; bpp -= 2*3) {
1083                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1084                                                    bpp);
1085
1086                 for (clock = min_clock; clock <= max_clock; clock++) {
1087                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1088                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1089                                 link_avail = intel_dp_max_data_rate(link_clock,
1090                                                                     lane_count);
1091
1092                                 if (mode_rate <= link_avail) {
1093                                         goto found;
1094                                 }
1095                         }
1096                 }
1097         }
1098
1099         return false;
1100
1101 found:
1102         if (intel_dp->color_range_auto) {
1103                 /*
1104                  * See:
1105                  * CEA-861-E - 5.1 Default Encoding Parameters
1106                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1107                  */
1108                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1109                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1110                 else
1111                         intel_dp->color_range = 0;
1112         }
1113
1114         if (intel_dp->color_range)
1115                 pipe_config->limited_color_range = true;
1116
1117         intel_dp->link_bw = bws[clock];
1118         intel_dp->lane_count = lane_count;
1119         pipe_config->pipe_bpp = bpp;
1120         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1121
1122         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1123                       intel_dp->link_bw, intel_dp->lane_count,
1124                       pipe_config->port_clock, bpp);
1125         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1126                       mode_rate, link_avail);
1127
1128         intel_link_compute_m_n(bpp, lane_count,
1129                                adjusted_mode->crtc_clock,
1130                                pipe_config->port_clock,
1131                                &pipe_config->dp_m_n);
1132
1133         if (intel_connector->panel.downclock_mode != NULL &&
1134                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1135                         pipe_config->has_drrs = true;
1136                         intel_link_compute_m_n(bpp, lane_count,
1137                                 intel_connector->panel.downclock_mode->clock,
1138                                 pipe_config->port_clock,
1139                                 &pipe_config->dp_m2_n2);
1140         }
1141
1142         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1143                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1144         else
1145                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1146
1147         return true;
1148 }
1149
1150 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1151 {
1152         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1154         struct drm_device *dev = crtc->base.dev;
1155         struct drm_i915_private *dev_priv = dev->dev_private;
1156         u32 dpa_ctl;
1157
1158         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1159         dpa_ctl = I915_READ(DP_A);
1160         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1161
1162         if (crtc->config.port_clock == 162000) {
1163                 /* For a long time we've carried around a ILK-DevA w/a for the
1164                  * 160MHz clock. If we're really unlucky, it's still required.
1165                  */
1166                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1167                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1168                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1169         } else {
1170                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1171                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1172         }
1173
1174         I915_WRITE(DP_A, dpa_ctl);
1175
1176         POSTING_READ(DP_A);
1177         udelay(500);
1178 }
1179
1180 static void intel_dp_prepare(struct intel_encoder *encoder)
1181 {
1182         struct drm_device *dev = encoder->base.dev;
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1185         enum port port = dp_to_dig_port(intel_dp)->port;
1186         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1187         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1188
1189         /*
1190          * There are four kinds of DP registers:
1191          *
1192          *      IBX PCH
1193          *      SNB CPU
1194          *      IVB CPU
1195          *      CPT PCH
1196          *
1197          * IBX PCH and CPU are the same for almost everything,
1198          * except that the CPU DP PLL is configured in this
1199          * register
1200          *
1201          * CPT PCH is quite different, having many bits moved
1202          * to the TRANS_DP_CTL register instead. That
1203          * configuration happens (oddly) in ironlake_pch_enable
1204          */
1205
1206         /* Preserve the BIOS-computed detected bit. This is
1207          * supposed to be read-only.
1208          */
1209         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1210
1211         /* Handle DP bits in common between all three register formats */
1212         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1213         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1214
1215         if (crtc->config.has_audio) {
1216                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1217                                  pipe_name(crtc->pipe));
1218                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1219                 intel_write_eld(&encoder->base, adjusted_mode);
1220         }
1221
1222         /* Split out the IBX/CPU vs CPT settings */
1223
1224         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1225                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1226                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1227                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1228                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1229                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1230
1231                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1232                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1233
1234                 intel_dp->DP |= crtc->pipe << 29;
1235         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1236                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1237                         intel_dp->DP |= intel_dp->color_range;
1238
1239                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1240                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1241                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1242                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1243                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1244
1245                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1246                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1247
1248                 if (!IS_CHERRYVIEW(dev)) {
1249                         if (crtc->pipe == 1)
1250                                 intel_dp->DP |= DP_PIPEB_SELECT;
1251                 } else {
1252                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1253                 }
1254         } else {
1255                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1256         }
1257 }
1258
1259 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1260 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1261
1262 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1263 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1264
1265 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1266 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1267
1268 static void wait_panel_status(struct intel_dp *intel_dp,
1269                                        u32 mask,
1270                                        u32 value)
1271 {
1272         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1273         struct drm_i915_private *dev_priv = dev->dev_private;
1274         u32 pp_stat_reg, pp_ctrl_reg;
1275
1276         lockdep_assert_held(&dev_priv->pps_mutex);
1277
1278         pp_stat_reg = _pp_stat_reg(intel_dp);
1279         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1280
1281         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1282                         mask, value,
1283                         I915_READ(pp_stat_reg),
1284                         I915_READ(pp_ctrl_reg));
1285
1286         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1287                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1288                                 I915_READ(pp_stat_reg),
1289                                 I915_READ(pp_ctrl_reg));
1290         }
1291
1292         DRM_DEBUG_KMS("Wait complete\n");
1293 }
1294
1295 static void wait_panel_on(struct intel_dp *intel_dp)
1296 {
1297         DRM_DEBUG_KMS("Wait for panel power on\n");
1298         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1299 }
1300
1301 static void wait_panel_off(struct intel_dp *intel_dp)
1302 {
1303         DRM_DEBUG_KMS("Wait for panel power off time\n");
1304         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1305 }
1306
1307 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1308 {
1309         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1310
1311         /* When we disable the VDD override bit last we have to do the manual
1312          * wait. */
1313         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1314                                        intel_dp->panel_power_cycle_delay);
1315
1316         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1317 }
1318
1319 static void wait_backlight_on(struct intel_dp *intel_dp)
1320 {
1321         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1322                                        intel_dp->backlight_on_delay);
1323 }
1324
1325 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1326 {
1327         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1328                                        intel_dp->backlight_off_delay);
1329 }
1330
1331 /* Read the current pp_control value, unlocking the register if it
1332  * is locked
1333  */
1334
1335 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1336 {
1337         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1338         struct drm_i915_private *dev_priv = dev->dev_private;
1339         u32 control;
1340
1341         lockdep_assert_held(&dev_priv->pps_mutex);
1342
1343         control = I915_READ(_pp_ctrl_reg(intel_dp));
1344         control &= ~PANEL_UNLOCK_MASK;
1345         control |= PANEL_UNLOCK_REGS;
1346         return control;
1347 }
1348
1349 /*
1350  * Must be paired with edp_panel_vdd_off().
1351  * Must hold pps_mutex around the whole on/off sequence.
1352  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1353  */
1354 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1355 {
1356         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360         enum intel_display_power_domain power_domain;
1361         u32 pp;
1362         u32 pp_stat_reg, pp_ctrl_reg;
1363         bool need_to_disable = !intel_dp->want_panel_vdd;
1364
1365         lockdep_assert_held(&dev_priv->pps_mutex);
1366
1367         if (!is_edp(intel_dp))
1368                 return false;
1369
1370         intel_dp->want_panel_vdd = true;
1371
1372         if (edp_have_panel_vdd(intel_dp))
1373                 return need_to_disable;
1374
1375         power_domain = intel_display_port_power_domain(intel_encoder);
1376         intel_display_power_get(dev_priv, power_domain);
1377
1378         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1379
1380         if (!edp_have_panel_power(intel_dp))
1381                 wait_panel_power_cycle(intel_dp);
1382
1383         pp = ironlake_get_pp_control(intel_dp);
1384         pp |= EDP_FORCE_VDD;
1385
1386         pp_stat_reg = _pp_stat_reg(intel_dp);
1387         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1388
1389         I915_WRITE(pp_ctrl_reg, pp);
1390         POSTING_READ(pp_ctrl_reg);
1391         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1392                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1393         /*
1394          * If the panel wasn't on, delay before accessing aux channel
1395          */
1396         if (!edp_have_panel_power(intel_dp)) {
1397                 DRM_DEBUG_KMS("eDP was not running\n");
1398                 msleep(intel_dp->panel_power_up_delay);
1399         }
1400
1401         return need_to_disable;
1402 }
1403
1404 /*
1405  * Must be paired with intel_edp_panel_vdd_off() or
1406  * intel_edp_panel_off().
1407  * Nested calls to these functions are not allowed since
1408  * we drop the lock. Caller must use some higher level
1409  * locking to prevent nested calls from other threads.
1410  */
1411 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1412 {
1413         bool vdd;
1414
1415         if (!is_edp(intel_dp))
1416                 return;
1417
1418         pps_lock(intel_dp);
1419         vdd = edp_panel_vdd_on(intel_dp);
1420         pps_unlock(intel_dp);
1421
1422         WARN(!vdd, "eDP VDD already requested on\n");
1423 }
1424
1425 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1426 {
1427         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         struct intel_digital_port *intel_dig_port =
1430                 dp_to_dig_port(intel_dp);
1431         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1432         enum intel_display_power_domain power_domain;
1433         u32 pp;
1434         u32 pp_stat_reg, pp_ctrl_reg;
1435
1436         lockdep_assert_held(&dev_priv->pps_mutex);
1437
1438         WARN_ON(intel_dp->want_panel_vdd);
1439
1440         if (!edp_have_panel_vdd(intel_dp))
1441                 return;
1442
1443         DRM_DEBUG_KMS("Turning eDP VDD off\n");
1444
1445         pp = ironlake_get_pp_control(intel_dp);
1446         pp &= ~EDP_FORCE_VDD;
1447
1448         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1449         pp_stat_reg = _pp_stat_reg(intel_dp);
1450
1451         I915_WRITE(pp_ctrl_reg, pp);
1452         POSTING_READ(pp_ctrl_reg);
1453
1454         /* Make sure sequencer is idle before allowing subsequent activity */
1455         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1456         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1457
1458         if ((pp & POWER_TARGET_ON) == 0)
1459                 intel_dp->last_power_cycle = jiffies;
1460
1461         power_domain = intel_display_port_power_domain(intel_encoder);
1462         intel_display_power_put(dev_priv, power_domain);
1463 }
1464
1465 static void edp_panel_vdd_work(struct work_struct *__work)
1466 {
1467         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1468                                                  struct intel_dp, panel_vdd_work);
1469
1470         pps_lock(intel_dp);
1471         if (!intel_dp->want_panel_vdd)
1472                 edp_panel_vdd_off_sync(intel_dp);
1473         pps_unlock(intel_dp);
1474 }
1475
1476 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1477 {
1478         unsigned long delay;
1479
1480         /*
1481          * Queue the timer to fire a long time from now (relative to the power
1482          * down delay) to keep the panel power up across a sequence of
1483          * operations.
1484          */
1485         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1486         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1487 }
1488
1489 /*
1490  * Must be paired with edp_panel_vdd_on().
1491  * Must hold pps_mutex around the whole on/off sequence.
1492  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1493  */
1494 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1495 {
1496         struct drm_i915_private *dev_priv =
1497                 intel_dp_to_dev(intel_dp)->dev_private;
1498
1499         lockdep_assert_held(&dev_priv->pps_mutex);
1500
1501         if (!is_edp(intel_dp))
1502                 return;
1503
1504         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1505
1506         intel_dp->want_panel_vdd = false;
1507
1508         if (sync)
1509                 edp_panel_vdd_off_sync(intel_dp);
1510         else
1511                 edp_panel_vdd_schedule_off(intel_dp);
1512 }
1513
1514 /*
1515  * Must be paired with intel_edp_panel_vdd_on().
1516  * Nested calls to these functions are not allowed since
1517  * we drop the lock. Caller must use some higher level
1518  * locking to prevent nested calls from other threads.
1519  */
1520 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1521 {
1522         if (!is_edp(intel_dp))
1523                 return;
1524
1525         pps_lock(intel_dp);
1526         edp_panel_vdd_off(intel_dp, sync);
1527         pps_unlock(intel_dp);
1528 }
1529
1530 void intel_edp_panel_on(struct intel_dp *intel_dp)
1531 {
1532         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534         u32 pp;
1535         u32 pp_ctrl_reg;
1536
1537         if (!is_edp(intel_dp))
1538                 return;
1539
1540         DRM_DEBUG_KMS("Turn eDP power on\n");
1541
1542         pps_lock(intel_dp);
1543
1544         if (edp_have_panel_power(intel_dp)) {
1545                 DRM_DEBUG_KMS("eDP power already on\n");
1546                 goto out;
1547         }
1548
1549         wait_panel_power_cycle(intel_dp);
1550
1551         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1552         pp = ironlake_get_pp_control(intel_dp);
1553         if (IS_GEN5(dev)) {
1554                 /* ILK workaround: disable reset around power sequence */
1555                 pp &= ~PANEL_POWER_RESET;
1556                 I915_WRITE(pp_ctrl_reg, pp);
1557                 POSTING_READ(pp_ctrl_reg);
1558         }
1559
1560         pp |= POWER_TARGET_ON;
1561         if (!IS_GEN5(dev))
1562                 pp |= PANEL_POWER_RESET;
1563
1564         I915_WRITE(pp_ctrl_reg, pp);
1565         POSTING_READ(pp_ctrl_reg);
1566
1567         wait_panel_on(intel_dp);
1568         intel_dp->last_power_on = jiffies;
1569
1570         if (IS_GEN5(dev)) {
1571                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1572                 I915_WRITE(pp_ctrl_reg, pp);
1573                 POSTING_READ(pp_ctrl_reg);
1574         }
1575
1576  out:
1577         pps_unlock(intel_dp);
1578 }
1579
1580 void intel_edp_panel_off(struct intel_dp *intel_dp)
1581 {
1582         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1583         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1584         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1585         struct drm_i915_private *dev_priv = dev->dev_private;
1586         enum intel_display_power_domain power_domain;
1587         u32 pp;
1588         u32 pp_ctrl_reg;
1589
1590         if (!is_edp(intel_dp))
1591                 return;
1592
1593         DRM_DEBUG_KMS("Turn eDP power off\n");
1594
1595         pps_lock(intel_dp);
1596
1597         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1598
1599         pp = ironlake_get_pp_control(intel_dp);
1600         /* We need to switch off panel power _and_ force vdd, for otherwise some
1601          * panels get very unhappy and cease to work. */
1602         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1603                 EDP_BLC_ENABLE);
1604
1605         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1606
1607         intel_dp->want_panel_vdd = false;
1608
1609         I915_WRITE(pp_ctrl_reg, pp);
1610         POSTING_READ(pp_ctrl_reg);
1611
1612         intel_dp->last_power_cycle = jiffies;
1613         wait_panel_off(intel_dp);
1614
1615         /* We got a reference when we enabled the VDD. */
1616         power_domain = intel_display_port_power_domain(intel_encoder);
1617         intel_display_power_put(dev_priv, power_domain);
1618
1619         pps_unlock(intel_dp);
1620 }
1621
1622 /* Enable backlight in the panel power control. */
1623 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1624 {
1625         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1626         struct drm_device *dev = intel_dig_port->base.base.dev;
1627         struct drm_i915_private *dev_priv = dev->dev_private;
1628         u32 pp;
1629         u32 pp_ctrl_reg;
1630
1631         /*
1632          * If we enable the backlight right away following a panel power
1633          * on, we may see slight flicker as the panel syncs with the eDP
1634          * link.  So delay a bit to make sure the image is solid before
1635          * allowing it to appear.
1636          */
1637         wait_backlight_on(intel_dp);
1638
1639         pps_lock(intel_dp);
1640
1641         pp = ironlake_get_pp_control(intel_dp);
1642         pp |= EDP_BLC_ENABLE;
1643
1644         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1645
1646         I915_WRITE(pp_ctrl_reg, pp);
1647         POSTING_READ(pp_ctrl_reg);
1648
1649         pps_unlock(intel_dp);
1650 }
1651
1652 /* Enable backlight PWM and backlight PP control. */
1653 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1654 {
1655         if (!is_edp(intel_dp))
1656                 return;
1657
1658         DRM_DEBUG_KMS("\n");
1659
1660         intel_panel_enable_backlight(intel_dp->attached_connector);
1661         _intel_edp_backlight_on(intel_dp);
1662 }
1663
1664 /* Disable backlight in the panel power control. */
1665 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1666 {
1667         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1668         struct drm_i915_private *dev_priv = dev->dev_private;
1669         u32 pp;
1670         u32 pp_ctrl_reg;
1671
1672         if (!is_edp(intel_dp))
1673                 return;
1674
1675         pps_lock(intel_dp);
1676
1677         pp = ironlake_get_pp_control(intel_dp);
1678         pp &= ~EDP_BLC_ENABLE;
1679
1680         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1681
1682         I915_WRITE(pp_ctrl_reg, pp);
1683         POSTING_READ(pp_ctrl_reg);
1684
1685         pps_unlock(intel_dp);
1686
1687         intel_dp->last_backlight_off = jiffies;
1688         edp_wait_backlight_off(intel_dp);
1689 }
1690
1691 /* Disable backlight PP control and backlight PWM. */
1692 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1693 {
1694         if (!is_edp(intel_dp))
1695                 return;
1696
1697         DRM_DEBUG_KMS("\n");
1698
1699         _intel_edp_backlight_off(intel_dp);
1700         intel_panel_disable_backlight(intel_dp->attached_connector);
1701 }
1702
1703 /*
1704  * Hook for controlling the panel power control backlight through the bl_power
1705  * sysfs attribute. Take care to handle multiple calls.
1706  */
1707 static void intel_edp_backlight_power(struct intel_connector *connector,
1708                                       bool enable)
1709 {
1710         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1711         bool is_enabled;
1712
1713         pps_lock(intel_dp);
1714         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1715         pps_unlock(intel_dp);
1716
1717         if (is_enabled == enable)
1718                 return;
1719
1720         DRM_DEBUG_KMS("panel power control backlight %s\n",
1721                       enable ? "enable" : "disable");
1722
1723         if (enable)
1724                 _intel_edp_backlight_on(intel_dp);
1725         else
1726                 _intel_edp_backlight_off(intel_dp);
1727 }
1728
1729 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1730 {
1731         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1732         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1733         struct drm_device *dev = crtc->dev;
1734         struct drm_i915_private *dev_priv = dev->dev_private;
1735         u32 dpa_ctl;
1736
1737         assert_pipe_disabled(dev_priv,
1738                              to_intel_crtc(crtc)->pipe);
1739
1740         DRM_DEBUG_KMS("\n");
1741         dpa_ctl = I915_READ(DP_A);
1742         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1743         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1744
1745         /* We don't adjust intel_dp->DP while tearing down the link, to
1746          * facilitate link retraining (e.g. after hotplug). Hence clear all
1747          * enable bits here to ensure that we don't enable too much. */
1748         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1749         intel_dp->DP |= DP_PLL_ENABLE;
1750         I915_WRITE(DP_A, intel_dp->DP);
1751         POSTING_READ(DP_A);
1752         udelay(200);
1753 }
1754
1755 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1756 {
1757         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1758         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1759         struct drm_device *dev = crtc->dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         u32 dpa_ctl;
1762
1763         assert_pipe_disabled(dev_priv,
1764                              to_intel_crtc(crtc)->pipe);
1765
1766         dpa_ctl = I915_READ(DP_A);
1767         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1768              "dp pll off, should be on\n");
1769         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1770
1771         /* We can't rely on the value tracked for the DP register in
1772          * intel_dp->DP because link_down must not change that (otherwise link
1773          * re-training will fail. */
1774         dpa_ctl &= ~DP_PLL_ENABLE;
1775         I915_WRITE(DP_A, dpa_ctl);
1776         POSTING_READ(DP_A);
1777         udelay(200);
1778 }
1779
1780 /* If the sink supports it, try to set the power state appropriately */
1781 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1782 {
1783         int ret, i;
1784
1785         /* Should have a valid DPCD by this point */
1786         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1787                 return;
1788
1789         if (mode != DRM_MODE_DPMS_ON) {
1790                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1791                                          DP_SET_POWER_D3);
1792         } else {
1793                 /*
1794                  * When turning on, we need to retry for 1ms to give the sink
1795                  * time to wake up.
1796                  */
1797                 for (i = 0; i < 3; i++) {
1798                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1799                                                  DP_SET_POWER_D0);
1800                         if (ret == 1)
1801                                 break;
1802                         msleep(1);
1803                 }
1804         }
1805
1806         if (ret != 1)
1807                 DRM_DEBUG_KMS("failed to %s sink power state\n",
1808                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1809 }
1810
1811 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1812                                   enum pipe *pipe)
1813 {
1814         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815         enum port port = dp_to_dig_port(intel_dp)->port;
1816         struct drm_device *dev = encoder->base.dev;
1817         struct drm_i915_private *dev_priv = dev->dev_private;
1818         enum intel_display_power_domain power_domain;
1819         u32 tmp;
1820
1821         power_domain = intel_display_port_power_domain(encoder);
1822         if (!intel_display_power_enabled(dev_priv, power_domain))
1823                 return false;
1824
1825         tmp = I915_READ(intel_dp->output_reg);
1826
1827         if (!(tmp & DP_PORT_EN))
1828                 return false;
1829
1830         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1831                 *pipe = PORT_TO_PIPE_CPT(tmp);
1832         } else if (IS_CHERRYVIEW(dev)) {
1833                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1834         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1835                 *pipe = PORT_TO_PIPE(tmp);
1836         } else {
1837                 u32 trans_sel;
1838                 u32 trans_dp;
1839                 int i;
1840
1841                 switch (intel_dp->output_reg) {
1842                 case PCH_DP_B:
1843                         trans_sel = TRANS_DP_PORT_SEL_B;
1844                         break;
1845                 case PCH_DP_C:
1846                         trans_sel = TRANS_DP_PORT_SEL_C;
1847                         break;
1848                 case PCH_DP_D:
1849                         trans_sel = TRANS_DP_PORT_SEL_D;
1850                         break;
1851                 default:
1852                         return true;
1853                 }
1854
1855                 for_each_pipe(dev_priv, i) {
1856                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1857                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1858                                 *pipe = i;
1859                                 return true;
1860                         }
1861                 }
1862
1863                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1864                               intel_dp->output_reg);
1865         }
1866
1867         return true;
1868 }
1869
1870 static void intel_dp_get_config(struct intel_encoder *encoder,
1871                                 struct intel_crtc_config *pipe_config)
1872 {
1873         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1874         u32 tmp, flags = 0;
1875         struct drm_device *dev = encoder->base.dev;
1876         struct drm_i915_private *dev_priv = dev->dev_private;
1877         enum port port = dp_to_dig_port(intel_dp)->port;
1878         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1879         int dotclock;
1880
1881         tmp = I915_READ(intel_dp->output_reg);
1882         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1883                 pipe_config->has_audio = true;
1884
1885         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1886                 if (tmp & DP_SYNC_HS_HIGH)
1887                         flags |= DRM_MODE_FLAG_PHSYNC;
1888                 else
1889                         flags |= DRM_MODE_FLAG_NHSYNC;
1890
1891                 if (tmp & DP_SYNC_VS_HIGH)
1892                         flags |= DRM_MODE_FLAG_PVSYNC;
1893                 else
1894                         flags |= DRM_MODE_FLAG_NVSYNC;
1895         } else {
1896                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1897                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1898                         flags |= DRM_MODE_FLAG_PHSYNC;
1899                 else
1900                         flags |= DRM_MODE_FLAG_NHSYNC;
1901
1902                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1903                         flags |= DRM_MODE_FLAG_PVSYNC;
1904                 else
1905                         flags |= DRM_MODE_FLAG_NVSYNC;
1906         }
1907
1908         pipe_config->adjusted_mode.flags |= flags;
1909
1910         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1911             tmp & DP_COLOR_RANGE_16_235)
1912                 pipe_config->limited_color_range = true;
1913
1914         pipe_config->has_dp_encoder = true;
1915
1916         intel_dp_get_m_n(crtc, pipe_config);
1917
1918         if (port == PORT_A) {
1919                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1920                         pipe_config->port_clock = 162000;
1921                 else
1922                         pipe_config->port_clock = 270000;
1923         }
1924
1925         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1926                                             &pipe_config->dp_m_n);
1927
1928         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1929                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1930
1931         pipe_config->adjusted_mode.crtc_clock = dotclock;
1932
1933         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1934             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1935                 /*
1936                  * This is a big fat ugly hack.
1937                  *
1938                  * Some machines in UEFI boot mode provide us a VBT that has 18
1939                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1940                  * unknown we fail to light up. Yet the same BIOS boots up with
1941                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1942                  * max, not what it tells us to use.
1943                  *
1944                  * Note: This will still be broken if the eDP panel is not lit
1945                  * up by the BIOS, and thus we can't get the mode at module
1946                  * load.
1947                  */
1948                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1949                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1950                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1951         }
1952 }
1953
1954 static bool is_edp_psr(struct intel_dp *intel_dp)
1955 {
1956         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1957 }
1958
1959 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1960 {
1961         struct drm_i915_private *dev_priv = dev->dev_private;
1962
1963         if (!HAS_PSR(dev))
1964                 return false;
1965
1966         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1967 }
1968
1969 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1970                                     struct edp_vsc_psr *vsc_psr)
1971 {
1972         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1973         struct drm_device *dev = dig_port->base.base.dev;
1974         struct drm_i915_private *dev_priv = dev->dev_private;
1975         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1976         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1977         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1978         uint32_t *data = (uint32_t *) vsc_psr;
1979         unsigned int i;
1980
1981         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1982            the video DIP being updated before program video DIP data buffer
1983            registers for DIP being updated. */
1984         I915_WRITE(ctl_reg, 0);
1985         POSTING_READ(ctl_reg);
1986
1987         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1988                 if (i < sizeof(struct edp_vsc_psr))
1989                         I915_WRITE(data_reg + i, *data++);
1990                 else
1991                         I915_WRITE(data_reg + i, 0);
1992         }
1993
1994         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1995         POSTING_READ(ctl_reg);
1996 }
1997
1998 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1999 {
2000         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002         struct edp_vsc_psr psr_vsc;
2003
2004         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2005         memset(&psr_vsc, 0, sizeof(psr_vsc));
2006         psr_vsc.sdp_header.HB0 = 0;
2007         psr_vsc.sdp_header.HB1 = 0x7;
2008         psr_vsc.sdp_header.HB2 = 0x2;
2009         psr_vsc.sdp_header.HB3 = 0x8;
2010         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2011
2012         /* Avoid continuous PSR exit by masking memup and hpd */
2013         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2014                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2015 }
2016
2017 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2018 {
2019         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2020         struct drm_device *dev = dig_port->base.base.dev;
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022         uint32_t aux_clock_divider;
2023         int precharge = 0x3;
2024         int msg_size = 5;       /* Header(4) + Message(1) */
2025         bool only_standby = false;
2026
2027         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2028
2029         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2030                 only_standby = true;
2031
2032         /* Enable PSR in sink */
2033         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2034                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2035                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2036         else
2037                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2038                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2039
2040         /* Setup AUX registers */
2041         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2042         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2043         I915_WRITE(EDP_PSR_AUX_CTL(dev),
2044                    DP_AUX_CH_CTL_TIME_OUT_400us |
2045                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2046                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2047                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2048 }
2049
2050 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2051 {
2052         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2053         struct drm_device *dev = dig_port->base.base.dev;
2054         struct drm_i915_private *dev_priv = dev->dev_private;
2055         uint32_t max_sleep_time = 0x1f;
2056         uint32_t idle_frames = 1;
2057         uint32_t val = 0x0;
2058         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2059         bool only_standby = false;
2060
2061         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2062                 only_standby = true;
2063
2064         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2065                 val |= EDP_PSR_LINK_STANDBY;
2066                 val |= EDP_PSR_TP2_TP3_TIME_0us;
2067                 val |= EDP_PSR_TP1_TIME_0us;
2068                 val |= EDP_PSR_SKIP_AUX_EXIT;
2069                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2070         } else
2071                 val |= EDP_PSR_LINK_DISABLE;
2072
2073         I915_WRITE(EDP_PSR_CTL(dev), val |
2074                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2075                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2076                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2077                    EDP_PSR_ENABLE);
2078 }
2079
2080 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2081 {
2082         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2083         struct drm_device *dev = dig_port->base.base.dev;
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085         struct drm_crtc *crtc = dig_port->base.base.crtc;
2086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087
2088         lockdep_assert_held(&dev_priv->psr.lock);
2089         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2090         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2091
2092         dev_priv->psr.source_ok = false;
2093
2094         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2095                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2096                 return false;
2097         }
2098
2099         if (!i915.enable_psr) {
2100                 DRM_DEBUG_KMS("PSR disable by flag\n");
2101                 return false;
2102         }
2103
2104         /* Below limitations aren't valid for Broadwell */
2105         if (IS_BROADWELL(dev))
2106                 goto out;
2107
2108         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2109             S3D_ENABLE) {
2110                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2111                 return false;
2112         }
2113
2114         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2115                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2116                 return false;
2117         }
2118
2119  out:
2120         dev_priv->psr.source_ok = true;
2121         return true;
2122 }
2123
2124 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2125 {
2126         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2127         struct drm_device *dev = intel_dig_port->base.base.dev;
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129
2130         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2131         WARN_ON(dev_priv->psr.active);
2132         lockdep_assert_held(&dev_priv->psr.lock);
2133
2134         /* Enable PSR on the panel */
2135         intel_edp_psr_enable_sink(intel_dp);
2136
2137         /* Enable PSR on the host */
2138         intel_edp_psr_enable_source(intel_dp);
2139
2140         dev_priv->psr.active = true;
2141 }
2142
2143 void intel_edp_psr_enable(struct intel_dp *intel_dp)
2144 {
2145         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2146         struct drm_i915_private *dev_priv = dev->dev_private;
2147
2148         if (!HAS_PSR(dev)) {
2149                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2150                 return;
2151         }
2152
2153         if (!is_edp_psr(intel_dp)) {
2154                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2155                 return;
2156         }
2157
2158         mutex_lock(&dev_priv->psr.lock);
2159         if (dev_priv->psr.enabled) {
2160                 DRM_DEBUG_KMS("PSR already in use\n");
2161                 mutex_unlock(&dev_priv->psr.lock);
2162                 return;
2163         }
2164
2165         dev_priv->psr.busy_frontbuffer_bits = 0;
2166
2167         /* Setup PSR once */
2168         intel_edp_psr_setup(intel_dp);
2169
2170         if (intel_edp_psr_match_conditions(intel_dp))
2171                 dev_priv->psr.enabled = intel_dp;
2172         mutex_unlock(&dev_priv->psr.lock);
2173 }
2174
2175 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2176 {
2177         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2178         struct drm_i915_private *dev_priv = dev->dev_private;
2179
2180         mutex_lock(&dev_priv->psr.lock);
2181         if (!dev_priv->psr.enabled) {
2182                 mutex_unlock(&dev_priv->psr.lock);
2183                 return;
2184         }
2185
2186         if (dev_priv->psr.active) {
2187                 I915_WRITE(EDP_PSR_CTL(dev),
2188                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2189
2190                 /* Wait till PSR is idle */
2191                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2192                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2193                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
2194
2195                 dev_priv->psr.active = false;
2196         } else {
2197                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2198         }
2199
2200         dev_priv->psr.enabled = NULL;
2201         mutex_unlock(&dev_priv->psr.lock);
2202
2203         cancel_delayed_work_sync(&dev_priv->psr.work);
2204 }
2205
2206 static void intel_edp_psr_work(struct work_struct *work)
2207 {
2208         struct drm_i915_private *dev_priv =
2209                 container_of(work, typeof(*dev_priv), psr.work.work);
2210         struct intel_dp *intel_dp = dev_priv->psr.enabled;
2211
2212         mutex_lock(&dev_priv->psr.lock);
2213         intel_dp = dev_priv->psr.enabled;
2214
2215         if (!intel_dp)
2216                 goto unlock;
2217
2218         /*
2219          * The delayed work can race with an invalidate hence we need to
2220          * recheck. Since psr_flush first clears this and then reschedules we
2221          * won't ever miss a flush when bailing out here.
2222          */
2223         if (dev_priv->psr.busy_frontbuffer_bits)
2224                 goto unlock;
2225
2226         intel_edp_psr_do_enable(intel_dp);
2227 unlock:
2228         mutex_unlock(&dev_priv->psr.lock);
2229 }
2230
2231 static void intel_edp_psr_do_exit(struct drm_device *dev)
2232 {
2233         struct drm_i915_private *dev_priv = dev->dev_private;
2234
2235         if (dev_priv->psr.active) {
2236                 u32 val = I915_READ(EDP_PSR_CTL(dev));
2237
2238                 WARN_ON(!(val & EDP_PSR_ENABLE));
2239
2240                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2241
2242                 dev_priv->psr.active = false;
2243         }
2244
2245 }
2246
2247 void intel_edp_psr_invalidate(struct drm_device *dev,
2248                               unsigned frontbuffer_bits)
2249 {
2250         struct drm_i915_private *dev_priv = dev->dev_private;
2251         struct drm_crtc *crtc;
2252         enum pipe pipe;
2253
2254         mutex_lock(&dev_priv->psr.lock);
2255         if (!dev_priv->psr.enabled) {
2256                 mutex_unlock(&dev_priv->psr.lock);
2257                 return;
2258         }
2259
2260         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2261         pipe = to_intel_crtc(crtc)->pipe;
2262
2263         intel_edp_psr_do_exit(dev);
2264
2265         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2266
2267         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2268         mutex_unlock(&dev_priv->psr.lock);
2269 }
2270
2271 void intel_edp_psr_flush(struct drm_device *dev,
2272                          unsigned frontbuffer_bits)
2273 {
2274         struct drm_i915_private *dev_priv = dev->dev_private;
2275         struct drm_crtc *crtc;
2276         enum pipe pipe;
2277
2278         mutex_lock(&dev_priv->psr.lock);
2279         if (!dev_priv->psr.enabled) {
2280                 mutex_unlock(&dev_priv->psr.lock);
2281                 return;
2282         }
2283
2284         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2285         pipe = to_intel_crtc(crtc)->pipe;
2286         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2287
2288         /*
2289          * On Haswell sprite plane updates don't result in a psr invalidating
2290          * signal in the hardware. Which means we need to manually fake this in
2291          * software for all flushes, not just when we've seen a preceding
2292          * invalidation through frontbuffer rendering.
2293          */
2294         if (IS_HASWELL(dev) &&
2295             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2296                 intel_edp_psr_do_exit(dev);
2297
2298         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2299                 schedule_delayed_work(&dev_priv->psr.work,
2300                                       msecs_to_jiffies(100));
2301         mutex_unlock(&dev_priv->psr.lock);
2302 }
2303
2304 void intel_edp_psr_init(struct drm_device *dev)
2305 {
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307
2308         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2309         mutex_init(&dev_priv->psr.lock);
2310 }
2311
2312 static void intel_disable_dp(struct intel_encoder *encoder)
2313 {
2314         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2315         struct drm_device *dev = encoder->base.dev;
2316
2317         /* Make sure the panel is off before trying to change the mode. But also
2318          * ensure that we have vdd while we switch off the panel. */
2319         intel_edp_panel_vdd_on(intel_dp);
2320         intel_edp_backlight_off(intel_dp);
2321         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2322         intel_edp_panel_off(intel_dp);
2323
2324         /* disable the port before the pipe on g4x */
2325         if (INTEL_INFO(dev)->gen < 5)
2326                 intel_dp_link_down(intel_dp);
2327 }
2328
2329 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2330 {
2331         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332         enum port port = dp_to_dig_port(intel_dp)->port;
2333
2334         intel_dp_link_down(intel_dp);
2335         if (port == PORT_A)
2336                 ironlake_edp_pll_off(intel_dp);
2337 }
2338
2339 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2340 {
2341         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2342
2343         intel_dp_link_down(intel_dp);
2344 }
2345
2346 static void chv_post_disable_dp(struct intel_encoder *encoder)
2347 {
2348         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2349         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2350         struct drm_device *dev = encoder->base.dev;
2351         struct drm_i915_private *dev_priv = dev->dev_private;
2352         struct intel_crtc *intel_crtc =
2353                 to_intel_crtc(encoder->base.crtc);
2354         enum dpio_channel ch = vlv_dport_to_channel(dport);
2355         enum pipe pipe = intel_crtc->pipe;
2356         u32 val;
2357
2358         intel_dp_link_down(intel_dp);
2359
2360         mutex_lock(&dev_priv->dpio_lock);
2361
2362         /* Propagate soft reset to data lane reset */
2363         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2364         val |= CHV_PCS_REQ_SOFTRESET_EN;
2365         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2366
2367         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2368         val |= CHV_PCS_REQ_SOFTRESET_EN;
2369         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2370
2371         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2372         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2373         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2374
2375         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2376         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2377         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2378
2379         mutex_unlock(&dev_priv->dpio_lock);
2380 }
2381
2382 static void
2383 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2384                          uint32_t *DP,
2385                          uint8_t dp_train_pat)
2386 {
2387         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2388         struct drm_device *dev = intel_dig_port->base.base.dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         enum port port = intel_dig_port->port;
2391
2392         if (HAS_DDI(dev)) {
2393                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2394
2395                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2396                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2397                 else
2398                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2399
2400                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2401                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2402                 case DP_TRAINING_PATTERN_DISABLE:
2403                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2404
2405                         break;
2406                 case DP_TRAINING_PATTERN_1:
2407                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2408                         break;
2409                 case DP_TRAINING_PATTERN_2:
2410                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2411                         break;
2412                 case DP_TRAINING_PATTERN_3:
2413                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2414                         break;
2415                 }
2416                 I915_WRITE(DP_TP_CTL(port), temp);
2417
2418         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2419                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2420
2421                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2422                 case DP_TRAINING_PATTERN_DISABLE:
2423                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2424                         break;
2425                 case DP_TRAINING_PATTERN_1:
2426                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2427                         break;
2428                 case DP_TRAINING_PATTERN_2:
2429                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2430                         break;
2431                 case DP_TRAINING_PATTERN_3:
2432                         DRM_ERROR("DP training pattern 3 not supported\n");
2433                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2434                         break;
2435                 }
2436
2437         } else {
2438                 if (IS_CHERRYVIEW(dev))
2439                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2440                 else
2441                         *DP &= ~DP_LINK_TRAIN_MASK;
2442
2443                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2444                 case DP_TRAINING_PATTERN_DISABLE:
2445                         *DP |= DP_LINK_TRAIN_OFF;
2446                         break;
2447                 case DP_TRAINING_PATTERN_1:
2448                         *DP |= DP_LINK_TRAIN_PAT_1;
2449                         break;
2450                 case DP_TRAINING_PATTERN_2:
2451                         *DP |= DP_LINK_TRAIN_PAT_2;
2452                         break;
2453                 case DP_TRAINING_PATTERN_3:
2454                         if (IS_CHERRYVIEW(dev)) {
2455                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2456                         } else {
2457                                 DRM_ERROR("DP training pattern 3 not supported\n");
2458                                 *DP |= DP_LINK_TRAIN_PAT_2;
2459                         }
2460                         break;
2461                 }
2462         }
2463 }
2464
2465 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2466 {
2467         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469
2470         intel_dp->DP |= DP_PORT_EN;
2471
2472         /* enable with pattern 1 (as per spec) */
2473         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2474                                  DP_TRAINING_PATTERN_1);
2475
2476         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2477         POSTING_READ(intel_dp->output_reg);
2478 }
2479
2480 static void intel_enable_dp(struct intel_encoder *encoder)
2481 {
2482         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2483         struct drm_device *dev = encoder->base.dev;
2484         struct drm_i915_private *dev_priv = dev->dev_private;
2485         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2486
2487         if (WARN_ON(dp_reg & DP_PORT_EN))
2488                 return;
2489
2490         intel_dp_enable_port(intel_dp);
2491         intel_edp_panel_vdd_on(intel_dp);
2492         intel_edp_panel_on(intel_dp);
2493         intel_edp_panel_vdd_off(intel_dp, true);
2494         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2495         intel_dp_start_link_train(intel_dp);
2496         intel_dp_complete_link_train(intel_dp);
2497         intel_dp_stop_link_train(intel_dp);
2498 }
2499
2500 static void g4x_enable_dp(struct intel_encoder *encoder)
2501 {
2502         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2503
2504         intel_enable_dp(encoder);
2505         intel_edp_backlight_on(intel_dp);
2506 }
2507
2508 static void vlv_enable_dp(struct intel_encoder *encoder)
2509 {
2510         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2511
2512         intel_edp_backlight_on(intel_dp);
2513 }
2514
2515 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2516 {
2517         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2518         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2519
2520         intel_dp_prepare(encoder);
2521
2522         /* Only ilk+ has port A */
2523         if (dport->port == PORT_A) {
2524                 ironlake_set_pll_cpu_edp(intel_dp);
2525                 ironlake_edp_pll_on(intel_dp);
2526         }
2527 }
2528
2529 static void vlv_steal_power_sequencer(struct drm_device *dev,
2530                                       enum pipe pipe)
2531 {
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533         struct intel_encoder *encoder;
2534
2535         lockdep_assert_held(&dev_priv->pps_mutex);
2536
2537         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2538                             base.head) {
2539                 struct intel_dp *intel_dp;
2540                 enum port port;
2541
2542                 if (encoder->type != INTEL_OUTPUT_EDP)
2543                         continue;
2544
2545                 intel_dp = enc_to_intel_dp(&encoder->base);
2546                 port = dp_to_dig_port(intel_dp)->port;
2547
2548                 if (intel_dp->pps_pipe != pipe)
2549                         continue;
2550
2551                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2552                               pipe_name(pipe), port_name(port));
2553
2554                 /* make sure vdd is off before we steal it */
2555                 edp_panel_vdd_off_sync(intel_dp);
2556
2557                 intel_dp->pps_pipe = INVALID_PIPE;
2558         }
2559 }
2560
2561 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2562 {
2563         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2564         struct intel_encoder *encoder = &intel_dig_port->base;
2565         struct drm_device *dev = encoder->base.dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2568         struct edp_power_seq power_seq;
2569
2570         lockdep_assert_held(&dev_priv->pps_mutex);
2571
2572         if (intel_dp->pps_pipe == crtc->pipe)
2573                 return;
2574
2575         /*
2576          * If another power sequencer was being used on this
2577          * port previously make sure to turn off vdd there while
2578          * we still have control of it.
2579          */
2580         if (intel_dp->pps_pipe != INVALID_PIPE)
2581                 edp_panel_vdd_off_sync(intel_dp);
2582
2583         /*
2584          * We may be stealing the power
2585          * sequencer from another port.
2586          */
2587         vlv_steal_power_sequencer(dev, crtc->pipe);
2588
2589         /* now it's all ours */
2590         intel_dp->pps_pipe = crtc->pipe;
2591
2592         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2593                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2594
2595         /* init power sequencer on this pipe and port */
2596         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2597         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2598                                                       &power_seq);
2599 }
2600
2601 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2602 {
2603         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2604         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2605         struct drm_device *dev = encoder->base.dev;
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2608         enum dpio_channel port = vlv_dport_to_channel(dport);
2609         int pipe = intel_crtc->pipe;
2610         u32 val;
2611
2612         mutex_lock(&dev_priv->dpio_lock);
2613
2614         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2615         val = 0;
2616         if (pipe)
2617                 val |= (1<<21);
2618         else
2619                 val &= ~(1<<21);
2620         val |= 0x001000c4;
2621         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2622         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2623         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2624
2625         mutex_unlock(&dev_priv->dpio_lock);
2626
2627         if (is_edp(intel_dp)) {
2628                 pps_lock(intel_dp);
2629                 vlv_init_panel_power_sequencer(intel_dp);
2630                 pps_unlock(intel_dp);
2631         }
2632
2633         intel_enable_dp(encoder);
2634
2635         vlv_wait_port_ready(dev_priv, dport);
2636 }
2637
2638 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2639 {
2640         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2641         struct drm_device *dev = encoder->base.dev;
2642         struct drm_i915_private *dev_priv = dev->dev_private;
2643         struct intel_crtc *intel_crtc =
2644                 to_intel_crtc(encoder->base.crtc);
2645         enum dpio_channel port = vlv_dport_to_channel(dport);
2646         int pipe = intel_crtc->pipe;
2647
2648         intel_dp_prepare(encoder);
2649
2650         /* Program Tx lane resets to default */
2651         mutex_lock(&dev_priv->dpio_lock);
2652         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2653                          DPIO_PCS_TX_LANE2_RESET |
2654                          DPIO_PCS_TX_LANE1_RESET);
2655         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2656                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2657                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2658                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2659                                  DPIO_PCS_CLK_SOFT_RESET);
2660
2661         /* Fix up inter-pair skew failure */
2662         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2663         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2664         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2665         mutex_unlock(&dev_priv->dpio_lock);
2666 }
2667
2668 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2669 {
2670         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2671         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2672         struct drm_device *dev = encoder->base.dev;
2673         struct drm_i915_private *dev_priv = dev->dev_private;
2674         struct intel_crtc *intel_crtc =
2675                 to_intel_crtc(encoder->base.crtc);
2676         enum dpio_channel ch = vlv_dport_to_channel(dport);
2677         int pipe = intel_crtc->pipe;
2678         int data, i;
2679         u32 val;
2680
2681         mutex_lock(&dev_priv->dpio_lock);
2682
2683         /* Deassert soft data lane reset*/
2684         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2685         val |= CHV_PCS_REQ_SOFTRESET_EN;
2686         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2687
2688         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2689         val |= CHV_PCS_REQ_SOFTRESET_EN;
2690         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2691
2692         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2693         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2694         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2695
2696         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2697         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2698         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2699
2700         /* Program Tx lane latency optimal setting*/
2701         for (i = 0; i < 4; i++) {
2702                 /* Set the latency optimal bit */
2703                 data = (i == 1) ? 0x0 : 0x6;
2704                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2705                                 data << DPIO_FRC_LATENCY_SHFIT);
2706
2707                 /* Set the upar bit */
2708                 data = (i == 1) ? 0x0 : 0x1;
2709                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2710                                 data << DPIO_UPAR_SHIFT);
2711         }
2712
2713         /* Data lane stagger programming */
2714         /* FIXME: Fix up value only after power analysis */
2715
2716         mutex_unlock(&dev_priv->dpio_lock);
2717
2718         if (is_edp(intel_dp)) {
2719                 pps_lock(intel_dp);
2720                 vlv_init_panel_power_sequencer(intel_dp);
2721                 pps_unlock(intel_dp);
2722         }
2723
2724         intel_enable_dp(encoder);
2725
2726         vlv_wait_port_ready(dev_priv, dport);
2727 }
2728
2729 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2730 {
2731         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2732         struct drm_device *dev = encoder->base.dev;
2733         struct drm_i915_private *dev_priv = dev->dev_private;
2734         struct intel_crtc *intel_crtc =
2735                 to_intel_crtc(encoder->base.crtc);
2736         enum dpio_channel ch = vlv_dport_to_channel(dport);
2737         enum pipe pipe = intel_crtc->pipe;
2738         u32 val;
2739
2740         intel_dp_prepare(encoder);
2741
2742         mutex_lock(&dev_priv->dpio_lock);
2743
2744         /* program left/right clock distribution */
2745         if (pipe != PIPE_B) {
2746                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2747                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2748                 if (ch == DPIO_CH0)
2749                         val |= CHV_BUFLEFTENA1_FORCE;
2750                 if (ch == DPIO_CH1)
2751                         val |= CHV_BUFRIGHTENA1_FORCE;
2752                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2753         } else {
2754                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2755                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2756                 if (ch == DPIO_CH0)
2757                         val |= CHV_BUFLEFTENA2_FORCE;
2758                 if (ch == DPIO_CH1)
2759                         val |= CHV_BUFRIGHTENA2_FORCE;
2760                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2761         }
2762
2763         /* program clock channel usage */
2764         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2765         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2766         if (pipe != PIPE_B)
2767                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2768         else
2769                 val |= CHV_PCS_USEDCLKCHANNEL;
2770         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2771
2772         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2773         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2774         if (pipe != PIPE_B)
2775                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2776         else
2777                 val |= CHV_PCS_USEDCLKCHANNEL;
2778         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2779
2780         /*
2781          * This a a bit weird since generally CL
2782          * matches the pipe, but here we need to
2783          * pick the CL based on the port.
2784          */
2785         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2786         if (pipe != PIPE_B)
2787                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2788         else
2789                 val |= CHV_CMN_USEDCLKCHANNEL;
2790         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2791
2792         mutex_unlock(&dev_priv->dpio_lock);
2793 }
2794
2795 /*
2796  * Native read with retry for link status and receiver capability reads for
2797  * cases where the sink may still be asleep.
2798  *
2799  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2800  * supposed to retry 3 times per the spec.
2801  */
2802 static ssize_t
2803 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2804                         void *buffer, size_t size)
2805 {
2806         ssize_t ret;
2807         int i;
2808
2809         for (i = 0; i < 3; i++) {
2810                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2811                 if (ret == size)
2812                         return ret;
2813                 msleep(1);
2814         }
2815
2816         return ret;
2817 }
2818
2819 /*
2820  * Fetch AUX CH registers 0x202 - 0x207 which contain
2821  * link status information
2822  */
2823 static bool
2824 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2825 {
2826         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2827                                        DP_LANE0_1_STATUS,
2828                                        link_status,
2829                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2830 }
2831
2832 /* These are source-specific values. */
2833 static uint8_t
2834 intel_dp_voltage_max(struct intel_dp *intel_dp)
2835 {
2836         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2837         enum port port = dp_to_dig_port(intel_dp)->port;
2838
2839         if (IS_VALLEYVIEW(dev))
2840                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2841         else if (IS_GEN7(dev) && port == PORT_A)
2842                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2843         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2844                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2845         else
2846                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2847 }
2848
2849 static uint8_t
2850 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2851 {
2852         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2853         enum port port = dp_to_dig_port(intel_dp)->port;
2854
2855         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2856                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2857                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2858                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2859                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2860                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2861                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2862                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2863                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2864                 default:
2865                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2866                 }
2867         } else if (IS_VALLEYVIEW(dev)) {
2868                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2869                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2870                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2871                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2872                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2873                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2874                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2875                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2876                 default:
2877                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2878                 }
2879         } else if (IS_GEN7(dev) && port == PORT_A) {
2880                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2881                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2882                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2883                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2884                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2885                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2886                 default:
2887                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2888                 }
2889         } else {
2890                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2891                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2892                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2893                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2894                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2895                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2896                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2897                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2898                 default:
2899                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2900                 }
2901         }
2902 }
2903
2904 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2905 {
2906         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2909         struct intel_crtc *intel_crtc =
2910                 to_intel_crtc(dport->base.base.crtc);
2911         unsigned long demph_reg_value, preemph_reg_value,
2912                 uniqtranscale_reg_value;
2913         uint8_t train_set = intel_dp->train_set[0];
2914         enum dpio_channel port = vlv_dport_to_channel(dport);
2915         int pipe = intel_crtc->pipe;
2916
2917         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2918         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2919                 preemph_reg_value = 0x0004000;
2920                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2921                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2922                         demph_reg_value = 0x2B405555;
2923                         uniqtranscale_reg_value = 0x552AB83A;
2924                         break;
2925                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2926                         demph_reg_value = 0x2B404040;
2927                         uniqtranscale_reg_value = 0x5548B83A;
2928                         break;
2929                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2930                         demph_reg_value = 0x2B245555;
2931                         uniqtranscale_reg_value = 0x5560B83A;
2932                         break;
2933                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2934                         demph_reg_value = 0x2B405555;
2935                         uniqtranscale_reg_value = 0x5598DA3A;
2936                         break;
2937                 default:
2938                         return 0;
2939                 }
2940                 break;
2941         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2942                 preemph_reg_value = 0x0002000;
2943                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2944                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2945                         demph_reg_value = 0x2B404040;
2946                         uniqtranscale_reg_value = 0x5552B83A;
2947                         break;
2948                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2949                         demph_reg_value = 0x2B404848;
2950                         uniqtranscale_reg_value = 0x5580B83A;
2951                         break;
2952                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2953                         demph_reg_value = 0x2B404040;
2954                         uniqtranscale_reg_value = 0x55ADDA3A;
2955                         break;
2956                 default:
2957                         return 0;
2958                 }
2959                 break;
2960         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2961                 preemph_reg_value = 0x0000000;
2962                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2963                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2964                         demph_reg_value = 0x2B305555;
2965                         uniqtranscale_reg_value = 0x5570B83A;
2966                         break;
2967                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2968                         demph_reg_value = 0x2B2B4040;
2969                         uniqtranscale_reg_value = 0x55ADDA3A;
2970                         break;
2971                 default:
2972                         return 0;
2973                 }
2974                 break;
2975         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2976                 preemph_reg_value = 0x0006000;
2977                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2978                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2979                         demph_reg_value = 0x1B405555;
2980                         uniqtranscale_reg_value = 0x55ADDA3A;
2981                         break;
2982                 default:
2983                         return 0;
2984                 }
2985                 break;
2986         default:
2987                 return 0;
2988         }
2989
2990         mutex_lock(&dev_priv->dpio_lock);
2991         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2992         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2993         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2994                          uniqtranscale_reg_value);
2995         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2996         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2997         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2998         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2999         mutex_unlock(&dev_priv->dpio_lock);
3000
3001         return 0;
3002 }
3003
3004 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3005 {
3006         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3009         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3010         u32 deemph_reg_value, margin_reg_value, val;
3011         uint8_t train_set = intel_dp->train_set[0];
3012         enum dpio_channel ch = vlv_dport_to_channel(dport);
3013         enum pipe pipe = intel_crtc->pipe;
3014         int i;
3015
3016         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3017         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3018                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3019                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3020                         deemph_reg_value = 128;
3021                         margin_reg_value = 52;
3022                         break;
3023                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3024                         deemph_reg_value = 128;
3025                         margin_reg_value = 77;
3026                         break;
3027                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3028                         deemph_reg_value = 128;
3029                         margin_reg_value = 102;
3030                         break;
3031                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3032                         deemph_reg_value = 128;
3033                         margin_reg_value = 154;
3034                         /* FIXME extra to set for 1200 */
3035                         break;
3036                 default:
3037                         return 0;
3038                 }
3039                 break;
3040         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3041                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3042                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3043                         deemph_reg_value = 85;
3044                         margin_reg_value = 78;
3045                         break;
3046                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3047                         deemph_reg_value = 85;
3048                         margin_reg_value = 116;
3049                         break;
3050                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3051                         deemph_reg_value = 85;
3052                         margin_reg_value = 154;
3053                         break;
3054                 default:
3055                         return 0;
3056                 }
3057                 break;
3058         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3059                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3060                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3061                         deemph_reg_value = 64;
3062                         margin_reg_value = 104;
3063                         break;
3064                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3065                         deemph_reg_value = 64;
3066                         margin_reg_value = 154;
3067                         break;
3068                 default:
3069                         return 0;
3070                 }
3071                 break;
3072         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3073                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3074                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3075                         deemph_reg_value = 43;
3076                         margin_reg_value = 154;
3077                         break;
3078                 default:
3079                         return 0;
3080                 }
3081                 break;
3082         default:
3083                 return 0;
3084         }
3085
3086         mutex_lock(&dev_priv->dpio_lock);
3087
3088         /* Clear calc init */
3089         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3090         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3091         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3092
3093         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3094         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3095         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3096
3097         /* Program swing deemph */
3098         for (i = 0; i < 4; i++) {
3099                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3100                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3101                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3102                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3103         }
3104
3105         /* Program swing margin */
3106         for (i = 0; i < 4; i++) {
3107                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3108                 val &= ~DPIO_SWING_MARGIN000_MASK;
3109                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3110                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3111         }
3112
3113         /* Disable unique transition scale */
3114         for (i = 0; i < 4; i++) {
3115                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3116                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3117                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3118         }
3119
3120         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3121                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3122                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3123                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3124
3125                 /*
3126                  * The document said it needs to set bit 27 for ch0 and bit 26
3127                  * for ch1. Might be a typo in the doc.
3128                  * For now, for this unique transition scale selection, set bit
3129                  * 27 for ch0 and ch1.
3130                  */
3131                 for (i = 0; i < 4; i++) {
3132                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3133                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3134                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3135                 }
3136
3137                 for (i = 0; i < 4; i++) {
3138                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3139                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3140                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3141                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3142                 }
3143         }
3144
3145         /* Start swing calculation */
3146         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3147         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3148         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3149
3150         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3151         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3152         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3153
3154         /* LRC Bypass */
3155         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3156         val |= DPIO_LRC_BYPASS;
3157         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3158
3159         mutex_unlock(&dev_priv->dpio_lock);
3160
3161         return 0;
3162 }
3163
3164 static void
3165 intel_get_adjust_train(struct intel_dp *intel_dp,
3166                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3167 {
3168         uint8_t v = 0;
3169         uint8_t p = 0;
3170         int lane;
3171         uint8_t voltage_max;
3172         uint8_t preemph_max;
3173
3174         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3175                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3176                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3177
3178                 if (this_v > v)
3179                         v = this_v;
3180                 if (this_p > p)
3181                         p = this_p;
3182         }
3183
3184         voltage_max = intel_dp_voltage_max(intel_dp);
3185         if (v >= voltage_max)
3186                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3187
3188         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3189         if (p >= preemph_max)
3190                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3191
3192         for (lane = 0; lane < 4; lane++)
3193                 intel_dp->train_set[lane] = v | p;
3194 }
3195
3196 static uint32_t
3197 intel_gen4_signal_levels(uint8_t train_set)
3198 {
3199         uint32_t        signal_levels = 0;
3200
3201         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3202         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3203         default:
3204                 signal_levels |= DP_VOLTAGE_0_4;
3205                 break;
3206         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3207                 signal_levels |= DP_VOLTAGE_0_6;
3208                 break;
3209         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3210                 signal_levels |= DP_VOLTAGE_0_8;
3211                 break;
3212         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3213                 signal_levels |= DP_VOLTAGE_1_2;
3214                 break;
3215         }
3216         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3217         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3218         default:
3219                 signal_levels |= DP_PRE_EMPHASIS_0;
3220                 break;
3221         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3222                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3223                 break;
3224         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3225                 signal_levels |= DP_PRE_EMPHASIS_6;
3226                 break;
3227         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3228                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3229                 break;
3230         }
3231         return signal_levels;
3232 }
3233
3234 /* Gen6's DP voltage swing and pre-emphasis control */
3235 static uint32_t
3236 intel_gen6_edp_signal_levels(uint8_t train_set)
3237 {
3238         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3239                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3240         switch (signal_levels) {
3241         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3242         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3243                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3244         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3245                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3246         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3247         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3248                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3249         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3250         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3251                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3252         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3253         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3254                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3255         default:
3256                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3257                               "0x%x\n", signal_levels);
3258                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3259         }
3260 }
3261
3262 /* Gen7's DP voltage swing and pre-emphasis control */
3263 static uint32_t
3264 intel_gen7_edp_signal_levels(uint8_t train_set)
3265 {
3266         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3267                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3268         switch (signal_levels) {
3269         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3270                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3271         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3272                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3273         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3274                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3275
3276         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3277                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3278         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3279                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3280
3281         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3282                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3283         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3284                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3285
3286         default:
3287                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3288                               "0x%x\n", signal_levels);
3289                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3290         }
3291 }
3292
3293 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3294 static uint32_t
3295 intel_hsw_signal_levels(uint8_t train_set)
3296 {
3297         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3298                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3299         switch (signal_levels) {
3300         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3301                 return DDI_BUF_TRANS_SELECT(0);
3302         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3303                 return DDI_BUF_TRANS_SELECT(1);
3304         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3305                 return DDI_BUF_TRANS_SELECT(2);
3306         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3307                 return DDI_BUF_TRANS_SELECT(3);
3308
3309         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3310                 return DDI_BUF_TRANS_SELECT(4);
3311         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3312                 return DDI_BUF_TRANS_SELECT(5);
3313         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3314                 return DDI_BUF_TRANS_SELECT(6);
3315
3316         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3317                 return DDI_BUF_TRANS_SELECT(7);
3318         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3319                 return DDI_BUF_TRANS_SELECT(8);
3320         default:
3321                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3322                               "0x%x\n", signal_levels);
3323                 return DDI_BUF_TRANS_SELECT(0);
3324         }
3325 }
3326
3327 /* Properly updates "DP" with the correct signal levels. */
3328 static void
3329 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3330 {
3331         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3332         enum port port = intel_dig_port->port;
3333         struct drm_device *dev = intel_dig_port->base.base.dev;
3334         uint32_t signal_levels, mask;
3335         uint8_t train_set = intel_dp->train_set[0];
3336
3337         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3338                 signal_levels = intel_hsw_signal_levels(train_set);
3339                 mask = DDI_BUF_EMP_MASK;
3340         } else if (IS_CHERRYVIEW(dev)) {
3341                 signal_levels = intel_chv_signal_levels(intel_dp);
3342                 mask = 0;
3343         } else if (IS_VALLEYVIEW(dev)) {
3344                 signal_levels = intel_vlv_signal_levels(intel_dp);
3345                 mask = 0;
3346         } else if (IS_GEN7(dev) && port == PORT_A) {
3347                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3348                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3349         } else if (IS_GEN6(dev) && port == PORT_A) {
3350                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3351                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3352         } else {
3353                 signal_levels = intel_gen4_signal_levels(train_set);
3354                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3355         }
3356
3357         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3358
3359         *DP = (*DP & ~mask) | signal_levels;
3360 }
3361
3362 static bool
3363 intel_dp_set_link_train(struct intel_dp *intel_dp,
3364                         uint32_t *DP,
3365                         uint8_t dp_train_pat)
3366 {
3367         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3368         struct drm_device *dev = intel_dig_port->base.base.dev;
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3371         int ret, len;
3372
3373         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3374
3375         I915_WRITE(intel_dp->output_reg, *DP);
3376         POSTING_READ(intel_dp->output_reg);
3377
3378         buf[0] = dp_train_pat;
3379         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3380             DP_TRAINING_PATTERN_DISABLE) {
3381                 /* don't write DP_TRAINING_LANEx_SET on disable */
3382                 len = 1;
3383         } else {
3384                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3385                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3386                 len = intel_dp->lane_count + 1;
3387         }
3388
3389         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3390                                 buf, len);
3391
3392         return ret == len;
3393 }
3394
3395 static bool
3396 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3397                         uint8_t dp_train_pat)
3398 {
3399         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3400         intel_dp_set_signal_levels(intel_dp, DP);
3401         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3402 }
3403
3404 static bool
3405 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3406                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3407 {
3408         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3409         struct drm_device *dev = intel_dig_port->base.base.dev;
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         int ret;
3412
3413         intel_get_adjust_train(intel_dp, link_status);
3414         intel_dp_set_signal_levels(intel_dp, DP);
3415
3416         I915_WRITE(intel_dp->output_reg, *DP);
3417         POSTING_READ(intel_dp->output_reg);
3418
3419         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3420                                 intel_dp->train_set, intel_dp->lane_count);
3421
3422         return ret == intel_dp->lane_count;
3423 }
3424
3425 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3426 {
3427         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3428         struct drm_device *dev = intel_dig_port->base.base.dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         enum port port = intel_dig_port->port;
3431         uint32_t val;
3432
3433         if (!HAS_DDI(dev))
3434                 return;
3435
3436         val = I915_READ(DP_TP_CTL(port));
3437         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3438         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3439         I915_WRITE(DP_TP_CTL(port), val);
3440
3441         /*
3442          * On PORT_A we can have only eDP in SST mode. There the only reason
3443          * we need to set idle transmission mode is to work around a HW issue
3444          * where we enable the pipe while not in idle link-training mode.
3445          * In this case there is requirement to wait for a minimum number of
3446          * idle patterns to be sent.
3447          */
3448         if (port == PORT_A)
3449                 return;
3450
3451         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3452                      1))
3453                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3454 }
3455
3456 /* Enable corresponding port and start training pattern 1 */
3457 void
3458 intel_dp_start_link_train(struct intel_dp *intel_dp)
3459 {
3460         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3461         struct drm_device *dev = encoder->dev;
3462         int i;
3463         uint8_t voltage;
3464         int voltage_tries, loop_tries;
3465         uint32_t DP = intel_dp->DP;
3466         uint8_t link_config[2];
3467
3468         if (HAS_DDI(dev))
3469                 intel_ddi_prepare_link_retrain(encoder);
3470
3471         /* Write the link configuration data */
3472         link_config[0] = intel_dp->link_bw;
3473         link_config[1] = intel_dp->lane_count;
3474         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3475                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3476         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3477
3478         link_config[0] = 0;
3479         link_config[1] = DP_SET_ANSI_8B10B;
3480         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3481
3482         DP |= DP_PORT_EN;
3483
3484         /* clock recovery */
3485         if (!intel_dp_reset_link_train(intel_dp, &DP,
3486                                        DP_TRAINING_PATTERN_1 |
3487                                        DP_LINK_SCRAMBLING_DISABLE)) {
3488                 DRM_ERROR("failed to enable link training\n");
3489                 return;
3490         }
3491
3492         voltage = 0xff;
3493         voltage_tries = 0;
3494         loop_tries = 0;
3495         for (;;) {
3496                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3497
3498                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3499                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3500                         DRM_ERROR("failed to get link status\n");
3501                         break;
3502                 }
3503
3504                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3505                         DRM_DEBUG_KMS("clock recovery OK\n");
3506                         break;
3507                 }
3508
3509                 /* Check to see if we've tried the max voltage */
3510                 for (i = 0; i < intel_dp->lane_count; i++)
3511                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3512                                 break;
3513                 if (i == intel_dp->lane_count) {
3514                         ++loop_tries;
3515                         if (loop_tries == 5) {
3516                                 DRM_ERROR("too many full retries, give up\n");
3517                                 break;
3518                         }
3519                         intel_dp_reset_link_train(intel_dp, &DP,
3520                                                   DP_TRAINING_PATTERN_1 |
3521                                                   DP_LINK_SCRAMBLING_DISABLE);
3522                         voltage_tries = 0;
3523                         continue;
3524                 }
3525
3526                 /* Check to see if we've tried the same voltage 5 times */
3527                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3528                         ++voltage_tries;
3529                         if (voltage_tries == 5) {
3530                                 DRM_ERROR("too many voltage retries, give up\n");
3531                                 break;
3532                         }
3533                 } else
3534                         voltage_tries = 0;
3535                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3536
3537                 /* Update training set as requested by target */
3538                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3539                         DRM_ERROR("failed to update link training\n");
3540                         break;
3541                 }
3542         }
3543
3544         intel_dp->DP = DP;
3545 }
3546
3547 void
3548 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3549 {
3550         bool channel_eq = false;
3551         int tries, cr_tries;
3552         uint32_t DP = intel_dp->DP;
3553         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3554
3555         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3556         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3557                 training_pattern = DP_TRAINING_PATTERN_3;
3558
3559         /* channel equalization */
3560         if (!intel_dp_set_link_train(intel_dp, &DP,
3561                                      training_pattern |
3562                                      DP_LINK_SCRAMBLING_DISABLE)) {
3563                 DRM_ERROR("failed to start channel equalization\n");
3564                 return;
3565         }
3566
3567         tries = 0;
3568         cr_tries = 0;
3569         channel_eq = false;
3570         for (;;) {
3571                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3572
3573                 if (cr_tries > 5) {
3574                         DRM_ERROR("failed to train DP, aborting\n");
3575                         break;
3576                 }
3577
3578                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3579                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3580                         DRM_ERROR("failed to get link status\n");
3581                         break;
3582                 }
3583
3584                 /* Make sure clock is still ok */
3585                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3586                         intel_dp_start_link_train(intel_dp);
3587                         intel_dp_set_link_train(intel_dp, &DP,
3588                                                 training_pattern |
3589                                                 DP_LINK_SCRAMBLING_DISABLE);
3590                         cr_tries++;
3591                         continue;
3592                 }
3593
3594                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3595                         channel_eq = true;
3596                         break;
3597                 }
3598
3599                 /* Try 5 times, then try clock recovery if that fails */
3600                 if (tries > 5) {
3601                         intel_dp_link_down(intel_dp);
3602                         intel_dp_start_link_train(intel_dp);
3603                         intel_dp_set_link_train(intel_dp, &DP,
3604                                                 training_pattern |
3605                                                 DP_LINK_SCRAMBLING_DISABLE);
3606                         tries = 0;
3607                         cr_tries++;
3608                         continue;
3609                 }
3610
3611                 /* Update training set as requested by target */
3612                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3613                         DRM_ERROR("failed to update link training\n");
3614                         break;
3615                 }
3616                 ++tries;
3617         }
3618
3619         intel_dp_set_idle_link_train(intel_dp);
3620
3621         intel_dp->DP = DP;
3622
3623         if (channel_eq)
3624                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3625
3626 }
3627
3628 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3629 {
3630         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3631                                 DP_TRAINING_PATTERN_DISABLE);
3632 }
3633
3634 static void
3635 intel_dp_link_down(struct intel_dp *intel_dp)
3636 {
3637         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3638         enum port port = intel_dig_port->port;
3639         struct drm_device *dev = intel_dig_port->base.base.dev;
3640         struct drm_i915_private *dev_priv = dev->dev_private;
3641         struct intel_crtc *intel_crtc =
3642                 to_intel_crtc(intel_dig_port->base.base.crtc);
3643         uint32_t DP = intel_dp->DP;
3644
3645         if (WARN_ON(HAS_DDI(dev)))
3646                 return;
3647
3648         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3649                 return;
3650
3651         DRM_DEBUG_KMS("\n");
3652
3653         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3654                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3655                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3656         } else {
3657                 if (IS_CHERRYVIEW(dev))
3658                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3659                 else
3660                         DP &= ~DP_LINK_TRAIN_MASK;
3661                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3662         }
3663         POSTING_READ(intel_dp->output_reg);
3664
3665         if (HAS_PCH_IBX(dev) &&
3666             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3667                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3668
3669                 /* Hardware workaround: leaving our transcoder select
3670                  * set to transcoder B while it's off will prevent the
3671                  * corresponding HDMI output on transcoder A.
3672                  *
3673                  * Combine this with another hardware workaround:
3674                  * transcoder select bit can only be cleared while the
3675                  * port is enabled.
3676                  */
3677                 DP &= ~DP_PIPEB_SELECT;
3678                 I915_WRITE(intel_dp->output_reg, DP);
3679
3680                 /* Changes to enable or select take place the vblank
3681                  * after being written.
3682                  */
3683                 if (WARN_ON(crtc == NULL)) {
3684                         /* We should never try to disable a port without a crtc
3685                          * attached. For paranoia keep the code around for a
3686                          * bit. */
3687                         POSTING_READ(intel_dp->output_reg);
3688                         msleep(50);
3689                 } else
3690                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3691         }
3692
3693         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3694         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3695         POSTING_READ(intel_dp->output_reg);
3696         msleep(intel_dp->panel_power_down_delay);
3697 }
3698
3699 static bool
3700 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3701 {
3702         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3703         struct drm_device *dev = dig_port->base.base.dev;
3704         struct drm_i915_private *dev_priv = dev->dev_private;
3705
3706         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3707                                     sizeof(intel_dp->dpcd)) < 0)
3708                 return false; /* aux transfer failed */
3709
3710         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3711
3712         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3713                 return false; /* DPCD not present */
3714
3715         /* Check if the panel supports PSR */
3716         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3717         if (is_edp(intel_dp)) {
3718                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3719                                         intel_dp->psr_dpcd,
3720                                         sizeof(intel_dp->psr_dpcd));
3721                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3722                         dev_priv->psr.sink_support = true;
3723                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3724                 }
3725         }
3726
3727         /* Training Pattern 3 support */
3728         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3729             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3730                 intel_dp->use_tps3 = true;
3731                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3732         } else
3733                 intel_dp->use_tps3 = false;
3734
3735         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3736               DP_DWN_STRM_PORT_PRESENT))
3737                 return true; /* native DP sink */
3738
3739         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3740                 return true; /* no per-port downstream info */
3741
3742         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3743                                     intel_dp->downstream_ports,
3744                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3745                 return false; /* downstream port status fetch failed */
3746
3747         return true;
3748 }
3749
3750 static void
3751 intel_dp_probe_oui(struct intel_dp *intel_dp)
3752 {
3753         u8 buf[3];
3754
3755         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3756                 return;
3757
3758         intel_edp_panel_vdd_on(intel_dp);
3759
3760         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3761                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3762                               buf[0], buf[1], buf[2]);
3763
3764         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3765                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3766                               buf[0], buf[1], buf[2]);
3767
3768         intel_edp_panel_vdd_off(intel_dp, false);
3769 }
3770
3771 static bool
3772 intel_dp_probe_mst(struct intel_dp *intel_dp)
3773 {
3774         u8 buf[1];
3775
3776         if (!intel_dp->can_mst)
3777                 return false;
3778
3779         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3780                 return false;
3781
3782         intel_edp_panel_vdd_on(intel_dp);
3783         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3784                 if (buf[0] & DP_MST_CAP) {
3785                         DRM_DEBUG_KMS("Sink is MST capable\n");
3786                         intel_dp->is_mst = true;
3787                 } else {
3788                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3789                         intel_dp->is_mst = false;
3790                 }
3791         }
3792         intel_edp_panel_vdd_off(intel_dp, false);
3793
3794         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3795         return intel_dp->is_mst;
3796 }
3797
3798 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3799 {
3800         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3801         struct drm_device *dev = intel_dig_port->base.base.dev;
3802         struct intel_crtc *intel_crtc =
3803                 to_intel_crtc(intel_dig_port->base.base.crtc);
3804         u8 buf[1];
3805
3806         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3807                 return -EIO;
3808
3809         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3810                 return -ENOTTY;
3811
3812         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3813                                DP_TEST_SINK_START) < 0)
3814                 return -EIO;
3815
3816         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3817         intel_wait_for_vblank(dev, intel_crtc->pipe);
3818         intel_wait_for_vblank(dev, intel_crtc->pipe);
3819
3820         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3821                 return -EIO;
3822
3823         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3824         return 0;
3825 }
3826
3827 static bool
3828 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3829 {
3830         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3831                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3832                                        sink_irq_vector, 1) == 1;
3833 }
3834
3835 static bool
3836 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3837 {
3838         int ret;
3839
3840         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3841                                              DP_SINK_COUNT_ESI,
3842                                              sink_irq_vector, 14);
3843         if (ret != 14)
3844                 return false;
3845
3846         return true;
3847 }
3848
3849 static void
3850 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3851 {
3852         /* NAK by default */
3853         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3854 }
3855
3856 static int
3857 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3858 {
3859         bool bret;
3860
3861         if (intel_dp->is_mst) {
3862                 u8 esi[16] = { 0 };
3863                 int ret = 0;
3864                 int retry;
3865                 bool handled;
3866                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3867 go_again:
3868                 if (bret == true) {
3869
3870                         /* check link status - esi[10] = 0x200c */
3871                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3872                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3873                                 intel_dp_start_link_train(intel_dp);
3874                                 intel_dp_complete_link_train(intel_dp);
3875                                 intel_dp_stop_link_train(intel_dp);
3876                         }
3877
3878                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3879                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3880
3881                         if (handled) {
3882                                 for (retry = 0; retry < 3; retry++) {
3883                                         int wret;
3884                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3885                                                                  DP_SINK_COUNT_ESI+1,
3886                                                                  &esi[1], 3);
3887                                         if (wret == 3) {
3888                                                 break;
3889                                         }
3890                                 }
3891
3892                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3893                                 if (bret == true) {
3894                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3895                                         goto go_again;
3896                                 }
3897                         } else
3898                                 ret = 0;
3899
3900                         return ret;
3901                 } else {
3902                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3903                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3904                         intel_dp->is_mst = false;
3905                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3906                         /* send a hotplug event */
3907                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3908                 }
3909         }
3910         return -EINVAL;
3911 }
3912
3913 /*
3914  * According to DP spec
3915  * 5.1.2:
3916  *  1. Read DPCD
3917  *  2. Configure link according to Receiver Capabilities
3918  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3919  *  4. Check link status on receipt of hot-plug interrupt
3920  */
3921 void
3922 intel_dp_check_link_status(struct intel_dp *intel_dp)
3923 {
3924         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3925         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3926         u8 sink_irq_vector;
3927         u8 link_status[DP_LINK_STATUS_SIZE];
3928
3929         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3930
3931         if (!intel_encoder->connectors_active)
3932                 return;
3933
3934         if (WARN_ON(!intel_encoder->base.crtc))
3935                 return;
3936
3937         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3938                 return;
3939
3940         /* Try to read receiver status if the link appears to be up */
3941         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3942                 return;
3943         }
3944
3945         /* Now read the DPCD to see if it's actually running */
3946         if (!intel_dp_get_dpcd(intel_dp)) {
3947                 return;
3948         }
3949
3950         /* Try to read the source of the interrupt */
3951         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3952             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3953                 /* Clear interrupt source */
3954                 drm_dp_dpcd_writeb(&intel_dp->aux,
3955                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3956                                    sink_irq_vector);
3957
3958                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3959                         intel_dp_handle_test_request(intel_dp);
3960                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3961                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3962         }
3963
3964         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3965                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3966                               intel_encoder->base.name);
3967                 intel_dp_start_link_train(intel_dp);
3968                 intel_dp_complete_link_train(intel_dp);
3969                 intel_dp_stop_link_train(intel_dp);
3970         }
3971 }
3972
3973 /* XXX this is probably wrong for multiple downstream ports */
3974 static enum drm_connector_status
3975 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3976 {
3977         uint8_t *dpcd = intel_dp->dpcd;
3978         uint8_t type;
3979
3980         if (!intel_dp_get_dpcd(intel_dp))
3981                 return connector_status_disconnected;
3982
3983         /* if there's no downstream port, we're done */
3984         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3985                 return connector_status_connected;
3986
3987         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3988         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3989             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3990                 uint8_t reg;
3991
3992                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3993                                             &reg, 1) < 0)
3994                         return connector_status_unknown;
3995
3996                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3997                                               : connector_status_disconnected;
3998         }
3999
4000         /* If no HPD, poke DDC gently */
4001         if (drm_probe_ddc(&intel_dp->aux.ddc))
4002                 return connector_status_connected;
4003
4004         /* Well we tried, say unknown for unreliable port types */
4005         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4006                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4007                 if (type == DP_DS_PORT_TYPE_VGA ||
4008                     type == DP_DS_PORT_TYPE_NON_EDID)
4009                         return connector_status_unknown;
4010         } else {
4011                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4012                         DP_DWN_STRM_PORT_TYPE_MASK;
4013                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4014                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4015                         return connector_status_unknown;
4016         }
4017
4018         /* Anything else is out of spec, warn and ignore */
4019         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4020         return connector_status_disconnected;
4021 }
4022
4023 static enum drm_connector_status
4024 edp_detect(struct intel_dp *intel_dp)
4025 {
4026         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4027         enum drm_connector_status status;
4028
4029         status = intel_panel_detect(dev);
4030         if (status == connector_status_unknown)
4031                 status = connector_status_connected;
4032
4033         return status;
4034 }
4035
4036 static enum drm_connector_status
4037 ironlake_dp_detect(struct intel_dp *intel_dp)
4038 {
4039         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4040         struct drm_i915_private *dev_priv = dev->dev_private;
4041         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4042
4043         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4044                 return connector_status_disconnected;
4045
4046         return intel_dp_detect_dpcd(intel_dp);
4047 }
4048
4049 static int g4x_digital_port_connected(struct drm_device *dev,
4050                                        struct intel_digital_port *intel_dig_port)
4051 {
4052         struct drm_i915_private *dev_priv = dev->dev_private;
4053         uint32_t bit;
4054
4055         if (IS_VALLEYVIEW(dev)) {
4056                 switch (intel_dig_port->port) {
4057                 case PORT_B:
4058                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4059                         break;
4060                 case PORT_C:
4061                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4062                         break;
4063                 case PORT_D:
4064                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4065                         break;
4066                 default:
4067                         return -EINVAL;
4068                 }
4069         } else {
4070                 switch (intel_dig_port->port) {
4071                 case PORT_B:
4072                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4073                         break;
4074                 case PORT_C:
4075                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4076                         break;
4077                 case PORT_D:
4078                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4079                         break;
4080                 default:
4081                         return -EINVAL;
4082                 }
4083         }
4084
4085         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4086                 return 0;
4087         return 1;
4088 }
4089
4090 static enum drm_connector_status
4091 g4x_dp_detect(struct intel_dp *intel_dp)
4092 {
4093         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4094         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4095         int ret;
4096
4097         /* Can't disconnect eDP, but you can close the lid... */
4098         if (is_edp(intel_dp)) {
4099                 enum drm_connector_status status;
4100
4101                 status = intel_panel_detect(dev);
4102                 if (status == connector_status_unknown)
4103                         status = connector_status_connected;
4104                 return status;
4105         }
4106
4107         ret = g4x_digital_port_connected(dev, intel_dig_port);
4108         if (ret == -EINVAL)
4109                 return connector_status_unknown;
4110         else if (ret == 0)
4111                 return connector_status_disconnected;
4112
4113         return intel_dp_detect_dpcd(intel_dp);
4114 }
4115
4116 static struct edid *
4117 intel_dp_get_edid(struct intel_dp *intel_dp)
4118 {
4119         struct intel_connector *intel_connector = intel_dp->attached_connector;
4120
4121         /* use cached edid if we have one */
4122         if (intel_connector->edid) {
4123                 /* invalid edid */
4124                 if (IS_ERR(intel_connector->edid))
4125                         return NULL;
4126
4127                 return drm_edid_duplicate(intel_connector->edid);
4128         } else
4129                 return drm_get_edid(&intel_connector->base,
4130                                     &intel_dp->aux.ddc);
4131 }
4132
4133 static void
4134 intel_dp_set_edid(struct intel_dp *intel_dp)
4135 {
4136         struct intel_connector *intel_connector = intel_dp->attached_connector;
4137         struct edid *edid;
4138
4139         edid = intel_dp_get_edid(intel_dp);
4140         intel_connector->detect_edid = edid;
4141
4142         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4143                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4144         else
4145                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4146 }
4147
4148 static void
4149 intel_dp_unset_edid(struct intel_dp *intel_dp)
4150 {
4151         struct intel_connector *intel_connector = intel_dp->attached_connector;
4152
4153         kfree(intel_connector->detect_edid);
4154         intel_connector->detect_edid = NULL;
4155
4156         intel_dp->has_audio = false;
4157 }
4158
4159 static enum intel_display_power_domain
4160 intel_dp_power_get(struct intel_dp *dp)
4161 {
4162         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4163         enum intel_display_power_domain power_domain;
4164
4165         power_domain = intel_display_port_power_domain(encoder);
4166         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4167
4168         return power_domain;
4169 }
4170
4171 static void
4172 intel_dp_power_put(struct intel_dp *dp,
4173                    enum intel_display_power_domain power_domain)
4174 {
4175         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4176         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4177 }
4178
4179 static enum drm_connector_status
4180 intel_dp_detect(struct drm_connector *connector, bool force)
4181 {
4182         struct intel_dp *intel_dp = intel_attached_dp(connector);
4183         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4184         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4185         struct drm_device *dev = connector->dev;
4186         enum drm_connector_status status;
4187         enum intel_display_power_domain power_domain;
4188         bool ret;
4189
4190         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4191                       connector->base.id, connector->name);
4192         intel_dp_unset_edid(intel_dp);
4193
4194         if (intel_dp->is_mst) {
4195                 /* MST devices are disconnected from a monitor POV */
4196                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4197                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4198                 return connector_status_disconnected;
4199         }
4200
4201         power_domain = intel_dp_power_get(intel_dp);
4202
4203         /* Can't disconnect eDP, but you can close the lid... */
4204         if (is_edp(intel_dp))
4205                 status = edp_detect(intel_dp);
4206         else if (HAS_PCH_SPLIT(dev))
4207                 status = ironlake_dp_detect(intel_dp);
4208         else
4209                 status = g4x_dp_detect(intel_dp);
4210         if (status != connector_status_connected)
4211                 goto out;
4212
4213         intel_dp_probe_oui(intel_dp);
4214
4215         ret = intel_dp_probe_mst(intel_dp);
4216         if (ret) {
4217                 /* if we are in MST mode then this connector
4218                    won't appear connected or have anything with EDID on it */
4219                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4220                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4221                 status = connector_status_disconnected;
4222                 goto out;
4223         }
4224
4225         intel_dp_set_edid(intel_dp);
4226
4227         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4228                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4229         status = connector_status_connected;
4230
4231 out:
4232         intel_dp_power_put(intel_dp, power_domain);
4233         return status;
4234 }
4235
4236 static void
4237 intel_dp_force(struct drm_connector *connector)
4238 {
4239         struct intel_dp *intel_dp = intel_attached_dp(connector);
4240         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4241         enum intel_display_power_domain power_domain;
4242
4243         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4244                       connector->base.id, connector->name);
4245         intel_dp_unset_edid(intel_dp);
4246
4247         if (connector->status != connector_status_connected)
4248                 return;
4249
4250         power_domain = intel_dp_power_get(intel_dp);
4251
4252         intel_dp_set_edid(intel_dp);
4253
4254         intel_dp_power_put(intel_dp, power_domain);
4255
4256         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4257                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4258 }
4259
4260 static int intel_dp_get_modes(struct drm_connector *connector)
4261 {
4262         struct intel_connector *intel_connector = to_intel_connector(connector);
4263         struct edid *edid;
4264
4265         edid = intel_connector->detect_edid;
4266         if (edid) {
4267                 int ret = intel_connector_update_modes(connector, edid);
4268                 if (ret)
4269                         return ret;
4270         }
4271
4272         /* if eDP has no EDID, fall back to fixed mode */
4273         if (is_edp(intel_attached_dp(connector)) &&
4274             intel_connector->panel.fixed_mode) {
4275                 struct drm_display_mode *mode;
4276
4277                 mode = drm_mode_duplicate(connector->dev,
4278                                           intel_connector->panel.fixed_mode);
4279                 if (mode) {
4280                         drm_mode_probed_add(connector, mode);
4281                         return 1;
4282                 }
4283         }
4284
4285         return 0;
4286 }
4287
4288 static bool
4289 intel_dp_detect_audio(struct drm_connector *connector)
4290 {
4291         bool has_audio = false;
4292         struct edid *edid;
4293
4294         edid = to_intel_connector(connector)->detect_edid;
4295         if (edid)
4296                 has_audio = drm_detect_monitor_audio(edid);
4297
4298         return has_audio;
4299 }
4300
4301 static int
4302 intel_dp_set_property(struct drm_connector *connector,
4303                       struct drm_property *property,
4304                       uint64_t val)
4305 {
4306         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4307         struct intel_connector *intel_connector = to_intel_connector(connector);
4308         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4309         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4310         int ret;
4311
4312         ret = drm_object_property_set_value(&connector->base, property, val);
4313         if (ret)
4314                 return ret;
4315
4316         if (property == dev_priv->force_audio_property) {
4317                 int i = val;
4318                 bool has_audio;
4319
4320                 if (i == intel_dp->force_audio)
4321                         return 0;
4322
4323                 intel_dp->force_audio = i;
4324
4325                 if (i == HDMI_AUDIO_AUTO)
4326                         has_audio = intel_dp_detect_audio(connector);
4327                 else
4328                         has_audio = (i == HDMI_AUDIO_ON);
4329
4330                 if (has_audio == intel_dp->has_audio)
4331                         return 0;
4332
4333                 intel_dp->has_audio = has_audio;
4334                 goto done;
4335         }
4336
4337         if (property == dev_priv->broadcast_rgb_property) {
4338                 bool old_auto = intel_dp->color_range_auto;
4339                 uint32_t old_range = intel_dp->color_range;
4340
4341                 switch (val) {
4342                 case INTEL_BROADCAST_RGB_AUTO:
4343                         intel_dp->color_range_auto = true;
4344                         break;
4345                 case INTEL_BROADCAST_RGB_FULL:
4346                         intel_dp->color_range_auto = false;
4347                         intel_dp->color_range = 0;
4348                         break;
4349                 case INTEL_BROADCAST_RGB_LIMITED:
4350                         intel_dp->color_range_auto = false;
4351                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4352                         break;
4353                 default:
4354                         return -EINVAL;
4355                 }
4356
4357                 if (old_auto == intel_dp->color_range_auto &&
4358                     old_range == intel_dp->color_range)
4359                         return 0;
4360
4361                 goto done;
4362         }
4363
4364         if (is_edp(intel_dp) &&
4365             property == connector->dev->mode_config.scaling_mode_property) {
4366                 if (val == DRM_MODE_SCALE_NONE) {
4367                         DRM_DEBUG_KMS("no scaling not supported\n");
4368                         return -EINVAL;
4369                 }
4370
4371                 if (intel_connector->panel.fitting_mode == val) {
4372                         /* the eDP scaling property is not changed */
4373                         return 0;
4374                 }
4375                 intel_connector->panel.fitting_mode = val;
4376
4377                 goto done;
4378         }
4379
4380         return -EINVAL;
4381
4382 done:
4383         if (intel_encoder->base.crtc)
4384                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4385
4386         return 0;
4387 }
4388
4389 static void
4390 intel_dp_connector_destroy(struct drm_connector *connector)
4391 {
4392         struct intel_connector *intel_connector = to_intel_connector(connector);
4393
4394         kfree(intel_connector->detect_edid);
4395
4396         if (!IS_ERR_OR_NULL(intel_connector->edid))
4397                 kfree(intel_connector->edid);
4398
4399         /* Can't call is_edp() since the encoder may have been destroyed
4400          * already. */
4401         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4402                 intel_panel_fini(&intel_connector->panel);
4403
4404         drm_connector_cleanup(connector);
4405         kfree(connector);
4406 }
4407
4408 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4409 {
4410         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4411         struct intel_dp *intel_dp = &intel_dig_port->dp;
4412
4413         drm_dp_aux_unregister(&intel_dp->aux);
4414         intel_dp_mst_encoder_cleanup(intel_dig_port);
4415         drm_encoder_cleanup(encoder);
4416         if (is_edp(intel_dp)) {
4417                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4418                 /*
4419                  * vdd might still be enabled do to the delayed vdd off.
4420                  * Make sure vdd is actually turned off here.
4421                  */
4422                 pps_lock(intel_dp);
4423                 edp_panel_vdd_off_sync(intel_dp);
4424                 pps_unlock(intel_dp);
4425
4426                 if (intel_dp->edp_notifier.notifier_call) {
4427                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4428                         intel_dp->edp_notifier.notifier_call = NULL;
4429                 }
4430         }
4431         kfree(intel_dig_port);
4432 }
4433
4434 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4435 {
4436         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4437
4438         if (!is_edp(intel_dp))
4439                 return;
4440
4441         /*
4442          * vdd might still be enabled do to the delayed vdd off.
4443          * Make sure vdd is actually turned off here.
4444          */
4445         pps_lock(intel_dp);
4446         edp_panel_vdd_off_sync(intel_dp);
4447         pps_unlock(intel_dp);
4448 }
4449
4450 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4451 {
4452         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4453 }
4454
4455 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4456         .dpms = intel_connector_dpms,
4457         .detect = intel_dp_detect,
4458         .force = intel_dp_force,
4459         .fill_modes = drm_helper_probe_single_connector_modes,
4460         .set_property = intel_dp_set_property,
4461         .destroy = intel_dp_connector_destroy,
4462 };
4463
4464 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4465         .get_modes = intel_dp_get_modes,
4466         .mode_valid = intel_dp_mode_valid,
4467         .best_encoder = intel_best_encoder,
4468 };
4469
4470 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4471         .reset = intel_dp_encoder_reset,
4472         .destroy = intel_dp_encoder_destroy,
4473 };
4474
4475 void
4476 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4477 {
4478         return;
4479 }
4480
4481 bool
4482 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4483 {
4484         struct intel_dp *intel_dp = &intel_dig_port->dp;
4485         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4486         struct drm_device *dev = intel_dig_port->base.base.dev;
4487         struct drm_i915_private *dev_priv = dev->dev_private;
4488         enum intel_display_power_domain power_domain;
4489         bool ret = true;
4490
4491         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4492                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4493
4494         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4495                       port_name(intel_dig_port->port),
4496                       long_hpd ? "long" : "short");
4497
4498         power_domain = intel_display_port_power_domain(intel_encoder);
4499         intel_display_power_get(dev_priv, power_domain);
4500
4501         if (long_hpd) {
4502
4503                 if (HAS_PCH_SPLIT(dev)) {
4504                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4505                                 goto mst_fail;
4506                 } else {
4507                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4508                                 goto mst_fail;
4509                 }
4510
4511                 if (!intel_dp_get_dpcd(intel_dp)) {
4512                         goto mst_fail;
4513                 }
4514
4515                 intel_dp_probe_oui(intel_dp);
4516
4517                 if (!intel_dp_probe_mst(intel_dp))
4518                         goto mst_fail;
4519
4520         } else {
4521                 if (intel_dp->is_mst) {
4522                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4523                                 goto mst_fail;
4524                 }
4525
4526                 if (!intel_dp->is_mst) {
4527                         /*
4528                          * we'll check the link status via the normal hot plug path later -
4529                          * but for short hpds we should check it now
4530                          */
4531                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4532                         intel_dp_check_link_status(intel_dp);
4533                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4534                 }
4535         }
4536         ret = false;
4537         goto put_power;
4538 mst_fail:
4539         /* if we were in MST mode, and device is not there get out of MST mode */
4540         if (intel_dp->is_mst) {
4541                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4542                 intel_dp->is_mst = false;
4543                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4544         }
4545 put_power:
4546         intel_display_power_put(dev_priv, power_domain);
4547
4548         return ret;
4549 }
4550
4551 /* Return which DP Port should be selected for Transcoder DP control */
4552 int
4553 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4554 {
4555         struct drm_device *dev = crtc->dev;
4556         struct intel_encoder *intel_encoder;
4557         struct intel_dp *intel_dp;
4558
4559         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4560                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4561
4562                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4563                     intel_encoder->type == INTEL_OUTPUT_EDP)
4564                         return intel_dp->output_reg;
4565         }
4566
4567         return -1;
4568 }
4569
4570 /* check the VBT to see whether the eDP is on DP-D port */
4571 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4572 {
4573         struct drm_i915_private *dev_priv = dev->dev_private;
4574         union child_device_config *p_child;
4575         int i;
4576         static const short port_mapping[] = {
4577                 [PORT_B] = PORT_IDPB,
4578                 [PORT_C] = PORT_IDPC,
4579                 [PORT_D] = PORT_IDPD,
4580         };
4581
4582         if (port == PORT_A)
4583                 return true;
4584
4585         if (!dev_priv->vbt.child_dev_num)
4586                 return false;
4587
4588         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4589                 p_child = dev_priv->vbt.child_dev + i;
4590
4591                 if (p_child->common.dvo_port == port_mapping[port] &&
4592                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4593                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4594                         return true;
4595         }
4596         return false;
4597 }
4598
4599 void
4600 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4601 {
4602         struct intel_connector *intel_connector = to_intel_connector(connector);
4603
4604         intel_attach_force_audio_property(connector);
4605         intel_attach_broadcast_rgb_property(connector);
4606         intel_dp->color_range_auto = true;
4607
4608         if (is_edp(intel_dp)) {
4609                 drm_mode_create_scaling_mode_property(connector->dev);
4610                 drm_object_attach_property(
4611                         &connector->base,
4612                         connector->dev->mode_config.scaling_mode_property,
4613                         DRM_MODE_SCALE_ASPECT);
4614                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4615         }
4616 }
4617
4618 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4619 {
4620         intel_dp->last_power_cycle = jiffies;
4621         intel_dp->last_power_on = jiffies;
4622         intel_dp->last_backlight_off = jiffies;
4623 }
4624
4625 static void
4626 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4627                                     struct intel_dp *intel_dp,
4628                                     struct edp_power_seq *out)
4629 {
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631         struct edp_power_seq cur, vbt, spec, final;
4632         u32 pp_on, pp_off, pp_div, pp;
4633         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4634
4635         lockdep_assert_held(&dev_priv->pps_mutex);
4636
4637         if (HAS_PCH_SPLIT(dev)) {
4638                 pp_ctrl_reg = PCH_PP_CONTROL;
4639                 pp_on_reg = PCH_PP_ON_DELAYS;
4640                 pp_off_reg = PCH_PP_OFF_DELAYS;
4641                 pp_div_reg = PCH_PP_DIVISOR;
4642         } else {
4643                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4644
4645                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4646                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4647                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4648                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4649         }
4650
4651         /* Workaround: Need to write PP_CONTROL with the unlock key as
4652          * the very first thing. */
4653         pp = ironlake_get_pp_control(intel_dp);
4654         I915_WRITE(pp_ctrl_reg, pp);
4655
4656         pp_on = I915_READ(pp_on_reg);
4657         pp_off = I915_READ(pp_off_reg);
4658         pp_div = I915_READ(pp_div_reg);
4659
4660         /* Pull timing values out of registers */
4661         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4662                 PANEL_POWER_UP_DELAY_SHIFT;
4663
4664         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4665                 PANEL_LIGHT_ON_DELAY_SHIFT;
4666
4667         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4668                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4669
4670         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4671                 PANEL_POWER_DOWN_DELAY_SHIFT;
4672
4673         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4674                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4675
4676         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4677                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4678
4679         vbt = dev_priv->vbt.edp_pps;
4680
4681         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4682          * our hw here, which are all in 100usec. */
4683         spec.t1_t3 = 210 * 10;
4684         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4685         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4686         spec.t10 = 500 * 10;
4687         /* This one is special and actually in units of 100ms, but zero
4688          * based in the hw (so we need to add 100 ms). But the sw vbt
4689          * table multiplies it with 1000 to make it in units of 100usec,
4690          * too. */
4691         spec.t11_t12 = (510 + 100) * 10;
4692
4693         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4694                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4695
4696         /* Use the max of the register settings and vbt. If both are
4697          * unset, fall back to the spec limits. */
4698 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4699                                        spec.field : \
4700                                        max(cur.field, vbt.field))
4701         assign_final(t1_t3);
4702         assign_final(t8);
4703         assign_final(t9);
4704         assign_final(t10);
4705         assign_final(t11_t12);
4706 #undef assign_final
4707
4708 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4709         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4710         intel_dp->backlight_on_delay = get_delay(t8);
4711         intel_dp->backlight_off_delay = get_delay(t9);
4712         intel_dp->panel_power_down_delay = get_delay(t10);
4713         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4714 #undef get_delay
4715
4716         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4717                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4718                       intel_dp->panel_power_cycle_delay);
4719
4720         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4721                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4722
4723         if (out)
4724                 *out = final;
4725 }
4726
4727 static void
4728 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4729                                               struct intel_dp *intel_dp,
4730                                               struct edp_power_seq *seq)
4731 {
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733         u32 pp_on, pp_off, pp_div, port_sel = 0;
4734         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4735         int pp_on_reg, pp_off_reg, pp_div_reg;
4736         enum port port = dp_to_dig_port(intel_dp)->port;
4737
4738         lockdep_assert_held(&dev_priv->pps_mutex);
4739
4740         if (HAS_PCH_SPLIT(dev)) {
4741                 pp_on_reg = PCH_PP_ON_DELAYS;
4742                 pp_off_reg = PCH_PP_OFF_DELAYS;
4743                 pp_div_reg = PCH_PP_DIVISOR;
4744         } else {
4745                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4746
4747                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4748                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4749                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4750         }
4751
4752         /*
4753          * And finally store the new values in the power sequencer. The
4754          * backlight delays are set to 1 because we do manual waits on them. For
4755          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4756          * we'll end up waiting for the backlight off delay twice: once when we
4757          * do the manual sleep, and once when we disable the panel and wait for
4758          * the PP_STATUS bit to become zero.
4759          */
4760         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4761                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4762         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4763                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4764         /* Compute the divisor for the pp clock, simply match the Bspec
4765          * formula. */
4766         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4767         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4768                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4769
4770         /* Haswell doesn't have any port selection bits for the panel
4771          * power sequencer any more. */
4772         if (IS_VALLEYVIEW(dev)) {
4773                 port_sel = PANEL_PORT_SELECT_VLV(port);
4774         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4775                 if (port == PORT_A)
4776                         port_sel = PANEL_PORT_SELECT_DPA;
4777                 else
4778                         port_sel = PANEL_PORT_SELECT_DPD;
4779         }
4780
4781         pp_on |= port_sel;
4782
4783         I915_WRITE(pp_on_reg, pp_on);
4784         I915_WRITE(pp_off_reg, pp_off);
4785         I915_WRITE(pp_div_reg, pp_div);
4786
4787         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4788                       I915_READ(pp_on_reg),
4789                       I915_READ(pp_off_reg),
4790                       I915_READ(pp_div_reg));
4791 }
4792
4793 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4794 {
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796         struct intel_encoder *encoder;
4797         struct intel_dp *intel_dp = NULL;
4798         struct intel_crtc_config *config = NULL;
4799         struct intel_crtc *intel_crtc = NULL;
4800         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4801         u32 reg, val;
4802         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4803
4804         if (refresh_rate <= 0) {
4805                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4806                 return;
4807         }
4808
4809         if (intel_connector == NULL) {
4810                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4811                 return;
4812         }
4813
4814         /*
4815          * FIXME: This needs proper synchronization with psr state. But really
4816          * hard to tell without seeing the user of this function of this code.
4817          * Check locking and ordering once that lands.
4818          */
4819         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4820                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4821                 return;
4822         }
4823
4824         encoder = intel_attached_encoder(&intel_connector->base);
4825         intel_dp = enc_to_intel_dp(&encoder->base);
4826         intel_crtc = encoder->new_crtc;
4827
4828         if (!intel_crtc) {
4829                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4830                 return;
4831         }
4832
4833         config = &intel_crtc->config;
4834
4835         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4836                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4837                 return;
4838         }
4839
4840         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4841                 index = DRRS_LOW_RR;
4842
4843         if (index == intel_dp->drrs_state.refresh_rate_type) {
4844                 DRM_DEBUG_KMS(
4845                         "DRRS requested for previously set RR...ignoring\n");
4846                 return;
4847         }
4848
4849         if (!intel_crtc->active) {
4850                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4851                 return;
4852         }
4853
4854         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4855                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4856                 val = I915_READ(reg);
4857                 if (index > DRRS_HIGH_RR) {
4858                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4859                         intel_dp_set_m_n(intel_crtc);
4860                 } else {
4861                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4862                 }
4863                 I915_WRITE(reg, val);
4864         }
4865
4866         /*
4867          * mutex taken to ensure that there is no race between differnt
4868          * drrs calls trying to update refresh rate. This scenario may occur
4869          * in future when idleness detection based DRRS in kernel and
4870          * possible calls from user space to set differnt RR are made.
4871          */
4872
4873         mutex_lock(&intel_dp->drrs_state.mutex);
4874
4875         intel_dp->drrs_state.refresh_rate_type = index;
4876
4877         mutex_unlock(&intel_dp->drrs_state.mutex);
4878
4879         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4880 }
4881
4882 static struct drm_display_mode *
4883 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4884                         struct intel_connector *intel_connector,
4885                         struct drm_display_mode *fixed_mode)
4886 {
4887         struct drm_connector *connector = &intel_connector->base;
4888         struct intel_dp *intel_dp = &intel_dig_port->dp;
4889         struct drm_device *dev = intel_dig_port->base.base.dev;
4890         struct drm_i915_private *dev_priv = dev->dev_private;
4891         struct drm_display_mode *downclock_mode = NULL;
4892
4893         if (INTEL_INFO(dev)->gen <= 6) {
4894                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4895                 return NULL;
4896         }
4897
4898         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4899                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4900                 return NULL;
4901         }
4902
4903         downclock_mode = intel_find_panel_downclock
4904                                         (dev, fixed_mode, connector);
4905
4906         if (!downclock_mode) {
4907                 DRM_DEBUG_KMS("DRRS not supported\n");
4908                 return NULL;
4909         }
4910
4911         dev_priv->drrs.connector = intel_connector;
4912
4913         mutex_init(&intel_dp->drrs_state.mutex);
4914
4915         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4916
4917         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4918         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4919         return downclock_mode;
4920 }
4921
4922 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4923 {
4924         struct drm_device *dev = intel_encoder->base.dev;
4925         struct drm_i915_private *dev_priv = dev->dev_private;
4926         struct intel_dp *intel_dp;
4927         enum intel_display_power_domain power_domain;
4928
4929         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4930                 return;
4931
4932         intel_dp = enc_to_intel_dp(&intel_encoder->base);
4933
4934         pps_lock(intel_dp);
4935
4936         if (!edp_have_panel_vdd(intel_dp))
4937                 goto out;
4938         /*
4939          * The VDD bit needs a power domain reference, so if the bit is
4940          * already enabled when we boot or resume, grab this reference and
4941          * schedule a vdd off, so we don't hold on to the reference
4942          * indefinitely.
4943          */
4944         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4945         power_domain = intel_display_port_power_domain(intel_encoder);
4946         intel_display_power_get(dev_priv, power_domain);
4947
4948         edp_panel_vdd_schedule_off(intel_dp);
4949  out:
4950         pps_unlock(intel_dp);
4951 }
4952
4953 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4954                                      struct intel_connector *intel_connector,
4955                                      struct edp_power_seq *power_seq)
4956 {
4957         struct drm_connector *connector = &intel_connector->base;
4958         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4959         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4960         struct drm_device *dev = intel_encoder->base.dev;
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962         struct drm_display_mode *fixed_mode = NULL;
4963         struct drm_display_mode *downclock_mode = NULL;
4964         bool has_dpcd;
4965         struct drm_display_mode *scan;
4966         struct edid *edid;
4967
4968         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4969
4970         if (!is_edp(intel_dp))
4971                 return true;
4972
4973         intel_edp_panel_vdd_sanitize(intel_encoder);
4974
4975         /* Cache DPCD and EDID for edp. */
4976         intel_edp_panel_vdd_on(intel_dp);
4977         has_dpcd = intel_dp_get_dpcd(intel_dp);
4978         intel_edp_panel_vdd_off(intel_dp, false);
4979
4980         if (has_dpcd) {
4981                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4982                         dev_priv->no_aux_handshake =
4983                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4984                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4985         } else {
4986                 /* if this fails, presume the device is a ghost */
4987                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4988                 return false;
4989         }
4990
4991         /* We now know it's not a ghost, init power sequence regs. */
4992         pps_lock(intel_dp);
4993         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4994         pps_unlock(intel_dp);
4995
4996         mutex_lock(&dev->mode_config.mutex);
4997         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4998         if (edid) {
4999                 if (drm_add_edid_modes(connector, edid)) {
5000                         drm_mode_connector_update_edid_property(connector,
5001                                                                 edid);
5002                         drm_edid_to_eld(connector, edid);
5003                 } else {
5004                         kfree(edid);
5005                         edid = ERR_PTR(-EINVAL);
5006                 }
5007         } else {
5008                 edid = ERR_PTR(-ENOENT);
5009         }
5010         intel_connector->edid = edid;
5011
5012         /* prefer fixed mode from EDID if available */
5013         list_for_each_entry(scan, &connector->probed_modes, head) {
5014                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5015                         fixed_mode = drm_mode_duplicate(dev, scan);
5016                         downclock_mode = intel_dp_drrs_init(
5017                                                 intel_dig_port,
5018                                                 intel_connector, fixed_mode);
5019                         break;
5020                 }
5021         }
5022
5023         /* fallback to VBT if available for eDP */
5024         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5025                 fixed_mode = drm_mode_duplicate(dev,
5026                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5027                 if (fixed_mode)
5028                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5029         }
5030         mutex_unlock(&dev->mode_config.mutex);
5031
5032         if (IS_VALLEYVIEW(dev)) {
5033                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5034                 register_reboot_notifier(&intel_dp->edp_notifier);
5035         }
5036
5037         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5038         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5039         intel_panel_setup_backlight(connector);
5040
5041         return true;
5042 }
5043
5044 bool
5045 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5046                         struct intel_connector *intel_connector)
5047 {
5048         struct drm_connector *connector = &intel_connector->base;
5049         struct intel_dp *intel_dp = &intel_dig_port->dp;
5050         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5051         struct drm_device *dev = intel_encoder->base.dev;
5052         struct drm_i915_private *dev_priv = dev->dev_private;
5053         enum port port = intel_dig_port->port;
5054         struct edp_power_seq power_seq = { 0 };
5055         int type;
5056
5057         intel_dp->pps_pipe = INVALID_PIPE;
5058
5059         /* intel_dp vfuncs */
5060         if (IS_VALLEYVIEW(dev))
5061                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5062         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5063                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5064         else if (HAS_PCH_SPLIT(dev))
5065                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5066         else
5067                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5068
5069         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5070
5071         /* Preserve the current hw state. */
5072         intel_dp->DP = I915_READ(intel_dp->output_reg);
5073         intel_dp->attached_connector = intel_connector;
5074
5075         if (intel_dp_is_edp(dev, port))
5076                 type = DRM_MODE_CONNECTOR_eDP;
5077         else
5078                 type = DRM_MODE_CONNECTOR_DisplayPort;
5079
5080         /*
5081          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5082          * for DP the encoder type can be set by the caller to
5083          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5084          */
5085         if (type == DRM_MODE_CONNECTOR_eDP)
5086                 intel_encoder->type = INTEL_OUTPUT_EDP;
5087
5088         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5089                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5090                         port_name(port));
5091
5092         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5093         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5094
5095         connector->interlace_allowed = true;
5096         connector->doublescan_allowed = 0;
5097
5098         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5099                           edp_panel_vdd_work);
5100
5101         intel_connector_attach_encoder(intel_connector, intel_encoder);
5102         drm_connector_register(connector);
5103
5104         if (HAS_DDI(dev))
5105                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5106         else
5107                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5108         intel_connector->unregister = intel_dp_connector_unregister;
5109
5110         /* Set up the hotplug pin. */
5111         switch (port) {
5112         case PORT_A:
5113                 intel_encoder->hpd_pin = HPD_PORT_A;
5114                 break;
5115         case PORT_B:
5116                 intel_encoder->hpd_pin = HPD_PORT_B;
5117                 break;
5118         case PORT_C:
5119                 intel_encoder->hpd_pin = HPD_PORT_C;
5120                 break;
5121         case PORT_D:
5122                 intel_encoder->hpd_pin = HPD_PORT_D;
5123                 break;
5124         default:
5125                 BUG();
5126         }
5127
5128         if (is_edp(intel_dp)) {
5129                 pps_lock(intel_dp);
5130                 if (IS_VALLEYVIEW(dev)) {
5131                         vlv_initial_power_sequencer_setup(intel_dp);
5132                 } else {
5133                         intel_dp_init_panel_power_timestamps(intel_dp);
5134                         intel_dp_init_panel_power_sequencer(dev, intel_dp,
5135                                                             &power_seq);
5136                 }
5137                 pps_unlock(intel_dp);
5138         }
5139
5140         intel_dp_aux_init(intel_dp, intel_connector);
5141
5142         /* init MST on ports that can support it */
5143         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5144                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5145                         intel_dp_mst_encoder_init(intel_dig_port,
5146                                                   intel_connector->base.base.id);
5147                 }
5148         }
5149
5150         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
5151                 drm_dp_aux_unregister(&intel_dp->aux);
5152                 if (is_edp(intel_dp)) {
5153                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5154                         /*
5155                          * vdd might still be enabled do to the delayed vdd off.
5156                          * Make sure vdd is actually turned off here.
5157                          */
5158                         pps_lock(intel_dp);
5159                         edp_panel_vdd_off_sync(intel_dp);
5160                         pps_unlock(intel_dp);
5161                 }
5162                 drm_connector_unregister(connector);
5163                 drm_connector_cleanup(connector);
5164                 return false;
5165         }
5166
5167         intel_dp_add_properties(intel_dp, connector);
5168
5169         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5170          * 0xd.  Failure to do so will result in spurious interrupts being
5171          * generated on the port when a cable is not attached.
5172          */
5173         if (IS_G4X(dev) && !IS_GM45(dev)) {
5174                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5175                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5176         }
5177
5178         return true;
5179 }
5180
5181 void
5182 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5183 {
5184         struct drm_i915_private *dev_priv = dev->dev_private;
5185         struct intel_digital_port *intel_dig_port;
5186         struct intel_encoder *intel_encoder;
5187         struct drm_encoder *encoder;
5188         struct intel_connector *intel_connector;
5189
5190         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5191         if (!intel_dig_port)
5192                 return;
5193
5194         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5195         if (!intel_connector) {
5196                 kfree(intel_dig_port);
5197                 return;
5198         }
5199
5200         intel_encoder = &intel_dig_port->base;
5201         encoder = &intel_encoder->base;
5202
5203         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5204                          DRM_MODE_ENCODER_TMDS);
5205
5206         intel_encoder->compute_config = intel_dp_compute_config;
5207         intel_encoder->disable = intel_disable_dp;
5208         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5209         intel_encoder->get_config = intel_dp_get_config;
5210         intel_encoder->suspend = intel_dp_encoder_suspend;
5211         if (IS_CHERRYVIEW(dev)) {
5212                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5213                 intel_encoder->pre_enable = chv_pre_enable_dp;
5214                 intel_encoder->enable = vlv_enable_dp;
5215                 intel_encoder->post_disable = chv_post_disable_dp;
5216         } else if (IS_VALLEYVIEW(dev)) {
5217                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5218                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5219                 intel_encoder->enable = vlv_enable_dp;
5220                 intel_encoder->post_disable = vlv_post_disable_dp;
5221         } else {
5222                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5223                 intel_encoder->enable = g4x_enable_dp;
5224                 if (INTEL_INFO(dev)->gen >= 5)
5225                         intel_encoder->post_disable = ilk_post_disable_dp;
5226         }
5227
5228         intel_dig_port->port = port;
5229         intel_dig_port->dp.output_reg = output_reg;
5230
5231         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5232         if (IS_CHERRYVIEW(dev)) {
5233                 if (port == PORT_D)
5234                         intel_encoder->crtc_mask = 1 << 2;
5235                 else
5236                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5237         } else {
5238                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5239         }
5240         intel_encoder->cloneable = 0;
5241         intel_encoder->hot_plug = intel_dp_hot_plug;
5242
5243         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5244         dev_priv->hpd_irq_port[port] = intel_dig_port;
5245
5246         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5247                 drm_encoder_cleanup(encoder);
5248                 kfree(intel_dig_port);
5249                 kfree(intel_connector);
5250         }
5251 }
5252
5253 void intel_dp_mst_suspend(struct drm_device *dev)
5254 {
5255         struct drm_i915_private *dev_priv = dev->dev_private;
5256         int i;
5257
5258         /* disable MST */
5259         for (i = 0; i < I915_MAX_PORTS; i++) {
5260                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5261                 if (!intel_dig_port)
5262                         continue;
5263
5264                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5265                         if (!intel_dig_port->dp.can_mst)
5266                                 continue;
5267                         if (intel_dig_port->dp.is_mst)
5268                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5269                 }
5270         }
5271 }
5272
5273 void intel_dp_mst_resume(struct drm_device *dev)
5274 {
5275         struct drm_i915_private *dev_priv = dev->dev_private;
5276         int i;
5277
5278         for (i = 0; i < I915_MAX_PORTS; i++) {
5279                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5280                 if (!intel_dig_port)
5281                         continue;
5282                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5283                         int ret;
5284
5285                         if (!intel_dig_port->dp.can_mst)
5286                                 continue;
5287
5288                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5289                         if (ret != 0) {
5290                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5291                         }
5292                 }
5293         }
5294 }