2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000 * (x))
69 #define MHz(x) KHz(1000 * (x))
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 /* Maximum cursor sizes */
82 #define GEN2_CURSOR_WIDTH 64
83 #define GEN2_CURSOR_HEIGHT 64
84 #define MAX_CURSOR_WIDTH 256
85 #define MAX_CURSOR_HEIGHT 256
87 #define INTEL_I2C_BUS_DVO 1
88 #define INTEL_I2C_BUS_SDVO 2
90 /* these are outputs from the chip - integrated only
91 external chips are via DVO or SDVO output */
92 #define INTEL_OUTPUT_UNUSED 0
93 #define INTEL_OUTPUT_ANALOG 1
94 #define INTEL_OUTPUT_DVO 2
95 #define INTEL_OUTPUT_SDVO 3
96 #define INTEL_OUTPUT_LVDS 4
97 #define INTEL_OUTPUT_TVOUT 5
98 #define INTEL_OUTPUT_HDMI 6
99 #define INTEL_OUTPUT_DISPLAYPORT 7
100 #define INTEL_OUTPUT_EDP 8
101 #define INTEL_OUTPUT_DSI 9
102 #define INTEL_OUTPUT_UNKNOWN 10
104 #define INTEL_DVO_CHIP_NONE 0
105 #define INTEL_DVO_CHIP_LVDS 1
106 #define INTEL_DVO_CHIP_TMDS 2
107 #define INTEL_DVO_CHIP_TVOUT 4
109 #define INTEL_DSI_COMMAND_MODE 0
110 #define INTEL_DSI_VIDEO_MODE 1
112 struct intel_framebuffer {
113 struct drm_framebuffer base;
114 struct drm_i915_gem_object *obj;
118 struct drm_fb_helper helper;
119 struct intel_framebuffer *fb;
120 struct list_head fbdev_list;
121 struct drm_display_mode *our_mode;
125 struct intel_encoder {
126 struct drm_encoder base;
128 * The new crtc this encoder will be driven from. Only differs from
129 * base->crtc while a modeset is in progress.
131 struct intel_crtc *new_crtc;
134 unsigned int cloneable;
135 bool connectors_active;
136 void (*hot_plug)(struct intel_encoder *);
137 bool (*compute_config)(struct intel_encoder *,
138 struct intel_crtc_config *);
139 void (*pre_pll_enable)(struct intel_encoder *);
140 void (*pre_enable)(struct intel_encoder *);
141 void (*enable)(struct intel_encoder *);
142 void (*mode_set)(struct intel_encoder *intel_encoder);
143 void (*disable)(struct intel_encoder *);
144 void (*post_disable)(struct intel_encoder *);
145 /* Read out the current hw state of this connector, returning true if
146 * the encoder is active. If the encoder is enabled it also set the pipe
147 * it is connected to in the pipe parameter. */
148 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
149 /* Reconstructs the equivalent mode flags for the current hardware
150 * state. This must be called _after_ display->get_pipe_config has
151 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
152 * be set correctly before calling this function. */
153 void (*get_config)(struct intel_encoder *,
154 struct intel_crtc_config *pipe_config);
156 enum hpd_pin hpd_pin;
160 struct drm_display_mode *fixed_mode;
161 struct drm_display_mode *downclock_mode;
170 bool combination_mode; /* gen 2/4 only */
172 struct backlight_device *device;
176 struct intel_connector {
177 struct drm_connector base;
179 * The fixed encoder this connector is connected to.
181 struct intel_encoder *encoder;
184 * The new encoder this connector will be driven. Only differs from
185 * encoder while a modeset is in progress.
187 struct intel_encoder *new_encoder;
189 /* Reads out the current hw, returning true if the connector is enabled
190 * and active (i.e. dpms ON state). */
191 bool (*get_hw_state)(struct intel_connector *);
194 * Removes all interfaces through which the connector is accessible
195 * - like sysfs, debugfs entries -, so that no new operations can be
196 * started on the connector. Also makes sure all currently pending
197 * operations finish before returing.
199 void (*unregister)(struct intel_connector *);
201 /* Panel info for eDP and LVDS */
202 struct intel_panel panel;
204 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
207 /* since POLL and HPD connectors may use the same HPD line keep the native
208 state of connector->polled in case hotplug storm detection changes it */
212 typedef struct dpll {
224 struct intel_plane_config {
230 struct intel_crtc_config {
232 * quirks - bitfield with hw state readout quirks
234 * For various reasons the hw state readout code might not be able to
235 * completely faithfully read out the current state. These cases are
236 * tracked with quirk flags so that fastboot and state checker can act
239 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
240 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
241 unsigned long quirks;
243 /* User requested mode, only valid as a starting point to
244 * compute adjusted_mode, except in the case of (S)DVO where
245 * it's also for the output timings of the (S)DVO chip.
246 * adjusted_mode will then correspond to the S(DVO) chip's
247 * preferred input timings. */
248 struct drm_display_mode requested_mode;
249 /* Actual pipe timings ie. what we program into the pipe timing
250 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
251 struct drm_display_mode adjusted_mode;
253 /* Pipe source size (ie. panel fitter input size)
254 * All planes will be positioned inside this space,
255 * and get clipped at the edges. */
256 int pipe_src_w, pipe_src_h;
258 /* Whether to set up the PCH/FDI. Note that we never allow sharing
259 * between pch encoders and cpu encoders. */
260 bool has_pch_encoder;
262 /* CPU Transcoder for the pipe. Currently this can only differ from the
263 * pipe on Haswell (where we have a special eDP transcoder). */
264 enum transcoder cpu_transcoder;
267 * Use reduced/limited/broadcast rbg range, compressing from the full
268 * range fed into the crtcs.
270 bool limited_color_range;
272 /* DP has a bunch of special case unfortunately, so mark the pipe
277 * Enable dithering, used when the selected pipe bpp doesn't match the
282 /* Controls for the clock computation, to override various stages. */
285 /* SDVO TV has a bunch of special case. To make multifunction encoders
286 * work correctly, we need to track this at runtime.*/
290 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
291 * required. This is set in the 2nd loop of calling encoder's
292 * ->compute_config if the first pick doesn't work out.
296 /* Settings for the intel dpll used on pretty much everything but
300 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
301 enum intel_dpll_id shared_dpll;
303 /* Actual register state of the dpll, for shared dpll cross-checking. */
304 struct intel_dpll_hw_state dpll_hw_state;
307 struct intel_link_m_n dp_m_n;
309 /* m2_n2 for eDP downclock */
310 struct intel_link_m_n dp_m2_n2;
313 * Frequence the dpll for the port should run at. Differs from the
314 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
315 * already multiplied by pixel_multiplier.
319 /* Used by SDVO (and if we ever fix it, HDMI). */
320 unsigned pixel_multiplier;
322 /* Panel fitter controls for gen2-gen4 + VLV */
326 u32 lvds_border_bits;
329 /* Panel fitter placement and size for Ironlake+ */
336 /* FDI configuration, only valid if has_pch_encoder is set. */
338 struct intel_link_m_n fdi_m_n;
345 struct intel_pipe_wm {
346 struct intel_wm_level wm[5];
350 bool sprites_enabled;
355 struct drm_crtc base;
358 u8 lut_r[256], lut_g[256], lut_b[256];
360 * Whether the crtc and the connected output pipeline is active. Implies
361 * that crtc->enabled is set, i.e. the current mode configuration has
362 * some outputs connected to this crtc.
365 unsigned long enabled_power_domains;
367 bool primary_enabled; /* is the primary plane (partially) visible? */
369 struct intel_overlay *overlay;
370 struct intel_unpin_work *unpin_work;
372 atomic_t unpin_work_count;
374 /* Display surface base address adjustement for pageflips. Note that on
375 * gen4+ this only adjusts up to a tile, offsets within a tile are
376 * handled in the hw itself (with the TILEOFF register). */
377 unsigned long dspaddr_offset;
379 struct drm_i915_gem_object *cursor_bo;
380 uint32_t cursor_addr;
381 int16_t cursor_x, cursor_y;
382 int16_t cursor_width, cursor_height;
385 struct intel_plane_config plane_config;
386 struct intel_crtc_config config;
387 struct intel_crtc_config *new_config;
390 uint32_t ddi_pll_sel;
392 /* reset counter value when the last flip was submitted */
393 unsigned int reset_counter;
395 /* Access to these should be protected by dev_priv->irq_lock. */
396 bool cpu_fifo_underrun_disabled;
397 bool pch_fifo_underrun_disabled;
399 /* per-pipe watermark state */
401 /* watermarks currently being used */
402 struct intel_pipe_wm active;
406 struct intel_plane_wm_parameters {
407 uint32_t horiz_pixels;
408 uint8_t bytes_per_pixel;
414 struct drm_plane base;
417 struct drm_i915_gem_object *obj;
420 u32 lut_r[1024], lut_g[1024], lut_b[1024];
422 unsigned int crtc_w, crtc_h;
423 uint32_t src_x, src_y;
424 uint32_t src_w, src_h;
426 /* Since we need to change the watermarks before/after
427 * enabling/disabling the planes, we need to store the parameters here
428 * as the other pieces of the struct may not reflect the values we want
429 * for the watermark calculations. Currently only Haswell uses this.
431 struct intel_plane_wm_parameters wm;
433 void (*update_plane)(struct drm_plane *plane,
434 struct drm_crtc *crtc,
435 struct drm_framebuffer *fb,
436 struct drm_i915_gem_object *obj,
437 int crtc_x, int crtc_y,
438 unsigned int crtc_w, unsigned int crtc_h,
439 uint32_t x, uint32_t y,
440 uint32_t src_w, uint32_t src_h);
441 void (*disable_plane)(struct drm_plane *plane,
442 struct drm_crtc *crtc);
443 int (*update_colorkey)(struct drm_plane *plane,
444 struct drm_intel_sprite_colorkey *key);
445 void (*get_colorkey)(struct drm_plane *plane,
446 struct drm_intel_sprite_colorkey *key);
449 struct intel_watermark_params {
450 unsigned long fifo_size;
451 unsigned long max_wm;
452 unsigned long default_wm;
453 unsigned long guard_size;
454 unsigned long cacheline_size;
457 struct cxsr_latency {
460 unsigned long fsb_freq;
461 unsigned long mem_freq;
462 unsigned long display_sr;
463 unsigned long display_hpll_disable;
464 unsigned long cursor_sr;
465 unsigned long cursor_hpll_disable;
468 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
469 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
470 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
471 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
472 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
477 uint32_t color_range;
478 bool color_range_auto;
481 enum hdmi_force_audio force_audio;
482 bool rgb_quant_range_selectable;
483 void (*write_infoframe)(struct drm_encoder *encoder,
484 enum hdmi_infoframe_type type,
485 const void *frame, ssize_t len);
486 void (*set_infoframes)(struct drm_encoder *encoder,
487 struct drm_display_mode *adjusted_mode);
490 #define DP_MAX_DOWNSTREAM_PORTS 0x10
493 * HIGH_RR is the highest eDP panel refresh rate read from EDID
494 * LOW_RR is the lowest eDP panel refresh rate found from EDID
495 * parsing for same resolution.
497 enum edp_drrs_refresh_rate_type {
500 DRRS_MAX_RR, /* RR count */
505 uint32_t aux_ch_ctl_reg;
508 enum hdmi_force_audio force_audio;
509 uint32_t color_range;
510 bool color_range_auto;
513 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
514 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
515 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
516 struct drm_dp_aux aux;
517 uint8_t train_set[4];
518 int panel_power_up_delay;
519 int panel_power_down_delay;
520 int panel_power_cycle_delay;
521 int backlight_on_delay;
522 int backlight_off_delay;
523 struct delayed_work panel_vdd_work;
525 unsigned long last_power_cycle;
526 unsigned long last_power_on;
527 unsigned long last_backlight_off;
530 struct intel_connector *attached_connector;
532 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
534 * This function returns the value we have to program the AUX_CTL
535 * register with to kick off an AUX transaction.
537 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
540 uint32_t aux_clock_divider);
542 enum drrs_support_type type;
543 enum edp_drrs_refresh_rate_type refresh_rate_type;
549 struct intel_digital_port {
550 struct intel_encoder base;
554 struct intel_hdmi hdmi;
558 vlv_dport_to_channel(struct intel_digital_port *dport)
560 switch (dport->port) {
570 static inline struct drm_crtc *
571 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
573 struct drm_i915_private *dev_priv = dev->dev_private;
574 return dev_priv->pipe_to_crtc_mapping[pipe];
577 static inline struct drm_crtc *
578 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
580 struct drm_i915_private *dev_priv = dev->dev_private;
581 return dev_priv->plane_to_crtc_mapping[plane];
584 struct intel_unpin_work {
585 struct work_struct work;
586 struct drm_crtc *crtc;
587 struct drm_i915_gem_object *old_fb_obj;
588 struct drm_i915_gem_object *pending_flip_obj;
589 struct drm_pending_vblank_event *event;
591 #define INTEL_FLIP_INACTIVE 0
592 #define INTEL_FLIP_PENDING 1
593 #define INTEL_FLIP_COMPLETE 2
594 bool enable_stall_check;
597 struct intel_set_config {
598 struct drm_encoder **save_connector_encoders;
599 struct drm_crtc **save_encoder_crtcs;
600 bool *save_crtc_enabled;
606 struct intel_load_detect_pipe {
607 struct drm_framebuffer *release_fb;
608 bool load_detect_temp;
612 static inline struct intel_encoder *
613 intel_attached_encoder(struct drm_connector *connector)
615 return to_intel_connector(connector)->encoder;
618 static inline struct intel_digital_port *
619 enc_to_dig_port(struct drm_encoder *encoder)
621 return container_of(encoder, struct intel_digital_port, base.base);
624 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
626 return &enc_to_dig_port(encoder)->dp;
629 static inline struct intel_digital_port *
630 dp_to_dig_port(struct intel_dp *intel_dp)
632 return container_of(intel_dp, struct intel_digital_port, dp);
635 static inline struct intel_digital_port *
636 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
638 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
643 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
644 enum pipe pipe, bool enable);
645 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
646 enum pipe pipe, bool enable);
647 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
648 enum transcoder pch_transcoder,
650 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
651 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
652 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
653 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
654 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
655 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
659 void intel_crt_init(struct drm_device *dev);
663 void intel_prepare_ddi(struct drm_device *dev);
664 void hsw_fdi_link_train(struct drm_crtc *crtc);
665 void intel_ddi_init(struct drm_device *dev, enum port port);
666 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
667 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
668 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
669 void intel_ddi_pll_init(struct drm_device *dev);
670 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
671 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
672 enum transcoder cpu_transcoder);
673 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
674 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
675 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
676 bool intel_ddi_pll_select(struct intel_crtc *crtc);
677 void intel_ddi_pll_enable(struct intel_crtc *crtc);
678 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
679 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
680 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
681 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
682 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
683 void intel_ddi_get_config(struct intel_encoder *encoder,
684 struct intel_crtc_config *pipe_config);
687 /* intel_display.c */
688 const char *intel_output_name(int output);
689 bool intel_has_pending_fb_unpin(struct drm_device *dev);
690 int intel_pch_rawclk(struct drm_device *dev);
691 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv);
692 void intel_mark_busy(struct drm_device *dev);
693 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
694 struct intel_ring_buffer *ring);
695 void intel_mark_idle(struct drm_device *dev);
696 void intel_crtc_restore_mode(struct drm_crtc *crtc);
697 void intel_crtc_update_dpms(struct drm_crtc *crtc);
698 void intel_encoder_destroy(struct drm_encoder *encoder);
699 void intel_connector_dpms(struct drm_connector *, int mode);
700 bool intel_connector_get_hw_state(struct intel_connector *connector);
701 void intel_modeset_check_state(struct drm_device *dev);
702 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
703 struct intel_digital_port *port);
704 void intel_connector_attach_encoder(struct intel_connector *connector,
705 struct intel_encoder *encoder);
706 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
707 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
708 struct drm_crtc *crtc);
709 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
710 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
712 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
714 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
715 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
716 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
717 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
718 struct intel_digital_port *dport);
719 bool intel_get_load_detect_pipe(struct drm_connector *connector,
720 struct drm_display_mode *mode,
721 struct intel_load_detect_pipe *old);
722 void intel_release_load_detect_pipe(struct drm_connector *connector,
723 struct intel_load_detect_pipe *old);
724 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
725 struct drm_i915_gem_object *obj,
726 struct intel_ring_buffer *pipelined);
727 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
728 struct drm_framebuffer *
729 __intel_framebuffer_create(struct drm_device *dev,
730 struct drm_mode_fb_cmd2 *mode_cmd,
731 struct drm_i915_gem_object *obj);
732 void intel_prepare_page_flip(struct drm_device *dev, int plane);
733 void intel_finish_page_flip(struct drm_device *dev, int pipe);
734 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
735 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
736 void assert_shared_dpll(struct drm_i915_private *dev_priv,
737 struct intel_shared_dpll *pll,
739 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
740 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
741 void assert_pll(struct drm_i915_private *dev_priv,
742 enum pipe pipe, bool state);
743 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
744 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
745 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
746 enum pipe pipe, bool state);
747 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
748 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
749 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
750 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
751 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
752 void intel_write_eld(struct drm_encoder *encoder,
753 struct drm_display_mode *mode);
754 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
755 unsigned int tiling_mode,
758 void intel_display_handle_reset(struct drm_device *dev);
759 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
760 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
761 void intel_dp_get_m_n(struct intel_crtc *crtc,
762 struct intel_crtc_config *pipe_config);
763 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
765 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
767 bool intel_crtc_active(struct drm_crtc *crtc);
768 void hsw_enable_ips(struct intel_crtc *crtc);
769 void hsw_disable_ips(struct intel_crtc *crtc);
770 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
771 enum intel_display_power_domain
772 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
773 int valleyview_get_vco(struct drm_i915_private *dev_priv);
774 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
775 struct intel_crtc_config *pipe_config);
776 int intel_format_to_fourcc(int format);
779 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
780 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
781 struct intel_connector *intel_connector);
782 void intel_dp_start_link_train(struct intel_dp *intel_dp);
783 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
784 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
785 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
786 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
787 void intel_dp_check_link_status(struct intel_dp *intel_dp);
788 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
789 bool intel_dp_compute_config(struct intel_encoder *encoder,
790 struct intel_crtc_config *pipe_config);
791 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
792 void intel_edp_backlight_on(struct intel_dp *intel_dp);
793 void intel_edp_backlight_off(struct intel_dp *intel_dp);
794 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
795 void intel_edp_panel_on(struct intel_dp *intel_dp);
796 void intel_edp_panel_off(struct intel_dp *intel_dp);
797 void intel_edp_psr_enable(struct intel_dp *intel_dp);
798 void intel_edp_psr_disable(struct intel_dp *intel_dp);
799 void intel_edp_psr_update(struct drm_device *dev);
800 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
803 bool intel_dsi_init(struct drm_device *dev);
807 void intel_dvo_init(struct drm_device *dev);
810 /* legacy fbdev emulation in intel_fbdev.c */
811 #ifdef CONFIG_DRM_I915_FBDEV
812 extern int intel_fbdev_init(struct drm_device *dev);
813 extern void intel_fbdev_initial_config(struct drm_device *dev);
814 extern void intel_fbdev_fini(struct drm_device *dev);
815 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
816 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
817 extern void intel_fbdev_restore_mode(struct drm_device *dev);
819 static inline int intel_fbdev_init(struct drm_device *dev)
824 static inline void intel_fbdev_initial_config(struct drm_device *dev)
828 static inline void intel_fbdev_fini(struct drm_device *dev)
832 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
836 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
842 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
843 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
844 struct intel_connector *intel_connector);
845 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
846 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
847 struct intel_crtc_config *pipe_config);
851 void intel_lvds_init(struct drm_device *dev);
852 bool intel_is_dual_link_lvds(struct drm_device *dev);
856 int intel_connector_update_modes(struct drm_connector *connector,
858 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
859 void intel_attach_force_audio_property(struct drm_connector *connector);
860 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
863 /* intel_overlay.c */
864 void intel_setup_overlay(struct drm_device *dev);
865 void intel_cleanup_overlay(struct drm_device *dev);
866 int intel_overlay_switch_off(struct intel_overlay *overlay);
867 int intel_overlay_put_image(struct drm_device *dev, void *data,
868 struct drm_file *file_priv);
869 int intel_overlay_attrs(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
874 int intel_panel_init(struct intel_panel *panel,
875 struct drm_display_mode *fixed_mode,
876 struct drm_display_mode *downclock_mode);
877 void intel_panel_fini(struct intel_panel *panel);
878 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
879 struct drm_display_mode *adjusted_mode);
880 void intel_pch_panel_fitting(struct intel_crtc *crtc,
881 struct intel_crtc_config *pipe_config,
883 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
884 struct intel_crtc_config *pipe_config,
886 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
888 int intel_panel_setup_backlight(struct drm_connector *connector);
889 void intel_panel_enable_backlight(struct intel_connector *connector);
890 void intel_panel_disable_backlight(struct intel_connector *connector);
891 void intel_panel_destroy_backlight(struct drm_connector *connector);
892 void intel_panel_init_backlight_funcs(struct drm_device *dev);
893 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
894 extern struct drm_display_mode *intel_find_panel_downclock(
895 struct drm_device *dev,
896 struct drm_display_mode *fixed_mode,
897 struct drm_connector *connector);
900 void intel_init_clock_gating(struct drm_device *dev);
901 void intel_suspend_hw(struct drm_device *dev);
902 void intel_update_watermarks(struct drm_crtc *crtc);
903 void intel_update_sprite_watermarks(struct drm_plane *plane,
904 struct drm_crtc *crtc,
905 uint32_t sprite_width, int pixel_size,
906 bool enabled, bool scaled);
907 void intel_init_pm(struct drm_device *dev);
908 void intel_pm_setup(struct drm_device *dev);
909 bool intel_fbc_enabled(struct drm_device *dev);
910 void intel_update_fbc(struct drm_device *dev);
911 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
912 void intel_gpu_ips_teardown(void);
913 int intel_power_domains_init(struct drm_i915_private *);
914 void intel_power_domains_remove(struct drm_i915_private *);
915 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
916 enum intel_display_power_domain domain);
917 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
918 enum intel_display_power_domain domain);
919 void intel_display_power_get(struct drm_i915_private *dev_priv,
920 enum intel_display_power_domain domain);
921 void intel_display_power_put(struct drm_i915_private *dev_priv,
922 enum intel_display_power_domain domain);
923 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
924 void intel_init_gt_powersave(struct drm_device *dev);
925 void intel_cleanup_gt_powersave(struct drm_device *dev);
926 void intel_enable_gt_powersave(struct drm_device *dev);
927 void intel_disable_gt_powersave(struct drm_device *dev);
928 void intel_reset_gt_powersave(struct drm_device *dev);
929 void ironlake_teardown_rc6(struct drm_device *dev);
930 void gen6_update_ring_freq(struct drm_device *dev);
931 void gen6_rps_idle(struct drm_i915_private *dev_priv);
932 void gen6_rps_boost(struct drm_i915_private *dev_priv);
933 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
934 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
935 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
936 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
937 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
938 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
939 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
940 void ilk_wm_get_hw_state(struct drm_device *dev);
944 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
948 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
949 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
951 void intel_plane_restore(struct drm_plane *plane);
952 void intel_plane_disable(struct drm_plane *plane);
953 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
954 struct drm_file *file_priv);
955 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
956 struct drm_file *file_priv);
960 void intel_tv_init(struct drm_device *dev);
962 #endif /* __INTEL_DRV_H__ */