drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72 #define wait_for_us(COND, US)           _wait_for((COND), (US), 1)
  73
  74 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  75 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  76 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
  77 #else
  78 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
  79 #endif
  80
  81 #define _wait_for_atomic(COND, US) ({ \
  82         unsigned long end__; \
  83         int ret__ = 0; \
  84         _WAIT_FOR_ATOMIC_CHECK; \
  85         BUILD_BUG_ON((US) > 50000); \
  86         end__ = (local_clock() >> 10) + (US) + 1; \
  87         while (!(COND)) { \
  88                 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
  89                         /* Unlike the regular wait_for(), this atomic variant \
  90                          * cannot be preempted (and we'll just ignore the issue\
  91                          * of irq interruptions) and so we know that no time \
  92                          * has passed since the last check of COND and can \
  93                          * immediately report the timeout. \
  94                          */ \
  95                         ret__ = -ETIMEDOUT; \
  96                         break; \
  97                 } \
  98                 cpu_relax(); \
  99         } \
 100         ret__; \
 101 })
 102
 103 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000)
 104 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US))
 105
 106 #define KHz(x) (1000 * (x))
 107 #define MHz(x) KHz(1000 * (x))
 108
 109 /*
 110  * Display related stuff
 111  */
 112
 113 /* store information about an Ixxx DVO */
 114 /* The i830->i865 use multiple DVOs with multiple i2cs */
 115 /* the i915, i945 have a single sDVO i2c bus - which is different */
 116 #define MAX_OUTPUTS 6
 117 /* maximum connectors per crtcs in the mode set */
 118
 119 /* Maximum cursor sizes */
 120 #define GEN2_CURSOR_WIDTH 64
 121 #define GEN2_CURSOR_HEIGHT 64
 122 #define MAX_CURSOR_WIDTH 256
 123 #define MAX_CURSOR_HEIGHT 256
 124
 125 #define INTEL_I2C_BUS_DVO 1
 126 #define INTEL_I2C_BUS_SDVO 2
 127
 128 /* these are outputs from the chip - integrated only
 129    external chips are via DVO or SDVO output */
 130 enum intel_output_type {
 131         INTEL_OUTPUT_UNUSED = 0,
 132         INTEL_OUTPUT_ANALOG = 1,
 133         INTEL_OUTPUT_DVO = 2,
 134         INTEL_OUTPUT_SDVO = 3,
 135         INTEL_OUTPUT_LVDS = 4,
 136         INTEL_OUTPUT_TVOUT = 5,
 137         INTEL_OUTPUT_HDMI = 6,
 138         INTEL_OUTPUT_DISPLAYPORT = 7,
 139         INTEL_OUTPUT_EDP = 8,
 140         INTEL_OUTPUT_DSI = 9,
 141         INTEL_OUTPUT_UNKNOWN = 10,
 142         INTEL_OUTPUT_DP_MST = 11,
 143 };
 144
 145 #define INTEL_DVO_CHIP_NONE 0
 146 #define INTEL_DVO_CHIP_LVDS 1
 147 #define INTEL_DVO_CHIP_TMDS 2
 148 #define INTEL_DVO_CHIP_TVOUT 4
 149
 150 #define INTEL_DSI_VIDEO_MODE    0
 151 #define INTEL_DSI_COMMAND_MODE  1
 152
 153 struct intel_framebuffer {
 154         struct drm_framebuffer base;
 155         struct drm_i915_gem_object *obj;
 156         struct intel_rotation_info rot_info;
 157 };
 158
 159 struct intel_fbdev {
 160         struct drm_fb_helper helper;
 161         struct intel_framebuffer *fb;
 162         int preferred_bpp;
 163 };
 164
 165 struct intel_encoder {
 166         struct drm_encoder base;
 167
 168         enum intel_output_type type;
 169         unsigned int cloneable;
 170         void (*hot_plug)(struct intel_encoder *);
 171         bool (*compute_config)(struct intel_encoder *,
 172                                struct intel_crtc_state *);
 173         void (*pre_pll_enable)(struct intel_encoder *);
 174         void (*pre_enable)(struct intel_encoder *);
 175         void (*enable)(struct intel_encoder *);
 176         void (*mode_set)(struct intel_encoder *intel_encoder);
 177         void (*disable)(struct intel_encoder *);
 178         void (*post_disable)(struct intel_encoder *);
 179         void (*post_pll_disable)(struct intel_encoder *);
 180         /* Read out the current hw state of this connector, returning true if
 181          * the encoder is active. If the encoder is enabled it also set the pipe
 182          * it is connected to in the pipe parameter. */
 183         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 184         /* Reconstructs the equivalent mode flags for the current hardware
 185          * state. This must be called _after_ display->get_pipe_config has
 186          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 187          * be set correctly before calling this function. */
 188         void (*get_config)(struct intel_encoder *,
 189                            struct intel_crtc_state *pipe_config);
 190         /*
 191          * Called during system suspend after all pending requests for the
 192          * encoder are flushed (for example for DP AUX transactions) and
 193          * device interrupts are disabled.
 194          */
 195         void (*suspend)(struct intel_encoder *);
 196         int crtc_mask;
 197         enum hpd_pin hpd_pin;
 198 };
 199
 200 struct intel_panel {
 201         struct drm_display_mode *fixed_mode;
 202         struct drm_display_mode *downclock_mode;
 203         int fitting_mode;
 204
 205         /* backlight */
 206         struct {
 207                 bool present;
 208                 u32 level;
 209                 u32 min;
 210                 u32 max;
 211                 bool enabled;
 212                 bool combination_mode;  /* gen 2/4 only */
 213                 bool active_low_pwm;
 214
 215                 /* PWM chip */
 216                 bool util_pin_active_low;       /* bxt+ */
 217                 u8 controller;          /* bxt+ only */
 218                 struct pwm_device *pwm;
 219
 220                 struct backlight_device *device;
 221
 222                 /* Connector and platform specific backlight functions */
 223                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 224                 uint32_t (*get)(struct intel_connector *connector);
 225                 void (*set)(struct intel_connector *connector, uint32_t level);
 226                 void (*disable)(struct intel_connector *connector);
 227                 void (*enable)(struct intel_connector *connector);
 228                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 229                                       uint32_t hz);
 230                 void (*power)(struct intel_connector *, bool enable);
 231         } backlight;
 232 };
 233
 234 struct intel_connector {
 235         struct drm_connector base;
 236         /*
 237          * The fixed encoder this connector is connected to.
 238          */
 239         struct intel_encoder *encoder;
 240
 241         /* Reads out the current hw, returning true if the connector is enabled
 242          * and active (i.e. dpms ON state). */
 243         bool (*get_hw_state)(struct intel_connector *);
 244
 245         /*
 246          * Removes all interfaces through which the connector is accessible
 247          * - like sysfs, debugfs entries -, so that no new operations can be
 248          * started on the connector. Also makes sure all currently pending
 249          * operations finish before returing.
 250          */
 251         void (*unregister)(struct intel_connector *);
 252
 253         /* Panel info for eDP and LVDS */
 254         struct intel_panel panel;
 255
 256         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 257         struct edid *edid;
 258         struct edid *detect_edid;
 259
 260         /* since POLL and HPD connectors may use the same HPD line keep the native
 261            state of connector->polled in case hotplug storm detection changes it */
 262         u8 polled;
 263
 264         void *port; /* store this opaque as its illegal to dereference it */
 265
 266         struct intel_dp *mst_port;
 267 };
 268
 269 struct dpll {
 270         /* given values */
 271         int n;
 272         int m1, m2;
 273         int p1, p2;
 274         /* derived values */
 275         int     dot;
 276         int     vco;
 277         int     m;
 278         int     p;
 279 };
 280
 281 struct intel_atomic_state {
 282         struct drm_atomic_state base;
 283
 284         unsigned int cdclk;
 285
 286         /*
 287          * Calculated device cdclk, can be different from cdclk
 288          * only when all crtc's are DPMS off.
 289          */
 290         unsigned int dev_cdclk;
 291
 292         bool dpll_set, modeset;
 293
 294         /*
 295          * Does this transaction change the pipes that are active?  This mask
 296          * tracks which CRTC's have changed their active state at the end of
 297          * the transaction (not counting the temporary disable during modesets).
 298          * This mask should only be non-zero when intel_state->modeset is true,
 299          * but the converse is not necessarily true; simply changing a mode may
 300          * not flip the final active status of any CRTC's
 301          */
 302         unsigned int active_pipe_changes;
 303
 304         unsigned int active_crtcs;
 305         unsigned int min_pixclk[I915_MAX_PIPES];
 306
 307         /* SKL/KBL Only */
 308         unsigned int cdclk_pll_vco;
 309
 310         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 311
 312         /*
 313          * Current watermarks can't be trusted during hardware readout, so
 314          * don't bother calculating intermediate watermarks.
 315          */
 316         bool skip_intermediate_wm;
 317
 318         /* Gen9+ only */
 319         struct skl_wm_values wm_results;
 320 };
 321
 322 struct intel_plane_state {
 323         struct drm_plane_state base;
 324         struct drm_rect src;
 325         struct drm_rect dst;
 326         struct drm_rect clip;
 327         bool visible;
 328
 329         /*
 330          * scaler_id
 331          *    = -1 : not using a scaler
 332          *    >=  0 : using a scalers
 333          *
 334          * plane requiring a scaler:
 335          *   - During check_plane, its bit is set in
 336          *     crtc_state->scaler_state.scaler_users by calling helper function
 337          *     update_scaler_plane.
 338          *   - scaler_id indicates the scaler it got assigned.
 339          *
 340          * plane doesn't require a scaler:
 341          *   - this can happen when scaling is no more required or plane simply
 342          *     got disabled.
 343          *   - During check_plane, corresponding bit is reset in
 344          *     crtc_state->scaler_state.scaler_users by calling helper function
 345          *     update_scaler_plane.
 346          */
 347         int scaler_id;
 348
 349         struct drm_intel_sprite_colorkey ckey;
 350
 351         /* async flip related structures */
 352         struct drm_i915_gem_request *wait_req;
 353 };
 354
 355 struct intel_initial_plane_config {
 356         struct intel_framebuffer *fb;
 357         unsigned int tiling;
 358         int size;
 359         u32 base;
 360 };
 361
 362 #define SKL_MIN_SRC_W 8
 363 #define SKL_MAX_SRC_W 4096
 364 #define SKL_MIN_SRC_H 8
 365 #define SKL_MAX_SRC_H 4096
 366 #define SKL_MIN_DST_W 8
 367 #define SKL_MAX_DST_W 4096
 368 #define SKL_MIN_DST_H 8
 369 #define SKL_MAX_DST_H 4096
 370
 371 struct intel_scaler {
 372         int in_use;
 373         uint32_t mode;
 374 };
 375
 376 struct intel_crtc_scaler_state {
 377 #define SKL_NUM_SCALERS 2
 378         struct intel_scaler scalers[SKL_NUM_SCALERS];
 379
 380         /*
 381          * scaler_users: keeps track of users requesting scalers on this crtc.
 382          *
 383          *     If a bit is set, a user is using a scaler.
 384          *     Here user can be a plane or crtc as defined below:
 385          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 386          *       bit 31    - crtc
 387          *
 388          * Instead of creating a new index to cover planes and crtc, using
 389          * existing drm_plane_index for planes which is well less than 31
 390          * planes and bit 31 for crtc. This should be fine to cover all
 391          * our platforms.
 392          *
 393          * intel_atomic_setup_scalers will setup available scalers to users
 394          * requesting scalers. It will gracefully fail if request exceeds
 395          * avilability.
 396          */
 397 #define SKL_CRTC_INDEX 31
 398         unsigned scaler_users;
 399
 400         /* scaler used by crtc for panel fitting purpose */
 401         int scaler_id;
 402 };
 403
 404 /* drm_mode->private_flags */
 405 #define I915_MODE_FLAG_INHERITED 1
 406
 407 struct intel_pipe_wm {
 408         struct intel_wm_level wm[5];
 409         struct intel_wm_level raw_wm[5];
 410         uint32_t linetime;
 411         bool fbc_wm_enabled;
 412         bool pipe_enabled;
 413         bool sprites_enabled;
 414         bool sprites_scaled;
 415 };
 416
 417 struct skl_pipe_wm {
 418         struct skl_wm_level wm[8];
 419         struct skl_wm_level trans_wm;
 420         uint32_t linetime;
 421 };
 422
 423 struct intel_crtc_wm_state {
 424         union {
 425                 struct {
 426                         /*
 427                          * Intermediate watermarks; these can be
 428                          * programmed immediately since they satisfy
 429                          * both the current configuration we're
 430                          * switching away from and the new
 431                          * configuration we're switching to.
 432                          */
 433                         struct intel_pipe_wm intermediate;
 434
 435                         /*
 436                          * Optimal watermarks, programmed post-vblank
 437                          * when this state is committed.
 438                          */
 439                         struct intel_pipe_wm optimal;
 440                 } ilk;
 441
 442                 struct {
 443                         /* gen9+ only needs 1-step wm programming */
 444                         struct skl_pipe_wm optimal;
 445
 446                         /* cached plane data rate */
 447                         unsigned plane_data_rate[I915_MAX_PLANES];
 448                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 449
 450                         /* minimum block allocation */
 451                         uint16_t minimum_blocks[I915_MAX_PLANES];
 452                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 453                 } skl;
 454         };
 455
 456         /*
 457          * Platforms with two-step watermark programming will need to
 458          * update watermark programming post-vblank to switch from the
 459          * safe intermediate watermarks to the optimal final
 460          * watermarks.
 461          */
 462         bool need_postvbl_update;
 463 };
 464
 465 struct intel_crtc_state {
 466         struct drm_crtc_state base;
 467
 468         /**
 469          * quirks - bitfield with hw state readout quirks
 470          *
 471          * For various reasons the hw state readout code might not be able to
 472          * completely faithfully read out the current state. These cases are
 473          * tracked with quirk flags so that fastboot and state checker can act
 474          * accordingly.
 475          */
 476 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 477         unsigned long quirks;
 478
 479         unsigned fb_bits; /* framebuffers to flip */
 480         bool update_pipe; /* can a fast modeset be performed? */
 481         bool disable_cxsr;
 482         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 483         bool fb_changed; /* fb on any of the planes is changed */
 484
 485         /* Pipe source size (ie. panel fitter input size)
 486          * All planes will be positioned inside this space,
 487          * and get clipped at the edges. */
 488         int pipe_src_w, pipe_src_h;
 489
 490         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 491          * between pch encoders and cpu encoders. */
 492         bool has_pch_encoder;
 493
 494         /* Are we sending infoframes on the attached port */
 495         bool has_infoframe;
 496
 497         /* CPU Transcoder for the pipe. Currently this can only differ from the
 498          * pipe on Haswell and later (where we have a special eDP transcoder)
 499          * and Broxton (where we have special DSI transcoders). */
 500         enum transcoder cpu_transcoder;
 501
 502         /*
 503          * Use reduced/limited/broadcast rbg range, compressing from the full
 504          * range fed into the crtcs.
 505          */
 506         bool limited_color_range;
 507
 508         /* DP has a bunch of special case unfortunately, so mark the pipe
 509          * accordingly. */
 510         bool has_dp_encoder;
 511
 512         /* DSI has special cases */
 513         bool has_dsi_encoder;
 514
 515         /* Whether we should send NULL infoframes. Required for audio. */
 516         bool has_hdmi_sink;
 517
 518         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 519          * has_dp_encoder is set. */
 520         bool has_audio;
 521
 522         /*
 523          * Enable dithering, used when the selected pipe bpp doesn't match the
 524          * plane bpp.
 525          */
 526         bool dither;
 527
 528         /* Controls for the clock computation, to override various stages. */
 529         bool clock_set;
 530
 531         /* SDVO TV has a bunch of special case. To make multifunction encoders
 532          * work correctly, we need to track this at runtime.*/
 533         bool sdvo_tv_clock;
 534
 535         /*
 536          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 537          * required. This is set in the 2nd loop of calling encoder's
 538          * ->compute_config if the first pick doesn't work out.
 539          */
 540         bool bw_constrained;
 541
 542         /* Settings for the intel dpll used on pretty much everything but
 543          * haswell. */
 544         struct dpll dpll;
 545
 546         /* Selected dpll when shared or NULL. */
 547         struct intel_shared_dpll *shared_dpll;
 548
 549         /*
 550          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 551          * - enum skl_dpll on SKL
 552          */
 553         uint32_t ddi_pll_sel;
 554
 555         /* Actual register state of the dpll, for shared dpll cross-checking. */
 556         struct intel_dpll_hw_state dpll_hw_state;
 557
 558         /* DSI PLL registers */
 559         struct {
 560                 u32 ctrl, div;
 561         } dsi_pll;
 562
 563         int pipe_bpp;
 564         struct intel_link_m_n dp_m_n;
 565
 566         /* m2_n2 for eDP downclock */
 567         struct intel_link_m_n dp_m2_n2;
 568         bool has_drrs;
 569
 570         /*
 571          * Frequence the dpll for the port should run at. Differs from the
 572          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 573          * already multiplied by pixel_multiplier.
 574          */
 575         int port_clock;
 576
 577         /* Used by SDVO (and if we ever fix it, HDMI). */
 578         unsigned pixel_multiplier;
 579
 580         uint8_t lane_count;
 581
 582         /*
 583          * Used by platforms having DP/HDMI PHY with programmable lane
 584          * latency optimization.
 585          */
 586         uint8_t lane_lat_optim_mask;
 587
 588         /* Panel fitter controls for gen2-gen4 + VLV */
 589         struct {
 590                 u32 control;
 591                 u32 pgm_ratios;
 592                 u32 lvds_border_bits;
 593         } gmch_pfit;
 594
 595         /* Panel fitter placement and size for Ironlake+ */
 596         struct {
 597                 u32 pos;
 598                 u32 size;
 599                 bool enabled;
 600                 bool force_thru;
 601         } pch_pfit;
 602
 603         /* FDI configuration, only valid if has_pch_encoder is set. */
 604         int fdi_lanes;
 605         struct intel_link_m_n fdi_m_n;
 606
 607         bool ips_enabled;
 608
 609         bool enable_fbc;
 610
 611         bool double_wide;
 612
 613         bool dp_encoder_is_mst;
 614         int pbn;
 615
 616         struct intel_crtc_scaler_state scaler_state;
 617
 618         /* w/a for waiting 2 vblanks during crtc enable */
 619         enum pipe hsw_workaround_pipe;
 620
 621         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 622         bool disable_lp_wm;
 623
 624         struct intel_crtc_wm_state wm;
 625
 626         /* Gamma mode programmed on the pipe */
 627         uint32_t gamma_mode;
 628 };
 629
 630 struct vlv_wm_state {
 631         struct vlv_pipe_wm wm[3];
 632         struct vlv_sr_wm sr[3];
 633         uint8_t num_active_planes;
 634         uint8_t num_levels;
 635         uint8_t level;
 636         bool cxsr;
 637 };
 638
 639 struct intel_crtc {
 640         struct drm_crtc base;
 641         enum pipe pipe;
 642         enum plane plane;
 643         u8 lut_r[256], lut_g[256], lut_b[256];
 644         /*
 645          * Whether the crtc and the connected output pipeline is active. Implies
 646          * that crtc->enabled is set, i.e. the current mode configuration has
 647          * some outputs connected to this crtc.
 648          */
 649         bool active;
 650         unsigned long enabled_power_domains;
 651         bool lowfreq_avail;
 652         struct intel_overlay *overlay;
 653         struct intel_flip_work *flip_work;
 654
 655         atomic_t unpin_work_count;
 656
 657         /* Display surface base address adjustement for pageflips. Note that on
 658          * gen4+ this only adjusts up to a tile, offsets within a tile are
 659          * handled in the hw itself (with the TILEOFF register). */
 660         u32 dspaddr_offset;
 661         int adjusted_x;
 662         int adjusted_y;
 663
 664         uint32_t cursor_addr;
 665         uint32_t cursor_cntl;
 666         uint32_t cursor_size;
 667         uint32_t cursor_base;
 668
 669         struct intel_crtc_state *config;
 670
 671         /* reset counter value when the last flip was submitted */
 672         unsigned int reset_counter;
 673
 674         /* Access to these should be protected by dev_priv->irq_lock. */
 675         bool cpu_fifo_underrun_disabled;
 676         bool pch_fifo_underrun_disabled;
 677
 678         /* per-pipe watermark state */
 679         struct {
 680                 /* watermarks currently being used  */
 681                 union {
 682                         struct intel_pipe_wm ilk;
 683                         struct skl_pipe_wm skl;
 684                 } active;
 685
 686                 /* allow CxSR on this pipe */
 687                 bool cxsr_allowed;
 688         } wm;
 689
 690         int scanline_offset;
 691
 692         struct {
 693                 unsigned start_vbl_count;
 694                 ktime_t start_vbl_time;
 695                 int min_vbl, max_vbl;
 696                 int scanline_start;
 697         } debug;
 698
 699         /* scalers available on this crtc */
 700         int num_scalers;
 701
 702         struct vlv_wm_state wm_state;
 703 };
 704
 705 struct intel_plane_wm_parameters {
 706         uint32_t horiz_pixels;
 707         uint32_t vert_pixels;
 708         /*
 709          *   For packed pixel formats:
 710          *     bytes_per_pixel - holds bytes per pixel
 711          *   For planar pixel formats:
 712          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 713          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 714          */
 715         uint8_t bytes_per_pixel;
 716         uint8_t y_bytes_per_pixel;
 717         bool enabled;
 718         bool scaled;
 719         u64 tiling;
 720         unsigned int rotation;
 721         uint16_t fifo_size;
 722 };
 723
 724 struct intel_plane {
 725         struct drm_plane base;
 726         int plane;
 727         enum pipe pipe;
 728         bool can_scale;
 729         int max_downscale;
 730         uint32_t frontbuffer_bit;
 731
 732         /* Since we need to change the watermarks before/after
 733          * enabling/disabling the planes, we need to store the parameters here
 734          * as the other pieces of the struct may not reflect the values we want
 735          * for the watermark calculations. Currently only Haswell uses this.
 736          */
 737         struct intel_plane_wm_parameters wm;
 738
 739         /*
 740          * NOTE: Do not place new plane state fields here (e.g., when adding
 741          * new plane properties).  New runtime state should now be placed in
 742          * the intel_plane_state structure and accessed via plane_state.
 743          */
 744
 745         void (*update_plane)(struct drm_plane *plane,
 746                              const struct intel_crtc_state *crtc_state,
 747                              const struct intel_plane_state *plane_state);
 748         void (*disable_plane)(struct drm_plane *plane,
 749                               struct drm_crtc *crtc);
 750         int (*check_plane)(struct drm_plane *plane,
 751                            struct intel_crtc_state *crtc_state,
 752                            struct intel_plane_state *state);
 753 };
 754
 755 struct intel_watermark_params {
 756         unsigned long fifo_size;
 757         unsigned long max_wm;
 758         unsigned long default_wm;
 759         unsigned long guard_size;
 760         unsigned long cacheline_size;
 761 };
 762
 763 struct cxsr_latency {
 764         int is_desktop;
 765         int is_ddr3;
 766         unsigned long fsb_freq;
 767         unsigned long mem_freq;
 768         unsigned long display_sr;
 769         unsigned long display_hpll_disable;
 770         unsigned long cursor_sr;
 771         unsigned long cursor_hpll_disable;
 772 };
 773
 774 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 775 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 776 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 777 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 778 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 779 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 780 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 781 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 782 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 783
 784 struct intel_hdmi {
 785         i915_reg_t hdmi_reg;
 786         int ddc_bus;
 787         struct {
 788                 enum drm_dp_dual_mode_type type;
 789                 int max_tmds_clock;
 790         } dp_dual_mode;
 791         bool limited_color_range;
 792         bool color_range_auto;
 793         bool has_hdmi_sink;
 794         bool has_audio;
 795         enum hdmi_force_audio force_audio;
 796         bool rgb_quant_range_selectable;
 797         enum hdmi_picture_aspect aspect_ratio;
 798         struct intel_connector *attached_connector;
 799         void (*write_infoframe)(struct drm_encoder *encoder,
 800                                 enum hdmi_infoframe_type type,
 801                                 const void *frame, ssize_t len);
 802         void (*set_infoframes)(struct drm_encoder *encoder,
 803                                bool enable,
 804                                const struct drm_display_mode *adjusted_mode);
 805         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 806                                   const struct intel_crtc_state *pipe_config);
 807 };
 808
 809 struct intel_dp_mst_encoder;
 810 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 811
 812 /*
 813  * enum link_m_n_set:
 814  *      When platform provides two set of M_N registers for dp, we can
 815  *      program them and switch between them incase of DRRS.
 816  *      But When only one such register is provided, we have to program the
 817  *      required divider value on that registers itself based on the DRRS state.
 818  *
 819  * M1_N1        : Program dp_m_n on M1_N1 registers
 820  *                        dp_m2_n2 on M2_N2 registers (If supported)
 821  *
 822  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 823  *                        M2_N2 registers are not supported
 824  */
 825
 826 enum link_m_n_set {
 827         /* Sets the m1_n1 and m2_n2 */
 828         M1_N1 = 0,
 829         M2_N2
 830 };
 831
 832 struct intel_dp {
 833         i915_reg_t output_reg;
 834         i915_reg_t aux_ch_ctl_reg;
 835         i915_reg_t aux_ch_data_reg[5];
 836         uint32_t DP;
 837         int link_rate;
 838         uint8_t lane_count;
 839         uint8_t sink_count;
 840         bool has_audio;
 841         bool detect_done;
 842         enum hdmi_force_audio force_audio;
 843         bool limited_color_range;
 844         bool color_range_auto;
 845         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 846         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 847         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 848         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 849         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 850         uint8_t num_sink_rates;
 851         int sink_rates[DP_MAX_SUPPORTED_RATES];
 852         struct drm_dp_aux aux;
 853         uint8_t train_set[4];
 854         int panel_power_up_delay;
 855         int panel_power_down_delay;
 856         int panel_power_cycle_delay;
 857         int backlight_on_delay;
 858         int backlight_off_delay;
 859         struct delayed_work panel_vdd_work;
 860         bool want_panel_vdd;
 861         unsigned long last_power_on;
 862         unsigned long last_backlight_off;
 863         ktime_t panel_power_off_time;
 864
 865         struct notifier_block edp_notifier;
 866
 867         /*
 868          * Pipe whose power sequencer is currently locked into
 869          * this port. Only relevant on VLV/CHV.
 870          */
 871         enum pipe pps_pipe;
 872         struct edp_power_seq pps_delays;
 873
 874         bool can_mst; /* this port supports mst */
 875         bool is_mst;
 876         int active_mst_links;
 877         /* connector directly attached - won't be use for modeset in mst world */
 878         struct intel_connector *attached_connector;
 879
 880         /* mst connector list */
 881         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 882         struct drm_dp_mst_topology_mgr mst_mgr;
 883
 884         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 885         /*
 886          * This function returns the value we have to program the AUX_CTL
 887          * register with to kick off an AUX transaction.
 888          */
 889         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 890                                      bool has_aux_irq,
 891                                      int send_bytes,
 892                                      uint32_t aux_clock_divider);
 893
 894         /* This is called before a link training is starterd */
 895         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 896
 897         bool train_set_valid;
 898
 899         /* Displayport compliance testing */
 900         unsigned long compliance_test_type;
 901         unsigned long compliance_test_data;
 902         bool compliance_test_active;
 903 };
 904
 905 struct intel_digital_port {
 906         struct intel_encoder base;
 907         enum port port;
 908         u32 saved_port_bits;
 909         struct intel_dp dp;
 910         struct intel_hdmi hdmi;
 911         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 912         bool release_cl2_override;
 913         uint8_t max_lanes;
 914         /* for communication with audio component; protected by av_mutex */
 915         const struct drm_connector *audio_connector;
 916 };
 917
 918 struct intel_dp_mst_encoder {
 919         struct intel_encoder base;
 920         enum pipe pipe;
 921         struct intel_digital_port *primary;
 922         struct intel_connector *connector;
 923 };
 924
 925 static inline enum dpio_channel
 926 vlv_dport_to_channel(struct intel_digital_port *dport)
 927 {
 928         switch (dport->port) {
 929         case PORT_B:
 930         case PORT_D:
 931                 return DPIO_CH0;
 932         case PORT_C:
 933                 return DPIO_CH1;
 934         default:
 935                 BUG();
 936         }
 937 }
 938
 939 static inline enum dpio_phy
 940 vlv_dport_to_phy(struct intel_digital_port *dport)
 941 {
 942         switch (dport->port) {
 943         case PORT_B:
 944         case PORT_C:
 945                 return DPIO_PHY0;
 946         case PORT_D:
 947                 return DPIO_PHY1;
 948         default:
 949                 BUG();
 950         }
 951 }
 952
 953 static inline enum dpio_channel
 954 vlv_pipe_to_channel(enum pipe pipe)
 955 {
 956         switch (pipe) {
 957         case PIPE_A:
 958         case PIPE_C:
 959                 return DPIO_CH0;
 960         case PIPE_B:
 961                 return DPIO_CH1;
 962         default:
 963                 BUG();
 964         }
 965 }
 966
 967 static inline struct drm_crtc *
 968 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         return dev_priv->pipe_to_crtc_mapping[pipe];
 972 }
 973
 974 static inline struct drm_crtc *
 975 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 976 {
 977         struct drm_i915_private *dev_priv = dev->dev_private;
 978         return dev_priv->plane_to_crtc_mapping[plane];
 979 }
 980
 981 struct intel_flip_work {
 982         struct work_struct unpin_work;
 983         struct work_struct mmio_work;
 984
 985         struct drm_crtc *crtc;
 986         struct drm_framebuffer *old_fb;
 987         struct drm_i915_gem_object *pending_flip_obj;
 988         struct drm_pending_vblank_event *event;
 989         atomic_t pending;
 990         u32 flip_count;
 991         u32 gtt_offset;
 992         struct drm_i915_gem_request *flip_queued_req;
 993         u32 flip_queued_vblank;
 994         u32 flip_ready_vblank;
 995         unsigned int rotation;
 996 };
 997
 998 struct intel_load_detect_pipe {
 999         struct drm_atomic_state *restore_state;
1000 };
1001
1002 static inline struct intel_encoder *
1003 intel_attached_encoder(struct drm_connector *connector)
1004 {
1005         return to_intel_connector(connector)->encoder;
1006 }
1007
1008 static inline struct intel_digital_port *
1009 enc_to_dig_port(struct drm_encoder *encoder)
1010 {
1011         return container_of(encoder, struct intel_digital_port, base.base);
1012 }
1013
1014 static inline struct intel_dp_mst_encoder *
1015 enc_to_mst(struct drm_encoder *encoder)
1016 {
1017         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1018 }
1019
1020 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1021 {
1022         return &enc_to_dig_port(encoder)->dp;
1023 }
1024
1025 static inline struct intel_digital_port *
1026 dp_to_dig_port(struct intel_dp *intel_dp)
1027 {
1028         return container_of(intel_dp, struct intel_digital_port, dp);
1029 }
1030
1031 static inline struct intel_digital_port *
1032 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1033 {
1034         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1035 }
1036
1037 /*
1038  * Returns the number of planes for this pipe, ie the number of sprites + 1
1039  * (primary plane). This doesn't count the cursor plane then.
1040  */
1041 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1042 {
1043         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1044 }
1045
1046 /* intel_fifo_underrun.c */
1047 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1048                                            enum pipe pipe, bool enable);
1049 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1050                                            enum transcoder pch_transcoder,
1051                                            bool enable);
1052 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1053                                          enum pipe pipe);
1054 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1055                                          enum transcoder pch_transcoder);
1056 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1057 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1058
1059 /* i915_irq.c */
1060 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1061 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1062 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1063 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1064 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1065 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1066 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1067 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1068 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1069 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1070 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1071 {
1072         /*
1073          * We only use drm_irq_uninstall() at unload and VT switch, so
1074          * this is the only thing we need to check.
1075          */
1076         return dev_priv->pm.irqs_enabled;
1077 }
1078
1079 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1080 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1081                                      unsigned int pipe_mask);
1082 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1083                                      unsigned int pipe_mask);
1084
1085 /* intel_crt.c */
1086 void intel_crt_init(struct drm_device *dev);
1087
1088
1089 /* intel_ddi.c */
1090 void intel_ddi_clk_select(struct intel_encoder *encoder,
1091                           const struct intel_crtc_state *pipe_config);
1092 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1093 void hsw_fdi_link_train(struct drm_crtc *crtc);
1094 void intel_ddi_init(struct drm_device *dev, enum port port);
1095 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1096 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1097 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1098 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1099                                        enum transcoder cpu_transcoder);
1100 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1101 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1102 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1103                           struct intel_crtc_state *crtc_state);
1104 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1105 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1106 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1107 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1108 void intel_ddi_get_config(struct intel_encoder *encoder,
1109                           struct intel_crtc_state *pipe_config);
1110 struct intel_encoder *
1111 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1112
1113 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1114 void intel_ddi_clock_get(struct intel_encoder *encoder,
1115                          struct intel_crtc_state *pipe_config);
1116 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1117 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1118
1119 /* intel_frontbuffer.c */
1120 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1121                              enum fb_op_origin origin);
1122 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1123                                     unsigned frontbuffer_bits);
1124 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1125                                      unsigned frontbuffer_bits);
1126 void intel_frontbuffer_flip(struct drm_device *dev,
1127                             unsigned frontbuffer_bits);
1128 unsigned int intel_fb_align_height(struct drm_device *dev,
1129                                    unsigned int height,
1130                                    uint32_t pixel_format,
1131                                    uint64_t fb_format_modifier);
1132 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1133                         enum fb_op_origin origin);
1134 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1135                               uint64_t fb_modifier, uint32_t pixel_format);
1136
1137 /* intel_audio.c */
1138 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1139 void intel_audio_codec_enable(struct intel_encoder *encoder);
1140 void intel_audio_codec_disable(struct intel_encoder *encoder);
1141 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1142 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1143
1144 /* intel_display.c */
1145 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1146 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1147 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1148                       const char *name, u32 reg, int ref_freq);
1149 extern const struct drm_plane_funcs intel_plane_funcs;
1150 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1151 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1152 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1153 void intel_mark_busy(struct drm_i915_private *dev_priv);
1154 void intel_mark_idle(struct drm_i915_private *dev_priv);
1155 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1156 int intel_display_suspend(struct drm_device *dev);
1157 void intel_encoder_destroy(struct drm_encoder *encoder);
1158 int intel_connector_init(struct intel_connector *);
1159 struct intel_connector *intel_connector_alloc(void);
1160 bool intel_connector_get_hw_state(struct intel_connector *connector);
1161 void intel_connector_attach_encoder(struct intel_connector *connector,
1162                                     struct intel_encoder *encoder);
1163 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1164 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1165                                              struct drm_crtc *crtc);
1166 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1167 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1168                                 struct drm_file *file_priv);
1169 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1170                                              enum pipe pipe);
1171 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1172 static inline void
1173 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1174 {
1175         drm_wait_one_vblank(dev, pipe);
1176 }
1177 static inline void
1178 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1179 {
1180         const struct intel_crtc *crtc =
1181                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1182
1183         if (crtc->active)
1184                 intel_wait_for_vblank(dev, pipe);
1185 }
1186
1187 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1188
1189 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1190 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1191                          struct intel_digital_port *dport,
1192                          unsigned int expected_mask);
1193 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1194                                 struct drm_display_mode *mode,
1195                                 struct intel_load_detect_pipe *old,
1196                                 struct drm_modeset_acquire_ctx *ctx);
1197 void intel_release_load_detect_pipe(struct drm_connector *connector,
1198                                     struct intel_load_detect_pipe *old,
1199                                     struct drm_modeset_acquire_ctx *ctx);
1200 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1201                                unsigned int rotation);
1202 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1203 struct drm_framebuffer *
1204 __intel_framebuffer_create(struct drm_device *dev,
1205                            struct drm_mode_fb_cmd2 *mode_cmd,
1206                            struct drm_i915_gem_object *obj);
1207 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1208 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1209 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1210 int intel_prepare_plane_fb(struct drm_plane *plane,
1211                            const struct drm_plane_state *new_state);
1212 void intel_cleanup_plane_fb(struct drm_plane *plane,
1213                             const struct drm_plane_state *old_state);
1214 int intel_plane_atomic_get_property(struct drm_plane *plane,
1215                                     const struct drm_plane_state *state,
1216                                     struct drm_property *property,
1217                                     uint64_t *val);
1218 int intel_plane_atomic_set_property(struct drm_plane *plane,
1219                                     struct drm_plane_state *state,
1220                                     struct drm_property *property,
1221                                     uint64_t val);
1222 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1223                                     struct drm_plane_state *plane_state);
1224
1225 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1226                                uint64_t fb_modifier, unsigned int cpp);
1227
1228 static inline bool
1229 intel_rotation_90_or_270(unsigned int rotation)
1230 {
1231         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1232 }
1233
1234 void intel_create_rotation_property(struct drm_device *dev,
1235                                         struct intel_plane *plane);
1236
1237 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1238                                     enum pipe pipe);
1239
1240 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1241                      const struct dpll *dpll);
1242 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1243 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1244
1245 /* modesetting asserts */
1246 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247                            enum pipe pipe);
1248 void assert_pll(struct drm_i915_private *dev_priv,
1249                 enum pipe pipe, bool state);
1250 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1251 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1252 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1253 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1254 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1255 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1256                        enum pipe pipe, bool state);
1257 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1258 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1259 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1260 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1261 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1262 u32 intel_compute_tile_offset(int *x, int *y,
1263                               const struct drm_framebuffer *fb, int plane,
1264                               unsigned int pitch,
1265                               unsigned int rotation);
1266 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1267 void intel_finish_reset(struct drm_i915_private *dev_priv);
1268 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1269 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1270 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
1271 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
1272 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1273 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1274 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1275                             enum dpio_phy phy);
1276 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1277                               enum dpio_phy phy);
1278 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1279 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1280 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1281 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1282 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1283 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1284 unsigned int skl_cdclk_get_vco(unsigned int freq);
1285 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1286 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1287 void intel_dp_get_m_n(struct intel_crtc *crtc,
1288                       struct intel_crtc_state *pipe_config);
1289 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1290 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1291 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1292                         struct dpll *best_clock);
1293 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1294
1295 bool intel_crtc_active(struct drm_crtc *crtc);
1296 void hsw_enable_ips(struct intel_crtc *crtc);
1297 void hsw_disable_ips(struct intel_crtc *crtc);
1298 enum intel_display_power_domain
1299 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1300 enum intel_display_power_domain
1301 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1302 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1303                                  struct intel_crtc_state *pipe_config);
1304
1305 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1306 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1307
1308 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1309                            struct drm_i915_gem_object *obj,
1310                            unsigned int plane);
1311
1312 u32 skl_plane_ctl_format(uint32_t pixel_format);
1313 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1314 u32 skl_plane_ctl_rotation(unsigned int rotation);
1315
1316 /* intel_csr.c */
1317 void intel_csr_ucode_init(struct drm_i915_private *);
1318 void intel_csr_load_program(struct drm_i915_private *);
1319 void intel_csr_ucode_fini(struct drm_i915_private *);
1320 void intel_csr_ucode_suspend(struct drm_i915_private *);
1321 void intel_csr_ucode_resume(struct drm_i915_private *);
1322
1323 /* intel_dp.c */
1324 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1325 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1326                              struct intel_connector *intel_connector);
1327 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1328                               const struct intel_crtc_state *pipe_config);
1329 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1330 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1331 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1332 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1333 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1334 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1335 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1336 bool intel_dp_compute_config(struct intel_encoder *encoder,
1337                              struct intel_crtc_state *pipe_config);
1338 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1339 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1340                                   bool long_hpd);
1341 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1342 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1343 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1344 void intel_edp_panel_on(struct intel_dp *intel_dp);
1345 void intel_edp_panel_off(struct intel_dp *intel_dp);
1346 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1347 void intel_dp_mst_suspend(struct drm_device *dev);
1348 void intel_dp_mst_resume(struct drm_device *dev);
1349 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1350 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1351 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1352 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1353 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1354 void intel_plane_destroy(struct drm_plane *plane);
1355 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1356 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1357 void intel_edp_drrs_invalidate(struct drm_device *dev,
1358                 unsigned frontbuffer_bits);
1359 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1360 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1361                                          struct intel_digital_port *port);
1362
1363 void
1364 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1365                                        uint8_t dp_train_pat);
1366 void
1367 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1368 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1369 uint8_t
1370 intel_dp_voltage_max(struct intel_dp *intel_dp);
1371 uint8_t
1372 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1373 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1374                            uint8_t *link_bw, uint8_t *rate_select);
1375 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1376 bool
1377 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1378
1379 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1380 {
1381         return ~((1 << lane_count) - 1) & 0xf;
1382 }
1383
1384 /* intel_dp_aux_backlight.c */
1385 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1386
1387 /* intel_dp_mst.c */
1388 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1389 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1390 /* intel_dsi.c */
1391 void intel_dsi_init(struct drm_device *dev);
1392
1393 /* intel_dsi_dcs_backlight.c */
1394 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1395
1396 /* intel_dvo.c */
1397 void intel_dvo_init(struct drm_device *dev);
1398
1399
1400 /* legacy fbdev emulation in intel_fbdev.c */
1401 #ifdef CONFIG_DRM_FBDEV_EMULATION
1402 extern int intel_fbdev_init(struct drm_device *dev);
1403 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1404 extern void intel_fbdev_fini(struct drm_device *dev);
1405 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1406 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1407 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1408 #else
1409 static inline int intel_fbdev_init(struct drm_device *dev)
1410 {
1411         return 0;
1412 }
1413
1414 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1415 {
1416 }
1417
1418 static inline void intel_fbdev_fini(struct drm_device *dev)
1419 {
1420 }
1421
1422 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1423 {
1424 }
1425
1426 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1427 {
1428 }
1429 #endif
1430
1431 /* intel_fbc.c */
1432 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1433                            struct drm_atomic_state *state);
1434 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1435 void intel_fbc_pre_update(struct intel_crtc *crtc);
1436 void intel_fbc_post_update(struct intel_crtc *crtc);
1437 void intel_fbc_init(struct drm_i915_private *dev_priv);
1438 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1439 void intel_fbc_enable(struct intel_crtc *crtc);
1440 void intel_fbc_disable(struct intel_crtc *crtc);
1441 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1442 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1443                           unsigned int frontbuffer_bits,
1444                           enum fb_op_origin origin);
1445 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1446                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1447 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1448
1449 /* intel_hdmi.c */
1450 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1451 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1452                                struct intel_connector *intel_connector);
1453 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1454 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1455                                struct intel_crtc_state *pipe_config);
1456 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1457
1458
1459 /* intel_lvds.c */
1460 void intel_lvds_init(struct drm_device *dev);
1461 bool intel_is_dual_link_lvds(struct drm_device *dev);
1462
1463
1464 /* intel_modes.c */
1465 int intel_connector_update_modes(struct drm_connector *connector,
1466                                  struct edid *edid);
1467 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1468 void intel_attach_force_audio_property(struct drm_connector *connector);
1469 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1470 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1471
1472
1473 /* intel_overlay.c */
1474 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1475 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1476 int intel_overlay_switch_off(struct intel_overlay *overlay);
1477 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1478                                   struct drm_file *file_priv);
1479 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1480                               struct drm_file *file_priv);
1481 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1482
1483
1484 /* intel_panel.c */
1485 int intel_panel_init(struct intel_panel *panel,
1486                      struct drm_display_mode *fixed_mode,
1487                      struct drm_display_mode *downclock_mode);
1488 void intel_panel_fini(struct intel_panel *panel);
1489 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1490                             struct drm_display_mode *adjusted_mode);
1491 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1492                              struct intel_crtc_state *pipe_config,
1493                              int fitting_mode);
1494 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1495                               struct intel_crtc_state *pipe_config,
1496                               int fitting_mode);
1497 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1498                                     u32 level, u32 max);
1499 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1500 void intel_panel_enable_backlight(struct intel_connector *connector);
1501 void intel_panel_disable_backlight(struct intel_connector *connector);
1502 void intel_panel_destroy_backlight(struct drm_connector *connector);
1503 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1504 extern struct drm_display_mode *intel_find_panel_downclock(
1505                                 struct drm_device *dev,
1506                                 struct drm_display_mode *fixed_mode,
1507                                 struct drm_connector *connector);
1508 void intel_backlight_register(struct drm_device *dev);
1509 void intel_backlight_unregister(struct drm_device *dev);
1510
1511
1512 /* intel_psr.c */
1513 void intel_psr_enable(struct intel_dp *intel_dp);
1514 void intel_psr_disable(struct intel_dp *intel_dp);
1515 void intel_psr_invalidate(struct drm_device *dev,
1516                           unsigned frontbuffer_bits);
1517 void intel_psr_flush(struct drm_device *dev,
1518                      unsigned frontbuffer_bits,
1519                      enum fb_op_origin origin);
1520 void intel_psr_init(struct drm_device *dev);
1521 void intel_psr_single_frame_update(struct drm_device *dev,
1522                                    unsigned frontbuffer_bits);
1523
1524 /* intel_runtime_pm.c */
1525 int intel_power_domains_init(struct drm_i915_private *);
1526 void intel_power_domains_fini(struct drm_i915_private *);
1527 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1528 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1529 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1530 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1531 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1532 const char *
1533 intel_display_power_domain_str(enum intel_display_power_domain domain);
1534
1535 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1536                                     enum intel_display_power_domain domain);
1537 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1538                                       enum intel_display_power_domain domain);
1539 void intel_display_power_get(struct drm_i915_private *dev_priv,
1540                              enum intel_display_power_domain domain);
1541 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1542                                         enum intel_display_power_domain domain);
1543 void intel_display_power_put(struct drm_i915_private *dev_priv,
1544                              enum intel_display_power_domain domain);
1545
1546 static inline void
1547 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1548 {
1549         WARN_ONCE(dev_priv->pm.suspended,
1550                   "Device suspended during HW access\n");
1551 }
1552
1553 static inline void
1554 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1555 {
1556         assert_rpm_device_not_suspended(dev_priv);
1557         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1558          * too much noise. */
1559         if (!atomic_read(&dev_priv->pm.wakeref_count))
1560                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1561 }
1562
1563 static inline int
1564 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1565 {
1566         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1567
1568         assert_rpm_wakelock_held(dev_priv);
1569
1570         return seq;
1571 }
1572
1573 static inline void
1574 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1575 {
1576         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1577                   "HW access outside of RPM atomic section\n");
1578 }
1579
1580 /**
1581  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1582  * @dev_priv: i915 device instance
1583  *
1584  * This function disable asserts that check if we hold an RPM wakelock
1585  * reference, while keeping the device-not-suspended checks still enabled.
1586  * It's meant to be used only in special circumstances where our rule about
1587  * the wakelock refcount wrt. the device power state doesn't hold. According
1588  * to this rule at any point where we access the HW or want to keep the HW in
1589  * an active state we must hold an RPM wakelock reference acquired via one of
1590  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1591  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1592  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1593  * users should avoid using this function.
1594  *
1595  * Any calls to this function must have a symmetric call to
1596  * enable_rpm_wakeref_asserts().
1597  */
1598 static inline void
1599 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1600 {
1601         atomic_inc(&dev_priv->pm.wakeref_count);
1602 }
1603
1604 /**
1605  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1606  * @dev_priv: i915 device instance
1607  *
1608  * This function re-enables the RPM assert checks after disabling them with
1609  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1610  * circumstances otherwise its use should be avoided.
1611  *
1612  * Any calls to this function must have a symmetric call to
1613  * disable_rpm_wakeref_asserts().
1614  */
1615 static inline void
1616 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1617 {
1618         atomic_dec(&dev_priv->pm.wakeref_count);
1619 }
1620
1621 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1622 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1623         disable_rpm_wakeref_asserts(dev_priv)
1624
1625 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1626         enable_rpm_wakeref_asserts(dev_priv)
1627
1628 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1629 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1630 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1631 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1632
1633 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1634
1635 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1636                              bool override, unsigned int mask);
1637 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1638                           enum dpio_channel ch, bool override);
1639
1640
1641 /* intel_pm.c */
1642 void intel_init_clock_gating(struct drm_device *dev);
1643 void intel_suspend_hw(struct drm_device *dev);
1644 int ilk_wm_max_level(const struct drm_device *dev);
1645 void intel_update_watermarks(struct drm_crtc *crtc);
1646 void intel_init_pm(struct drm_device *dev);
1647 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1648 void intel_pm_setup(struct drm_device *dev);
1649 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1650 void intel_gpu_ips_teardown(void);
1651 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1652 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1653 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1654 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1655 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1656 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1657 void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1658 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1659 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1660 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1661 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1662                     struct intel_rps_client *rps,
1663                     unsigned long submitted);
1664 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1665 void vlv_wm_get_hw_state(struct drm_device *dev);
1666 void ilk_wm_get_hw_state(struct drm_device *dev);
1667 void skl_wm_get_hw_state(struct drm_device *dev);
1668 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1669                           struct skl_ddb_allocation *ddb /* out */);
1670 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1671 bool ilk_disable_lp_wm(struct drm_device *dev);
1672 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1673 static inline int intel_enable_rc6(void)
1674 {
1675         return i915.enable_rc6;
1676 }
1677
1678 /* intel_sdvo.c */
1679 bool intel_sdvo_init(struct drm_device *dev,
1680                      i915_reg_t reg, enum port port);
1681
1682
1683 /* intel_sprite.c */
1684 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1685 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1686                               struct drm_file *file_priv);
1687 void intel_pipe_update_start(struct intel_crtc *crtc);
1688 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1689
1690 /* intel_tv.c */
1691 void intel_tv_init(struct drm_device *dev);
1692
1693 /* intel_atomic.c */
1694 int intel_connector_atomic_get_property(struct drm_connector *connector,
1695                                         const struct drm_connector_state *state,
1696                                         struct drm_property *property,
1697                                         uint64_t *val);
1698 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1699 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1700                                struct drm_crtc_state *state);
1701 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1702 void intel_atomic_state_clear(struct drm_atomic_state *);
1703 struct intel_shared_dpll_config *
1704 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1705
1706 static inline struct intel_crtc_state *
1707 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1708                             struct intel_crtc *crtc)
1709 {
1710         struct drm_crtc_state *crtc_state;
1711         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1712         if (IS_ERR(crtc_state))
1713                 return ERR_CAST(crtc_state);
1714
1715         return to_intel_crtc_state(crtc_state);
1716 }
1717
1718 static inline struct intel_plane_state *
1719 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1720                                       struct intel_plane *plane)
1721 {
1722         struct drm_plane_state *plane_state;
1723
1724         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1725
1726         return to_intel_plane_state(plane_state);
1727 }
1728
1729 int intel_atomic_setup_scalers(struct drm_device *dev,
1730         struct intel_crtc *intel_crtc,
1731         struct intel_crtc_state *crtc_state);
1732
1733 /* intel_atomic_plane.c */
1734 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1735 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1736 void intel_plane_destroy_state(struct drm_plane *plane,
1737                                struct drm_plane_state *state);
1738 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1739
1740 /* intel_color.c */
1741 void intel_color_init(struct drm_crtc *crtc);
1742 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1743 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1744 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1745
1746 #endif /* __INTEL_DRV_H__ */