drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72 #define wait_for_us(COND, US)           _wait_for((COND), (US), 1)
  73
  74 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  75 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  76 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
  77 #else
  78 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
  79 #endif
  80
  81 #define _wait_for_atomic(COND, US) ({ \
  82         unsigned long end__; \
  83         int ret__ = 0; \
  84         _WAIT_FOR_ATOMIC_CHECK; \
  85         BUILD_BUG_ON((US) > 50000); \
  86         end__ = (local_clock() >> 10) + (US) + 1; \
  87         while (!(COND)) { \
  88                 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
  89                         /* Unlike the regular wait_for(), this atomic variant \
  90                          * cannot be preempted (and we'll just ignore the issue\
  91                          * of irq interruptions) and so we know that no time \
  92                          * has passed since the last check of COND and can \
  93                          * immediately report the timeout. \
  94                          */ \
  95                         ret__ = -ETIMEDOUT; \
  96                         break; \
  97                 } \
  98                 cpu_relax(); \
  99         } \
 100         ret__; \
 101 })
 102
 103 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000)
 104 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US))
 105
 106 #define KHz(x) (1000 * (x))
 107 #define MHz(x) KHz(1000 * (x))
 108
 109 /*
 110  * Display related stuff
 111  */
 112
 113 /* store information about an Ixxx DVO */
 114 /* The i830->i865 use multiple DVOs with multiple i2cs */
 115 /* the i915, i945 have a single sDVO i2c bus - which is different */
 116 #define MAX_OUTPUTS 6
 117 /* maximum connectors per crtcs in the mode set */
 118
 119 /* Maximum cursor sizes */
 120 #define GEN2_CURSOR_WIDTH 64
 121 #define GEN2_CURSOR_HEIGHT 64
 122 #define MAX_CURSOR_WIDTH 256
 123 #define MAX_CURSOR_HEIGHT 256
 124
 125 #define INTEL_I2C_BUS_DVO 1
 126 #define INTEL_I2C_BUS_SDVO 2
 127
 128 /* these are outputs from the chip - integrated only
 129    external chips are via DVO or SDVO output */
 130 enum intel_output_type {
 131         INTEL_OUTPUT_UNUSED = 0,
 132         INTEL_OUTPUT_ANALOG = 1,
 133         INTEL_OUTPUT_DVO = 2,
 134         INTEL_OUTPUT_SDVO = 3,
 135         INTEL_OUTPUT_LVDS = 4,
 136         INTEL_OUTPUT_TVOUT = 5,
 137         INTEL_OUTPUT_HDMI = 6,
 138         INTEL_OUTPUT_DISPLAYPORT = 7,
 139         INTEL_OUTPUT_EDP = 8,
 140         INTEL_OUTPUT_DSI = 9,
 141         INTEL_OUTPUT_UNKNOWN = 10,
 142         INTEL_OUTPUT_DP_MST = 11,
 143 };
 144
 145 #define INTEL_DVO_CHIP_NONE 0
 146 #define INTEL_DVO_CHIP_LVDS 1
 147 #define INTEL_DVO_CHIP_TMDS 2
 148 #define INTEL_DVO_CHIP_TVOUT 4
 149
 150 #define INTEL_DSI_VIDEO_MODE    0
 151 #define INTEL_DSI_COMMAND_MODE  1
 152
 153 struct intel_framebuffer {
 154         struct drm_framebuffer base;
 155         struct drm_i915_gem_object *obj;
 156         struct intel_rotation_info rot_info;
 157 };
 158
 159 struct intel_fbdev {
 160         struct drm_fb_helper helper;
 161         struct intel_framebuffer *fb;
 162         int preferred_bpp;
 163 };
 164
 165 struct intel_encoder {
 166         struct drm_encoder base;
 167
 168         enum intel_output_type type;
 169         unsigned int cloneable;
 170         void (*hot_plug)(struct intel_encoder *);
 171         bool (*compute_config)(struct intel_encoder *,
 172                                struct intel_crtc_state *);
 173         void (*pre_pll_enable)(struct intel_encoder *);
 174         void (*pre_enable)(struct intel_encoder *);
 175         void (*enable)(struct intel_encoder *);
 176         void (*mode_set)(struct intel_encoder *intel_encoder);
 177         void (*disable)(struct intel_encoder *);
 178         void (*post_disable)(struct intel_encoder *);
 179         void (*post_pll_disable)(struct intel_encoder *);
 180         /* Read out the current hw state of this connector, returning true if
 181          * the encoder is active. If the encoder is enabled it also set the pipe
 182          * it is connected to in the pipe parameter. */
 183         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 184         /* Reconstructs the equivalent mode flags for the current hardware
 185          * state. This must be called _after_ display->get_pipe_config has
 186          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 187          * be set correctly before calling this function. */
 188         void (*get_config)(struct intel_encoder *,
 189                            struct intel_crtc_state *pipe_config);
 190         /*
 191          * Called during system suspend after all pending requests for the
 192          * encoder are flushed (for example for DP AUX transactions) and
 193          * device interrupts are disabled.
 194          */
 195         void (*suspend)(struct intel_encoder *);
 196         int crtc_mask;
 197         enum hpd_pin hpd_pin;
 198 };
 199
 200 struct intel_panel {
 201         struct drm_display_mode *fixed_mode;
 202         struct drm_display_mode *downclock_mode;
 203         int fitting_mode;
 204
 205         /* backlight */
 206         struct {
 207                 bool present;
 208                 u32 level;
 209                 u32 min;
 210                 u32 max;
 211                 bool enabled;
 212                 bool combination_mode;  /* gen 2/4 only */
 213                 bool active_low_pwm;
 214
 215                 /* PWM chip */
 216                 bool util_pin_active_low;       /* bxt+ */
 217                 u8 controller;          /* bxt+ only */
 218                 struct pwm_device *pwm;
 219
 220                 struct backlight_device *device;
 221
 222                 /* Connector and platform specific backlight functions */
 223                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 224                 uint32_t (*get)(struct intel_connector *connector);
 225                 void (*set)(struct intel_connector *connector, uint32_t level);
 226                 void (*disable)(struct intel_connector *connector);
 227                 void (*enable)(struct intel_connector *connector);
 228                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 229                                       uint32_t hz);
 230                 void (*power)(struct intel_connector *, bool enable);
 231         } backlight;
 232 };
 233
 234 struct intel_connector {
 235         struct drm_connector base;
 236         /*
 237          * The fixed encoder this connector is connected to.
 238          */
 239         struct intel_encoder *encoder;
 240
 241         /* Reads out the current hw, returning true if the connector is enabled
 242          * and active (i.e. dpms ON state). */
 243         bool (*get_hw_state)(struct intel_connector *);
 244
 245         /* Panel info for eDP and LVDS */
 246         struct intel_panel panel;
 247
 248         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 249         struct edid *edid;
 250         struct edid *detect_edid;
 251
 252         /* since POLL and HPD connectors may use the same HPD line keep the native
 253            state of connector->polled in case hotplug storm detection changes it */
 254         u8 polled;
 255
 256         void *port; /* store this opaque as its illegal to dereference it */
 257
 258         struct intel_dp *mst_port;
 259 };
 260
 261 struct dpll {
 262         /* given values */
 263         int n;
 264         int m1, m2;
 265         int p1, p2;
 266         /* derived values */
 267         int     dot;
 268         int     vco;
 269         int     m;
 270         int     p;
 271 };
 272
 273 struct intel_atomic_state {
 274         struct drm_atomic_state base;
 275
 276         unsigned int cdclk;
 277
 278         /*
 279          * Calculated device cdclk, can be different from cdclk
 280          * only when all crtc's are DPMS off.
 281          */
 282         unsigned int dev_cdclk;
 283
 284         bool dpll_set, modeset;
 285
 286         /*
 287          * Does this transaction change the pipes that are active?  This mask
 288          * tracks which CRTC's have changed their active state at the end of
 289          * the transaction (not counting the temporary disable during modesets).
 290          * This mask should only be non-zero when intel_state->modeset is true,
 291          * but the converse is not necessarily true; simply changing a mode may
 292          * not flip the final active status of any CRTC's
 293          */
 294         unsigned int active_pipe_changes;
 295
 296         unsigned int active_crtcs;
 297         unsigned int min_pixclk[I915_MAX_PIPES];
 298
 299         /* SKL/KBL Only */
 300         unsigned int cdclk_pll_vco;
 301
 302         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 303
 304         /*
 305          * Current watermarks can't be trusted during hardware readout, so
 306          * don't bother calculating intermediate watermarks.
 307          */
 308         bool skip_intermediate_wm;
 309
 310         /* Gen9+ only */
 311         struct skl_wm_values wm_results;
 312 };
 313
 314 struct intel_plane_state {
 315         struct drm_plane_state base;
 316         struct drm_rect src;
 317         struct drm_rect dst;
 318         struct drm_rect clip;
 319         bool visible;
 320
 321         /*
 322          * scaler_id
 323          *    = -1 : not using a scaler
 324          *    >=  0 : using a scalers
 325          *
 326          * plane requiring a scaler:
 327          *   - During check_plane, its bit is set in
 328          *     crtc_state->scaler_state.scaler_users by calling helper function
 329          *     update_scaler_plane.
 330          *   - scaler_id indicates the scaler it got assigned.
 331          *
 332          * plane doesn't require a scaler:
 333          *   - this can happen when scaling is no more required or plane simply
 334          *     got disabled.
 335          *   - During check_plane, corresponding bit is reset in
 336          *     crtc_state->scaler_state.scaler_users by calling helper function
 337          *     update_scaler_plane.
 338          */
 339         int scaler_id;
 340
 341         struct drm_intel_sprite_colorkey ckey;
 342
 343         /* async flip related structures */
 344         struct drm_i915_gem_request *wait_req;
 345 };
 346
 347 struct intel_initial_plane_config {
 348         struct intel_framebuffer *fb;
 349         unsigned int tiling;
 350         int size;
 351         u32 base;
 352 };
 353
 354 #define SKL_MIN_SRC_W 8
 355 #define SKL_MAX_SRC_W 4096
 356 #define SKL_MIN_SRC_H 8
 357 #define SKL_MAX_SRC_H 4096
 358 #define SKL_MIN_DST_W 8
 359 #define SKL_MAX_DST_W 4096
 360 #define SKL_MIN_DST_H 8
 361 #define SKL_MAX_DST_H 4096
 362
 363 struct intel_scaler {
 364         int in_use;
 365         uint32_t mode;
 366 };
 367
 368 struct intel_crtc_scaler_state {
 369 #define SKL_NUM_SCALERS 2
 370         struct intel_scaler scalers[SKL_NUM_SCALERS];
 371
 372         /*
 373          * scaler_users: keeps track of users requesting scalers on this crtc.
 374          *
 375          *     If a bit is set, a user is using a scaler.
 376          *     Here user can be a plane or crtc as defined below:
 377          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 378          *       bit 31    - crtc
 379          *
 380          * Instead of creating a new index to cover planes and crtc, using
 381          * existing drm_plane_index for planes which is well less than 31
 382          * planes and bit 31 for crtc. This should be fine to cover all
 383          * our platforms.
 384          *
 385          * intel_atomic_setup_scalers will setup available scalers to users
 386          * requesting scalers. It will gracefully fail if request exceeds
 387          * avilability.
 388          */
 389 #define SKL_CRTC_INDEX 31
 390         unsigned scaler_users;
 391
 392         /* scaler used by crtc for panel fitting purpose */
 393         int scaler_id;
 394 };
 395
 396 /* drm_mode->private_flags */
 397 #define I915_MODE_FLAG_INHERITED 1
 398
 399 struct intel_pipe_wm {
 400         struct intel_wm_level wm[5];
 401         struct intel_wm_level raw_wm[5];
 402         uint32_t linetime;
 403         bool fbc_wm_enabled;
 404         bool pipe_enabled;
 405         bool sprites_enabled;
 406         bool sprites_scaled;
 407 };
 408
 409 struct skl_pipe_wm {
 410         struct skl_wm_level wm[8];
 411         struct skl_wm_level trans_wm;
 412         uint32_t linetime;
 413 };
 414
 415 struct intel_crtc_wm_state {
 416         union {
 417                 struct {
 418                         /*
 419                          * Intermediate watermarks; these can be
 420                          * programmed immediately since they satisfy
 421                          * both the current configuration we're
 422                          * switching away from and the new
 423                          * configuration we're switching to.
 424                          */
 425                         struct intel_pipe_wm intermediate;
 426
 427                         /*
 428                          * Optimal watermarks, programmed post-vblank
 429                          * when this state is committed.
 430                          */
 431                         struct intel_pipe_wm optimal;
 432                 } ilk;
 433
 434                 struct {
 435                         /* gen9+ only needs 1-step wm programming */
 436                         struct skl_pipe_wm optimal;
 437
 438                         /* cached plane data rate */
 439                         unsigned plane_data_rate[I915_MAX_PLANES];
 440                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 441
 442                         /* minimum block allocation */
 443                         uint16_t minimum_blocks[I915_MAX_PLANES];
 444                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 445                 } skl;
 446         };
 447
 448         /*
 449          * Platforms with two-step watermark programming will need to
 450          * update watermark programming post-vblank to switch from the
 451          * safe intermediate watermarks to the optimal final
 452          * watermarks.
 453          */
 454         bool need_postvbl_update;
 455 };
 456
 457 struct intel_crtc_state {
 458         struct drm_crtc_state base;
 459
 460         /**
 461          * quirks - bitfield with hw state readout quirks
 462          *
 463          * For various reasons the hw state readout code might not be able to
 464          * completely faithfully read out the current state. These cases are
 465          * tracked with quirk flags so that fastboot and state checker can act
 466          * accordingly.
 467          */
 468 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 469         unsigned long quirks;
 470
 471         unsigned fb_bits; /* framebuffers to flip */
 472         bool update_pipe; /* can a fast modeset be performed? */
 473         bool disable_cxsr;
 474         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 475         bool fb_changed; /* fb on any of the planes is changed */
 476
 477         /* Pipe source size (ie. panel fitter input size)
 478          * All planes will be positioned inside this space,
 479          * and get clipped at the edges. */
 480         int pipe_src_w, pipe_src_h;
 481
 482         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 483          * between pch encoders and cpu encoders. */
 484         bool has_pch_encoder;
 485
 486         /* Are we sending infoframes on the attached port */
 487         bool has_infoframe;
 488
 489         /* CPU Transcoder for the pipe. Currently this can only differ from the
 490          * pipe on Haswell and later (where we have a special eDP transcoder)
 491          * and Broxton (where we have special DSI transcoders). */
 492         enum transcoder cpu_transcoder;
 493
 494         /*
 495          * Use reduced/limited/broadcast rbg range, compressing from the full
 496          * range fed into the crtcs.
 497          */
 498         bool limited_color_range;
 499
 500         /* DP has a bunch of special case unfortunately, so mark the pipe
 501          * accordingly. */
 502         bool has_dp_encoder;
 503
 504         /* DSI has special cases */
 505         bool has_dsi_encoder;
 506
 507         /* Whether we should send NULL infoframes. Required for audio. */
 508         bool has_hdmi_sink;
 509
 510         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 511          * has_dp_encoder is set. */
 512         bool has_audio;
 513
 514         /*
 515          * Enable dithering, used when the selected pipe bpp doesn't match the
 516          * plane bpp.
 517          */
 518         bool dither;
 519
 520         /* Controls for the clock computation, to override various stages. */
 521         bool clock_set;
 522
 523         /* SDVO TV has a bunch of special case. To make multifunction encoders
 524          * work correctly, we need to track this at runtime.*/
 525         bool sdvo_tv_clock;
 526
 527         /*
 528          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 529          * required. This is set in the 2nd loop of calling encoder's
 530          * ->compute_config if the first pick doesn't work out.
 531          */
 532         bool bw_constrained;
 533
 534         /* Settings for the intel dpll used on pretty much everything but
 535          * haswell. */
 536         struct dpll dpll;
 537
 538         /* Selected dpll when shared or NULL. */
 539         struct intel_shared_dpll *shared_dpll;
 540
 541         /*
 542          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 543          * - enum skl_dpll on SKL
 544          */
 545         uint32_t ddi_pll_sel;
 546
 547         /* Actual register state of the dpll, for shared dpll cross-checking. */
 548         struct intel_dpll_hw_state dpll_hw_state;
 549
 550         /* DSI PLL registers */
 551         struct {
 552                 u32 ctrl, div;
 553         } dsi_pll;
 554
 555         int pipe_bpp;
 556         struct intel_link_m_n dp_m_n;
 557
 558         /* m2_n2 for eDP downclock */
 559         struct intel_link_m_n dp_m2_n2;
 560         bool has_drrs;
 561
 562         /*
 563          * Frequence the dpll for the port should run at. Differs from the
 564          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 565          * already multiplied by pixel_multiplier.
 566          */
 567         int port_clock;
 568
 569         /* Used by SDVO (and if we ever fix it, HDMI). */
 570         unsigned pixel_multiplier;
 571
 572         uint8_t lane_count;
 573
 574         /*
 575          * Used by platforms having DP/HDMI PHY with programmable lane
 576          * latency optimization.
 577          */
 578         uint8_t lane_lat_optim_mask;
 579
 580         /* Panel fitter controls for gen2-gen4 + VLV */
 581         struct {
 582                 u32 control;
 583                 u32 pgm_ratios;
 584                 u32 lvds_border_bits;
 585         } gmch_pfit;
 586
 587         /* Panel fitter placement and size for Ironlake+ */
 588         struct {
 589                 u32 pos;
 590                 u32 size;
 591                 bool enabled;
 592                 bool force_thru;
 593         } pch_pfit;
 594
 595         /* FDI configuration, only valid if has_pch_encoder is set. */
 596         int fdi_lanes;
 597         struct intel_link_m_n fdi_m_n;
 598
 599         bool ips_enabled;
 600
 601         bool enable_fbc;
 602
 603         bool double_wide;
 604
 605         bool dp_encoder_is_mst;
 606         int pbn;
 607
 608         struct intel_crtc_scaler_state scaler_state;
 609
 610         /* w/a for waiting 2 vblanks during crtc enable */
 611         enum pipe hsw_workaround_pipe;
 612
 613         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 614         bool disable_lp_wm;
 615
 616         struct intel_crtc_wm_state wm;
 617
 618         /* Gamma mode programmed on the pipe */
 619         uint32_t gamma_mode;
 620 };
 621
 622 struct vlv_wm_state {
 623         struct vlv_pipe_wm wm[3];
 624         struct vlv_sr_wm sr[3];
 625         uint8_t num_active_planes;
 626         uint8_t num_levels;
 627         uint8_t level;
 628         bool cxsr;
 629 };
 630
 631 struct intel_crtc {
 632         struct drm_crtc base;
 633         enum pipe pipe;
 634         enum plane plane;
 635         u8 lut_r[256], lut_g[256], lut_b[256];
 636         /*
 637          * Whether the crtc and the connected output pipeline is active. Implies
 638          * that crtc->enabled is set, i.e. the current mode configuration has
 639          * some outputs connected to this crtc.
 640          */
 641         bool active;
 642         unsigned long enabled_power_domains;
 643         bool lowfreq_avail;
 644         struct intel_overlay *overlay;
 645         struct intel_flip_work *flip_work;
 646
 647         atomic_t unpin_work_count;
 648
 649         /* Display surface base address adjustement for pageflips. Note that on
 650          * gen4+ this only adjusts up to a tile, offsets within a tile are
 651          * handled in the hw itself (with the TILEOFF register). */
 652         u32 dspaddr_offset;
 653         int adjusted_x;
 654         int adjusted_y;
 655
 656         uint32_t cursor_addr;
 657         uint32_t cursor_cntl;
 658         uint32_t cursor_size;
 659         uint32_t cursor_base;
 660
 661         struct intel_crtc_state *config;
 662
 663         /* reset counter value when the last flip was submitted */
 664         unsigned int reset_counter;
 665
 666         /* Access to these should be protected by dev_priv->irq_lock. */
 667         bool cpu_fifo_underrun_disabled;
 668         bool pch_fifo_underrun_disabled;
 669
 670         /* per-pipe watermark state */
 671         struct {
 672                 /* watermarks currently being used  */
 673                 union {
 674                         struct intel_pipe_wm ilk;
 675                         struct skl_pipe_wm skl;
 676                 } active;
 677
 678                 /* allow CxSR on this pipe */
 679                 bool cxsr_allowed;
 680         } wm;
 681
 682         int scanline_offset;
 683
 684         struct {
 685                 unsigned start_vbl_count;
 686                 ktime_t start_vbl_time;
 687                 int min_vbl, max_vbl;
 688                 int scanline_start;
 689         } debug;
 690
 691         /* scalers available on this crtc */
 692         int num_scalers;
 693
 694         struct vlv_wm_state wm_state;
 695 };
 696
 697 struct intel_plane_wm_parameters {
 698         uint32_t horiz_pixels;
 699         uint32_t vert_pixels;
 700         /*
 701          *   For packed pixel formats:
 702          *     bytes_per_pixel - holds bytes per pixel
 703          *   For planar pixel formats:
 704          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 705          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 706          */
 707         uint8_t bytes_per_pixel;
 708         uint8_t y_bytes_per_pixel;
 709         bool enabled;
 710         bool scaled;
 711         u64 tiling;
 712         unsigned int rotation;
 713         uint16_t fifo_size;
 714 };
 715
 716 struct intel_plane {
 717         struct drm_plane base;
 718         int plane;
 719         enum pipe pipe;
 720         bool can_scale;
 721         int max_downscale;
 722         uint32_t frontbuffer_bit;
 723
 724         /* Since we need to change the watermarks before/after
 725          * enabling/disabling the planes, we need to store the parameters here
 726          * as the other pieces of the struct may not reflect the values we want
 727          * for the watermark calculations. Currently only Haswell uses this.
 728          */
 729         struct intel_plane_wm_parameters wm;
 730
 731         /*
 732          * NOTE: Do not place new plane state fields here (e.g., when adding
 733          * new plane properties).  New runtime state should now be placed in
 734          * the intel_plane_state structure and accessed via plane_state.
 735          */
 736
 737         void (*update_plane)(struct drm_plane *plane,
 738                              const struct intel_crtc_state *crtc_state,
 739                              const struct intel_plane_state *plane_state);
 740         void (*disable_plane)(struct drm_plane *plane,
 741                               struct drm_crtc *crtc);
 742         int (*check_plane)(struct drm_plane *plane,
 743                            struct intel_crtc_state *crtc_state,
 744                            struct intel_plane_state *state);
 745 };
 746
 747 struct intel_watermark_params {
 748         unsigned long fifo_size;
 749         unsigned long max_wm;
 750         unsigned long default_wm;
 751         unsigned long guard_size;
 752         unsigned long cacheline_size;
 753 };
 754
 755 struct cxsr_latency {
 756         int is_desktop;
 757         int is_ddr3;
 758         unsigned long fsb_freq;
 759         unsigned long mem_freq;
 760         unsigned long display_sr;
 761         unsigned long display_hpll_disable;
 762         unsigned long cursor_sr;
 763         unsigned long cursor_hpll_disable;
 764 };
 765
 766 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 767 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 768 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 769 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 770 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 771 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 772 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 773 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 774 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 775
 776 struct intel_hdmi {
 777         i915_reg_t hdmi_reg;
 778         int ddc_bus;
 779         struct {
 780                 enum drm_dp_dual_mode_type type;
 781                 int max_tmds_clock;
 782         } dp_dual_mode;
 783         bool limited_color_range;
 784         bool color_range_auto;
 785         bool has_hdmi_sink;
 786         bool has_audio;
 787         enum hdmi_force_audio force_audio;
 788         bool rgb_quant_range_selectable;
 789         enum hdmi_picture_aspect aspect_ratio;
 790         struct intel_connector *attached_connector;
 791         void (*write_infoframe)(struct drm_encoder *encoder,
 792                                 enum hdmi_infoframe_type type,
 793                                 const void *frame, ssize_t len);
 794         void (*set_infoframes)(struct drm_encoder *encoder,
 795                                bool enable,
 796                                const struct drm_display_mode *adjusted_mode);
 797         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 798                                   const struct intel_crtc_state *pipe_config);
 799 };
 800
 801 struct intel_dp_mst_encoder;
 802 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 803
 804 /*
 805  * enum link_m_n_set:
 806  *      When platform provides two set of M_N registers for dp, we can
 807  *      program them and switch between them incase of DRRS.
 808  *      But When only one such register is provided, we have to program the
 809  *      required divider value on that registers itself based on the DRRS state.
 810  *
 811  * M1_N1        : Program dp_m_n on M1_N1 registers
 812  *                        dp_m2_n2 on M2_N2 registers (If supported)
 813  *
 814  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 815  *                        M2_N2 registers are not supported
 816  */
 817
 818 enum link_m_n_set {
 819         /* Sets the m1_n1 and m2_n2 */
 820         M1_N1 = 0,
 821         M2_N2
 822 };
 823
 824 struct intel_dp {
 825         i915_reg_t output_reg;
 826         i915_reg_t aux_ch_ctl_reg;
 827         i915_reg_t aux_ch_data_reg[5];
 828         uint32_t DP;
 829         int link_rate;
 830         uint8_t lane_count;
 831         uint8_t sink_count;
 832         bool has_audio;
 833         bool detect_done;
 834         enum hdmi_force_audio force_audio;
 835         bool limited_color_range;
 836         bool color_range_auto;
 837         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 838         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 839         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 840         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 841         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 842         uint8_t num_sink_rates;
 843         int sink_rates[DP_MAX_SUPPORTED_RATES];
 844         struct drm_dp_aux aux;
 845         uint8_t train_set[4];
 846         int panel_power_up_delay;
 847         int panel_power_down_delay;
 848         int panel_power_cycle_delay;
 849         int backlight_on_delay;
 850         int backlight_off_delay;
 851         struct delayed_work panel_vdd_work;
 852         bool want_panel_vdd;
 853         unsigned long last_power_on;
 854         unsigned long last_backlight_off;
 855         ktime_t panel_power_off_time;
 856
 857         struct notifier_block edp_notifier;
 858
 859         /*
 860          * Pipe whose power sequencer is currently locked into
 861          * this port. Only relevant on VLV/CHV.
 862          */
 863         enum pipe pps_pipe;
 864         struct edp_power_seq pps_delays;
 865
 866         bool can_mst; /* this port supports mst */
 867         bool is_mst;
 868         int active_mst_links;
 869         /* connector directly attached - won't be use for modeset in mst world */
 870         struct intel_connector *attached_connector;
 871
 872         /* mst connector list */
 873         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 874         struct drm_dp_mst_topology_mgr mst_mgr;
 875
 876         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 877         /*
 878          * This function returns the value we have to program the AUX_CTL
 879          * register with to kick off an AUX transaction.
 880          */
 881         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 882                                      bool has_aux_irq,
 883                                      int send_bytes,
 884                                      uint32_t aux_clock_divider);
 885
 886         /* This is called before a link training is starterd */
 887         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 888
 889         bool train_set_valid;
 890
 891         /* Displayport compliance testing */
 892         unsigned long compliance_test_type;
 893         unsigned long compliance_test_data;
 894         bool compliance_test_active;
 895 };
 896
 897 struct intel_digital_port {
 898         struct intel_encoder base;
 899         enum port port;
 900         u32 saved_port_bits;
 901         struct intel_dp dp;
 902         struct intel_hdmi hdmi;
 903         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 904         bool release_cl2_override;
 905         uint8_t max_lanes;
 906         /* for communication with audio component; protected by av_mutex */
 907         const struct drm_connector *audio_connector;
 908 };
 909
 910 struct intel_dp_mst_encoder {
 911         struct intel_encoder base;
 912         enum pipe pipe;
 913         struct intel_digital_port *primary;
 914         struct intel_connector *connector;
 915 };
 916
 917 static inline enum dpio_channel
 918 vlv_dport_to_channel(struct intel_digital_port *dport)
 919 {
 920         switch (dport->port) {
 921         case PORT_B:
 922         case PORT_D:
 923                 return DPIO_CH0;
 924         case PORT_C:
 925                 return DPIO_CH1;
 926         default:
 927                 BUG();
 928         }
 929 }
 930
 931 static inline enum dpio_phy
 932 vlv_dport_to_phy(struct intel_digital_port *dport)
 933 {
 934         switch (dport->port) {
 935         case PORT_B:
 936         case PORT_C:
 937                 return DPIO_PHY0;
 938         case PORT_D:
 939                 return DPIO_PHY1;
 940         default:
 941                 BUG();
 942         }
 943 }
 944
 945 static inline enum dpio_channel
 946 vlv_pipe_to_channel(enum pipe pipe)
 947 {
 948         switch (pipe) {
 949         case PIPE_A:
 950         case PIPE_C:
 951                 return DPIO_CH0;
 952         case PIPE_B:
 953                 return DPIO_CH1;
 954         default:
 955                 BUG();
 956         }
 957 }
 958
 959 static inline struct drm_crtc *
 960 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 961 {
 962         struct drm_i915_private *dev_priv = dev->dev_private;
 963         return dev_priv->pipe_to_crtc_mapping[pipe];
 964 }
 965
 966 static inline struct drm_crtc *
 967 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 968 {
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         return dev_priv->plane_to_crtc_mapping[plane];
 971 }
 972
 973 struct intel_flip_work {
 974         struct work_struct unpin_work;
 975         struct work_struct mmio_work;
 976
 977         struct drm_crtc *crtc;
 978         struct drm_framebuffer *old_fb;
 979         struct drm_i915_gem_object *pending_flip_obj;
 980         struct drm_pending_vblank_event *event;
 981         atomic_t pending;
 982         u32 flip_count;
 983         u32 gtt_offset;
 984         struct drm_i915_gem_request *flip_queued_req;
 985         u32 flip_queued_vblank;
 986         u32 flip_ready_vblank;
 987         unsigned int rotation;
 988 };
 989
 990 struct intel_load_detect_pipe {
 991         struct drm_atomic_state *restore_state;
 992 };
 993
 994 static inline struct intel_encoder *
 995 intel_attached_encoder(struct drm_connector *connector)
 996 {
 997         return to_intel_connector(connector)->encoder;
 998 }
 999
1000 static inline struct intel_digital_port *
1001 enc_to_dig_port(struct drm_encoder *encoder)
1002 {
1003         return container_of(encoder, struct intel_digital_port, base.base);
1004 }
1005
1006 static inline struct intel_dp_mst_encoder *
1007 enc_to_mst(struct drm_encoder *encoder)
1008 {
1009         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1010 }
1011
1012 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1013 {
1014         return &enc_to_dig_port(encoder)->dp;
1015 }
1016
1017 static inline struct intel_digital_port *
1018 dp_to_dig_port(struct intel_dp *intel_dp)
1019 {
1020         return container_of(intel_dp, struct intel_digital_port, dp);
1021 }
1022
1023 static inline struct intel_digital_port *
1024 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1025 {
1026         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1027 }
1028
1029 /*
1030  * Returns the number of planes for this pipe, ie the number of sprites + 1
1031  * (primary plane). This doesn't count the cursor plane then.
1032  */
1033 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1034 {
1035         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1036 }
1037
1038 /* intel_fifo_underrun.c */
1039 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1040                                            enum pipe pipe, bool enable);
1041 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1042                                            enum transcoder pch_transcoder,
1043                                            bool enable);
1044 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1045                                          enum pipe pipe);
1046 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1047                                          enum transcoder pch_transcoder);
1048 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1049 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1050
1051 /* i915_irq.c */
1052 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1053 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1054 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1055 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1056 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1057 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1058 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1059 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1060 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1061 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1062 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1063 {
1064         /*
1065          * We only use drm_irq_uninstall() at unload and VT switch, so
1066          * this is the only thing we need to check.
1067          */
1068         return dev_priv->pm.irqs_enabled;
1069 }
1070
1071 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1072 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1073                                      unsigned int pipe_mask);
1074 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1075                                      unsigned int pipe_mask);
1076
1077 /* intel_crt.c */
1078 void intel_crt_init(struct drm_device *dev);
1079
1080
1081 /* intel_ddi.c */
1082 void intel_ddi_clk_select(struct intel_encoder *encoder,
1083                           const struct intel_crtc_state *pipe_config);
1084 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1085 void hsw_fdi_link_train(struct drm_crtc *crtc);
1086 void intel_ddi_init(struct drm_device *dev, enum port port);
1087 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1088 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1089 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1090 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1091                                        enum transcoder cpu_transcoder);
1092 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1093 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1094 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1095                           struct intel_crtc_state *crtc_state);
1096 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1097 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1098 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1099 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1100 void intel_ddi_get_config(struct intel_encoder *encoder,
1101                           struct intel_crtc_state *pipe_config);
1102 struct intel_encoder *
1103 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1104
1105 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1106 void intel_ddi_clock_get(struct intel_encoder *encoder,
1107                          struct intel_crtc_state *pipe_config);
1108 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1109 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1110
1111 /* intel_frontbuffer.c */
1112 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1113                              enum fb_op_origin origin);
1114 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1115                                     unsigned frontbuffer_bits);
1116 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1117                                      unsigned frontbuffer_bits);
1118 void intel_frontbuffer_flip(struct drm_device *dev,
1119                             unsigned frontbuffer_bits);
1120 unsigned int intel_fb_align_height(struct drm_device *dev,
1121                                    unsigned int height,
1122                                    uint32_t pixel_format,
1123                                    uint64_t fb_format_modifier);
1124 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1125                         enum fb_op_origin origin);
1126 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1127                               uint64_t fb_modifier, uint32_t pixel_format);
1128
1129 /* intel_audio.c */
1130 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1131 void intel_audio_codec_enable(struct intel_encoder *encoder);
1132 void intel_audio_codec_disable(struct intel_encoder *encoder);
1133 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1134 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1135
1136 /* intel_display.c */
1137 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1138 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1139 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1140                       const char *name, u32 reg, int ref_freq);
1141 extern const struct drm_plane_funcs intel_plane_funcs;
1142 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1143 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1144 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1145 void intel_mark_busy(struct drm_i915_private *dev_priv);
1146 void intel_mark_idle(struct drm_i915_private *dev_priv);
1147 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1148 int intel_display_suspend(struct drm_device *dev);
1149 void intel_encoder_destroy(struct drm_encoder *encoder);
1150 int intel_connector_init(struct intel_connector *);
1151 struct intel_connector *intel_connector_alloc(void);
1152 bool intel_connector_get_hw_state(struct intel_connector *connector);
1153 void intel_connector_attach_encoder(struct intel_connector *connector,
1154                                     struct intel_encoder *encoder);
1155 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1156                                              struct drm_crtc *crtc);
1157 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1158 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1159                                 struct drm_file *file_priv);
1160 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1161                                              enum pipe pipe);
1162 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1163 static inline void
1164 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1165 {
1166         drm_wait_one_vblank(dev, pipe);
1167 }
1168 static inline void
1169 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1170 {
1171         const struct intel_crtc *crtc =
1172                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1173
1174         if (crtc->active)
1175                 intel_wait_for_vblank(dev, pipe);
1176 }
1177
1178 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1179
1180 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1181 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1182                          struct intel_digital_port *dport,
1183                          unsigned int expected_mask);
1184 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1185                                 struct drm_display_mode *mode,
1186                                 struct intel_load_detect_pipe *old,
1187                                 struct drm_modeset_acquire_ctx *ctx);
1188 void intel_release_load_detect_pipe(struct drm_connector *connector,
1189                                     struct intel_load_detect_pipe *old,
1190                                     struct drm_modeset_acquire_ctx *ctx);
1191 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1192                                unsigned int rotation);
1193 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1194 struct drm_framebuffer *
1195 __intel_framebuffer_create(struct drm_device *dev,
1196                            struct drm_mode_fb_cmd2 *mode_cmd,
1197                            struct drm_i915_gem_object *obj);
1198 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1199 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1200 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1201 int intel_prepare_plane_fb(struct drm_plane *plane,
1202                            const struct drm_plane_state *new_state);
1203 void intel_cleanup_plane_fb(struct drm_plane *plane,
1204                             const struct drm_plane_state *old_state);
1205 int intel_plane_atomic_get_property(struct drm_plane *plane,
1206                                     const struct drm_plane_state *state,
1207                                     struct drm_property *property,
1208                                     uint64_t *val);
1209 int intel_plane_atomic_set_property(struct drm_plane *plane,
1210                                     struct drm_plane_state *state,
1211                                     struct drm_property *property,
1212                                     uint64_t val);
1213 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1214                                     struct drm_plane_state *plane_state);
1215
1216 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1217                                uint64_t fb_modifier, unsigned int cpp);
1218
1219 static inline bool
1220 intel_rotation_90_or_270(unsigned int rotation)
1221 {
1222         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1223 }
1224
1225 void intel_create_rotation_property(struct drm_device *dev,
1226                                         struct intel_plane *plane);
1227
1228 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1229                                     enum pipe pipe);
1230
1231 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1232                      const struct dpll *dpll);
1233 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1234 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1235
1236 /* modesetting asserts */
1237 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1238                            enum pipe pipe);
1239 void assert_pll(struct drm_i915_private *dev_priv,
1240                 enum pipe pipe, bool state);
1241 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1242 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1243 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1244 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1245 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1246 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247                        enum pipe pipe, bool state);
1248 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1249 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1250 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1251 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1252 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1253 u32 intel_compute_tile_offset(int *x, int *y,
1254                               const struct drm_framebuffer *fb, int plane,
1255                               unsigned int pitch,
1256                               unsigned int rotation);
1257 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1258 void intel_finish_reset(struct drm_i915_private *dev_priv);
1259 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1260 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1261 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1262 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1263 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1264 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1265 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1266                             enum dpio_phy phy);
1267 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1268                               enum dpio_phy phy);
1269 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1270 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1271 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1272 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1273 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1274 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1275 unsigned int skl_cdclk_get_vco(unsigned int freq);
1276 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1277 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1278 void intel_dp_get_m_n(struct intel_crtc *crtc,
1279                       struct intel_crtc_state *pipe_config);
1280 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1281 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1282 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1283                         struct dpll *best_clock);
1284 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1285
1286 bool intel_crtc_active(struct drm_crtc *crtc);
1287 void hsw_enable_ips(struct intel_crtc *crtc);
1288 void hsw_disable_ips(struct intel_crtc *crtc);
1289 enum intel_display_power_domain
1290 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1291 enum intel_display_power_domain
1292 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1293 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1294                                  struct intel_crtc_state *pipe_config);
1295
1296 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1297 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1298
1299 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1300                            struct drm_i915_gem_object *obj,
1301                            unsigned int plane);
1302
1303 u32 skl_plane_ctl_format(uint32_t pixel_format);
1304 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1305 u32 skl_plane_ctl_rotation(unsigned int rotation);
1306
1307 /* intel_csr.c */
1308 void intel_csr_ucode_init(struct drm_i915_private *);
1309 void intel_csr_load_program(struct drm_i915_private *);
1310 void intel_csr_ucode_fini(struct drm_i915_private *);
1311 void intel_csr_ucode_suspend(struct drm_i915_private *);
1312 void intel_csr_ucode_resume(struct drm_i915_private *);
1313
1314 /* intel_dp.c */
1315 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1316 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1317                              struct intel_connector *intel_connector);
1318 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1319                               const struct intel_crtc_state *pipe_config);
1320 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1321 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1322 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1323 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1324 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1325 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1326 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1327 bool intel_dp_compute_config(struct intel_encoder *encoder,
1328                              struct intel_crtc_state *pipe_config);
1329 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1330 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1331                                   bool long_hpd);
1332 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1333 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1334 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1335 void intel_edp_panel_on(struct intel_dp *intel_dp);
1336 void intel_edp_panel_off(struct intel_dp *intel_dp);
1337 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1338 void intel_dp_mst_suspend(struct drm_device *dev);
1339 void intel_dp_mst_resume(struct drm_device *dev);
1340 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1341 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1342 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1343 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1344 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1345 void intel_plane_destroy(struct drm_plane *plane);
1346 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1347 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1348 void intel_edp_drrs_invalidate(struct drm_device *dev,
1349                 unsigned frontbuffer_bits);
1350 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1351 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1352                                          struct intel_digital_port *port);
1353
1354 void
1355 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1356                                        uint8_t dp_train_pat);
1357 void
1358 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1359 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1360 uint8_t
1361 intel_dp_voltage_max(struct intel_dp *intel_dp);
1362 uint8_t
1363 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1364 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1365                            uint8_t *link_bw, uint8_t *rate_select);
1366 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1367 bool
1368 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1369
1370 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1371 {
1372         return ~((1 << lane_count) - 1) & 0xf;
1373 }
1374
1375 /* intel_dp_aux_backlight.c */
1376 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1377
1378 /* intel_dp_mst.c */
1379 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1380 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1381 /* intel_dsi.c */
1382 void intel_dsi_init(struct drm_device *dev);
1383
1384 /* intel_dsi_dcs_backlight.c */
1385 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1386
1387 /* intel_dvo.c */
1388 void intel_dvo_init(struct drm_device *dev);
1389
1390
1391 /* legacy fbdev emulation in intel_fbdev.c */
1392 #ifdef CONFIG_DRM_FBDEV_EMULATION
1393 extern int intel_fbdev_init(struct drm_device *dev);
1394 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1395 extern void intel_fbdev_fini(struct drm_device *dev);
1396 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1397 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1398 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1399 #else
1400 static inline int intel_fbdev_init(struct drm_device *dev)
1401 {
1402         return 0;
1403 }
1404
1405 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1406 {
1407 }
1408
1409 static inline void intel_fbdev_fini(struct drm_device *dev)
1410 {
1411 }
1412
1413 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1414 {
1415 }
1416
1417 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1418 {
1419 }
1420 #endif
1421
1422 /* intel_fbc.c */
1423 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1424                            struct drm_atomic_state *state);
1425 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1426 void intel_fbc_pre_update(struct intel_crtc *crtc,
1427                           struct intel_crtc_state *crtc_state,
1428                           struct intel_plane_state *plane_state);
1429 void intel_fbc_post_update(struct intel_crtc *crtc);
1430 void intel_fbc_init(struct drm_i915_private *dev_priv);
1431 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1432 void intel_fbc_enable(struct intel_crtc *crtc,
1433                       struct intel_crtc_state *crtc_state,
1434                       struct intel_plane_state *plane_state);
1435 void intel_fbc_disable(struct intel_crtc *crtc);
1436 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1437 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1438                           unsigned int frontbuffer_bits,
1439                           enum fb_op_origin origin);
1440 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1441                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1442 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1443
1444 /* intel_hdmi.c */
1445 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1446 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1447                                struct intel_connector *intel_connector);
1448 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1449 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1450                                struct intel_crtc_state *pipe_config);
1451 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1452
1453
1454 /* intel_lvds.c */
1455 void intel_lvds_init(struct drm_device *dev);
1456 bool intel_is_dual_link_lvds(struct drm_device *dev);
1457
1458
1459 /* intel_modes.c */
1460 int intel_connector_update_modes(struct drm_connector *connector,
1461                                  struct edid *edid);
1462 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1463 void intel_attach_force_audio_property(struct drm_connector *connector);
1464 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1465 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1466
1467
1468 /* intel_overlay.c */
1469 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1470 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1471 int intel_overlay_switch_off(struct intel_overlay *overlay);
1472 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1473                                   struct drm_file *file_priv);
1474 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1475                               struct drm_file *file_priv);
1476 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1477
1478
1479 /* intel_panel.c */
1480 int intel_panel_init(struct intel_panel *panel,
1481                      struct drm_display_mode *fixed_mode,
1482                      struct drm_display_mode *downclock_mode);
1483 void intel_panel_fini(struct intel_panel *panel);
1484 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1485                             struct drm_display_mode *adjusted_mode);
1486 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1487                              struct intel_crtc_state *pipe_config,
1488                              int fitting_mode);
1489 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1490                               struct intel_crtc_state *pipe_config,
1491                               int fitting_mode);
1492 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1493                                     u32 level, u32 max);
1494 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1495 void intel_panel_enable_backlight(struct intel_connector *connector);
1496 void intel_panel_disable_backlight(struct intel_connector *connector);
1497 void intel_panel_destroy_backlight(struct drm_connector *connector);
1498 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1499 extern struct drm_display_mode *intel_find_panel_downclock(
1500                                 struct drm_device *dev,
1501                                 struct drm_display_mode *fixed_mode,
1502                                 struct drm_connector *connector);
1503 void intel_backlight_register(struct drm_device *dev);
1504
1505 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1506 void intel_backlight_device_unregister(struct intel_connector *connector);
1507 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1508 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1509 {
1510 }
1511 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1512
1513
1514 /* intel_psr.c */
1515 void intel_psr_enable(struct intel_dp *intel_dp);
1516 void intel_psr_disable(struct intel_dp *intel_dp);
1517 void intel_psr_invalidate(struct drm_device *dev,
1518                           unsigned frontbuffer_bits);
1519 void intel_psr_flush(struct drm_device *dev,
1520                      unsigned frontbuffer_bits,
1521                      enum fb_op_origin origin);
1522 void intel_psr_init(struct drm_device *dev);
1523 void intel_psr_single_frame_update(struct drm_device *dev,
1524                                    unsigned frontbuffer_bits);
1525
1526 /* intel_runtime_pm.c */
1527 int intel_power_domains_init(struct drm_i915_private *);
1528 void intel_power_domains_fini(struct drm_i915_private *);
1529 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1530 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1531 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1532 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1533 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1534 const char *
1535 intel_display_power_domain_str(enum intel_display_power_domain domain);
1536
1537 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1538                                     enum intel_display_power_domain domain);
1539 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1540                                       enum intel_display_power_domain domain);
1541 void intel_display_power_get(struct drm_i915_private *dev_priv,
1542                              enum intel_display_power_domain domain);
1543 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1544                                         enum intel_display_power_domain domain);
1545 void intel_display_power_put(struct drm_i915_private *dev_priv,
1546                              enum intel_display_power_domain domain);
1547
1548 static inline void
1549 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1550 {
1551         WARN_ONCE(dev_priv->pm.suspended,
1552                   "Device suspended during HW access\n");
1553 }
1554
1555 static inline void
1556 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1557 {
1558         assert_rpm_device_not_suspended(dev_priv);
1559         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1560          * too much noise. */
1561         if (!atomic_read(&dev_priv->pm.wakeref_count))
1562                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1563 }
1564
1565 static inline int
1566 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1567 {
1568         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1569
1570         assert_rpm_wakelock_held(dev_priv);
1571
1572         return seq;
1573 }
1574
1575 static inline void
1576 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1577 {
1578         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1579                   "HW access outside of RPM atomic section\n");
1580 }
1581
1582 /**
1583  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1584  * @dev_priv: i915 device instance
1585  *
1586  * This function disable asserts that check if we hold an RPM wakelock
1587  * reference, while keeping the device-not-suspended checks still enabled.
1588  * It's meant to be used only in special circumstances where our rule about
1589  * the wakelock refcount wrt. the device power state doesn't hold. According
1590  * to this rule at any point where we access the HW or want to keep the HW in
1591  * an active state we must hold an RPM wakelock reference acquired via one of
1592  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1593  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1594  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1595  * users should avoid using this function.
1596  *
1597  * Any calls to this function must have a symmetric call to
1598  * enable_rpm_wakeref_asserts().
1599  */
1600 static inline void
1601 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1602 {
1603         atomic_inc(&dev_priv->pm.wakeref_count);
1604 }
1605
1606 /**
1607  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1608  * @dev_priv: i915 device instance
1609  *
1610  * This function re-enables the RPM assert checks after disabling them with
1611  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1612  * circumstances otherwise its use should be avoided.
1613  *
1614  * Any calls to this function must have a symmetric call to
1615  * disable_rpm_wakeref_asserts().
1616  */
1617 static inline void
1618 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1619 {
1620         atomic_dec(&dev_priv->pm.wakeref_count);
1621 }
1622
1623 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1624 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1625         disable_rpm_wakeref_asserts(dev_priv)
1626
1627 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1628         enable_rpm_wakeref_asserts(dev_priv)
1629
1630 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1631 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1632 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1633 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1634
1635 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1636
1637 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1638                              bool override, unsigned int mask);
1639 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1640                           enum dpio_channel ch, bool override);
1641
1642
1643 /* intel_pm.c */
1644 void intel_init_clock_gating(struct drm_device *dev);
1645 void intel_suspend_hw(struct drm_device *dev);
1646 int ilk_wm_max_level(const struct drm_device *dev);
1647 void intel_update_watermarks(struct drm_crtc *crtc);
1648 void intel_init_pm(struct drm_device *dev);
1649 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1650 void intel_pm_setup(struct drm_device *dev);
1651 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1652 void intel_gpu_ips_teardown(void);
1653 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1654 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1655 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1656 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1657 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1658 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1659 void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1660 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1661 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1662 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1663 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1664                     struct intel_rps_client *rps,
1665                     unsigned long submitted);
1666 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1667 void vlv_wm_get_hw_state(struct drm_device *dev);
1668 void ilk_wm_get_hw_state(struct drm_device *dev);
1669 void skl_wm_get_hw_state(struct drm_device *dev);
1670 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1671                           struct skl_ddb_allocation *ddb /* out */);
1672 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1673 bool ilk_disable_lp_wm(struct drm_device *dev);
1674 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1675 static inline int intel_enable_rc6(void)
1676 {
1677         return i915.enable_rc6;
1678 }
1679
1680 /* intel_sdvo.c */
1681 bool intel_sdvo_init(struct drm_device *dev,
1682                      i915_reg_t reg, enum port port);
1683
1684
1685 /* intel_sprite.c */
1686 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1687 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1688                               struct drm_file *file_priv);
1689 void intel_pipe_update_start(struct intel_crtc *crtc);
1690 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1691
1692 /* intel_tv.c */
1693 void intel_tv_init(struct drm_device *dev);
1694
1695 /* intel_atomic.c */
1696 int intel_connector_atomic_get_property(struct drm_connector *connector,
1697                                         const struct drm_connector_state *state,
1698                                         struct drm_property *property,
1699                                         uint64_t *val);
1700 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1701 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1702                                struct drm_crtc_state *state);
1703 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1704 void intel_atomic_state_clear(struct drm_atomic_state *);
1705 struct intel_shared_dpll_config *
1706 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1707
1708 static inline struct intel_crtc_state *
1709 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1710                             struct intel_crtc *crtc)
1711 {
1712         struct drm_crtc_state *crtc_state;
1713         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1714         if (IS_ERR(crtc_state))
1715                 return ERR_CAST(crtc_state);
1716
1717         return to_intel_crtc_state(crtc_state);
1718 }
1719
1720 static inline struct intel_plane_state *
1721 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1722                                       struct intel_plane *plane)
1723 {
1724         struct drm_plane_state *plane_state;
1725
1726         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1727
1728         return to_intel_plane_state(plane_state);
1729 }
1730
1731 int intel_atomic_setup_scalers(struct drm_device *dev,
1732         struct intel_crtc *intel_crtc,
1733         struct intel_crtc_state *crtc_state);
1734
1735 /* intel_atomic_plane.c */
1736 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1737 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1738 void intel_plane_destroy_state(struct drm_plane *plane,
1739                                struct drm_plane_state *state);
1740 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1741
1742 /* intel_color.c */
1743 void intel_color_init(struct drm_crtc *crtc);
1744 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1745 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1746 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1747
1748 #endif /* __INTEL_DRV_H__ */