drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72 #define wait_for_us(COND, US)           _wait_for((COND), (US), 1)
  73
  74 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  75 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  76 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
  77 #else
  78 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
  79 #endif
  80
  81 #define _wait_for_atomic(COND, US) ({ \
  82         unsigned long end__; \
  83         int ret__ = 0; \
  84         _WAIT_FOR_ATOMIC_CHECK; \
  85         BUILD_BUG_ON((US) > 50000); \
  86         end__ = (local_clock() >> 10) + (US) + 1; \
  87         while (!(COND)) { \
  88                 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
  89                         /* Unlike the regular wait_for(), this atomic variant \
  90                          * cannot be preempted (and we'll just ignore the issue\
  91                          * of irq interruptions) and so we know that no time \
  92                          * has passed since the last check of COND and can \
  93                          * immediately report the timeout. \
  94                          */ \
  95                         ret__ = -ETIMEDOUT; \
  96                         break; \
  97                 } \
  98                 cpu_relax(); \
  99         } \
 100         ret__; \
 101 })
 102
 103 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000)
 104 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US))
 105
 106 #define KHz(x) (1000 * (x))
 107 #define MHz(x) KHz(1000 * (x))
 108
 109 /*
 110  * Display related stuff
 111  */
 112
 113 /* store information about an Ixxx DVO */
 114 /* The i830->i865 use multiple DVOs with multiple i2cs */
 115 /* the i915, i945 have a single sDVO i2c bus - which is different */
 116 #define MAX_OUTPUTS 6
 117 /* maximum connectors per crtcs in the mode set */
 118
 119 /* Maximum cursor sizes */
 120 #define GEN2_CURSOR_WIDTH 64
 121 #define GEN2_CURSOR_HEIGHT 64
 122 #define MAX_CURSOR_WIDTH 256
 123 #define MAX_CURSOR_HEIGHT 256
 124
 125 #define INTEL_I2C_BUS_DVO 1
 126 #define INTEL_I2C_BUS_SDVO 2
 127
 128 /* these are outputs from the chip - integrated only
 129    external chips are via DVO or SDVO output */
 130 enum intel_output_type {
 131         INTEL_OUTPUT_UNUSED = 0,
 132         INTEL_OUTPUT_ANALOG = 1,
 133         INTEL_OUTPUT_DVO = 2,
 134         INTEL_OUTPUT_SDVO = 3,
 135         INTEL_OUTPUT_LVDS = 4,
 136         INTEL_OUTPUT_TVOUT = 5,
 137         INTEL_OUTPUT_HDMI = 6,
 138         INTEL_OUTPUT_DISPLAYPORT = 7,
 139         INTEL_OUTPUT_EDP = 8,
 140         INTEL_OUTPUT_DSI = 9,
 141         INTEL_OUTPUT_UNKNOWN = 10,
 142         INTEL_OUTPUT_DP_MST = 11,
 143 };
 144
 145 #define INTEL_DVO_CHIP_NONE 0
 146 #define INTEL_DVO_CHIP_LVDS 1
 147 #define INTEL_DVO_CHIP_TMDS 2
 148 #define INTEL_DVO_CHIP_TVOUT 4
 149
 150 #define INTEL_DSI_VIDEO_MODE    0
 151 #define INTEL_DSI_COMMAND_MODE  1
 152
 153 struct intel_framebuffer {
 154         struct drm_framebuffer base;
 155         struct drm_i915_gem_object *obj;
 156         struct intel_rotation_info rot_info;
 157 };
 158
 159 struct intel_fbdev {
 160         struct drm_fb_helper helper;
 161         struct intel_framebuffer *fb;
 162         int preferred_bpp;
 163 };
 164
 165 struct intel_encoder {
 166         struct drm_encoder base;
 167
 168         enum intel_output_type type;
 169         unsigned int cloneable;
 170         void (*hot_plug)(struct intel_encoder *);
 171         bool (*compute_config)(struct intel_encoder *,
 172                                struct intel_crtc_state *);
 173         void (*pre_pll_enable)(struct intel_encoder *);
 174         void (*pre_enable)(struct intel_encoder *);
 175         void (*enable)(struct intel_encoder *);
 176         void (*mode_set)(struct intel_encoder *intel_encoder);
 177         void (*disable)(struct intel_encoder *);
 178         void (*post_disable)(struct intel_encoder *);
 179         void (*post_pll_disable)(struct intel_encoder *);
 180         /* Read out the current hw state of this connector, returning true if
 181          * the encoder is active. If the encoder is enabled it also set the pipe
 182          * it is connected to in the pipe parameter. */
 183         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 184         /* Reconstructs the equivalent mode flags for the current hardware
 185          * state. This must be called _after_ display->get_pipe_config has
 186          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 187          * be set correctly before calling this function. */
 188         void (*get_config)(struct intel_encoder *,
 189                            struct intel_crtc_state *pipe_config);
 190         /*
 191          * Called during system suspend after all pending requests for the
 192          * encoder are flushed (for example for DP AUX transactions) and
 193          * device interrupts are disabled.
 194          */
 195         void (*suspend)(struct intel_encoder *);
 196         int crtc_mask;
 197         enum hpd_pin hpd_pin;
 198 };
 199
 200 struct intel_panel {
 201         struct drm_display_mode *fixed_mode;
 202         struct drm_display_mode *downclock_mode;
 203         int fitting_mode;
 204
 205         /* backlight */
 206         struct {
 207                 bool present;
 208                 u32 level;
 209                 u32 min;
 210                 u32 max;
 211                 bool enabled;
 212                 bool combination_mode;  /* gen 2/4 only */
 213                 bool active_low_pwm;
 214
 215                 /* PWM chip */
 216                 bool util_pin_active_low;       /* bxt+ */
 217                 u8 controller;          /* bxt+ only */
 218                 struct pwm_device *pwm;
 219
 220                 struct backlight_device *device;
 221
 222                 /* Connector and platform specific backlight functions */
 223                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 224                 uint32_t (*get)(struct intel_connector *connector);
 225                 void (*set)(struct intel_connector *connector, uint32_t level);
 226                 void (*disable)(struct intel_connector *connector);
 227                 void (*enable)(struct intel_connector *connector);
 228                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 229                                       uint32_t hz);
 230                 void (*power)(struct intel_connector *, bool enable);
 231         } backlight;
 232 };
 233
 234 struct intel_connector {
 235         struct drm_connector base;
 236         /*
 237          * The fixed encoder this connector is connected to.
 238          */
 239         struct intel_encoder *encoder;
 240
 241         /* Reads out the current hw, returning true if the connector is enabled
 242          * and active (i.e. dpms ON state). */
 243         bool (*get_hw_state)(struct intel_connector *);
 244
 245         /*
 246          * Removes all interfaces through which the connector is accessible
 247          * - like sysfs, debugfs entries -, so that no new operations can be
 248          * started on the connector. Also makes sure all currently pending
 249          * operations finish before returing.
 250          */
 251         void (*unregister)(struct intel_connector *);
 252
 253         /* Panel info for eDP and LVDS */
 254         struct intel_panel panel;
 255
 256         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 257         struct edid *edid;
 258         struct edid *detect_edid;
 259
 260         /* since POLL and HPD connectors may use the same HPD line keep the native
 261            state of connector->polled in case hotplug storm detection changes it */
 262         u8 polled;
 263
 264         void *port; /* store this opaque as its illegal to dereference it */
 265
 266         struct intel_dp *mst_port;
 267 };
 268
 269 struct dpll {
 270         /* given values */
 271         int n;
 272         int m1, m2;
 273         int p1, p2;
 274         /* derived values */
 275         int     dot;
 276         int     vco;
 277         int     m;
 278         int     p;
 279 };
 280
 281 struct intel_atomic_state {
 282         struct drm_atomic_state base;
 283
 284         unsigned int cdclk;
 285
 286         /*
 287          * Calculated device cdclk, can be different from cdclk
 288          * only when all crtc's are DPMS off.
 289          */
 290         unsigned int dev_cdclk;
 291
 292         bool dpll_set, modeset;
 293
 294         /*
 295          * Does this transaction change the pipes that are active?  This mask
 296          * tracks which CRTC's have changed their active state at the end of
 297          * the transaction (not counting the temporary disable during modesets).
 298          * This mask should only be non-zero when intel_state->modeset is true,
 299          * but the converse is not necessarily true; simply changing a mode may
 300          * not flip the final active status of any CRTC's
 301          */
 302         unsigned int active_pipe_changes;
 303
 304         unsigned int active_crtcs;
 305         unsigned int min_pixclk[I915_MAX_PIPES];
 306
 307         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 308
 309         /*
 310          * Current watermarks can't be trusted during hardware readout, so
 311          * don't bother calculating intermediate watermarks.
 312          */
 313         bool skip_intermediate_wm;
 314
 315         /* Gen9+ only */
 316         struct skl_wm_values wm_results;
 317 };
 318
 319 struct intel_plane_state {
 320         struct drm_plane_state base;
 321         struct drm_rect src;
 322         struct drm_rect dst;
 323         struct drm_rect clip;
 324         bool visible;
 325
 326         /*
 327          * scaler_id
 328          *    = -1 : not using a scaler
 329          *    >=  0 : using a scalers
 330          *
 331          * plane requiring a scaler:
 332          *   - During check_plane, its bit is set in
 333          *     crtc_state->scaler_state.scaler_users by calling helper function
 334          *     update_scaler_plane.
 335          *   - scaler_id indicates the scaler it got assigned.
 336          *
 337          * plane doesn't require a scaler:
 338          *   - this can happen when scaling is no more required or plane simply
 339          *     got disabled.
 340          *   - During check_plane, corresponding bit is reset in
 341          *     crtc_state->scaler_state.scaler_users by calling helper function
 342          *     update_scaler_plane.
 343          */
 344         int scaler_id;
 345
 346         struct drm_intel_sprite_colorkey ckey;
 347
 348         /* async flip related structures */
 349         struct drm_i915_gem_request *wait_req;
 350 };
 351
 352 struct intel_initial_plane_config {
 353         struct intel_framebuffer *fb;
 354         unsigned int tiling;
 355         int size;
 356         u32 base;
 357 };
 358
 359 #define SKL_MIN_SRC_W 8
 360 #define SKL_MAX_SRC_W 4096
 361 #define SKL_MIN_SRC_H 8
 362 #define SKL_MAX_SRC_H 4096
 363 #define SKL_MIN_DST_W 8
 364 #define SKL_MAX_DST_W 4096
 365 #define SKL_MIN_DST_H 8
 366 #define SKL_MAX_DST_H 4096
 367
 368 struct intel_scaler {
 369         int in_use;
 370         uint32_t mode;
 371 };
 372
 373 struct intel_crtc_scaler_state {
 374 #define SKL_NUM_SCALERS 2
 375         struct intel_scaler scalers[SKL_NUM_SCALERS];
 376
 377         /*
 378          * scaler_users: keeps track of users requesting scalers on this crtc.
 379          *
 380          *     If a bit is set, a user is using a scaler.
 381          *     Here user can be a plane or crtc as defined below:
 382          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 383          *       bit 31    - crtc
 384          *
 385          * Instead of creating a new index to cover planes and crtc, using
 386          * existing drm_plane_index for planes which is well less than 31
 387          * planes and bit 31 for crtc. This should be fine to cover all
 388          * our platforms.
 389          *
 390          * intel_atomic_setup_scalers will setup available scalers to users
 391          * requesting scalers. It will gracefully fail if request exceeds
 392          * avilability.
 393          */
 394 #define SKL_CRTC_INDEX 31
 395         unsigned scaler_users;
 396
 397         /* scaler used by crtc for panel fitting purpose */
 398         int scaler_id;
 399 };
 400
 401 /* drm_mode->private_flags */
 402 #define I915_MODE_FLAG_INHERITED 1
 403
 404 struct intel_pipe_wm {
 405         struct intel_wm_level wm[5];
 406         struct intel_wm_level raw_wm[5];
 407         uint32_t linetime;
 408         bool fbc_wm_enabled;
 409         bool pipe_enabled;
 410         bool sprites_enabled;
 411         bool sprites_scaled;
 412 };
 413
 414 struct skl_pipe_wm {
 415         struct skl_wm_level wm[8];
 416         struct skl_wm_level trans_wm;
 417         uint32_t linetime;
 418 };
 419
 420 struct intel_crtc_wm_state {
 421         union {
 422                 struct {
 423                         /*
 424                          * Intermediate watermarks; these can be
 425                          * programmed immediately since they satisfy
 426                          * both the current configuration we're
 427                          * switching away from and the new
 428                          * configuration we're switching to.
 429                          */
 430                         struct intel_pipe_wm intermediate;
 431
 432                         /*
 433                          * Optimal watermarks, programmed post-vblank
 434                          * when this state is committed.
 435                          */
 436                         struct intel_pipe_wm optimal;
 437                 } ilk;
 438
 439                 struct {
 440                         /* gen9+ only needs 1-step wm programming */
 441                         struct skl_pipe_wm optimal;
 442
 443                         /* cached plane data rate */
 444                         unsigned plane_data_rate[I915_MAX_PLANES];
 445                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 446
 447                         /* minimum block allocation */
 448                         uint16_t minimum_blocks[I915_MAX_PLANES];
 449                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 450                 } skl;
 451         };
 452
 453         /*
 454          * Platforms with two-step watermark programming will need to
 455          * update watermark programming post-vblank to switch from the
 456          * safe intermediate watermarks to the optimal final
 457          * watermarks.
 458          */
 459         bool need_postvbl_update;
 460 };
 461
 462 struct intel_crtc_state {
 463         struct drm_crtc_state base;
 464
 465         /**
 466          * quirks - bitfield with hw state readout quirks
 467          *
 468          * For various reasons the hw state readout code might not be able to
 469          * completely faithfully read out the current state. These cases are
 470          * tracked with quirk flags so that fastboot and state checker can act
 471          * accordingly.
 472          */
 473 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 474         unsigned long quirks;
 475
 476         unsigned fb_bits; /* framebuffers to flip */
 477         bool update_pipe; /* can a fast modeset be performed? */
 478         bool disable_cxsr;
 479         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 480         bool fb_changed; /* fb on any of the planes is changed */
 481
 482         /* Pipe source size (ie. panel fitter input size)
 483          * All planes will be positioned inside this space,
 484          * and get clipped at the edges. */
 485         int pipe_src_w, pipe_src_h;
 486
 487         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 488          * between pch encoders and cpu encoders. */
 489         bool has_pch_encoder;
 490
 491         /* Are we sending infoframes on the attached port */
 492         bool has_infoframe;
 493
 494         /* CPU Transcoder for the pipe. Currently this can only differ from the
 495          * pipe on Haswell and later (where we have a special eDP transcoder)
 496          * and Broxton (where we have special DSI transcoders). */
 497         enum transcoder cpu_transcoder;
 498
 499         /*
 500          * Use reduced/limited/broadcast rbg range, compressing from the full
 501          * range fed into the crtcs.
 502          */
 503         bool limited_color_range;
 504
 505         /* DP has a bunch of special case unfortunately, so mark the pipe
 506          * accordingly. */
 507         bool has_dp_encoder;
 508
 509         /* DSI has special cases */
 510         bool has_dsi_encoder;
 511
 512         /* Whether we should send NULL infoframes. Required for audio. */
 513         bool has_hdmi_sink;
 514
 515         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 516          * has_dp_encoder is set. */
 517         bool has_audio;
 518
 519         /*
 520          * Enable dithering, used when the selected pipe bpp doesn't match the
 521          * plane bpp.
 522          */
 523         bool dither;
 524
 525         /* Controls for the clock computation, to override various stages. */
 526         bool clock_set;
 527
 528         /* SDVO TV has a bunch of special case. To make multifunction encoders
 529          * work correctly, we need to track this at runtime.*/
 530         bool sdvo_tv_clock;
 531
 532         /*
 533          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 534          * required. This is set in the 2nd loop of calling encoder's
 535          * ->compute_config if the first pick doesn't work out.
 536          */
 537         bool bw_constrained;
 538
 539         /* Settings for the intel dpll used on pretty much everything but
 540          * haswell. */
 541         struct dpll dpll;
 542
 543         /* Selected dpll when shared or NULL. */
 544         struct intel_shared_dpll *shared_dpll;
 545
 546         /*
 547          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 548          * - enum skl_dpll on SKL
 549          */
 550         uint32_t ddi_pll_sel;
 551
 552         /* Actual register state of the dpll, for shared dpll cross-checking. */
 553         struct intel_dpll_hw_state dpll_hw_state;
 554
 555         /* DSI PLL registers */
 556         struct {
 557                 u32 ctrl, div;
 558         } dsi_pll;
 559
 560         int pipe_bpp;
 561         struct intel_link_m_n dp_m_n;
 562
 563         /* m2_n2 for eDP downclock */
 564         struct intel_link_m_n dp_m2_n2;
 565         bool has_drrs;
 566
 567         /*
 568          * Frequence the dpll for the port should run at. Differs from the
 569          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 570          * already multiplied by pixel_multiplier.
 571          */
 572         int port_clock;
 573
 574         /* Used by SDVO (and if we ever fix it, HDMI). */
 575         unsigned pixel_multiplier;
 576
 577         uint8_t lane_count;
 578
 579         /* Panel fitter controls for gen2-gen4 + VLV */
 580         struct {
 581                 u32 control;
 582                 u32 pgm_ratios;
 583                 u32 lvds_border_bits;
 584         } gmch_pfit;
 585
 586         /* Panel fitter placement and size for Ironlake+ */
 587         struct {
 588                 u32 pos;
 589                 u32 size;
 590                 bool enabled;
 591                 bool force_thru;
 592         } pch_pfit;
 593
 594         /* FDI configuration, only valid if has_pch_encoder is set. */
 595         int fdi_lanes;
 596         struct intel_link_m_n fdi_m_n;
 597
 598         bool ips_enabled;
 599
 600         bool enable_fbc;
 601
 602         bool double_wide;
 603
 604         bool dp_encoder_is_mst;
 605         int pbn;
 606
 607         struct intel_crtc_scaler_state scaler_state;
 608
 609         /* w/a for waiting 2 vblanks during crtc enable */
 610         enum pipe hsw_workaround_pipe;
 611
 612         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 613         bool disable_lp_wm;
 614
 615         struct intel_crtc_wm_state wm;
 616
 617         /* Gamma mode programmed on the pipe */
 618         uint32_t gamma_mode;
 619 };
 620
 621 struct vlv_wm_state {
 622         struct vlv_pipe_wm wm[3];
 623         struct vlv_sr_wm sr[3];
 624         uint8_t num_active_planes;
 625         uint8_t num_levels;
 626         uint8_t level;
 627         bool cxsr;
 628 };
 629
 630 struct intel_crtc {
 631         struct drm_crtc base;
 632         enum pipe pipe;
 633         enum plane plane;
 634         u8 lut_r[256], lut_g[256], lut_b[256];
 635         /*
 636          * Whether the crtc and the connected output pipeline is active. Implies
 637          * that crtc->enabled is set, i.e. the current mode configuration has
 638          * some outputs connected to this crtc.
 639          */
 640         bool active;
 641         unsigned long enabled_power_domains;
 642         bool lowfreq_avail;
 643         struct intel_overlay *overlay;
 644         struct intel_flip_work *flip_work;
 645
 646         atomic_t unpin_work_count;
 647
 648         /* Display surface base address adjustement for pageflips. Note that on
 649          * gen4+ this only adjusts up to a tile, offsets within a tile are
 650          * handled in the hw itself (with the TILEOFF register). */
 651         u32 dspaddr_offset;
 652         int adjusted_x;
 653         int adjusted_y;
 654
 655         uint32_t cursor_addr;
 656         uint32_t cursor_cntl;
 657         uint32_t cursor_size;
 658         uint32_t cursor_base;
 659
 660         struct intel_crtc_state *config;
 661
 662         /* reset counter value when the last flip was submitted */
 663         unsigned int reset_counter;
 664
 665         /* Access to these should be protected by dev_priv->irq_lock. */
 666         bool cpu_fifo_underrun_disabled;
 667         bool pch_fifo_underrun_disabled;
 668
 669         /* per-pipe watermark state */
 670         struct {
 671                 /* watermarks currently being used  */
 672                 union {
 673                         struct intel_pipe_wm ilk;
 674                         struct skl_pipe_wm skl;
 675                 } active;
 676
 677                 /* allow CxSR on this pipe */
 678                 bool cxsr_allowed;
 679         } wm;
 680
 681         int scanline_offset;
 682
 683         struct {
 684                 unsigned start_vbl_count;
 685                 ktime_t start_vbl_time;
 686                 int min_vbl, max_vbl;
 687                 int scanline_start;
 688         } debug;
 689
 690         /* scalers available on this crtc */
 691         int num_scalers;
 692
 693         struct vlv_wm_state wm_state;
 694 };
 695
 696 struct intel_plane_wm_parameters {
 697         uint32_t horiz_pixels;
 698         uint32_t vert_pixels;
 699         /*
 700          *   For packed pixel formats:
 701          *     bytes_per_pixel - holds bytes per pixel
 702          *   For planar pixel formats:
 703          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 704          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 705          */
 706         uint8_t bytes_per_pixel;
 707         uint8_t y_bytes_per_pixel;
 708         bool enabled;
 709         bool scaled;
 710         u64 tiling;
 711         unsigned int rotation;
 712         uint16_t fifo_size;
 713 };
 714
 715 struct intel_plane {
 716         struct drm_plane base;
 717         int plane;
 718         enum pipe pipe;
 719         bool can_scale;
 720         int max_downscale;
 721         uint32_t frontbuffer_bit;
 722
 723         /* Since we need to change the watermarks before/after
 724          * enabling/disabling the planes, we need to store the parameters here
 725          * as the other pieces of the struct may not reflect the values we want
 726          * for the watermark calculations. Currently only Haswell uses this.
 727          */
 728         struct intel_plane_wm_parameters wm;
 729
 730         /*
 731          * NOTE: Do not place new plane state fields here (e.g., when adding
 732          * new plane properties).  New runtime state should now be placed in
 733          * the intel_plane_state structure and accessed via plane_state.
 734          */
 735
 736         void (*update_plane)(struct drm_plane *plane,
 737                              const struct intel_crtc_state *crtc_state,
 738                              const struct intel_plane_state *plane_state);
 739         void (*disable_plane)(struct drm_plane *plane,
 740                               struct drm_crtc *crtc);
 741         int (*check_plane)(struct drm_plane *plane,
 742                            struct intel_crtc_state *crtc_state,
 743                            struct intel_plane_state *state);
 744 };
 745
 746 struct intel_watermark_params {
 747         unsigned long fifo_size;
 748         unsigned long max_wm;
 749         unsigned long default_wm;
 750         unsigned long guard_size;
 751         unsigned long cacheline_size;
 752 };
 753
 754 struct cxsr_latency {
 755         int is_desktop;
 756         int is_ddr3;
 757         unsigned long fsb_freq;
 758         unsigned long mem_freq;
 759         unsigned long display_sr;
 760         unsigned long display_hpll_disable;
 761         unsigned long cursor_sr;
 762         unsigned long cursor_hpll_disable;
 763 };
 764
 765 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 766 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 767 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 768 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 769 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 770 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 771 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 772 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 773 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 774
 775 struct intel_hdmi {
 776         i915_reg_t hdmi_reg;
 777         int ddc_bus;
 778         struct {
 779                 enum drm_dp_dual_mode_type type;
 780                 int max_tmds_clock;
 781         } dp_dual_mode;
 782         bool limited_color_range;
 783         bool color_range_auto;
 784         bool has_hdmi_sink;
 785         bool has_audio;
 786         enum hdmi_force_audio force_audio;
 787         bool rgb_quant_range_selectable;
 788         enum hdmi_picture_aspect aspect_ratio;
 789         struct intel_connector *attached_connector;
 790         void (*write_infoframe)(struct drm_encoder *encoder,
 791                                 enum hdmi_infoframe_type type,
 792                                 const void *frame, ssize_t len);
 793         void (*set_infoframes)(struct drm_encoder *encoder,
 794                                bool enable,
 795                                const struct drm_display_mode *adjusted_mode);
 796         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 797                                   const struct intel_crtc_state *pipe_config);
 798 };
 799
 800 struct intel_dp_mst_encoder;
 801 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 802
 803 /*
 804  * enum link_m_n_set:
 805  *      When platform provides two set of M_N registers for dp, we can
 806  *      program them and switch between them incase of DRRS.
 807  *      But When only one such register is provided, we have to program the
 808  *      required divider value on that registers itself based on the DRRS state.
 809  *
 810  * M1_N1        : Program dp_m_n on M1_N1 registers
 811  *                        dp_m2_n2 on M2_N2 registers (If supported)
 812  *
 813  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 814  *                        M2_N2 registers are not supported
 815  */
 816
 817 enum link_m_n_set {
 818         /* Sets the m1_n1 and m2_n2 */
 819         M1_N1 = 0,
 820         M2_N2
 821 };
 822
 823 struct intel_dp {
 824         i915_reg_t output_reg;
 825         i915_reg_t aux_ch_ctl_reg;
 826         i915_reg_t aux_ch_data_reg[5];
 827         uint32_t DP;
 828         int link_rate;
 829         uint8_t lane_count;
 830         uint8_t sink_count;
 831         bool has_audio;
 832         bool detect_done;
 833         enum hdmi_force_audio force_audio;
 834         bool limited_color_range;
 835         bool color_range_auto;
 836         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 837         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 838         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 839         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 840         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 841         uint8_t num_sink_rates;
 842         int sink_rates[DP_MAX_SUPPORTED_RATES];
 843         struct drm_dp_aux aux;
 844         uint8_t train_set[4];
 845         int panel_power_up_delay;
 846         int panel_power_down_delay;
 847         int panel_power_cycle_delay;
 848         int backlight_on_delay;
 849         int backlight_off_delay;
 850         struct delayed_work panel_vdd_work;
 851         bool want_panel_vdd;
 852         unsigned long last_power_on;
 853         unsigned long last_backlight_off;
 854         ktime_t panel_power_off_time;
 855
 856         struct notifier_block edp_notifier;
 857
 858         /*
 859          * Pipe whose power sequencer is currently locked into
 860          * this port. Only relevant on VLV/CHV.
 861          */
 862         enum pipe pps_pipe;
 863         struct edp_power_seq pps_delays;
 864
 865         bool can_mst; /* this port supports mst */
 866         bool is_mst;
 867         int active_mst_links;
 868         /* connector directly attached - won't be use for modeset in mst world */
 869         struct intel_connector *attached_connector;
 870
 871         /* mst connector list */
 872         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 873         struct drm_dp_mst_topology_mgr mst_mgr;
 874
 875         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 876         /*
 877          * This function returns the value we have to program the AUX_CTL
 878          * register with to kick off an AUX transaction.
 879          */
 880         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 881                                      bool has_aux_irq,
 882                                      int send_bytes,
 883                                      uint32_t aux_clock_divider);
 884
 885         /* This is called before a link training is starterd */
 886         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 887
 888         bool train_set_valid;
 889
 890         /* Displayport compliance testing */
 891         unsigned long compliance_test_type;
 892         unsigned long compliance_test_data;
 893         bool compliance_test_active;
 894 };
 895
 896 struct intel_digital_port {
 897         struct intel_encoder base;
 898         enum port port;
 899         u32 saved_port_bits;
 900         struct intel_dp dp;
 901         struct intel_hdmi hdmi;
 902         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 903         bool release_cl2_override;
 904         uint8_t max_lanes;
 905         /* for communication with audio component; protected by av_mutex */
 906         const struct drm_connector *audio_connector;
 907 };
 908
 909 struct intel_dp_mst_encoder {
 910         struct intel_encoder base;
 911         enum pipe pipe;
 912         struct intel_digital_port *primary;
 913         struct intel_connector *connector;
 914 };
 915
 916 static inline enum dpio_channel
 917 vlv_dport_to_channel(struct intel_digital_port *dport)
 918 {
 919         switch (dport->port) {
 920         case PORT_B:
 921         case PORT_D:
 922                 return DPIO_CH0;
 923         case PORT_C:
 924                 return DPIO_CH1;
 925         default:
 926                 BUG();
 927         }
 928 }
 929
 930 static inline enum dpio_phy
 931 vlv_dport_to_phy(struct intel_digital_port *dport)
 932 {
 933         switch (dport->port) {
 934         case PORT_B:
 935         case PORT_C:
 936                 return DPIO_PHY0;
 937         case PORT_D:
 938                 return DPIO_PHY1;
 939         default:
 940                 BUG();
 941         }
 942 }
 943
 944 static inline enum dpio_channel
 945 vlv_pipe_to_channel(enum pipe pipe)
 946 {
 947         switch (pipe) {
 948         case PIPE_A:
 949         case PIPE_C:
 950                 return DPIO_CH0;
 951         case PIPE_B:
 952                 return DPIO_CH1;
 953         default:
 954                 BUG();
 955         }
 956 }
 957
 958 static inline struct drm_crtc *
 959 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 960 {
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         return dev_priv->pipe_to_crtc_mapping[pipe];
 963 }
 964
 965 static inline struct drm_crtc *
 966 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 967 {
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         return dev_priv->plane_to_crtc_mapping[plane];
 970 }
 971
 972 struct intel_flip_work {
 973         struct work_struct unpin_work;
 974         struct work_struct mmio_work;
 975
 976         struct drm_crtc *crtc;
 977         struct drm_framebuffer *old_fb;
 978         struct drm_i915_gem_object *pending_flip_obj;
 979         struct drm_pending_vblank_event *event;
 980         atomic_t pending;
 981         u32 flip_count;
 982         u32 gtt_offset;
 983         struct drm_i915_gem_request *flip_queued_req;
 984         u32 flip_queued_vblank;
 985         u32 flip_ready_vblank;
 986         unsigned int rotation;
 987 };
 988
 989 struct intel_load_detect_pipe {
 990         struct drm_atomic_state *restore_state;
 991 };
 992
 993 static inline struct intel_encoder *
 994 intel_attached_encoder(struct drm_connector *connector)
 995 {
 996         return to_intel_connector(connector)->encoder;
 997 }
 998
 999 static inline struct intel_digital_port *
1000 enc_to_dig_port(struct drm_encoder *encoder)
1001 {
1002         return container_of(encoder, struct intel_digital_port, base.base);
1003 }
1004
1005 static inline struct intel_dp_mst_encoder *
1006 enc_to_mst(struct drm_encoder *encoder)
1007 {
1008         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1009 }
1010
1011 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1012 {
1013         return &enc_to_dig_port(encoder)->dp;
1014 }
1015
1016 static inline struct intel_digital_port *
1017 dp_to_dig_port(struct intel_dp *intel_dp)
1018 {
1019         return container_of(intel_dp, struct intel_digital_port, dp);
1020 }
1021
1022 static inline struct intel_digital_port *
1023 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1024 {
1025         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1026 }
1027
1028 /*
1029  * Returns the number of planes for this pipe, ie the number of sprites + 1
1030  * (primary plane). This doesn't count the cursor plane then.
1031  */
1032 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1033 {
1034         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1035 }
1036
1037 /* intel_fifo_underrun.c */
1038 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1039                                            enum pipe pipe, bool enable);
1040 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1041                                            enum transcoder pch_transcoder,
1042                                            bool enable);
1043 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1044                                          enum pipe pipe);
1045 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1046                                          enum transcoder pch_transcoder);
1047 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1048 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1049
1050 /* i915_irq.c */
1051 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1052 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1053 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1054 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1055 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1056 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1057 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1058 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1059 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1060 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1061 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1062 {
1063         /*
1064          * We only use drm_irq_uninstall() at unload and VT switch, so
1065          * this is the only thing we need to check.
1066          */
1067         return dev_priv->pm.irqs_enabled;
1068 }
1069
1070 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1071 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1072                                      unsigned int pipe_mask);
1073 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1074                                      unsigned int pipe_mask);
1075
1076 /* intel_crt.c */
1077 void intel_crt_init(struct drm_device *dev);
1078
1079
1080 /* intel_ddi.c */
1081 void intel_ddi_clk_select(struct intel_encoder *encoder,
1082                           const struct intel_crtc_state *pipe_config);
1083 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1084 void hsw_fdi_link_train(struct drm_crtc *crtc);
1085 void intel_ddi_init(struct drm_device *dev, enum port port);
1086 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1087 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1088 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1089 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1090                                        enum transcoder cpu_transcoder);
1091 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1092 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1093 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1094                           struct intel_crtc_state *crtc_state);
1095 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1096 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1097 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1098 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1099 void intel_ddi_get_config(struct intel_encoder *encoder,
1100                           struct intel_crtc_state *pipe_config);
1101 struct intel_encoder *
1102 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1103
1104 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1105 void intel_ddi_clock_get(struct intel_encoder *encoder,
1106                          struct intel_crtc_state *pipe_config);
1107 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1108 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1109
1110 /* intel_frontbuffer.c */
1111 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1112                              enum fb_op_origin origin);
1113 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1114                                     unsigned frontbuffer_bits);
1115 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1116                                      unsigned frontbuffer_bits);
1117 void intel_frontbuffer_flip(struct drm_device *dev,
1118                             unsigned frontbuffer_bits);
1119 unsigned int intel_fb_align_height(struct drm_device *dev,
1120                                    unsigned int height,
1121                                    uint32_t pixel_format,
1122                                    uint64_t fb_format_modifier);
1123 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1124                         enum fb_op_origin origin);
1125 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1126                               uint64_t fb_modifier, uint32_t pixel_format);
1127
1128 /* intel_audio.c */
1129 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1130 void intel_audio_codec_enable(struct intel_encoder *encoder);
1131 void intel_audio_codec_disable(struct intel_encoder *encoder);
1132 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1133 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1134
1135 /* intel_display.c */
1136 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1137 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1138                       const char *name, u32 reg, int ref_freq);
1139 extern const struct drm_plane_funcs intel_plane_funcs;
1140 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1141 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1142 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1143 void intel_mark_busy(struct drm_i915_private *dev_priv);
1144 void intel_mark_idle(struct drm_i915_private *dev_priv);
1145 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1146 int intel_display_suspend(struct drm_device *dev);
1147 void intel_encoder_destroy(struct drm_encoder *encoder);
1148 int intel_connector_init(struct intel_connector *);
1149 struct intel_connector *intel_connector_alloc(void);
1150 bool intel_connector_get_hw_state(struct intel_connector *connector);
1151 void intel_connector_attach_encoder(struct intel_connector *connector,
1152                                     struct intel_encoder *encoder);
1153 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1154 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1155                                              struct drm_crtc *crtc);
1156 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1157 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1158                                 struct drm_file *file_priv);
1159 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1160                                              enum pipe pipe);
1161 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1162 static inline void
1163 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1164 {
1165         drm_wait_one_vblank(dev, pipe);
1166 }
1167 static inline void
1168 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1169 {
1170         const struct intel_crtc *crtc =
1171                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1172
1173         if (crtc->active)
1174                 intel_wait_for_vblank(dev, pipe);
1175 }
1176
1177 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1178
1179 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1180 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1181                          struct intel_digital_port *dport,
1182                          unsigned int expected_mask);
1183 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1184                                 struct drm_display_mode *mode,
1185                                 struct intel_load_detect_pipe *old,
1186                                 struct drm_modeset_acquire_ctx *ctx);
1187 void intel_release_load_detect_pipe(struct drm_connector *connector,
1188                                     struct intel_load_detect_pipe *old,
1189                                     struct drm_modeset_acquire_ctx *ctx);
1190 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1191                                unsigned int rotation);
1192 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1193 struct drm_framebuffer *
1194 __intel_framebuffer_create(struct drm_device *dev,
1195                            struct drm_mode_fb_cmd2 *mode_cmd,
1196                            struct drm_i915_gem_object *obj);
1197 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1198 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1199 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1200 int intel_prepare_plane_fb(struct drm_plane *plane,
1201                            const struct drm_plane_state *new_state);
1202 void intel_cleanup_plane_fb(struct drm_plane *plane,
1203                             const struct drm_plane_state *old_state);
1204 int intel_plane_atomic_get_property(struct drm_plane *plane,
1205                                     const struct drm_plane_state *state,
1206                                     struct drm_property *property,
1207                                     uint64_t *val);
1208 int intel_plane_atomic_set_property(struct drm_plane *plane,
1209                                     struct drm_plane_state *state,
1210                                     struct drm_property *property,
1211                                     uint64_t val);
1212 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1213                                     struct drm_plane_state *plane_state);
1214
1215 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1216                                uint64_t fb_modifier, unsigned int cpp);
1217
1218 static inline bool
1219 intel_rotation_90_or_270(unsigned int rotation)
1220 {
1221         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1222 }
1223
1224 void intel_create_rotation_property(struct drm_device *dev,
1225                                         struct intel_plane *plane);
1226
1227 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228                                     enum pipe pipe);
1229
1230 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1231                      const struct dpll *dpll);
1232 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1233 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1234
1235 /* modesetting asserts */
1236 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1237                            enum pipe pipe);
1238 void assert_pll(struct drm_i915_private *dev_priv,
1239                 enum pipe pipe, bool state);
1240 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1241 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1242 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1243 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1244 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1245 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1246                        enum pipe pipe, bool state);
1247 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1248 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1249 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1250 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1251 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1252 u32 intel_compute_tile_offset(int *x, int *y,
1253                               const struct drm_framebuffer *fb, int plane,
1254                               unsigned int pitch,
1255                               unsigned int rotation);
1256 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1257 void intel_finish_reset(struct drm_i915_private *dev_priv);
1258 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1259 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1260 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
1261 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
1262 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
1263 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
1264 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
1265 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
1266 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1267 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1268 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1269 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1270 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1271 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1272 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1273 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1274 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1275 void intel_dp_get_m_n(struct intel_crtc *crtc,
1276                       struct intel_crtc_state *pipe_config);
1277 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1278 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1279 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1280                         struct dpll *best_clock);
1281 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1282
1283 bool intel_crtc_active(struct drm_crtc *crtc);
1284 void hsw_enable_ips(struct intel_crtc *crtc);
1285 void hsw_disable_ips(struct intel_crtc *crtc);
1286 enum intel_display_power_domain
1287 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1288 enum intel_display_power_domain
1289 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1290 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1291                                  struct intel_crtc_state *pipe_config);
1292
1293 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1294 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1295
1296 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1297                            struct drm_i915_gem_object *obj,
1298                            unsigned int plane);
1299
1300 u32 skl_plane_ctl_format(uint32_t pixel_format);
1301 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1302 u32 skl_plane_ctl_rotation(unsigned int rotation);
1303
1304 /* intel_csr.c */
1305 void intel_csr_ucode_init(struct drm_i915_private *);
1306 void intel_csr_load_program(struct drm_i915_private *);
1307 void intel_csr_ucode_fini(struct drm_i915_private *);
1308 void intel_csr_ucode_suspend(struct drm_i915_private *);
1309 void intel_csr_ucode_resume(struct drm_i915_private *);
1310
1311 /* intel_dp.c */
1312 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1313 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1314                              struct intel_connector *intel_connector);
1315 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1316                               const struct intel_crtc_state *pipe_config);
1317 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1318 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1319 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1320 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1321 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1322 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1323 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1324 bool intel_dp_compute_config(struct intel_encoder *encoder,
1325                              struct intel_crtc_state *pipe_config);
1326 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1327 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1328                                   bool long_hpd);
1329 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1330 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1331 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1332 void intel_edp_panel_on(struct intel_dp *intel_dp);
1333 void intel_edp_panel_off(struct intel_dp *intel_dp);
1334 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1335 void intel_dp_mst_suspend(struct drm_device *dev);
1336 void intel_dp_mst_resume(struct drm_device *dev);
1337 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1338 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1339 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1340 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1341 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1342 void intel_plane_destroy(struct drm_plane *plane);
1343 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1344 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1345 void intel_edp_drrs_invalidate(struct drm_device *dev,
1346                 unsigned frontbuffer_bits);
1347 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1348 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1349                                          struct intel_digital_port *port);
1350
1351 void
1352 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1353                                        uint8_t dp_train_pat);
1354 void
1355 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1356 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1357 uint8_t
1358 intel_dp_voltage_max(struct intel_dp *intel_dp);
1359 uint8_t
1360 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1361 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1362                            uint8_t *link_bw, uint8_t *rate_select);
1363 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1364 bool
1365 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1366
1367 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1368 {
1369         return ~((1 << lane_count) - 1) & 0xf;
1370 }
1371
1372 /* intel_dp_aux_backlight.c */
1373 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1374
1375 /* intel_dp_mst.c */
1376 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1377 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1378 /* intel_dsi.c */
1379 void intel_dsi_init(struct drm_device *dev);
1380
1381 /* intel_dsi_dcs_backlight.c */
1382 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1383
1384 /* intel_dvo.c */
1385 void intel_dvo_init(struct drm_device *dev);
1386
1387
1388 /* legacy fbdev emulation in intel_fbdev.c */
1389 #ifdef CONFIG_DRM_FBDEV_EMULATION
1390 extern int intel_fbdev_init(struct drm_device *dev);
1391 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1392 extern void intel_fbdev_fini(struct drm_device *dev);
1393 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1394 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1395 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1396 #else
1397 static inline int intel_fbdev_init(struct drm_device *dev)
1398 {
1399         return 0;
1400 }
1401
1402 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1403 {
1404 }
1405
1406 static inline void intel_fbdev_fini(struct drm_device *dev)
1407 {
1408 }
1409
1410 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1411 {
1412 }
1413
1414 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1415 {
1416 }
1417 #endif
1418
1419 /* intel_fbc.c */
1420 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1421                            struct drm_atomic_state *state);
1422 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1423 void intel_fbc_pre_update(struct intel_crtc *crtc);
1424 void intel_fbc_post_update(struct intel_crtc *crtc);
1425 void intel_fbc_init(struct drm_i915_private *dev_priv);
1426 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1427 void intel_fbc_enable(struct intel_crtc *crtc);
1428 void intel_fbc_disable(struct intel_crtc *crtc);
1429 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1430 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1431                           unsigned int frontbuffer_bits,
1432                           enum fb_op_origin origin);
1433 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1434                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1435 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1436
1437 /* intel_hdmi.c */
1438 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1439 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1440                                struct intel_connector *intel_connector);
1441 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1442 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1443                                struct intel_crtc_state *pipe_config);
1444 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1445
1446
1447 /* intel_lvds.c */
1448 void intel_lvds_init(struct drm_device *dev);
1449 bool intel_is_dual_link_lvds(struct drm_device *dev);
1450
1451
1452 /* intel_modes.c */
1453 int intel_connector_update_modes(struct drm_connector *connector,
1454                                  struct edid *edid);
1455 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1456 void intel_attach_force_audio_property(struct drm_connector *connector);
1457 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1458 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1459
1460
1461 /* intel_overlay.c */
1462 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1463 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1464 int intel_overlay_switch_off(struct intel_overlay *overlay);
1465 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1466                                   struct drm_file *file_priv);
1467 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1468                               struct drm_file *file_priv);
1469 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1470
1471
1472 /* intel_panel.c */
1473 int intel_panel_init(struct intel_panel *panel,
1474                      struct drm_display_mode *fixed_mode,
1475                      struct drm_display_mode *downclock_mode);
1476 void intel_panel_fini(struct intel_panel *panel);
1477 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1478                             struct drm_display_mode *adjusted_mode);
1479 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1480                              struct intel_crtc_state *pipe_config,
1481                              int fitting_mode);
1482 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1483                               struct intel_crtc_state *pipe_config,
1484                               int fitting_mode);
1485 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1486                                     u32 level, u32 max);
1487 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1488 void intel_panel_enable_backlight(struct intel_connector *connector);
1489 void intel_panel_disable_backlight(struct intel_connector *connector);
1490 void intel_panel_destroy_backlight(struct drm_connector *connector);
1491 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1492 extern struct drm_display_mode *intel_find_panel_downclock(
1493                                 struct drm_device *dev,
1494                                 struct drm_display_mode *fixed_mode,
1495                                 struct drm_connector *connector);
1496 void intel_backlight_register(struct drm_device *dev);
1497 void intel_backlight_unregister(struct drm_device *dev);
1498
1499
1500 /* intel_psr.c */
1501 void intel_psr_enable(struct intel_dp *intel_dp);
1502 void intel_psr_disable(struct intel_dp *intel_dp);
1503 void intel_psr_invalidate(struct drm_device *dev,
1504                           unsigned frontbuffer_bits);
1505 void intel_psr_flush(struct drm_device *dev,
1506                      unsigned frontbuffer_bits,
1507                      enum fb_op_origin origin);
1508 void intel_psr_init(struct drm_device *dev);
1509 void intel_psr_single_frame_update(struct drm_device *dev,
1510                                    unsigned frontbuffer_bits);
1511
1512 /* intel_runtime_pm.c */
1513 int intel_power_domains_init(struct drm_i915_private *);
1514 void intel_power_domains_fini(struct drm_i915_private *);
1515 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1516 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1517 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1518 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1519 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1520 const char *
1521 intel_display_power_domain_str(enum intel_display_power_domain domain);
1522
1523 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1524                                     enum intel_display_power_domain domain);
1525 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1526                                       enum intel_display_power_domain domain);
1527 void intel_display_power_get(struct drm_i915_private *dev_priv,
1528                              enum intel_display_power_domain domain);
1529 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1530                                         enum intel_display_power_domain domain);
1531 void intel_display_power_put(struct drm_i915_private *dev_priv,
1532                              enum intel_display_power_domain domain);
1533
1534 static inline void
1535 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1536 {
1537         WARN_ONCE(dev_priv->pm.suspended,
1538                   "Device suspended during HW access\n");
1539 }
1540
1541 static inline void
1542 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1543 {
1544         assert_rpm_device_not_suspended(dev_priv);
1545         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1546          * too much noise. */
1547         if (!atomic_read(&dev_priv->pm.wakeref_count))
1548                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1549 }
1550
1551 static inline int
1552 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1553 {
1554         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1555
1556         assert_rpm_wakelock_held(dev_priv);
1557
1558         return seq;
1559 }
1560
1561 static inline void
1562 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1563 {
1564         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1565                   "HW access outside of RPM atomic section\n");
1566 }
1567
1568 /**
1569  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1570  * @dev_priv: i915 device instance
1571  *
1572  * This function disable asserts that check if we hold an RPM wakelock
1573  * reference, while keeping the device-not-suspended checks still enabled.
1574  * It's meant to be used only in special circumstances where our rule about
1575  * the wakelock refcount wrt. the device power state doesn't hold. According
1576  * to this rule at any point where we access the HW or want to keep the HW in
1577  * an active state we must hold an RPM wakelock reference acquired via one of
1578  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1579  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1580  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1581  * users should avoid using this function.
1582  *
1583  * Any calls to this function must have a symmetric call to
1584  * enable_rpm_wakeref_asserts().
1585  */
1586 static inline void
1587 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1588 {
1589         atomic_inc(&dev_priv->pm.wakeref_count);
1590 }
1591
1592 /**
1593  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1594  * @dev_priv: i915 device instance
1595  *
1596  * This function re-enables the RPM assert checks after disabling them with
1597  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1598  * circumstances otherwise its use should be avoided.
1599  *
1600  * Any calls to this function must have a symmetric call to
1601  * disable_rpm_wakeref_asserts().
1602  */
1603 static inline void
1604 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1605 {
1606         atomic_dec(&dev_priv->pm.wakeref_count);
1607 }
1608
1609 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1610 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1611         disable_rpm_wakeref_asserts(dev_priv)
1612
1613 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1614         enable_rpm_wakeref_asserts(dev_priv)
1615
1616 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1617 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1618 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1619 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1620
1621 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1622
1623 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1624                              bool override, unsigned int mask);
1625 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1626                           enum dpio_channel ch, bool override);
1627
1628
1629 /* intel_pm.c */
1630 void intel_init_clock_gating(struct drm_device *dev);
1631 void intel_suspend_hw(struct drm_device *dev);
1632 int ilk_wm_max_level(const struct drm_device *dev);
1633 void intel_update_watermarks(struct drm_crtc *crtc);
1634 void intel_init_pm(struct drm_device *dev);
1635 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1636 void intel_pm_setup(struct drm_device *dev);
1637 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1638 void intel_gpu_ips_teardown(void);
1639 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1640 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1641 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1642 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1643 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1644 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1645 void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1646 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1647 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1648 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1649 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1650                     struct intel_rps_client *rps,
1651                     unsigned long submitted);
1652 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1653 void vlv_wm_get_hw_state(struct drm_device *dev);
1654 void ilk_wm_get_hw_state(struct drm_device *dev);
1655 void skl_wm_get_hw_state(struct drm_device *dev);
1656 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1657                           struct skl_ddb_allocation *ddb /* out */);
1658 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1659 bool ilk_disable_lp_wm(struct drm_device *dev);
1660 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1661 static inline int intel_enable_rc6(void)
1662 {
1663         return i915.enable_rc6;
1664 }
1665
1666 /* intel_sdvo.c */
1667 bool intel_sdvo_init(struct drm_device *dev,
1668                      i915_reg_t reg, enum port port);
1669
1670
1671 /* intel_sprite.c */
1672 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1673 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1674                               struct drm_file *file_priv);
1675 void intel_pipe_update_start(struct intel_crtc *crtc);
1676 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1677
1678 /* intel_tv.c */
1679 void intel_tv_init(struct drm_device *dev);
1680
1681 /* intel_atomic.c */
1682 int intel_connector_atomic_get_property(struct drm_connector *connector,
1683                                         const struct drm_connector_state *state,
1684                                         struct drm_property *property,
1685                                         uint64_t *val);
1686 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1687 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1688                                struct drm_crtc_state *state);
1689 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1690 void intel_atomic_state_clear(struct drm_atomic_state *);
1691 struct intel_shared_dpll_config *
1692 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1693
1694 static inline struct intel_crtc_state *
1695 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1696                             struct intel_crtc *crtc)
1697 {
1698         struct drm_crtc_state *crtc_state;
1699         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1700         if (IS_ERR(crtc_state))
1701                 return ERR_CAST(crtc_state);
1702
1703         return to_intel_crtc_state(crtc_state);
1704 }
1705
1706 static inline struct intel_plane_state *
1707 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1708                                       struct intel_plane *plane)
1709 {
1710         struct drm_plane_state *plane_state;
1711
1712         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1713
1714         return to_intel_plane_state(plane_state);
1715 }
1716
1717 int intel_atomic_setup_scalers(struct drm_device *dev,
1718         struct intel_crtc *intel_crtc,
1719         struct intel_crtc_state *crtc_state);
1720
1721 /* intel_atomic_plane.c */
1722 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1723 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1724 void intel_plane_destroy_state(struct drm_plane *plane,
1725                                struct drm_plane_state *state);
1726 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1727
1728 /* intel_color.c */
1729 void intel_color_init(struct drm_crtc *crtc);
1730 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1731 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1732 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1733
1734 #endif /* __INTEL_DRV_H__ */