drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134 #include <linux/interrupt.h>
 135
 136 #include <drm/drmP.h>
 137 #include <drm/i915_drm.h>
 138 #include "i915_drv.h"
 139 #include "intel_mocs.h"
 140
 141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 144
 145 #define RING_EXECLIST_QFULL             (1 << 0x2)
 146 #define RING_EXECLIST1_VALID            (1 << 0x3)
 147 #define RING_EXECLIST0_VALID            (1 << 0x4)
 148 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 149 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 150 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 151
 152 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 153 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 155 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 156 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 157 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 158
 159 #define CTX_LRI_HEADER_0                0x01
 160 #define CTX_CONTEXT_CONTROL             0x02
 161 #define CTX_RING_HEAD                   0x04
 162 #define CTX_RING_TAIL                   0x06
 163 #define CTX_RING_BUFFER_START           0x08
 164 #define CTX_RING_BUFFER_CONTROL         0x0a
 165 #define CTX_BB_HEAD_U                   0x0c
 166 #define CTX_BB_HEAD_L                   0x0e
 167 #define CTX_BB_STATE                    0x10
 168 #define CTX_SECOND_BB_HEAD_U            0x12
 169 #define CTX_SECOND_BB_HEAD_L            0x14
 170 #define CTX_SECOND_BB_STATE             0x16
 171 #define CTX_BB_PER_CTX_PTR              0x18
 172 #define CTX_RCS_INDIRECT_CTX            0x1a
 173 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 174 #define CTX_LRI_HEADER_1                0x21
 175 #define CTX_CTX_TIMESTAMP               0x22
 176 #define CTX_PDP3_UDW                    0x24
 177 #define CTX_PDP3_LDW                    0x26
 178 #define CTX_PDP2_UDW                    0x28
 179 #define CTX_PDP2_LDW                    0x2a
 180 #define CTX_PDP1_UDW                    0x2c
 181 #define CTX_PDP1_LDW                    0x2e
 182 #define CTX_PDP0_UDW                    0x30
 183 #define CTX_PDP0_LDW                    0x32
 184 #define CTX_LRI_HEADER_2                0x41
 185 #define CTX_R_PWR_CLK_STATE             0x42
 186 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 187
 188 #define GEN8_CTX_VALID (1<<0)
 189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 192 #define GEN8_CTX_PRIVILEGE (1<<8)
 193
 194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
 195         (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
 196         (reg_state)[(pos)+1] = (val); \
 197 } while (0)
 198
 199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {                \
 200         const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
 201         reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
 202         reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
 203 } while (0)
 204
 205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
 206         reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
 207         reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
 208 } while (0)
 209
 210 enum {
 211         FAULT_AND_HANG = 0,
 212         FAULT_AND_HALT, /* Debug only */
 213         FAULT_AND_STREAM,
 214         FAULT_AND_CONTINUE /* Unsupported */
 215 };
 216 #define GEN8_CTX_ID_SHIFT 32
 217 #define GEN8_CTX_ID_WIDTH 21
 218 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT        0x17
 219 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT        0x26
 220
 221 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
 222 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
 223
 224 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
 225                                             struct intel_engine_cs *engine);
 226 static int intel_lr_context_pin(struct i915_gem_context *ctx,
 227                                 struct intel_engine_cs *engine);
 228
 229 /**
 230  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 231  * @dev_priv: i915 device private
 232  * @enable_execlists: value of i915.enable_execlists module parameter.
 233  *
 234  * Only certain platforms support Execlists (the prerequisites being
 235  * support for Logical Ring Contexts and Aliasing PPGTT or better).
 236  *
 237  * Return: 1 if Execlists is supported and has to be enabled.
 238  */
 239 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
 240 {
 241         /* On platforms with execlist available, vGPU will only
 242          * support execlist mode, no ring buffer mode.
 243          */
 244         if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
 245                 return 1;
 246
 247         if (INTEL_GEN(dev_priv) >= 9)
 248                 return 1;
 249
 250         if (enable_execlists == 0)
 251                 return 0;
 252
 253         if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
 254             USES_PPGTT(dev_priv) &&
 255             i915.use_mmio_flip >= 0)
 256                 return 1;
 257
 258         return 0;
 259 }
 260
 261 static void
 262 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
 263 {
 264         struct drm_i915_private *dev_priv = engine->i915;
 265
 266         if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
 267                 engine->idle_lite_restore_wa = ~0;
 268
 269         engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 270                                         IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
 271                                         (engine->id == VCS || engine->id == VCS2);
 272
 273         engine->ctx_desc_template = GEN8_CTX_VALID;
 274         if (IS_GEN8(dev_priv))
 275                 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
 276         engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
 277
 278         /* TODO: WaDisableLiteRestore when we start using semaphore
 279          * signalling between Command Streamers */
 280         /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
 281
 282         /* WaEnableForceRestoreInCtxtDescForVCS:skl */
 283         /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
 284         if (engine->disable_lite_restore_wa)
 285                 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
 286 }
 287
 288 /**
 289  * intel_lr_context_descriptor_update() - calculate & cache the descriptor
 290  *                                        descriptor for a pinned context
 291  * @ctx: Context to work on
 292  * @engine: Engine the descriptor will be used with
 293  *
 294  * The context descriptor encodes various attributes of a context,
 295  * including its GTT address and some flags. Because it's fairly
 296  * expensive to calculate, we'll just do it once and cache the result,
 297  * which remains valid until the context is unpinned.
 298  *
 299  * This is what a descriptor looks like, from LSB to MSB::
 300  *
 301  *      bits  0-11:    flags, GEN8_CTX_* (cached in ctx_desc_template)
 302  *      bits 12-31:    LRCA, GTT address of (the HWSP of) this context
 303  *      bits 32-52:    ctx ID, a globally unique tag
 304  *      bits 53-54:    mbz, reserved for use by hardware
 305  *      bits 55-63:    group ID, currently unused and set to 0
 306  */
 307 static void
 308 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
 309                                    struct intel_engine_cs *engine)
 310 {
 311         struct intel_context *ce = &ctx->engine[engine->id];
 312         u64 desc;
 313
 314         BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
 315
 316         desc = ctx->desc_template;                              /* bits  3-4  */
 317         desc |= engine->ctx_desc_template;                      /* bits  0-11 */
 318         desc |= ce->lrc_vma->node.start + LRC_PPHWSP_PN * PAGE_SIZE;
 319                                                                 /* bits 12-31 */
 320         desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;           /* bits 32-52 */
 321
 322         ce->lrc_desc = desc;
 323 }
 324
 325 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
 326                                      struct intel_engine_cs *engine)
 327 {
 328         return ctx->engine[engine->id].lrc_desc;
 329 }
 330
 331 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
 332                                  struct drm_i915_gem_request *rq1)
 333 {
 334
 335         struct intel_engine_cs *engine = rq0->engine;
 336         struct drm_i915_private *dev_priv = rq0->i915;
 337         uint64_t desc[2];
 338
 339         if (rq1) {
 340                 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
 341                 rq1->elsp_submitted++;
 342         } else {
 343                 desc[1] = 0;
 344         }
 345
 346         desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
 347         rq0->elsp_submitted++;
 348
 349         /* You must always write both descriptors in the order below. */
 350         I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
 351         I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
 352
 353         I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
 354         /* The context is automatically loaded after the following */
 355         I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
 356
 357         /* ELSP is a wo register, use another nearby reg for posting */
 358         POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
 359 }
 360
 361 static void
 362 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 363 {
 364         ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
 365         ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
 366         ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
 367         ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
 368 }
 369
 370 static void execlists_update_context(struct drm_i915_gem_request *rq)
 371 {
 372         struct intel_engine_cs *engine = rq->engine;
 373         struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
 374         uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
 375
 376         reg_state[CTX_RING_TAIL+1] = intel_ring_offset(rq->ring, rq->tail);
 377
 378         /* True 32b PPGTT with dynamic page allocation: update PDP
 379          * registers and point the unallocated PDPs to scratch page.
 380          * PML4 is allocated during ppgtt init, so this is not needed
 381          * in 48-bit mode.
 382          */
 383         if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 384                 execlists_update_context_pdps(ppgtt, reg_state);
 385 }
 386
 387 static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
 388                                            struct drm_i915_gem_request *rq1)
 389 {
 390         struct drm_i915_private *dev_priv = rq0->i915;
 391         unsigned int fw_domains = rq0->engine->fw_domains;
 392
 393         execlists_update_context(rq0);
 394
 395         if (rq1)
 396                 execlists_update_context(rq1);
 397
 398         spin_lock_irq(&dev_priv->uncore.lock);
 399         intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 400
 401         execlists_elsp_write(rq0, rq1);
 402
 403         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
 404         spin_unlock_irq(&dev_priv->uncore.lock);
 405 }
 406
 407 static inline void execlists_context_status_change(
 408                 struct drm_i915_gem_request *rq,
 409                 unsigned long status)
 410 {
 411         /*
 412          * Only used when GVT-g is enabled now. When GVT-g is disabled,
 413          * The compiler should eliminate this function as dead-code.
 414          */
 415         if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
 416                 return;
 417
 418         atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
 419 }
 420
 421 static void execlists_unqueue(struct intel_engine_cs *engine)
 422 {
 423         struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
 424         struct drm_i915_gem_request *cursor, *tmp;
 425
 426         assert_spin_locked(&engine->execlist_lock);
 427
 428         /*
 429          * If irqs are not active generate a warning as batches that finish
 430          * without the irqs may get lost and a GPU Hang may occur.
 431          */
 432         WARN_ON(!intel_irqs_enabled(engine->i915));
 433
 434         /* Try to read in pairs */
 435         list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
 436                                  execlist_link) {
 437                 if (!req0) {
 438                         req0 = cursor;
 439                 } else if (req0->ctx == cursor->ctx) {
 440                         /* Same ctx: ignore first request, as second request
 441                          * will update tail past first request's workload */
 442                         cursor->elsp_submitted = req0->elsp_submitted;
 443                         list_del(&req0->execlist_link);
 444                         i915_gem_request_put(req0);
 445                         req0 = cursor;
 446                 } else {
 447                         if (IS_ENABLED(CONFIG_DRM_I915_GVT)) {
 448                                 /*
 449                                  * req0 (after merged) ctx requires single
 450                                  * submission, stop picking
 451                                  */
 452                                 if (req0->ctx->execlists_force_single_submission)
 453                                         break;
 454                                 /*
 455                                  * req0 ctx doesn't require single submission,
 456                                  * but next req ctx requires, stop picking
 457                                  */
 458                                 if (cursor->ctx->execlists_force_single_submission)
 459                                         break;
 460                         }
 461                         req1 = cursor;
 462                         WARN_ON(req1->elsp_submitted);
 463                         break;
 464                 }
 465         }
 466
 467         if (unlikely(!req0))
 468                 return;
 469
 470         execlists_context_status_change(req0, INTEL_CONTEXT_SCHEDULE_IN);
 471
 472         if (req1)
 473                 execlists_context_status_change(req1,
 474                                                 INTEL_CONTEXT_SCHEDULE_IN);
 475
 476         if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
 477                 /*
 478                  * WaIdleLiteRestore: make sure we never cause a lite restore
 479                  * with HEAD==TAIL.
 480                  *
 481                  * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
 482                  * resubmit the request. See gen8_emit_request() for where we
 483                  * prepare the padding after the end of the request.
 484                  */
 485                 req0->tail += 8;
 486                 req0->tail &= req0->ring->size - 1;
 487         }
 488
 489         execlists_elsp_submit_contexts(req0, req1);
 490 }
 491
 492 static unsigned int
 493 execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
 494 {
 495         struct drm_i915_gem_request *head_req;
 496
 497         assert_spin_locked(&engine->execlist_lock);
 498
 499         head_req = list_first_entry_or_null(&engine->execlist_queue,
 500                                             struct drm_i915_gem_request,
 501                                             execlist_link);
 502
 503         if (WARN_ON(!head_req || (head_req->ctx_hw_id != ctx_id)))
 504                return 0;
 505
 506         WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
 507
 508         if (--head_req->elsp_submitted > 0)
 509                 return 0;
 510
 511         execlists_context_status_change(head_req, INTEL_CONTEXT_SCHEDULE_OUT);
 512
 513         list_del(&head_req->execlist_link);
 514         i915_gem_request_put(head_req);
 515
 516         return 1;
 517 }
 518
 519 static u32
 520 get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
 521                    u32 *context_id)
 522 {
 523         struct drm_i915_private *dev_priv = engine->i915;
 524         u32 status;
 525
 526         read_pointer %= GEN8_CSB_ENTRIES;
 527
 528         status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
 529
 530         if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
 531                 return 0;
 532
 533         *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
 534                                                               read_pointer));
 535
 536         return status;
 537 }
 538
 539 /*
 540  * Check the unread Context Status Buffers and manage the submission of new
 541  * contexts to the ELSP accordingly.
 542  */
 543 static void intel_lrc_irq_handler(unsigned long data)
 544 {
 545         struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
 546         struct drm_i915_private *dev_priv = engine->i915;
 547         u32 status_pointer;
 548         unsigned int read_pointer, write_pointer;
 549         u32 csb[GEN8_CSB_ENTRIES][2];
 550         unsigned int csb_read = 0, i;
 551         unsigned int submit_contexts = 0;
 552
 553         intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
 554
 555         status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
 556
 557         read_pointer = engine->next_context_status_buffer;
 558         write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
 559         if (read_pointer > write_pointer)
 560                 write_pointer += GEN8_CSB_ENTRIES;
 561
 562         while (read_pointer < write_pointer) {
 563                 if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
 564                         break;
 565                 csb[csb_read][0] = get_context_status(engine, ++read_pointer,
 566                                                       &csb[csb_read][1]);
 567                 csb_read++;
 568         }
 569
 570         engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
 571
 572         /* Update the read pointer to the old write pointer. Manual ringbuffer
 573          * management ftw </sarcasm> */
 574         I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
 575                       _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
 576                                     engine->next_context_status_buffer << 8));
 577
 578         intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
 579
 580         spin_lock(&engine->execlist_lock);
 581
 582         for (i = 0; i < csb_read; i++) {
 583                 if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
 584                         if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
 585                                 if (execlists_check_remove_request(engine, csb[i][1]))
 586                                         WARN(1, "Lite Restored request removed from queue\n");
 587                         } else
 588                                 WARN(1, "Preemption without Lite Restore\n");
 589                 }
 590
 591                 if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
 592                     GEN8_CTX_STATUS_ELEMENT_SWITCH))
 593                         submit_contexts +=
 594                                 execlists_check_remove_request(engine, csb[i][1]);
 595         }
 596
 597         if (submit_contexts) {
 598                 if (!engine->disable_lite_restore_wa ||
 599                     (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
 600                         execlists_unqueue(engine);
 601         }
 602
 603         spin_unlock(&engine->execlist_lock);
 604
 605         if (unlikely(submit_contexts > 2))
 606                 DRM_ERROR("More than two context complete events?\n");
 607 }
 608
 609 static void execlists_submit_request(struct drm_i915_gem_request *request)
 610 {
 611         struct intel_engine_cs *engine = request->engine;
 612         struct drm_i915_gem_request *cursor;
 613         int num_elements = 0;
 614
 615         spin_lock_bh(&engine->execlist_lock);
 616
 617         list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
 618                 if (++num_elements > 2)
 619                         break;
 620
 621         if (num_elements > 2) {
 622                 struct drm_i915_gem_request *tail_req;
 623
 624                 tail_req = list_last_entry(&engine->execlist_queue,
 625                                            struct drm_i915_gem_request,
 626                                            execlist_link);
 627
 628                 if (request->ctx == tail_req->ctx) {
 629                         WARN(tail_req->elsp_submitted != 0,
 630                                 "More than 2 already-submitted reqs queued\n");
 631                         list_del(&tail_req->execlist_link);
 632                         i915_gem_request_put(tail_req);
 633                 }
 634         }
 635
 636         i915_gem_request_get(request);
 637         list_add_tail(&request->execlist_link, &engine->execlist_queue);
 638         request->ctx_hw_id = request->ctx->hw_id;
 639         if (num_elements == 0)
 640                 execlists_unqueue(engine);
 641
 642         spin_unlock_bh(&engine->execlist_lock);
 643 }
 644
 645 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
 646 {
 647         struct intel_engine_cs *engine = request->engine;
 648         struct intel_context *ce = &request->ctx->engine[engine->id];
 649         int ret;
 650
 651         /* Flush enough space to reduce the likelihood of waiting after
 652          * we start building the request - in which case we will just
 653          * have to repeat work.
 654          */
 655         request->reserved_space += EXECLISTS_REQUEST_SIZE;
 656
 657         if (!ce->state) {
 658                 ret = execlists_context_deferred_alloc(request->ctx, engine);
 659                 if (ret)
 660                         return ret;
 661         }
 662
 663         request->ring = ce->ring;
 664
 665         if (i915.enable_guc_submission) {
 666                 /*
 667                  * Check that the GuC has space for the request before
 668                  * going any further, as the i915_add_request() call
 669                  * later on mustn't fail ...
 670                  */
 671                 ret = i915_guc_wq_check_space(request);
 672                 if (ret)
 673                         return ret;
 674         }
 675
 676         ret = intel_lr_context_pin(request->ctx, engine);
 677         if (ret)
 678                 return ret;
 679
 680         ret = intel_ring_begin(request, 0);
 681         if (ret)
 682                 goto err_unpin;
 683
 684         if (!ce->initialised) {
 685                 ret = engine->init_context(request);
 686                 if (ret)
 687                         goto err_unpin;
 688
 689                 ce->initialised = true;
 690         }
 691
 692         /* Note that after this point, we have committed to using
 693          * this request as it is being used to both track the
 694          * state of engine initialisation and liveness of the
 695          * golden renderstate above. Think twice before you try
 696          * to cancel/unwind this request now.
 697          */
 698
 699         request->reserved_space -= EXECLISTS_REQUEST_SIZE;
 700         return 0;
 701
 702 err_unpin:
 703         intel_lr_context_unpin(request->ctx, engine);
 704         return ret;
 705 }
 706
 707 /*
 708  * intel_logical_ring_advance() - advance the tail and prepare for submission
 709  * @request: Request to advance the logical ringbuffer of.
 710  *
 711  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 712  * really happens during submission is that the context and current tail will be placed
 713  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 714  * point, the tail *inside* the context is updated and the ELSP written to.
 715  */
 716 static int
 717 intel_logical_ring_advance(struct drm_i915_gem_request *request)
 718 {
 719         struct intel_ring *ring = request->ring;
 720         struct intel_engine_cs *engine = request->engine;
 721
 722         intel_ring_advance(ring);
 723         request->tail = ring->tail;
 724
 725         /*
 726          * Here we add two extra NOOPs as padding to avoid
 727          * lite restore of a context with HEAD==TAIL.
 728          *
 729          * Caller must reserve WA_TAIL_DWORDS for us!
 730          */
 731         intel_ring_emit(ring, MI_NOOP);
 732         intel_ring_emit(ring, MI_NOOP);
 733         intel_ring_advance(ring);
 734
 735         /* We keep the previous context alive until we retire the following
 736          * request. This ensures that any the context object is still pinned
 737          * for any residual writes the HW makes into it on the context switch
 738          * into the next object following the breadcrumb. Otherwise, we may
 739          * retire the context too early.
 740          */
 741         request->previous_context = engine->last_context;
 742         engine->last_context = request->ctx;
 743         return 0;
 744 }
 745
 746 void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
 747 {
 748         struct drm_i915_gem_request *req, *tmp;
 749         LIST_HEAD(cancel_list);
 750
 751         WARN_ON(!mutex_is_locked(&engine->i915->drm.struct_mutex));
 752
 753         spin_lock_bh(&engine->execlist_lock);
 754         list_replace_init(&engine->execlist_queue, &cancel_list);
 755         spin_unlock_bh(&engine->execlist_lock);
 756
 757         list_for_each_entry_safe(req, tmp, &cancel_list, execlist_link) {
 758                 list_del(&req->execlist_link);
 759                 i915_gem_request_put(req);
 760         }
 761 }
 762
 763 void intel_logical_ring_stop(struct intel_engine_cs *engine)
 764 {
 765         struct drm_i915_private *dev_priv = engine->i915;
 766         int ret;
 767
 768         if (!intel_engine_initialized(engine))
 769                 return;
 770
 771         ret = intel_engine_idle(engine);
 772         if (ret)
 773                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 774                           engine->name, ret);
 775
 776         /* TODO: Is this correct with Execlists enabled? */
 777         I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 778         if (intel_wait_for_register(dev_priv,
 779                                     RING_MI_MODE(engine->mmio_base),
 780                                     MODE_IDLE, MODE_IDLE,
 781                                     1000)) {
 782                 DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
 783                 return;
 784         }
 785         I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 786 }
 787
 788 static int intel_lr_context_pin(struct i915_gem_context *ctx,
 789                                 struct intel_engine_cs *engine)
 790 {
 791         struct drm_i915_private *dev_priv = ctx->i915;
 792         struct intel_context *ce = &ctx->engine[engine->id];
 793         void *vaddr;
 794         u32 *lrc_reg_state;
 795         int ret;
 796
 797         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
 798
 799         if (ce->pin_count++)
 800                 return 0;
 801
 802         ret = i915_gem_object_ggtt_pin(ce->state, NULL,
 803                                        0, GEN8_LR_CONTEXT_ALIGN,
 804                                        PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 805         if (ret)
 806                 goto err;
 807
 808         vaddr = i915_gem_object_pin_map(ce->state);
 809         if (IS_ERR(vaddr)) {
 810                 ret = PTR_ERR(vaddr);
 811                 goto unpin_ctx_obj;
 812         }
 813
 814         lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
 815
 816         ret = intel_ring_pin(ce->ring);
 817         if (ret)
 818                 goto unpin_map;
 819
 820         ce->lrc_vma = i915_gem_obj_to_ggtt(ce->state);
 821         intel_lr_context_descriptor_update(ctx, engine);
 822
 823         lrc_reg_state[CTX_RING_BUFFER_START+1] = ce->ring->vma->node.start;
 824         ce->lrc_reg_state = lrc_reg_state;
 825         ce->state->dirty = true;
 826
 827         /* Invalidate GuC TLB. */
 828         if (i915.enable_guc_submission)
 829                 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 830
 831         i915_gem_context_get(ctx);
 832         return 0;
 833
 834 unpin_map:
 835         i915_gem_object_unpin_map(ce->state);
 836 unpin_ctx_obj:
 837         i915_gem_object_ggtt_unpin(ce->state);
 838 err:
 839         ce->pin_count = 0;
 840         return ret;
 841 }
 842
 843 void intel_lr_context_unpin(struct i915_gem_context *ctx,
 844                             struct intel_engine_cs *engine)
 845 {
 846         struct intel_context *ce = &ctx->engine[engine->id];
 847
 848         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
 849         GEM_BUG_ON(ce->pin_count == 0);
 850
 851         if (--ce->pin_count)
 852                 return;
 853
 854         intel_ring_unpin(ce->ring);
 855
 856         i915_gem_object_unpin_map(ce->state);
 857         i915_gem_object_ggtt_unpin(ce->state);
 858
 859         ce->lrc_vma = NULL;
 860         ce->lrc_desc = 0;
 861         ce->lrc_reg_state = NULL;
 862
 863         i915_gem_context_put(ctx);
 864 }
 865
 866 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
 867 {
 868         int ret, i;
 869         struct intel_ring *ring = req->ring;
 870         struct i915_workarounds *w = &req->i915->workarounds;
 871
 872         if (w->count == 0)
 873                 return 0;
 874
 875         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 876         if (ret)
 877                 return ret;
 878
 879         ret = intel_ring_begin(req, w->count * 2 + 2);
 880         if (ret)
 881                 return ret;
 882
 883         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 884         for (i = 0; i < w->count; i++) {
 885                 intel_ring_emit_reg(ring, w->reg[i].addr);
 886                 intel_ring_emit(ring, w->reg[i].value);
 887         }
 888         intel_ring_emit(ring, MI_NOOP);
 889
 890         intel_ring_advance(ring);
 891
 892         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 893         if (ret)
 894                 return ret;
 895
 896         return 0;
 897 }
 898
 899 #define wa_ctx_emit(batch, index, cmd)                                  \
 900         do {                                                            \
 901                 int __index = (index)++;                                \
 902                 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
 903                         return -ENOSPC;                                 \
 904                 }                                                       \
 905                 batch[__index] = (cmd);                                 \
 906         } while (0)
 907
 908 #define wa_ctx_emit_reg(batch, index, reg) \
 909         wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
 910
 911 /*
 912  * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 913  * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 914  * but there is a slight complication as this is applied in WA batch where the
 915  * values are only initialized once so we cannot take register value at the
 916  * beginning and reuse it further; hence we save its value to memory, upload a
 917  * constant value with bit21 set and then we restore it back with the saved value.
 918  * To simplify the WA, a constant value is formed by using the default value
 919  * of this register. This shouldn't be a problem because we are only modifying
 920  * it for a short period and this batch in non-premptible. We can ofcourse
 921  * use additional instructions that read the actual value of the register
 922  * at that time and set our bit of interest but it makes the WA complicated.
 923  *
 924  * This WA is also required for Gen9 so extracting as a function avoids
 925  * code duplication.
 926  */
 927 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
 928                                                 uint32_t *batch,
 929                                                 uint32_t index)
 930 {
 931         struct drm_i915_private *dev_priv = engine->i915;
 932         uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
 933
 934         /*
 935          * WaDisableLSQCROPERFforOCL:skl,kbl
 936          * This WA is implemented in skl_init_clock_gating() but since
 937          * this batch updates GEN8_L3SQCREG4 with default value we need to
 938          * set this bit here to retain the WA during flush.
 939          */
 940         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||
 941             IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
 942                 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
 943
 944         wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
 945                                    MI_SRM_LRM_GLOBAL_GTT));
 946         wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
 947         wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
 948         wa_ctx_emit(batch, index, 0);
 949
 950         wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
 951         wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
 952         wa_ctx_emit(batch, index, l3sqc4_flush);
 953
 954         wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
 955         wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
 956                                    PIPE_CONTROL_DC_FLUSH_ENABLE));
 957         wa_ctx_emit(batch, index, 0);
 958         wa_ctx_emit(batch, index, 0);
 959         wa_ctx_emit(batch, index, 0);
 960         wa_ctx_emit(batch, index, 0);
 961
 962         wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
 963                                    MI_SRM_LRM_GLOBAL_GTT));
 964         wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
 965         wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
 966         wa_ctx_emit(batch, index, 0);
 967
 968         return index;
 969 }
 970
 971 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
 972                                     uint32_t offset,
 973                                     uint32_t start_alignment)
 974 {
 975         return wa_ctx->offset = ALIGN(offset, start_alignment);
 976 }
 977
 978 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
 979                              uint32_t offset,
 980                              uint32_t size_alignment)
 981 {
 982         wa_ctx->size = offset - wa_ctx->offset;
 983
 984         WARN(wa_ctx->size % size_alignment,
 985              "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
 986              wa_ctx->size, size_alignment);
 987         return 0;
 988 }
 989
 990 /*
 991  * Typically we only have one indirect_ctx and per_ctx batch buffer which are
 992  * initialized at the beginning and shared across all contexts but this field
 993  * helps us to have multiple batches at different offsets and select them based
 994  * on a criteria. At the moment this batch always start at the beginning of the page
 995  * and at this point we don't have multiple wa_ctx batch buffers.
 996  *
 997  * The number of WA applied are not known at the beginning; we use this field
 998  * to return the no of DWORDS written.
 999  *
1000  * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1001  * so it adds NOOPs as padding to make it cacheline aligned.
1002  * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1003  * makes a complete batch buffer.
1004  */
1005 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1006                                     struct i915_wa_ctx_bb *wa_ctx,
1007                                     uint32_t *batch,
1008                                     uint32_t *offset)
1009 {
1010         uint32_t scratch_addr;
1011         uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1012
1013         /* WaDisableCtxRestoreArbitration:bdw,chv */
1014         wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1015
1016         /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1017         if (IS_BROADWELL(engine->i915)) {
1018                 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1019                 if (rc < 0)
1020                         return rc;
1021                 index = rc;
1022         }
1023
1024         /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1025         /* Actual scratch location is at 128 bytes offset */
1026         scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1027
1028         wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1029         wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1030                                    PIPE_CONTROL_GLOBAL_GTT_IVB |
1031                                    PIPE_CONTROL_CS_STALL |
1032                                    PIPE_CONTROL_QW_WRITE));
1033         wa_ctx_emit(batch, index, scratch_addr);
1034         wa_ctx_emit(batch, index, 0);
1035         wa_ctx_emit(batch, index, 0);
1036         wa_ctx_emit(batch, index, 0);
1037
1038         /* Pad to end of cacheline */
1039         while (index % CACHELINE_DWORDS)
1040                 wa_ctx_emit(batch, index, MI_NOOP);
1041
1042         /*
1043          * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1044          * execution depends on the length specified in terms of cache lines
1045          * in the register CTX_RCS_INDIRECT_CTX
1046          */
1047
1048         return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1049 }
1050
1051 /*
1052  *  This batch is started immediately after indirect_ctx batch. Since we ensure
1053  *  that indirect_ctx ends on a cacheline this batch is aligned automatically.
1054  *
1055  *  The number of DWORDS written are returned using this field.
1056  *
1057  *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1058  *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1059  */
1060 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1061                                struct i915_wa_ctx_bb *wa_ctx,
1062                                uint32_t *batch,
1063                                uint32_t *offset)
1064 {
1065         uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1066
1067         /* WaDisableCtxRestoreArbitration:bdw,chv */
1068         wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1069
1070         wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1071
1072         return wa_ctx_end(wa_ctx, *offset = index, 1);
1073 }
1074
1075 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1076                                     struct i915_wa_ctx_bb *wa_ctx,
1077                                     uint32_t *batch,
1078                                     uint32_t *offset)
1079 {
1080         int ret;
1081         struct drm_i915_private *dev_priv = engine->i915;
1082         uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1083
1084         /* WaDisableCtxRestoreArbitration:skl,bxt */
1085         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
1086             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1087                 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1088
1089         /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1090         ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1091         if (ret < 0)
1092                 return ret;
1093         index = ret;
1094
1095         /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1096         wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1097         wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
1098         wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
1099                             GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
1100         wa_ctx_emit(batch, index, MI_NOOP);
1101
1102         /* WaClearSlmSpaceAtContextSwitch:kbl */
1103         /* Actual scratch location is at 128 bytes offset */
1104         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1105                 uint32_t scratch_addr
1106                         = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1107
1108                 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1109                 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1110                                            PIPE_CONTROL_GLOBAL_GTT_IVB |
1111                                            PIPE_CONTROL_CS_STALL |
1112                                            PIPE_CONTROL_QW_WRITE));
1113                 wa_ctx_emit(batch, index, scratch_addr);
1114                 wa_ctx_emit(batch, index, 0);
1115                 wa_ctx_emit(batch, index, 0);
1116                 wa_ctx_emit(batch, index, 0);
1117         }
1118
1119         /* WaMediaPoolStateCmdInWABB:bxt */
1120         if (HAS_POOLED_EU(engine->i915)) {
1121                 /*
1122                  * EU pool configuration is setup along with golden context
1123                  * during context initialization. This value depends on
1124                  * device type (2x6 or 3x6) and needs to be updated based
1125                  * on which subslice is disabled especially for 2x6
1126                  * devices, however it is safe to load default
1127                  * configuration of 3x6 device instead of masking off
1128                  * corresponding bits because HW ignores bits of a disabled
1129                  * subslice and drops down to appropriate config. Please
1130                  * see render_state_setup() in i915_gem_render_state.c for
1131                  * possible configurations, to avoid duplication they are
1132                  * not shown here again.
1133                  */
1134                 u32 eu_pool_config = 0x00777000;
1135                 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
1136                 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
1137                 wa_ctx_emit(batch, index, eu_pool_config);
1138                 wa_ctx_emit(batch, index, 0);
1139                 wa_ctx_emit(batch, index, 0);
1140                 wa_ctx_emit(batch, index, 0);
1141         }
1142
1143         /* Pad to end of cacheline */
1144         while (index % CACHELINE_DWORDS)
1145                 wa_ctx_emit(batch, index, MI_NOOP);
1146
1147         return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1148 }
1149
1150 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1151                                struct i915_wa_ctx_bb *wa_ctx,
1152                                uint32_t *batch,
1153                                uint32_t *offset)
1154 {
1155         uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1156
1157         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1158         if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
1159             IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
1160                 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1161                 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1162                 wa_ctx_emit(batch, index,
1163                             _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1164                 wa_ctx_emit(batch, index, MI_NOOP);
1165         }
1166
1167         /* WaClearTdlStateAckDirtyBits:bxt */
1168         if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
1169                 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1170
1171                 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1172                 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1173
1174                 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1175                 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1176
1177                 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1178                 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1179
1180                 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1181                 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1182                 wa_ctx_emit(batch, index, 0x0);
1183                 wa_ctx_emit(batch, index, MI_NOOP);
1184         }
1185
1186         /* WaDisableCtxRestoreArbitration:skl,bxt */
1187         if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
1188             IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1189                 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1190
1191         wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1192
1193         return wa_ctx_end(wa_ctx, *offset = index, 1);
1194 }
1195
1196 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1197 {
1198         int ret;
1199
1200         engine->wa_ctx.obj = i915_gem_object_create(&engine->i915->drm,
1201                                                     PAGE_ALIGN(size));
1202         if (IS_ERR(engine->wa_ctx.obj)) {
1203                 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1204                 ret = PTR_ERR(engine->wa_ctx.obj);
1205                 engine->wa_ctx.obj = NULL;
1206                 return ret;
1207         }
1208
1209         ret = i915_gem_object_ggtt_pin(engine->wa_ctx.obj, NULL,
1210                                        0, PAGE_SIZE, 0);
1211         if (ret) {
1212                 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1213                                  ret);
1214                 i915_gem_object_put(engine->wa_ctx.obj);
1215                 return ret;
1216         }
1217
1218         return 0;
1219 }
1220
1221 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1222 {
1223         if (engine->wa_ctx.obj) {
1224                 i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
1225                 i915_gem_object_put(engine->wa_ctx.obj);
1226                 engine->wa_ctx.obj = NULL;
1227         }
1228 }
1229
1230 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1231 {
1232         int ret;
1233         uint32_t *batch;
1234         uint32_t offset;
1235         struct page *page;
1236         struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1237
1238         WARN_ON(engine->id != RCS);
1239
1240         /* update this when WA for higher Gen are added */
1241         if (INTEL_GEN(engine->i915) > 9) {
1242                 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1243                           INTEL_GEN(engine->i915));
1244                 return 0;
1245         }
1246
1247         /* some WA perform writes to scratch page, ensure it is valid */
1248         if (engine->scratch.obj == NULL) {
1249                 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1250                 return -EINVAL;
1251         }
1252
1253         ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1254         if (ret) {
1255                 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1256                 return ret;
1257         }
1258
1259         page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1260         batch = kmap_atomic(page);
1261         offset = 0;
1262
1263         if (IS_GEN8(engine->i915)) {
1264                 ret = gen8_init_indirectctx_bb(engine,
1265                                                &wa_ctx->indirect_ctx,
1266                                                batch,
1267                                                &offset);
1268                 if (ret)
1269                         goto out;
1270
1271                 ret = gen8_init_perctx_bb(engine,
1272                                           &wa_ctx->per_ctx,
1273                                           batch,
1274                                           &offset);
1275                 if (ret)
1276                         goto out;
1277         } else if (IS_GEN9(engine->i915)) {
1278                 ret = gen9_init_indirectctx_bb(engine,
1279                                                &wa_ctx->indirect_ctx,
1280                                                batch,
1281                                                &offset);
1282                 if (ret)
1283                         goto out;
1284
1285                 ret = gen9_init_perctx_bb(engine,
1286                                           &wa_ctx->per_ctx,
1287                                           batch,
1288                                           &offset);
1289                 if (ret)
1290                         goto out;
1291         }
1292
1293 out:
1294         kunmap_atomic(batch);
1295         if (ret)
1296                 lrc_destroy_wa_ctx_obj(engine);
1297
1298         return ret;
1299 }
1300
1301 static void lrc_init_hws(struct intel_engine_cs *engine)
1302 {
1303         struct drm_i915_private *dev_priv = engine->i915;
1304
1305         I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1306                    (u32)engine->status_page.gfx_addr);
1307         POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1308 }
1309
1310 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1311 {
1312         struct drm_i915_private *dev_priv = engine->i915;
1313         unsigned int next_context_status_buffer_hw;
1314
1315         lrc_init_hws(engine);
1316
1317         I915_WRITE_IMR(engine,
1318                        ~(engine->irq_enable_mask | engine->irq_keep_mask));
1319         I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1320
1321         I915_WRITE(RING_MODE_GEN7(engine),
1322                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1323                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1324         POSTING_READ(RING_MODE_GEN7(engine));
1325
1326         /*
1327          * Instead of resetting the Context Status Buffer (CSB) read pointer to
1328          * zero, we need to read the write pointer from hardware and use its
1329          * value because "this register is power context save restored".
1330          * Effectively, these states have been observed:
1331          *
1332          *      | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1333          * BDW  | CSB regs not reset       | CSB regs reset       |
1334          * CHT  | CSB regs not reset       | CSB regs not reset   |
1335          * SKL  |         ?                |         ?            |
1336          * BXT  |         ?                |         ?            |
1337          */
1338         next_context_status_buffer_hw =
1339                 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1340
1341         /*
1342          * When the CSB registers are reset (also after power-up / gpu reset),
1343          * CSB write pointer is set to all 1's, which is not valid, use '5' in
1344          * this special case, so the first element read is CSB[0].
1345          */
1346         if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1347                 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1348
1349         engine->next_context_status_buffer = next_context_status_buffer_hw;
1350         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1351
1352         intel_engine_init_hangcheck(engine);
1353
1354         return intel_mocs_init_engine(engine);
1355 }
1356
1357 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1358 {
1359         struct drm_i915_private *dev_priv = engine->i915;
1360         int ret;
1361
1362         ret = gen8_init_common_ring(engine);
1363         if (ret)
1364                 return ret;
1365
1366         /* We need to disable the AsyncFlip performance optimisations in order
1367          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1368          * programmed to '1' on all products.
1369          *
1370          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1371          */
1372         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1373
1374         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1375
1376         return init_workarounds_ring(engine);
1377 }
1378
1379 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1380 {
1381         int ret;
1382
1383         ret = gen8_init_common_ring(engine);
1384         if (ret)
1385                 return ret;
1386
1387         return init_workarounds_ring(engine);
1388 }
1389
1390 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1391 {
1392         struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1393         struct intel_ring *ring = req->ring;
1394         struct intel_engine_cs *engine = req->engine;
1395         const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1396         int i, ret;
1397
1398         ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1399         if (ret)
1400                 return ret;
1401
1402         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1403         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1404                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1405
1406                 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
1407                 intel_ring_emit(ring, upper_32_bits(pd_daddr));
1408                 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
1409                 intel_ring_emit(ring, lower_32_bits(pd_daddr));
1410         }
1411
1412         intel_ring_emit(ring, MI_NOOP);
1413         intel_ring_advance(ring);
1414
1415         return 0;
1416 }
1417
1418 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1419                               u64 offset, u32 len,
1420                               unsigned int dispatch_flags)
1421 {
1422         struct intel_ring *ring = req->ring;
1423         bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1424         int ret;
1425
1426         /* Don't rely in hw updating PDPs, specially in lite-restore.
1427          * Ideally, we should set Force PD Restore in ctx descriptor,
1428          * but we can't. Force Restore would be a second option, but
1429          * it is unsafe in case of lite-restore (because the ctx is
1430          * not idle). PML4 is allocated during ppgtt init so this is
1431          * not needed in 48-bit.*/
1432         if (req->ctx->ppgtt &&
1433             (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1434                 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1435                     !intel_vgpu_active(req->i915)) {
1436                         ret = intel_logical_ring_emit_pdps(req);
1437                         if (ret)
1438                                 return ret;
1439                 }
1440
1441                 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1442         }
1443
1444         ret = intel_ring_begin(req, 4);
1445         if (ret)
1446                 return ret;
1447
1448         /* FIXME(BDW): Address space and security selectors. */
1449         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
1450                         (ppgtt<<8) |
1451                         (dispatch_flags & I915_DISPATCH_RS ?
1452                          MI_BATCH_RESOURCE_STREAMER : 0));
1453         intel_ring_emit(ring, lower_32_bits(offset));
1454         intel_ring_emit(ring, upper_32_bits(offset));
1455         intel_ring_emit(ring, MI_NOOP);
1456         intel_ring_advance(ring);
1457
1458         return 0;
1459 }
1460
1461 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1462 {
1463         struct drm_i915_private *dev_priv = engine->i915;
1464         I915_WRITE_IMR(engine,
1465                        ~(engine->irq_enable_mask | engine->irq_keep_mask));
1466         POSTING_READ_FW(RING_IMR(engine->mmio_base));
1467 }
1468
1469 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1470 {
1471         struct drm_i915_private *dev_priv = engine->i915;
1472         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1473 }
1474
1475 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1476 {
1477         struct intel_ring *ring = request->ring;
1478         u32 cmd;
1479         int ret;
1480
1481         ret = intel_ring_begin(request, 4);
1482         if (ret)
1483                 return ret;
1484
1485         cmd = MI_FLUSH_DW + 1;
1486
1487         /* We always require a command barrier so that subsequent
1488          * commands, such as breadcrumb interrupts, are strictly ordered
1489          * wrt the contents of the write cache being flushed to memory
1490          * (and thus being coherent from the CPU).
1491          */
1492         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1493
1494         if (mode & EMIT_INVALIDATE) {
1495                 cmd |= MI_INVALIDATE_TLB;
1496                 if (request->engine->id == VCS)
1497                         cmd |= MI_INVALIDATE_BSD;
1498         }
1499
1500         intel_ring_emit(ring, cmd);
1501         intel_ring_emit(ring,
1502                         I915_GEM_HWS_SCRATCH_ADDR |
1503                         MI_FLUSH_DW_USE_GTT);
1504         intel_ring_emit(ring, 0); /* upper addr */
1505         intel_ring_emit(ring, 0); /* value */
1506         intel_ring_advance(ring);
1507
1508         return 0;
1509 }
1510
1511 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1512                                   u32 mode)
1513 {
1514         struct intel_ring *ring = request->ring;
1515         struct intel_engine_cs *engine = request->engine;
1516         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1517         bool vf_flush_wa = false, dc_flush_wa = false;
1518         u32 flags = 0;
1519         int ret;
1520         int len;
1521
1522         flags |= PIPE_CONTROL_CS_STALL;
1523
1524         if (mode & EMIT_FLUSH) {
1525                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1526                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1527                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1528                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1529         }
1530
1531         if (mode & EMIT_INVALIDATE) {
1532                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1533                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1534                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1535                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1536                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1537                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1538                 flags |= PIPE_CONTROL_QW_WRITE;
1539                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1540
1541                 /*
1542                  * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1543                  * pipe control.
1544                  */
1545                 if (IS_GEN9(request->i915))
1546                         vf_flush_wa = true;
1547
1548                 /* WaForGAMHang:kbl */
1549                 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1550                         dc_flush_wa = true;
1551         }
1552
1553         len = 6;
1554
1555         if (vf_flush_wa)
1556                 len += 6;
1557
1558         if (dc_flush_wa)
1559                 len += 12;
1560
1561         ret = intel_ring_begin(request, len);
1562         if (ret)
1563                 return ret;
1564
1565         if (vf_flush_wa) {
1566                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1567                 intel_ring_emit(ring, 0);
1568                 intel_ring_emit(ring, 0);
1569                 intel_ring_emit(ring, 0);
1570                 intel_ring_emit(ring, 0);
1571                 intel_ring_emit(ring, 0);
1572         }
1573
1574         if (dc_flush_wa) {
1575                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1576                 intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
1577                 intel_ring_emit(ring, 0);
1578                 intel_ring_emit(ring, 0);
1579                 intel_ring_emit(ring, 0);
1580                 intel_ring_emit(ring, 0);
1581         }
1582
1583         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1584         intel_ring_emit(ring, flags);
1585         intel_ring_emit(ring, scratch_addr);
1586         intel_ring_emit(ring, 0);
1587         intel_ring_emit(ring, 0);
1588         intel_ring_emit(ring, 0);
1589
1590         if (dc_flush_wa) {
1591                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1592                 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
1593                 intel_ring_emit(ring, 0);
1594                 intel_ring_emit(ring, 0);
1595                 intel_ring_emit(ring, 0);
1596                 intel_ring_emit(ring, 0);
1597         }
1598
1599         intel_ring_advance(ring);
1600
1601         return 0;
1602 }
1603
1604 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1605 {
1606         /*
1607          * On BXT A steppings there is a HW coherency issue whereby the
1608          * MI_STORE_DATA_IMM storing the completed request's seqno
1609          * occasionally doesn't invalidate the CPU cache. Work around this by
1610          * clflushing the corresponding cacheline whenever the caller wants
1611          * the coherency to be guaranteed. Note that this cacheline is known
1612          * to be clean at this point, since we only write it in
1613          * bxt_a_set_seqno(), where we also do a clflush after the write. So
1614          * this clflush in practice becomes an invalidate operation.
1615          */
1616         intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1617 }
1618
1619 /*
1620  * Reserve space for 2 NOOPs at the end of each request to be
1621  * used as a workaround for not being allowed to do lite
1622  * restore with HEAD==TAIL (WaIdleLiteRestore).
1623  */
1624 #define WA_TAIL_DWORDS 2
1625
1626 static int gen8_emit_request(struct drm_i915_gem_request *request)
1627 {
1628         struct intel_ring *ring = request->ring;
1629         int ret;
1630
1631         ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
1632         if (ret)
1633                 return ret;
1634
1635         /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1636         BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1637
1638         intel_ring_emit(ring, (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1639         intel_ring_emit(ring,
1640                         intel_hws_seqno_address(request->engine) |
1641                         MI_FLUSH_DW_USE_GTT);
1642         intel_ring_emit(ring, 0);
1643         intel_ring_emit(ring, request->fence.seqno);
1644         intel_ring_emit(ring, MI_USER_INTERRUPT);
1645         intel_ring_emit(ring, MI_NOOP);
1646         return intel_logical_ring_advance(request);
1647 }
1648
1649 static int gen8_emit_request_render(struct drm_i915_gem_request *request)
1650 {
1651         struct intel_ring *ring = request->ring;
1652         int ret;
1653
1654         ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
1655         if (ret)
1656                 return ret;
1657
1658         /* We're using qword write, seqno should be aligned to 8 bytes. */
1659         BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1660
1661         /* w/a for post sync ops following a GPGPU operation we
1662          * need a prior CS_STALL, which is emitted by the flush
1663          * following the batch.
1664          */
1665         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1666         intel_ring_emit(ring,
1667                         (PIPE_CONTROL_GLOBAL_GTT_IVB |
1668                          PIPE_CONTROL_CS_STALL |
1669                          PIPE_CONTROL_QW_WRITE));
1670         intel_ring_emit(ring, intel_hws_seqno_address(request->engine));
1671         intel_ring_emit(ring, 0);
1672         intel_ring_emit(ring, i915_gem_request_get_seqno(request));
1673         /* We're thrashing one dword of HWS. */
1674         intel_ring_emit(ring, 0);
1675         intel_ring_emit(ring, MI_USER_INTERRUPT);
1676         intel_ring_emit(ring, MI_NOOP);
1677         return intel_logical_ring_advance(request);
1678 }
1679
1680 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1681 {
1682         int ret;
1683
1684         ret = intel_logical_ring_workarounds_emit(req);
1685         if (ret)
1686                 return ret;
1687
1688         ret = intel_rcs_context_init_mocs(req);
1689         /*
1690          * Failing to program the MOCS is non-fatal.The system will not
1691          * run at peak performance. So generate an error and carry on.
1692          */
1693         if (ret)
1694                 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1695
1696         return i915_gem_render_state_init(req);
1697 }
1698
1699 /**
1700  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1701  * @engine: Engine Command Streamer.
1702  */
1703 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1704 {
1705         struct drm_i915_private *dev_priv;
1706
1707         if (!intel_engine_initialized(engine))
1708                 return;
1709
1710         /*
1711          * Tasklet cannot be active at this point due intel_mark_active/idle
1712          * so this is just for documentation.
1713          */
1714         if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1715                 tasklet_kill(&engine->irq_tasklet);
1716
1717         dev_priv = engine->i915;
1718
1719         if (engine->buffer) {
1720                 intel_logical_ring_stop(engine);
1721                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1722         }
1723
1724         if (engine->cleanup)
1725                 engine->cleanup(engine);
1726
1727         intel_engine_cleanup_common(engine);
1728
1729         if (engine->status_page.obj) {
1730                 i915_gem_object_unpin_map(engine->status_page.obj);
1731                 engine->status_page.obj = NULL;
1732         }
1733         intel_lr_context_unpin(dev_priv->kernel_context, engine);
1734
1735         engine->idle_lite_restore_wa = 0;
1736         engine->disable_lite_restore_wa = false;
1737         engine->ctx_desc_template = 0;
1738
1739         lrc_destroy_wa_ctx_obj(engine);
1740         engine->i915 = NULL;
1741 }
1742
1743 void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
1744 {
1745         struct intel_engine_cs *engine;
1746
1747         for_each_engine(engine, dev_priv)
1748                 engine->submit_request = execlists_submit_request;
1749 }
1750
1751 static void
1752 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1753 {
1754         /* Default vfuncs which can be overriden by each engine. */
1755         engine->init_hw = gen8_init_common_ring;
1756         engine->emit_flush = gen8_emit_flush;
1757         engine->emit_request = gen8_emit_request;
1758         engine->submit_request = execlists_submit_request;
1759
1760         engine->irq_enable = gen8_logical_ring_enable_irq;
1761         engine->irq_disable = gen8_logical_ring_disable_irq;
1762         engine->emit_bb_start = gen8_emit_bb_start;
1763         if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1764                 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1765 }
1766
1767 static inline void
1768 logical_ring_default_irqs(struct intel_engine_cs *engine)
1769 {
1770         unsigned shift = engine->irq_shift;
1771         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1772         engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1773 }
1774
1775 static int
1776 lrc_setup_hws(struct intel_engine_cs *engine,
1777               struct drm_i915_gem_object *dctx_obj)
1778 {
1779         void *hws;
1780
1781         /* The HWSP is part of the default context object in LRC mode. */
1782         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) +
1783                                        LRC_PPHWSP_PN * PAGE_SIZE;
1784         hws = i915_gem_object_pin_map(dctx_obj);
1785         if (IS_ERR(hws))
1786                 return PTR_ERR(hws);
1787         engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE;
1788         engine->status_page.obj = dctx_obj;
1789
1790         return 0;
1791 }
1792
1793 static void
1794 logical_ring_setup(struct intel_engine_cs *engine)
1795 {
1796         struct drm_i915_private *dev_priv = engine->i915;
1797         enum forcewake_domains fw_domains;
1798
1799         intel_engine_setup_common(engine);
1800
1801         /* Intentionally left blank. */
1802         engine->buffer = NULL;
1803
1804         fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1805                                                     RING_ELSP(engine),
1806                                                     FW_REG_WRITE);
1807
1808         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1809                                                      RING_CONTEXT_STATUS_PTR(engine),
1810                                                      FW_REG_READ | FW_REG_WRITE);
1811
1812         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1813                                                      RING_CONTEXT_STATUS_BUF_BASE(engine),
1814                                                      FW_REG_READ);
1815
1816         engine->fw_domains = fw_domains;
1817
1818         tasklet_init(&engine->irq_tasklet,
1819                      intel_lrc_irq_handler, (unsigned long)engine);
1820
1821         logical_ring_init_platform_invariants(engine);
1822         logical_ring_default_vfuncs(engine);
1823         logical_ring_default_irqs(engine);
1824 }
1825
1826 static int
1827 logical_ring_init(struct intel_engine_cs *engine)
1828 {
1829         struct i915_gem_context *dctx = engine->i915->kernel_context;
1830         int ret;
1831
1832         ret = intel_engine_init_common(engine);
1833         if (ret)
1834                 goto error;
1835
1836         ret = execlists_context_deferred_alloc(dctx, engine);
1837         if (ret)
1838                 goto error;
1839
1840         /* As this is the default context, always pin it */
1841         ret = intel_lr_context_pin(dctx, engine);
1842         if (ret) {
1843                 DRM_ERROR("Failed to pin context for %s: %d\n",
1844                           engine->name, ret);
1845                 goto error;
1846         }
1847
1848         /* And setup the hardware status page. */
1849         ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1850         if (ret) {
1851                 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1852                 goto error;
1853         }
1854
1855         return 0;
1856
1857 error:
1858         intel_logical_ring_cleanup(engine);
1859         return ret;
1860 }
1861
1862 int logical_render_ring_init(struct intel_engine_cs *engine)
1863 {
1864         struct drm_i915_private *dev_priv = engine->i915;
1865         int ret;
1866
1867         logical_ring_setup(engine);
1868
1869         if (HAS_L3_DPF(dev_priv))
1870                 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1871
1872         /* Override some for render ring. */
1873         if (INTEL_GEN(dev_priv) >= 9)
1874                 engine->init_hw = gen9_init_render_ring;
1875         else
1876                 engine->init_hw = gen8_init_render_ring;
1877         engine->init_context = gen8_init_rcs_context;
1878         engine->cleanup = intel_fini_pipe_control;
1879         engine->emit_flush = gen8_emit_flush_render;
1880         engine->emit_request = gen8_emit_request_render;
1881
1882         ret = intel_init_pipe_control(engine, 4096);
1883         if (ret)
1884                 return ret;
1885
1886         ret = intel_init_workaround_bb(engine);
1887         if (ret) {
1888                 /*
1889                  * We continue even if we fail to initialize WA batch
1890                  * because we only expect rare glitches but nothing
1891                  * critical to prevent us from using GPU
1892                  */
1893                 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1894                           ret);
1895         }
1896
1897         ret = logical_ring_init(engine);
1898         if (ret) {
1899                 lrc_destroy_wa_ctx_obj(engine);
1900         }
1901
1902         return ret;
1903 }
1904
1905 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1906 {
1907         logical_ring_setup(engine);
1908
1909         return logical_ring_init(engine);
1910 }
1911
1912 static u32
1913 make_rpcs(struct drm_i915_private *dev_priv)
1914 {
1915         u32 rpcs = 0;
1916
1917         /*
1918          * No explicit RPCS request is needed to ensure full
1919          * slice/subslice/EU enablement prior to Gen9.
1920         */
1921         if (INTEL_GEN(dev_priv) < 9)
1922                 return 0;
1923
1924         /*
1925          * Starting in Gen9, render power gating can leave
1926          * slice/subslice/EU in a partially enabled state. We
1927          * must make an explicit request through RPCS for full
1928          * enablement.
1929         */
1930         if (INTEL_INFO(dev_priv)->has_slice_pg) {
1931                 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1932                 rpcs |= INTEL_INFO(dev_priv)->slice_total <<
1933                         GEN8_RPCS_S_CNT_SHIFT;
1934                 rpcs |= GEN8_RPCS_ENABLE;
1935         }
1936
1937         if (INTEL_INFO(dev_priv)->has_subslice_pg) {
1938                 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1939                 rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
1940                         GEN8_RPCS_SS_CNT_SHIFT;
1941                 rpcs |= GEN8_RPCS_ENABLE;
1942         }
1943
1944         if (INTEL_INFO(dev_priv)->has_eu_pg) {
1945                 rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
1946                         GEN8_RPCS_EU_MIN_SHIFT;
1947                 rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
1948                         GEN8_RPCS_EU_MAX_SHIFT;
1949                 rpcs |= GEN8_RPCS_ENABLE;
1950         }
1951
1952         return rpcs;
1953 }
1954
1955 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1956 {
1957         u32 indirect_ctx_offset;
1958
1959         switch (INTEL_GEN(engine->i915)) {
1960         default:
1961                 MISSING_CASE(INTEL_GEN(engine->i915));
1962                 /* fall through */
1963         case 9:
1964                 indirect_ctx_offset =
1965                         GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1966                 break;
1967         case 8:
1968                 indirect_ctx_offset =
1969                         GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1970                 break;
1971         }
1972
1973         return indirect_ctx_offset;
1974 }
1975
1976 static int
1977 populate_lr_context(struct i915_gem_context *ctx,
1978                     struct drm_i915_gem_object *ctx_obj,
1979                     struct intel_engine_cs *engine,
1980                     struct intel_ring *ring)
1981 {
1982         struct drm_i915_private *dev_priv = ctx->i915;
1983         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1984         void *vaddr;
1985         u32 *reg_state;
1986         int ret;
1987
1988         if (!ppgtt)
1989                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1990
1991         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1992         if (ret) {
1993                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1994                 return ret;
1995         }
1996
1997         vaddr = i915_gem_object_pin_map(ctx_obj);
1998         if (IS_ERR(vaddr)) {
1999                 ret = PTR_ERR(vaddr);
2000                 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2001                 return ret;
2002         }
2003         ctx_obj->dirty = true;
2004
2005         /* The second page of the context object contains some fields which must
2006          * be set up prior to the first execution. */
2007         reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2008
2009         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2010          * commands followed by (reg, value) pairs. The values we are setting here are
2011          * only for the first context restore: on a subsequent save, the GPU will
2012          * recreate this batchbuffer with new values (including all the missing
2013          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2014         reg_state[CTX_LRI_HEADER_0] =
2015                 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2016         ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2017                        RING_CONTEXT_CONTROL(engine),
2018                        _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2019                                           CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2020                                           (HAS_RESOURCE_STREAMER(dev_priv) ?
2021                                             CTX_CTRL_RS_CTX_ENABLE : 0)));
2022         ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2023                        0);
2024         ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2025                        0);
2026         /* Ring buffer start address is not known until the buffer is pinned.
2027          * It is written to the context image in execlists_update_context()
2028          */
2029         ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2030                        RING_START(engine->mmio_base), 0);
2031         ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2032                        RING_CTL(engine->mmio_base),
2033                        ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2034         ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2035                        RING_BBADDR_UDW(engine->mmio_base), 0);
2036         ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2037                        RING_BBADDR(engine->mmio_base), 0);
2038         ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2039                        RING_BBSTATE(engine->mmio_base),
2040                        RING_BB_PPGTT);
2041         ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2042                        RING_SBBADDR_UDW(engine->mmio_base), 0);
2043         ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2044                        RING_SBBADDR(engine->mmio_base), 0);
2045         ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2046                        RING_SBBSTATE(engine->mmio_base), 0);
2047         if (engine->id == RCS) {
2048                 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2049                                RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2050                 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2051                                RING_INDIRECT_CTX(engine->mmio_base), 0);
2052                 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2053                                RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2054                 if (engine->wa_ctx.obj) {
2055                         struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2056                         uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2057
2058                         reg_state[CTX_RCS_INDIRECT_CTX+1] =
2059                                 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2060                                 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2061
2062                         reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2063                                 intel_lr_indirect_ctx_offset(engine) << 6;
2064
2065                         reg_state[CTX_BB_PER_CTX_PTR+1] =
2066                                 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2067                                 0x01;
2068                 }
2069         }
2070         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2071         ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2072                        RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2073         /* PDP values well be assigned later if needed */
2074         ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2075                        0);
2076         ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2077                        0);
2078         ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2079                        0);
2080         ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2081                        0);
2082         ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2083                        0);
2084         ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2085                        0);
2086         ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2087                        0);
2088         ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2089                        0);
2090
2091         if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2092                 /* 64b PPGTT (48bit canonical)
2093                  * PDP0_DESCRIPTOR contains the base address to PML4 and
2094                  * other PDP Descriptors are ignored.
2095                  */
2096                 ASSIGN_CTX_PML4(ppgtt, reg_state);
2097         } else {
2098                 /* 32b PPGTT
2099                  * PDP*_DESCRIPTOR contains the base address of space supported.
2100                  * With dynamic page allocation, PDPs may not be allocated at
2101                  * this point. Point the unallocated PDPs to the scratch page
2102                  */
2103                 execlists_update_context_pdps(ppgtt, reg_state);
2104         }
2105
2106         if (engine->id == RCS) {
2107                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2108                 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2109                                make_rpcs(dev_priv));
2110         }
2111
2112         i915_gem_object_unpin_map(ctx_obj);
2113
2114         return 0;
2115 }
2116
2117 /**
2118  * intel_lr_context_size() - return the size of the context for an engine
2119  * @engine: which engine to find the context size for
2120  *
2121  * Each engine may require a different amount of space for a context image,
2122  * so when allocating (or copying) an image, this function can be used to
2123  * find the right size for the specific engine.
2124  *
2125  * Return: size (in bytes) of an engine-specific context image
2126  *
2127  * Note: this size includes the HWSP, which is part of the context image
2128  * in LRC mode, but does not include the "shared data page" used with
2129  * GuC submission. The caller should account for this if using the GuC.
2130  */
2131 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2132 {
2133         int ret = 0;
2134
2135         WARN_ON(INTEL_GEN(engine->i915) < 8);
2136
2137         switch (engine->id) {
2138         case RCS:
2139                 if (INTEL_GEN(engine->i915) >= 9)
2140                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2141                 else
2142                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2143                 break;
2144         case VCS:
2145         case BCS:
2146         case VECS:
2147         case VCS2:
2148                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2149                 break;
2150         }
2151
2152         return ret;
2153 }
2154
2155 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2156                                             struct intel_engine_cs *engine)
2157 {
2158         struct drm_i915_gem_object *ctx_obj;
2159         struct intel_context *ce = &ctx->engine[engine->id];
2160         uint32_t context_size;
2161         struct intel_ring *ring;
2162         int ret;
2163
2164         WARN_ON(ce->state);
2165
2166         context_size = round_up(intel_lr_context_size(engine), 4096);
2167
2168         /* One extra page as the sharing data between driver and GuC */
2169         context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2170
2171         ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size);
2172         if (IS_ERR(ctx_obj)) {
2173                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2174                 return PTR_ERR(ctx_obj);
2175         }
2176
2177         ring = intel_engine_create_ring(engine, ctx->ring_size);
2178         if (IS_ERR(ring)) {
2179                 ret = PTR_ERR(ring);
2180                 goto error_deref_obj;
2181         }
2182
2183         ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2184         if (ret) {
2185                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2186                 goto error_ring_free;
2187         }
2188
2189         ce->ring = ring;
2190         ce->state = ctx_obj;
2191         ce->initialised = engine->init_context == NULL;
2192
2193         return 0;
2194
2195 error_ring_free:
2196         intel_ring_free(ring);
2197 error_deref_obj:
2198         i915_gem_object_put(ctx_obj);
2199         ce->ring = NULL;
2200         ce->state = NULL;
2201         return ret;
2202 }
2203
2204 void intel_lr_context_reset(struct drm_i915_private *dev_priv,
2205                             struct i915_gem_context *ctx)
2206 {
2207         struct intel_engine_cs *engine;
2208
2209         for_each_engine(engine, dev_priv) {
2210                 struct intel_context *ce = &ctx->engine[engine->id];
2211                 struct drm_i915_gem_object *ctx_obj = ce->state;
2212                 void *vaddr;
2213                 uint32_t *reg_state;
2214
2215                 if (!ctx_obj)
2216                         continue;
2217
2218                 vaddr = i915_gem_object_pin_map(ctx_obj);
2219                 if (WARN_ON(IS_ERR(vaddr)))
2220                         continue;
2221
2222                 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2223                 ctx_obj->dirty = true;
2224
2225                 reg_state[CTX_RING_HEAD+1] = 0;
2226                 reg_state[CTX_RING_TAIL+1] = 0;
2227
2228                 i915_gem_object_unpin_map(ctx_obj);
2229
2230                 ce->ring->head = 0;
2231                 ce->ring->tail = 0;
2232         }
2233 }