2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT = 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT, /* Debug only */
224 FAULT_AND_CONTINUE /* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
230 static int intel_lr_context_pin(struct intel_context *ctx,
231 struct intel_engine_cs *engine);
232 static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
233 struct drm_i915_gem_object *default_ctx_obj);
237 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
239 * @enable_execlists: value of i915.enable_execlists module parameter.
241 * Only certain platforms support Execlists (the prerequisites being
242 * support for Logical Ring Contexts and Aliasing PPGTT or better).
244 * Return: 1 if Execlists is supported and has to be enabled.
246 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
248 WARN_ON(i915.enable_ppgtt == -1);
250 /* On platforms with execlist available, vGPU will only
251 * support execlist mode, no ring buffer mode.
253 if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
256 if (INTEL_INFO(dev)->gen >= 9)
259 if (enable_execlists == 0)
262 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
263 i915.use_mmio_flip >= 0)
270 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
272 struct drm_device *dev = engine->dev;
274 if (IS_GEN8(dev) || IS_GEN9(dev))
275 engine->idle_lite_restore_wa = ~0;
277 engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
278 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
279 (engine->id == VCS || engine->id == VCS2);
281 engine->ctx_desc_template = GEN8_CTX_VALID;
282 engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
283 GEN8_CTX_ADDRESSING_MODE_SHIFT;
285 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
286 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
288 /* TODO: WaDisableLiteRestore when we start using semaphore
289 * signalling between Command Streamers */
290 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
292 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
293 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
294 if (engine->disable_lite_restore_wa)
295 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
299 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
300 * descriptor for a pinned context
302 * @ctx: Context to work on
303 * @ring: Engine the descriptor will be used with
305 * The context descriptor encodes various attributes of a context,
306 * including its GTT address and some flags. Because it's fairly
307 * expensive to calculate, we'll just do it once and cache the result,
308 * which remains valid until the context is unpinned.
310 * This is what a descriptor looks like, from LSB to MSB:
311 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
312 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
313 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
314 * bits 52-63: reserved, may encode the engine ID (for GuC)
317 intel_lr_context_descriptor_update(struct intel_context *ctx,
318 struct intel_engine_cs *engine)
322 lrca = ctx->engine[engine->id].lrc_vma->node.start +
323 LRC_PPHWSP_PN * PAGE_SIZE;
325 desc = engine->ctx_desc_template; /* bits 0-11 */
326 desc |= lrca; /* bits 12-31 */
327 desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
329 ctx->engine[engine->id].lrc_desc = desc;
332 uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
333 struct intel_engine_cs *engine)
335 return ctx->engine[engine->id].lrc_desc;
339 * intel_execlists_ctx_id() - get the Execlists Context ID
340 * @ctx: Context to get the ID for
341 * @ring: Engine to get the ID for
343 * Do not confuse with ctx->id! Unfortunately we have a name overload
344 * here: the old context ID we pass to userspace as a handler so that
345 * they can refer to a context, and the new context ID we pass to the
346 * ELSP so that the GPU can inform us of the context status via
349 * The context ID is a portion of the context descriptor, so we can
350 * just extract the required part from the cached descriptor.
352 * Return: 20-bits globally unique context ID.
354 u32 intel_execlists_ctx_id(struct intel_context *ctx,
355 struct intel_engine_cs *engine)
357 return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT;
360 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
361 struct drm_i915_gem_request *rq1)
364 struct intel_engine_cs *engine = rq0->engine;
365 struct drm_device *dev = engine->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
370 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
371 rq1->elsp_submitted++;
376 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
377 rq0->elsp_submitted++;
379 /* You must always write both descriptors in the order below. */
380 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
381 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
383 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
384 /* The context is automatically loaded after the following */
385 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
387 /* ELSP is a wo register, use another nearby reg for posting */
388 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
392 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
394 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
395 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
396 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
397 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
400 static void execlists_update_context(struct drm_i915_gem_request *rq)
402 struct intel_engine_cs *engine = rq->engine;
403 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
404 uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
406 reg_state[CTX_RING_TAIL+1] = rq->tail;
408 /* True 32b PPGTT with dynamic page allocation: update PDP
409 * registers and point the unallocated PDPs to scratch page.
410 * PML4 is allocated during ppgtt init, so this is not needed
413 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
414 execlists_update_context_pdps(ppgtt, reg_state);
417 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
418 struct drm_i915_gem_request *rq1)
420 struct drm_i915_private *dev_priv = rq0->i915;
422 execlists_update_context(rq0);
425 execlists_update_context(rq1);
427 spin_lock_irq(&dev_priv->uncore.lock);
428 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
430 execlists_elsp_write(rq0, rq1);
432 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
433 spin_unlock_irq(&dev_priv->uncore.lock);
436 static void execlists_context_unqueue(struct intel_engine_cs *engine)
438 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
439 struct drm_i915_gem_request *cursor, *tmp;
441 assert_spin_locked(&engine->execlist_lock);
444 * If irqs are not active generate a warning as batches that finish
445 * without the irqs may get lost and a GPU Hang may occur.
447 WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
449 /* Try to read in pairs */
450 list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
454 } else if (req0->ctx == cursor->ctx) {
455 /* Same ctx: ignore first request, as second request
456 * will update tail past first request's workload */
457 cursor->elsp_submitted = req0->elsp_submitted;
458 list_move_tail(&req0->execlist_link,
459 &engine->execlist_retired_req_list);
463 WARN_ON(req1->elsp_submitted);
471 if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
473 * WaIdleLiteRestore: make sure we never cause a lite restore
476 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
477 * resubmit the request. See gen8_emit_request() for where we
478 * prepare the padding after the end of the request.
480 struct intel_ringbuffer *ringbuf;
482 ringbuf = req0->ctx->engine[engine->id].ringbuf;
484 req0->tail &= ringbuf->size - 1;
487 execlists_submit_requests(req0, req1);
491 execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id)
493 struct drm_i915_gem_request *head_req;
495 assert_spin_locked(&engine->execlist_lock);
497 head_req = list_first_entry_or_null(&engine->execlist_queue,
498 struct drm_i915_gem_request,
504 if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id))
507 WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
509 if (--head_req->elsp_submitted > 0)
512 list_move_tail(&head_req->execlist_link,
513 &engine->execlist_retired_req_list);
519 get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
522 struct drm_i915_private *dev_priv = engine->dev->dev_private;
525 read_pointer %= GEN8_CSB_ENTRIES;
527 status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
529 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
532 *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
539 * intel_lrc_irq_handler() - handle Context Switch interrupts
540 * @engine: Engine Command Streamer to handle.
542 * Check the unread Context Status Buffers and manage the submission of new
543 * contexts to the ELSP accordingly.
545 static void intel_lrc_irq_handler(unsigned long data)
547 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
548 struct drm_i915_private *dev_priv = engine->dev->dev_private;
550 unsigned int read_pointer, write_pointer;
551 u32 csb[GEN8_CSB_ENTRIES][2];
552 unsigned int csb_read = 0, i;
553 unsigned int submit_contexts = 0;
555 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
557 status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
559 read_pointer = engine->next_context_status_buffer;
560 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
561 if (read_pointer > write_pointer)
562 write_pointer += GEN8_CSB_ENTRIES;
564 while (read_pointer < write_pointer) {
565 if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
567 csb[csb_read][0] = get_context_status(engine, ++read_pointer,
572 engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
574 /* Update the read pointer to the old write pointer. Manual ringbuffer
575 * management ftw </sarcasm> */
576 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
577 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
578 engine->next_context_status_buffer << 8));
580 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
582 spin_lock(&engine->execlist_lock);
584 for (i = 0; i < csb_read; i++) {
585 if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
586 if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
587 if (execlists_check_remove_request(engine, csb[i][1]))
588 WARN(1, "Lite Restored request removed from queue\n");
590 WARN(1, "Preemption without Lite Restore\n");
593 if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
594 GEN8_CTX_STATUS_ELEMENT_SWITCH))
596 execlists_check_remove_request(engine, csb[i][1]);
599 if (submit_contexts) {
600 if (!engine->disable_lite_restore_wa ||
601 (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
602 execlists_context_unqueue(engine);
605 spin_unlock(&engine->execlist_lock);
607 if (unlikely(submit_contexts > 2))
608 DRM_ERROR("More than two context complete events?\n");
611 static void execlists_context_queue(struct drm_i915_gem_request *request)
613 struct intel_engine_cs *engine = request->engine;
614 struct drm_i915_gem_request *cursor;
615 int num_elements = 0;
617 if (request->ctx != request->i915->kernel_context)
618 intel_lr_context_pin(request->ctx, engine);
620 i915_gem_request_reference(request);
622 spin_lock_bh(&engine->execlist_lock);
624 list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
625 if (++num_elements > 2)
628 if (num_elements > 2) {
629 struct drm_i915_gem_request *tail_req;
631 tail_req = list_last_entry(&engine->execlist_queue,
632 struct drm_i915_gem_request,
635 if (request->ctx == tail_req->ctx) {
636 WARN(tail_req->elsp_submitted != 0,
637 "More than 2 already-submitted reqs queued\n");
638 list_move_tail(&tail_req->execlist_link,
639 &engine->execlist_retired_req_list);
643 list_add_tail(&request->execlist_link, &engine->execlist_queue);
644 if (num_elements == 0)
645 execlists_context_unqueue(engine);
647 spin_unlock_bh(&engine->execlist_lock);
650 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
652 struct intel_engine_cs *engine = req->engine;
653 uint32_t flush_domains;
657 if (engine->gpu_caches_dirty)
658 flush_domains = I915_GEM_GPU_DOMAINS;
660 ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
664 engine->gpu_caches_dirty = false;
668 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
669 struct list_head *vmas)
671 const unsigned other_rings = ~intel_engine_flag(req->engine);
672 struct i915_vma *vma;
673 uint32_t flush_domains = 0;
674 bool flush_chipset = false;
677 list_for_each_entry(vma, vmas, exec_list) {
678 struct drm_i915_gem_object *obj = vma->obj;
680 if (obj->active & other_rings) {
681 ret = i915_gem_object_sync(obj, req->engine, &req);
686 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
687 flush_chipset |= i915_gem_clflush_object(obj, false);
689 flush_domains |= obj->base.write_domain;
692 if (flush_domains & I915_GEM_DOMAIN_GTT)
695 /* Unconditionally invalidate gpu caches and ensure that we do flush
696 * any residual writes from the previous batch.
698 return logical_ring_invalidate_all_caches(req);
701 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
705 request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
707 if (i915.enable_guc_submission) {
709 * Check that the GuC has space for the request before
710 * going any further, as the i915_add_request() call
711 * later on mustn't fail ...
713 struct intel_guc *guc = &request->i915->guc;
715 ret = i915_guc_wq_check_space(guc->execbuf_client);
720 if (request->ctx != request->i915->kernel_context)
721 ret = intel_lr_context_pin(request->ctx, request->engine);
726 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
729 struct intel_ringbuffer *ringbuf = req->ringbuf;
730 struct intel_engine_cs *engine = req->engine;
731 struct drm_i915_gem_request *target;
735 if (intel_ring_space(ringbuf) >= bytes)
738 /* The whole point of reserving space is to not wait! */
739 WARN_ON(ringbuf->reserved_in_use);
741 list_for_each_entry(target, &engine->request_list, list) {
743 * The request queue is per-engine, so can contain requests
744 * from multiple ringbuffers. Here, we must ignore any that
745 * aren't from the ringbuffer we're considering.
747 if (target->ringbuf != ringbuf)
750 /* Would completion of this request free enough space? */
751 space = __intel_ring_space(target->postfix, ringbuf->tail,
757 if (WARN_ON(&target->list == &engine->request_list))
760 ret = i915_wait_request(target);
764 ringbuf->space = space;
769 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
770 * @request: Request to advance the logical ringbuffer of.
772 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
773 * really happens during submission is that the context and current tail will be placed
774 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
775 * point, the tail *inside* the context is updated and the ELSP written to.
778 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
780 struct intel_ringbuffer *ringbuf = request->ringbuf;
781 struct drm_i915_private *dev_priv = request->i915;
782 struct intel_engine_cs *engine = request->engine;
784 intel_logical_ring_advance(ringbuf);
785 request->tail = ringbuf->tail;
788 * Here we add two extra NOOPs as padding to avoid
789 * lite restore of a context with HEAD==TAIL.
791 * Caller must reserve WA_TAIL_DWORDS for us!
793 intel_logical_ring_emit(ringbuf, MI_NOOP);
794 intel_logical_ring_emit(ringbuf, MI_NOOP);
795 intel_logical_ring_advance(ringbuf);
797 if (intel_engine_stopped(engine))
800 if (engine->last_context != request->ctx) {
801 if (engine->last_context)
802 intel_lr_context_unpin(engine->last_context, engine);
803 if (request->ctx != request->i915->kernel_context) {
804 intel_lr_context_pin(request->ctx, engine);
805 engine->last_context = request->ctx;
807 engine->last_context = NULL;
811 if (dev_priv->guc.execbuf_client)
812 i915_guc_submit(dev_priv->guc.execbuf_client, request);
814 execlists_context_queue(request);
819 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
821 uint32_t __iomem *virt;
822 int rem = ringbuf->size - ringbuf->tail;
824 virt = ringbuf->virtual_start + ringbuf->tail;
827 iowrite32(MI_NOOP, virt++);
830 intel_ring_update_space(ringbuf);
833 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
835 struct intel_ringbuffer *ringbuf = req->ringbuf;
836 int remain_usable = ringbuf->effective_size - ringbuf->tail;
837 int remain_actual = ringbuf->size - ringbuf->tail;
838 int ret, total_bytes, wait_bytes = 0;
839 bool need_wrap = false;
841 if (ringbuf->reserved_in_use)
844 total_bytes = bytes + ringbuf->reserved_size;
846 if (unlikely(bytes > remain_usable)) {
848 * Not enough space for the basic request. So need to flush
849 * out the remainder and then wait for base + reserved.
851 wait_bytes = remain_actual + total_bytes;
854 if (unlikely(total_bytes > remain_usable)) {
856 * The base request will fit but the reserved space
857 * falls off the end. So only need to to wait for the
858 * reserved size after flushing out the remainder.
860 wait_bytes = remain_actual + ringbuf->reserved_size;
862 } else if (total_bytes > ringbuf->space) {
863 /* No wrapping required, just waiting. */
864 wait_bytes = total_bytes;
869 ret = logical_ring_wait_for_space(req, wait_bytes);
874 __wrap_ring_buffer(ringbuf);
881 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
883 * @req: The request to start some new work for
884 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
886 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
887 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
888 * and also preallocates a request (every workload submission is still mediated through
889 * requests, same as it did with legacy ringbuffer submission).
891 * Return: non-zero if the ringbuffer is not ready to be written to.
893 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
895 struct drm_i915_private *dev_priv;
898 WARN_ON(req == NULL);
899 dev_priv = req->i915;
901 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
902 dev_priv->mm.interruptible);
906 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
910 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
914 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
917 * The first call merely notes the reserve request and is common for
918 * all back ends. The subsequent localised _begin() call actually
919 * ensures that the reservation is available. Without the begin, if
920 * the request creator immediately submitted the request without
921 * adding any commands to it then there might not actually be
922 * sufficient room for the submission commands.
924 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
926 return intel_logical_ring_begin(request, 0);
930 * execlists_submission() - submit a batchbuffer for execution, Execlists style
933 * @ring: Engine Command Streamer to submit to.
934 * @ctx: Context to employ for this submission.
935 * @args: execbuffer call arguments.
936 * @vmas: list of vmas.
937 * @batch_obj: the batchbuffer to submit.
938 * @exec_start: batchbuffer start virtual address pointer.
939 * @dispatch_flags: translated execbuffer call flags.
941 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
942 * away the submission details of the execbuffer ioctl call.
944 * Return: non-zero if the submission fails.
946 int intel_execlists_submission(struct i915_execbuffer_params *params,
947 struct drm_i915_gem_execbuffer2 *args,
948 struct list_head *vmas)
950 struct drm_device *dev = params->dev;
951 struct intel_engine_cs *engine = params->engine;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
959 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
960 instp_mask = I915_EXEC_CONSTANTS_MASK;
961 switch (instp_mode) {
962 case I915_EXEC_CONSTANTS_REL_GENERAL:
963 case I915_EXEC_CONSTANTS_ABSOLUTE:
964 case I915_EXEC_CONSTANTS_REL_SURFACE:
965 if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
966 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
970 if (instp_mode != dev_priv->relative_constants_mode) {
971 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
972 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
976 /* The HW changed the meaning on this bit on gen6 */
977 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
981 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
985 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
986 DRM_DEBUG("sol reset is gen7 only\n");
990 ret = execlists_move_to_gpu(params->request, vmas);
994 if (engine == &dev_priv->engine[RCS] &&
995 instp_mode != dev_priv->relative_constants_mode) {
996 ret = intel_logical_ring_begin(params->request, 4);
1000 intel_logical_ring_emit(ringbuf, MI_NOOP);
1001 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
1002 intel_logical_ring_emit_reg(ringbuf, INSTPM);
1003 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
1004 intel_logical_ring_advance(ringbuf);
1006 dev_priv->relative_constants_mode = instp_mode;
1009 exec_start = params->batch_obj_vm_offset +
1010 args->batch_start_offset;
1012 ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
1016 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1018 i915_gem_execbuffer_move_to_active(vmas, params->request);
1019 i915_gem_execbuffer_retire_commands(params);
1024 void intel_execlists_retire_requests(struct intel_engine_cs *engine)
1026 struct drm_i915_gem_request *req, *tmp;
1027 struct list_head retired_list;
1029 WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
1030 if (list_empty(&engine->execlist_retired_req_list))
1033 INIT_LIST_HEAD(&retired_list);
1034 spin_lock_bh(&engine->execlist_lock);
1035 list_replace_init(&engine->execlist_retired_req_list, &retired_list);
1036 spin_unlock_bh(&engine->execlist_lock);
1038 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
1039 struct intel_context *ctx = req->ctx;
1040 struct drm_i915_gem_object *ctx_obj =
1041 ctx->engine[engine->id].state;
1043 if (ctx_obj && (ctx != req->i915->kernel_context))
1044 intel_lr_context_unpin(ctx, engine);
1046 list_del(&req->execlist_link);
1047 i915_gem_request_unreference(req);
1051 void intel_logical_ring_stop(struct intel_engine_cs *engine)
1053 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1056 if (!intel_engine_initialized(engine))
1059 ret = intel_engine_idle(engine);
1060 if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
1061 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1064 /* TODO: Is this correct with Execlists enabled? */
1065 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
1066 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
1067 DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
1070 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
1073 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1075 struct intel_engine_cs *engine = req->engine;
1078 if (!engine->gpu_caches_dirty)
1081 ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1085 engine->gpu_caches_dirty = false;
1089 static int intel_lr_context_do_pin(struct intel_context *ctx,
1090 struct intel_engine_cs *engine)
1092 struct drm_device *dev = engine->dev;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1095 struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf;
1096 struct page *lrc_state_page;
1097 uint32_t *lrc_reg_state;
1100 WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
1102 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
1103 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
1107 lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
1108 if (WARN_ON(!lrc_state_page)) {
1113 ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
1117 ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
1118 intel_lr_context_descriptor_update(ctx, engine);
1119 lrc_reg_state = kmap(lrc_state_page);
1120 lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
1121 ctx->engine[engine->id].lrc_reg_state = lrc_reg_state;
1122 ctx_obj->dirty = true;
1124 /* Invalidate GuC TLB. */
1125 if (i915.enable_guc_submission)
1126 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1131 i915_gem_object_ggtt_unpin(ctx_obj);
1136 static int intel_lr_context_pin(struct intel_context *ctx,
1137 struct intel_engine_cs *engine)
1141 if (ctx->engine[engine->id].pin_count++ == 0) {
1142 ret = intel_lr_context_do_pin(ctx, engine);
1144 goto reset_pin_count;
1146 i915_gem_context_reference(ctx);
1151 ctx->engine[engine->id].pin_count = 0;
1155 void intel_lr_context_unpin(struct intel_context *ctx,
1156 struct intel_engine_cs *engine)
1158 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1160 WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex));
1161 if (--ctx->engine[engine->id].pin_count == 0) {
1162 kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state));
1163 intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1164 i915_gem_object_ggtt_unpin(ctx_obj);
1165 ctx->engine[engine->id].lrc_vma = NULL;
1166 ctx->engine[engine->id].lrc_desc = 0;
1167 ctx->engine[engine->id].lrc_reg_state = NULL;
1169 i915_gem_context_unreference(ctx);
1173 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1176 struct intel_engine_cs *engine = req->engine;
1177 struct intel_ringbuffer *ringbuf = req->ringbuf;
1178 struct drm_device *dev = engine->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct i915_workarounds *w = &dev_priv->workarounds;
1185 engine->gpu_caches_dirty = true;
1186 ret = logical_ring_flush_all_caches(req);
1190 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1194 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1195 for (i = 0; i < w->count; i++) {
1196 intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1197 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1199 intel_logical_ring_emit(ringbuf, MI_NOOP);
1201 intel_logical_ring_advance(ringbuf);
1203 engine->gpu_caches_dirty = true;
1204 ret = logical_ring_flush_all_caches(req);
1211 #define wa_ctx_emit(batch, index, cmd) \
1213 int __index = (index)++; \
1214 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1217 batch[__index] = (cmd); \
1220 #define wa_ctx_emit_reg(batch, index, reg) \
1221 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1224 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1225 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1226 * but there is a slight complication as this is applied in WA batch where the
1227 * values are only initialized once so we cannot take register value at the
1228 * beginning and reuse it further; hence we save its value to memory, upload a
1229 * constant value with bit21 set and then we restore it back with the saved value.
1230 * To simplify the WA, a constant value is formed by using the default value
1231 * of this register. This shouldn't be a problem because we are only modifying
1232 * it for a short period and this batch in non-premptible. We can ofcourse
1233 * use additional instructions that read the actual value of the register
1234 * at that time and set our bit of interest but it makes the WA complicated.
1236 * This WA is also required for Gen9 so extracting as a function avoids
1239 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
1240 uint32_t *const batch,
1243 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1246 * WaDisableLSQCROPERFforOCL:skl
1247 * This WA is implemented in skl_init_clock_gating() but since
1248 * this batch updates GEN8_L3SQCREG4 with default value we need to
1249 * set this bit here to retain the WA during flush.
1251 if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1252 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1254 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1255 MI_SRM_LRM_GLOBAL_GTT));
1256 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1257 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1258 wa_ctx_emit(batch, index, 0);
1260 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1261 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1262 wa_ctx_emit(batch, index, l3sqc4_flush);
1264 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1265 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1266 PIPE_CONTROL_DC_FLUSH_ENABLE));
1267 wa_ctx_emit(batch, index, 0);
1268 wa_ctx_emit(batch, index, 0);
1269 wa_ctx_emit(batch, index, 0);
1270 wa_ctx_emit(batch, index, 0);
1272 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1273 MI_SRM_LRM_GLOBAL_GTT));
1274 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1275 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1276 wa_ctx_emit(batch, index, 0);
1281 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1283 uint32_t start_alignment)
1285 return wa_ctx->offset = ALIGN(offset, start_alignment);
1288 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1290 uint32_t size_alignment)
1292 wa_ctx->size = offset - wa_ctx->offset;
1294 WARN(wa_ctx->size % size_alignment,
1295 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1296 wa_ctx->size, size_alignment);
1301 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1303 * @ring: only applicable for RCS
1304 * @wa_ctx: structure representing wa_ctx
1305 * offset: specifies start of the batch, should be cache-aligned. This is updated
1306 * with the offset value received as input.
1307 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1308 * @batch: page in which WA are loaded
1309 * @offset: This field specifies the start of the batch, it should be
1310 * cache-aligned otherwise it is adjusted accordingly.
1311 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1312 * initialized at the beginning and shared across all contexts but this field
1313 * helps us to have multiple batches at different offsets and select them based
1314 * on a criteria. At the moment this batch always start at the beginning of the page
1315 * and at this point we don't have multiple wa_ctx batch buffers.
1317 * The number of WA applied are not known at the beginning; we use this field
1318 * to return the no of DWORDS written.
1320 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1321 * so it adds NOOPs as padding to make it cacheline aligned.
1322 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1323 * makes a complete batch buffer.
1325 * Return: non-zero if we exceed the PAGE_SIZE limit.
1328 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1329 struct i915_wa_ctx_bb *wa_ctx,
1330 uint32_t *const batch,
1333 uint32_t scratch_addr;
1334 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1336 /* WaDisableCtxRestoreArbitration:bdw,chv */
1337 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1339 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1340 if (IS_BROADWELL(engine->dev)) {
1341 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1347 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1348 /* Actual scratch location is at 128 bytes offset */
1349 scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1351 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1352 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1353 PIPE_CONTROL_GLOBAL_GTT_IVB |
1354 PIPE_CONTROL_CS_STALL |
1355 PIPE_CONTROL_QW_WRITE));
1356 wa_ctx_emit(batch, index, scratch_addr);
1357 wa_ctx_emit(batch, index, 0);
1358 wa_ctx_emit(batch, index, 0);
1359 wa_ctx_emit(batch, index, 0);
1361 /* Pad to end of cacheline */
1362 while (index % CACHELINE_DWORDS)
1363 wa_ctx_emit(batch, index, MI_NOOP);
1366 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1367 * execution depends on the length specified in terms of cache lines
1368 * in the register CTX_RCS_INDIRECT_CTX
1371 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1375 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1377 * @ring: only applicable for RCS
1378 * @wa_ctx: structure representing wa_ctx
1379 * offset: specifies start of the batch, should be cache-aligned.
1380 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1381 * @batch: page in which WA are loaded
1382 * @offset: This field specifies the start of this batch.
1383 * This batch is started immediately after indirect_ctx batch. Since we ensure
1384 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1386 * The number of DWORDS written are returned using this field.
1388 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1389 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1391 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1392 struct i915_wa_ctx_bb *wa_ctx,
1393 uint32_t *const batch,
1396 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1398 /* WaDisableCtxRestoreArbitration:bdw,chv */
1399 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1401 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1403 return wa_ctx_end(wa_ctx, *offset = index, 1);
1406 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1407 struct i915_wa_ctx_bb *wa_ctx,
1408 uint32_t *const batch,
1412 struct drm_device *dev = engine->dev;
1413 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1415 /* WaDisableCtxRestoreArbitration:skl,bxt */
1416 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1417 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1418 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1420 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1421 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1426 /* Pad to end of cacheline */
1427 while (index % CACHELINE_DWORDS)
1428 wa_ctx_emit(batch, index, MI_NOOP);
1430 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1433 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1434 struct i915_wa_ctx_bb *wa_ctx,
1435 uint32_t *const batch,
1438 struct drm_device *dev = engine->dev;
1439 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1441 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1442 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
1443 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1444 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1445 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1446 wa_ctx_emit(batch, index,
1447 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1448 wa_ctx_emit(batch, index, MI_NOOP);
1451 /* WaDisableCtxRestoreArbitration:skl,bxt */
1452 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
1453 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1454 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1456 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1458 return wa_ctx_end(wa_ctx, *offset = index, 1);
1461 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1465 engine->wa_ctx.obj = i915_gem_alloc_object(engine->dev,
1467 if (!engine->wa_ctx.obj) {
1468 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1472 ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0);
1474 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1476 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1483 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1485 if (engine->wa_ctx.obj) {
1486 i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
1487 drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1488 engine->wa_ctx.obj = NULL;
1492 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1498 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1500 WARN_ON(engine->id != RCS);
1502 /* update this when WA for higher Gen are added */
1503 if (INTEL_INFO(engine->dev)->gen > 9) {
1504 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1505 INTEL_INFO(engine->dev)->gen);
1509 /* some WA perform writes to scratch page, ensure it is valid */
1510 if (engine->scratch.obj == NULL) {
1511 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1515 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1517 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1521 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1522 batch = kmap_atomic(page);
1525 if (INTEL_INFO(engine->dev)->gen == 8) {
1526 ret = gen8_init_indirectctx_bb(engine,
1527 &wa_ctx->indirect_ctx,
1533 ret = gen8_init_perctx_bb(engine,
1539 } else if (INTEL_INFO(engine->dev)->gen == 9) {
1540 ret = gen9_init_indirectctx_bb(engine,
1541 &wa_ctx->indirect_ctx,
1547 ret = gen9_init_perctx_bb(engine,
1556 kunmap_atomic(batch);
1558 lrc_destroy_wa_ctx_obj(engine);
1563 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1565 struct drm_device *dev = engine->dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 unsigned int next_context_status_buffer_hw;
1569 lrc_setup_hardware_status_page(engine,
1570 dev_priv->kernel_context->engine[engine->id].state);
1572 I915_WRITE_IMR(engine,
1573 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1574 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1576 I915_WRITE(RING_MODE_GEN7(engine),
1577 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1578 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1579 POSTING_READ(RING_MODE_GEN7(engine));
1582 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1583 * zero, we need to read the write pointer from hardware and use its
1584 * value because "this register is power context save restored".
1585 * Effectively, these states have been observed:
1587 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1588 * BDW | CSB regs not reset | CSB regs reset |
1589 * CHT | CSB regs not reset | CSB regs not reset |
1593 next_context_status_buffer_hw =
1594 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1597 * When the CSB registers are reset (also after power-up / gpu reset),
1598 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1599 * this special case, so the first element read is CSB[0].
1601 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1602 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1604 engine->next_context_status_buffer = next_context_status_buffer_hw;
1605 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1607 intel_engine_init_hangcheck(engine);
1612 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1614 struct drm_device *dev = engine->dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1618 ret = gen8_init_common_ring(engine);
1622 /* We need to disable the AsyncFlip performance optimisations in order
1623 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1624 * programmed to '1' on all products.
1626 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1628 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1630 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1632 return init_workarounds_ring(engine);
1635 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1639 ret = gen8_init_common_ring(engine);
1643 return init_workarounds_ring(engine);
1646 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1648 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1649 struct intel_engine_cs *engine = req->engine;
1650 struct intel_ringbuffer *ringbuf = req->ringbuf;
1651 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1654 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1658 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1659 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1660 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1662 intel_logical_ring_emit_reg(ringbuf,
1663 GEN8_RING_PDP_UDW(engine, i));
1664 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1665 intel_logical_ring_emit_reg(ringbuf,
1666 GEN8_RING_PDP_LDW(engine, i));
1667 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1670 intel_logical_ring_emit(ringbuf, MI_NOOP);
1671 intel_logical_ring_advance(ringbuf);
1676 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1677 u64 offset, unsigned dispatch_flags)
1679 struct intel_ringbuffer *ringbuf = req->ringbuf;
1680 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1683 /* Don't rely in hw updating PDPs, specially in lite-restore.
1684 * Ideally, we should set Force PD Restore in ctx descriptor,
1685 * but we can't. Force Restore would be a second option, but
1686 * it is unsafe in case of lite-restore (because the ctx is
1687 * not idle). PML4 is allocated during ppgtt init so this is
1688 * not needed in 48-bit.*/
1689 if (req->ctx->ppgtt &&
1690 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1691 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1692 !intel_vgpu_active(req->i915->dev)) {
1693 ret = intel_logical_ring_emit_pdps(req);
1698 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1701 ret = intel_logical_ring_begin(req, 4);
1705 /* FIXME(BDW): Address space and security selectors. */
1706 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1708 (dispatch_flags & I915_DISPATCH_RS ?
1709 MI_BATCH_RESOURCE_STREAMER : 0));
1710 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1711 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1712 intel_logical_ring_emit(ringbuf, MI_NOOP);
1713 intel_logical_ring_advance(ringbuf);
1718 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
1720 struct drm_device *dev = engine->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 unsigned long flags;
1724 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1727 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1728 if (engine->irq_refcount++ == 0) {
1729 I915_WRITE_IMR(engine,
1730 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1731 POSTING_READ(RING_IMR(engine->mmio_base));
1733 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1738 static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
1740 struct drm_device *dev = engine->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 unsigned long flags;
1744 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1745 if (--engine->irq_refcount == 0) {
1746 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1747 POSTING_READ(RING_IMR(engine->mmio_base));
1749 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1752 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1753 u32 invalidate_domains,
1756 struct intel_ringbuffer *ringbuf = request->ringbuf;
1757 struct intel_engine_cs *engine = ringbuf->engine;
1758 struct drm_device *dev = engine->dev;
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1763 ret = intel_logical_ring_begin(request, 4);
1767 cmd = MI_FLUSH_DW + 1;
1769 /* We always require a command barrier so that subsequent
1770 * commands, such as breadcrumb interrupts, are strictly ordered
1771 * wrt the contents of the write cache being flushed to memory
1772 * (and thus being coherent from the CPU).
1774 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1776 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1777 cmd |= MI_INVALIDATE_TLB;
1778 if (engine == &dev_priv->engine[VCS])
1779 cmd |= MI_INVALIDATE_BSD;
1782 intel_logical_ring_emit(ringbuf, cmd);
1783 intel_logical_ring_emit(ringbuf,
1784 I915_GEM_HWS_SCRATCH_ADDR |
1785 MI_FLUSH_DW_USE_GTT);
1786 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1787 intel_logical_ring_emit(ringbuf, 0); /* value */
1788 intel_logical_ring_advance(ringbuf);
1793 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1794 u32 invalidate_domains,
1797 struct intel_ringbuffer *ringbuf = request->ringbuf;
1798 struct intel_engine_cs *engine = ringbuf->engine;
1799 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1800 bool vf_flush_wa = false;
1804 flags |= PIPE_CONTROL_CS_STALL;
1806 if (flush_domains) {
1807 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1808 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1809 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1810 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1813 if (invalidate_domains) {
1814 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1815 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1816 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1817 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1818 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1819 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1820 flags |= PIPE_CONTROL_QW_WRITE;
1821 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1824 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1827 if (IS_GEN9(engine->dev))
1831 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1836 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1837 intel_logical_ring_emit(ringbuf, 0);
1838 intel_logical_ring_emit(ringbuf, 0);
1839 intel_logical_ring_emit(ringbuf, 0);
1840 intel_logical_ring_emit(ringbuf, 0);
1841 intel_logical_ring_emit(ringbuf, 0);
1844 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1845 intel_logical_ring_emit(ringbuf, flags);
1846 intel_logical_ring_emit(ringbuf, scratch_addr);
1847 intel_logical_ring_emit(ringbuf, 0);
1848 intel_logical_ring_emit(ringbuf, 0);
1849 intel_logical_ring_emit(ringbuf, 0);
1850 intel_logical_ring_advance(ringbuf);
1855 static u32 gen8_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1857 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1860 static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1862 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1865 static u32 bxt_a_get_seqno(struct intel_engine_cs *engine,
1866 bool lazy_coherency)
1870 * On BXT A steppings there is a HW coherency issue whereby the
1871 * MI_STORE_DATA_IMM storing the completed request's seqno
1872 * occasionally doesn't invalidate the CPU cache. Work around this by
1873 * clflushing the corresponding cacheline whenever the caller wants
1874 * the coherency to be guaranteed. Note that this cacheline is known
1875 * to be clean at this point, since we only write it in
1876 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1877 * this clflush in practice becomes an invalidate operation.
1880 if (!lazy_coherency)
1881 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1883 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1886 static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1888 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1890 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1891 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1895 * Reserve space for 2 NOOPs at the end of each request to be
1896 * used as a workaround for not being allowed to do lite
1897 * restore with HEAD==TAIL (WaIdleLiteRestore).
1899 #define WA_TAIL_DWORDS 2
1901 static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
1903 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
1906 static int gen8_emit_request(struct drm_i915_gem_request *request)
1908 struct intel_ringbuffer *ringbuf = request->ringbuf;
1911 ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1915 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1916 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1918 intel_logical_ring_emit(ringbuf,
1919 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1920 intel_logical_ring_emit(ringbuf,
1921 hws_seqno_address(request->engine) |
1922 MI_FLUSH_DW_USE_GTT);
1923 intel_logical_ring_emit(ringbuf, 0);
1924 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1925 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1926 intel_logical_ring_emit(ringbuf, MI_NOOP);
1927 return intel_logical_ring_advance_and_submit(request);
1930 static int gen8_emit_request_render(struct drm_i915_gem_request *request)
1932 struct intel_ringbuffer *ringbuf = request->ringbuf;
1935 ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1939 /* w/a for post sync ops following a GPGPU operation we
1940 * need a prior CS_STALL, which is emitted by the flush
1941 * following the batch.
1943 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
1944 intel_logical_ring_emit(ringbuf,
1945 (PIPE_CONTROL_GLOBAL_GTT_IVB |
1946 PIPE_CONTROL_CS_STALL |
1947 PIPE_CONTROL_QW_WRITE));
1948 intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine));
1949 intel_logical_ring_emit(ringbuf, 0);
1950 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1951 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1952 return intel_logical_ring_advance_and_submit(request);
1955 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1957 struct render_state so;
1960 ret = i915_gem_render_state_prepare(req->engine, &so);
1964 if (so.rodata == NULL)
1967 ret = req->engine->emit_bb_start(req, so.ggtt_offset,
1968 I915_DISPATCH_SECURE);
1972 ret = req->engine->emit_bb_start(req,
1973 (so.ggtt_offset + so.aux_batch_offset),
1974 I915_DISPATCH_SECURE);
1978 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1981 i915_gem_render_state_fini(&so);
1985 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1989 ret = intel_logical_ring_workarounds_emit(req);
1993 ret = intel_rcs_context_init_mocs(req);
1995 * Failing to program the MOCS is non-fatal.The system will not
1996 * run at peak performance. So generate an error and carry on.
1999 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2001 return intel_lr_context_render_state_init(req);
2005 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2007 * @ring: Engine Command Streamer.
2010 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2012 struct drm_i915_private *dev_priv;
2014 if (!intel_engine_initialized(engine))
2018 * Tasklet cannot be active at this point due intel_mark_active/idle
2019 * so this is just for documentation.
2021 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
2022 tasklet_kill(&engine->irq_tasklet);
2024 dev_priv = engine->dev->dev_private;
2026 if (engine->buffer) {
2027 intel_logical_ring_stop(engine);
2028 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2031 if (engine->cleanup)
2032 engine->cleanup(engine);
2034 i915_cmd_parser_fini_ring(engine);
2035 i915_gem_batch_pool_fini(&engine->batch_pool);
2037 if (engine->status_page.obj) {
2038 kunmap(sg_page(engine->status_page.obj->pages->sgl));
2039 engine->status_page.obj = NULL;
2042 engine->idle_lite_restore_wa = 0;
2043 engine->disable_lite_restore_wa = false;
2044 engine->ctx_desc_template = 0;
2046 lrc_destroy_wa_ctx_obj(engine);
2051 logical_ring_default_vfuncs(struct drm_device *dev,
2052 struct intel_engine_cs *engine)
2054 /* Default vfuncs which can be overriden by each engine. */
2055 engine->init_hw = gen8_init_common_ring;
2056 engine->emit_request = gen8_emit_request;
2057 engine->emit_flush = gen8_emit_flush;
2058 engine->irq_get = gen8_logical_ring_get_irq;
2059 engine->irq_put = gen8_logical_ring_put_irq;
2060 engine->emit_bb_start = gen8_emit_bb_start;
2061 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2062 engine->get_seqno = bxt_a_get_seqno;
2063 engine->set_seqno = bxt_a_set_seqno;
2065 engine->get_seqno = gen8_get_seqno;
2066 engine->set_seqno = gen8_set_seqno;
2071 logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
2073 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2074 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2078 logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
2080 struct intel_context *dctx = to_i915(dev)->kernel_context;
2083 /* Intentionally left blank. */
2084 engine->buffer = NULL;
2087 INIT_LIST_HEAD(&engine->active_list);
2088 INIT_LIST_HEAD(&engine->request_list);
2089 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2090 init_waitqueue_head(&engine->irq_queue);
2092 INIT_LIST_HEAD(&engine->buffers);
2093 INIT_LIST_HEAD(&engine->execlist_queue);
2094 INIT_LIST_HEAD(&engine->execlist_retired_req_list);
2095 spin_lock_init(&engine->execlist_lock);
2097 tasklet_init(&engine->irq_tasklet,
2098 intel_lrc_irq_handler, (unsigned long)engine);
2100 logical_ring_init_platform_invariants(engine);
2102 ret = i915_cmd_parser_init_ring(engine);
2106 ret = intel_lr_context_deferred_alloc(dctx, engine);
2110 /* As this is the default context, always pin it */
2111 ret = intel_lr_context_do_pin(dctx, engine);
2114 "Failed to pin and map ringbuffer %s: %d\n",
2122 intel_logical_ring_cleanup(engine);
2126 static int logical_render_ring_init(struct drm_device *dev)
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2132 engine->name = "render ring";
2134 engine->exec_id = I915_EXEC_RENDER;
2135 engine->guc_id = GUC_RENDER_ENGINE;
2136 engine->mmio_base = RENDER_RING_BASE;
2138 logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
2139 if (HAS_L3_DPF(dev))
2140 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2142 logical_ring_default_vfuncs(dev, engine);
2144 /* Override some for render ring. */
2145 if (INTEL_INFO(dev)->gen >= 9)
2146 engine->init_hw = gen9_init_render_ring;
2148 engine->init_hw = gen8_init_render_ring;
2149 engine->init_context = gen8_init_rcs_context;
2150 engine->cleanup = intel_fini_pipe_control;
2151 engine->emit_flush = gen8_emit_flush_render;
2152 engine->emit_request = gen8_emit_request_render;
2156 ret = intel_init_pipe_control(engine);
2160 ret = intel_init_workaround_bb(engine);
2163 * We continue even if we fail to initialize WA batch
2164 * because we only expect rare glitches but nothing
2165 * critical to prevent us from using GPU
2167 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2171 ret = logical_ring_init(dev, engine);
2173 lrc_destroy_wa_ctx_obj(engine);
2179 static int logical_bsd_ring_init(struct drm_device *dev)
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2184 engine->name = "bsd ring";
2186 engine->exec_id = I915_EXEC_BSD;
2187 engine->guc_id = GUC_VIDEO_ENGINE;
2188 engine->mmio_base = GEN6_BSD_RING_BASE;
2190 logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
2191 logical_ring_default_vfuncs(dev, engine);
2193 return logical_ring_init(dev, engine);
2196 static int logical_bsd2_ring_init(struct drm_device *dev)
2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2201 engine->name = "bsd2 ring";
2203 engine->exec_id = I915_EXEC_BSD;
2204 engine->guc_id = GUC_VIDEO_ENGINE2;
2205 engine->mmio_base = GEN8_BSD2_RING_BASE;
2207 logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
2208 logical_ring_default_vfuncs(dev, engine);
2210 return logical_ring_init(dev, engine);
2213 static int logical_blt_ring_init(struct drm_device *dev)
2215 struct drm_i915_private *dev_priv = dev->dev_private;
2216 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2218 engine->name = "blitter ring";
2220 engine->exec_id = I915_EXEC_BLT;
2221 engine->guc_id = GUC_BLITTER_ENGINE;
2222 engine->mmio_base = BLT_RING_BASE;
2224 logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
2225 logical_ring_default_vfuncs(dev, engine);
2227 return logical_ring_init(dev, engine);
2230 static int logical_vebox_ring_init(struct drm_device *dev)
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2235 engine->name = "video enhancement ring";
2237 engine->exec_id = I915_EXEC_VEBOX;
2238 engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
2239 engine->mmio_base = VEBOX_RING_BASE;
2241 logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
2242 logical_ring_default_vfuncs(dev, engine);
2244 return logical_ring_init(dev, engine);
2248 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2251 * This function inits the engines for an Execlists submission style (the equivalent in the
2252 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2253 * those engines that are present in the hardware.
2255 * Return: non-zero if the initialization failed.
2257 int intel_logical_rings_init(struct drm_device *dev)
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2262 ret = logical_render_ring_init(dev);
2267 ret = logical_bsd_ring_init(dev);
2269 goto cleanup_render_ring;
2273 ret = logical_blt_ring_init(dev);
2275 goto cleanup_bsd_ring;
2278 if (HAS_VEBOX(dev)) {
2279 ret = logical_vebox_ring_init(dev);
2281 goto cleanup_blt_ring;
2284 if (HAS_BSD2(dev)) {
2285 ret = logical_bsd2_ring_init(dev);
2287 goto cleanup_vebox_ring;
2293 intel_logical_ring_cleanup(&dev_priv->engine[VECS]);
2295 intel_logical_ring_cleanup(&dev_priv->engine[BCS]);
2297 intel_logical_ring_cleanup(&dev_priv->engine[VCS]);
2298 cleanup_render_ring:
2299 intel_logical_ring_cleanup(&dev_priv->engine[RCS]);
2305 make_rpcs(struct drm_device *dev)
2310 * No explicit RPCS request is needed to ensure full
2311 * slice/subslice/EU enablement prior to Gen9.
2313 if (INTEL_INFO(dev)->gen < 9)
2317 * Starting in Gen9, render power gating can leave
2318 * slice/subslice/EU in a partially enabled state. We
2319 * must make an explicit request through RPCS for full
2322 if (INTEL_INFO(dev)->has_slice_pg) {
2323 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2324 rpcs |= INTEL_INFO(dev)->slice_total <<
2325 GEN8_RPCS_S_CNT_SHIFT;
2326 rpcs |= GEN8_RPCS_ENABLE;
2329 if (INTEL_INFO(dev)->has_subslice_pg) {
2330 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2331 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2332 GEN8_RPCS_SS_CNT_SHIFT;
2333 rpcs |= GEN8_RPCS_ENABLE;
2336 if (INTEL_INFO(dev)->has_eu_pg) {
2337 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2338 GEN8_RPCS_EU_MIN_SHIFT;
2339 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2340 GEN8_RPCS_EU_MAX_SHIFT;
2341 rpcs |= GEN8_RPCS_ENABLE;
2347 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2349 u32 indirect_ctx_offset;
2351 switch (INTEL_INFO(engine->dev)->gen) {
2353 MISSING_CASE(INTEL_INFO(engine->dev)->gen);
2356 indirect_ctx_offset =
2357 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2360 indirect_ctx_offset =
2361 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2365 return indirect_ctx_offset;
2369 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2370 struct intel_engine_cs *engine,
2371 struct intel_ringbuffer *ringbuf)
2373 struct drm_device *dev = engine->dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2377 uint32_t *reg_state;
2381 ppgtt = dev_priv->mm.aliasing_ppgtt;
2383 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2385 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2389 ret = i915_gem_object_get_pages(ctx_obj);
2391 DRM_DEBUG_DRIVER("Could not get object pages\n");
2395 i915_gem_object_pin_pages(ctx_obj);
2397 /* The second page of the context object contains some fields which must
2398 * be set up prior to the first execution. */
2399 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2400 reg_state = kmap_atomic(page);
2402 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2403 * commands followed by (reg, value) pairs. The values we are setting here are
2404 * only for the first context restore: on a subsequent save, the GPU will
2405 * recreate this batchbuffer with new values (including all the missing
2406 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2407 reg_state[CTX_LRI_HEADER_0] =
2408 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2409 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2410 RING_CONTEXT_CONTROL(engine),
2411 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2412 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2413 (HAS_RESOURCE_STREAMER(dev) ?
2414 CTX_CTRL_RS_CTX_ENABLE : 0)));
2415 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2417 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2419 /* Ring buffer start address is not known until the buffer is pinned.
2420 * It is written to the context image in execlists_update_context()
2422 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2423 RING_START(engine->mmio_base), 0);
2424 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2425 RING_CTL(engine->mmio_base),
2426 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2427 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2428 RING_BBADDR_UDW(engine->mmio_base), 0);
2429 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2430 RING_BBADDR(engine->mmio_base), 0);
2431 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2432 RING_BBSTATE(engine->mmio_base),
2434 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2435 RING_SBBADDR_UDW(engine->mmio_base), 0);
2436 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2437 RING_SBBADDR(engine->mmio_base), 0);
2438 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2439 RING_SBBSTATE(engine->mmio_base), 0);
2440 if (engine->id == RCS) {
2441 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2442 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2443 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2444 RING_INDIRECT_CTX(engine->mmio_base), 0);
2445 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2446 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2447 if (engine->wa_ctx.obj) {
2448 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2449 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2451 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2452 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2453 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2455 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2456 intel_lr_indirect_ctx_offset(engine) << 6;
2458 reg_state[CTX_BB_PER_CTX_PTR+1] =
2459 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2463 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2464 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2465 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2466 /* PDP values well be assigned later if needed */
2467 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2469 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2471 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2473 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2475 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2477 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2479 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2481 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2484 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2485 /* 64b PPGTT (48bit canonical)
2486 * PDP0_DESCRIPTOR contains the base address to PML4 and
2487 * other PDP Descriptors are ignored.
2489 ASSIGN_CTX_PML4(ppgtt, reg_state);
2492 * PDP*_DESCRIPTOR contains the base address of space supported.
2493 * With dynamic page allocation, PDPs may not be allocated at
2494 * this point. Point the unallocated PDPs to the scratch page
2496 execlists_update_context_pdps(ppgtt, reg_state);
2499 if (engine->id == RCS) {
2500 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2501 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2505 kunmap_atomic(reg_state);
2506 i915_gem_object_unpin_pages(ctx_obj);
2512 * intel_lr_context_free() - free the LRC specific bits of a context
2513 * @ctx: the LR context to free.
2515 * The real context freeing is done in i915_gem_context_free: this only
2516 * takes care of the bits that are LRC related: the per-engine backing
2517 * objects and the logical ringbuffer.
2519 void intel_lr_context_free(struct intel_context *ctx)
2523 for (i = I915_NUM_ENGINES; --i >= 0; ) {
2524 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2525 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2530 if (ctx == ctx->i915->kernel_context) {
2531 intel_unpin_ringbuffer_obj(ringbuf);
2532 i915_gem_object_ggtt_unpin(ctx_obj);
2535 WARN_ON(ctx->engine[i].pin_count);
2536 intel_ringbuffer_free(ringbuf);
2537 drm_gem_object_unreference(&ctx_obj->base);
2542 * intel_lr_context_size() - return the size of the context for an engine
2543 * @ring: which engine to find the context size for
2545 * Each engine may require a different amount of space for a context image,
2546 * so when allocating (or copying) an image, this function can be used to
2547 * find the right size for the specific engine.
2549 * Return: size (in bytes) of an engine-specific context image
2551 * Note: this size includes the HWSP, which is part of the context image
2552 * in LRC mode, but does not include the "shared data page" used with
2553 * GuC submission. The caller should account for this if using the GuC.
2555 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2559 WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
2561 switch (engine->id) {
2563 if (INTEL_INFO(engine->dev)->gen >= 9)
2564 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2566 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2572 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2579 static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
2580 struct drm_i915_gem_object *default_ctx_obj)
2582 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2585 /* The HWSP is part of the default context object in LRC mode. */
2586 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2587 + LRC_PPHWSP_PN * PAGE_SIZE;
2588 page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2589 engine->status_page.page_addr = kmap(page);
2590 engine->status_page.obj = default_ctx_obj;
2592 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
2593 (u32)engine->status_page.gfx_addr);
2594 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
2598 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2599 * @ctx: LR context to create.
2600 * @ring: engine to be used with the context.
2602 * This function can be called more than once, with different engines, if we plan
2603 * to use the context with them. The context backing objects and the ringbuffers
2604 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2605 * the creation is a deferred call: it's better to make sure first that we need to use
2606 * a given ring with the context.
2608 * Return: non-zero on error.
2611 int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2612 struct intel_engine_cs *engine)
2614 struct drm_device *dev = engine->dev;
2615 struct drm_i915_gem_object *ctx_obj;
2616 uint32_t context_size;
2617 struct intel_ringbuffer *ringbuf;
2620 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2621 WARN_ON(ctx->engine[engine->id].state);
2623 context_size = round_up(intel_lr_context_size(engine), 4096);
2625 /* One extra page as the sharing data between driver and GuC */
2626 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2628 ctx_obj = i915_gem_alloc_object(dev, context_size);
2630 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2634 ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
2635 if (IS_ERR(ringbuf)) {
2636 ret = PTR_ERR(ringbuf);
2637 goto error_deref_obj;
2640 ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
2642 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2646 ctx->engine[engine->id].ringbuf = ringbuf;
2647 ctx->engine[engine->id].state = ctx_obj;
2649 if (ctx != ctx->i915->kernel_context && engine->init_context) {
2650 struct drm_i915_gem_request *req;
2652 req = i915_gem_request_alloc(engine, ctx);
2655 DRM_ERROR("ring create req: %d\n", ret);
2659 ret = engine->init_context(req);
2661 DRM_ERROR("ring init context: %d\n",
2663 i915_gem_request_cancel(req);
2666 i915_add_request_no_flush(req);
2671 intel_ringbuffer_free(ringbuf);
2673 drm_gem_object_unreference(&ctx_obj->base);
2674 ctx->engine[engine->id].ringbuf = NULL;
2675 ctx->engine[engine->id].state = NULL;
2679 void intel_lr_context_reset(struct drm_device *dev,
2680 struct intel_context *ctx)
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_engine_cs *engine;
2685 for_each_engine(engine, dev_priv) {
2686 struct drm_i915_gem_object *ctx_obj =
2687 ctx->engine[engine->id].state;
2688 struct intel_ringbuffer *ringbuf =
2689 ctx->engine[engine->id].ringbuf;
2690 uint32_t *reg_state;
2696 if (i915_gem_object_get_pages(ctx_obj)) {
2697 WARN(1, "Failed get_pages for context obj\n");
2700 page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2701 reg_state = kmap_atomic(page);
2703 reg_state[CTX_RING_HEAD+1] = 0;
2704 reg_state[CTX_RING_TAIL+1] = 0;
2706 kunmap_atomic(reg_state);