drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191 enum {
 192         ADVANCED_CONTEXT = 0,
 193         LEGACY_CONTEXT,
 194         ADVANCED_AD_CONTEXT,
 195         LEGACY_64B_CONTEXT
 196 };
 197 #define GEN8_CTX_MODE_SHIFT 3
 198 enum {
 199         FAULT_AND_HANG = 0,
 200         FAULT_AND_HALT, /* Debug only */
 201         FAULT_AND_STREAM,
 202         FAULT_AND_CONTINUE /* Unsupported */
 203 };
 204 #define GEN8_CTX_ID_SHIFT 32
 205
 206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 207                 struct intel_context *ctx);
 208
 209 /**
 210  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 211  * @dev: DRM device.
 212  * @enable_execlists: value of i915.enable_execlists module parameter.
 213  *
 214  * Only certain platforms support Execlists (the prerequisites being
 215  * support for Logical Ring Contexts and Aliasing PPGTT or better),
 216  * and only when enabled via module parameter.
 217  *
 218  * Return: 1 if Execlists is supported and has to be enabled.
 219  */
 220 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 221 {
 222         WARN_ON(i915.enable_ppgtt == -1);
 223
 224         if (INTEL_INFO(dev)->gen >= 9)
 225                 return 1;
 226
 227         if (enable_execlists == 0)
 228                 return 0;
 229
 230         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 231             i915.use_mmio_flip >= 0)
 232                 return 1;
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * intel_execlists_ctx_id() - get the Execlists Context ID
 239  * @ctx_obj: Logical Ring Context backing object.
 240  *
 241  * Do not confuse with ctx->id! Unfortunately we have a name overload
 242  * here: the old context ID we pass to userspace as a handler so that
 243  * they can refer to a context, and the new context ID we pass to the
 244  * ELSP so that the GPU can inform us of the context status via
 245  * interrupts.
 246  *
 247  * Return: 20-bits globally unique context ID.
 248  */
 249 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 250 {
 251         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 252
 253         /* LRCA is required to be 4K aligned so the more significant 20 bits
 254          * are globally unique */
 255         return lrca >> 12;
 256 }
 257
 258 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
 259 {
 260         uint64_t desc;
 261         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 262
 263         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 264
 265         desc = GEN8_CTX_VALID;
 266         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 267         desc |= GEN8_CTX_L3LLC_COHERENT;
 268         desc |= GEN8_CTX_PRIVILEGE;
 269         desc |= lrca;
 270         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 271
 272         /* TODO: WaDisableLiteRestore when we start using semaphore
 273          * signalling between Command Streamers */
 274         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 275
 276         return desc;
 277 }
 278
 279 static void execlists_elsp_write(struct intel_engine_cs *ring,
 280                                  struct drm_i915_gem_object *ctx_obj0,
 281                                  struct drm_i915_gem_object *ctx_obj1)
 282 {
 283         struct drm_device *dev = ring->dev;
 284         struct drm_i915_private *dev_priv = dev->dev_private;
 285         uint64_t temp = 0;
 286         uint32_t desc[4];
 287         unsigned long flags;
 288
 289         /* XXX: You must always write both descriptors in the order below. */
 290         if (ctx_obj1)
 291                 temp = execlists_ctx_descriptor(ctx_obj1);
 292         else
 293                 temp = 0;
 294         desc[1] = (u32)(temp >> 32);
 295         desc[0] = (u32)temp;
 296
 297         temp = execlists_ctx_descriptor(ctx_obj0);
 298         desc[3] = (u32)(temp >> 32);
 299         desc[2] = (u32)temp;
 300
 301         /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
 302          * are in progress.
 303          *
 304          * The other problem is that we can't just call gen6_gt_force_wake_get()
 305          * because that function calls intel_runtime_pm_get(), which might sleep.
 306          * Instead, we do the runtime_pm_get/put when creating/destroying requests.
 307          */
 308         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 309         if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
 310                 if (dev_priv->uncore.fw_rendercount++ == 0)
 311                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 312                                                               FORCEWAKE_RENDER);
 313                 if (dev_priv->uncore.fw_mediacount++ == 0)
 314                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 315                                                               FORCEWAKE_MEDIA);
 316                 if (INTEL_INFO(dev)->gen >= 9) {
 317                         if (dev_priv->uncore.fw_blittercount++ == 0)
 318                                 dev_priv->uncore.funcs.force_wake_get(dev_priv,
 319                                                         FORCEWAKE_BLITTER);
 320                 }
 321         } else {
 322                 if (dev_priv->uncore.forcewake_count++ == 0)
 323                         dev_priv->uncore.funcs.force_wake_get(dev_priv,
 324                                                               FORCEWAKE_ALL);
 325         }
 326         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 327
 328         I915_WRITE(RING_ELSP(ring), desc[1]);
 329         I915_WRITE(RING_ELSP(ring), desc[0]);
 330         I915_WRITE(RING_ELSP(ring), desc[3]);
 331         /* The context is automatically loaded after the following */
 332         I915_WRITE(RING_ELSP(ring), desc[2]);
 333
 334         /* ELSP is a wo register, so use another nearby reg for posting instead */
 335         POSTING_READ(RING_EXECLIST_STATUS(ring));
 336
 337         /* Release Force Wakeup (see the big comment above). */
 338         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 339         if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
 340                 if (--dev_priv->uncore.fw_rendercount == 0)
 341                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 342                                                               FORCEWAKE_RENDER);
 343                 if (--dev_priv->uncore.fw_mediacount == 0)
 344                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 345                                                               FORCEWAKE_MEDIA);
 346                 if (INTEL_INFO(dev)->gen >= 9) {
 347                         if (--dev_priv->uncore.fw_blittercount == 0)
 348                                 dev_priv->uncore.funcs.force_wake_put(dev_priv,
 349                                                         FORCEWAKE_BLITTER);
 350                 }
 351         } else {
 352                 if (--dev_priv->uncore.forcewake_count == 0)
 353                         dev_priv->uncore.funcs.force_wake_put(dev_priv,
 354                                                               FORCEWAKE_ALL);
 355         }
 356
 357         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 358 }
 359
 360 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
 361                                     struct drm_i915_gem_object *ring_obj,
 362                                     u32 tail)
 363 {
 364         struct page *page;
 365         uint32_t *reg_state;
 366
 367         page = i915_gem_object_get_page(ctx_obj, 1);
 368         reg_state = kmap_atomic(page);
 369
 370         reg_state[CTX_RING_TAIL+1] = tail;
 371         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
 372
 373         kunmap_atomic(reg_state);
 374
 375         return 0;
 376 }
 377
 378 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 379                                       struct intel_context *to0, u32 tail0,
 380                                       struct intel_context *to1, u32 tail1)
 381 {
 382         struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
 383         struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
 384         struct drm_i915_gem_object *ctx_obj1 = NULL;
 385         struct intel_ringbuffer *ringbuf1 = NULL;
 386
 387         BUG_ON(!ctx_obj0);
 388         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 389         WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
 390
 391         execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
 392
 393         if (to1) {
 394                 ringbuf1 = to1->engine[ring->id].ringbuf;
 395                 ctx_obj1 = to1->engine[ring->id].state;
 396                 BUG_ON(!ctx_obj1);
 397                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 398                 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
 399
 400                 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
 401         }
 402
 403         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 404 }
 405
 406 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 407 {
 408         struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL;
 409         struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL;
 410
 411         assert_spin_locked(&ring->execlist_lock);
 412
 413         if (list_empty(&ring->execlist_queue))
 414                 return;
 415
 416         /* Try to read in pairs */
 417         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 418                                  execlist_link) {
 419                 if (!req0) {
 420                         req0 = cursor;
 421                 } else if (req0->ctx == cursor->ctx) {
 422                         /* Same ctx: ignore first request, as second request
 423                          * will update tail past first request's workload */
 424                         cursor->elsp_submitted = req0->elsp_submitted;
 425                         list_del(&req0->execlist_link);
 426                         list_add_tail(&req0->execlist_link,
 427                                 &ring->execlist_retired_req_list);
 428                         req0 = cursor;
 429                 } else {
 430                         req1 = cursor;
 431                         break;
 432                 }
 433         }
 434
 435         WARN_ON(req1 && req1->elsp_submitted);
 436
 437         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 438                                   req1 ? req1->ctx : NULL,
 439                                   req1 ? req1->tail : 0);
 440
 441         req0->elsp_submitted++;
 442         if (req1)
 443                 req1->elsp_submitted++;
 444 }
 445
 446 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 447                                            u32 request_id)
 448 {
 449         struct intel_ctx_submit_request *head_req;
 450
 451         assert_spin_locked(&ring->execlist_lock);
 452
 453         head_req = list_first_entry_or_null(&ring->execlist_queue,
 454                                             struct intel_ctx_submit_request,
 455                                             execlist_link);
 456
 457         if (head_req != NULL) {
 458                 struct drm_i915_gem_object *ctx_obj =
 459                                 head_req->ctx->engine[ring->id].state;
 460                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 461                         WARN(head_req->elsp_submitted == 0,
 462                              "Never submitted head request\n");
 463
 464                         if (--head_req->elsp_submitted <= 0) {
 465                                 list_del(&head_req->execlist_link);
 466                                 list_add_tail(&head_req->execlist_link,
 467                                         &ring->execlist_retired_req_list);
 468                                 return true;
 469                         }
 470                 }
 471         }
 472
 473         return false;
 474 }
 475
 476 /**
 477  * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
 478  * @ring: Engine Command Streamer to handle.
 479  *
 480  * Check the unread Context Status Buffers and manage the submission of new
 481  * contexts to the ELSP accordingly.
 482  */
 483 void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring)
 484 {
 485         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 486         u32 status_pointer;
 487         u8 read_pointer;
 488         u8 write_pointer;
 489         u32 status;
 490         u32 status_id;
 491         u32 submit_contexts = 0;
 492
 493         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 494
 495         read_pointer = ring->next_context_status_buffer;
 496         write_pointer = status_pointer & 0x07;
 497         if (read_pointer > write_pointer)
 498                 write_pointer += 6;
 499
 500         spin_lock(&ring->execlist_lock);
 501
 502         while (read_pointer < write_pointer) {
 503                 read_pointer++;
 504                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 505                                 (read_pointer % 6) * 8);
 506                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 507                                 (read_pointer % 6) * 8 + 4);
 508
 509                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 510                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 511                                 if (execlists_check_remove_request(ring, status_id))
 512                                         WARN(1, "Lite Restored request removed from queue\n");
 513                         } else
 514                                 WARN(1, "Preemption without Lite Restore\n");
 515                 }
 516
 517                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 518                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 519                         if (execlists_check_remove_request(ring, status_id))
 520                                 submit_contexts++;
 521                 }
 522         }
 523
 524         if (submit_contexts != 0)
 525                 execlists_context_unqueue(ring);
 526
 527         spin_unlock(&ring->execlist_lock);
 528
 529         WARN(submit_contexts > 2, "More than two context complete events?\n");
 530         ring->next_context_status_buffer = write_pointer % 6;
 531
 532         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 533                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 534 }
 535
 536 static int execlists_context_queue(struct intel_engine_cs *ring,
 537                                    struct intel_context *to,
 538                                    u32 tail)
 539 {
 540         struct intel_ctx_submit_request *req = NULL, *cursor;
 541         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 542         unsigned long flags;
 543         int num_elements = 0;
 544
 545         req = kzalloc(sizeof(*req), GFP_KERNEL);
 546         if (req == NULL)
 547                 return -ENOMEM;
 548         req->ctx = to;
 549         i915_gem_context_reference(req->ctx);
 550
 551         if (to != ring->default_context)
 552                 intel_lr_context_pin(ring, to);
 553
 554         req->ring = ring;
 555         req->tail = tail;
 556
 557         intel_runtime_pm_get(dev_priv);
 558
 559         spin_lock_irqsave(&ring->execlist_lock, flags);
 560
 561         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 562                 if (++num_elements > 2)
 563                         break;
 564
 565         if (num_elements > 2) {
 566                 struct intel_ctx_submit_request *tail_req;
 567
 568                 tail_req = list_last_entry(&ring->execlist_queue,
 569                                            struct intel_ctx_submit_request,
 570                                            execlist_link);
 571
 572                 if (to == tail_req->ctx) {
 573                         WARN(tail_req->elsp_submitted != 0,
 574                                 "More than 2 already-submitted reqs queued\n");
 575                         list_del(&tail_req->execlist_link);
 576                         list_add_tail(&tail_req->execlist_link,
 577                                 &ring->execlist_retired_req_list);
 578                 }
 579         }
 580
 581         list_add_tail(&req->execlist_link, &ring->execlist_queue);
 582         if (num_elements == 0)
 583                 execlists_context_unqueue(ring);
 584
 585         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 586
 587         return 0;
 588 }
 589
 590 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
 591 {
 592         struct intel_engine_cs *ring = ringbuf->ring;
 593         uint32_t flush_domains;
 594         int ret;
 595
 596         flush_domains = 0;
 597         if (ring->gpu_caches_dirty)
 598                 flush_domains = I915_GEM_GPU_DOMAINS;
 599
 600         ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains);
 601         if (ret)
 602                 return ret;
 603
 604         ring->gpu_caches_dirty = false;
 605         return 0;
 606 }
 607
 608 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 609                                  struct list_head *vmas)
 610 {
 611         struct intel_engine_cs *ring = ringbuf->ring;
 612         struct i915_vma *vma;
 613         uint32_t flush_domains = 0;
 614         bool flush_chipset = false;
 615         int ret;
 616
 617         list_for_each_entry(vma, vmas, exec_list) {
 618                 struct drm_i915_gem_object *obj = vma->obj;
 619
 620                 ret = i915_gem_object_sync(obj, ring);
 621                 if (ret)
 622                         return ret;
 623
 624                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 625                         flush_chipset |= i915_gem_clflush_object(obj, false);
 626
 627                 flush_domains |= obj->base.write_domain;
 628         }
 629
 630         if (flush_domains & I915_GEM_DOMAIN_GTT)
 631                 wmb();
 632
 633         /* Unconditionally invalidate gpu caches and ensure that we do flush
 634          * any residual writes from the previous batch.
 635          */
 636         return logical_ring_invalidate_all_caches(ringbuf);
 637 }
 638
 639 /**
 640  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 641  * @dev: DRM device.
 642  * @file: DRM file.
 643  * @ring: Engine Command Streamer to submit to.
 644  * @ctx: Context to employ for this submission.
 645  * @args: execbuffer call arguments.
 646  * @vmas: list of vmas.
 647  * @batch_obj: the batchbuffer to submit.
 648  * @exec_start: batchbuffer start virtual address pointer.
 649  * @flags: translated execbuffer call flags.
 650  *
 651  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 652  * away the submission details of the execbuffer ioctl call.
 653  *
 654  * Return: non-zero if the submission fails.
 655  */
 656 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 657                                struct intel_engine_cs *ring,
 658                                struct intel_context *ctx,
 659                                struct drm_i915_gem_execbuffer2 *args,
 660                                struct list_head *vmas,
 661                                struct drm_i915_gem_object *batch_obj,
 662                                u64 exec_start, u32 flags)
 663 {
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 666         int instp_mode;
 667         u32 instp_mask;
 668         int ret;
 669
 670         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 671         instp_mask = I915_EXEC_CONSTANTS_MASK;
 672         switch (instp_mode) {
 673         case I915_EXEC_CONSTANTS_REL_GENERAL:
 674         case I915_EXEC_CONSTANTS_ABSOLUTE:
 675         case I915_EXEC_CONSTANTS_REL_SURFACE:
 676                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 677                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 678                         return -EINVAL;
 679                 }
 680
 681                 if (instp_mode != dev_priv->relative_constants_mode) {
 682                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 683                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 684                                 return -EINVAL;
 685                         }
 686
 687                         /* The HW changed the meaning on this bit on gen6 */
 688                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 689                 }
 690                 break;
 691         default:
 692                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 693                 return -EINVAL;
 694         }
 695
 696         if (args->num_cliprects != 0) {
 697                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 698                 return -EINVAL;
 699         } else {
 700                 if (args->DR4 == 0xffffffff) {
 701                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 702                         args->DR4 = 0;
 703                 }
 704
 705                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 706                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 707                         return -EINVAL;
 708                 }
 709         }
 710
 711         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 712                 DRM_DEBUG("sol reset is gen7 only\n");
 713                 return -EINVAL;
 714         }
 715
 716         ret = execlists_move_to_gpu(ringbuf, vmas);
 717         if (ret)
 718                 return ret;
 719
 720         if (ring == &dev_priv->ring[RCS] &&
 721             instp_mode != dev_priv->relative_constants_mode) {
 722                 ret = intel_logical_ring_begin(ringbuf, 4);
 723                 if (ret)
 724                         return ret;
 725
 726                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 727                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 728                 intel_logical_ring_emit(ringbuf, INSTPM);
 729                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 730                 intel_logical_ring_advance(ringbuf);
 731
 732                 dev_priv->relative_constants_mode = instp_mode;
 733         }
 734
 735         ret = ring->emit_bb_start(ringbuf, exec_start, flags);
 736         if (ret)
 737                 return ret;
 738
 739         i915_gem_execbuffer_move_to_active(vmas, ring);
 740         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 741
 742         return 0;
 743 }
 744
 745 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 746 {
 747         struct intel_ctx_submit_request *req, *tmp;
 748         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 749         unsigned long flags;
 750         struct list_head retired_list;
 751
 752         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 753         if (list_empty(&ring->execlist_retired_req_list))
 754                 return;
 755
 756         INIT_LIST_HEAD(&retired_list);
 757         spin_lock_irqsave(&ring->execlist_lock, flags);
 758         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 759         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 760
 761         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 762                 struct intel_context *ctx = req->ctx;
 763                 struct drm_i915_gem_object *ctx_obj =
 764                                 ctx->engine[ring->id].state;
 765
 766                 if (ctx_obj && (ctx != ring->default_context))
 767                         intel_lr_context_unpin(ring, ctx);
 768                 intel_runtime_pm_put(dev_priv);
 769                 i915_gem_context_unreference(req->ctx);
 770                 list_del(&req->execlist_link);
 771                 kfree(req);
 772         }
 773 }
 774
 775 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 776 {
 777         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 778         int ret;
 779
 780         if (!intel_ring_initialized(ring))
 781                 return;
 782
 783         ret = intel_ring_idle(ring);
 784         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 785                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 786                           ring->name, ret);
 787
 788         /* TODO: Is this correct with Execlists enabled? */
 789         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 790         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 791                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 792                 return;
 793         }
 794         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 795 }
 796
 797 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
 798 {
 799         struct intel_engine_cs *ring = ringbuf->ring;
 800         int ret;
 801
 802         if (!ring->gpu_caches_dirty)
 803                 return 0;
 804
 805         ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS);
 806         if (ret)
 807                 return ret;
 808
 809         ring->gpu_caches_dirty = false;
 810         return 0;
 811 }
 812
 813 /**
 814  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 815  * @ringbuf: Logical Ringbuffer to advance.
 816  *
 817  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 818  * really happens during submission is that the context and current tail will be placed
 819  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 820  * point, the tail *inside* the context is updated and the ELSP written to.
 821  */
 822 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf)
 823 {
 824         struct intel_engine_cs *ring = ringbuf->ring;
 825         struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
 826
 827         intel_logical_ring_advance(ringbuf);
 828
 829         if (intel_ring_stopped(ring))
 830                 return;
 831
 832         execlists_context_queue(ring, ctx, ringbuf->tail);
 833 }
 834
 835 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 836                 struct intel_context *ctx)
 837 {
 838         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 839         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 840         int ret = 0;
 841
 842         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 843         if (ctx->engine[ring->id].unpin_count++ == 0) {
 844                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
 845                                 GEN8_LR_CONTEXT_ALIGN, 0);
 846                 if (ret)
 847                         goto reset_unpin_count;
 848
 849                 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
 850                 if (ret)
 851                         goto unpin_ctx_obj;
 852         }
 853
 854         return ret;
 855
 856 unpin_ctx_obj:
 857         i915_gem_object_ggtt_unpin(ctx_obj);
 858 reset_unpin_count:
 859         ctx->engine[ring->id].unpin_count = 0;
 860
 861         return ret;
 862 }
 863
 864 void intel_lr_context_unpin(struct intel_engine_cs *ring,
 865                 struct intel_context *ctx)
 866 {
 867         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 868         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 869
 870         if (ctx_obj) {
 871                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 872                 if (--ctx->engine[ring->id].unpin_count == 0) {
 873                         intel_unpin_ringbuffer_obj(ringbuf);
 874                         i915_gem_object_ggtt_unpin(ctx_obj);
 875                 }
 876         }
 877 }
 878
 879 static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
 880                                     struct intel_context *ctx)
 881 {
 882         int ret;
 883
 884         if (ring->outstanding_lazy_seqno)
 885                 return 0;
 886
 887         if (ring->preallocated_lazy_request == NULL) {
 888                 struct drm_i915_gem_request *request;
 889
 890                 request = kmalloc(sizeof(*request), GFP_KERNEL);
 891                 if (request == NULL)
 892                         return -ENOMEM;
 893
 894                 if (ctx != ring->default_context) {
 895                         ret = intel_lr_context_pin(ring, ctx);
 896                         if (ret) {
 897                                 kfree(request);
 898                                 return ret;
 899                         }
 900                 }
 901
 902                 /* Hold a reference to the context this request belongs to
 903                  * (we will need it when the time comes to emit/retire the
 904                  * request).
 905                  */
 906                 request->ctx = ctx;
 907                 i915_gem_context_reference(request->ctx);
 908
 909                 ring->preallocated_lazy_request = request;
 910         }
 911
 912         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
 913 }
 914
 915 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 916                                      int bytes)
 917 {
 918         struct intel_engine_cs *ring = ringbuf->ring;
 919         struct drm_i915_gem_request *request;
 920         u32 seqno = 0;
 921         int ret;
 922
 923         if (ringbuf->last_retired_head != -1) {
 924                 ringbuf->head = ringbuf->last_retired_head;
 925                 ringbuf->last_retired_head = -1;
 926
 927                 ringbuf->space = intel_ring_space(ringbuf);
 928                 if (ringbuf->space >= bytes)
 929                         return 0;
 930         }
 931
 932         list_for_each_entry(request, &ring->request_list, list) {
 933                 if (__intel_ring_space(request->tail, ringbuf->tail,
 934                                        ringbuf->size) >= bytes) {
 935                         seqno = request->seqno;
 936                         break;
 937                 }
 938         }
 939
 940         if (seqno == 0)
 941                 return -ENOSPC;
 942
 943         ret = i915_wait_seqno(ring, seqno);
 944         if (ret)
 945                 return ret;
 946
 947         i915_gem_retire_requests_ring(ring);
 948         ringbuf->head = ringbuf->last_retired_head;
 949         ringbuf->last_retired_head = -1;
 950
 951         ringbuf->space = intel_ring_space(ringbuf);
 952         return 0;
 953 }
 954
 955 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 956                                        int bytes)
 957 {
 958         struct intel_engine_cs *ring = ringbuf->ring;
 959         struct drm_device *dev = ring->dev;
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         unsigned long end;
 962         int ret;
 963
 964         ret = logical_ring_wait_request(ringbuf, bytes);
 965         if (ret != -ENOSPC)
 966                 return ret;
 967
 968         /* Force the context submission in case we have been skipping it */
 969         intel_logical_ring_advance_and_submit(ringbuf);
 970
 971         /* With GEM the hangcheck timer should kick us out of the loop,
 972          * leaving it early runs the risk of corrupting GEM state (due
 973          * to running on almost untested codepaths). But on resume
 974          * timers don't work yet, so prevent a complete hang in that
 975          * case by choosing an insanely large timeout. */
 976         end = jiffies + 60 * HZ;
 977
 978         do {
 979                 ringbuf->head = I915_READ_HEAD(ring);
 980                 ringbuf->space = intel_ring_space(ringbuf);
 981                 if (ringbuf->space >= bytes) {
 982                         ret = 0;
 983                         break;
 984                 }
 985
 986                 msleep(1);
 987
 988                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 989                         ret = -ERESTARTSYS;
 990                         break;
 991                 }
 992
 993                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 994                                            dev_priv->mm.interruptible);
 995                 if (ret)
 996                         break;
 997
 998                 if (time_after(jiffies, end)) {
 999                         ret = -EBUSY;
1000                         break;
1001                 }
1002         } while (1);
1003
1004         return ret;
1005 }
1006
1007 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
1008 {
1009         uint32_t __iomem *virt;
1010         int rem = ringbuf->size - ringbuf->tail;
1011
1012         if (ringbuf->space < rem) {
1013                 int ret = logical_ring_wait_for_space(ringbuf, rem);
1014
1015                 if (ret)
1016                         return ret;
1017         }
1018
1019         virt = ringbuf->virtual_start + ringbuf->tail;
1020         rem /= 4;
1021         while (rem--)
1022                 iowrite32(MI_NOOP, virt++);
1023
1024         ringbuf->tail = 0;
1025         ringbuf->space = intel_ring_space(ringbuf);
1026
1027         return 0;
1028 }
1029
1030 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
1031 {
1032         int ret;
1033
1034         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1035                 ret = logical_ring_wrap_buffer(ringbuf);
1036                 if (unlikely(ret))
1037                         return ret;
1038         }
1039
1040         if (unlikely(ringbuf->space < bytes)) {
1041                 ret = logical_ring_wait_for_space(ringbuf, bytes);
1042                 if (unlikely(ret))
1043                         return ret;
1044         }
1045
1046         return 0;
1047 }
1048
1049 /**
1050  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1051  *
1052  * @ringbuf: Logical ringbuffer.
1053  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1054  *
1055  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1056  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1057  * and also preallocates a request (every workload submission is still mediated through
1058  * requests, same as it did with legacy ringbuffer submission).
1059  *
1060  * Return: non-zero if the ringbuffer is not ready to be written to.
1061  */
1062 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
1063 {
1064         struct intel_engine_cs *ring = ringbuf->ring;
1065         struct drm_device *dev = ring->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         int ret;
1068
1069         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1070                                    dev_priv->mm.interruptible);
1071         if (ret)
1072                 return ret;
1073
1074         ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t));
1075         if (ret)
1076                 return ret;
1077
1078         /* Preallocate the olr before touching the ring */
1079         ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx);
1080         if (ret)
1081                 return ret;
1082
1083         ringbuf->space -= num_dwords * sizeof(uint32_t);
1084         return 0;
1085 }
1086
1087 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1088                                                struct intel_context *ctx)
1089 {
1090         int ret, i;
1091         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1092         struct drm_device *dev = ring->dev;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         struct i915_workarounds *w = &dev_priv->workarounds;
1095
1096         if (WARN_ON(w->count == 0))
1097                 return 0;
1098
1099         ring->gpu_caches_dirty = true;
1100         ret = logical_ring_flush_all_caches(ringbuf);
1101         if (ret)
1102                 return ret;
1103
1104         ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2);
1105         if (ret)
1106                 return ret;
1107
1108         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1109         for (i = 0; i < w->count; i++) {
1110                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1111                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1112         }
1113         intel_logical_ring_emit(ringbuf, MI_NOOP);
1114
1115         intel_logical_ring_advance(ringbuf);
1116
1117         ring->gpu_caches_dirty = true;
1118         ret = logical_ring_flush_all_caches(ringbuf);
1119         if (ret)
1120                 return ret;
1121
1122         return 0;
1123 }
1124
1125 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1126 {
1127         struct drm_device *dev = ring->dev;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1131         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1132
1133         I915_WRITE(RING_MODE_GEN7(ring),
1134                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1135                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1136         POSTING_READ(RING_MODE_GEN7(ring));
1137         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1138
1139         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1140
1141         return 0;
1142 }
1143
1144 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1145 {
1146         struct drm_device *dev = ring->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148         int ret;
1149
1150         ret = gen8_init_common_ring(ring);
1151         if (ret)
1152                 return ret;
1153
1154         /* We need to disable the AsyncFlip performance optimisations in order
1155          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1156          * programmed to '1' on all products.
1157          *
1158          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1159          */
1160         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1161
1162         ret = intel_init_pipe_control(ring);
1163         if (ret)
1164                 return ret;
1165
1166         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1167
1168         return init_workarounds_ring(ring);
1169 }
1170
1171 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1172                               u64 offset, unsigned flags)
1173 {
1174         bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1175         int ret;
1176
1177         ret = intel_logical_ring_begin(ringbuf, 4);
1178         if (ret)
1179                 return ret;
1180
1181         /* FIXME(BDW): Address space and security selectors. */
1182         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1183         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1184         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1185         intel_logical_ring_emit(ringbuf, MI_NOOP);
1186         intel_logical_ring_advance(ringbuf);
1187
1188         return 0;
1189 }
1190
1191 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1192 {
1193         struct drm_device *dev = ring->dev;
1194         struct drm_i915_private *dev_priv = dev->dev_private;
1195         unsigned long flags;
1196
1197         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1198                 return false;
1199
1200         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1201         if (ring->irq_refcount++ == 0) {
1202                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1203                 POSTING_READ(RING_IMR(ring->mmio_base));
1204         }
1205         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1206
1207         return true;
1208 }
1209
1210 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1211 {
1212         struct drm_device *dev = ring->dev;
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214         unsigned long flags;
1215
1216         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1217         if (--ring->irq_refcount == 0) {
1218                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1219                 POSTING_READ(RING_IMR(ring->mmio_base));
1220         }
1221         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1222 }
1223
1224 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1225                            u32 invalidate_domains,
1226                            u32 unused)
1227 {
1228         struct intel_engine_cs *ring = ringbuf->ring;
1229         struct drm_device *dev = ring->dev;
1230         struct drm_i915_private *dev_priv = dev->dev_private;
1231         uint32_t cmd;
1232         int ret;
1233
1234         ret = intel_logical_ring_begin(ringbuf, 4);
1235         if (ret)
1236                 return ret;
1237
1238         cmd = MI_FLUSH_DW + 1;
1239
1240         if (ring == &dev_priv->ring[VCS]) {
1241                 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1242                         cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1243                                 MI_FLUSH_DW_STORE_INDEX |
1244                                 MI_FLUSH_DW_OP_STOREDW;
1245         } else {
1246                 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1247                         cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1248                                 MI_FLUSH_DW_OP_STOREDW;
1249         }
1250
1251         intel_logical_ring_emit(ringbuf, cmd);
1252         intel_logical_ring_emit(ringbuf,
1253                                 I915_GEM_HWS_SCRATCH_ADDR |
1254                                 MI_FLUSH_DW_USE_GTT);
1255         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1256         intel_logical_ring_emit(ringbuf, 0); /* value */
1257         intel_logical_ring_advance(ringbuf);
1258
1259         return 0;
1260 }
1261
1262 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1263                                   u32 invalidate_domains,
1264                                   u32 flush_domains)
1265 {
1266         struct intel_engine_cs *ring = ringbuf->ring;
1267         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1268         u32 flags = 0;
1269         int ret;
1270
1271         flags |= PIPE_CONTROL_CS_STALL;
1272
1273         if (flush_domains) {
1274                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1275                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1276         }
1277
1278         if (invalidate_domains) {
1279                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1280                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1281                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1282                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1283                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1284                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1285                 flags |= PIPE_CONTROL_QW_WRITE;
1286                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1287         }
1288
1289         ret = intel_logical_ring_begin(ringbuf, 6);
1290         if (ret)
1291                 return ret;
1292
1293         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1294         intel_logical_ring_emit(ringbuf, flags);
1295         intel_logical_ring_emit(ringbuf, scratch_addr);
1296         intel_logical_ring_emit(ringbuf, 0);
1297         intel_logical_ring_emit(ringbuf, 0);
1298         intel_logical_ring_emit(ringbuf, 0);
1299         intel_logical_ring_advance(ringbuf);
1300
1301         return 0;
1302 }
1303
1304 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1305 {
1306         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1307 }
1308
1309 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1310 {
1311         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1312 }
1313
1314 static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1315 {
1316         struct intel_engine_cs *ring = ringbuf->ring;
1317         u32 cmd;
1318         int ret;
1319
1320         ret = intel_logical_ring_begin(ringbuf, 6);
1321         if (ret)
1322                 return ret;
1323
1324         cmd = MI_STORE_DWORD_IMM_GEN8;
1325         cmd |= MI_GLOBAL_GTT;
1326
1327         intel_logical_ring_emit(ringbuf, cmd);
1328         intel_logical_ring_emit(ringbuf,
1329                                 (ring->status_page.gfx_addr +
1330                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1331         intel_logical_ring_emit(ringbuf, 0);
1332         intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno);
1333         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1334         intel_logical_ring_emit(ringbuf, MI_NOOP);
1335         intel_logical_ring_advance_and_submit(ringbuf);
1336
1337         return 0;
1338 }
1339
1340 /**
1341  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1342  *
1343  * @ring: Engine Command Streamer.
1344  *
1345  */
1346 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1347 {
1348         struct drm_i915_private *dev_priv;
1349
1350         if (!intel_ring_initialized(ring))
1351                 return;
1352
1353         dev_priv = ring->dev->dev_private;
1354
1355         intel_logical_ring_stop(ring);
1356         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1357         ring->preallocated_lazy_request = NULL;
1358         ring->outstanding_lazy_seqno = 0;
1359
1360         if (ring->cleanup)
1361                 ring->cleanup(ring);
1362
1363         i915_cmd_parser_fini_ring(ring);
1364
1365         if (ring->status_page.obj) {
1366                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1367                 ring->status_page.obj = NULL;
1368         }
1369 }
1370
1371 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1372 {
1373         int ret;
1374
1375         /* Intentionally left blank. */
1376         ring->buffer = NULL;
1377
1378         ring->dev = dev;
1379         INIT_LIST_HEAD(&ring->active_list);
1380         INIT_LIST_HEAD(&ring->request_list);
1381         init_waitqueue_head(&ring->irq_queue);
1382
1383         INIT_LIST_HEAD(&ring->execlist_queue);
1384         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1385         spin_lock_init(&ring->execlist_lock);
1386         ring->next_context_status_buffer = 0;
1387
1388         ret = i915_cmd_parser_init_ring(ring);
1389         if (ret)
1390                 return ret;
1391
1392         if (ring->init) {
1393                 ret = ring->init(ring);
1394                 if (ret)
1395                         return ret;
1396         }
1397
1398         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1399
1400         return ret;
1401 }
1402
1403 static int logical_render_ring_init(struct drm_device *dev)
1404 {
1405         struct drm_i915_private *dev_priv = dev->dev_private;
1406         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1407
1408         ring->name = "render ring";
1409         ring->id = RCS;
1410         ring->mmio_base = RENDER_RING_BASE;
1411         ring->irq_enable_mask =
1412                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1413         ring->irq_keep_mask =
1414                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1415         if (HAS_L3_DPF(dev))
1416                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1417
1418         ring->init = gen8_init_render_ring;
1419         ring->init_context = intel_logical_ring_workarounds_emit;
1420         ring->cleanup = intel_fini_pipe_control;
1421         ring->get_seqno = gen8_get_seqno;
1422         ring->set_seqno = gen8_set_seqno;
1423         ring->emit_request = gen8_emit_request;
1424         ring->emit_flush = gen8_emit_flush_render;
1425         ring->irq_get = gen8_logical_ring_get_irq;
1426         ring->irq_put = gen8_logical_ring_put_irq;
1427         ring->emit_bb_start = gen8_emit_bb_start;
1428
1429         return logical_ring_init(dev, ring);
1430 }
1431
1432 static int logical_bsd_ring_init(struct drm_device *dev)
1433 {
1434         struct drm_i915_private *dev_priv = dev->dev_private;
1435         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1436
1437         ring->name = "bsd ring";
1438         ring->id = VCS;
1439         ring->mmio_base = GEN6_BSD_RING_BASE;
1440         ring->irq_enable_mask =
1441                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1442         ring->irq_keep_mask =
1443                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1444
1445         ring->init = gen8_init_common_ring;
1446         ring->get_seqno = gen8_get_seqno;
1447         ring->set_seqno = gen8_set_seqno;
1448         ring->emit_request = gen8_emit_request;
1449         ring->emit_flush = gen8_emit_flush;
1450         ring->irq_get = gen8_logical_ring_get_irq;
1451         ring->irq_put = gen8_logical_ring_put_irq;
1452         ring->emit_bb_start = gen8_emit_bb_start;
1453
1454         return logical_ring_init(dev, ring);
1455 }
1456
1457 static int logical_bsd2_ring_init(struct drm_device *dev)
1458 {
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1461
1462         ring->name = "bds2 ring";
1463         ring->id = VCS2;
1464         ring->mmio_base = GEN8_BSD2_RING_BASE;
1465         ring->irq_enable_mask =
1466                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1467         ring->irq_keep_mask =
1468                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1469
1470         ring->init = gen8_init_common_ring;
1471         ring->get_seqno = gen8_get_seqno;
1472         ring->set_seqno = gen8_set_seqno;
1473         ring->emit_request = gen8_emit_request;
1474         ring->emit_flush = gen8_emit_flush;
1475         ring->irq_get = gen8_logical_ring_get_irq;
1476         ring->irq_put = gen8_logical_ring_put_irq;
1477         ring->emit_bb_start = gen8_emit_bb_start;
1478
1479         return logical_ring_init(dev, ring);
1480 }
1481
1482 static int logical_blt_ring_init(struct drm_device *dev)
1483 {
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1486
1487         ring->name = "blitter ring";
1488         ring->id = BCS;
1489         ring->mmio_base = BLT_RING_BASE;
1490         ring->irq_enable_mask =
1491                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1492         ring->irq_keep_mask =
1493                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1494
1495         ring->init = gen8_init_common_ring;
1496         ring->get_seqno = gen8_get_seqno;
1497         ring->set_seqno = gen8_set_seqno;
1498         ring->emit_request = gen8_emit_request;
1499         ring->emit_flush = gen8_emit_flush;
1500         ring->irq_get = gen8_logical_ring_get_irq;
1501         ring->irq_put = gen8_logical_ring_put_irq;
1502         ring->emit_bb_start = gen8_emit_bb_start;
1503
1504         return logical_ring_init(dev, ring);
1505 }
1506
1507 static int logical_vebox_ring_init(struct drm_device *dev)
1508 {
1509         struct drm_i915_private *dev_priv = dev->dev_private;
1510         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1511
1512         ring->name = "video enhancement ring";
1513         ring->id = VECS;
1514         ring->mmio_base = VEBOX_RING_BASE;
1515         ring->irq_enable_mask =
1516                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1517         ring->irq_keep_mask =
1518                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1519
1520         ring->init = gen8_init_common_ring;
1521         ring->get_seqno = gen8_get_seqno;
1522         ring->set_seqno = gen8_set_seqno;
1523         ring->emit_request = gen8_emit_request;
1524         ring->emit_flush = gen8_emit_flush;
1525         ring->irq_get = gen8_logical_ring_get_irq;
1526         ring->irq_put = gen8_logical_ring_put_irq;
1527         ring->emit_bb_start = gen8_emit_bb_start;
1528
1529         return logical_ring_init(dev, ring);
1530 }
1531
1532 /**
1533  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1534  * @dev: DRM device.
1535  *
1536  * This function inits the engines for an Execlists submission style (the equivalent in the
1537  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1538  * those engines that are present in the hardware.
1539  *
1540  * Return: non-zero if the initialization failed.
1541  */
1542 int intel_logical_rings_init(struct drm_device *dev)
1543 {
1544         struct drm_i915_private *dev_priv = dev->dev_private;
1545         int ret;
1546
1547         ret = logical_render_ring_init(dev);
1548         if (ret)
1549                 return ret;
1550
1551         if (HAS_BSD(dev)) {
1552                 ret = logical_bsd_ring_init(dev);
1553                 if (ret)
1554                         goto cleanup_render_ring;
1555         }
1556
1557         if (HAS_BLT(dev)) {
1558                 ret = logical_blt_ring_init(dev);
1559                 if (ret)
1560                         goto cleanup_bsd_ring;
1561         }
1562
1563         if (HAS_VEBOX(dev)) {
1564                 ret = logical_vebox_ring_init(dev);
1565                 if (ret)
1566                         goto cleanup_blt_ring;
1567         }
1568
1569         if (HAS_BSD2(dev)) {
1570                 ret = logical_bsd2_ring_init(dev);
1571                 if (ret)
1572                         goto cleanup_vebox_ring;
1573         }
1574
1575         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1576         if (ret)
1577                 goto cleanup_bsd2_ring;
1578
1579         return 0;
1580
1581 cleanup_bsd2_ring:
1582         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1583 cleanup_vebox_ring:
1584         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1585 cleanup_blt_ring:
1586         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1587 cleanup_bsd_ring:
1588         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1589 cleanup_render_ring:
1590         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1591
1592         return ret;
1593 }
1594
1595 int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1596                                        struct intel_context *ctx)
1597 {
1598         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1599         struct render_state so;
1600         struct drm_i915_file_private *file_priv = ctx->file_priv;
1601         struct drm_file *file = file_priv ? file_priv->file : NULL;
1602         int ret;
1603
1604         ret = i915_gem_render_state_prepare(ring, &so);
1605         if (ret)
1606                 return ret;
1607
1608         if (so.rodata == NULL)
1609                 return 0;
1610
1611         ret = ring->emit_bb_start(ringbuf,
1612                         so.ggtt_offset,
1613                         I915_DISPATCH_SECURE);
1614         if (ret)
1615                 goto out;
1616
1617         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1618
1619         ret = __i915_add_request(ring, file, so.obj, NULL);
1620         /* intel_logical_ring_add_request moves object to inactive if it
1621          * fails */
1622 out:
1623         i915_gem_render_state_fini(&so);
1624         return ret;
1625 }
1626
1627 static int
1628 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1629                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1630 {
1631         struct drm_device *dev = ring->dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1634         struct page *page;
1635         uint32_t *reg_state;
1636         int ret;
1637
1638         if (!ppgtt)
1639                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1640
1641         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1642         if (ret) {
1643                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1644                 return ret;
1645         }
1646
1647         ret = i915_gem_object_get_pages(ctx_obj);
1648         if (ret) {
1649                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1650                 return ret;
1651         }
1652
1653         i915_gem_object_pin_pages(ctx_obj);
1654
1655         /* The second page of the context object contains some fields which must
1656          * be set up prior to the first execution. */
1657         page = i915_gem_object_get_page(ctx_obj, 1);
1658         reg_state = kmap_atomic(page);
1659
1660         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1661          * commands followed by (reg, value) pairs. The values we are setting here are
1662          * only for the first context restore: on a subsequent save, the GPU will
1663          * recreate this batchbuffer with new values (including all the missing
1664          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1665         if (ring->id == RCS)
1666                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1667         else
1668                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1669         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1670         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1671         reg_state[CTX_CONTEXT_CONTROL+1] =
1672                         _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1673         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1674         reg_state[CTX_RING_HEAD+1] = 0;
1675         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1676         reg_state[CTX_RING_TAIL+1] = 0;
1677         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1678         /* Ring buffer start address is not known until the buffer is pinned.
1679          * It is written to the context image in execlists_update_context()
1680          */
1681         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1682         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1683                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1684         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1685         reg_state[CTX_BB_HEAD_U+1] = 0;
1686         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1687         reg_state[CTX_BB_HEAD_L+1] = 0;
1688         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1689         reg_state[CTX_BB_STATE+1] = (1<<5);
1690         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1691         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1692         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1693         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1694         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1695         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1696         if (ring->id == RCS) {
1697                 /* TODO: according to BSpec, the register state context
1698                  * for CHV does not have these. OTOH, these registers do
1699                  * exist in CHV. I'm waiting for a clarification */
1700                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1701                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1702                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1703                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1704                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1705                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1706         }
1707         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1708         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1709         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1710         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1711         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1712         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1713         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1714         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1715         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1716         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1717         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1718         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1719         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1720         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1721         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1722         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1723         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1724         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1725         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1726         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1727         if (ring->id == RCS) {
1728                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1729                 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1730                 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1731         }
1732
1733         kunmap_atomic(reg_state);
1734
1735         ctx_obj->dirty = 1;
1736         set_page_dirty(page);
1737         i915_gem_object_unpin_pages(ctx_obj);
1738
1739         return 0;
1740 }
1741
1742 /**
1743  * intel_lr_context_free() - free the LRC specific bits of a context
1744  * @ctx: the LR context to free.
1745  *
1746  * The real context freeing is done in i915_gem_context_free: this only
1747  * takes care of the bits that are LRC related: the per-engine backing
1748  * objects and the logical ringbuffer.
1749  */
1750 void intel_lr_context_free(struct intel_context *ctx)
1751 {
1752         int i;
1753
1754         for (i = 0; i < I915_NUM_RINGS; i++) {
1755                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1756
1757                 if (ctx_obj) {
1758                         struct intel_ringbuffer *ringbuf =
1759                                         ctx->engine[i].ringbuf;
1760                         struct intel_engine_cs *ring = ringbuf->ring;
1761
1762                         if (ctx == ring->default_context) {
1763                                 intel_unpin_ringbuffer_obj(ringbuf);
1764                                 i915_gem_object_ggtt_unpin(ctx_obj);
1765                         }
1766                         intel_destroy_ringbuffer_obj(ringbuf);
1767                         kfree(ringbuf);
1768                         drm_gem_object_unreference(&ctx_obj->base);
1769                 }
1770         }
1771 }
1772
1773 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1774 {
1775         int ret = 0;
1776
1777         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1778
1779         switch (ring->id) {
1780         case RCS:
1781                 if (INTEL_INFO(ring->dev)->gen >= 9)
1782                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1783                 else
1784                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1785                 break;
1786         case VCS:
1787         case BCS:
1788         case VECS:
1789         case VCS2:
1790                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1791                 break;
1792         }
1793
1794         return ret;
1795 }
1796
1797 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1798                 struct drm_i915_gem_object *default_ctx_obj)
1799 {
1800         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1801
1802         /* The status page is offset 0 from the default context object
1803          * in LRC mode. */
1804         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1805         ring->status_page.page_addr =
1806                         kmap(sg_page(default_ctx_obj->pages->sgl));
1807         ring->status_page.obj = default_ctx_obj;
1808
1809         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1810                         (u32)ring->status_page.gfx_addr);
1811         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1812 }
1813
1814 /**
1815  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1816  * @ctx: LR context to create.
1817  * @ring: engine to be used with the context.
1818  *
1819  * This function can be called more than once, with different engines, if we plan
1820  * to use the context with them. The context backing objects and the ringbuffers
1821  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1822  * the creation is a deferred call: it's better to make sure first that we need to use
1823  * a given ring with the context.
1824  *
1825  * Return: non-zero on error.
1826  */
1827 int intel_lr_context_deferred_create(struct intel_context *ctx,
1828                                      struct intel_engine_cs *ring)
1829 {
1830         const bool is_global_default_ctx = (ctx == ring->default_context);
1831         struct drm_device *dev = ring->dev;
1832         struct drm_i915_gem_object *ctx_obj;
1833         uint32_t context_size;
1834         struct intel_ringbuffer *ringbuf;
1835         int ret;
1836
1837         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1838         if (ctx->engine[ring->id].state)
1839                 return 0;
1840
1841         context_size = round_up(get_lr_context_size(ring), 4096);
1842
1843         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1844         if (IS_ERR(ctx_obj)) {
1845                 ret = PTR_ERR(ctx_obj);
1846                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1847                 return ret;
1848         }
1849
1850         if (is_global_default_ctx) {
1851                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1852                 if (ret) {
1853                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1854                                         ret);
1855                         drm_gem_object_unreference(&ctx_obj->base);
1856                         return ret;
1857                 }
1858         }
1859
1860         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1861         if (!ringbuf) {
1862                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1863                                 ring->name);
1864                 ret = -ENOMEM;
1865                 goto error_unpin_ctx;
1866         }
1867
1868         ringbuf->ring = ring;
1869         ringbuf->FIXME_lrc_ctx = ctx;
1870
1871         ringbuf->size = 32 * PAGE_SIZE;
1872         ringbuf->effective_size = ringbuf->size;
1873         ringbuf->head = 0;
1874         ringbuf->tail = 0;
1875         ringbuf->space = ringbuf->size;
1876         ringbuf->last_retired_head = -1;
1877
1878         if (ringbuf->obj == NULL) {
1879                 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1880                 if (ret) {
1881                         DRM_DEBUG_DRIVER(
1882                                 "Failed to allocate ringbuffer obj %s: %d\n",
1883                                 ring->name, ret);
1884                         goto error_free_rbuf;
1885                 }
1886
1887                 if (is_global_default_ctx) {
1888                         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1889                         if (ret) {
1890                                 DRM_ERROR(
1891                                         "Failed to pin and map ringbuffer %s: %d\n",
1892                                         ring->name, ret);
1893                                 goto error_destroy_rbuf;
1894                         }
1895                 }
1896
1897         }
1898
1899         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1900         if (ret) {
1901                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1902                 goto error;
1903         }
1904
1905         ctx->engine[ring->id].ringbuf = ringbuf;
1906         ctx->engine[ring->id].state = ctx_obj;
1907
1908         if (ctx == ring->default_context)
1909                 lrc_setup_hardware_status_page(ring, ctx_obj);
1910
1911         if (ring->id == RCS && !ctx->rcs_initialized) {
1912                 if (ring->init_context) {
1913                         ret = ring->init_context(ring, ctx);
1914                         if (ret)
1915                                 DRM_ERROR("ring init context: %d\n", ret);
1916                 }
1917
1918                 ret = intel_lr_context_render_state_init(ring, ctx);
1919                 if (ret) {
1920                         DRM_ERROR("Init render state failed: %d\n", ret);
1921                         ctx->engine[ring->id].ringbuf = NULL;
1922                         ctx->engine[ring->id].state = NULL;
1923                         goto error;
1924                 }
1925                 ctx->rcs_initialized = true;
1926         }
1927
1928         return 0;
1929
1930 error:
1931         if (is_global_default_ctx)
1932                 intel_unpin_ringbuffer_obj(ringbuf);
1933 error_destroy_rbuf:
1934         intel_destroy_ringbuffer_obj(ringbuf);
1935 error_free_rbuf:
1936         kfree(ringbuf);
1937 error_unpin_ctx:
1938         if (is_global_default_ctx)
1939                 i915_gem_object_ggtt_unpin(ctx_obj);
1940         drm_gem_object_unreference(&ctx_obj->base);
1941         return ret;
1942 }