drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  35  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  36  * during in-memory transfers and, therefore, reduce the power packet.
  37  *
  38  * The benefits of FBC are mostly visible with solid backgrounds and
  39  * variation-less patterns.
  40  *
  41  * FBC-related functionality can be enabled by the means of the
  42  * i915.i915_enable_fbc parameter
  43  */
  44
  45 static void i8xx_disable_fbc(struct drm_device *dev)
  46 {
  47         struct drm_i915_private *dev_priv = dev->dev_private;
  48         u32 fbc_ctl;
  49
  50         /* Disable compression */
  51         fbc_ctl = I915_READ(FBC_CONTROL);
  52         if ((fbc_ctl & FBC_CTL_EN) == 0)
  53                 return;
  54
  55         fbc_ctl &= ~FBC_CTL_EN;
  56         I915_WRITE(FBC_CONTROL, fbc_ctl);
  57
  58         /* Wait for compressing bit to clear */
  59         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  60                 DRM_DEBUG_KMS("FBC idle timed out\n");
  61                 return;
  62         }
  63
  64         DRM_DEBUG_KMS("disabled FBC\n");
  65 }
  66
  67 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  68 {
  69         struct drm_device *dev = crtc->dev;
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         struct drm_framebuffer *fb = crtc->fb;
  72         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  73         struct drm_i915_gem_object *obj = intel_fb->obj;
  74         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  75         int cfb_pitch;
  76         int plane, i;
  77         u32 fbc_ctl, fbc_ctl2;
  78
  79         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  80         if (fb->pitches[0] < cfb_pitch)
  81                 cfb_pitch = fb->pitches[0];
  82
  83         /* FBC_CTL wants 64B units */
  84         cfb_pitch = (cfb_pitch / 64) - 1;
  85         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  86
  87         /* Clear old tags */
  88         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  89                 I915_WRITE(FBC_TAG + (i * 4), 0);
  90
  91         /* Set it up... */
  92         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  93         fbc_ctl2 |= plane;
  94         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  95         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  96
  97         /* enable it... */
  98         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  99         if (IS_I945GM(dev))
 100                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 101         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 102         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 103         fbc_ctl |= obj->fence_reg;
 104         I915_WRITE(FBC_CONTROL, fbc_ctl);
 105
 106         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 107                       cfb_pitch, crtc->y, intel_crtc->plane);
 108 }
 109
 110 static bool i8xx_fbc_enabled(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = dev->dev_private;
 113
 114         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 115 }
 116
 117 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 118 {
 119         struct drm_device *dev = crtc->dev;
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         struct drm_framebuffer *fb = crtc->fb;
 122         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 123         struct drm_i915_gem_object *obj = intel_fb->obj;
 124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 125         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 126         unsigned long stall_watermark = 200;
 127         u32 dpfc_ctl;
 128
 129         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 130         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 131         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 132
 133         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 134                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 135                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 136         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 137
 138         /* enable it... */
 139         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 140
 141         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 142 }
 143
 144 static void g4x_disable_fbc(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         u32 dpfc_ctl;
 148
 149         /* Disable compression */
 150         dpfc_ctl = I915_READ(DPFC_CONTROL);
 151         if (dpfc_ctl & DPFC_CTL_EN) {
 152                 dpfc_ctl &= ~DPFC_CTL_EN;
 153                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 154
 155                 DRM_DEBUG_KMS("disabled FBC\n");
 156         }
 157 }
 158
 159 static bool g4x_fbc_enabled(struct drm_device *dev)
 160 {
 161         struct drm_i915_private *dev_priv = dev->dev_private;
 162
 163         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 164 }
 165
 166 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         u32 blt_ecoskpd;
 170
 171         /* Make sure blitter notifies FBC of writes */
 172         gen6_gt_force_wake_get(dev_priv);
 173         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 174         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 175                 GEN6_BLITTER_LOCK_SHIFT;
 176         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 177         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 178         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 179         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 180                          GEN6_BLITTER_LOCK_SHIFT);
 181         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 182         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 183         gen6_gt_force_wake_put(dev_priv);
 184 }
 185
 186 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 187 {
 188         struct drm_device *dev = crtc->dev;
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190         struct drm_framebuffer *fb = crtc->fb;
 191         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 192         struct drm_i915_gem_object *obj = intel_fb->obj;
 193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 194         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 195         unsigned long stall_watermark = 200;
 196         u32 dpfc_ctl;
 197
 198         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 199         dpfc_ctl &= DPFC_RESERVED;
 200         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 201         /* Set persistent mode for front-buffer rendering, ala X. */
 202         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 203         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 204         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 205
 206         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 207                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 208                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 209         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 210         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 211         /* enable it... */
 212         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 213
 214         if (IS_GEN6(dev)) {
 215                 I915_WRITE(SNB_DPFC_CTL_SA,
 216                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 217                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 218                 sandybridge_blit_fbc_update(dev);
 219         }
 220
 221         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 222 }
 223
 224 static void ironlake_disable_fbc(struct drm_device *dev)
 225 {
 226         struct drm_i915_private *dev_priv = dev->dev_private;
 227         u32 dpfc_ctl;
 228
 229         /* Disable compression */
 230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 231         if (dpfc_ctl & DPFC_CTL_EN) {
 232                 dpfc_ctl &= ~DPFC_CTL_EN;
 233                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 234
 235                 DRM_DEBUG_KMS("disabled FBC\n");
 236         }
 237 }
 238
 239 static bool ironlake_fbc_enabled(struct drm_device *dev)
 240 {
 241         struct drm_i915_private *dev_priv = dev->dev_private;
 242
 243         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 244 }
 245
 246 bool intel_fbc_enabled(struct drm_device *dev)
 247 {
 248         struct drm_i915_private *dev_priv = dev->dev_private;
 249
 250         if (!dev_priv->display.fbc_enabled)
 251                 return false;
 252
 253         return dev_priv->display.fbc_enabled(dev);
 254 }
 255
 256 static void intel_fbc_work_fn(struct work_struct *__work)
 257 {
 258         struct intel_fbc_work *work =
 259                 container_of(to_delayed_work(__work),
 260                              struct intel_fbc_work, work);
 261         struct drm_device *dev = work->crtc->dev;
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263
 264         mutex_lock(&dev->struct_mutex);
 265         if (work == dev_priv->fbc_work) {
 266                 /* Double check that we haven't switched fb without cancelling
 267                  * the prior work.
 268                  */
 269                 if (work->crtc->fb == work->fb) {
 270                         dev_priv->display.enable_fbc(work->crtc,
 271                                                      work->interval);
 272
 273                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 274                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 275                         dev_priv->cfb_y = work->crtc->y;
 276                 }
 277
 278                 dev_priv->fbc_work = NULL;
 279         }
 280         mutex_unlock(&dev->struct_mutex);
 281
 282         kfree(work);
 283 }
 284
 285 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 286 {
 287         if (dev_priv->fbc_work == NULL)
 288                 return;
 289
 290         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 291
 292         /* Synchronisation is provided by struct_mutex and checking of
 293          * dev_priv->fbc_work, so we can perform the cancellation
 294          * entirely asynchronously.
 295          */
 296         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 297                 /* tasklet was killed before being run, clean up */
 298                 kfree(dev_priv->fbc_work);
 299
 300         /* Mark the work as no longer wanted so that if it does
 301          * wake-up (because the work was already running and waiting
 302          * for our mutex), it will discover that is no longer
 303          * necessary to run.
 304          */
 305         dev_priv->fbc_work = NULL;
 306 }
 307
 308 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 309 {
 310         struct intel_fbc_work *work;
 311         struct drm_device *dev = crtc->dev;
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         if (!dev_priv->display.enable_fbc)
 315                 return;
 316
 317         intel_cancel_fbc_work(dev_priv);
 318
 319         work = kzalloc(sizeof *work, GFP_KERNEL);
 320         if (work == NULL) {
 321                 dev_priv->display.enable_fbc(crtc, interval);
 322                 return;
 323         }
 324
 325         work->crtc = crtc;
 326         work->fb = crtc->fb;
 327         work->interval = interval;
 328         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 329
 330         dev_priv->fbc_work = work;
 331
 332         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 333
 334         /* Delay the actual enabling to let pageflipping cease and the
 335          * display to settle before starting the compression. Note that
 336          * this delay also serves a second purpose: it allows for a
 337          * vblank to pass after disabling the FBC before we attempt
 338          * to modify the control registers.
 339          *
 340          * A more complicated solution would involve tracking vblanks
 341          * following the termination of the page-flipping sequence
 342          * and indeed performing the enable as a co-routine and not
 343          * waiting synchronously upon the vblank.
 344          */
 345         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 346 }
 347
 348 void intel_disable_fbc(struct drm_device *dev)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351
 352         intel_cancel_fbc_work(dev_priv);
 353
 354         if (!dev_priv->display.disable_fbc)
 355                 return;
 356
 357         dev_priv->display.disable_fbc(dev);
 358         dev_priv->cfb_plane = -1;
 359 }
 360
 361 /**
 362  * intel_update_fbc - enable/disable FBC as needed
 363  * @dev: the drm_device
 364  *
 365  * Set up the framebuffer compression hardware at mode set time.  We
 366  * enable it if possible:
 367  *   - plane A only (on pre-965)
 368  *   - no pixel mulitply/line duplication
 369  *   - no alpha buffer discard
 370  *   - no dual wide
 371  *   - framebuffer <= 2048 in width, 1536 in height
 372  *
 373  * We can't assume that any compression will take place (worst case),
 374  * so the compressed buffer has to be the same size as the uncompressed
 375  * one.  It also must reside (along with the line length buffer) in
 376  * stolen memory.
 377  *
 378  * We need to enable/disable FBC on a global basis.
 379  */
 380 void intel_update_fbc(struct drm_device *dev)
 381 {
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         struct drm_crtc *crtc = NULL, *tmp_crtc;
 384         struct intel_crtc *intel_crtc;
 385         struct drm_framebuffer *fb;
 386         struct intel_framebuffer *intel_fb;
 387         struct drm_i915_gem_object *obj;
 388         int enable_fbc;
 389
 390         DRM_DEBUG_KMS("\n");
 391
 392         if (!i915_powersave)
 393                 return;
 394
 395         if (!I915_HAS_FBC(dev))
 396                 return;
 397
 398         /*
 399          * If FBC is already on, we just have to verify that we can
 400          * keep it that way...
 401          * Need to disable if:
 402          *   - more than one pipe is active
 403          *   - changing FBC params (stride, fence, mode)
 404          *   - new fb is too large to fit in compressed buffer
 405          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 406          */
 407         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 408                 if (tmp_crtc->enabled && tmp_crtc->fb) {
 409                         if (crtc) {
 410                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 411                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 412                                 goto out_disable;
 413                         }
 414                         crtc = tmp_crtc;
 415                 }
 416         }
 417
 418         if (!crtc || crtc->fb == NULL) {
 419                 DRM_DEBUG_KMS("no output, disabling\n");
 420                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 421                 goto out_disable;
 422         }
 423
 424         intel_crtc = to_intel_crtc(crtc);
 425         fb = crtc->fb;
 426         intel_fb = to_intel_framebuffer(fb);
 427         obj = intel_fb->obj;
 428
 429         enable_fbc = i915_enable_fbc;
 430         if (enable_fbc < 0) {
 431                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 432                 enable_fbc = 1;
 433                 if (INTEL_INFO(dev)->gen <= 6)
 434                         enable_fbc = 0;
 435         }
 436         if (!enable_fbc) {
 437                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 438                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 439                 goto out_disable;
 440         }
 441         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
 442                 DRM_DEBUG_KMS("framebuffer too large, disabling "
 443                               "compression\n");
 444                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 445                 goto out_disable;
 446         }
 447         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 448             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 449                 DRM_DEBUG_KMS("mode incompatible with compression, "
 450                               "disabling\n");
 451                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 452                 goto out_disable;
 453         }
 454         if ((crtc->mode.hdisplay > 2048) ||
 455             (crtc->mode.vdisplay > 1536)) {
 456                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 457                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 458                 goto out_disable;
 459         }
 460         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 461                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 462                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 463                 goto out_disable;
 464         }
 465
 466         /* The use of a CPU fence is mandatory in order to detect writes
 467          * by the CPU to the scanout and trigger updates to the FBC.
 468          */
 469         if (obj->tiling_mode != I915_TILING_X ||
 470             obj->fence_reg == I915_FENCE_REG_NONE) {
 471                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 472                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 473                 goto out_disable;
 474         }
 475
 476         /* If the kernel debugger is active, always disable compression */
 477         if (in_dbg_master())
 478                 goto out_disable;
 479
 480         /* If the scanout has not changed, don't modify the FBC settings.
 481          * Note that we make the fundamental assumption that the fb->obj
 482          * cannot be unpinned (and have its GTT offset and fence revoked)
 483          * without first being decoupled from the scanout and FBC disabled.
 484          */
 485         if (dev_priv->cfb_plane == intel_crtc->plane &&
 486             dev_priv->cfb_fb == fb->base.id &&
 487             dev_priv->cfb_y == crtc->y)
 488                 return;
 489
 490         if (intel_fbc_enabled(dev)) {
 491                 /* We update FBC along two paths, after changing fb/crtc
 492                  * configuration (modeswitching) and after page-flipping
 493                  * finishes. For the latter, we know that not only did
 494                  * we disable the FBC at the start of the page-flip
 495                  * sequence, but also more than one vblank has passed.
 496                  *
 497                  * For the former case of modeswitching, it is possible
 498                  * to switch between two FBC valid configurations
 499                  * instantaneously so we do need to disable the FBC
 500                  * before we can modify its control registers. We also
 501                  * have to wait for the next vblank for that to take
 502                  * effect. However, since we delay enabling FBC we can
 503                  * assume that a vblank has passed since disabling and
 504                  * that we can safely alter the registers in the deferred
 505                  * callback.
 506                  *
 507                  * In the scenario that we go from a valid to invalid
 508                  * and then back to valid FBC configuration we have
 509                  * no strict enforcement that a vblank occurred since
 510                  * disabling the FBC. However, along all current pipe
 511                  * disabling paths we do need to wait for a vblank at
 512                  * some point. And we wait before enabling FBC anyway.
 513                  */
 514                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 515                 intel_disable_fbc(dev);
 516         }
 517
 518         intel_enable_fbc(crtc, 500);
 519         return;
 520
 521 out_disable:
 522         /* Multiple disables should be harmless */
 523         if (intel_fbc_enabled(dev)) {
 524                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 525                 intel_disable_fbc(dev);
 526         }
 527 }
 528
 529 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 530 {
 531         drm_i915_private_t *dev_priv = dev->dev_private;
 532         u32 tmp;
 533
 534         tmp = I915_READ(CLKCFG);
 535
 536         switch (tmp & CLKCFG_FSB_MASK) {
 537         case CLKCFG_FSB_533:
 538                 dev_priv->fsb_freq = 533; /* 133*4 */
 539                 break;
 540         case CLKCFG_FSB_800:
 541                 dev_priv->fsb_freq = 800; /* 200*4 */
 542                 break;
 543         case CLKCFG_FSB_667:
 544                 dev_priv->fsb_freq =  667; /* 167*4 */
 545                 break;
 546         case CLKCFG_FSB_400:
 547                 dev_priv->fsb_freq = 400; /* 100*4 */
 548                 break;
 549         }
 550
 551         switch (tmp & CLKCFG_MEM_MASK) {
 552         case CLKCFG_MEM_533:
 553                 dev_priv->mem_freq = 533;
 554                 break;
 555         case CLKCFG_MEM_667:
 556                 dev_priv->mem_freq = 667;
 557                 break;
 558         case CLKCFG_MEM_800:
 559                 dev_priv->mem_freq = 800;
 560                 break;
 561         }
 562
 563         /* detect pineview DDR3 setting */
 564         tmp = I915_READ(CSHRDDR3CTL);
 565         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 566 }
 567
 568 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 569 {
 570         drm_i915_private_t *dev_priv = dev->dev_private;
 571         u16 ddrpll, csipll;
 572
 573         ddrpll = I915_READ16(DDRMPLL1);
 574         csipll = I915_READ16(CSIPLL0);
 575
 576         switch (ddrpll & 0xff) {
 577         case 0xc:
 578                 dev_priv->mem_freq = 800;
 579                 break;
 580         case 0x10:
 581                 dev_priv->mem_freq = 1066;
 582                 break;
 583         case 0x14:
 584                 dev_priv->mem_freq = 1333;
 585                 break;
 586         case 0x18:
 587                 dev_priv->mem_freq = 1600;
 588                 break;
 589         default:
 590                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 591                                  ddrpll & 0xff);
 592                 dev_priv->mem_freq = 0;
 593                 break;
 594         }
 595
 596         dev_priv->r_t = dev_priv->mem_freq;
 597
 598         switch (csipll & 0x3ff) {
 599         case 0x00c:
 600                 dev_priv->fsb_freq = 3200;
 601                 break;
 602         case 0x00e:
 603                 dev_priv->fsb_freq = 3733;
 604                 break;
 605         case 0x010:
 606                 dev_priv->fsb_freq = 4266;
 607                 break;
 608         case 0x012:
 609                 dev_priv->fsb_freq = 4800;
 610                 break;
 611         case 0x014:
 612                 dev_priv->fsb_freq = 5333;
 613                 break;
 614         case 0x016:
 615                 dev_priv->fsb_freq = 5866;
 616                 break;
 617         case 0x018:
 618                 dev_priv->fsb_freq = 6400;
 619                 break;
 620         default:
 621                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 622                                  csipll & 0x3ff);
 623                 dev_priv->fsb_freq = 0;
 624                 break;
 625         }
 626
 627         if (dev_priv->fsb_freq == 3200) {
 628                 dev_priv->c_m = 0;
 629         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 630                 dev_priv->c_m = 1;
 631         } else {
 632                 dev_priv->c_m = 2;
 633         }
 634 }
 635
 636 static const struct cxsr_latency cxsr_latency_table[] = {
 637         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 638         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 639         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 640         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 641         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 642
 643         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 644         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 645         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 646         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 647         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 648
 649         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 650         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 651         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 652         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 653         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 654
 655         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 656         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 657         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 658         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 659         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 660
 661         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 662         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 663         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 664         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 665         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 666
 667         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 668         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 669         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 670         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 671         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 672 };
 673
 674 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 675                                                          int is_ddr3,
 676                                                          int fsb,
 677                                                          int mem)
 678 {
 679         const struct cxsr_latency *latency;
 680         int i;
 681
 682         if (fsb == 0 || mem == 0)
 683                 return NULL;
 684
 685         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 686                 latency = &cxsr_latency_table[i];
 687                 if (is_desktop == latency->is_desktop &&
 688                     is_ddr3 == latency->is_ddr3 &&
 689                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 690                         return latency;
 691         }
 692
 693         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 694
 695         return NULL;
 696 }
 697
 698 static void pineview_disable_cxsr(struct drm_device *dev)
 699 {
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701
 702         /* deactivate cxsr */
 703         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 704 }
 705
 706 /*
 707  * Latency for FIFO fetches is dependent on several factors:
 708  *   - memory configuration (speed, channels)
 709  *   - chipset
 710  *   - current MCH state
 711  * It can be fairly high in some situations, so here we assume a fairly
 712  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 713  * set this value too high, the FIFO will fetch frequently to stay full)
 714  * and power consumption (set it too low to save power and we might see
 715  * FIFO underruns and display "flicker").
 716  *
 717  * A value of 5us seems to be a good balance; safe for very low end
 718  * platforms but not overly aggressive on lower latency configs.
 719  */
 720 static const int latency_ns = 5000;
 721
 722 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725         uint32_t dsparb = I915_READ(DSPARB);
 726         int size;
 727
 728         size = dsparb & 0x7f;
 729         if (plane)
 730                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 731
 732         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 733                       plane ? "B" : "A", size);
 734
 735         return size;
 736 }
 737
 738 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 739 {
 740         struct drm_i915_private *dev_priv = dev->dev_private;
 741         uint32_t dsparb = I915_READ(DSPARB);
 742         int size;
 743
 744         size = dsparb & 0x1ff;
 745         if (plane)
 746                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 747         size >>= 1; /* Convert to cachelines */
 748
 749         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 750                       plane ? "B" : "A", size);
 751
 752         return size;
 753 }
 754
 755 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 756 {
 757         struct drm_i915_private *dev_priv = dev->dev_private;
 758         uint32_t dsparb = I915_READ(DSPARB);
 759         int size;
 760
 761         size = dsparb & 0x7f;
 762         size >>= 2; /* Convert to cachelines */
 763
 764         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 765                       plane ? "B" : "A",
 766                       size);
 767
 768         return size;
 769 }
 770
 771 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         uint32_t dsparb = I915_READ(DSPARB);
 775         int size;
 776
 777         size = dsparb & 0x7f;
 778         size >>= 1; /* Convert to cachelines */
 779
 780         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 781                       plane ? "B" : "A", size);
 782
 783         return size;
 784 }
 785
 786 /* Pineview has different values for various configs */
 787 static const struct intel_watermark_params pineview_display_wm = {
 788         PINEVIEW_DISPLAY_FIFO,
 789         PINEVIEW_MAX_WM,
 790         PINEVIEW_DFT_WM,
 791         PINEVIEW_GUARD_WM,
 792         PINEVIEW_FIFO_LINE_SIZE
 793 };
 794 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 795         PINEVIEW_DISPLAY_FIFO,
 796         PINEVIEW_MAX_WM,
 797         PINEVIEW_DFT_HPLLOFF_WM,
 798         PINEVIEW_GUARD_WM,
 799         PINEVIEW_FIFO_LINE_SIZE
 800 };
 801 static const struct intel_watermark_params pineview_cursor_wm = {
 802         PINEVIEW_CURSOR_FIFO,
 803         PINEVIEW_CURSOR_MAX_WM,
 804         PINEVIEW_CURSOR_DFT_WM,
 805         PINEVIEW_CURSOR_GUARD_WM,
 806         PINEVIEW_FIFO_LINE_SIZE,
 807 };
 808 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 809         PINEVIEW_CURSOR_FIFO,
 810         PINEVIEW_CURSOR_MAX_WM,
 811         PINEVIEW_CURSOR_DFT_WM,
 812         PINEVIEW_CURSOR_GUARD_WM,
 813         PINEVIEW_FIFO_LINE_SIZE
 814 };
 815 static const struct intel_watermark_params g4x_wm_info = {
 816         G4X_FIFO_SIZE,
 817         G4X_MAX_WM,
 818         G4X_MAX_WM,
 819         2,
 820         G4X_FIFO_LINE_SIZE,
 821 };
 822 static const struct intel_watermark_params g4x_cursor_wm_info = {
 823         I965_CURSOR_FIFO,
 824         I965_CURSOR_MAX_WM,
 825         I965_CURSOR_DFT_WM,
 826         2,
 827         G4X_FIFO_LINE_SIZE,
 828 };
 829 static const struct intel_watermark_params valleyview_wm_info = {
 830         VALLEYVIEW_FIFO_SIZE,
 831         VALLEYVIEW_MAX_WM,
 832         VALLEYVIEW_MAX_WM,
 833         2,
 834         G4X_FIFO_LINE_SIZE,
 835 };
 836 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 837         I965_CURSOR_FIFO,
 838         VALLEYVIEW_CURSOR_MAX_WM,
 839         I965_CURSOR_DFT_WM,
 840         2,
 841         G4X_FIFO_LINE_SIZE,
 842 };
 843 static const struct intel_watermark_params i965_cursor_wm_info = {
 844         I965_CURSOR_FIFO,
 845         I965_CURSOR_MAX_WM,
 846         I965_CURSOR_DFT_WM,
 847         2,
 848         I915_FIFO_LINE_SIZE,
 849 };
 850 static const struct intel_watermark_params i945_wm_info = {
 851         I945_FIFO_SIZE,
 852         I915_MAX_WM,
 853         1,
 854         2,
 855         I915_FIFO_LINE_SIZE
 856 };
 857 static const struct intel_watermark_params i915_wm_info = {
 858         I915_FIFO_SIZE,
 859         I915_MAX_WM,
 860         1,
 861         2,
 862         I915_FIFO_LINE_SIZE
 863 };
 864 static const struct intel_watermark_params i855_wm_info = {
 865         I855GM_FIFO_SIZE,
 866         I915_MAX_WM,
 867         1,
 868         2,
 869         I830_FIFO_LINE_SIZE
 870 };
 871 static const struct intel_watermark_params i830_wm_info = {
 872         I830_FIFO_SIZE,
 873         I915_MAX_WM,
 874         1,
 875         2,
 876         I830_FIFO_LINE_SIZE
 877 };
 878
 879 static const struct intel_watermark_params ironlake_display_wm_info = {
 880         ILK_DISPLAY_FIFO,
 881         ILK_DISPLAY_MAXWM,
 882         ILK_DISPLAY_DFTWM,
 883         2,
 884         ILK_FIFO_LINE_SIZE
 885 };
 886 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 887         ILK_CURSOR_FIFO,
 888         ILK_CURSOR_MAXWM,
 889         ILK_CURSOR_DFTWM,
 890         2,
 891         ILK_FIFO_LINE_SIZE
 892 };
 893 static const struct intel_watermark_params ironlake_display_srwm_info = {
 894         ILK_DISPLAY_SR_FIFO,
 895         ILK_DISPLAY_MAX_SRWM,
 896         ILK_DISPLAY_DFT_SRWM,
 897         2,
 898         ILK_FIFO_LINE_SIZE
 899 };
 900 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 901         ILK_CURSOR_SR_FIFO,
 902         ILK_CURSOR_MAX_SRWM,
 903         ILK_CURSOR_DFT_SRWM,
 904         2,
 905         ILK_FIFO_LINE_SIZE
 906 };
 907
 908 static const struct intel_watermark_params sandybridge_display_wm_info = {
 909         SNB_DISPLAY_FIFO,
 910         SNB_DISPLAY_MAXWM,
 911         SNB_DISPLAY_DFTWM,
 912         2,
 913         SNB_FIFO_LINE_SIZE
 914 };
 915 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 916         SNB_CURSOR_FIFO,
 917         SNB_CURSOR_MAXWM,
 918         SNB_CURSOR_DFTWM,
 919         2,
 920         SNB_FIFO_LINE_SIZE
 921 };
 922 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 923         SNB_DISPLAY_SR_FIFO,
 924         SNB_DISPLAY_MAX_SRWM,
 925         SNB_DISPLAY_DFT_SRWM,
 926         2,
 927         SNB_FIFO_LINE_SIZE
 928 };
 929 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 930         SNB_CURSOR_SR_FIFO,
 931         SNB_CURSOR_MAX_SRWM,
 932         SNB_CURSOR_DFT_SRWM,
 933         2,
 934         SNB_FIFO_LINE_SIZE
 935 };
 936
 937
 938 /**
 939  * intel_calculate_wm - calculate watermark level
 940  * @clock_in_khz: pixel clock
 941  * @wm: chip FIFO params
 942  * @pixel_size: display pixel size
 943  * @latency_ns: memory latency for the platform
 944  *
 945  * Calculate the watermark level (the level at which the display plane will
 946  * start fetching from memory again).  Each chip has a different display
 947  * FIFO size and allocation, so the caller needs to figure that out and pass
 948  * in the correct intel_watermark_params structure.
 949  *
 950  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 951  * on the pixel size.  When it reaches the watermark level, it'll start
 952  * fetching FIFO line sized based chunks from memory until the FIFO fills
 953  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 954  * will occur, and a display engine hang could result.
 955  */
 956 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 957                                         const struct intel_watermark_params *wm,
 958                                         int fifo_size,
 959                                         int pixel_size,
 960                                         unsigned long latency_ns)
 961 {
 962         long entries_required, wm_size;
 963
 964         /*
 965          * Note: we need to make sure we don't overflow for various clock &
 966          * latency values.
 967          * clocks go from a few thousand to several hundred thousand.
 968          * latency is usually a few thousand
 969          */
 970         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 971                 1000;
 972         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 973
 974         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 975
 976         wm_size = fifo_size - (entries_required + wm->guard_size);
 977
 978         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 979
 980         /* Don't promote wm_size to unsigned... */
 981         if (wm_size > (long)wm->max_wm)
 982                 wm_size = wm->max_wm;
 983         if (wm_size <= 0)
 984                 wm_size = wm->default_wm;
 985         return wm_size;
 986 }
 987
 988 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 989 {
 990         struct drm_crtc *crtc, *enabled = NULL;
 991
 992         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 993                 if (crtc->enabled && crtc->fb) {
 994                         if (enabled)
 995                                 return NULL;
 996                         enabled = crtc;
 997                 }
 998         }
 999
1000         return enabled;
1001 }
1002
1003 static void pineview_update_wm(struct drm_device *dev)
1004 {
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         struct drm_crtc *crtc;
1007         const struct cxsr_latency *latency;
1008         u32 reg;
1009         unsigned long wm;
1010
1011         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1012                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1013         if (!latency) {
1014                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1015                 pineview_disable_cxsr(dev);
1016                 return;
1017         }
1018
1019         crtc = single_enabled_crtc(dev);
1020         if (crtc) {
1021                 int clock = crtc->mode.clock;
1022                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1023
1024                 /* Display SR */
1025                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1026                                         pineview_display_wm.fifo_size,
1027                                         pixel_size, latency->display_sr);
1028                 reg = I915_READ(DSPFW1);
1029                 reg &= ~DSPFW_SR_MASK;
1030                 reg |= wm << DSPFW_SR_SHIFT;
1031                 I915_WRITE(DSPFW1, reg);
1032                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1033
1034                 /* cursor SR */
1035                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1036                                         pineview_display_wm.fifo_size,
1037                                         pixel_size, latency->cursor_sr);
1038                 reg = I915_READ(DSPFW3);
1039                 reg &= ~DSPFW_CURSOR_SR_MASK;
1040                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1041                 I915_WRITE(DSPFW3, reg);
1042
1043                 /* Display HPLL off SR */
1044                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1045                                         pineview_display_hplloff_wm.fifo_size,
1046                                         pixel_size, latency->display_hpll_disable);
1047                 reg = I915_READ(DSPFW3);
1048                 reg &= ~DSPFW_HPLL_SR_MASK;
1049                 reg |= wm & DSPFW_HPLL_SR_MASK;
1050                 I915_WRITE(DSPFW3, reg);
1051
1052                 /* cursor HPLL off SR */
1053                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1054                                         pineview_display_hplloff_wm.fifo_size,
1055                                         pixel_size, latency->cursor_hpll_disable);
1056                 reg = I915_READ(DSPFW3);
1057                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1058                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1059                 I915_WRITE(DSPFW3, reg);
1060                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1061
1062                 /* activate cxsr */
1063                 I915_WRITE(DSPFW3,
1064                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1065                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1066         } else {
1067                 pineview_disable_cxsr(dev);
1068                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1069         }
1070 }
1071
1072 static bool g4x_compute_wm0(struct drm_device *dev,
1073                             int plane,
1074                             const struct intel_watermark_params *display,
1075                             int display_latency_ns,
1076                             const struct intel_watermark_params *cursor,
1077                             int cursor_latency_ns,
1078                             int *plane_wm,
1079                             int *cursor_wm)
1080 {
1081         struct drm_crtc *crtc;
1082         int htotal, hdisplay, clock, pixel_size;
1083         int line_time_us, line_count;
1084         int entries, tlb_miss;
1085
1086         crtc = intel_get_crtc_for_plane(dev, plane);
1087         if (crtc->fb == NULL || !crtc->enabled) {
1088                 *cursor_wm = cursor->guard_size;
1089                 *plane_wm = display->guard_size;
1090                 return false;
1091         }
1092
1093         htotal = crtc->mode.htotal;
1094         hdisplay = crtc->mode.hdisplay;
1095         clock = crtc->mode.clock;
1096         pixel_size = crtc->fb->bits_per_pixel / 8;
1097
1098         /* Use the small buffer method to calculate plane watermark */
1099         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1100         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1101         if (tlb_miss > 0)
1102                 entries += tlb_miss;
1103         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1104         *plane_wm = entries + display->guard_size;
1105         if (*plane_wm > (int)display->max_wm)
1106                 *plane_wm = display->max_wm;
1107
1108         /* Use the large buffer method to calculate cursor watermark */
1109         line_time_us = ((htotal * 1000) / clock);
1110         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1111         entries = line_count * 64 * pixel_size;
1112         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1113         if (tlb_miss > 0)
1114                 entries += tlb_miss;
1115         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1116         *cursor_wm = entries + cursor->guard_size;
1117         if (*cursor_wm > (int)cursor->max_wm)
1118                 *cursor_wm = (int)cursor->max_wm;
1119
1120         return true;
1121 }
1122
1123 /*
1124  * Check the wm result.
1125  *
1126  * If any calculated watermark values is larger than the maximum value that
1127  * can be programmed into the associated watermark register, that watermark
1128  * must be disabled.
1129  */
1130 static bool g4x_check_srwm(struct drm_device *dev,
1131                            int display_wm, int cursor_wm,
1132                            const struct intel_watermark_params *display,
1133                            const struct intel_watermark_params *cursor)
1134 {
1135         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1136                       display_wm, cursor_wm);
1137
1138         if (display_wm > display->max_wm) {
1139                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1140                               display_wm, display->max_wm);
1141                 return false;
1142         }
1143
1144         if (cursor_wm > cursor->max_wm) {
1145                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1146                               cursor_wm, cursor->max_wm);
1147                 return false;
1148         }
1149
1150         if (!(display_wm || cursor_wm)) {
1151                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1152                 return false;
1153         }
1154
1155         return true;
1156 }
1157
1158 static bool g4x_compute_srwm(struct drm_device *dev,
1159                              int plane,
1160                              int latency_ns,
1161                              const struct intel_watermark_params *display,
1162                              const struct intel_watermark_params *cursor,
1163                              int *display_wm, int *cursor_wm)
1164 {
1165         struct drm_crtc *crtc;
1166         int hdisplay, htotal, pixel_size, clock;
1167         unsigned long line_time_us;
1168         int line_count, line_size;
1169         int small, large;
1170         int entries;
1171
1172         if (!latency_ns) {
1173                 *display_wm = *cursor_wm = 0;
1174                 return false;
1175         }
1176
1177         crtc = intel_get_crtc_for_plane(dev, plane);
1178         hdisplay = crtc->mode.hdisplay;
1179         htotal = crtc->mode.htotal;
1180         clock = crtc->mode.clock;
1181         pixel_size = crtc->fb->bits_per_pixel / 8;
1182
1183         line_time_us = (htotal * 1000) / clock;
1184         line_count = (latency_ns / line_time_us + 1000) / 1000;
1185         line_size = hdisplay * pixel_size;
1186
1187         /* Use the minimum of the small and large buffer method for primary */
1188         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1189         large = line_count * line_size;
1190
1191         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1192         *display_wm = entries + display->guard_size;
1193
1194         /* calculate the self-refresh watermark for display cursor */
1195         entries = line_count * pixel_size * 64;
1196         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1197         *cursor_wm = entries + cursor->guard_size;
1198
1199         return g4x_check_srwm(dev,
1200                               *display_wm, *cursor_wm,
1201                               display, cursor);
1202 }
1203
1204 static bool vlv_compute_drain_latency(struct drm_device *dev,
1205                                      int plane,
1206                                      int *plane_prec_mult,
1207                                      int *plane_dl,
1208                                      int *cursor_prec_mult,
1209                                      int *cursor_dl)
1210 {
1211         struct drm_crtc *crtc;
1212         int clock, pixel_size;
1213         int entries;
1214
1215         crtc = intel_get_crtc_for_plane(dev, plane);
1216         if (crtc->fb == NULL || !crtc->enabled)
1217                 return false;
1218
1219         clock = crtc->mode.clock;       /* VESA DOT Clock */
1220         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1221
1222         entries = (clock / 1000) * pixel_size;
1223         *plane_prec_mult = (entries > 256) ?
1224                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1225         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1226                                                      pixel_size);
1227
1228         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1229         *cursor_prec_mult = (entries > 256) ?
1230                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1231         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1232
1233         return true;
1234 }
1235
1236 /*
1237  * Update drain latency registers of memory arbiter
1238  *
1239  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1240  * to be programmed. Each plane has a drain latency multiplier and a drain
1241  * latency value.
1242  */
1243
1244 static void vlv_update_drain_latency(struct drm_device *dev)
1245 {
1246         struct drm_i915_private *dev_priv = dev->dev_private;
1247         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1248         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1249         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1250                                                         either 16 or 32 */
1251
1252         /* For plane A, Cursor A */
1253         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1254                                       &cursor_prec_mult, &cursora_dl)) {
1255                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1256                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1257                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1259
1260                 I915_WRITE(VLV_DDL1, cursora_prec |
1261                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1262                                 planea_prec | planea_dl);
1263         }
1264
1265         /* For plane B, Cursor B */
1266         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1267                                       &cursor_prec_mult, &cursorb_dl)) {
1268                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1269                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1270                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1272
1273                 I915_WRITE(VLV_DDL2, cursorb_prec |
1274                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1275                                 planeb_prec | planeb_dl);
1276         }
1277 }
1278
1279 #define single_plane_enabled(mask) is_power_of_2(mask)
1280
1281 static void valleyview_update_wm(struct drm_device *dev)
1282 {
1283         static const int sr_latency_ns = 12000;
1284         struct drm_i915_private *dev_priv = dev->dev_private;
1285         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1286         int plane_sr, cursor_sr;
1287         unsigned int enabled = 0;
1288
1289         vlv_update_drain_latency(dev);
1290
1291         if (g4x_compute_wm0(dev, 0,
1292                             &valleyview_wm_info, latency_ns,
1293                             &valleyview_cursor_wm_info, latency_ns,
1294                             &planea_wm, &cursora_wm))
1295                 enabled |= 1;
1296
1297         if (g4x_compute_wm0(dev, 1,
1298                             &valleyview_wm_info, latency_ns,
1299                             &valleyview_cursor_wm_info, latency_ns,
1300                             &planeb_wm, &cursorb_wm))
1301                 enabled |= 2;
1302
1303         plane_sr = cursor_sr = 0;
1304         if (single_plane_enabled(enabled) &&
1305             g4x_compute_srwm(dev, ffs(enabled) - 1,
1306                              sr_latency_ns,
1307                              &valleyview_wm_info,
1308                              &valleyview_cursor_wm_info,
1309                              &plane_sr, &cursor_sr))
1310                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1311         else
1312                 I915_WRITE(FW_BLC_SELF_VLV,
1313                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1314
1315         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1316                       planea_wm, cursora_wm,
1317                       planeb_wm, cursorb_wm,
1318                       plane_sr, cursor_sr);
1319
1320         I915_WRITE(DSPFW1,
1321                    (plane_sr << DSPFW_SR_SHIFT) |
1322                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1323                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1324                    planea_wm);
1325         I915_WRITE(DSPFW2,
1326                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1327                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1328         I915_WRITE(DSPFW3,
1329                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
1330 }
1331
1332 static void g4x_update_wm(struct drm_device *dev)
1333 {
1334         static const int sr_latency_ns = 12000;
1335         struct drm_i915_private *dev_priv = dev->dev_private;
1336         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1337         int plane_sr, cursor_sr;
1338         unsigned int enabled = 0;
1339
1340         if (g4x_compute_wm0(dev, 0,
1341                             &g4x_wm_info, latency_ns,
1342                             &g4x_cursor_wm_info, latency_ns,
1343                             &planea_wm, &cursora_wm))
1344                 enabled |= 1;
1345
1346         if (g4x_compute_wm0(dev, 1,
1347                             &g4x_wm_info, latency_ns,
1348                             &g4x_cursor_wm_info, latency_ns,
1349                             &planeb_wm, &cursorb_wm))
1350                 enabled |= 2;
1351
1352         plane_sr = cursor_sr = 0;
1353         if (single_plane_enabled(enabled) &&
1354             g4x_compute_srwm(dev, ffs(enabled) - 1,
1355                              sr_latency_ns,
1356                              &g4x_wm_info,
1357                              &g4x_cursor_wm_info,
1358                              &plane_sr, &cursor_sr))
1359                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1360         else
1361                 I915_WRITE(FW_BLC_SELF,
1362                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1363
1364         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1365                       planea_wm, cursora_wm,
1366                       planeb_wm, cursorb_wm,
1367                       plane_sr, cursor_sr);
1368
1369         I915_WRITE(DSPFW1,
1370                    (plane_sr << DSPFW_SR_SHIFT) |
1371                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1372                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1373                    planea_wm);
1374         I915_WRITE(DSPFW2,
1375                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1376                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1377         /* HPLL off in SR has some issues on G4x... disable it */
1378         I915_WRITE(DSPFW3,
1379                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
1380                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1381 }
1382
1383 static void i965_update_wm(struct drm_device *dev)
1384 {
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         struct drm_crtc *crtc;
1387         int srwm = 1;
1388         int cursor_sr = 16;
1389
1390         /* Calc sr entries for one plane configs */
1391         crtc = single_enabled_crtc(dev);
1392         if (crtc) {
1393                 /* self-refresh has much higher latency */
1394                 static const int sr_latency_ns = 12000;
1395                 int clock = crtc->mode.clock;
1396                 int htotal = crtc->mode.htotal;
1397                 int hdisplay = crtc->mode.hdisplay;
1398                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1399                 unsigned long line_time_us;
1400                 int entries;
1401
1402                 line_time_us = ((htotal * 1000) / clock);
1403
1404                 /* Use ns/us then divide to preserve precision */
1405                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1406                         pixel_size * hdisplay;
1407                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1408                 srwm = I965_FIFO_SIZE - entries;
1409                 if (srwm < 0)
1410                         srwm = 1;
1411                 srwm &= 0x1ff;
1412                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1413                               entries, srwm);
1414
1415                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1416                         pixel_size * 64;
1417                 entries = DIV_ROUND_UP(entries,
1418                                           i965_cursor_wm_info.cacheline_size);
1419                 cursor_sr = i965_cursor_wm_info.fifo_size -
1420                         (entries + i965_cursor_wm_info.guard_size);
1421
1422                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1423                         cursor_sr = i965_cursor_wm_info.max_wm;
1424
1425                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1426                               "cursor %d\n", srwm, cursor_sr);
1427
1428                 if (IS_CRESTLINE(dev))
1429                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1430         } else {
1431                 /* Turn off self refresh if both pipes are enabled */
1432                 if (IS_CRESTLINE(dev))
1433                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1434                                    & ~FW_BLC_SELF_EN);
1435         }
1436
1437         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1438                       srwm);
1439
1440         /* 965 has limitations... */
1441         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1442                    (8 << 16) | (8 << 8) | (8 << 0));
1443         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1444         /* update cursor SR watermark */
1445         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1446 }
1447
1448 static void i9xx_update_wm(struct drm_device *dev)
1449 {
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         const struct intel_watermark_params *wm_info;
1452         uint32_t fwater_lo;
1453         uint32_t fwater_hi;
1454         int cwm, srwm = 1;
1455         int fifo_size;
1456         int planea_wm, planeb_wm;
1457         struct drm_crtc *crtc, *enabled = NULL;
1458
1459         if (IS_I945GM(dev))
1460                 wm_info = &i945_wm_info;
1461         else if (!IS_GEN2(dev))
1462                 wm_info = &i915_wm_info;
1463         else
1464                 wm_info = &i855_wm_info;
1465
1466         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1467         crtc = intel_get_crtc_for_plane(dev, 0);
1468         if (crtc->enabled && crtc->fb) {
1469                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1470                                                wm_info, fifo_size,
1471                                                crtc->fb->bits_per_pixel / 8,
1472                                                latency_ns);
1473                 enabled = crtc;
1474         } else
1475                 planea_wm = fifo_size - wm_info->guard_size;
1476
1477         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1478         crtc = intel_get_crtc_for_plane(dev, 1);
1479         if (crtc->enabled && crtc->fb) {
1480                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1481                                                wm_info, fifo_size,
1482                                                crtc->fb->bits_per_pixel / 8,
1483                                                latency_ns);
1484                 if (enabled == NULL)
1485                         enabled = crtc;
1486                 else
1487                         enabled = NULL;
1488         } else
1489                 planeb_wm = fifo_size - wm_info->guard_size;
1490
1491         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1492
1493         /*
1494          * Overlay gets an aggressive default since video jitter is bad.
1495          */
1496         cwm = 2;
1497
1498         /* Play safe and disable self-refresh before adjusting watermarks. */
1499         if (IS_I945G(dev) || IS_I945GM(dev))
1500                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1501         else if (IS_I915GM(dev))
1502                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1503
1504         /* Calc sr entries for one plane configs */
1505         if (HAS_FW_BLC(dev) && enabled) {
1506                 /* self-refresh has much higher latency */
1507                 static const int sr_latency_ns = 6000;
1508                 int clock = enabled->mode.clock;
1509                 int htotal = enabled->mode.htotal;
1510                 int hdisplay = enabled->mode.hdisplay;
1511                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1512                 unsigned long line_time_us;
1513                 int entries;
1514
1515                 line_time_us = (htotal * 1000) / clock;
1516
1517                 /* Use ns/us then divide to preserve precision */
1518                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1519                         pixel_size * hdisplay;
1520                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1521                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1522                 srwm = wm_info->fifo_size - entries;
1523                 if (srwm < 0)
1524                         srwm = 1;
1525
1526                 if (IS_I945G(dev) || IS_I945GM(dev))
1527                         I915_WRITE(FW_BLC_SELF,
1528                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1529                 else if (IS_I915GM(dev))
1530                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1531         }
1532
1533         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1534                       planea_wm, planeb_wm, cwm, srwm);
1535
1536         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1537         fwater_hi = (cwm & 0x1f);
1538
1539         /* Set request length to 8 cachelines per fetch */
1540         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1541         fwater_hi = fwater_hi | (1 << 8);
1542
1543         I915_WRITE(FW_BLC, fwater_lo);
1544         I915_WRITE(FW_BLC2, fwater_hi);
1545
1546         if (HAS_FW_BLC(dev)) {
1547                 if (enabled) {
1548                         if (IS_I945G(dev) || IS_I945GM(dev))
1549                                 I915_WRITE(FW_BLC_SELF,
1550                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1551                         else if (IS_I915GM(dev))
1552                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1553                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1554                 } else
1555                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1556         }
1557 }
1558
1559 static void i830_update_wm(struct drm_device *dev)
1560 {
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         struct drm_crtc *crtc;
1563         uint32_t fwater_lo;
1564         int planea_wm;
1565
1566         crtc = single_enabled_crtc(dev);
1567         if (crtc == NULL)
1568                 return;
1569
1570         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1571                                        dev_priv->display.get_fifo_size(dev, 0),
1572                                        crtc->fb->bits_per_pixel / 8,
1573                                        latency_ns);
1574         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1575         fwater_lo |= (3<<8) | planea_wm;
1576
1577         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1578
1579         I915_WRITE(FW_BLC, fwater_lo);
1580 }
1581
1582 #define ILK_LP0_PLANE_LATENCY           700
1583 #define ILK_LP0_CURSOR_LATENCY          1300
1584
1585 /*
1586  * Check the wm result.
1587  *
1588  * If any calculated watermark values is larger than the maximum value that
1589  * can be programmed into the associated watermark register, that watermark
1590  * must be disabled.
1591  */
1592 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1593                                 int fbc_wm, int display_wm, int cursor_wm,
1594                                 const struct intel_watermark_params *display,
1595                                 const struct intel_watermark_params *cursor)
1596 {
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598
1599         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1600                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1601
1602         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1603                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1604                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1605
1606                 /* fbc has it's own way to disable FBC WM */
1607                 I915_WRITE(DISP_ARB_CTL,
1608                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1609                 return false;
1610         }
1611
1612         if (display_wm > display->max_wm) {
1613                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1614                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1615                 return false;
1616         }
1617
1618         if (cursor_wm > cursor->max_wm) {
1619                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1620                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1621                 return false;
1622         }
1623
1624         if (!(fbc_wm || display_wm || cursor_wm)) {
1625                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1626                 return false;
1627         }
1628
1629         return true;
1630 }
1631
1632 /*
1633  * Compute watermark values of WM[1-3],
1634  */
1635 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1636                                   int latency_ns,
1637                                   const struct intel_watermark_params *display,
1638                                   const struct intel_watermark_params *cursor,
1639                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1640 {
1641         struct drm_crtc *crtc;
1642         unsigned long line_time_us;
1643         int hdisplay, htotal, pixel_size, clock;
1644         int line_count, line_size;
1645         int small, large;
1646         int entries;
1647
1648         if (!latency_ns) {
1649                 *fbc_wm = *display_wm = *cursor_wm = 0;
1650                 return false;
1651         }
1652
1653         crtc = intel_get_crtc_for_plane(dev, plane);
1654         hdisplay = crtc->mode.hdisplay;
1655         htotal = crtc->mode.htotal;
1656         clock = crtc->mode.clock;
1657         pixel_size = crtc->fb->bits_per_pixel / 8;
1658
1659         line_time_us = (htotal * 1000) / clock;
1660         line_count = (latency_ns / line_time_us + 1000) / 1000;
1661         line_size = hdisplay * pixel_size;
1662
1663         /* Use the minimum of the small and large buffer method for primary */
1664         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1665         large = line_count * line_size;
1666
1667         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1668         *display_wm = entries + display->guard_size;
1669
1670         /*
1671          * Spec says:
1672          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1673          */
1674         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1675
1676         /* calculate the self-refresh watermark for display cursor */
1677         entries = line_count * pixel_size * 64;
1678         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1679         *cursor_wm = entries + cursor->guard_size;
1680
1681         return ironlake_check_srwm(dev, level,
1682                                    *fbc_wm, *display_wm, *cursor_wm,
1683                                    display, cursor);
1684 }
1685
1686 static void ironlake_update_wm(struct drm_device *dev)
1687 {
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         int fbc_wm, plane_wm, cursor_wm;
1690         unsigned int enabled;
1691
1692         enabled = 0;
1693         if (g4x_compute_wm0(dev, 0,
1694                             &ironlake_display_wm_info,
1695                             ILK_LP0_PLANE_LATENCY,
1696                             &ironlake_cursor_wm_info,
1697                             ILK_LP0_CURSOR_LATENCY,
1698                             &plane_wm, &cursor_wm)) {
1699                 I915_WRITE(WM0_PIPEA_ILK,
1700                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1701                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1702                               " plane %d, " "cursor: %d\n",
1703                               plane_wm, cursor_wm);
1704                 enabled |= 1;
1705         }
1706
1707         if (g4x_compute_wm0(dev, 1,
1708                             &ironlake_display_wm_info,
1709                             ILK_LP0_PLANE_LATENCY,
1710                             &ironlake_cursor_wm_info,
1711                             ILK_LP0_CURSOR_LATENCY,
1712                             &plane_wm, &cursor_wm)) {
1713                 I915_WRITE(WM0_PIPEB_ILK,
1714                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1715                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1716                               " plane %d, cursor: %d\n",
1717                               plane_wm, cursor_wm);
1718                 enabled |= 2;
1719         }
1720
1721         /*
1722          * Calculate and update the self-refresh watermark only when one
1723          * display plane is used.
1724          */
1725         I915_WRITE(WM3_LP_ILK, 0);
1726         I915_WRITE(WM2_LP_ILK, 0);
1727         I915_WRITE(WM1_LP_ILK, 0);
1728
1729         if (!single_plane_enabled(enabled))
1730                 return;
1731         enabled = ffs(enabled) - 1;
1732
1733         /* WM1 */
1734         if (!ironlake_compute_srwm(dev, 1, enabled,
1735                                    ILK_READ_WM1_LATENCY() * 500,
1736                                    &ironlake_display_srwm_info,
1737                                    &ironlake_cursor_srwm_info,
1738                                    &fbc_wm, &plane_wm, &cursor_wm))
1739                 return;
1740
1741         I915_WRITE(WM1_LP_ILK,
1742                    WM1_LP_SR_EN |
1743                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1744                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1745                    (plane_wm << WM1_LP_SR_SHIFT) |
1746                    cursor_wm);
1747
1748         /* WM2 */
1749         if (!ironlake_compute_srwm(dev, 2, enabled,
1750                                    ILK_READ_WM2_LATENCY() * 500,
1751                                    &ironlake_display_srwm_info,
1752                                    &ironlake_cursor_srwm_info,
1753                                    &fbc_wm, &plane_wm, &cursor_wm))
1754                 return;
1755
1756         I915_WRITE(WM2_LP_ILK,
1757                    WM2_LP_EN |
1758                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1759                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1760                    (plane_wm << WM1_LP_SR_SHIFT) |
1761                    cursor_wm);
1762
1763         /*
1764          * WM3 is unsupported on ILK, probably because we don't have latency
1765          * data for that power state
1766          */
1767 }
1768
1769 static void sandybridge_update_wm(struct drm_device *dev)
1770 {
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1773         u32 val;
1774         int fbc_wm, plane_wm, cursor_wm;
1775         unsigned int enabled;
1776
1777         enabled = 0;
1778         if (g4x_compute_wm0(dev, 0,
1779                             &sandybridge_display_wm_info, latency,
1780                             &sandybridge_cursor_wm_info, latency,
1781                             &plane_wm, &cursor_wm)) {
1782                 val = I915_READ(WM0_PIPEA_ILK);
1783                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1784                 I915_WRITE(WM0_PIPEA_ILK, val |
1785                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1786                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1787                               " plane %d, " "cursor: %d\n",
1788                               plane_wm, cursor_wm);
1789                 enabled |= 1;
1790         }
1791
1792         if (g4x_compute_wm0(dev, 1,
1793                             &sandybridge_display_wm_info, latency,
1794                             &sandybridge_cursor_wm_info, latency,
1795                             &plane_wm, &cursor_wm)) {
1796                 val = I915_READ(WM0_PIPEB_ILK);
1797                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1798                 I915_WRITE(WM0_PIPEB_ILK, val |
1799                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1800                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1801                               " plane %d, cursor: %d\n",
1802                               plane_wm, cursor_wm);
1803                 enabled |= 2;
1804         }
1805
1806         if ((dev_priv->num_pipe == 3) &&
1807             g4x_compute_wm0(dev, 2,
1808                             &sandybridge_display_wm_info, latency,
1809                             &sandybridge_cursor_wm_info, latency,
1810                             &plane_wm, &cursor_wm)) {
1811                 val = I915_READ(WM0_PIPEC_IVB);
1812                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1813                 I915_WRITE(WM0_PIPEC_IVB, val |
1814                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1815                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1816                               " plane %d, cursor: %d\n",
1817                               plane_wm, cursor_wm);
1818                 enabled |= 3;
1819         }
1820
1821         /*
1822          * Calculate and update the self-refresh watermark only when one
1823          * display plane is used.
1824          *
1825          * SNB support 3 levels of watermark.
1826          *
1827          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1828          * and disabled in the descending order
1829          *
1830          */
1831         I915_WRITE(WM3_LP_ILK, 0);
1832         I915_WRITE(WM2_LP_ILK, 0);
1833         I915_WRITE(WM1_LP_ILK, 0);
1834
1835         if (!single_plane_enabled(enabled) ||
1836             dev_priv->sprite_scaling_enabled)
1837                 return;
1838         enabled = ffs(enabled) - 1;
1839
1840         /* WM1 */
1841         if (!ironlake_compute_srwm(dev, 1, enabled,
1842                                    SNB_READ_WM1_LATENCY() * 500,
1843                                    &sandybridge_display_srwm_info,
1844                                    &sandybridge_cursor_srwm_info,
1845                                    &fbc_wm, &plane_wm, &cursor_wm))
1846                 return;
1847
1848         I915_WRITE(WM1_LP_ILK,
1849                    WM1_LP_SR_EN |
1850                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1851                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1852                    (plane_wm << WM1_LP_SR_SHIFT) |
1853                    cursor_wm);
1854
1855         /* WM2 */
1856         if (!ironlake_compute_srwm(dev, 2, enabled,
1857                                    SNB_READ_WM2_LATENCY() * 500,
1858                                    &sandybridge_display_srwm_info,
1859                                    &sandybridge_cursor_srwm_info,
1860                                    &fbc_wm, &plane_wm, &cursor_wm))
1861                 return;
1862
1863         I915_WRITE(WM2_LP_ILK,
1864                    WM2_LP_EN |
1865                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1866                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1867                    (plane_wm << WM1_LP_SR_SHIFT) |
1868                    cursor_wm);
1869
1870         /* WM3 */
1871         if (!ironlake_compute_srwm(dev, 3, enabled,
1872                                    SNB_READ_WM3_LATENCY() * 500,
1873                                    &sandybridge_display_srwm_info,
1874                                    &sandybridge_cursor_srwm_info,
1875                                    &fbc_wm, &plane_wm, &cursor_wm))
1876                 return;
1877
1878         I915_WRITE(WM3_LP_ILK,
1879                    WM3_LP_EN |
1880                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1881                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1882                    (plane_wm << WM1_LP_SR_SHIFT) |
1883                    cursor_wm);
1884 }
1885
1886 static bool
1887 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1888                               uint32_t sprite_width, int pixel_size,
1889                               const struct intel_watermark_params *display,
1890                               int display_latency_ns, int *sprite_wm)
1891 {
1892         struct drm_crtc *crtc;
1893         int clock;
1894         int entries, tlb_miss;
1895
1896         crtc = intel_get_crtc_for_plane(dev, plane);
1897         if (crtc->fb == NULL || !crtc->enabled) {
1898                 *sprite_wm = display->guard_size;
1899                 return false;
1900         }
1901
1902         clock = crtc->mode.clock;
1903
1904         /* Use the small buffer method to calculate the sprite watermark */
1905         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1906         tlb_miss = display->fifo_size*display->cacheline_size -
1907                 sprite_width * 8;
1908         if (tlb_miss > 0)
1909                 entries += tlb_miss;
1910         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1911         *sprite_wm = entries + display->guard_size;
1912         if (*sprite_wm > (int)display->max_wm)
1913                 *sprite_wm = display->max_wm;
1914
1915         return true;
1916 }
1917
1918 static bool
1919 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1920                                 uint32_t sprite_width, int pixel_size,
1921                                 const struct intel_watermark_params *display,
1922                                 int latency_ns, int *sprite_wm)
1923 {
1924         struct drm_crtc *crtc;
1925         unsigned long line_time_us;
1926         int clock;
1927         int line_count, line_size;
1928         int small, large;
1929         int entries;
1930
1931         if (!latency_ns) {
1932                 *sprite_wm = 0;
1933                 return false;
1934         }
1935
1936         crtc = intel_get_crtc_for_plane(dev, plane);
1937         clock = crtc->mode.clock;
1938         if (!clock) {
1939                 *sprite_wm = 0;
1940                 return false;
1941         }
1942
1943         line_time_us = (sprite_width * 1000) / clock;
1944         if (!line_time_us) {
1945                 *sprite_wm = 0;
1946                 return false;
1947         }
1948
1949         line_count = (latency_ns / line_time_us + 1000) / 1000;
1950         line_size = sprite_width * pixel_size;
1951
1952         /* Use the minimum of the small and large buffer method for primary */
1953         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1954         large = line_count * line_size;
1955
1956         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1957         *sprite_wm = entries + display->guard_size;
1958
1959         return *sprite_wm > 0x3ff ? false : true;
1960 }
1961
1962 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
1963                                          uint32_t sprite_width, int pixel_size)
1964 {
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1967         u32 val;
1968         int sprite_wm, reg;
1969         int ret;
1970
1971         switch (pipe) {
1972         case 0:
1973                 reg = WM0_PIPEA_ILK;
1974                 break;
1975         case 1:
1976                 reg = WM0_PIPEB_ILK;
1977                 break;
1978         case 2:
1979                 reg = WM0_PIPEC_IVB;
1980                 break;
1981         default:
1982                 return; /* bad pipe */
1983         }
1984
1985         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
1986                                             &sandybridge_display_wm_info,
1987                                             latency, &sprite_wm);
1988         if (!ret) {
1989                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
1990                               pipe);
1991                 return;
1992         }
1993
1994         val = I915_READ(reg);
1995         val &= ~WM0_PIPE_SPRITE_MASK;
1996         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
1997         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
1998
1999
2000         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2001                                               pixel_size,
2002                                               &sandybridge_display_srwm_info,
2003                                               SNB_READ_WM1_LATENCY() * 500,
2004                                               &sprite_wm);
2005         if (!ret) {
2006                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2007                               pipe);
2008                 return;
2009         }
2010         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2011
2012         /* Only IVB has two more LP watermarks for sprite */
2013         if (!IS_IVYBRIDGE(dev))
2014                 return;
2015
2016         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2017                                               pixel_size,
2018                                               &sandybridge_display_srwm_info,
2019                                               SNB_READ_WM2_LATENCY() * 500,
2020                                               &sprite_wm);
2021         if (!ret) {
2022                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2023                               pipe);
2024                 return;
2025         }
2026         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2027
2028         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2029                                               pixel_size,
2030                                               &sandybridge_display_srwm_info,
2031                                               SNB_READ_WM3_LATENCY() * 500,
2032                                               &sprite_wm);
2033         if (!ret) {
2034                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2035                               pipe);
2036                 return;
2037         }
2038         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2039 }
2040
2041 /**
2042  * intel_update_watermarks - update FIFO watermark values based on current modes
2043  *
2044  * Calculate watermark values for the various WM regs based on current mode
2045  * and plane configuration.
2046  *
2047  * There are several cases to deal with here:
2048  *   - normal (i.e. non-self-refresh)
2049  *   - self-refresh (SR) mode
2050  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2051  *   - lines are small relative to FIFO size (buffer can hold more than 2
2052  *     lines), so need to account for TLB latency
2053  *
2054  *   The normal calculation is:
2055  *     watermark = dotclock * bytes per pixel * latency
2056  *   where latency is platform & configuration dependent (we assume pessimal
2057  *   values here).
2058  *
2059  *   The SR calculation is:
2060  *     watermark = (trunc(latency/line time)+1) * surface width *
2061  *       bytes per pixel
2062  *   where
2063  *     line time = htotal / dotclock
2064  *     surface width = hdisplay for normal plane and 64 for cursor
2065  *   and latency is assumed to be high, as above.
2066  *
2067  * The final value programmed to the register should always be rounded up,
2068  * and include an extra 2 entries to account for clock crossings.
2069  *
2070  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2071  * to set the non-SR watermarks to 8.
2072  */
2073 void intel_update_watermarks(struct drm_device *dev)
2074 {
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076
2077         if (dev_priv->display.update_wm)
2078                 dev_priv->display.update_wm(dev);
2079 }
2080
2081 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2082                                     uint32_t sprite_width, int pixel_size)
2083 {
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085
2086         if (dev_priv->display.update_sprite_wm)
2087                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2088                                                    pixel_size);
2089 }
2090
2091 static struct drm_i915_gem_object *
2092 intel_alloc_context_page(struct drm_device *dev)
2093 {
2094         struct drm_i915_gem_object *ctx;
2095         int ret;
2096
2097         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2098
2099         ctx = i915_gem_alloc_object(dev, 4096);
2100         if (!ctx) {
2101                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2102                 return NULL;
2103         }
2104
2105         ret = i915_gem_object_pin(ctx, 4096, true);
2106         if (ret) {
2107                 DRM_ERROR("failed to pin power context: %d\n", ret);
2108                 goto err_unref;
2109         }
2110
2111         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2112         if (ret) {
2113                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2114                 goto err_unpin;
2115         }
2116
2117         return ctx;
2118
2119 err_unpin:
2120         i915_gem_object_unpin(ctx);
2121 err_unref:
2122         drm_gem_object_unreference(&ctx->base);
2123         mutex_unlock(&dev->struct_mutex);
2124         return NULL;
2125 }
2126
2127 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2128 {
2129         struct drm_i915_private *dev_priv = dev->dev_private;
2130         u16 rgvswctl;
2131
2132         rgvswctl = I915_READ16(MEMSWCTL);
2133         if (rgvswctl & MEMCTL_CMD_STS) {
2134                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2135                 return false; /* still busy with another command */
2136         }
2137
2138         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2139                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2140         I915_WRITE16(MEMSWCTL, rgvswctl);
2141         POSTING_READ16(MEMSWCTL);
2142
2143         rgvswctl |= MEMCTL_CMD_STS;
2144         I915_WRITE16(MEMSWCTL, rgvswctl);
2145
2146         return true;
2147 }
2148
2149 void ironlake_enable_drps(struct drm_device *dev)
2150 {
2151         struct drm_i915_private *dev_priv = dev->dev_private;
2152         u32 rgvmodectl = I915_READ(MEMMODECTL);
2153         u8 fmax, fmin, fstart, vstart;
2154
2155         /* Enable temp reporting */
2156         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2157         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2158
2159         /* 100ms RC evaluation intervals */
2160         I915_WRITE(RCUPEI, 100000);
2161         I915_WRITE(RCDNEI, 100000);
2162
2163         /* Set max/min thresholds to 90ms and 80ms respectively */
2164         I915_WRITE(RCBMAXAVG, 90000);
2165         I915_WRITE(RCBMINAVG, 80000);
2166
2167         I915_WRITE(MEMIHYST, 1);
2168
2169         /* Set up min, max, and cur for interrupt handling */
2170         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2171         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2172         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2173                 MEMMODE_FSTART_SHIFT;
2174
2175         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2176                 PXVFREQ_PX_SHIFT;
2177
2178         dev_priv->fmax = fmax; /* IPS callback will increase this */
2179         dev_priv->fstart = fstart;
2180
2181         dev_priv->max_delay = fstart;
2182         dev_priv->min_delay = fmin;
2183         dev_priv->cur_delay = fstart;
2184
2185         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2186                          fmax, fmin, fstart);
2187
2188         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2189
2190         /*
2191          * Interrupts will be enabled in ironlake_irq_postinstall
2192          */
2193
2194         I915_WRITE(VIDSTART, vstart);
2195         POSTING_READ(VIDSTART);
2196
2197         rgvmodectl |= MEMMODE_SWMODE_EN;
2198         I915_WRITE(MEMMODECTL, rgvmodectl);
2199
2200         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2201                 DRM_ERROR("stuck trying to change perf mode\n");
2202         msleep(1);
2203
2204         ironlake_set_drps(dev, fstart);
2205
2206         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2207                 I915_READ(0x112e0);
2208         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
2209         dev_priv->last_count2 = I915_READ(0x112f4);
2210         getrawmonotonic(&dev_priv->last_time2);
2211 }
2212
2213 void ironlake_disable_drps(struct drm_device *dev)
2214 {
2215         struct drm_i915_private *dev_priv = dev->dev_private;
2216         u16 rgvswctl = I915_READ16(MEMSWCTL);
2217
2218         /* Ack interrupts, disable EFC interrupt */
2219         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2220         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2221         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2222         I915_WRITE(DEIIR, DE_PCU_EVENT);
2223         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2224
2225         /* Go back to the starting frequency */
2226         ironlake_set_drps(dev, dev_priv->fstart);
2227         msleep(1);
2228         rgvswctl |= MEMCTL_CMD_STS;
2229         I915_WRITE(MEMSWCTL, rgvswctl);
2230         msleep(1);
2231
2232 }
2233
2234 void gen6_set_rps(struct drm_device *dev, u8 val)
2235 {
2236         struct drm_i915_private *dev_priv = dev->dev_private;
2237         u32 swreq;
2238
2239         swreq = (val & 0x3ff) << 25;
2240         I915_WRITE(GEN6_RPNSWREQ, swreq);
2241 }
2242
2243 void gen6_disable_rps(struct drm_device *dev)
2244 {
2245         struct drm_i915_private *dev_priv = dev->dev_private;
2246
2247         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2248         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2249         I915_WRITE(GEN6_PMIER, 0);
2250         /* Complete PM interrupt masking here doesn't race with the rps work
2251          * item again unmasking PM interrupts because that is using a different
2252          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2253          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2254
2255         spin_lock_irq(&dev_priv->rps_lock);
2256         dev_priv->pm_iir = 0;
2257         spin_unlock_irq(&dev_priv->rps_lock);
2258
2259         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2260 }
2261
2262 int intel_enable_rc6(const struct drm_device *dev)
2263 {
2264         /*
2265          * Respect the kernel parameter if it is set
2266          */
2267         if (i915_enable_rc6 >= 0)
2268                 return i915_enable_rc6;
2269
2270         /*
2271          * Disable RC6 on Ironlake
2272          */
2273         if (INTEL_INFO(dev)->gen == 5)
2274                 return 0;
2275
2276         /* Sorry Haswell, no RC6 for you for now. */
2277         if (IS_HASWELL(dev))
2278                 return 0;
2279
2280         /*
2281          * Disable rc6 on Sandybridge
2282          */
2283         if (INTEL_INFO(dev)->gen == 6) {
2284                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2285                 return INTEL_RC6_ENABLE;
2286         }
2287         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2288         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2289 }
2290
2291 void gen6_enable_rps(struct drm_i915_private *dev_priv)
2292 {
2293         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2294         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2295         u32 pcu_mbox, rc6_mask = 0;
2296         u32 gtfifodbg;
2297         int cur_freq, min_freq, max_freq;
2298         int rc6_mode;
2299         int i;
2300
2301         /* Here begins a magic sequence of register writes to enable
2302          * auto-downclocking.
2303          *
2304          * Perhaps there might be some value in exposing these to
2305          * userspace...
2306          */
2307         I915_WRITE(GEN6_RC_STATE, 0);
2308         mutex_lock(&dev_priv->dev->struct_mutex);
2309
2310         /* Clear the DBG now so we don't confuse earlier errors */
2311         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2312                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2313                 I915_WRITE(GTFIFODBG, gtfifodbg);
2314         }
2315
2316         gen6_gt_force_wake_get(dev_priv);
2317
2318         /* disable the counters and set deterministic thresholds */
2319         I915_WRITE(GEN6_RC_CONTROL, 0);
2320
2321         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2322         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2323         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2324         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2325         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2326
2327         for (i = 0; i < I915_NUM_RINGS; i++)
2328                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
2329
2330         I915_WRITE(GEN6_RC_SLEEP, 0);
2331         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2332         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2333         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2334         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2335
2336         rc6_mode = intel_enable_rc6(dev_priv->dev);
2337         if (rc6_mode & INTEL_RC6_ENABLE)
2338                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2339
2340         if (rc6_mode & INTEL_RC6p_ENABLE)
2341                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2342
2343         if (rc6_mode & INTEL_RC6pp_ENABLE)
2344                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2345
2346         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2347                         (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
2348                         (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
2349                         (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
2350
2351         I915_WRITE(GEN6_RC_CONTROL,
2352                    rc6_mask |
2353                    GEN6_RC_CTL_EI_MODE(1) |
2354                    GEN6_RC_CTL_HW_ENABLE);
2355
2356         I915_WRITE(GEN6_RPNSWREQ,
2357                    GEN6_FREQUENCY(10) |
2358                    GEN6_OFFSET(0) |
2359                    GEN6_AGGRESSIVE_TURBO);
2360         I915_WRITE(GEN6_RC_VIDEO_FREQ,
2361                    GEN6_FREQUENCY(12));
2362
2363         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2364         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2365                    18 << 24 |
2366                    6 << 16);
2367         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
2368         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
2369         I915_WRITE(GEN6_RP_UP_EI, 100000);
2370         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
2371         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2372         I915_WRITE(GEN6_RP_CONTROL,
2373                    GEN6_RP_MEDIA_TURBO |
2374                    GEN6_RP_MEDIA_HW_MODE |
2375                    GEN6_RP_MEDIA_IS_GFX |
2376                    GEN6_RP_ENABLE |
2377                    GEN6_RP_UP_BUSY_AVG |
2378                    GEN6_RP_DOWN_IDLE_CONT);
2379
2380         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2381                      500))
2382                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2383
2384         I915_WRITE(GEN6_PCODE_DATA, 0);
2385         I915_WRITE(GEN6_PCODE_MAILBOX,
2386                    GEN6_PCODE_READY |
2387                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
2388         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2389                      500))
2390                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2391
2392         min_freq = (rp_state_cap & 0xff0000) >> 16;
2393         max_freq = rp_state_cap & 0xff;
2394         cur_freq = (gt_perf_status & 0xff00) >> 8;
2395
2396         /* Check for overclock support */
2397         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2398                      500))
2399                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2400         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
2401         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
2402         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2403                      500))
2404                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2405         if (pcu_mbox & (1<<31)) { /* OC supported */
2406                 max_freq = pcu_mbox & 0xff;
2407                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2408         }
2409
2410         /* In units of 100MHz */
2411         dev_priv->max_delay = max_freq;
2412         dev_priv->min_delay = min_freq;
2413         dev_priv->cur_delay = cur_freq;
2414
2415         /* requires MSI enabled */
2416         I915_WRITE(GEN6_PMIER,
2417                    GEN6_PM_MBOX_EVENT |
2418                    GEN6_PM_THERMAL_EVENT |
2419                    GEN6_PM_RP_DOWN_TIMEOUT |
2420                    GEN6_PM_RP_UP_THRESHOLD |
2421                    GEN6_PM_RP_DOWN_THRESHOLD |
2422                    GEN6_PM_RP_UP_EI_EXPIRED |
2423                    GEN6_PM_RP_DOWN_EI_EXPIRED);
2424         spin_lock_irq(&dev_priv->rps_lock);
2425         WARN_ON(dev_priv->pm_iir != 0);
2426         I915_WRITE(GEN6_PMIMR, 0);
2427         spin_unlock_irq(&dev_priv->rps_lock);
2428         /* enable all PM interrupts */
2429         I915_WRITE(GEN6_PMINTRMSK, 0);
2430
2431         gen6_gt_force_wake_put(dev_priv);
2432         mutex_unlock(&dev_priv->dev->struct_mutex);
2433 }
2434
2435 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2436 {
2437         int min_freq = 15;
2438         int gpu_freq, ia_freq, max_ia_freq;
2439         int scaling_factor = 180;
2440
2441         max_ia_freq = cpufreq_quick_get_max(0);
2442         /*
2443          * Default to measured freq if none found, PCU will ensure we don't go
2444          * over
2445          */
2446         if (!max_ia_freq)
2447                 max_ia_freq = tsc_khz;
2448
2449         /* Convert from kHz to MHz */
2450         max_ia_freq /= 1000;
2451
2452         mutex_lock(&dev_priv->dev->struct_mutex);
2453
2454         /*
2455          * For each potential GPU frequency, load a ring frequency we'd like
2456          * to use for memory access.  We do this by specifying the IA frequency
2457          * the PCU should use as a reference to determine the ring frequency.
2458          */
2459         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
2460              gpu_freq--) {
2461                 int diff = dev_priv->max_delay - gpu_freq;
2462
2463                 /*
2464                  * For GPU frequencies less than 750MHz, just use the lowest
2465                  * ring freq.
2466                  */
2467                 if (gpu_freq < min_freq)
2468                         ia_freq = 800;
2469                 else
2470                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2471                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2472
2473                 I915_WRITE(GEN6_PCODE_DATA,
2474                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
2475                            gpu_freq);
2476                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
2477                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
2478                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
2479                               GEN6_PCODE_READY) == 0, 10)) {
2480                         DRM_ERROR("pcode write of freq table timed out\n");
2481                         continue;
2482                 }
2483         }
2484
2485         mutex_unlock(&dev_priv->dev->struct_mutex);
2486 }
2487
2488 static void ironlake_teardown_rc6(struct drm_device *dev)
2489 {
2490         struct drm_i915_private *dev_priv = dev->dev_private;
2491
2492         if (dev_priv->renderctx) {
2493                 i915_gem_object_unpin(dev_priv->renderctx);
2494                 drm_gem_object_unreference(&dev_priv->renderctx->base);
2495                 dev_priv->renderctx = NULL;
2496         }
2497
2498         if (dev_priv->pwrctx) {
2499                 i915_gem_object_unpin(dev_priv->pwrctx);
2500                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
2501                 dev_priv->pwrctx = NULL;
2502         }
2503 }
2504
2505 void ironlake_disable_rc6(struct drm_device *dev)
2506 {
2507         struct drm_i915_private *dev_priv = dev->dev_private;
2508
2509         if (I915_READ(PWRCTXA)) {
2510                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2511                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2512                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2513                          50);
2514
2515                 I915_WRITE(PWRCTXA, 0);
2516                 POSTING_READ(PWRCTXA);
2517
2518                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2519                 POSTING_READ(RSTDBYCTL);
2520         }
2521
2522         ironlake_teardown_rc6(dev);
2523 }
2524
2525 static int ironlake_setup_rc6(struct drm_device *dev)
2526 {
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528
2529         if (dev_priv->renderctx == NULL)
2530                 dev_priv->renderctx = intel_alloc_context_page(dev);
2531         if (!dev_priv->renderctx)
2532                 return -ENOMEM;
2533
2534         if (dev_priv->pwrctx == NULL)
2535                 dev_priv->pwrctx = intel_alloc_context_page(dev);
2536         if (!dev_priv->pwrctx) {
2537                 ironlake_teardown_rc6(dev);
2538                 return -ENOMEM;
2539         }
2540
2541         return 0;
2542 }
2543
2544 void ironlake_enable_rc6(struct drm_device *dev)
2545 {
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2548         int ret;
2549
2550         /* rc6 disabled by default due to repeated reports of hanging during
2551          * boot and resume.
2552          */
2553         if (!intel_enable_rc6(dev))
2554                 return;
2555
2556         mutex_lock(&dev->struct_mutex);
2557         ret = ironlake_setup_rc6(dev);
2558         if (ret) {
2559                 mutex_unlock(&dev->struct_mutex);
2560                 return;
2561         }
2562
2563         /*
2564          * GPU can automatically power down the render unit if given a page
2565          * to save state.
2566          */
2567         ret = intel_ring_begin(ring, 6);
2568         if (ret) {
2569                 ironlake_teardown_rc6(dev);
2570                 mutex_unlock(&dev->struct_mutex);
2571                 return;
2572         }
2573
2574         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2575         intel_ring_emit(ring, MI_SET_CONTEXT);
2576         intel_ring_emit(ring, dev_priv->renderctx->gtt_offset |
2577                         MI_MM_SPACE_GTT |
2578                         MI_SAVE_EXT_STATE_EN |
2579                         MI_RESTORE_EXT_STATE_EN |
2580                         MI_RESTORE_INHIBIT);
2581         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2582         intel_ring_emit(ring, MI_NOOP);
2583         intel_ring_emit(ring, MI_FLUSH);
2584         intel_ring_advance(ring);
2585
2586         /*
2587          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2588          * does an implicit flush, combined with MI_FLUSH above, it should be
2589          * safe to assume that renderctx is valid
2590          */
2591         ret = intel_wait_ring_idle(ring);
2592         if (ret) {
2593                 DRM_ERROR("failed to enable ironlake power power savings\n");
2594                 ironlake_teardown_rc6(dev);
2595                 mutex_unlock(&dev->struct_mutex);
2596                 return;
2597         }
2598
2599         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
2600         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2601         mutex_unlock(&dev->struct_mutex);
2602 }
2603
2604 static unsigned long intel_pxfreq(u32 vidfreq)
2605 {
2606         unsigned long freq;
2607         int div = (vidfreq & 0x3f0000) >> 16;
2608         int post = (vidfreq & 0x3000) >> 12;
2609         int pre = (vidfreq & 0x7);
2610
2611         if (!pre)
2612                 return 0;
2613
2614         freq = ((div * 133333) / ((1<<post) * pre));
2615
2616         return freq;
2617 }
2618
2619 static const struct cparams {
2620         u16 i;
2621         u16 t;
2622         u16 m;
2623         u16 c;
2624 } cparams[] = {
2625         { 1, 1333, 301, 28664 },
2626         { 1, 1066, 294, 24460 },
2627         { 1, 800, 294, 25192 },
2628         { 0, 1333, 276, 27605 },
2629         { 0, 1066, 276, 27605 },
2630         { 0, 800, 231, 23784 },
2631 };
2632
2633 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2634 {
2635         u64 total_count, diff, ret;
2636         u32 count1, count2, count3, m = 0, c = 0;
2637         unsigned long now = jiffies_to_msecs(jiffies), diff1;
2638         int i;
2639
2640         diff1 = now - dev_priv->last_time1;
2641
2642         /* Prevent division-by-zero if we are asking too fast.
2643          * Also, we don't get interesting results if we are polling
2644          * faster than once in 10ms, so just return the saved value
2645          * in such cases.
2646          */
2647         if (diff1 <= 10)
2648                 return dev_priv->chipset_power;
2649
2650         count1 = I915_READ(DMIEC);
2651         count2 = I915_READ(DDREC);
2652         count3 = I915_READ(CSIEC);
2653
2654         total_count = count1 + count2 + count3;
2655
2656         /* FIXME: handle per-counter overflow */
2657         if (total_count < dev_priv->last_count1) {
2658                 diff = ~0UL - dev_priv->last_count1;
2659                 diff += total_count;
2660         } else {
2661                 diff = total_count - dev_priv->last_count1;
2662         }
2663
2664         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2665                 if (cparams[i].i == dev_priv->c_m &&
2666                     cparams[i].t == dev_priv->r_t) {
2667                         m = cparams[i].m;
2668                         c = cparams[i].c;
2669                         break;
2670                 }
2671         }
2672
2673         diff = div_u64(diff, diff1);
2674         ret = ((m * diff) + c);
2675         ret = div_u64(ret, 10);
2676
2677         dev_priv->last_count1 = total_count;
2678         dev_priv->last_time1 = now;
2679
2680         dev_priv->chipset_power = ret;
2681
2682         return ret;
2683 }
2684
2685 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2686 {
2687         unsigned long m, x, b;
2688         u32 tsfs;
2689
2690         tsfs = I915_READ(TSFS);
2691
2692         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2693         x = I915_READ8(TR1);
2694
2695         b = tsfs & TSFS_INTR_MASK;
2696
2697         return ((m * x) / 127) - b;
2698 }
2699
2700 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2701 {
2702         static const struct v_table {
2703                 u16 vd; /* in .1 mil */
2704                 u16 vm; /* in .1 mil */
2705         } v_table[] = {
2706                 { 0, 0, },
2707                 { 375, 0, },
2708                 { 500, 0, },
2709                 { 625, 0, },
2710                 { 750, 0, },
2711                 { 875, 0, },
2712                 { 1000, 0, },
2713                 { 1125, 0, },
2714                 { 4125, 3000, },
2715                 { 4125, 3000, },
2716                 { 4125, 3000, },
2717                 { 4125, 3000, },
2718                 { 4125, 3000, },
2719                 { 4125, 3000, },
2720                 { 4125, 3000, },
2721                 { 4125, 3000, },
2722                 { 4125, 3000, },
2723                 { 4125, 3000, },
2724                 { 4125, 3000, },
2725                 { 4125, 3000, },
2726                 { 4125, 3000, },
2727                 { 4125, 3000, },
2728                 { 4125, 3000, },
2729                 { 4125, 3000, },
2730                 { 4125, 3000, },
2731                 { 4125, 3000, },
2732                 { 4125, 3000, },
2733                 { 4125, 3000, },
2734                 { 4125, 3000, },
2735                 { 4125, 3000, },
2736                 { 4125, 3000, },
2737                 { 4125, 3000, },
2738                 { 4250, 3125, },
2739                 { 4375, 3250, },
2740                 { 4500, 3375, },
2741                 { 4625, 3500, },
2742                 { 4750, 3625, },
2743                 { 4875, 3750, },
2744                 { 5000, 3875, },
2745                 { 5125, 4000, },
2746                 { 5250, 4125, },
2747                 { 5375, 4250, },
2748                 { 5500, 4375, },
2749                 { 5625, 4500, },
2750                 { 5750, 4625, },
2751                 { 5875, 4750, },
2752                 { 6000, 4875, },
2753                 { 6125, 5000, },
2754                 { 6250, 5125, },
2755                 { 6375, 5250, },
2756                 { 6500, 5375, },
2757                 { 6625, 5500, },
2758                 { 6750, 5625, },
2759                 { 6875, 5750, },
2760                 { 7000, 5875, },
2761                 { 7125, 6000, },
2762                 { 7250, 6125, },
2763                 { 7375, 6250, },
2764                 { 7500, 6375, },
2765                 { 7625, 6500, },
2766                 { 7750, 6625, },
2767                 { 7875, 6750, },
2768                 { 8000, 6875, },
2769                 { 8125, 7000, },
2770                 { 8250, 7125, },
2771                 { 8375, 7250, },
2772                 { 8500, 7375, },
2773                 { 8625, 7500, },
2774                 { 8750, 7625, },
2775                 { 8875, 7750, },
2776                 { 9000, 7875, },
2777                 { 9125, 8000, },
2778                 { 9250, 8125, },
2779                 { 9375, 8250, },
2780                 { 9500, 8375, },
2781                 { 9625, 8500, },
2782                 { 9750, 8625, },
2783                 { 9875, 8750, },
2784                 { 10000, 8875, },
2785                 { 10125, 9000, },
2786                 { 10250, 9125, },
2787                 { 10375, 9250, },
2788                 { 10500, 9375, },
2789                 { 10625, 9500, },
2790                 { 10750, 9625, },
2791                 { 10875, 9750, },
2792                 { 11000, 9875, },
2793                 { 11125, 10000, },
2794                 { 11250, 10125, },
2795                 { 11375, 10250, },
2796                 { 11500, 10375, },
2797                 { 11625, 10500, },
2798                 { 11750, 10625, },
2799                 { 11875, 10750, },
2800                 { 12000, 10875, },
2801                 { 12125, 11000, },
2802                 { 12250, 11125, },
2803                 { 12375, 11250, },
2804                 { 12500, 11375, },
2805                 { 12625, 11500, },
2806                 { 12750, 11625, },
2807                 { 12875, 11750, },
2808                 { 13000, 11875, },
2809                 { 13125, 12000, },
2810                 { 13250, 12125, },
2811                 { 13375, 12250, },
2812                 { 13500, 12375, },
2813                 { 13625, 12500, },
2814                 { 13750, 12625, },
2815                 { 13875, 12750, },
2816                 { 14000, 12875, },
2817                 { 14125, 13000, },
2818                 { 14250, 13125, },
2819                 { 14375, 13250, },
2820                 { 14500, 13375, },
2821                 { 14625, 13500, },
2822                 { 14750, 13625, },
2823                 { 14875, 13750, },
2824                 { 15000, 13875, },
2825                 { 15125, 14000, },
2826                 { 15250, 14125, },
2827                 { 15375, 14250, },
2828                 { 15500, 14375, },
2829                 { 15625, 14500, },
2830                 { 15750, 14625, },
2831                 { 15875, 14750, },
2832                 { 16000, 14875, },
2833                 { 16125, 15000, },
2834         };
2835         if (dev_priv->info->is_mobile)
2836                 return v_table[pxvid].vm;
2837         else
2838                 return v_table[pxvid].vd;
2839 }
2840
2841 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
2842 {
2843         struct timespec now, diff1;
2844         u64 diff;
2845         unsigned long diffms;
2846         u32 count;
2847
2848         if (dev_priv->info->gen != 5)
2849                 return;
2850
2851         getrawmonotonic(&now);
2852         diff1 = timespec_sub(now, dev_priv->last_time2);
2853
2854         /* Don't divide by 0 */
2855         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2856         if (!diffms)
2857                 return;
2858
2859         count = I915_READ(GFXEC);
2860
2861         if (count < dev_priv->last_count2) {
2862                 diff = ~0UL - dev_priv->last_count2;
2863                 diff += count;
2864         } else {
2865                 diff = count - dev_priv->last_count2;
2866         }
2867
2868         dev_priv->last_count2 = count;
2869         dev_priv->last_time2 = now;
2870
2871         /* More magic constants... */
2872         diff = diff * 1181;
2873         diff = div_u64(diff, diffms * 10);
2874         dev_priv->gfx_power = diff;
2875 }
2876
2877 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
2878 {
2879         unsigned long t, corr, state1, corr2, state2;
2880         u32 pxvid, ext_v;
2881
2882         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
2883         pxvid = (pxvid >> 24) & 0x7f;
2884         ext_v = pvid_to_extvid(dev_priv, pxvid);
2885
2886         state1 = ext_v;
2887
2888         t = i915_mch_val(dev_priv);
2889
2890         /* Revel in the empirically derived constants */
2891
2892         /* Correction factor in 1/100000 units */
2893         if (t > 80)
2894                 corr = ((t * 2349) + 135940);
2895         else if (t >= 50)
2896                 corr = ((t * 964) + 29317);
2897         else /* < 50 */
2898                 corr = ((t * 301) + 1004);
2899
2900         corr = corr * ((150142 * state1) / 10000 - 78642);
2901         corr /= 100000;
2902         corr2 = (corr * dev_priv->corr);
2903
2904         state2 = (corr2 * state1) / 10000;
2905         state2 /= 100; /* convert to mW */
2906
2907         i915_update_gfx_val(dev_priv);
2908
2909         return dev_priv->gfx_power + state2;
2910 }
2911
2912 /* Global for IPS driver to get at the current i915 device */
2913 static struct drm_i915_private *i915_mch_dev;
2914 /*
2915  * Lock protecting IPS related data structures
2916  *   - i915_mch_dev
2917  *   - dev_priv->max_delay
2918  *   - dev_priv->min_delay
2919  *   - dev_priv->fmax
2920  *   - dev_priv->gpu_busy
2921  */
2922 static DEFINE_SPINLOCK(mchdev_lock);
2923
2924 /**
2925  * i915_read_mch_val - return value for IPS use
2926  *
2927  * Calculate and return a value for the IPS driver to use when deciding whether
2928  * we have thermal and power headroom to increase CPU or GPU power budget.
2929  */
2930 unsigned long i915_read_mch_val(void)
2931 {
2932         struct drm_i915_private *dev_priv;
2933         unsigned long chipset_val, graphics_val, ret = 0;
2934
2935         spin_lock(&mchdev_lock);
2936         if (!i915_mch_dev)
2937                 goto out_unlock;
2938         dev_priv = i915_mch_dev;
2939
2940         chipset_val = i915_chipset_val(dev_priv);
2941         graphics_val = i915_gfx_val(dev_priv);
2942
2943         ret = chipset_val + graphics_val;
2944
2945 out_unlock:
2946         spin_unlock(&mchdev_lock);
2947
2948         return ret;
2949 }
2950 EXPORT_SYMBOL_GPL(i915_read_mch_val);
2951
2952 /**
2953  * i915_gpu_raise - raise GPU frequency limit
2954  *
2955  * Raise the limit; IPS indicates we have thermal headroom.
2956  */
2957 bool i915_gpu_raise(void)
2958 {
2959         struct drm_i915_private *dev_priv;
2960         bool ret = true;
2961
2962         spin_lock(&mchdev_lock);
2963         if (!i915_mch_dev) {
2964                 ret = false;
2965                 goto out_unlock;
2966         }
2967         dev_priv = i915_mch_dev;
2968
2969         if (dev_priv->max_delay > dev_priv->fmax)
2970                 dev_priv->max_delay--;
2971
2972 out_unlock:
2973         spin_unlock(&mchdev_lock);
2974
2975         return ret;
2976 }
2977 EXPORT_SYMBOL_GPL(i915_gpu_raise);
2978
2979 /**
2980  * i915_gpu_lower - lower GPU frequency limit
2981  *
2982  * IPS indicates we're close to a thermal limit, so throttle back the GPU
2983  * frequency maximum.
2984  */
2985 bool i915_gpu_lower(void)
2986 {
2987         struct drm_i915_private *dev_priv;
2988         bool ret = true;
2989
2990         spin_lock(&mchdev_lock);
2991         if (!i915_mch_dev) {
2992                 ret = false;
2993                 goto out_unlock;
2994         }
2995         dev_priv = i915_mch_dev;
2996
2997         if (dev_priv->max_delay < dev_priv->min_delay)
2998                 dev_priv->max_delay++;
2999
3000 out_unlock:
3001         spin_unlock(&mchdev_lock);
3002
3003         return ret;
3004 }
3005 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3006
3007 /**
3008  * i915_gpu_busy - indicate GPU business to IPS
3009  *
3010  * Tell the IPS driver whether or not the GPU is busy.
3011  */
3012 bool i915_gpu_busy(void)
3013 {
3014         struct drm_i915_private *dev_priv;
3015         bool ret = false;
3016
3017         spin_lock(&mchdev_lock);
3018         if (!i915_mch_dev)
3019                 goto out_unlock;
3020         dev_priv = i915_mch_dev;
3021
3022         ret = dev_priv->busy;
3023
3024 out_unlock:
3025         spin_unlock(&mchdev_lock);
3026
3027         return ret;
3028 }
3029 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3030
3031 /**
3032  * i915_gpu_turbo_disable - disable graphics turbo
3033  *
3034  * Disable graphics turbo by resetting the max frequency and setting the
3035  * current frequency to the default.
3036  */
3037 bool i915_gpu_turbo_disable(void)
3038 {
3039         struct drm_i915_private *dev_priv;
3040         bool ret = true;
3041
3042         spin_lock(&mchdev_lock);
3043         if (!i915_mch_dev) {
3044                 ret = false;
3045                 goto out_unlock;
3046         }
3047         dev_priv = i915_mch_dev;
3048
3049         dev_priv->max_delay = dev_priv->fstart;
3050
3051         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
3052                 ret = false;
3053
3054 out_unlock:
3055         spin_unlock(&mchdev_lock);
3056
3057         return ret;
3058 }
3059 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3060
3061 /**
3062  * Tells the intel_ips driver that the i915 driver is now loaded, if
3063  * IPS got loaded first.
3064  *
3065  * This awkward dance is so that neither module has to depend on the
3066  * other in order for IPS to do the appropriate communication of
3067  * GPU turbo limits to i915.
3068  */
3069 static void
3070 ips_ping_for_i915_load(void)
3071 {
3072         void (*link)(void);
3073
3074         link = symbol_get(ips_link_to_i915_driver);
3075         if (link) {
3076                 link();
3077                 symbol_put(ips_link_to_i915_driver);
3078         }
3079 }
3080
3081 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3082 {
3083         spin_lock(&mchdev_lock);
3084         i915_mch_dev = dev_priv;
3085         dev_priv->mchdev_lock = &mchdev_lock;
3086         spin_unlock(&mchdev_lock);
3087
3088         ips_ping_for_i915_load();
3089 }
3090
3091 void intel_gpu_ips_teardown(void)
3092 {
3093         spin_lock(&mchdev_lock);
3094         i915_mch_dev = NULL;
3095         spin_unlock(&mchdev_lock);
3096 }
3097
3098 void intel_init_emon(struct drm_device *dev)
3099 {
3100         struct drm_i915_private *dev_priv = dev->dev_private;
3101         u32 lcfuse;
3102         u8 pxw[16];
3103         int i;
3104
3105         /* Disable to program */
3106         I915_WRITE(ECR, 0);
3107         POSTING_READ(ECR);
3108
3109         /* Program energy weights for various events */
3110         I915_WRITE(SDEW, 0x15040d00);
3111         I915_WRITE(CSIEW0, 0x007f0000);
3112         I915_WRITE(CSIEW1, 0x1e220004);
3113         I915_WRITE(CSIEW2, 0x04000004);
3114
3115         for (i = 0; i < 5; i++)
3116                 I915_WRITE(PEW + (i * 4), 0);
3117         for (i = 0; i < 3; i++)
3118                 I915_WRITE(DEW + (i * 4), 0);
3119
3120         /* Program P-state weights to account for frequency power adjustment */
3121         for (i = 0; i < 16; i++) {
3122                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3123                 unsigned long freq = intel_pxfreq(pxvidfreq);
3124                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3125                         PXVFREQ_PX_SHIFT;
3126                 unsigned long val;
3127
3128                 val = vid * vid;
3129                 val *= (freq / 1000);
3130                 val *= 255;
3131                 val /= (127*127*900);
3132                 if (val > 0xff)
3133                         DRM_ERROR("bad pxval: %ld\n", val);
3134                 pxw[i] = val;
3135         }
3136         /* Render standby states get 0 weight */
3137         pxw[14] = 0;
3138         pxw[15] = 0;
3139
3140         for (i = 0; i < 4; i++) {
3141                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3142                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3143                 I915_WRITE(PXW + (i * 4), val);
3144         }
3145
3146         /* Adjust magic regs to magic values (more experimental results) */
3147         I915_WRITE(OGW0, 0);
3148         I915_WRITE(OGW1, 0);
3149         I915_WRITE(EG0, 0x00007f00);
3150         I915_WRITE(EG1, 0x0000000e);
3151         I915_WRITE(EG2, 0x000e0000);
3152         I915_WRITE(EG3, 0x68000300);
3153         I915_WRITE(EG4, 0x42000000);
3154         I915_WRITE(EG5, 0x00140031);
3155         I915_WRITE(EG6, 0);
3156         I915_WRITE(EG7, 0);
3157
3158         for (i = 0; i < 8; i++)
3159                 I915_WRITE(PXWL + (i * 4), 0);
3160
3161         /* Enable PMON + select events */
3162         I915_WRITE(ECR, 0x80000019);
3163
3164         lcfuse = I915_READ(LCFUSE02);
3165
3166         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
3167 }
3168
3169 static void ironlake_init_clock_gating(struct drm_device *dev)
3170 {
3171         struct drm_i915_private *dev_priv = dev->dev_private;
3172         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3173
3174         /* Required for FBC */
3175         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
3176                 DPFCRUNIT_CLOCK_GATE_DISABLE |
3177                 DPFDUNIT_CLOCK_GATE_DISABLE;
3178         /* Required for CxSR */
3179         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
3180
3181         I915_WRITE(PCH_3DCGDIS0,
3182                    MARIUNIT_CLOCK_GATE_DISABLE |
3183                    SVSMUNIT_CLOCK_GATE_DISABLE);
3184         I915_WRITE(PCH_3DCGDIS1,
3185                    VFMUNIT_CLOCK_GATE_DISABLE);
3186
3187         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3188
3189         /*
3190          * According to the spec the following bits should be set in
3191          * order to enable memory self-refresh
3192          * The bit 22/21 of 0x42004
3193          * The bit 5 of 0x42020
3194          * The bit 15 of 0x45000
3195          */
3196         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3197                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3198                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3199         I915_WRITE(ILK_DSPCLK_GATE,
3200                    (I915_READ(ILK_DSPCLK_GATE) |
3201                     ILK_DPARB_CLK_GATE));
3202         I915_WRITE(DISP_ARB_CTL,
3203                    (I915_READ(DISP_ARB_CTL) |
3204                     DISP_FBC_WM_DIS));
3205         I915_WRITE(WM3_LP_ILK, 0);
3206         I915_WRITE(WM2_LP_ILK, 0);
3207         I915_WRITE(WM1_LP_ILK, 0);
3208
3209         /*
3210          * Based on the document from hardware guys the following bits
3211          * should be set unconditionally in order to enable FBC.
3212          * The bit 22 of 0x42000
3213          * The bit 22 of 0x42004
3214          * The bit 7,8,9 of 0x42020.
3215          */
3216         if (IS_IRONLAKE_M(dev)) {
3217                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3218                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3219                            ILK_FBCQ_DIS);
3220                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3221                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3222                            ILK_DPARB_GATE);
3223                 I915_WRITE(ILK_DSPCLK_GATE,
3224                            I915_READ(ILK_DSPCLK_GATE) |
3225                            ILK_DPFC_DIS1 |
3226                            ILK_DPFC_DIS2 |
3227                            ILK_CLK_FBC);
3228         }
3229
3230         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3231                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3232                    ILK_ELPIN_409_SELECT);
3233         I915_WRITE(_3D_CHICKEN2,
3234                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3235                    _3D_CHICKEN2_WM_READ_PIPELINED);
3236 }
3237
3238 static void gen6_init_clock_gating(struct drm_device *dev)
3239 {
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         int pipe;
3242         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3243
3244         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3245
3246         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3247                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3248                    ILK_ELPIN_409_SELECT);
3249
3250         I915_WRITE(WM3_LP_ILK, 0);
3251         I915_WRITE(WM2_LP_ILK, 0);
3252         I915_WRITE(WM1_LP_ILK, 0);
3253
3254         I915_WRITE(CACHE_MODE_0,
3255                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3256
3257         I915_WRITE(GEN6_UCGCTL1,
3258                    I915_READ(GEN6_UCGCTL1) |
3259                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3260                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3261
3262         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3263          * gating disable must be set.  Failure to set it results in
3264          * flickering pixels due to Z write ordering failures after
3265          * some amount of runtime in the Mesa "fire" demo, and Unigine
3266          * Sanctuary and Tropics, and apparently anything else with
3267          * alpha test or pixel discard.
3268          *
3269          * According to the spec, bit 11 (RCCUNIT) must also be set,
3270          * but we didn't debug actual testcases to find it out.
3271          */
3272         I915_WRITE(GEN6_UCGCTL2,
3273                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3274                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3275
3276         /* Bspec says we need to always set all mask bits. */
3277         I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
3278                    _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
3279
3280         /*
3281          * According to the spec the following bits should be
3282          * set in order to enable memory self-refresh and fbc:
3283          * The bit21 and bit22 of 0x42000
3284          * The bit21 and bit22 of 0x42004
3285          * The bit5 and bit7 of 0x42020
3286          * The bit14 of 0x70180
3287          * The bit14 of 0x71180
3288          */
3289         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3290                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3291                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3292         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3293                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3294                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3295         I915_WRITE(ILK_DSPCLK_GATE,
3296                    I915_READ(ILK_DSPCLK_GATE) |
3297                    ILK_DPARB_CLK_GATE  |
3298                    ILK_DPFD_CLK_GATE);
3299
3300         for_each_pipe(pipe) {
3301                 I915_WRITE(DSPCNTR(pipe),
3302                            I915_READ(DSPCNTR(pipe)) |
3303                            DISPPLANE_TRICKLE_FEED_DISABLE);
3304                 intel_flush_display_plane(dev_priv, pipe);
3305         }
3306 }
3307
3308 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3309 {
3310         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3311
3312         reg &= ~GEN7_FF_SCHED_MASK;
3313         reg |= GEN7_FF_TS_SCHED_HW;
3314         reg |= GEN7_FF_VS_SCHED_HW;
3315         reg |= GEN7_FF_DS_SCHED_HW;
3316
3317         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3318 }
3319
3320 static void ivybridge_init_clock_gating(struct drm_device *dev)
3321 {
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323         int pipe;
3324         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3325
3326         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3327
3328         I915_WRITE(WM3_LP_ILK, 0);
3329         I915_WRITE(WM2_LP_ILK, 0);
3330         I915_WRITE(WM1_LP_ILK, 0);
3331
3332         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3333          * This implements the WaDisableRCZUnitClockGating workaround.
3334          */
3335         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3336
3337         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3338
3339         I915_WRITE(IVB_CHICKEN3,
3340                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3341                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3342
3343         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3344         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3345                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3346
3347         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3348         I915_WRITE(GEN7_L3CNTLREG1,
3349                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3350         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3351                         GEN7_WA_L3_CHICKEN_MODE);
3352
3353         /* This is required by WaCatErrorRejectionIssue */
3354         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3355                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3356                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3357
3358         for_each_pipe(pipe) {
3359                 I915_WRITE(DSPCNTR(pipe),
3360                            I915_READ(DSPCNTR(pipe)) |
3361                            DISPPLANE_TRICKLE_FEED_DISABLE);
3362                 intel_flush_display_plane(dev_priv, pipe);
3363         }
3364
3365         gen7_setup_fixed_func_scheduler(dev_priv);
3366
3367         /* WaDisable4x2SubspanOptimization */
3368         I915_WRITE(CACHE_MODE_1,
3369                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3370 }
3371
3372 static void valleyview_init_clock_gating(struct drm_device *dev)
3373 {
3374         struct drm_i915_private *dev_priv = dev->dev_private;
3375         int pipe;
3376         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3377
3378         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3379
3380         I915_WRITE(WM3_LP_ILK, 0);
3381         I915_WRITE(WM2_LP_ILK, 0);
3382         I915_WRITE(WM1_LP_ILK, 0);
3383
3384         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3385          * This implements the WaDisableRCZUnitClockGating workaround.
3386          */
3387         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3388
3389         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3390
3391         I915_WRITE(IVB_CHICKEN3,
3392                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3393                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3394
3395         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3396         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3397                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3398
3399         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3400         I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
3401         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3402
3403         /* This is required by WaCatErrorRejectionIssue */
3404         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3405                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3406                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3407
3408         for_each_pipe(pipe) {
3409                 I915_WRITE(DSPCNTR(pipe),
3410                            I915_READ(DSPCNTR(pipe)) |
3411                            DISPPLANE_TRICKLE_FEED_DISABLE);
3412                 intel_flush_display_plane(dev_priv, pipe);
3413         }
3414
3415         I915_WRITE(CACHE_MODE_1,
3416                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3417 }
3418
3419 static void g4x_init_clock_gating(struct drm_device *dev)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         uint32_t dspclk_gate;
3423
3424         I915_WRITE(RENCLK_GATE_D1, 0);
3425         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3426                    GS_UNIT_CLOCK_GATE_DISABLE |
3427                    CL_UNIT_CLOCK_GATE_DISABLE);
3428         I915_WRITE(RAMCLK_GATE_D, 0);
3429         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3430                 OVRUNIT_CLOCK_GATE_DISABLE |
3431                 OVCUNIT_CLOCK_GATE_DISABLE;
3432         if (IS_GM45(dev))
3433                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3434         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3435 }
3436
3437 static void crestline_init_clock_gating(struct drm_device *dev)
3438 {
3439         struct drm_i915_private *dev_priv = dev->dev_private;
3440
3441         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3442         I915_WRITE(RENCLK_GATE_D2, 0);
3443         I915_WRITE(DSPCLK_GATE_D, 0);
3444         I915_WRITE(RAMCLK_GATE_D, 0);
3445         I915_WRITE16(DEUC, 0);
3446 }
3447
3448 static void broadwater_init_clock_gating(struct drm_device *dev)
3449 {
3450         struct drm_i915_private *dev_priv = dev->dev_private;
3451
3452         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3453                    I965_RCC_CLOCK_GATE_DISABLE |
3454                    I965_RCPB_CLOCK_GATE_DISABLE |
3455                    I965_ISC_CLOCK_GATE_DISABLE |
3456                    I965_FBC_CLOCK_GATE_DISABLE);
3457         I915_WRITE(RENCLK_GATE_D2, 0);
3458 }
3459
3460 static void gen3_init_clock_gating(struct drm_device *dev)
3461 {
3462         struct drm_i915_private *dev_priv = dev->dev_private;
3463         u32 dstate = I915_READ(D_STATE);
3464
3465         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3466                 DSTATE_DOT_CLOCK_GATING;
3467         I915_WRITE(D_STATE, dstate);
3468
3469         if (IS_PINEVIEW(dev))
3470                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
3471 }
3472
3473 static void i85x_init_clock_gating(struct drm_device *dev)
3474 {
3475         struct drm_i915_private *dev_priv = dev->dev_private;
3476
3477         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3478 }
3479
3480 static void i830_init_clock_gating(struct drm_device *dev)
3481 {
3482         struct drm_i915_private *dev_priv = dev->dev_private;
3483
3484         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3485 }
3486
3487 static void ibx_init_clock_gating(struct drm_device *dev)
3488 {
3489         struct drm_i915_private *dev_priv = dev->dev_private;
3490
3491         /*
3492          * On Ibex Peak and Cougar Point, we need to disable clock
3493          * gating for the panel power sequencer or it will fail to
3494          * start up when no ports are active.
3495          */
3496         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3497 }
3498
3499 static void cpt_init_clock_gating(struct drm_device *dev)
3500 {
3501         struct drm_i915_private *dev_priv = dev->dev_private;
3502         int pipe;
3503
3504         /*
3505          * On Ibex Peak and Cougar Point, we need to disable clock
3506          * gating for the panel power sequencer or it will fail to
3507          * start up when no ports are active.
3508          */
3509         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3510         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3511                    DPLS_EDP_PPS_FIX_DIS);
3512         /* Without this, mode sets may fail silently on FDI */
3513         for_each_pipe(pipe)
3514                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
3515 }
3516
3517 void intel_init_clock_gating(struct drm_device *dev)
3518 {
3519         struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521         dev_priv->display.init_clock_gating(dev);
3522
3523         if (dev_priv->display.init_pch_clock_gating)
3524                 dev_priv->display.init_pch_clock_gating(dev);
3525 }
3526
3527 static void gen6_sanitize_pm(struct drm_device *dev)
3528 {
3529         struct drm_i915_private *dev_priv = dev->dev_private;
3530         u32 limits, delay, old;
3531
3532         gen6_gt_force_wake_get(dev_priv);
3533
3534         old = limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
3535         /* Make sure we continue to get interrupts
3536          * until we hit the minimum or maximum frequencies.
3537          */
3538         limits &= ~(0x3f << 16 | 0x3f << 24);
3539         delay = dev_priv->cur_delay;
3540         if (delay < dev_priv->max_delay)
3541                 limits |= (dev_priv->max_delay & 0x3f) << 24;
3542         if (delay > dev_priv->min_delay)
3543                 limits |= (dev_priv->min_delay & 0x3f) << 16;
3544
3545         if (old != limits) {
3546                 DRM_ERROR("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS expected %08x, was %08x\n",
3547                           limits, old);
3548                 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3549         }
3550
3551         gen6_gt_force_wake_put(dev_priv);
3552 }
3553
3554 void intel_sanitize_pm(struct drm_device *dev)
3555 {
3556         struct drm_i915_private *dev_priv = dev->dev_private;
3557
3558         if (dev_priv->display.sanitize_pm)
3559                 dev_priv->display.sanitize_pm(dev);
3560 }
3561
3562 /* Set up chip specific power management-related functions */
3563 void intel_init_pm(struct drm_device *dev)
3564 {
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566
3567         if (I915_HAS_FBC(dev)) {
3568                 if (HAS_PCH_SPLIT(dev)) {
3569                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3570                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
3571                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
3572                 } else if (IS_GM45(dev)) {
3573                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3574                         dev_priv->display.enable_fbc = g4x_enable_fbc;
3575                         dev_priv->display.disable_fbc = g4x_disable_fbc;
3576                 } else if (IS_CRESTLINE(dev)) {
3577                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3578                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
3579                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
3580                 }
3581                 /* 855GM needs testing */
3582         }
3583
3584         /* For cxsr */
3585         if (IS_PINEVIEW(dev))
3586                 i915_pineview_get_mem_freq(dev);
3587         else if (IS_GEN5(dev))
3588                 i915_ironlake_get_mem_freq(dev);
3589
3590         /* For FIFO watermark updates */
3591         if (HAS_PCH_SPLIT(dev)) {
3592                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
3593                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
3594
3595                 /* IVB configs may use multi-threaded forcewake */
3596                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3597                         u32     ecobus;
3598
3599                         /* A small trick here - if the bios hasn't configured MT forcewake,
3600                          * and if the device is in RC6, then force_wake_mt_get will not wake
3601                          * the device and the ECOBUS read will return zero. Which will be
3602                          * (correctly) interpreted by the test below as MT forcewake being
3603                          * disabled.
3604                          */
3605                         mutex_lock(&dev->struct_mutex);
3606                         __gen6_gt_force_wake_mt_get(dev_priv);
3607                         ecobus = I915_READ_NOTRACE(ECOBUS);
3608                         __gen6_gt_force_wake_mt_put(dev_priv);
3609                         mutex_unlock(&dev->struct_mutex);
3610
3611                         if (ecobus & FORCEWAKE_MT_ENABLE) {
3612                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
3613                                 dev_priv->display.force_wake_get =
3614                                         __gen6_gt_force_wake_mt_get;
3615                                 dev_priv->display.force_wake_put =
3616                                         __gen6_gt_force_wake_mt_put;
3617                         }
3618                 }
3619
3620                 if (HAS_PCH_IBX(dev))
3621                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
3622                 else if (HAS_PCH_CPT(dev))
3623                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
3624
3625                 if (IS_GEN5(dev)) {
3626                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3627                                 dev_priv->display.update_wm = ironlake_update_wm;
3628                         else {
3629                                 DRM_DEBUG_KMS("Failed to get proper latency. "
3630                                               "Disable CxSR\n");
3631                                 dev_priv->display.update_wm = NULL;
3632                         }
3633                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3634                 } else if (IS_GEN6(dev)) {
3635                         if (SNB_READ_WM0_LATENCY()) {
3636                                 dev_priv->display.update_wm = sandybridge_update_wm;
3637                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3638                         } else {
3639                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
3640                                               "Disable CxSR\n");
3641                                 dev_priv->display.update_wm = NULL;
3642                         }
3643                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
3644                         dev_priv->display.sanitize_pm = gen6_sanitize_pm;
3645                 } else if (IS_IVYBRIDGE(dev)) {
3646                         /* FIXME: detect B0+ stepping and use auto training */
3647                         if (SNB_READ_WM0_LATENCY()) {
3648                                 dev_priv->display.update_wm = sandybridge_update_wm;
3649                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3650                         } else {
3651                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
3652                                               "Disable CxSR\n");
3653                                 dev_priv->display.update_wm = NULL;
3654                         }
3655                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
3656                         dev_priv->display.sanitize_pm = gen6_sanitize_pm;
3657                 } else
3658                         dev_priv->display.update_wm = NULL;
3659         } else if (IS_VALLEYVIEW(dev)) {
3660                 dev_priv->display.update_wm = valleyview_update_wm;
3661                 dev_priv->display.init_clock_gating =
3662                         valleyview_init_clock_gating;
3663                 dev_priv->display.force_wake_get = vlv_force_wake_get;
3664                 dev_priv->display.force_wake_put = vlv_force_wake_put;
3665         } else if (IS_PINEVIEW(dev)) {
3666                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
3667                                             dev_priv->is_ddr3,
3668                                             dev_priv->fsb_freq,
3669                                             dev_priv->mem_freq)) {
3670                         DRM_INFO("failed to find known CxSR latency "
3671                                  "(found ddr%s fsb freq %d, mem freq %d), "
3672                                  "disabling CxSR\n",
3673                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
3674                                  dev_priv->fsb_freq, dev_priv->mem_freq);
3675                         /* Disable CxSR and never update its watermark again */
3676                         pineview_disable_cxsr(dev);
3677                         dev_priv->display.update_wm = NULL;
3678                 } else
3679                         dev_priv->display.update_wm = pineview_update_wm;
3680                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
3681         } else if (IS_G4X(dev)) {
3682                 dev_priv->display.update_wm = g4x_update_wm;
3683                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
3684         } else if (IS_GEN4(dev)) {
3685                 dev_priv->display.update_wm = i965_update_wm;
3686                 if (IS_CRESTLINE(dev))
3687                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
3688                 else if (IS_BROADWATER(dev))
3689                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
3690         } else if (IS_GEN3(dev)) {
3691                 dev_priv->display.update_wm = i9xx_update_wm;
3692                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
3693                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
3694         } else if (IS_I865G(dev)) {
3695                 dev_priv->display.update_wm = i830_update_wm;
3696                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
3697                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
3698         } else if (IS_I85X(dev)) {
3699                 dev_priv->display.update_wm = i9xx_update_wm;
3700                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
3701                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
3702         } else {
3703                 dev_priv->display.update_wm = i830_update_wm;
3704                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
3705                 if (IS_845G(dev))
3706                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
3707                 else
3708                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
3709         }
3710 }
3711