2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
46 static void i8xx_disable_fbc(struct drm_device *dev)
48 struct drm_i915_private *dev_priv = dev->dev_private;
51 /* Disable compression */
52 fbc_ctl = I915_READ(FBC_CONTROL);
53 if ((fbc_ctl & FBC_CTL_EN) == 0)
56 fbc_ctl &= ~FBC_CTL_EN;
57 I915_WRITE(FBC_CONTROL, fbc_ctl);
59 /* Wait for compressing bit to clear */
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
61 DRM_DEBUG_KMS("FBC idle timed out\n");
65 DRM_DEBUG_KMS("disabled FBC\n");
68 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
70 struct drm_device *dev = crtc->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 struct drm_framebuffer *fb = crtc->fb;
73 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
74 struct drm_i915_gem_object *obj = intel_fb->obj;
75 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
78 u32 fbc_ctl, fbc_ctl2;
80 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
81 if (fb->pitches[0] < cfb_pitch)
82 cfb_pitch = fb->pitches[0];
84 /* FBC_CTL wants 64B units */
85 cfb_pitch = (cfb_pitch / 64) - 1;
86 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
89 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
90 I915_WRITE(FBC_TAG + (i * 4), 0);
93 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
95 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
96 I915_WRITE(FBC_FENCE_OFF, crtc->y);
99 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
101 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
102 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
103 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
104 fbc_ctl |= obj->fence_reg;
105 I915_WRITE(FBC_CONTROL, fbc_ctl);
107 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
108 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
111 static bool i8xx_fbc_enabled(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
115 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
118 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
120 struct drm_device *dev = crtc->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_framebuffer *fb = crtc->fb;
123 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
124 struct drm_i915_gem_object *obj = intel_fb->obj;
125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
126 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
127 unsigned long stall_watermark = 200;
130 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
131 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
132 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
134 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
135 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
136 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
137 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
140 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
142 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
145 static void g4x_disable_fbc(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 /* Disable compression */
151 dpfc_ctl = I915_READ(DPFC_CONTROL);
152 if (dpfc_ctl & DPFC_CTL_EN) {
153 dpfc_ctl &= ~DPFC_CTL_EN;
154 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
156 DRM_DEBUG_KMS("disabled FBC\n");
160 static bool g4x_fbc_enabled(struct drm_device *dev)
162 struct drm_i915_private *dev_priv = dev->dev_private;
164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
167 static void sandybridge_blit_fbc_update(struct drm_device *dev)
169 struct drm_i915_private *dev_priv = dev->dev_private;
172 /* Make sure blitter notifies FBC of writes */
173 gen6_gt_force_wake_get(dev_priv);
174 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
175 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
176 GEN6_BLITTER_LOCK_SHIFT;
177 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
178 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
179 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
180 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
181 GEN6_BLITTER_LOCK_SHIFT);
182 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
183 POSTING_READ(GEN6_BLITTER_ECOSKPD);
184 gen6_gt_force_wake_put(dev_priv);
187 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
189 struct drm_device *dev = crtc->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct drm_framebuffer *fb = crtc->fb;
192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
193 struct drm_i915_gem_object *obj = intel_fb->obj;
194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
195 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
196 unsigned long stall_watermark = 200;
199 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
200 dpfc_ctl &= DPFC_RESERVED;
201 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
202 /* Set persistent mode for front-buffer rendering, ala X. */
203 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
207 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
208 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
209 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
210 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
211 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
213 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
216 I915_WRITE(SNB_DPFC_CTL_SA,
217 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
218 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
219 sandybridge_blit_fbc_update(dev);
222 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
225 static void ironlake_disable_fbc(struct drm_device *dev)
227 struct drm_i915_private *dev_priv = dev->dev_private;
230 /* Disable compression */
231 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
232 if (dpfc_ctl & DPFC_CTL_EN) {
233 dpfc_ctl &= ~DPFC_CTL_EN;
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
236 if (IS_IVYBRIDGE(dev))
237 /* WaFbcDisableDpfcClockGating:ivb */
238 I915_WRITE(ILK_DSPCLK_GATE_D,
239 I915_READ(ILK_DSPCLK_GATE_D) &
240 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
243 /* WaFbcDisableDpfcClockGating:hsw */
244 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
245 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
246 ~HSW_DPFC_GATING_DISABLE);
248 DRM_DEBUG_KMS("disabled FBC\n");
252 static bool ironlake_fbc_enabled(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
259 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
261 struct drm_device *dev = crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_framebuffer *fb = crtc->fb;
264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
265 struct drm_i915_gem_object *obj = intel_fb->obj;
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
268 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
270 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
271 IVB_DPFC_CTL_FENCE_EN |
272 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
274 if (IS_IVYBRIDGE(dev)) {
275 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
276 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
277 /* WaFbcDisableDpfcClockGating:ivb */
278 I915_WRITE(ILK_DSPCLK_GATE_D,
279 I915_READ(ILK_DSPCLK_GATE_D) |
280 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
282 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
283 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
284 HSW_BYPASS_FBC_QUEUE);
285 /* WaFbcDisableDpfcClockGating:hsw */
286 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
287 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
288 HSW_DPFC_GATING_DISABLE);
291 I915_WRITE(SNB_DPFC_CTL_SA,
292 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
293 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
295 sandybridge_blit_fbc_update(dev);
297 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
300 bool intel_fbc_enabled(struct drm_device *dev)
302 struct drm_i915_private *dev_priv = dev->dev_private;
304 if (!dev_priv->display.fbc_enabled)
307 return dev_priv->display.fbc_enabled(dev);
310 static void intel_fbc_work_fn(struct work_struct *__work)
312 struct intel_fbc_work *work =
313 container_of(to_delayed_work(__work),
314 struct intel_fbc_work, work);
315 struct drm_device *dev = work->crtc->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
318 mutex_lock(&dev->struct_mutex);
319 if (work == dev_priv->fbc.fbc_work) {
320 /* Double check that we haven't switched fb without cancelling
323 if (work->crtc->fb == work->fb) {
324 dev_priv->display.enable_fbc(work->crtc,
327 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
328 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
329 dev_priv->fbc.y = work->crtc->y;
332 dev_priv->fbc.fbc_work = NULL;
334 mutex_unlock(&dev->struct_mutex);
339 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
341 if (dev_priv->fbc.fbc_work == NULL)
344 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
346 /* Synchronisation is provided by struct_mutex and checking of
347 * dev_priv->fbc.fbc_work, so we can perform the cancellation
348 * entirely asynchronously.
350 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
351 /* tasklet was killed before being run, clean up */
352 kfree(dev_priv->fbc.fbc_work);
354 /* Mark the work as no longer wanted so that if it does
355 * wake-up (because the work was already running and waiting
356 * for our mutex), it will discover that is no longer
359 dev_priv->fbc.fbc_work = NULL;
362 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
364 struct intel_fbc_work *work;
365 struct drm_device *dev = crtc->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
368 if (!dev_priv->display.enable_fbc)
371 intel_cancel_fbc_work(dev_priv);
373 work = kzalloc(sizeof(*work), GFP_KERNEL);
375 DRM_ERROR("Failed to allocate FBC work structure\n");
376 dev_priv->display.enable_fbc(crtc, interval);
382 work->interval = interval;
383 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
385 dev_priv->fbc.fbc_work = work;
387 /* Delay the actual enabling to let pageflipping cease and the
388 * display to settle before starting the compression. Note that
389 * this delay also serves a second purpose: it allows for a
390 * vblank to pass after disabling the FBC before we attempt
391 * to modify the control registers.
393 * A more complicated solution would involve tracking vblanks
394 * following the termination of the page-flipping sequence
395 * and indeed performing the enable as a co-routine and not
396 * waiting synchronously upon the vblank.
398 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
400 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
403 void intel_disable_fbc(struct drm_device *dev)
405 struct drm_i915_private *dev_priv = dev->dev_private;
407 intel_cancel_fbc_work(dev_priv);
409 if (!dev_priv->display.disable_fbc)
412 dev_priv->display.disable_fbc(dev);
413 dev_priv->fbc.plane = -1;
416 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
417 enum no_fbc_reason reason)
419 if (dev_priv->fbc.no_fbc_reason == reason)
422 dev_priv->fbc.no_fbc_reason = reason;
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
443 * We need to enable/disable FBC on a global basis.
445 void intel_update_fbc(struct drm_device *dev)
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
453 const struct drm_display_mode *adjusted_mode;
454 unsigned int max_width, max_height;
456 if (!I915_HAS_FBC(dev)) {
457 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
461 if (!i915_powersave) {
462 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
463 DRM_DEBUG_KMS("fbc disabled per module param\n");
468 * If FBC is already on, we just have to verify that we can
469 * keep it that way...
470 * Need to disable if:
471 * - more than one pipe is active
472 * - changing FBC params (stride, fence, mode)
473 * - new fb is too large to fit in compressed buffer
474 * - going to an unsupported config (interlace, pixel multiply, etc.)
476 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
477 if (intel_crtc_active(tmp_crtc) &&
478 to_intel_crtc(tmp_crtc)->primary_enabled) {
480 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
481 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
488 if (!crtc || crtc->fb == NULL) {
489 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
490 DRM_DEBUG_KMS("no output, disabling\n");
494 intel_crtc = to_intel_crtc(crtc);
496 intel_fb = to_intel_framebuffer(fb);
498 adjusted_mode = &intel_crtc->config.adjusted_mode;
500 if (i915_enable_fbc < 0 &&
501 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
502 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
503 DRM_DEBUG_KMS("disabled per chip default\n");
506 if (!i915_enable_fbc) {
507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
511 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
512 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
513 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
514 DRM_DEBUG_KMS("mode incompatible with compression, "
519 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 if (intel_crtc->config.pipe_src_w > max_width ||
527 intel_crtc->config.pipe_src_h > max_height) {
528 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
529 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
532 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
533 intel_crtc->plane != 0) {
534 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
535 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
539 /* The use of a CPU fence is mandatory in order to detect writes
540 * by the CPU to the scanout and trigger updates to the FBC.
542 if (obj->tiling_mode != I915_TILING_X ||
543 obj->fence_reg == I915_FENCE_REG_NONE) {
544 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
545 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
549 /* If the kernel debugger is active, always disable compression */
553 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
554 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
555 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
559 /* If the scanout has not changed, don't modify the FBC settings.
560 * Note that we make the fundamental assumption that the fb->obj
561 * cannot be unpinned (and have its GTT offset and fence revoked)
562 * without first being decoupled from the scanout and FBC disabled.
564 if (dev_priv->fbc.plane == intel_crtc->plane &&
565 dev_priv->fbc.fb_id == fb->base.id &&
566 dev_priv->fbc.y == crtc->y)
569 if (intel_fbc_enabled(dev)) {
570 /* We update FBC along two paths, after changing fb/crtc
571 * configuration (modeswitching) and after page-flipping
572 * finishes. For the latter, we know that not only did
573 * we disable the FBC at the start of the page-flip
574 * sequence, but also more than one vblank has passed.
576 * For the former case of modeswitching, it is possible
577 * to switch between two FBC valid configurations
578 * instantaneously so we do need to disable the FBC
579 * before we can modify its control registers. We also
580 * have to wait for the next vblank for that to take
581 * effect. However, since we delay enabling FBC we can
582 * assume that a vblank has passed since disabling and
583 * that we can safely alter the registers in the deferred
586 * In the scenario that we go from a valid to invalid
587 * and then back to valid FBC configuration we have
588 * no strict enforcement that a vblank occurred since
589 * disabling the FBC. However, along all current pipe
590 * disabling paths we do need to wait for a vblank at
591 * some point. And we wait before enabling FBC anyway.
593 DRM_DEBUG_KMS("disabling active FBC for update\n");
594 intel_disable_fbc(dev);
597 intel_enable_fbc(crtc, 500);
598 dev_priv->fbc.no_fbc_reason = FBC_OK;
602 /* Multiple disables should be harmless */
603 if (intel_fbc_enabled(dev)) {
604 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
605 intel_disable_fbc(dev);
607 i915_gem_stolen_cleanup_compression(dev);
610 static void i915_pineview_get_mem_freq(struct drm_device *dev)
612 drm_i915_private_t *dev_priv = dev->dev_private;
615 tmp = I915_READ(CLKCFG);
617 switch (tmp & CLKCFG_FSB_MASK) {
619 dev_priv->fsb_freq = 533; /* 133*4 */
622 dev_priv->fsb_freq = 800; /* 200*4 */
625 dev_priv->fsb_freq = 667; /* 167*4 */
628 dev_priv->fsb_freq = 400; /* 100*4 */
632 switch (tmp & CLKCFG_MEM_MASK) {
634 dev_priv->mem_freq = 533;
637 dev_priv->mem_freq = 667;
640 dev_priv->mem_freq = 800;
644 /* detect pineview DDR3 setting */
645 tmp = I915_READ(CSHRDDR3CTL);
646 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
649 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
651 drm_i915_private_t *dev_priv = dev->dev_private;
654 ddrpll = I915_READ16(DDRMPLL1);
655 csipll = I915_READ16(CSIPLL0);
657 switch (ddrpll & 0xff) {
659 dev_priv->mem_freq = 800;
662 dev_priv->mem_freq = 1066;
665 dev_priv->mem_freq = 1333;
668 dev_priv->mem_freq = 1600;
671 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
673 dev_priv->mem_freq = 0;
677 dev_priv->ips.r_t = dev_priv->mem_freq;
679 switch (csipll & 0x3ff) {
681 dev_priv->fsb_freq = 3200;
684 dev_priv->fsb_freq = 3733;
687 dev_priv->fsb_freq = 4266;
690 dev_priv->fsb_freq = 4800;
693 dev_priv->fsb_freq = 5333;
696 dev_priv->fsb_freq = 5866;
699 dev_priv->fsb_freq = 6400;
702 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
704 dev_priv->fsb_freq = 0;
708 if (dev_priv->fsb_freq == 3200) {
709 dev_priv->ips.c_m = 0;
710 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
711 dev_priv->ips.c_m = 1;
713 dev_priv->ips.c_m = 2;
717 static const struct cxsr_latency cxsr_latency_table[] = {
718 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
719 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
720 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
721 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
722 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
724 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
725 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
726 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
727 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
728 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
730 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
731 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
732 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
733 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
734 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
736 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
737 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
738 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
739 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
740 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
742 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
743 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
744 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
745 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
746 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
748 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
749 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
750 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
751 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
752 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
755 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
760 const struct cxsr_latency *latency;
763 if (fsb == 0 || mem == 0)
766 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
767 latency = &cxsr_latency_table[i];
768 if (is_desktop == latency->is_desktop &&
769 is_ddr3 == latency->is_ddr3 &&
770 fsb == latency->fsb_freq && mem == latency->mem_freq)
774 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
779 static void pineview_disable_cxsr(struct drm_device *dev)
781 struct drm_i915_private *dev_priv = dev->dev_private;
783 /* deactivate cxsr */
784 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
788 * Latency for FIFO fetches is dependent on several factors:
789 * - memory configuration (speed, channels)
791 * - current MCH state
792 * It can be fairly high in some situations, so here we assume a fairly
793 * pessimal value. It's a tradeoff between extra memory fetches (if we
794 * set this value too high, the FIFO will fetch frequently to stay full)
795 * and power consumption (set it too low to save power and we might see
796 * FIFO underruns and display "flicker").
798 * A value of 5us seems to be a good balance; safe for very low end
799 * platforms but not overly aggressive on lower latency configs.
801 static const int latency_ns = 5000;
803 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 uint32_t dsparb = I915_READ(DSPARB);
809 size = dsparb & 0x7f;
811 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
819 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
825 size = dsparb & 0x1ff;
827 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
828 size >>= 1; /* Convert to cachelines */
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
836 static int i845_get_fifo_size(struct drm_device *dev, int plane)
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
842 size = dsparb & 0x7f;
843 size >>= 2; /* Convert to cachelines */
845 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 static int i830_get_fifo_size(struct drm_device *dev, int plane)
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 uint32_t dsparb = I915_READ(DSPARB);
858 size = dsparb & 0x7f;
859 size >>= 1; /* Convert to cachelines */
861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
862 plane ? "B" : "A", size);
867 /* Pineview has different values for various configs */
868 static const struct intel_watermark_params pineview_display_wm = {
869 PINEVIEW_DISPLAY_FIFO,
873 PINEVIEW_FIFO_LINE_SIZE
875 static const struct intel_watermark_params pineview_display_hplloff_wm = {
876 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_DFT_HPLLOFF_WM,
880 PINEVIEW_FIFO_LINE_SIZE
882 static const struct intel_watermark_params pineview_cursor_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE,
889 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
890 PINEVIEW_CURSOR_FIFO,
891 PINEVIEW_CURSOR_MAX_WM,
892 PINEVIEW_CURSOR_DFT_WM,
893 PINEVIEW_CURSOR_GUARD_WM,
894 PINEVIEW_FIFO_LINE_SIZE
896 static const struct intel_watermark_params g4x_wm_info = {
903 static const struct intel_watermark_params g4x_cursor_wm_info = {
910 static const struct intel_watermark_params valleyview_wm_info = {
911 VALLEYVIEW_FIFO_SIZE,
917 static const struct intel_watermark_params valleyview_cursor_wm_info = {
919 VALLEYVIEW_CURSOR_MAX_WM,
924 static const struct intel_watermark_params i965_cursor_wm_info = {
931 static const struct intel_watermark_params i945_wm_info = {
938 static const struct intel_watermark_params i915_wm_info = {
945 static const struct intel_watermark_params i855_wm_info = {
952 static const struct intel_watermark_params i830_wm_info = {
960 static const struct intel_watermark_params ironlake_display_wm_info = {
967 static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 static const struct intel_watermark_params ironlake_display_srwm_info = {
976 ILK_DISPLAY_MAX_SRWM,
977 ILK_DISPLAY_DFT_SRWM,
981 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
989 static const struct intel_watermark_params sandybridge_display_wm_info = {
996 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004 SNB_DISPLAY_SR_FIFO,
1005 SNB_DISPLAY_MAX_SRWM,
1006 SNB_DISPLAY_DFT_SRWM,
1010 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1012 SNB_CURSOR_MAX_SRWM,
1013 SNB_CURSOR_DFT_SRWM,
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1037 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1041 unsigned long latency_ns)
1043 long entries_required, wm_size;
1046 * Note: we need to make sure we don't overflow for various clock &
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1065 wm_size = wm->default_wm;
1069 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1071 struct drm_crtc *crtc, *enabled = NULL;
1073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1074 if (intel_crtc_active(crtc)) {
1084 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1086 struct drm_device *dev = unused_crtc->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 pineview_disable_cxsr(dev);
1101 crtc = single_enabled_crtc(dev);
1103 const struct drm_display_mode *adjusted_mode;
1104 int pixel_size = crtc->fb->bits_per_pixel / 8;
1107 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108 clock = adjusted_mode->crtc_clock;
1111 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->display_sr);
1114 reg = I915_READ(DSPFW1);
1115 reg &= ~DSPFW_SR_MASK;
1116 reg |= wm << DSPFW_SR_SHIFT;
1117 I915_WRITE(DSPFW1, reg);
1118 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1121 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->cursor_sr);
1124 reg = I915_READ(DSPFW3);
1125 reg &= ~DSPFW_CURSOR_SR_MASK;
1126 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127 I915_WRITE(DSPFW3, reg);
1129 /* Display HPLL off SR */
1130 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131 pineview_display_hplloff_wm.fifo_size,
1132 pixel_size, latency->display_hpll_disable);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_HPLL_SR_MASK;
1135 reg |= wm & DSPFW_HPLL_SR_MASK;
1136 I915_WRITE(DSPFW3, reg);
1138 /* cursor HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->cursor_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1150 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 pineview_disable_cxsr(dev);
1154 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1158 static bool g4x_compute_wm0(struct drm_device *dev,
1160 const struct intel_watermark_params *display,
1161 int display_latency_ns,
1162 const struct intel_watermark_params *cursor,
1163 int cursor_latency_ns,
1167 struct drm_crtc *crtc;
1168 const struct drm_display_mode *adjusted_mode;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1173 crtc = intel_get_crtc_for_plane(dev, plane);
1174 if (!intel_crtc_active(crtc)) {
1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1180 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1181 clock = adjusted_mode->crtc_clock;
1182 htotal = adjusted_mode->htotal;
1183 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1184 pixel_size = crtc->fb->bits_per_pixel / 8;
1186 /* Use the small buffer method to calculate plane watermark */
1187 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1190 entries += tlb_miss;
1191 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192 *plane_wm = entries + display->guard_size;
1193 if (*plane_wm > (int)display->max_wm)
1194 *plane_wm = display->max_wm;
1196 /* Use the large buffer method to calculate cursor watermark */
1197 line_time_us = ((htotal * 1000) / clock);
1198 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199 entries = line_count * 64 * pixel_size;
1200 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1202 entries += tlb_miss;
1203 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 *cursor_wm = entries + cursor->guard_size;
1205 if (*cursor_wm > (int)cursor->max_wm)
1206 *cursor_wm = (int)cursor->max_wm;
1212 * Check the wm result.
1214 * If any calculated watermark values is larger than the maximum value that
1215 * can be programmed into the associated watermark register, that watermark
1218 static bool g4x_check_srwm(struct drm_device *dev,
1219 int display_wm, int cursor_wm,
1220 const struct intel_watermark_params *display,
1221 const struct intel_watermark_params *cursor)
1223 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224 display_wm, cursor_wm);
1226 if (display_wm > display->max_wm) {
1227 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228 display_wm, display->max_wm);
1232 if (cursor_wm > cursor->max_wm) {
1233 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234 cursor_wm, cursor->max_wm);
1238 if (!(display_wm || cursor_wm)) {
1239 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1246 static bool g4x_compute_srwm(struct drm_device *dev,
1249 const struct intel_watermark_params *display,
1250 const struct intel_watermark_params *cursor,
1251 int *display_wm, int *cursor_wm)
1253 struct drm_crtc *crtc;
1254 const struct drm_display_mode *adjusted_mode;
1255 int hdisplay, htotal, pixel_size, clock;
1256 unsigned long line_time_us;
1257 int line_count, line_size;
1262 *display_wm = *cursor_wm = 0;
1266 crtc = intel_get_crtc_for_plane(dev, plane);
1267 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1268 clock = adjusted_mode->crtc_clock;
1269 htotal = adjusted_mode->htotal;
1270 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1271 pixel_size = crtc->fb->bits_per_pixel / 8;
1273 line_time_us = (htotal * 1000) / clock;
1274 line_count = (latency_ns / line_time_us + 1000) / 1000;
1275 line_size = hdisplay * pixel_size;
1277 /* Use the minimum of the small and large buffer method for primary */
1278 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279 large = line_count * line_size;
1281 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282 *display_wm = entries + display->guard_size;
1284 /* calculate the self-refresh watermark for display cursor */
1285 entries = line_count * pixel_size * 64;
1286 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287 *cursor_wm = entries + cursor->guard_size;
1289 return g4x_check_srwm(dev,
1290 *display_wm, *cursor_wm,
1294 static bool vlv_compute_drain_latency(struct drm_device *dev,
1296 int *plane_prec_mult,
1298 int *cursor_prec_mult,
1301 struct drm_crtc *crtc;
1302 int clock, pixel_size;
1305 crtc = intel_get_crtc_for_plane(dev, plane);
1306 if (!intel_crtc_active(crtc))
1309 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1310 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1312 entries = (clock / 1000) * pixel_size;
1313 *plane_prec_mult = (entries > 256) ?
1314 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1318 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1319 *cursor_prec_mult = (entries > 256) ?
1320 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1327 * Update drain latency registers of memory arbiter
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1334 static void vlv_update_drain_latency(struct drm_device *dev)
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1342 /* For plane A, Cursor A */
1343 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344 &cursor_prec_mult, &cursora_dl)) {
1345 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1350 I915_WRITE(VLV_DDL1, cursora_prec |
1351 (cursora_dl << DDL_CURSORA_SHIFT) |
1352 planea_prec | planea_dl);
1355 /* For plane B, Cursor B */
1356 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357 &cursor_prec_mult, &cursorb_dl)) {
1358 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1363 I915_WRITE(VLV_DDL2, cursorb_prec |
1364 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365 planeb_prec | planeb_dl);
1369 #define single_plane_enabled(mask) is_power_of_2(mask)
1371 static void valleyview_update_wm(struct drm_crtc *crtc)
1373 struct drm_device *dev = crtc->dev;
1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 int ignore_plane_sr, ignore_cursor_sr;
1379 unsigned int enabled = 0;
1381 vlv_update_drain_latency(dev);
1383 if (g4x_compute_wm0(dev, PIPE_A,
1384 &valleyview_wm_info, latency_ns,
1385 &valleyview_cursor_wm_info, latency_ns,
1386 &planea_wm, &cursora_wm))
1387 enabled |= 1 << PIPE_A;
1389 if (g4x_compute_wm0(dev, PIPE_B,
1390 &valleyview_wm_info, latency_ns,
1391 &valleyview_cursor_wm_info, latency_ns,
1392 &planeb_wm, &cursorb_wm))
1393 enabled |= 1 << PIPE_B;
1395 if (single_plane_enabled(enabled) &&
1396 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 &valleyview_wm_info,
1399 &valleyview_cursor_wm_info,
1400 &plane_sr, &ignore_cursor_sr) &&
1401 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 &valleyview_wm_info,
1404 &valleyview_cursor_wm_info,
1405 &ignore_plane_sr, &cursor_sr)) {
1406 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1408 I915_WRITE(FW_BLC_SELF_VLV,
1409 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1410 plane_sr = cursor_sr = 0;
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414 planea_wm, cursora_wm,
1415 planeb_wm, cursorb_wm,
1416 plane_sr, cursor_sr);
1419 (plane_sr << DSPFW_SR_SHIFT) |
1420 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1425 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1431 static void g4x_update_wm(struct drm_crtc *crtc)
1433 struct drm_device *dev = crtc->dev;
1434 static const int sr_latency_ns = 12000;
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437 int plane_sr, cursor_sr;
1438 unsigned int enabled = 0;
1440 if (g4x_compute_wm0(dev, PIPE_A,
1441 &g4x_wm_info, latency_ns,
1442 &g4x_cursor_wm_info, latency_ns,
1443 &planea_wm, &cursora_wm))
1444 enabled |= 1 << PIPE_A;
1446 if (g4x_compute_wm0(dev, PIPE_B,
1447 &g4x_wm_info, latency_ns,
1448 &g4x_cursor_wm_info, latency_ns,
1449 &planeb_wm, &cursorb_wm))
1450 enabled |= 1 << PIPE_B;
1452 if (single_plane_enabled(enabled) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1456 &g4x_cursor_wm_info,
1457 &plane_sr, &cursor_sr)) {
1458 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1460 I915_WRITE(FW_BLC_SELF,
1461 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1462 plane_sr = cursor_sr = 0;
1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466 planea_wm, cursora_wm,
1467 planeb_wm, cursorb_wm,
1468 plane_sr, cursor_sr);
1471 (plane_sr << DSPFW_SR_SHIFT) |
1472 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1476 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1477 (cursora_wm << DSPFW_CURSORA_SHIFT));
1478 /* HPLL off in SR has some issues on G4x... disable it */
1480 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1481 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1484 static void i965_update_wm(struct drm_crtc *unused_crtc)
1486 struct drm_device *dev = unused_crtc->dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 struct drm_crtc *crtc;
1492 /* Calc sr entries for one plane configs */
1493 crtc = single_enabled_crtc(dev);
1495 /* self-refresh has much higher latency */
1496 static const int sr_latency_ns = 12000;
1497 const struct drm_display_mode *adjusted_mode =
1498 &to_intel_crtc(crtc)->config.adjusted_mode;
1499 int clock = adjusted_mode->crtc_clock;
1500 int htotal = adjusted_mode->htotal;
1501 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1502 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503 unsigned long line_time_us;
1506 line_time_us = ((htotal * 1000) / clock);
1508 /* Use ns/us then divide to preserve precision */
1509 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510 pixel_size * hdisplay;
1511 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512 srwm = I965_FIFO_SIZE - entries;
1516 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 entries = DIV_ROUND_UP(entries,
1522 i965_cursor_wm_info.cacheline_size);
1523 cursor_sr = i965_cursor_wm_info.fifo_size -
1524 (entries + i965_cursor_wm_info.guard_size);
1526 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527 cursor_sr = i965_cursor_wm_info.max_wm;
1529 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530 "cursor %d\n", srwm, cursor_sr);
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1535 /* Turn off self refresh if both pipes are enabled */
1536 if (IS_CRESTLINE(dev))
1537 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1544 /* 965 has limitations... */
1545 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546 (8 << 16) | (8 << 8) | (8 << 0));
1547 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548 /* update cursor SR watermark */
1549 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1552 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1554 struct drm_device *dev = unused_crtc->dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 const struct intel_watermark_params *wm_info;
1561 int planea_wm, planeb_wm;
1562 struct drm_crtc *crtc, *enabled = NULL;
1565 wm_info = &i945_wm_info;
1566 else if (!IS_GEN2(dev))
1567 wm_info = &i915_wm_info;
1569 wm_info = &i855_wm_info;
1571 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572 crtc = intel_get_crtc_for_plane(dev, 0);
1573 if (intel_crtc_active(crtc)) {
1574 const struct drm_display_mode *adjusted_mode;
1575 int cpp = crtc->fb->bits_per_pixel / 8;
1579 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1581 wm_info, fifo_size, cpp,
1585 planea_wm = fifo_size - wm_info->guard_size;
1587 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588 crtc = intel_get_crtc_for_plane(dev, 1);
1589 if (intel_crtc_active(crtc)) {
1590 const struct drm_display_mode *adjusted_mode;
1591 int cpp = crtc->fb->bits_per_pixel / 8;
1595 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1597 wm_info, fifo_size, cpp,
1599 if (enabled == NULL)
1604 planeb_wm = fifo_size - wm_info->guard_size;
1606 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609 * Overlay gets an aggressive default since video jitter is bad.
1613 /* Play safe and disable self-refresh before adjusting watermarks. */
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616 else if (IS_I915GM(dev))
1617 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1619 /* Calc sr entries for one plane configs */
1620 if (HAS_FW_BLC(dev) && enabled) {
1621 /* self-refresh has much higher latency */
1622 static const int sr_latency_ns = 6000;
1623 const struct drm_display_mode *adjusted_mode =
1624 &to_intel_crtc(enabled)->config.adjusted_mode;
1625 int clock = adjusted_mode->crtc_clock;
1626 int htotal = adjusted_mode->htotal;
1627 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1628 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629 unsigned long line_time_us;
1632 line_time_us = (htotal * 1000) / clock;
1634 /* Use ns/us then divide to preserve precision */
1635 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636 pixel_size * hdisplay;
1637 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639 srwm = wm_info->fifo_size - entries;
1643 if (IS_I945G(dev) || IS_I945GM(dev))
1644 I915_WRITE(FW_BLC_SELF,
1645 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646 else if (IS_I915GM(dev))
1647 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1650 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651 planea_wm, planeb_wm, cwm, srwm);
1653 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654 fwater_hi = (cwm & 0x1f);
1656 /* Set request length to 8 cachelines per fetch */
1657 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658 fwater_hi = fwater_hi | (1 << 8);
1660 I915_WRITE(FW_BLC, fwater_lo);
1661 I915_WRITE(FW_BLC2, fwater_hi);
1663 if (HAS_FW_BLC(dev)) {
1665 if (IS_I945G(dev) || IS_I945GM(dev))
1666 I915_WRITE(FW_BLC_SELF,
1667 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668 else if (IS_I915GM(dev))
1669 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670 DRM_DEBUG_KMS("memory self refresh enabled\n");
1672 DRM_DEBUG_KMS("memory self refresh disabled\n");
1676 static void i830_update_wm(struct drm_crtc *unused_crtc)
1678 struct drm_device *dev = unused_crtc->dev;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
1681 const struct drm_display_mode *adjusted_mode;
1685 crtc = single_enabled_crtc(dev);
1689 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1692 dev_priv->display.get_fifo_size(dev, 0),
1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1699 I915_WRITE(FW_BLC, fwater_lo);
1703 * Check the wm result.
1705 * If any calculated watermark values is larger than the maximum value that
1706 * can be programmed into the associated watermark register, that watermark
1709 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710 int fbc_wm, int display_wm, int cursor_wm,
1711 const struct intel_watermark_params *display,
1712 const struct intel_watermark_params *cursor)
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1716 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1719 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721 fbc_wm, SNB_FBC_MAX_SRWM, level);
1723 /* fbc has it's own way to disable FBC WM */
1724 I915_WRITE(DISP_ARB_CTL,
1725 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1727 } else if (INTEL_INFO(dev)->gen >= 6) {
1728 /* enable FBC WM (except on ILK, where it must remain off) */
1729 I915_WRITE(DISP_ARB_CTL,
1730 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1733 if (display_wm > display->max_wm) {
1734 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1739 if (cursor_wm > cursor->max_wm) {
1740 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1745 if (!(fbc_wm || display_wm || cursor_wm)) {
1746 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1754 * Compute watermark values of WM[1-3],
1756 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1758 const struct intel_watermark_params *display,
1759 const struct intel_watermark_params *cursor,
1760 int *fbc_wm, int *display_wm, int *cursor_wm)
1762 struct drm_crtc *crtc;
1763 const struct drm_display_mode *adjusted_mode;
1764 unsigned long line_time_us;
1765 int hdisplay, htotal, pixel_size, clock;
1766 int line_count, line_size;
1771 *fbc_wm = *display_wm = *cursor_wm = 0;
1775 crtc = intel_get_crtc_for_plane(dev, plane);
1776 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1777 clock = adjusted_mode->crtc_clock;
1778 htotal = adjusted_mode->htotal;
1779 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1780 pixel_size = crtc->fb->bits_per_pixel / 8;
1782 line_time_us = (htotal * 1000) / clock;
1783 line_count = (latency_ns / line_time_us + 1000) / 1000;
1784 line_size = hdisplay * pixel_size;
1786 /* Use the minimum of the small and large buffer method for primary */
1787 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788 large = line_count * line_size;
1790 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791 *display_wm = entries + display->guard_size;
1795 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1797 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1799 /* calculate the self-refresh watermark for display cursor */
1800 entries = line_count * pixel_size * 64;
1801 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802 *cursor_wm = entries + cursor->guard_size;
1804 return ironlake_check_srwm(dev, level,
1805 *fbc_wm, *display_wm, *cursor_wm,
1809 static void ironlake_update_wm(struct drm_crtc *crtc)
1811 struct drm_device *dev = crtc->dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 int fbc_wm, plane_wm, cursor_wm;
1814 unsigned int enabled;
1817 if (g4x_compute_wm0(dev, PIPE_A,
1818 &ironlake_display_wm_info,
1819 dev_priv->wm.pri_latency[0] * 100,
1820 &ironlake_cursor_wm_info,
1821 dev_priv->wm.cur_latency[0] * 100,
1822 &plane_wm, &cursor_wm)) {
1823 I915_WRITE(WM0_PIPEA_ILK,
1824 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826 " plane %d, " "cursor: %d\n",
1827 plane_wm, cursor_wm);
1828 enabled |= 1 << PIPE_A;
1831 if (g4x_compute_wm0(dev, PIPE_B,
1832 &ironlake_display_wm_info,
1833 dev_priv->wm.pri_latency[0] * 100,
1834 &ironlake_cursor_wm_info,
1835 dev_priv->wm.cur_latency[0] * 100,
1836 &plane_wm, &cursor_wm)) {
1837 I915_WRITE(WM0_PIPEB_ILK,
1838 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840 " plane %d, cursor: %d\n",
1841 plane_wm, cursor_wm);
1842 enabled |= 1 << PIPE_B;
1846 * Calculate and update the self-refresh watermark only when one
1847 * display plane is used.
1849 I915_WRITE(WM3_LP_ILK, 0);
1850 I915_WRITE(WM2_LP_ILK, 0);
1851 I915_WRITE(WM1_LP_ILK, 0);
1853 if (!single_plane_enabled(enabled))
1855 enabled = ffs(enabled) - 1;
1858 if (!ironlake_compute_srwm(dev, 1, enabled,
1859 dev_priv->wm.pri_latency[1] * 500,
1860 &ironlake_display_srwm_info,
1861 &ironlake_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1865 I915_WRITE(WM1_LP_ILK,
1867 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1873 if (!ironlake_compute_srwm(dev, 2, enabled,
1874 dev_priv->wm.pri_latency[2] * 500,
1875 &ironlake_display_srwm_info,
1876 &ironlake_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1880 I915_WRITE(WM2_LP_ILK,
1882 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1888 * WM3 is unsupported on ILK, probably because we don't have latency
1889 * data for that power state
1893 static void sandybridge_update_wm(struct drm_crtc *crtc)
1895 struct drm_device *dev = crtc->dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1897 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1899 int fbc_wm, plane_wm, cursor_wm;
1900 unsigned int enabled;
1903 if (g4x_compute_wm0(dev, PIPE_A,
1904 &sandybridge_display_wm_info, latency,
1905 &sandybridge_cursor_wm_info, latency,
1906 &plane_wm, &cursor_wm)) {
1907 val = I915_READ(WM0_PIPEA_ILK);
1908 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909 I915_WRITE(WM0_PIPEA_ILK, val |
1910 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912 " plane %d, " "cursor: %d\n",
1913 plane_wm, cursor_wm);
1914 enabled |= 1 << PIPE_A;
1917 if (g4x_compute_wm0(dev, PIPE_B,
1918 &sandybridge_display_wm_info, latency,
1919 &sandybridge_cursor_wm_info, latency,
1920 &plane_wm, &cursor_wm)) {
1921 val = I915_READ(WM0_PIPEB_ILK);
1922 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923 I915_WRITE(WM0_PIPEB_ILK, val |
1924 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926 " plane %d, cursor: %d\n",
1927 plane_wm, cursor_wm);
1928 enabled |= 1 << PIPE_B;
1932 * Calculate and update the self-refresh watermark only when one
1933 * display plane is used.
1935 * SNB support 3 levels of watermark.
1937 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938 * and disabled in the descending order
1941 I915_WRITE(WM3_LP_ILK, 0);
1942 I915_WRITE(WM2_LP_ILK, 0);
1943 I915_WRITE(WM1_LP_ILK, 0);
1945 if (!single_plane_enabled(enabled) ||
1946 dev_priv->sprite_scaling_enabled)
1948 enabled = ffs(enabled) - 1;
1951 if (!ironlake_compute_srwm(dev, 1, enabled,
1952 dev_priv->wm.pri_latency[1] * 500,
1953 &sandybridge_display_srwm_info,
1954 &sandybridge_cursor_srwm_info,
1955 &fbc_wm, &plane_wm, &cursor_wm))
1958 I915_WRITE(WM1_LP_ILK,
1960 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1961 (fbc_wm << WM1_LP_FBC_SHIFT) |
1962 (plane_wm << WM1_LP_SR_SHIFT) |
1966 if (!ironlake_compute_srwm(dev, 2, enabled,
1967 dev_priv->wm.pri_latency[2] * 500,
1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1973 I915_WRITE(WM2_LP_ILK,
1975 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1981 if (!ironlake_compute_srwm(dev, 3, enabled,
1982 dev_priv->wm.pri_latency[3] * 500,
1983 &sandybridge_display_srwm_info,
1984 &sandybridge_cursor_srwm_info,
1985 &fbc_wm, &plane_wm, &cursor_wm))
1988 I915_WRITE(WM3_LP_ILK,
1990 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1991 (fbc_wm << WM1_LP_FBC_SHIFT) |
1992 (plane_wm << WM1_LP_SR_SHIFT) |
1996 static void ivybridge_update_wm(struct drm_crtc *crtc)
1998 struct drm_device *dev = crtc->dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2002 int fbc_wm, plane_wm, cursor_wm;
2003 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004 unsigned int enabled;
2007 if (g4x_compute_wm0(dev, PIPE_A,
2008 &sandybridge_display_wm_info, latency,
2009 &sandybridge_cursor_wm_info, latency,
2010 &plane_wm, &cursor_wm)) {
2011 val = I915_READ(WM0_PIPEA_ILK);
2012 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013 I915_WRITE(WM0_PIPEA_ILK, val |
2014 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016 " plane %d, " "cursor: %d\n",
2017 plane_wm, cursor_wm);
2018 enabled |= 1 << PIPE_A;
2021 if (g4x_compute_wm0(dev, PIPE_B,
2022 &sandybridge_display_wm_info, latency,
2023 &sandybridge_cursor_wm_info, latency,
2024 &plane_wm, &cursor_wm)) {
2025 val = I915_READ(WM0_PIPEB_ILK);
2026 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027 I915_WRITE(WM0_PIPEB_ILK, val |
2028 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030 " plane %d, cursor: %d\n",
2031 plane_wm, cursor_wm);
2032 enabled |= 1 << PIPE_B;
2035 if (g4x_compute_wm0(dev, PIPE_C,
2036 &sandybridge_display_wm_info, latency,
2037 &sandybridge_cursor_wm_info, latency,
2038 &plane_wm, &cursor_wm)) {
2039 val = I915_READ(WM0_PIPEC_IVB);
2040 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041 I915_WRITE(WM0_PIPEC_IVB, val |
2042 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044 " plane %d, cursor: %d\n",
2045 plane_wm, cursor_wm);
2046 enabled |= 1 << PIPE_C;
2050 * Calculate and update the self-refresh watermark only when one
2051 * display plane is used.
2053 * SNB support 3 levels of watermark.
2055 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056 * and disabled in the descending order
2059 I915_WRITE(WM3_LP_ILK, 0);
2060 I915_WRITE(WM2_LP_ILK, 0);
2061 I915_WRITE(WM1_LP_ILK, 0);
2063 if (!single_plane_enabled(enabled) ||
2064 dev_priv->sprite_scaling_enabled)
2066 enabled = ffs(enabled) - 1;
2069 if (!ironlake_compute_srwm(dev, 1, enabled,
2070 dev_priv->wm.pri_latency[1] * 500,
2071 &sandybridge_display_srwm_info,
2072 &sandybridge_cursor_srwm_info,
2073 &fbc_wm, &plane_wm, &cursor_wm))
2076 I915_WRITE(WM1_LP_ILK,
2078 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2079 (fbc_wm << WM1_LP_FBC_SHIFT) |
2080 (plane_wm << WM1_LP_SR_SHIFT) |
2084 if (!ironlake_compute_srwm(dev, 2, enabled,
2085 dev_priv->wm.pri_latency[2] * 500,
2086 &sandybridge_display_srwm_info,
2087 &sandybridge_cursor_srwm_info,
2088 &fbc_wm, &plane_wm, &cursor_wm))
2091 I915_WRITE(WM2_LP_ILK,
2093 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2094 (fbc_wm << WM1_LP_FBC_SHIFT) |
2095 (plane_wm << WM1_LP_SR_SHIFT) |
2098 /* WM3, note we have to correct the cursor latency */
2099 if (!ironlake_compute_srwm(dev, 3, enabled,
2100 dev_priv->wm.pri_latency[3] * 500,
2101 &sandybridge_display_srwm_info,
2102 &sandybridge_cursor_srwm_info,
2103 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104 !ironlake_compute_srwm(dev, 3, enabled,
2105 dev_priv->wm.cur_latency[3] * 500,
2106 &sandybridge_display_srwm_info,
2107 &sandybridge_cursor_srwm_info,
2108 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2111 I915_WRITE(WM3_LP_ILK,
2113 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2114 (fbc_wm << WM1_LP_FBC_SHIFT) |
2115 (plane_wm << WM1_LP_SR_SHIFT) |
2119 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120 struct drm_crtc *crtc)
2122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123 uint32_t pixel_rate;
2125 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2127 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128 * adjust the pixel_rate here. */
2130 if (intel_crtc->config.pch_pfit.enabled) {
2131 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2132 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2134 pipe_w = intel_crtc->config.pipe_src_w;
2135 pipe_h = intel_crtc->config.pipe_src_h;
2136 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137 pfit_h = pfit_size & 0xFFFF;
2138 if (pipe_w < pfit_w)
2140 if (pipe_h < pfit_h)
2143 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2150 /* latency must be in 0.1us units. */
2151 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2156 if (WARN(latency == 0, "Latency value missing\n"))
2159 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2165 /* latency must be in 0.1us units. */
2166 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2167 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2172 if (WARN(latency == 0, "Latency value missing\n"))
2175 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177 ret = DIV_ROUND_UP(ret, 64) + 2;
2181 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2182 uint8_t bytes_per_pixel)
2184 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2187 struct hsw_pipe_wm_parameters {
2189 uint32_t pipe_htotal;
2190 uint32_t pixel_rate;
2191 struct intel_plane_wm_parameters pri;
2192 struct intel_plane_wm_parameters spr;
2193 struct intel_plane_wm_parameters cur;
2196 struct hsw_wm_maximums {
2203 struct hsw_wm_values {
2204 uint32_t wm_pipe[3];
2206 uint32_t wm_lp_spr[3];
2207 uint32_t wm_linetime[3];
2211 /* used in computing the new watermarks state */
2212 struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
2216 bool fbc_wm_enabled;
2220 * For both WM_PIPE and WM_LP.
2221 * mem_value must be in 0.1us units.
2223 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2227 uint32_t method1, method2;
2229 if (!params->active || !params->pri.enabled)
2232 method1 = ilk_wm_method1(params->pixel_rate,
2233 params->pri.bytes_per_pixel,
2239 method2 = ilk_wm_method2(params->pixel_rate,
2240 params->pipe_htotal,
2241 params->pri.horiz_pixels,
2242 params->pri.bytes_per_pixel,
2245 return min(method1, method2);
2249 * For both WM_PIPE and WM_LP.
2250 * mem_value must be in 0.1us units.
2252 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2255 uint32_t method1, method2;
2257 if (!params->active || !params->spr.enabled)
2260 method1 = ilk_wm_method1(params->pixel_rate,
2261 params->spr.bytes_per_pixel,
2263 method2 = ilk_wm_method2(params->pixel_rate,
2264 params->pipe_htotal,
2265 params->spr.horiz_pixels,
2266 params->spr.bytes_per_pixel,
2268 return min(method1, method2);
2272 * For both WM_PIPE and WM_LP.
2273 * mem_value must be in 0.1us units.
2275 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2278 if (!params->active || !params->cur.enabled)
2281 return ilk_wm_method2(params->pixel_rate,
2282 params->pipe_htotal,
2283 params->cur.horiz_pixels,
2284 params->cur.bytes_per_pixel,
2288 /* Only for WM_LP. */
2289 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2292 if (!params->active || !params->pri.enabled)
2295 return ilk_wm_fbc(pri_val,
2296 params->pri.horiz_pixels,
2297 params->pri.bytes_per_pixel);
2300 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2302 if (INTEL_INFO(dev)->gen >= 7)
2308 /* Calculate the maximum primary/sprite plane watermark */
2309 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2311 const struct intel_wm_config *config,
2312 enum intel_ddb_partitioning ddb_partitioning,
2315 unsigned int fifo_size = ilk_display_fifo_size(dev);
2318 /* if sprites aren't enabled, sprites get nothing */
2319 if (is_sprite && !config->sprites_enabled)
2322 /* HSW allows LP1+ watermarks even with multiple pipes */
2323 if (level == 0 || config->num_pipes_active > 1) {
2324 fifo_size /= INTEL_INFO(dev)->num_pipes;
2327 * For some reason the non self refresh
2328 * FIFO size is only half of the self
2329 * refresh FIFO size on ILK/SNB.
2331 if (INTEL_INFO(dev)->gen <= 6)
2335 if (config->sprites_enabled) {
2336 /* level 0 is always calculated with 1:1 split */
2337 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2346 /* clamp to max that the registers can hold */
2347 if (INTEL_INFO(dev)->gen >= 7)
2348 /* IVB/HSW primary/sprite plane watermarks */
2349 max = level == 0 ? 127 : 1023;
2350 else if (!is_sprite)
2351 /* ILK/SNB primary plane watermarks */
2352 max = level == 0 ? 127 : 511;
2354 /* ILK/SNB sprite plane watermarks */
2355 max = level == 0 ? 63 : 255;
2357 return min(fifo_size, max);
2360 /* Calculate the maximum cursor plane watermark */
2361 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2363 const struct intel_wm_config *config)
2365 /* HSW LP1+ watermarks w/ multiple pipes */
2366 if (level > 0 && config->num_pipes_active > 1)
2369 /* otherwise just report max that registers can hold */
2370 if (INTEL_INFO(dev)->gen >= 7)
2371 return level == 0 ? 63 : 255;
2373 return level == 0 ? 31 : 63;
2376 /* Calculate the maximum FBC watermark */
2377 static unsigned int ilk_fbc_wm_max(void)
2379 /* max that registers can hold */
2383 static void ilk_wm_max(struct drm_device *dev,
2385 const struct intel_wm_config *config,
2386 enum intel_ddb_partitioning ddb_partitioning,
2387 struct hsw_wm_maximums *max)
2389 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2390 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2391 max->cur = ilk_cursor_wm_max(dev, level, config);
2392 max->fbc = ilk_fbc_wm_max();
2395 static bool ilk_check_wm(int level,
2396 const struct hsw_wm_maximums *max,
2397 struct intel_wm_level *result)
2401 /* already determined to be invalid? */
2402 if (!result->enable)
2405 result->enable = result->pri_val <= max->pri &&
2406 result->spr_val <= max->spr &&
2407 result->cur_val <= max->cur;
2409 ret = result->enable;
2412 * HACK until we can pre-compute everything,
2413 * and thus fail gracefully if LP0 watermarks
2416 if (level == 0 && !result->enable) {
2417 if (result->pri_val > max->pri)
2418 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2419 level, result->pri_val, max->pri);
2420 if (result->spr_val > max->spr)
2421 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2422 level, result->spr_val, max->spr);
2423 if (result->cur_val > max->cur)
2424 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2425 level, result->cur_val, max->cur);
2427 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2428 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2429 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2430 result->enable = true;
2433 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2438 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2440 const struct hsw_pipe_wm_parameters *p,
2441 struct intel_wm_level *result)
2443 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2444 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2445 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2447 /* WM1+ latency values stored in 0.5us units */
2454 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2455 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2456 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2457 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2458 result->enable = true;
2462 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2467 u32 linetime, ips_linetime;
2469 if (!intel_crtc_active(crtc))
2472 /* The WM are computed with base on how long it takes to fill a single
2473 * row at the given clock rate, multiplied by 8.
2475 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2476 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2477 intel_ddi_get_cdclk_freq(dev_priv));
2479 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2480 PIPE_WM_LINETIME_TIME(linetime);
2483 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2487 if (IS_HASWELL(dev)) {
2488 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2490 wm[0] = (sskpd >> 56) & 0xFF;
2492 wm[0] = sskpd & 0xF;
2493 wm[1] = (sskpd >> 4) & 0xFF;
2494 wm[2] = (sskpd >> 12) & 0xFF;
2495 wm[3] = (sskpd >> 20) & 0x1FF;
2496 wm[4] = (sskpd >> 32) & 0x1FF;
2497 } else if (INTEL_INFO(dev)->gen >= 6) {
2498 uint32_t sskpd = I915_READ(MCH_SSKPD);
2500 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2501 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2502 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2503 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2504 } else if (INTEL_INFO(dev)->gen >= 5) {
2505 uint32_t mltr = I915_READ(MLTR_ILK);
2507 /* ILK primary LP0 latency is 700 ns */
2509 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2510 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2514 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2516 /* ILK sprite LP0 latency is 1300 ns */
2517 if (INTEL_INFO(dev)->gen == 5)
2521 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2523 /* ILK cursor LP0 latency is 1300 ns */
2524 if (INTEL_INFO(dev)->gen == 5)
2527 /* WaDoubleCursorLP3Latency:ivb */
2528 if (IS_IVYBRIDGE(dev))
2532 static int ilk_wm_max_level(const struct drm_device *dev)
2534 /* how many WM levels are we expecting */
2535 if (IS_HASWELL(dev))
2537 else if (INTEL_INFO(dev)->gen >= 6)
2543 static void intel_print_wm_latency(struct drm_device *dev,
2545 const uint16_t wm[5])
2547 int level, max_level = ilk_wm_max_level(dev);
2549 for (level = 0; level <= max_level; level++) {
2550 unsigned int latency = wm[level];
2553 DRM_ERROR("%s WM%d latency not provided\n",
2558 /* WM1+ latency values in 0.5us units */
2562 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2563 name, level, wm[level],
2564 latency / 10, latency % 10);
2568 static void intel_setup_wm_latency(struct drm_device *dev)
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2572 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2574 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2575 sizeof(dev_priv->wm.pri_latency));
2576 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2577 sizeof(dev_priv->wm.pri_latency));
2579 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2580 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2582 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2583 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2584 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2587 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2588 struct hsw_pipe_wm_parameters *p,
2589 struct hsw_wm_maximums *lp_max_1_2,
2590 struct hsw_wm_maximums *lp_max_5_6)
2592 struct drm_device *dev = crtc->dev;
2593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2594 enum pipe pipe = intel_crtc->pipe;
2595 struct intel_wm_config config = {};
2596 struct drm_plane *plane;
2598 p->active = intel_crtc_active(crtc);
2600 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2601 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2602 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2603 p->cur.bytes_per_pixel = 4;
2604 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2605 p->cur.horiz_pixels = 64;
2606 /* TODO: for now, assume primary and cursor planes are always enabled. */
2607 p->pri.enabled = true;
2608 p->cur.enabled = true;
2611 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2612 config.num_pipes_active += intel_crtc_active(crtc);
2614 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2615 struct intel_plane *intel_plane = to_intel_plane(plane);
2617 if (intel_plane->pipe == pipe)
2618 p->spr = intel_plane->wm;
2620 config.sprites_enabled |= intel_plane->wm.enabled;
2621 config.sprites_scaled |= intel_plane->wm.scaled;
2624 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
2626 /* 5/6 split only in single pipe config on IVB+ */
2627 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2628 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
2630 *lp_max_5_6 = *lp_max_1_2;
2633 /* Compute new watermarks for the pipe */
2634 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2635 const struct hsw_pipe_wm_parameters *params,
2636 struct intel_pipe_wm *pipe_wm)
2638 struct drm_device *dev = crtc->dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 int level, max_level = ilk_wm_max_level(dev);
2641 /* LP0 watermark maximums depend on this pipe alone */
2642 struct intel_wm_config config = {
2643 .num_pipes_active = 1,
2644 .sprites_enabled = params->spr.enabled,
2645 .sprites_scaled = params->spr.scaled,
2647 struct hsw_wm_maximums max;
2649 /* LP0 watermarks always use 1/2 DDB partitioning */
2650 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2652 for (level = 0; level <= max_level; level++)
2653 ilk_compute_wm_level(dev_priv, level, params,
2654 &pipe_wm->wm[level]);
2656 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2658 /* At least LP0 must be valid */
2659 return ilk_check_wm(0, &max, &pipe_wm->wm[0]);
2663 * Merge the watermarks from all active pipes for a specific level.
2665 static void ilk_merge_wm_level(struct drm_device *dev,
2667 struct intel_wm_level *ret_wm)
2669 const struct intel_crtc *intel_crtc;
2671 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2672 const struct intel_wm_level *wm =
2673 &intel_crtc->wm.active.wm[level];
2678 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2679 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2680 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2681 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2684 ret_wm->enable = true;
2688 * Merge all low power watermarks for all active pipes.
2690 static void ilk_wm_merge(struct drm_device *dev,
2691 const struct hsw_wm_maximums *max,
2692 struct intel_pipe_wm *merged)
2694 int level, max_level = ilk_wm_max_level(dev);
2696 merged->fbc_wm_enabled = true;
2698 /* merge each WM1+ level */
2699 for (level = 1; level <= max_level; level++) {
2700 struct intel_wm_level *wm = &merged->wm[level];
2702 ilk_merge_wm_level(dev, level, wm);
2704 if (!ilk_check_wm(level, max, wm))
2708 * The spec says it is preferred to disable
2709 * FBC WMs instead of disabling a WM level.
2711 if (wm->fbc_val > max->fbc) {
2712 merged->fbc_wm_enabled = false;
2718 static void hsw_compute_wm_results(struct drm_device *dev,
2719 const struct hsw_wm_maximums *lp_maximums,
2720 struct hsw_wm_values *results)
2722 struct intel_crtc *intel_crtc;
2724 struct intel_pipe_wm merged = {};
2726 ilk_wm_merge(dev, lp_maximums, &merged);
2728 memset(results, 0, sizeof(*results));
2730 results->enable_fbc_wm = merged.fbc_wm_enabled;
2732 /* LP1+ register values */
2733 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2734 const struct intel_wm_level *r;
2736 level = wm_lp + (wm_lp >= 2 && merged.wm[4].enable);
2738 r = &merged.wm[level];
2742 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2746 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2749 /* LP0 register values */
2750 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2751 enum pipe pipe = intel_crtc->pipe;
2752 const struct intel_wm_level *r =
2753 &intel_crtc->wm.active.wm[0];
2755 if (WARN_ON(!r->enable))
2758 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2760 results->wm_pipe[pipe] =
2761 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2762 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2767 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2768 * case both are at the same level. Prefer r1 in case they're the same. */
2769 static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2770 struct hsw_wm_values *r2)
2772 int i, val_r1 = 0, val_r2 = 0;
2774 for (i = 0; i < 3; i++) {
2775 if (r1->wm_lp[i] & WM3_LP_EN)
2776 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2777 if (r2->wm_lp[i] & WM3_LP_EN)
2778 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2781 if (val_r1 == val_r2) {
2782 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2786 } else if (val_r1 > val_r2) {
2794 * The spec says we shouldn't write when we don't need, because every write
2795 * causes WMs to be re-evaluated, expending some power.
2797 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2798 struct hsw_wm_values *results,
2799 enum intel_ddb_partitioning partitioning)
2801 struct hsw_wm_values previous;
2803 enum intel_ddb_partitioning prev_partitioning;
2804 bool prev_enable_fbc_wm;
2806 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2807 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2808 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2809 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2810 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2811 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2812 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2813 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2814 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2815 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2816 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2817 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2819 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2820 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2822 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2824 if (memcmp(results->wm_pipe, previous.wm_pipe,
2825 sizeof(results->wm_pipe)) == 0 &&
2826 memcmp(results->wm_lp, previous.wm_lp,
2827 sizeof(results->wm_lp)) == 0 &&
2828 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2829 sizeof(results->wm_lp_spr)) == 0 &&
2830 memcmp(results->wm_linetime, previous.wm_linetime,
2831 sizeof(results->wm_linetime)) == 0 &&
2832 partitioning == prev_partitioning &&
2833 results->enable_fbc_wm == prev_enable_fbc_wm)
2836 if (previous.wm_lp[2] != 0)
2837 I915_WRITE(WM3_LP_ILK, 0);
2838 if (previous.wm_lp[1] != 0)
2839 I915_WRITE(WM2_LP_ILK, 0);
2840 if (previous.wm_lp[0] != 0)
2841 I915_WRITE(WM1_LP_ILK, 0);
2843 if (previous.wm_pipe[0] != results->wm_pipe[0])
2844 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2845 if (previous.wm_pipe[1] != results->wm_pipe[1])
2846 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2847 if (previous.wm_pipe[2] != results->wm_pipe[2])
2848 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2850 if (previous.wm_linetime[0] != results->wm_linetime[0])
2851 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2852 if (previous.wm_linetime[1] != results->wm_linetime[1])
2853 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2854 if (previous.wm_linetime[2] != results->wm_linetime[2])
2855 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2857 if (prev_partitioning != partitioning) {
2858 val = I915_READ(WM_MISC);
2859 if (partitioning == INTEL_DDB_PART_1_2)
2860 val &= ~WM_MISC_DATA_PARTITION_5_6;
2862 val |= WM_MISC_DATA_PARTITION_5_6;
2863 I915_WRITE(WM_MISC, val);
2866 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2867 val = I915_READ(DISP_ARB_CTL);
2868 if (results->enable_fbc_wm)
2869 val &= ~DISP_FBC_WM_DIS;
2871 val |= DISP_FBC_WM_DIS;
2872 I915_WRITE(DISP_ARB_CTL, val);
2875 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2876 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2877 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2878 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2879 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2880 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2882 if (results->wm_lp[0] != 0)
2883 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2884 if (results->wm_lp[1] != 0)
2885 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2886 if (results->wm_lp[2] != 0)
2887 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2890 static void haswell_update_wm(struct drm_crtc *crtc)
2892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893 struct drm_device *dev = crtc->dev;
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
2896 struct hsw_pipe_wm_parameters params = {};
2897 struct hsw_wm_values results_1_2, results_5_6, *best_results;
2898 enum intel_ddb_partitioning partitioning;
2899 struct intel_pipe_wm pipe_wm = {};
2901 hsw_compute_wm_parameters(crtc, ¶ms, &lp_max_1_2, &lp_max_5_6);
2903 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2905 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2908 intel_crtc->wm.active = pipe_wm;
2910 hsw_compute_wm_results(dev, &lp_max_1_2, &results_1_2);
2911 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2912 hsw_compute_wm_results(dev, &lp_max_5_6, &results_5_6);
2913 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2915 best_results = &results_1_2;
2918 partitioning = (best_results == &results_1_2) ?
2919 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2921 hsw_write_wm_values(dev_priv, best_results, partitioning);
2924 static void haswell_update_sprite_wm(struct drm_plane *plane,
2925 struct drm_crtc *crtc,
2926 uint32_t sprite_width, int pixel_size,
2927 bool enabled, bool scaled)
2929 struct intel_plane *intel_plane = to_intel_plane(plane);
2931 intel_plane->wm.enabled = enabled;
2932 intel_plane->wm.scaled = scaled;
2933 intel_plane->wm.horiz_pixels = sprite_width;
2934 intel_plane->wm.bytes_per_pixel = pixel_size;
2936 haswell_update_wm(crtc);
2940 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2941 uint32_t sprite_width, int pixel_size,
2942 const struct intel_watermark_params *display,
2943 int display_latency_ns, int *sprite_wm)
2945 struct drm_crtc *crtc;
2947 int entries, tlb_miss;
2949 crtc = intel_get_crtc_for_plane(dev, plane);
2950 if (!intel_crtc_active(crtc)) {
2951 *sprite_wm = display->guard_size;
2955 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2957 /* Use the small buffer method to calculate the sprite watermark */
2958 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2959 tlb_miss = display->fifo_size*display->cacheline_size -
2962 entries += tlb_miss;
2963 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2964 *sprite_wm = entries + display->guard_size;
2965 if (*sprite_wm > (int)display->max_wm)
2966 *sprite_wm = display->max_wm;
2972 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2973 uint32_t sprite_width, int pixel_size,
2974 const struct intel_watermark_params *display,
2975 int latency_ns, int *sprite_wm)
2977 struct drm_crtc *crtc;
2978 unsigned long line_time_us;
2980 int line_count, line_size;
2989 crtc = intel_get_crtc_for_plane(dev, plane);
2990 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2996 line_time_us = (sprite_width * 1000) / clock;
2997 if (!line_time_us) {
3002 line_count = (latency_ns / line_time_us + 1000) / 1000;
3003 line_size = sprite_width * pixel_size;
3005 /* Use the minimum of the small and large buffer method for primary */
3006 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3007 large = line_count * line_size;
3009 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3010 *sprite_wm = entries + display->guard_size;
3012 return *sprite_wm > 0x3ff ? false : true;
3015 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3016 struct drm_crtc *crtc,
3017 uint32_t sprite_width, int pixel_size,
3018 bool enabled, bool scaled)
3020 struct drm_device *dev = plane->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 int pipe = to_intel_plane(plane)->pipe;
3023 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
3033 reg = WM0_PIPEA_ILK;
3036 reg = WM0_PIPEB_ILK;
3039 reg = WM0_PIPEC_IVB;
3042 return; /* bad pipe */
3045 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3046 &sandybridge_display_wm_info,
3047 latency, &sprite_wm);
3049 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3054 val = I915_READ(reg);
3055 val &= ~WM0_PIPE_SPRITE_MASK;
3056 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3057 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3060 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3062 &sandybridge_display_srwm_info,
3063 dev_priv->wm.spr_latency[1] * 500,
3066 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3070 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3072 /* Only IVB has two more LP watermarks for sprite */
3073 if (!IS_IVYBRIDGE(dev))
3076 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3078 &sandybridge_display_srwm_info,
3079 dev_priv->wm.spr_latency[2] * 500,
3082 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3086 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3088 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3090 &sandybridge_display_srwm_info,
3091 dev_priv->wm.spr_latency[3] * 500,
3094 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3098 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3102 * intel_update_watermarks - update FIFO watermark values based on current modes
3104 * Calculate watermark values for the various WM regs based on current mode
3105 * and plane configuration.
3107 * There are several cases to deal with here:
3108 * - normal (i.e. non-self-refresh)
3109 * - self-refresh (SR) mode
3110 * - lines are large relative to FIFO size (buffer can hold up to 2)
3111 * - lines are small relative to FIFO size (buffer can hold more than 2
3112 * lines), so need to account for TLB latency
3114 * The normal calculation is:
3115 * watermark = dotclock * bytes per pixel * latency
3116 * where latency is platform & configuration dependent (we assume pessimal
3119 * The SR calculation is:
3120 * watermark = (trunc(latency/line time)+1) * surface width *
3123 * line time = htotal / dotclock
3124 * surface width = hdisplay for normal plane and 64 for cursor
3125 * and latency is assumed to be high, as above.
3127 * The final value programmed to the register should always be rounded up,
3128 * and include an extra 2 entries to account for clock crossings.
3130 * We don't use the sprite, so we can ignore that. And on Crestline we have
3131 * to set the non-SR watermarks to 8.
3133 void intel_update_watermarks(struct drm_crtc *crtc)
3135 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3137 if (dev_priv->display.update_wm)
3138 dev_priv->display.update_wm(crtc);
3141 void intel_update_sprite_watermarks(struct drm_plane *plane,
3142 struct drm_crtc *crtc,
3143 uint32_t sprite_width, int pixel_size,
3144 bool enabled, bool scaled)
3146 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3148 if (dev_priv->display.update_sprite_wm)
3149 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3150 pixel_size, enabled, scaled);
3153 static struct drm_i915_gem_object *
3154 intel_alloc_context_page(struct drm_device *dev)
3156 struct drm_i915_gem_object *ctx;
3159 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3161 ctx = i915_gem_alloc_object(dev, 4096);
3163 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3167 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3169 DRM_ERROR("failed to pin power context: %d\n", ret);
3173 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3175 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3182 i915_gem_object_unpin(ctx);
3184 drm_gem_object_unreference(&ctx->base);
3189 * Lock protecting IPS related data structures
3191 DEFINE_SPINLOCK(mchdev_lock);
3193 /* Global for IPS driver to get at the current i915 device. Protected by
3195 static struct drm_i915_private *i915_mch_dev;
3197 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3202 assert_spin_locked(&mchdev_lock);
3204 rgvswctl = I915_READ16(MEMSWCTL);
3205 if (rgvswctl & MEMCTL_CMD_STS) {
3206 DRM_DEBUG("gpu busy, RCS change rejected\n");
3207 return false; /* still busy with another command */
3210 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3211 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3212 I915_WRITE16(MEMSWCTL, rgvswctl);
3213 POSTING_READ16(MEMSWCTL);
3215 rgvswctl |= MEMCTL_CMD_STS;
3216 I915_WRITE16(MEMSWCTL, rgvswctl);
3221 static void ironlake_enable_drps(struct drm_device *dev)
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224 u32 rgvmodectl = I915_READ(MEMMODECTL);
3225 u8 fmax, fmin, fstart, vstart;
3227 spin_lock_irq(&mchdev_lock);
3229 /* Enable temp reporting */
3230 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3231 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3233 /* 100ms RC evaluation intervals */
3234 I915_WRITE(RCUPEI, 100000);
3235 I915_WRITE(RCDNEI, 100000);
3237 /* Set max/min thresholds to 90ms and 80ms respectively */
3238 I915_WRITE(RCBMAXAVG, 90000);
3239 I915_WRITE(RCBMINAVG, 80000);
3241 I915_WRITE(MEMIHYST, 1);
3243 /* Set up min, max, and cur for interrupt handling */
3244 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3245 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3246 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3247 MEMMODE_FSTART_SHIFT;
3249 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3252 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3253 dev_priv->ips.fstart = fstart;
3255 dev_priv->ips.max_delay = fstart;
3256 dev_priv->ips.min_delay = fmin;
3257 dev_priv->ips.cur_delay = fstart;
3259 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3260 fmax, fmin, fstart);
3262 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3265 * Interrupts will be enabled in ironlake_irq_postinstall
3268 I915_WRITE(VIDSTART, vstart);
3269 POSTING_READ(VIDSTART);
3271 rgvmodectl |= MEMMODE_SWMODE_EN;
3272 I915_WRITE(MEMMODECTL, rgvmodectl);
3274 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3275 DRM_ERROR("stuck trying to change perf mode\n");
3278 ironlake_set_drps(dev, fstart);
3280 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3282 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3283 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3284 getrawmonotonic(&dev_priv->ips.last_time2);
3286 spin_unlock_irq(&mchdev_lock);
3289 static void ironlake_disable_drps(struct drm_device *dev)
3291 struct drm_i915_private *dev_priv = dev->dev_private;
3294 spin_lock_irq(&mchdev_lock);
3296 rgvswctl = I915_READ16(MEMSWCTL);
3298 /* Ack interrupts, disable EFC interrupt */
3299 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3300 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3301 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3302 I915_WRITE(DEIIR, DE_PCU_EVENT);
3303 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3305 /* Go back to the starting frequency */
3306 ironlake_set_drps(dev, dev_priv->ips.fstart);
3308 rgvswctl |= MEMCTL_CMD_STS;
3309 I915_WRITE(MEMSWCTL, rgvswctl);
3312 spin_unlock_irq(&mchdev_lock);
3315 /* There's a funny hw issue where the hw returns all 0 when reading from
3316 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3317 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3318 * all limits and the gpu stuck at whatever frequency it is at atm).
3320 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3326 if (*val >= dev_priv->rps.max_delay)
3327 *val = dev_priv->rps.max_delay;
3328 limits |= dev_priv->rps.max_delay << 24;
3330 /* Only set the down limit when we've reached the lowest level to avoid
3331 * getting more interrupts, otherwise leave this clear. This prevents a
3332 * race in the hw when coming out of rc6: There's a tiny window where
3333 * the hw runs at the minimal clock before selecting the desired
3334 * frequency, if the down threshold expires in that window we will not
3335 * receive a down interrupt. */
3336 if (*val <= dev_priv->rps.min_delay) {
3337 *val = dev_priv->rps.min_delay;
3338 limits |= dev_priv->rps.min_delay << 16;
3344 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3348 new_power = dev_priv->rps.power;
3349 switch (dev_priv->rps.power) {
3351 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3352 new_power = BETWEEN;
3356 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3357 new_power = LOW_POWER;
3358 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3359 new_power = HIGH_POWER;
3363 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3364 new_power = BETWEEN;
3367 /* Max/min bins are special */
3368 if (val == dev_priv->rps.min_delay)
3369 new_power = LOW_POWER;
3370 if (val == dev_priv->rps.max_delay)
3371 new_power = HIGH_POWER;
3372 if (new_power == dev_priv->rps.power)
3375 /* Note the units here are not exactly 1us, but 1280ns. */
3376 switch (new_power) {
3378 /* Upclock if more than 95% busy over 16ms */
3379 I915_WRITE(GEN6_RP_UP_EI, 12500);
3380 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3382 /* Downclock if less than 85% busy over 32ms */
3383 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3384 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3386 I915_WRITE(GEN6_RP_CONTROL,
3387 GEN6_RP_MEDIA_TURBO |
3388 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3389 GEN6_RP_MEDIA_IS_GFX |
3391 GEN6_RP_UP_BUSY_AVG |
3392 GEN6_RP_DOWN_IDLE_AVG);
3396 /* Upclock if more than 90% busy over 13ms */
3397 I915_WRITE(GEN6_RP_UP_EI, 10250);
3398 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3400 /* Downclock if less than 75% busy over 32ms */
3401 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3402 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3404 I915_WRITE(GEN6_RP_CONTROL,
3405 GEN6_RP_MEDIA_TURBO |
3406 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3407 GEN6_RP_MEDIA_IS_GFX |
3409 GEN6_RP_UP_BUSY_AVG |
3410 GEN6_RP_DOWN_IDLE_AVG);
3414 /* Upclock if more than 85% busy over 10ms */
3415 I915_WRITE(GEN6_RP_UP_EI, 8000);
3416 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3418 /* Downclock if less than 60% busy over 32ms */
3419 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3420 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3422 I915_WRITE(GEN6_RP_CONTROL,
3423 GEN6_RP_MEDIA_TURBO |
3424 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3425 GEN6_RP_MEDIA_IS_GFX |
3427 GEN6_RP_UP_BUSY_AVG |
3428 GEN6_RP_DOWN_IDLE_AVG);
3432 dev_priv->rps.power = new_power;
3433 dev_priv->rps.last_adj = 0;
3436 void gen6_set_rps(struct drm_device *dev, u8 val)
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 u32 limits = gen6_rps_limits(dev_priv, &val);
3441 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3442 WARN_ON(val > dev_priv->rps.max_delay);
3443 WARN_ON(val < dev_priv->rps.min_delay);
3445 if (val == dev_priv->rps.cur_delay)
3448 gen6_set_rps_thresholds(dev_priv, val);
3450 if (IS_HASWELL(dev))
3451 I915_WRITE(GEN6_RPNSWREQ,
3452 HSW_FREQUENCY(val));
3454 I915_WRITE(GEN6_RPNSWREQ,
3455 GEN6_FREQUENCY(val) |
3457 GEN6_AGGRESSIVE_TURBO);
3459 /* Make sure we continue to get interrupts
3460 * until we hit the minimum or maximum frequencies.
3462 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3464 POSTING_READ(GEN6_RPNSWREQ);
3466 dev_priv->rps.cur_delay = val;
3468 trace_intel_gpu_freq_change(val * 50);
3471 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3473 mutex_lock(&dev_priv->rps.hw_lock);
3474 if (dev_priv->rps.enabled) {
3475 if (dev_priv->info->is_valleyview)
3476 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3478 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3479 dev_priv->rps.last_adj = 0;
3481 mutex_unlock(&dev_priv->rps.hw_lock);
3484 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3486 mutex_lock(&dev_priv->rps.hw_lock);
3487 if (dev_priv->rps.enabled) {
3488 if (dev_priv->info->is_valleyview)
3489 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3491 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3492 dev_priv->rps.last_adj = 0;
3494 mutex_unlock(&dev_priv->rps.hw_lock);
3498 * Wait until the previous freq change has completed,
3499 * or the timeout elapsed, and then update our notion
3500 * of the current GPU frequency.
3502 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3506 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3508 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3509 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3513 if (pval != dev_priv->rps.cur_delay)
3514 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3515 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3516 dev_priv->rps.cur_delay,
3517 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3519 dev_priv->rps.cur_delay = pval;
3522 void valleyview_set_rps(struct drm_device *dev, u8 val)
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3526 gen6_rps_limits(dev_priv, &val);
3528 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3529 WARN_ON(val > dev_priv->rps.max_delay);
3530 WARN_ON(val < dev_priv->rps.min_delay);
3532 vlv_update_rps_cur_delay(dev_priv);
3534 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3535 vlv_gpu_freq(dev_priv->mem_freq,
3536 dev_priv->rps.cur_delay),
3537 dev_priv->rps.cur_delay,
3538 vlv_gpu_freq(dev_priv->mem_freq, val), val);
3540 if (val == dev_priv->rps.cur_delay)
3543 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3545 dev_priv->rps.cur_delay = val;
3547 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3550 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3554 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3555 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3556 /* Complete PM interrupt masking here doesn't race with the rps work
3557 * item again unmasking PM interrupts because that is using a different
3558 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3559 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3561 spin_lock_irq(&dev_priv->irq_lock);
3562 dev_priv->rps.pm_iir = 0;
3563 spin_unlock_irq(&dev_priv->irq_lock);
3565 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3568 static void gen6_disable_rps(struct drm_device *dev)
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3572 I915_WRITE(GEN6_RC_CONTROL, 0);
3573 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3575 gen6_disable_rps_interrupts(dev);
3578 static void valleyview_disable_rps(struct drm_device *dev)
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3582 I915_WRITE(GEN6_RC_CONTROL, 0);
3584 gen6_disable_rps_interrupts(dev);
3586 if (dev_priv->vlv_pctx) {
3587 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3588 dev_priv->vlv_pctx = NULL;
3592 int intel_enable_rc6(const struct drm_device *dev)
3594 /* No RC6 before Ironlake */
3595 if (INTEL_INFO(dev)->gen < 5)
3598 /* Respect the kernel parameter if it is set */
3599 if (i915_enable_rc6 >= 0)
3600 return i915_enable_rc6;
3602 /* Disable RC6 on Ironlake */
3603 if (INTEL_INFO(dev)->gen == 5)
3606 if (IS_HASWELL(dev)) {
3607 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3608 return INTEL_RC6_ENABLE;
3611 /* snb/ivb have more than one rc6 state. */
3612 if (INTEL_INFO(dev)->gen == 6) {
3613 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3614 return INTEL_RC6_ENABLE;
3617 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3618 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3621 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3626 spin_lock_irq(&dev_priv->irq_lock);
3627 WARN_ON(dev_priv->rps.pm_iir);
3628 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3629 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3630 spin_unlock_irq(&dev_priv->irq_lock);
3632 /* only unmask PM interrupts we need. Mask all others. */
3633 enabled_intrs = GEN6_PM_RPS_EVENTS;
3635 /* IVB and SNB hard hangs on looping batchbuffer
3636 * if GEN6_PM_UP_EI_EXPIRED is masked.
3638 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3639 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3641 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3644 static void gen6_enable_rps(struct drm_device *dev)
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_ring_buffer *ring;
3650 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3655 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3657 /* Here begins a magic sequence of register writes to enable
3658 * auto-downclocking.
3660 * Perhaps there might be some value in exposing these to
3663 I915_WRITE(GEN6_RC_STATE, 0);
3665 /* Clear the DBG now so we don't confuse earlier errors */
3666 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3667 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3668 I915_WRITE(GTFIFODBG, gtfifodbg);
3671 gen6_gt_force_wake_get(dev_priv);
3673 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3674 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3676 /* In units of 50MHz */
3677 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3678 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3679 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3680 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3681 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3682 dev_priv->rps.cur_delay = 0;
3684 /* disable the counters and set deterministic thresholds */
3685 I915_WRITE(GEN6_RC_CONTROL, 0);
3687 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3688 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3689 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3690 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3691 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3693 for_each_ring(ring, dev_priv, i)
3694 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3696 I915_WRITE(GEN6_RC_SLEEP, 0);
3697 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3698 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3699 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3701 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3702 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3703 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3705 /* Check if we are enabling RC6 */
3706 rc6_mode = intel_enable_rc6(dev_priv->dev);
3707 if (rc6_mode & INTEL_RC6_ENABLE)
3708 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3710 /* We don't use those on Haswell */
3711 if (!IS_HASWELL(dev)) {
3712 if (rc6_mode & INTEL_RC6p_ENABLE)
3713 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3715 if (rc6_mode & INTEL_RC6pp_ENABLE)
3716 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3719 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3720 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3721 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3722 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3724 I915_WRITE(GEN6_RC_CONTROL,
3726 GEN6_RC_CTL_EI_MODE(1) |
3727 GEN6_RC_CTL_HW_ENABLE);
3729 /* Power down if completely idle for over 50ms */
3730 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3731 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3733 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3736 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3737 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3738 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3739 (dev_priv->rps.max_delay & 0xff) * 50,
3740 (pcu_mbox & 0xff) * 50);
3741 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3744 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3747 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3748 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3750 gen6_enable_rps_interrupts(dev);
3753 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3754 if (IS_GEN6(dev) && ret) {
3755 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3756 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3757 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3758 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3759 rc6vids &= 0xffff00;
3760 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3761 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3763 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3766 gen6_gt_force_wake_put(dev_priv);
3769 void gen6_update_ring_freq(struct drm_device *dev)
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3773 unsigned int gpu_freq;
3774 unsigned int max_ia_freq, min_ring_freq;
3775 int scaling_factor = 180;
3776 struct cpufreq_policy *policy;
3778 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3780 policy = cpufreq_cpu_get(0);
3782 max_ia_freq = policy->cpuinfo.max_freq;
3783 cpufreq_cpu_put(policy);
3786 * Default to measured freq if none found, PCU will ensure we
3789 max_ia_freq = tsc_khz;
3792 /* Convert from kHz to MHz */
3793 max_ia_freq /= 1000;
3795 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3796 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3797 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3800 * For each potential GPU frequency, load a ring frequency we'd like
3801 * to use for memory access. We do this by specifying the IA frequency
3802 * the PCU should use as a reference to determine the ring frequency.
3804 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3806 int diff = dev_priv->rps.max_delay - gpu_freq;
3807 unsigned int ia_freq = 0, ring_freq = 0;
3809 if (IS_HASWELL(dev)) {
3810 ring_freq = mult_frac(gpu_freq, 5, 4);
3811 ring_freq = max(min_ring_freq, ring_freq);
3812 /* leave ia_freq as the default, chosen by cpufreq */
3814 /* On older processors, there is no separate ring
3815 * clock domain, so in order to boost the bandwidth
3816 * of the ring, we need to upclock the CPU (ia_freq).
3818 * For GPU frequencies less than 750MHz,
3819 * just use the lowest ring freq.
3821 if (gpu_freq < min_freq)
3824 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3825 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3828 sandybridge_pcode_write(dev_priv,
3829 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3830 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3831 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3836 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3840 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3842 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3844 rp0 = min_t(u32, rp0, 0xea);
3849 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3853 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3854 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3855 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3856 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3861 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3863 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3866 static void valleyview_setup_pctx(struct drm_device *dev)
3868 struct drm_i915_private *dev_priv = dev->dev_private;
3869 struct drm_i915_gem_object *pctx;
3870 unsigned long pctx_paddr;
3872 int pctx_size = 24*1024;
3874 pcbr = I915_READ(VLV_PCBR);
3876 /* BIOS set it up already, grab the pre-alloc'd space */
3879 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3880 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3882 I915_GTT_OFFSET_NONE,
3888 * From the Gunit register HAS:
3889 * The Gfx driver is expected to program this register and ensure
3890 * proper allocation within Gfx stolen memory. For example, this
3891 * register should be programmed such than the PCBR range does not
3892 * overlap with other ranges, such as the frame buffer, protected
3893 * memory, or any other relevant ranges.
3895 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3897 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3901 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3902 I915_WRITE(VLV_PCBR, pctx_paddr);
3905 dev_priv->vlv_pctx = pctx;
3908 static void valleyview_enable_rps(struct drm_device *dev)
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911 struct intel_ring_buffer *ring;
3912 u32 gtfifodbg, val, rc6_mode = 0;
3915 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3917 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3918 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3920 I915_WRITE(GTFIFODBG, gtfifodbg);
3923 valleyview_setup_pctx(dev);
3925 gen6_gt_force_wake_get(dev_priv);
3927 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3928 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3929 I915_WRITE(GEN6_RP_UP_EI, 66000);
3930 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3932 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3934 I915_WRITE(GEN6_RP_CONTROL,
3935 GEN6_RP_MEDIA_TURBO |
3936 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3937 GEN6_RP_MEDIA_IS_GFX |
3939 GEN6_RP_UP_BUSY_AVG |
3940 GEN6_RP_DOWN_IDLE_CONT);
3942 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3943 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3944 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3946 for_each_ring(ring, dev_priv, i)
3947 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3949 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3951 /* allows RC6 residency counter to work */
3952 I915_WRITE(VLV_COUNTER_CONTROL,
3953 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3954 VLV_MEDIA_RC6_COUNT_EN |
3955 VLV_RENDER_RC6_COUNT_EN));
3956 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3957 rc6_mode = GEN7_RC_CTL_TO_MODE;
3958 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3960 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3961 switch ((val >> 6) & 3) {
3964 dev_priv->mem_freq = 800;
3967 dev_priv->mem_freq = 1066;
3970 dev_priv->mem_freq = 1333;
3973 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3975 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3976 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3978 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3979 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3980 vlv_gpu_freq(dev_priv->mem_freq,
3981 dev_priv->rps.cur_delay),
3982 dev_priv->rps.cur_delay);
3984 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3985 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3986 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3987 vlv_gpu_freq(dev_priv->mem_freq,
3988 dev_priv->rps.max_delay),
3989 dev_priv->rps.max_delay);
3991 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3992 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3993 vlv_gpu_freq(dev_priv->mem_freq,
3994 dev_priv->rps.rpe_delay),
3995 dev_priv->rps.rpe_delay);
3997 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3998 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3999 vlv_gpu_freq(dev_priv->mem_freq,
4000 dev_priv->rps.min_delay),
4001 dev_priv->rps.min_delay);
4003 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4004 vlv_gpu_freq(dev_priv->mem_freq,
4005 dev_priv->rps.rpe_delay),
4006 dev_priv->rps.rpe_delay);
4008 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4010 gen6_enable_rps_interrupts(dev);
4012 gen6_gt_force_wake_put(dev_priv);
4015 void ironlake_teardown_rc6(struct drm_device *dev)
4017 struct drm_i915_private *dev_priv = dev->dev_private;
4019 if (dev_priv->ips.renderctx) {
4020 i915_gem_object_unpin(dev_priv->ips.renderctx);
4021 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4022 dev_priv->ips.renderctx = NULL;
4025 if (dev_priv->ips.pwrctx) {
4026 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4027 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4028 dev_priv->ips.pwrctx = NULL;
4032 static void ironlake_disable_rc6(struct drm_device *dev)
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4036 if (I915_READ(PWRCTXA)) {
4037 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4038 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4039 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4042 I915_WRITE(PWRCTXA, 0);
4043 POSTING_READ(PWRCTXA);
4045 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4046 POSTING_READ(RSTDBYCTL);
4050 static int ironlake_setup_rc6(struct drm_device *dev)
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4054 if (dev_priv->ips.renderctx == NULL)
4055 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4056 if (!dev_priv->ips.renderctx)
4059 if (dev_priv->ips.pwrctx == NULL)
4060 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4061 if (!dev_priv->ips.pwrctx) {
4062 ironlake_teardown_rc6(dev);
4069 static void ironlake_enable_rc6(struct drm_device *dev)
4071 struct drm_i915_private *dev_priv = dev->dev_private;
4072 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4073 bool was_interruptible;
4076 /* rc6 disabled by default due to repeated reports of hanging during
4079 if (!intel_enable_rc6(dev))
4082 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4084 ret = ironlake_setup_rc6(dev);
4088 was_interruptible = dev_priv->mm.interruptible;
4089 dev_priv->mm.interruptible = false;
4092 * GPU can automatically power down the render unit if given a page
4095 ret = intel_ring_begin(ring, 6);
4097 ironlake_teardown_rc6(dev);
4098 dev_priv->mm.interruptible = was_interruptible;
4102 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4103 intel_ring_emit(ring, MI_SET_CONTEXT);
4104 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4106 MI_SAVE_EXT_STATE_EN |
4107 MI_RESTORE_EXT_STATE_EN |
4108 MI_RESTORE_INHIBIT);
4109 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4110 intel_ring_emit(ring, MI_NOOP);
4111 intel_ring_emit(ring, MI_FLUSH);
4112 intel_ring_advance(ring);
4115 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4116 * does an implicit flush, combined with MI_FLUSH above, it should be
4117 * safe to assume that renderctx is valid
4119 ret = intel_ring_idle(ring);
4120 dev_priv->mm.interruptible = was_interruptible;
4122 DRM_ERROR("failed to enable ironlake power savings\n");
4123 ironlake_teardown_rc6(dev);
4127 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4128 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4131 static unsigned long intel_pxfreq(u32 vidfreq)
4134 int div = (vidfreq & 0x3f0000) >> 16;
4135 int post = (vidfreq & 0x3000) >> 12;
4136 int pre = (vidfreq & 0x7);
4141 freq = ((div * 133333) / ((1<<post) * pre));
4146 static const struct cparams {
4152 { 1, 1333, 301, 28664 },
4153 { 1, 1066, 294, 24460 },
4154 { 1, 800, 294, 25192 },
4155 { 0, 1333, 276, 27605 },
4156 { 0, 1066, 276, 27605 },
4157 { 0, 800, 231, 23784 },
4160 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4162 u64 total_count, diff, ret;
4163 u32 count1, count2, count3, m = 0, c = 0;
4164 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4167 assert_spin_locked(&mchdev_lock);
4169 diff1 = now - dev_priv->ips.last_time1;
4171 /* Prevent division-by-zero if we are asking too fast.
4172 * Also, we don't get interesting results if we are polling
4173 * faster than once in 10ms, so just return the saved value
4177 return dev_priv->ips.chipset_power;
4179 count1 = I915_READ(DMIEC);
4180 count2 = I915_READ(DDREC);
4181 count3 = I915_READ(CSIEC);
4183 total_count = count1 + count2 + count3;
4185 /* FIXME: handle per-counter overflow */
4186 if (total_count < dev_priv->ips.last_count1) {
4187 diff = ~0UL - dev_priv->ips.last_count1;
4188 diff += total_count;
4190 diff = total_count - dev_priv->ips.last_count1;
4193 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4194 if (cparams[i].i == dev_priv->ips.c_m &&
4195 cparams[i].t == dev_priv->ips.r_t) {
4202 diff = div_u64(diff, diff1);
4203 ret = ((m * diff) + c);
4204 ret = div_u64(ret, 10);
4206 dev_priv->ips.last_count1 = total_count;
4207 dev_priv->ips.last_time1 = now;
4209 dev_priv->ips.chipset_power = ret;
4214 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4218 if (dev_priv->info->gen != 5)
4221 spin_lock_irq(&mchdev_lock);
4223 val = __i915_chipset_val(dev_priv);
4225 spin_unlock_irq(&mchdev_lock);
4230 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4232 unsigned long m, x, b;
4235 tsfs = I915_READ(TSFS);
4237 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4238 x = I915_READ8(TR1);
4240 b = tsfs & TSFS_INTR_MASK;
4242 return ((m * x) / 127) - b;
4245 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4247 static const struct v_table {
4248 u16 vd; /* in .1 mil */
4249 u16 vm; /* in .1 mil */
4380 if (dev_priv->info->is_mobile)
4381 return v_table[pxvid].vm;
4383 return v_table[pxvid].vd;
4386 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4388 struct timespec now, diff1;
4390 unsigned long diffms;
4393 assert_spin_locked(&mchdev_lock);
4395 getrawmonotonic(&now);
4396 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4398 /* Don't divide by 0 */
4399 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4403 count = I915_READ(GFXEC);
4405 if (count < dev_priv->ips.last_count2) {
4406 diff = ~0UL - dev_priv->ips.last_count2;
4409 diff = count - dev_priv->ips.last_count2;
4412 dev_priv->ips.last_count2 = count;
4413 dev_priv->ips.last_time2 = now;
4415 /* More magic constants... */
4417 diff = div_u64(diff, diffms * 10);
4418 dev_priv->ips.gfx_power = diff;
4421 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4423 if (dev_priv->info->gen != 5)
4426 spin_lock_irq(&mchdev_lock);
4428 __i915_update_gfx_val(dev_priv);
4430 spin_unlock_irq(&mchdev_lock);
4433 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4435 unsigned long t, corr, state1, corr2, state2;
4438 assert_spin_locked(&mchdev_lock);
4440 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4441 pxvid = (pxvid >> 24) & 0x7f;
4442 ext_v = pvid_to_extvid(dev_priv, pxvid);
4446 t = i915_mch_val(dev_priv);
4448 /* Revel in the empirically derived constants */
4450 /* Correction factor in 1/100000 units */
4452 corr = ((t * 2349) + 135940);
4454 corr = ((t * 964) + 29317);
4456 corr = ((t * 301) + 1004);
4458 corr = corr * ((150142 * state1) / 10000 - 78642);
4460 corr2 = (corr * dev_priv->ips.corr);
4462 state2 = (corr2 * state1) / 10000;
4463 state2 /= 100; /* convert to mW */
4465 __i915_update_gfx_val(dev_priv);
4467 return dev_priv->ips.gfx_power + state2;
4470 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4474 if (dev_priv->info->gen != 5)
4477 spin_lock_irq(&mchdev_lock);
4479 val = __i915_gfx_val(dev_priv);
4481 spin_unlock_irq(&mchdev_lock);
4487 * i915_read_mch_val - return value for IPS use
4489 * Calculate and return a value for the IPS driver to use when deciding whether
4490 * we have thermal and power headroom to increase CPU or GPU power budget.
4492 unsigned long i915_read_mch_val(void)
4494 struct drm_i915_private *dev_priv;
4495 unsigned long chipset_val, graphics_val, ret = 0;
4497 spin_lock_irq(&mchdev_lock);
4500 dev_priv = i915_mch_dev;
4502 chipset_val = __i915_chipset_val(dev_priv);
4503 graphics_val = __i915_gfx_val(dev_priv);
4505 ret = chipset_val + graphics_val;
4508 spin_unlock_irq(&mchdev_lock);
4512 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4515 * i915_gpu_raise - raise GPU frequency limit
4517 * Raise the limit; IPS indicates we have thermal headroom.
4519 bool i915_gpu_raise(void)
4521 struct drm_i915_private *dev_priv;
4524 spin_lock_irq(&mchdev_lock);
4525 if (!i915_mch_dev) {
4529 dev_priv = i915_mch_dev;
4531 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4532 dev_priv->ips.max_delay--;
4535 spin_unlock_irq(&mchdev_lock);
4539 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4542 * i915_gpu_lower - lower GPU frequency limit
4544 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4545 * frequency maximum.
4547 bool i915_gpu_lower(void)
4549 struct drm_i915_private *dev_priv;
4552 spin_lock_irq(&mchdev_lock);
4553 if (!i915_mch_dev) {
4557 dev_priv = i915_mch_dev;
4559 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4560 dev_priv->ips.max_delay++;
4563 spin_unlock_irq(&mchdev_lock);
4567 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4570 * i915_gpu_busy - indicate GPU business to IPS
4572 * Tell the IPS driver whether or not the GPU is busy.
4574 bool i915_gpu_busy(void)
4576 struct drm_i915_private *dev_priv;
4577 struct intel_ring_buffer *ring;
4581 spin_lock_irq(&mchdev_lock);
4584 dev_priv = i915_mch_dev;
4586 for_each_ring(ring, dev_priv, i)
4587 ret |= !list_empty(&ring->request_list);
4590 spin_unlock_irq(&mchdev_lock);
4594 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4597 * i915_gpu_turbo_disable - disable graphics turbo
4599 * Disable graphics turbo by resetting the max frequency and setting the
4600 * current frequency to the default.
4602 bool i915_gpu_turbo_disable(void)
4604 struct drm_i915_private *dev_priv;
4607 spin_lock_irq(&mchdev_lock);
4608 if (!i915_mch_dev) {
4612 dev_priv = i915_mch_dev;
4614 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4616 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4620 spin_unlock_irq(&mchdev_lock);
4624 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4627 * Tells the intel_ips driver that the i915 driver is now loaded, if
4628 * IPS got loaded first.
4630 * This awkward dance is so that neither module has to depend on the
4631 * other in order for IPS to do the appropriate communication of
4632 * GPU turbo limits to i915.
4635 ips_ping_for_i915_load(void)
4639 link = symbol_get(ips_link_to_i915_driver);
4642 symbol_put(ips_link_to_i915_driver);
4646 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4648 /* We only register the i915 ips part with intel-ips once everything is
4649 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4650 spin_lock_irq(&mchdev_lock);
4651 i915_mch_dev = dev_priv;
4652 spin_unlock_irq(&mchdev_lock);
4654 ips_ping_for_i915_load();
4657 void intel_gpu_ips_teardown(void)
4659 spin_lock_irq(&mchdev_lock);
4660 i915_mch_dev = NULL;
4661 spin_unlock_irq(&mchdev_lock);
4663 static void intel_init_emon(struct drm_device *dev)
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4670 /* Disable to program */
4674 /* Program energy weights for various events */
4675 I915_WRITE(SDEW, 0x15040d00);
4676 I915_WRITE(CSIEW0, 0x007f0000);
4677 I915_WRITE(CSIEW1, 0x1e220004);
4678 I915_WRITE(CSIEW2, 0x04000004);
4680 for (i = 0; i < 5; i++)
4681 I915_WRITE(PEW + (i * 4), 0);
4682 for (i = 0; i < 3; i++)
4683 I915_WRITE(DEW + (i * 4), 0);
4685 /* Program P-state weights to account for frequency power adjustment */
4686 for (i = 0; i < 16; i++) {
4687 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4688 unsigned long freq = intel_pxfreq(pxvidfreq);
4689 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4694 val *= (freq / 1000);
4696 val /= (127*127*900);
4698 DRM_ERROR("bad pxval: %ld\n", val);
4701 /* Render standby states get 0 weight */
4705 for (i = 0; i < 4; i++) {
4706 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4707 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4708 I915_WRITE(PXW + (i * 4), val);
4711 /* Adjust magic regs to magic values (more experimental results) */
4712 I915_WRITE(OGW0, 0);
4713 I915_WRITE(OGW1, 0);
4714 I915_WRITE(EG0, 0x00007f00);
4715 I915_WRITE(EG1, 0x0000000e);
4716 I915_WRITE(EG2, 0x000e0000);
4717 I915_WRITE(EG3, 0x68000300);
4718 I915_WRITE(EG4, 0x42000000);
4719 I915_WRITE(EG5, 0x00140031);
4723 for (i = 0; i < 8; i++)
4724 I915_WRITE(PXWL + (i * 4), 0);
4726 /* Enable PMON + select events */
4727 I915_WRITE(ECR, 0x80000019);
4729 lcfuse = I915_READ(LCFUSE02);
4731 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4734 void intel_disable_gt_powersave(struct drm_device *dev)
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4738 /* Interrupts should be disabled already to avoid re-arming. */
4739 WARN_ON(dev->irq_enabled);
4741 if (IS_IRONLAKE_M(dev)) {
4742 ironlake_disable_drps(dev);
4743 ironlake_disable_rc6(dev);
4744 } else if (INTEL_INFO(dev)->gen >= 6) {
4745 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4746 cancel_work_sync(&dev_priv->rps.work);
4747 mutex_lock(&dev_priv->rps.hw_lock);
4748 if (IS_VALLEYVIEW(dev))
4749 valleyview_disable_rps(dev);
4751 gen6_disable_rps(dev);
4752 dev_priv->rps.enabled = false;
4753 mutex_unlock(&dev_priv->rps.hw_lock);
4757 static void intel_gen6_powersave_work(struct work_struct *work)
4759 struct drm_i915_private *dev_priv =
4760 container_of(work, struct drm_i915_private,
4761 rps.delayed_resume_work.work);
4762 struct drm_device *dev = dev_priv->dev;
4764 mutex_lock(&dev_priv->rps.hw_lock);
4766 if (IS_VALLEYVIEW(dev)) {
4767 valleyview_enable_rps(dev);
4769 gen6_enable_rps(dev);
4770 gen6_update_ring_freq(dev);
4772 dev_priv->rps.enabled = true;
4773 mutex_unlock(&dev_priv->rps.hw_lock);
4776 void intel_enable_gt_powersave(struct drm_device *dev)
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4780 if (IS_IRONLAKE_M(dev)) {
4781 ironlake_enable_drps(dev);
4782 ironlake_enable_rc6(dev);
4783 intel_init_emon(dev);
4784 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4786 * PCU communication is slow and this doesn't need to be
4787 * done at any specific time, so do this out of our fast path
4788 * to make resume and init faster.
4790 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4791 round_jiffies_up_relative(HZ));
4795 static void ibx_init_clock_gating(struct drm_device *dev)
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4800 * On Ibex Peak and Cougar Point, we need to disable clock
4801 * gating for the panel power sequencer or it will fail to
4802 * start up when no ports are active.
4804 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4807 static void g4x_disable_trickle_feed(struct drm_device *dev)
4809 struct drm_i915_private *dev_priv = dev->dev_private;
4812 for_each_pipe(pipe) {
4813 I915_WRITE(DSPCNTR(pipe),
4814 I915_READ(DSPCNTR(pipe)) |
4815 DISPPLANE_TRICKLE_FEED_DISABLE);
4816 intel_flush_primary_plane(dev_priv, pipe);
4820 static void ironlake_init_clock_gating(struct drm_device *dev)
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4827 * WaFbcDisableDpfcClockGating:ilk
4829 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4830 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4831 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4833 I915_WRITE(PCH_3DCGDIS0,
4834 MARIUNIT_CLOCK_GATE_DISABLE |
4835 SVSMUNIT_CLOCK_GATE_DISABLE);
4836 I915_WRITE(PCH_3DCGDIS1,
4837 VFMUNIT_CLOCK_GATE_DISABLE);
4840 * According to the spec the following bits should be set in
4841 * order to enable memory self-refresh
4842 * The bit 22/21 of 0x42004
4843 * The bit 5 of 0x42020
4844 * The bit 15 of 0x45000
4846 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4847 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4848 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4849 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4850 I915_WRITE(DISP_ARB_CTL,
4851 (I915_READ(DISP_ARB_CTL) |
4853 I915_WRITE(WM3_LP_ILK, 0);
4854 I915_WRITE(WM2_LP_ILK, 0);
4855 I915_WRITE(WM1_LP_ILK, 0);
4858 * Based on the document from hardware guys the following bits
4859 * should be set unconditionally in order to enable FBC.
4860 * The bit 22 of 0x42000
4861 * The bit 22 of 0x42004
4862 * The bit 7,8,9 of 0x42020.
4864 if (IS_IRONLAKE_M(dev)) {
4865 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4866 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4867 I915_READ(ILK_DISPLAY_CHICKEN1) |
4869 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4870 I915_READ(ILK_DISPLAY_CHICKEN2) |
4874 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4876 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4877 I915_READ(ILK_DISPLAY_CHICKEN2) |
4878 ILK_ELPIN_409_SELECT);
4879 I915_WRITE(_3D_CHICKEN2,
4880 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4881 _3D_CHICKEN2_WM_READ_PIPELINED);
4883 /* WaDisableRenderCachePipelinedFlush:ilk */
4884 I915_WRITE(CACHE_MODE_0,
4885 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4887 g4x_disable_trickle_feed(dev);
4889 ibx_init_clock_gating(dev);
4892 static void cpt_init_clock_gating(struct drm_device *dev)
4894 struct drm_i915_private *dev_priv = dev->dev_private;
4899 * On Ibex Peak and Cougar Point, we need to disable clock
4900 * gating for the panel power sequencer or it will fail to
4901 * start up when no ports are active.
4903 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4904 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4905 DPLS_EDP_PPS_FIX_DIS);
4906 /* The below fixes the weird display corruption, a few pixels shifted
4907 * downward, on (only) LVDS of some HP laptops with IVY.
4909 for_each_pipe(pipe) {
4910 val = I915_READ(TRANS_CHICKEN2(pipe));
4911 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4912 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4913 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4914 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4915 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4916 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4917 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4918 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4920 /* WADP0ClockGatingDisable */
4921 for_each_pipe(pipe) {
4922 I915_WRITE(TRANS_CHICKEN1(pipe),
4923 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4927 static void gen6_check_mch_setup(struct drm_device *dev)
4929 struct drm_i915_private *dev_priv = dev->dev_private;
4932 tmp = I915_READ(MCH_SSKPD);
4933 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4934 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4935 DRM_INFO("This can cause pipe underruns and display issues.\n");
4936 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4940 static void gen6_init_clock_gating(struct drm_device *dev)
4942 struct drm_i915_private *dev_priv = dev->dev_private;
4943 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4945 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4947 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4948 I915_READ(ILK_DISPLAY_CHICKEN2) |
4949 ILK_ELPIN_409_SELECT);
4951 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4952 I915_WRITE(_3D_CHICKEN,
4953 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4955 /* WaSetupGtModeTdRowDispatch:snb */
4956 if (IS_SNB_GT1(dev))
4957 I915_WRITE(GEN6_GT_MODE,
4958 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4960 I915_WRITE(WM3_LP_ILK, 0);
4961 I915_WRITE(WM2_LP_ILK, 0);
4962 I915_WRITE(WM1_LP_ILK, 0);
4964 I915_WRITE(CACHE_MODE_0,
4965 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4967 I915_WRITE(GEN6_UCGCTL1,
4968 I915_READ(GEN6_UCGCTL1) |
4969 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4970 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4972 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4973 * gating disable must be set. Failure to set it results in
4974 * flickering pixels due to Z write ordering failures after
4975 * some amount of runtime in the Mesa "fire" demo, and Unigine
4976 * Sanctuary and Tropics, and apparently anything else with
4977 * alpha test or pixel discard.
4979 * According to the spec, bit 11 (RCCUNIT) must also be set,
4980 * but we didn't debug actual testcases to find it out.
4982 * Also apply WaDisableVDSUnitClockGating:snb and
4983 * WaDisableRCPBUnitClockGating:snb.
4985 I915_WRITE(GEN6_UCGCTL2,
4986 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4987 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4988 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4990 /* Bspec says we need to always set all mask bits. */
4991 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4992 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4995 * According to the spec the following bits should be
4996 * set in order to enable memory self-refresh and fbc:
4997 * The bit21 and bit22 of 0x42000
4998 * The bit21 and bit22 of 0x42004
4999 * The bit5 and bit7 of 0x42020
5000 * The bit14 of 0x70180
5001 * The bit14 of 0x71180
5003 * WaFbcAsynchFlipDisableFbcQueue:snb
5005 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5006 I915_READ(ILK_DISPLAY_CHICKEN1) |
5007 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5008 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5009 I915_READ(ILK_DISPLAY_CHICKEN2) |
5010 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5011 I915_WRITE(ILK_DSPCLK_GATE_D,
5012 I915_READ(ILK_DSPCLK_GATE_D) |
5013 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5014 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5016 g4x_disable_trickle_feed(dev);
5018 /* The default value should be 0x200 according to docs, but the two
5019 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5020 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5021 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5023 cpt_init_clock_gating(dev);
5025 gen6_check_mch_setup(dev);
5028 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5030 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5032 reg &= ~GEN7_FF_SCHED_MASK;
5033 reg |= GEN7_FF_TS_SCHED_HW;
5034 reg |= GEN7_FF_VS_SCHED_HW;
5035 reg |= GEN7_FF_DS_SCHED_HW;
5037 if (IS_HASWELL(dev_priv->dev))
5038 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5040 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5043 static void lpt_init_clock_gating(struct drm_device *dev)
5045 struct drm_i915_private *dev_priv = dev->dev_private;
5048 * TODO: this bit should only be enabled when really needed, then
5049 * disabled when not needed anymore in order to save power.
5051 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5052 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5053 I915_READ(SOUTH_DSPCLK_GATE_D) |
5054 PCH_LP_PARTITION_LEVEL_DISABLE);
5056 /* WADPOClockGatingDisable:hsw */
5057 I915_WRITE(_TRANSA_CHICKEN1,
5058 I915_READ(_TRANSA_CHICKEN1) |
5059 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5062 static void lpt_suspend_hw(struct drm_device *dev)
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5066 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5067 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5069 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5070 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5074 static void haswell_init_clock_gating(struct drm_device *dev)
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5078 I915_WRITE(WM3_LP_ILK, 0);
5079 I915_WRITE(WM2_LP_ILK, 0);
5080 I915_WRITE(WM1_LP_ILK, 0);
5082 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5083 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5085 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5087 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5088 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5089 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5091 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5092 I915_WRITE(GEN7_L3CNTLREG1,
5093 GEN7_WA_FOR_GEN7_L3_CONTROL);
5094 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5095 GEN7_WA_L3_CHICKEN_MODE);
5097 /* This is required by WaCatErrorRejectionIssue:hsw */
5098 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5099 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5100 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5102 /* WaVSRefCountFullforceMissDisable:hsw */
5103 gen7_setup_fixed_func_scheduler(dev_priv);
5105 /* WaDisable4x2SubspanOptimization:hsw */
5106 I915_WRITE(CACHE_MODE_1,
5107 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5109 /* WaSwitchSolVfFArbitrationPriority:hsw */
5110 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5112 /* WaRsPkgCStateDisplayPMReq:hsw */
5113 I915_WRITE(CHICKEN_PAR1_1,
5114 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5116 lpt_init_clock_gating(dev);
5119 static void ivybridge_init_clock_gating(struct drm_device *dev)
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5124 I915_WRITE(WM3_LP_ILK, 0);
5125 I915_WRITE(WM2_LP_ILK, 0);
5126 I915_WRITE(WM1_LP_ILK, 0);
5128 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5130 /* WaDisableEarlyCull:ivb */
5131 I915_WRITE(_3D_CHICKEN3,
5132 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5134 /* WaDisableBackToBackFlipFix:ivb */
5135 I915_WRITE(IVB_CHICKEN3,
5136 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5137 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5139 /* WaDisablePSDDualDispatchEnable:ivb */
5140 if (IS_IVB_GT1(dev))
5141 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5142 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5144 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5145 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5147 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5148 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5149 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5151 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5152 I915_WRITE(GEN7_L3CNTLREG1,
5153 GEN7_WA_FOR_GEN7_L3_CONTROL);
5154 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5155 GEN7_WA_L3_CHICKEN_MODE);
5156 if (IS_IVB_GT1(dev))
5157 I915_WRITE(GEN7_ROW_CHICKEN2,
5158 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5160 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5161 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5164 /* WaForceL3Serialization:ivb */
5165 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5166 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5168 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5169 * gating disable must be set. Failure to set it results in
5170 * flickering pixels due to Z write ordering failures after
5171 * some amount of runtime in the Mesa "fire" demo, and Unigine
5172 * Sanctuary and Tropics, and apparently anything else with
5173 * alpha test or pixel discard.
5175 * According to the spec, bit 11 (RCCUNIT) must also be set,
5176 * but we didn't debug actual testcases to find it out.
5178 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5179 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5181 I915_WRITE(GEN6_UCGCTL2,
5182 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5183 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5185 /* This is required by WaCatErrorRejectionIssue:ivb */
5186 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5187 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5188 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5190 g4x_disable_trickle_feed(dev);
5192 /* WaVSRefCountFullforceMissDisable:ivb */
5193 gen7_setup_fixed_func_scheduler(dev_priv);
5195 /* WaDisable4x2SubspanOptimization:ivb */
5196 I915_WRITE(CACHE_MODE_1,
5197 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5199 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5200 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5201 snpcr |= GEN6_MBC_SNPCR_MED;
5202 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5204 if (!HAS_PCH_NOP(dev))
5205 cpt_init_clock_gating(dev);
5207 gen6_check_mch_setup(dev);
5210 static void valleyview_init_clock_gating(struct drm_device *dev)
5212 struct drm_i915_private *dev_priv = dev->dev_private;
5214 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5216 /* WaDisableEarlyCull:vlv */
5217 I915_WRITE(_3D_CHICKEN3,
5218 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5220 /* WaDisableBackToBackFlipFix:vlv */
5221 I915_WRITE(IVB_CHICKEN3,
5222 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5223 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5225 /* WaDisablePSDDualDispatchEnable:vlv */
5226 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5227 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5228 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5230 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5231 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5232 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5234 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5235 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5236 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5238 /* WaForceL3Serialization:vlv */
5239 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5240 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5242 /* WaDisableDopClockGating:vlv */
5243 I915_WRITE(GEN7_ROW_CHICKEN2,
5244 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5246 /* This is required by WaCatErrorRejectionIssue:vlv */
5247 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5248 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5249 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5251 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5252 * gating disable must be set. Failure to set it results in
5253 * flickering pixels due to Z write ordering failures after
5254 * some amount of runtime in the Mesa "fire" demo, and Unigine
5255 * Sanctuary and Tropics, and apparently anything else with
5256 * alpha test or pixel discard.
5258 * According to the spec, bit 11 (RCCUNIT) must also be set,
5259 * but we didn't debug actual testcases to find it out.
5261 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5262 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5264 * Also apply WaDisableVDSUnitClockGating:vlv and
5265 * WaDisableRCPBUnitClockGating:vlv.
5267 I915_WRITE(GEN6_UCGCTL2,
5268 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5269 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5270 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5271 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5272 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5274 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5276 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5278 I915_WRITE(CACHE_MODE_1,
5279 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5282 * WaDisableVLVClockGating_VBIIssue:vlv
5283 * Disable clock gating on th GCFG unit to prevent a delay
5284 * in the reporting of vblank events.
5286 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5288 /* Conservative clock gating settings for now */
5289 I915_WRITE(0x9400, 0xffffffff);
5290 I915_WRITE(0x9404, 0xffffffff);
5291 I915_WRITE(0x9408, 0xffffffff);
5292 I915_WRITE(0x940c, 0xffffffff);
5293 I915_WRITE(0x9410, 0xffffffff);
5294 I915_WRITE(0x9414, 0xffffffff);
5295 I915_WRITE(0x9418, 0xffffffff);
5298 static void g4x_init_clock_gating(struct drm_device *dev)
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 uint32_t dspclk_gate;
5303 I915_WRITE(RENCLK_GATE_D1, 0);
5304 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5305 GS_UNIT_CLOCK_GATE_DISABLE |
5306 CL_UNIT_CLOCK_GATE_DISABLE);
5307 I915_WRITE(RAMCLK_GATE_D, 0);
5308 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5309 OVRUNIT_CLOCK_GATE_DISABLE |
5310 OVCUNIT_CLOCK_GATE_DISABLE;
5312 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5313 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5315 /* WaDisableRenderCachePipelinedFlush */
5316 I915_WRITE(CACHE_MODE_0,
5317 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5319 g4x_disable_trickle_feed(dev);
5322 static void crestline_init_clock_gating(struct drm_device *dev)
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5326 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5327 I915_WRITE(RENCLK_GATE_D2, 0);
5328 I915_WRITE(DSPCLK_GATE_D, 0);
5329 I915_WRITE(RAMCLK_GATE_D, 0);
5330 I915_WRITE16(DEUC, 0);
5331 I915_WRITE(MI_ARB_STATE,
5332 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5335 static void broadwater_init_clock_gating(struct drm_device *dev)
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5339 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5340 I965_RCC_CLOCK_GATE_DISABLE |
5341 I965_RCPB_CLOCK_GATE_DISABLE |
5342 I965_ISC_CLOCK_GATE_DISABLE |
5343 I965_FBC_CLOCK_GATE_DISABLE);
5344 I915_WRITE(RENCLK_GATE_D2, 0);
5345 I915_WRITE(MI_ARB_STATE,
5346 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5349 static void gen3_init_clock_gating(struct drm_device *dev)
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 u32 dstate = I915_READ(D_STATE);
5354 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5355 DSTATE_DOT_CLOCK_GATING;
5356 I915_WRITE(D_STATE, dstate);
5358 if (IS_PINEVIEW(dev))
5359 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5361 /* IIR "flip pending" means done if this bit is set */
5362 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5365 static void i85x_init_clock_gating(struct drm_device *dev)
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5369 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5372 static void i830_init_clock_gating(struct drm_device *dev)
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5376 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5379 void intel_init_clock_gating(struct drm_device *dev)
5381 struct drm_i915_private *dev_priv = dev->dev_private;
5383 dev_priv->display.init_clock_gating(dev);
5386 void intel_suspend_hw(struct drm_device *dev)
5388 if (HAS_PCH_LPT(dev))
5389 lpt_suspend_hw(dev);
5393 * We should only use the power well if we explicitly asked the hardware to
5394 * enable it, so check if it's enabled and also check if we've requested it to
5397 bool intel_display_power_enabled(struct drm_device *dev,
5398 enum intel_display_power_domain domain)
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5402 if (!HAS_POWER_WELL(dev))
5406 case POWER_DOMAIN_PIPE_A:
5407 case POWER_DOMAIN_TRANSCODER_EDP:
5409 case POWER_DOMAIN_VGA:
5410 case POWER_DOMAIN_PIPE_B:
5411 case POWER_DOMAIN_PIPE_C:
5412 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5413 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5414 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5415 case POWER_DOMAIN_TRANSCODER_A:
5416 case POWER_DOMAIN_TRANSCODER_B:
5417 case POWER_DOMAIN_TRANSCODER_C:
5418 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5419 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5425 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 bool is_enabled, enable_requested;
5431 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5432 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5433 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5436 if (!enable_requested)
5437 I915_WRITE(HSW_PWR_WELL_DRIVER,
5438 HSW_PWR_WELL_ENABLE_REQUEST);
5441 DRM_DEBUG_KMS("Enabling power well\n");
5442 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5443 HSW_PWR_WELL_STATE_ENABLED), 20))
5444 DRM_ERROR("Timeout enabling power well\n");
5447 if (enable_requested) {
5448 unsigned long irqflags;
5451 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5452 POSTING_READ(HSW_PWR_WELL_DRIVER);
5453 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5456 * After this, the registers on the pipes that are part
5457 * of the power well will become zero, so we have to
5458 * adjust our counters according to that.
5460 * FIXME: Should we do this in general in
5461 * drm_vblank_post_modeset?
5463 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5466 dev->vblank[p].last = 0;
5467 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5472 static void __intel_power_well_get(struct i915_power_well *power_well)
5474 if (!power_well->count++)
5475 __intel_set_power_well(power_well->device, true);
5478 static void __intel_power_well_put(struct i915_power_well *power_well)
5480 WARN_ON(!power_well->count);
5481 if (!--power_well->count)
5482 __intel_set_power_well(power_well->device, false);
5485 void intel_display_power_get(struct drm_device *dev,
5486 enum intel_display_power_domain domain)
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 struct i915_power_well *power_well = &dev_priv->power_well;
5491 if (!HAS_POWER_WELL(dev))
5495 case POWER_DOMAIN_PIPE_A:
5496 case POWER_DOMAIN_TRANSCODER_EDP:
5498 case POWER_DOMAIN_VGA:
5499 case POWER_DOMAIN_PIPE_B:
5500 case POWER_DOMAIN_PIPE_C:
5501 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5502 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5503 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5504 case POWER_DOMAIN_TRANSCODER_A:
5505 case POWER_DOMAIN_TRANSCODER_B:
5506 case POWER_DOMAIN_TRANSCODER_C:
5507 spin_lock_irq(&power_well->lock);
5508 __intel_power_well_get(power_well);
5509 spin_unlock_irq(&power_well->lock);
5516 void intel_display_power_put(struct drm_device *dev,
5517 enum intel_display_power_domain domain)
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 struct i915_power_well *power_well = &dev_priv->power_well;
5522 if (!HAS_POWER_WELL(dev))
5526 case POWER_DOMAIN_PIPE_A:
5527 case POWER_DOMAIN_TRANSCODER_EDP:
5529 case POWER_DOMAIN_VGA:
5530 case POWER_DOMAIN_PIPE_B:
5531 case POWER_DOMAIN_PIPE_C:
5532 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5533 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5534 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5535 case POWER_DOMAIN_TRANSCODER_A:
5536 case POWER_DOMAIN_TRANSCODER_B:
5537 case POWER_DOMAIN_TRANSCODER_C:
5538 spin_lock_irq(&power_well->lock);
5539 __intel_power_well_put(power_well);
5540 spin_unlock_irq(&power_well->lock);
5547 static struct i915_power_well *hsw_pwr;
5549 /* Display audio driver power well request */
5550 void i915_request_power_well(void)
5552 if (WARN_ON(!hsw_pwr))
5555 spin_lock_irq(&hsw_pwr->lock);
5556 __intel_power_well_get(hsw_pwr);
5557 spin_unlock_irq(&hsw_pwr->lock);
5559 EXPORT_SYMBOL_GPL(i915_request_power_well);
5561 /* Display audio driver power well release */
5562 void i915_release_power_well(void)
5564 if (WARN_ON(!hsw_pwr))
5567 spin_lock_irq(&hsw_pwr->lock);
5568 __intel_power_well_put(hsw_pwr);
5569 spin_unlock_irq(&hsw_pwr->lock);
5571 EXPORT_SYMBOL_GPL(i915_release_power_well);
5573 int i915_init_power_well(struct drm_device *dev)
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5577 hsw_pwr = &dev_priv->power_well;
5579 hsw_pwr->device = dev;
5580 spin_lock_init(&hsw_pwr->lock);
5586 void i915_remove_power_well(struct drm_device *dev)
5591 void intel_set_power_well(struct drm_device *dev, bool enable)
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594 struct i915_power_well *power_well = &dev_priv->power_well;
5596 if (!HAS_POWER_WELL(dev))
5599 if (!i915_disable_power_well && !enable)
5602 spin_lock_irq(&power_well->lock);
5605 * This function will only ever contribute one
5606 * to the power well reference count. i915_request
5607 * is what tracks whether we have or have not
5608 * added the one to the reference count.
5610 if (power_well->i915_request == enable)
5613 power_well->i915_request = enable;
5616 __intel_power_well_get(power_well);
5618 __intel_power_well_put(power_well);
5621 spin_unlock_irq(&power_well->lock);
5624 static void intel_resume_power_well(struct drm_device *dev)
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627 struct i915_power_well *power_well = &dev_priv->power_well;
5629 if (!HAS_POWER_WELL(dev))
5632 spin_lock_irq(&power_well->lock);
5633 __intel_set_power_well(dev, power_well->count > 0);
5634 spin_unlock_irq(&power_well->lock);
5638 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5639 * when not needed anymore. We have 4 registers that can request the power well
5640 * to be enabled, and it will only be disabled if none of the registers is
5641 * requesting it to be enabled.
5643 void intel_init_power_well(struct drm_device *dev)
5645 struct drm_i915_private *dev_priv = dev->dev_private;
5647 if (!HAS_POWER_WELL(dev))
5650 /* For now, we need the power well to be always enabled. */
5651 intel_set_power_well(dev, true);
5652 intel_resume_power_well(dev);
5654 /* We're taking over the BIOS, so clear any requests made by it since
5655 * the driver is in charge now. */
5656 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5657 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5660 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5661 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5663 hsw_disable_package_c8(dev_priv);
5666 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5668 hsw_enable_package_c8(dev_priv);
5671 /* Set up chip specific power management-related functions */
5672 void intel_init_pm(struct drm_device *dev)
5674 struct drm_i915_private *dev_priv = dev->dev_private;
5676 if (I915_HAS_FBC(dev)) {
5677 if (HAS_PCH_SPLIT(dev)) {
5678 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5679 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5680 dev_priv->display.enable_fbc =
5683 dev_priv->display.enable_fbc =
5684 ironlake_enable_fbc;
5685 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5686 } else if (IS_GM45(dev)) {
5687 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5688 dev_priv->display.enable_fbc = g4x_enable_fbc;
5689 dev_priv->display.disable_fbc = g4x_disable_fbc;
5690 } else if (IS_CRESTLINE(dev)) {
5691 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5692 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5693 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5695 /* 855GM needs testing */
5699 if (IS_PINEVIEW(dev))
5700 i915_pineview_get_mem_freq(dev);
5701 else if (IS_GEN5(dev))
5702 i915_ironlake_get_mem_freq(dev);
5704 /* For FIFO watermark updates */
5705 if (HAS_PCH_SPLIT(dev)) {
5706 intel_setup_wm_latency(dev);
5709 if (dev_priv->wm.pri_latency[1] &&
5710 dev_priv->wm.spr_latency[1] &&
5711 dev_priv->wm.cur_latency[1])
5712 dev_priv->display.update_wm = ironlake_update_wm;
5714 DRM_DEBUG_KMS("Failed to get proper latency. "
5716 dev_priv->display.update_wm = NULL;
5718 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5719 } else if (IS_GEN6(dev)) {
5720 if (dev_priv->wm.pri_latency[0] &&
5721 dev_priv->wm.spr_latency[0] &&
5722 dev_priv->wm.cur_latency[0]) {
5723 dev_priv->display.update_wm = sandybridge_update_wm;
5724 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5726 DRM_DEBUG_KMS("Failed to read display plane latency. "
5728 dev_priv->display.update_wm = NULL;
5730 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5731 } else if (IS_IVYBRIDGE(dev)) {
5732 if (dev_priv->wm.pri_latency[0] &&
5733 dev_priv->wm.spr_latency[0] &&
5734 dev_priv->wm.cur_latency[0]) {
5735 dev_priv->display.update_wm = ivybridge_update_wm;
5736 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5738 DRM_DEBUG_KMS("Failed to read display plane latency. "
5740 dev_priv->display.update_wm = NULL;
5742 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5743 } else if (IS_HASWELL(dev)) {
5744 if (dev_priv->wm.pri_latency[0] &&
5745 dev_priv->wm.spr_latency[0] &&
5746 dev_priv->wm.cur_latency[0]) {
5747 dev_priv->display.update_wm = haswell_update_wm;
5748 dev_priv->display.update_sprite_wm =
5749 haswell_update_sprite_wm;
5751 DRM_DEBUG_KMS("Failed to read display plane latency. "
5753 dev_priv->display.update_wm = NULL;
5755 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5757 dev_priv->display.update_wm = NULL;
5758 } else if (IS_VALLEYVIEW(dev)) {
5759 dev_priv->display.update_wm = valleyview_update_wm;
5760 dev_priv->display.init_clock_gating =
5761 valleyview_init_clock_gating;
5762 } else if (IS_PINEVIEW(dev)) {
5763 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5766 dev_priv->mem_freq)) {
5767 DRM_INFO("failed to find known CxSR latency "
5768 "(found ddr%s fsb freq %d, mem freq %d), "
5770 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5771 dev_priv->fsb_freq, dev_priv->mem_freq);
5772 /* Disable CxSR and never update its watermark again */
5773 pineview_disable_cxsr(dev);
5774 dev_priv->display.update_wm = NULL;
5776 dev_priv->display.update_wm = pineview_update_wm;
5777 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5778 } else if (IS_G4X(dev)) {
5779 dev_priv->display.update_wm = g4x_update_wm;
5780 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5781 } else if (IS_GEN4(dev)) {
5782 dev_priv->display.update_wm = i965_update_wm;
5783 if (IS_CRESTLINE(dev))
5784 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5785 else if (IS_BROADWATER(dev))
5786 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5787 } else if (IS_GEN3(dev)) {
5788 dev_priv->display.update_wm = i9xx_update_wm;
5789 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5790 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5791 } else if (IS_I865G(dev)) {
5792 dev_priv->display.update_wm = i830_update_wm;
5793 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5794 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5795 } else if (IS_I85X(dev)) {
5796 dev_priv->display.update_wm = i9xx_update_wm;
5797 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5798 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5800 dev_priv->display.update_wm = i830_update_wm;
5801 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5803 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5805 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5809 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5811 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5813 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5814 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5818 I915_WRITE(GEN6_PCODE_DATA, *val);
5819 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5821 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5823 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5827 *val = I915_READ(GEN6_PCODE_DATA);
5828 I915_WRITE(GEN6_PCODE_DATA, 0);
5833 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5835 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5837 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5838 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5842 I915_WRITE(GEN6_PCODE_DATA, val);
5843 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5845 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5847 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5851 I915_WRITE(GEN6_PCODE_DATA, 0);
5856 int vlv_gpu_freq(int ddr_freq, int val)
5877 return ((val - 0xbd) * mult) + base;
5880 int vlv_freq_opcode(int ddr_freq, int val)
5911 void intel_pm_init(struct drm_device *dev)
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5915 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5916 intel_gen6_powersave_work);