2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
46 static void i8xx_disable_fbc(struct drm_device *dev)
48 struct drm_i915_private *dev_priv = dev->dev_private;
51 /* Disable compression */
52 fbc_ctl = I915_READ(FBC_CONTROL);
53 if ((fbc_ctl & FBC_CTL_EN) == 0)
56 fbc_ctl &= ~FBC_CTL_EN;
57 I915_WRITE(FBC_CONTROL, fbc_ctl);
59 /* Wait for compressing bit to clear */
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
61 DRM_DEBUG_KMS("FBC idle timed out\n");
65 DRM_DEBUG_KMS("disabled FBC\n");
68 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
70 struct drm_device *dev = crtc->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 struct drm_framebuffer *fb = crtc->fb;
73 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
74 struct drm_i915_gem_object *obj = intel_fb->obj;
75 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
78 u32 fbc_ctl, fbc_ctl2;
80 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
81 if (fb->pitches[0] < cfb_pitch)
82 cfb_pitch = fb->pitches[0];
84 /* FBC_CTL wants 64B units */
85 cfb_pitch = (cfb_pitch / 64) - 1;
86 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
89 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
90 I915_WRITE(FBC_TAG + (i * 4), 0);
93 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
95 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
96 I915_WRITE(FBC_FENCE_OFF, crtc->y);
99 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
101 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
102 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
103 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
104 fbc_ctl |= obj->fence_reg;
105 I915_WRITE(FBC_CONTROL, fbc_ctl);
107 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
108 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
111 static bool i8xx_fbc_enabled(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
115 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
118 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
120 struct drm_device *dev = crtc->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_framebuffer *fb = crtc->fb;
123 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
124 struct drm_i915_gem_object *obj = intel_fb->obj;
125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
126 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
127 unsigned long stall_watermark = 200;
130 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
131 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
132 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
134 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
135 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
136 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
137 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
140 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
142 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
145 static void g4x_disable_fbc(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 /* Disable compression */
151 dpfc_ctl = I915_READ(DPFC_CONTROL);
152 if (dpfc_ctl & DPFC_CTL_EN) {
153 dpfc_ctl &= ~DPFC_CTL_EN;
154 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
156 DRM_DEBUG_KMS("disabled FBC\n");
160 static bool g4x_fbc_enabled(struct drm_device *dev)
162 struct drm_i915_private *dev_priv = dev->dev_private;
164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
167 static void sandybridge_blit_fbc_update(struct drm_device *dev)
169 struct drm_i915_private *dev_priv = dev->dev_private;
172 /* Make sure blitter notifies FBC of writes */
173 gen6_gt_force_wake_get(dev_priv);
174 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
175 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
176 GEN6_BLITTER_LOCK_SHIFT;
177 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
178 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
179 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
180 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
181 GEN6_BLITTER_LOCK_SHIFT);
182 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
183 POSTING_READ(GEN6_BLITTER_ECOSKPD);
184 gen6_gt_force_wake_put(dev_priv);
187 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
189 struct drm_device *dev = crtc->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct drm_framebuffer *fb = crtc->fb;
192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
193 struct drm_i915_gem_object *obj = intel_fb->obj;
194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
195 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
196 unsigned long stall_watermark = 200;
199 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
200 dpfc_ctl &= DPFC_RESERVED;
201 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
202 /* Set persistent mode for front-buffer rendering, ala X. */
203 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
207 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
208 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
209 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
210 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
211 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
213 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
216 I915_WRITE(SNB_DPFC_CTL_SA,
217 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
218 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
219 sandybridge_blit_fbc_update(dev);
222 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
225 static void ironlake_disable_fbc(struct drm_device *dev)
227 struct drm_i915_private *dev_priv = dev->dev_private;
230 /* Disable compression */
231 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
232 if (dpfc_ctl & DPFC_CTL_EN) {
233 dpfc_ctl &= ~DPFC_CTL_EN;
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
236 if (IS_IVYBRIDGE(dev))
237 /* WaFbcDisableDpfcClockGating:ivb */
238 I915_WRITE(ILK_DSPCLK_GATE_D,
239 I915_READ(ILK_DSPCLK_GATE_D) &
240 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
243 /* WaFbcDisableDpfcClockGating:hsw */
244 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
245 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
246 ~HSW_DPFC_GATING_DISABLE);
248 DRM_DEBUG_KMS("disabled FBC\n");
252 static bool ironlake_fbc_enabled(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
259 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
261 struct drm_device *dev = crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_framebuffer *fb = crtc->fb;
264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
265 struct drm_i915_gem_object *obj = intel_fb->obj;
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
268 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
270 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
271 IVB_DPFC_CTL_FENCE_EN |
272 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
274 if (IS_IVYBRIDGE(dev)) {
275 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
276 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
277 /* WaFbcDisableDpfcClockGating:ivb */
278 I915_WRITE(ILK_DSPCLK_GATE_D,
279 I915_READ(ILK_DSPCLK_GATE_D) |
280 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
282 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
283 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
284 HSW_BYPASS_FBC_QUEUE);
285 /* WaFbcDisableDpfcClockGating:hsw */
286 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
287 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
288 HSW_DPFC_GATING_DISABLE);
291 I915_WRITE(SNB_DPFC_CTL_SA,
292 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
293 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
295 sandybridge_blit_fbc_update(dev);
297 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
300 bool intel_fbc_enabled(struct drm_device *dev)
302 struct drm_i915_private *dev_priv = dev->dev_private;
304 if (!dev_priv->display.fbc_enabled)
307 return dev_priv->display.fbc_enabled(dev);
310 static void intel_fbc_work_fn(struct work_struct *__work)
312 struct intel_fbc_work *work =
313 container_of(to_delayed_work(__work),
314 struct intel_fbc_work, work);
315 struct drm_device *dev = work->crtc->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
318 mutex_lock(&dev->struct_mutex);
319 if (work == dev_priv->fbc.fbc_work) {
320 /* Double check that we haven't switched fb without cancelling
323 if (work->crtc->fb == work->fb) {
324 dev_priv->display.enable_fbc(work->crtc,
327 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
328 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
329 dev_priv->fbc.y = work->crtc->y;
332 dev_priv->fbc.fbc_work = NULL;
334 mutex_unlock(&dev->struct_mutex);
339 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
341 if (dev_priv->fbc.fbc_work == NULL)
344 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
346 /* Synchronisation is provided by struct_mutex and checking of
347 * dev_priv->fbc.fbc_work, so we can perform the cancellation
348 * entirely asynchronously.
350 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
351 /* tasklet was killed before being run, clean up */
352 kfree(dev_priv->fbc.fbc_work);
354 /* Mark the work as no longer wanted so that if it does
355 * wake-up (because the work was already running and waiting
356 * for our mutex), it will discover that is no longer
359 dev_priv->fbc.fbc_work = NULL;
362 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
364 struct intel_fbc_work *work;
365 struct drm_device *dev = crtc->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
368 if (!dev_priv->display.enable_fbc)
371 intel_cancel_fbc_work(dev_priv);
373 work = kzalloc(sizeof(*work), GFP_KERNEL);
375 DRM_ERROR("Failed to allocate FBC work structure\n");
376 dev_priv->display.enable_fbc(crtc, interval);
382 work->interval = interval;
383 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
385 dev_priv->fbc.fbc_work = work;
387 /* Delay the actual enabling to let pageflipping cease and the
388 * display to settle before starting the compression. Note that
389 * this delay also serves a second purpose: it allows for a
390 * vblank to pass after disabling the FBC before we attempt
391 * to modify the control registers.
393 * A more complicated solution would involve tracking vblanks
394 * following the termination of the page-flipping sequence
395 * and indeed performing the enable as a co-routine and not
396 * waiting synchronously upon the vblank.
398 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
400 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
403 void intel_disable_fbc(struct drm_device *dev)
405 struct drm_i915_private *dev_priv = dev->dev_private;
407 intel_cancel_fbc_work(dev_priv);
409 if (!dev_priv->display.disable_fbc)
412 dev_priv->display.disable_fbc(dev);
413 dev_priv->fbc.plane = -1;
416 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
417 enum no_fbc_reason reason)
419 if (dev_priv->fbc.no_fbc_reason == reason)
422 dev_priv->fbc.no_fbc_reason = reason;
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
443 * We need to enable/disable FBC on a global basis.
445 void intel_update_fbc(struct drm_device *dev)
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
453 const struct drm_display_mode *adjusted_mode;
454 unsigned int max_width, max_height;
456 if (!I915_HAS_FBC(dev)) {
457 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
461 if (!i915_powersave) {
462 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
463 DRM_DEBUG_KMS("fbc disabled per module param\n");
468 * If FBC is already on, we just have to verify that we can
469 * keep it that way...
470 * Need to disable if:
471 * - more than one pipe is active
472 * - changing FBC params (stride, fence, mode)
473 * - new fb is too large to fit in compressed buffer
474 * - going to an unsupported config (interlace, pixel multiply, etc.)
476 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
477 if (intel_crtc_active(tmp_crtc) &&
478 to_intel_crtc(tmp_crtc)->primary_enabled) {
480 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
481 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
488 if (!crtc || crtc->fb == NULL) {
489 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
490 DRM_DEBUG_KMS("no output, disabling\n");
494 intel_crtc = to_intel_crtc(crtc);
496 intel_fb = to_intel_framebuffer(fb);
498 adjusted_mode = &intel_crtc->config.adjusted_mode;
500 if (i915_enable_fbc < 0 &&
501 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
502 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
503 DRM_DEBUG_KMS("disabled per chip default\n");
506 if (!i915_enable_fbc) {
507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
511 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
512 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
513 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
514 DRM_DEBUG_KMS("mode incompatible with compression, "
519 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 if (intel_crtc->config.pipe_src_w > max_width ||
527 intel_crtc->config.pipe_src_h > max_height) {
528 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
529 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
532 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
533 intel_crtc->plane != 0) {
534 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
535 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
539 /* The use of a CPU fence is mandatory in order to detect writes
540 * by the CPU to the scanout and trigger updates to the FBC.
542 if (obj->tiling_mode != I915_TILING_X ||
543 obj->fence_reg == I915_FENCE_REG_NONE) {
544 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
545 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
549 /* If the kernel debugger is active, always disable compression */
553 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
554 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
555 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
559 /* If the scanout has not changed, don't modify the FBC settings.
560 * Note that we make the fundamental assumption that the fb->obj
561 * cannot be unpinned (and have its GTT offset and fence revoked)
562 * without first being decoupled from the scanout and FBC disabled.
564 if (dev_priv->fbc.plane == intel_crtc->plane &&
565 dev_priv->fbc.fb_id == fb->base.id &&
566 dev_priv->fbc.y == crtc->y)
569 if (intel_fbc_enabled(dev)) {
570 /* We update FBC along two paths, after changing fb/crtc
571 * configuration (modeswitching) and after page-flipping
572 * finishes. For the latter, we know that not only did
573 * we disable the FBC at the start of the page-flip
574 * sequence, but also more than one vblank has passed.
576 * For the former case of modeswitching, it is possible
577 * to switch between two FBC valid configurations
578 * instantaneously so we do need to disable the FBC
579 * before we can modify its control registers. We also
580 * have to wait for the next vblank for that to take
581 * effect. However, since we delay enabling FBC we can
582 * assume that a vblank has passed since disabling and
583 * that we can safely alter the registers in the deferred
586 * In the scenario that we go from a valid to invalid
587 * and then back to valid FBC configuration we have
588 * no strict enforcement that a vblank occurred since
589 * disabling the FBC. However, along all current pipe
590 * disabling paths we do need to wait for a vblank at
591 * some point. And we wait before enabling FBC anyway.
593 DRM_DEBUG_KMS("disabling active FBC for update\n");
594 intel_disable_fbc(dev);
597 intel_enable_fbc(crtc, 500);
598 dev_priv->fbc.no_fbc_reason = FBC_OK;
602 /* Multiple disables should be harmless */
603 if (intel_fbc_enabled(dev)) {
604 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
605 intel_disable_fbc(dev);
607 i915_gem_stolen_cleanup_compression(dev);
610 static void i915_pineview_get_mem_freq(struct drm_device *dev)
612 drm_i915_private_t *dev_priv = dev->dev_private;
615 tmp = I915_READ(CLKCFG);
617 switch (tmp & CLKCFG_FSB_MASK) {
619 dev_priv->fsb_freq = 533; /* 133*4 */
622 dev_priv->fsb_freq = 800; /* 200*4 */
625 dev_priv->fsb_freq = 667; /* 167*4 */
628 dev_priv->fsb_freq = 400; /* 100*4 */
632 switch (tmp & CLKCFG_MEM_MASK) {
634 dev_priv->mem_freq = 533;
637 dev_priv->mem_freq = 667;
640 dev_priv->mem_freq = 800;
644 /* detect pineview DDR3 setting */
645 tmp = I915_READ(CSHRDDR3CTL);
646 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
649 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
651 drm_i915_private_t *dev_priv = dev->dev_private;
654 ddrpll = I915_READ16(DDRMPLL1);
655 csipll = I915_READ16(CSIPLL0);
657 switch (ddrpll & 0xff) {
659 dev_priv->mem_freq = 800;
662 dev_priv->mem_freq = 1066;
665 dev_priv->mem_freq = 1333;
668 dev_priv->mem_freq = 1600;
671 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
673 dev_priv->mem_freq = 0;
677 dev_priv->ips.r_t = dev_priv->mem_freq;
679 switch (csipll & 0x3ff) {
681 dev_priv->fsb_freq = 3200;
684 dev_priv->fsb_freq = 3733;
687 dev_priv->fsb_freq = 4266;
690 dev_priv->fsb_freq = 4800;
693 dev_priv->fsb_freq = 5333;
696 dev_priv->fsb_freq = 5866;
699 dev_priv->fsb_freq = 6400;
702 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
704 dev_priv->fsb_freq = 0;
708 if (dev_priv->fsb_freq == 3200) {
709 dev_priv->ips.c_m = 0;
710 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
711 dev_priv->ips.c_m = 1;
713 dev_priv->ips.c_m = 2;
717 static const struct cxsr_latency cxsr_latency_table[] = {
718 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
719 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
720 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
721 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
722 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
724 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
725 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
726 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
727 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
728 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
730 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
731 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
732 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
733 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
734 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
736 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
737 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
738 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
739 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
740 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
742 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
743 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
744 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
745 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
746 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
748 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
749 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
750 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
751 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
752 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
755 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
760 const struct cxsr_latency *latency;
763 if (fsb == 0 || mem == 0)
766 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
767 latency = &cxsr_latency_table[i];
768 if (is_desktop == latency->is_desktop &&
769 is_ddr3 == latency->is_ddr3 &&
770 fsb == latency->fsb_freq && mem == latency->mem_freq)
774 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
779 static void pineview_disable_cxsr(struct drm_device *dev)
781 struct drm_i915_private *dev_priv = dev->dev_private;
783 /* deactivate cxsr */
784 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
788 * Latency for FIFO fetches is dependent on several factors:
789 * - memory configuration (speed, channels)
791 * - current MCH state
792 * It can be fairly high in some situations, so here we assume a fairly
793 * pessimal value. It's a tradeoff between extra memory fetches (if we
794 * set this value too high, the FIFO will fetch frequently to stay full)
795 * and power consumption (set it too low to save power and we might see
796 * FIFO underruns and display "flicker").
798 * A value of 5us seems to be a good balance; safe for very low end
799 * platforms but not overly aggressive on lower latency configs.
801 static const int latency_ns = 5000;
803 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 uint32_t dsparb = I915_READ(DSPARB);
809 size = dsparb & 0x7f;
811 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
819 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
825 size = dsparb & 0x1ff;
827 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
828 size >>= 1; /* Convert to cachelines */
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
836 static int i845_get_fifo_size(struct drm_device *dev, int plane)
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
842 size = dsparb & 0x7f;
843 size >>= 2; /* Convert to cachelines */
845 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 static int i830_get_fifo_size(struct drm_device *dev, int plane)
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 uint32_t dsparb = I915_READ(DSPARB);
858 size = dsparb & 0x7f;
859 size >>= 1; /* Convert to cachelines */
861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
862 plane ? "B" : "A", size);
867 /* Pineview has different values for various configs */
868 static const struct intel_watermark_params pineview_display_wm = {
869 PINEVIEW_DISPLAY_FIFO,
873 PINEVIEW_FIFO_LINE_SIZE
875 static const struct intel_watermark_params pineview_display_hplloff_wm = {
876 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_DFT_HPLLOFF_WM,
880 PINEVIEW_FIFO_LINE_SIZE
882 static const struct intel_watermark_params pineview_cursor_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE,
889 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
890 PINEVIEW_CURSOR_FIFO,
891 PINEVIEW_CURSOR_MAX_WM,
892 PINEVIEW_CURSOR_DFT_WM,
893 PINEVIEW_CURSOR_GUARD_WM,
894 PINEVIEW_FIFO_LINE_SIZE
896 static const struct intel_watermark_params g4x_wm_info = {
903 static const struct intel_watermark_params g4x_cursor_wm_info = {
910 static const struct intel_watermark_params valleyview_wm_info = {
911 VALLEYVIEW_FIFO_SIZE,
917 static const struct intel_watermark_params valleyview_cursor_wm_info = {
919 VALLEYVIEW_CURSOR_MAX_WM,
924 static const struct intel_watermark_params i965_cursor_wm_info = {
931 static const struct intel_watermark_params i945_wm_info = {
938 static const struct intel_watermark_params i915_wm_info = {
945 static const struct intel_watermark_params i855_wm_info = {
952 static const struct intel_watermark_params i830_wm_info = {
960 static const struct intel_watermark_params ironlake_display_wm_info = {
967 static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 static const struct intel_watermark_params ironlake_display_srwm_info = {
976 ILK_DISPLAY_MAX_SRWM,
977 ILK_DISPLAY_DFT_SRWM,
981 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
989 static const struct intel_watermark_params sandybridge_display_wm_info = {
996 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004 SNB_DISPLAY_SR_FIFO,
1005 SNB_DISPLAY_MAX_SRWM,
1006 SNB_DISPLAY_DFT_SRWM,
1010 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1012 SNB_CURSOR_MAX_SRWM,
1013 SNB_CURSOR_DFT_SRWM,
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1037 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1041 unsigned long latency_ns)
1043 long entries_required, wm_size;
1046 * Note: we need to make sure we don't overflow for various clock &
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1065 wm_size = wm->default_wm;
1069 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1071 struct drm_crtc *crtc, *enabled = NULL;
1073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1074 if (intel_crtc_active(crtc)) {
1084 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1086 struct drm_device *dev = unused_crtc->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 pineview_disable_cxsr(dev);
1101 crtc = single_enabled_crtc(dev);
1103 const struct drm_display_mode *adjusted_mode;
1104 int pixel_size = crtc->fb->bits_per_pixel / 8;
1107 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108 clock = adjusted_mode->crtc_clock;
1111 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->display_sr);
1114 reg = I915_READ(DSPFW1);
1115 reg &= ~DSPFW_SR_MASK;
1116 reg |= wm << DSPFW_SR_SHIFT;
1117 I915_WRITE(DSPFW1, reg);
1118 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1121 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->cursor_sr);
1124 reg = I915_READ(DSPFW3);
1125 reg &= ~DSPFW_CURSOR_SR_MASK;
1126 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127 I915_WRITE(DSPFW3, reg);
1129 /* Display HPLL off SR */
1130 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131 pineview_display_hplloff_wm.fifo_size,
1132 pixel_size, latency->display_hpll_disable);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_HPLL_SR_MASK;
1135 reg |= wm & DSPFW_HPLL_SR_MASK;
1136 I915_WRITE(DSPFW3, reg);
1138 /* cursor HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->cursor_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1150 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 pineview_disable_cxsr(dev);
1154 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1158 static bool g4x_compute_wm0(struct drm_device *dev,
1160 const struct intel_watermark_params *display,
1161 int display_latency_ns,
1162 const struct intel_watermark_params *cursor,
1163 int cursor_latency_ns,
1167 struct drm_crtc *crtc;
1168 const struct drm_display_mode *adjusted_mode;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1173 crtc = intel_get_crtc_for_plane(dev, plane);
1174 if (!intel_crtc_active(crtc)) {
1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1180 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1181 clock = adjusted_mode->crtc_clock;
1182 htotal = adjusted_mode->htotal;
1183 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1184 pixel_size = crtc->fb->bits_per_pixel / 8;
1186 /* Use the small buffer method to calculate plane watermark */
1187 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1190 entries += tlb_miss;
1191 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192 *plane_wm = entries + display->guard_size;
1193 if (*plane_wm > (int)display->max_wm)
1194 *plane_wm = display->max_wm;
1196 /* Use the large buffer method to calculate cursor watermark */
1197 line_time_us = ((htotal * 1000) / clock);
1198 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199 entries = line_count * 64 * pixel_size;
1200 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1202 entries += tlb_miss;
1203 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 *cursor_wm = entries + cursor->guard_size;
1205 if (*cursor_wm > (int)cursor->max_wm)
1206 *cursor_wm = (int)cursor->max_wm;
1212 * Check the wm result.
1214 * If any calculated watermark values is larger than the maximum value that
1215 * can be programmed into the associated watermark register, that watermark
1218 static bool g4x_check_srwm(struct drm_device *dev,
1219 int display_wm, int cursor_wm,
1220 const struct intel_watermark_params *display,
1221 const struct intel_watermark_params *cursor)
1223 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224 display_wm, cursor_wm);
1226 if (display_wm > display->max_wm) {
1227 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228 display_wm, display->max_wm);
1232 if (cursor_wm > cursor->max_wm) {
1233 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234 cursor_wm, cursor->max_wm);
1238 if (!(display_wm || cursor_wm)) {
1239 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1246 static bool g4x_compute_srwm(struct drm_device *dev,
1249 const struct intel_watermark_params *display,
1250 const struct intel_watermark_params *cursor,
1251 int *display_wm, int *cursor_wm)
1253 struct drm_crtc *crtc;
1254 const struct drm_display_mode *adjusted_mode;
1255 int hdisplay, htotal, pixel_size, clock;
1256 unsigned long line_time_us;
1257 int line_count, line_size;
1262 *display_wm = *cursor_wm = 0;
1266 crtc = intel_get_crtc_for_plane(dev, plane);
1267 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1268 clock = adjusted_mode->crtc_clock;
1269 htotal = adjusted_mode->htotal;
1270 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1271 pixel_size = crtc->fb->bits_per_pixel / 8;
1273 line_time_us = (htotal * 1000) / clock;
1274 line_count = (latency_ns / line_time_us + 1000) / 1000;
1275 line_size = hdisplay * pixel_size;
1277 /* Use the minimum of the small and large buffer method for primary */
1278 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279 large = line_count * line_size;
1281 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282 *display_wm = entries + display->guard_size;
1284 /* calculate the self-refresh watermark for display cursor */
1285 entries = line_count * pixel_size * 64;
1286 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287 *cursor_wm = entries + cursor->guard_size;
1289 return g4x_check_srwm(dev,
1290 *display_wm, *cursor_wm,
1294 static bool vlv_compute_drain_latency(struct drm_device *dev,
1296 int *plane_prec_mult,
1298 int *cursor_prec_mult,
1301 struct drm_crtc *crtc;
1302 int clock, pixel_size;
1305 crtc = intel_get_crtc_for_plane(dev, plane);
1306 if (!intel_crtc_active(crtc))
1309 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1310 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1312 entries = (clock / 1000) * pixel_size;
1313 *plane_prec_mult = (entries > 256) ?
1314 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1318 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1319 *cursor_prec_mult = (entries > 256) ?
1320 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1327 * Update drain latency registers of memory arbiter
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1334 static void vlv_update_drain_latency(struct drm_device *dev)
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1342 /* For plane A, Cursor A */
1343 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344 &cursor_prec_mult, &cursora_dl)) {
1345 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1350 I915_WRITE(VLV_DDL1, cursora_prec |
1351 (cursora_dl << DDL_CURSORA_SHIFT) |
1352 planea_prec | planea_dl);
1355 /* For plane B, Cursor B */
1356 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357 &cursor_prec_mult, &cursorb_dl)) {
1358 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1363 I915_WRITE(VLV_DDL2, cursorb_prec |
1364 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365 planeb_prec | planeb_dl);
1369 #define single_plane_enabled(mask) is_power_of_2(mask)
1371 static void valleyview_update_wm(struct drm_crtc *crtc)
1373 struct drm_device *dev = crtc->dev;
1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 int ignore_plane_sr, ignore_cursor_sr;
1379 unsigned int enabled = 0;
1381 vlv_update_drain_latency(dev);
1383 if (g4x_compute_wm0(dev, PIPE_A,
1384 &valleyview_wm_info, latency_ns,
1385 &valleyview_cursor_wm_info, latency_ns,
1386 &planea_wm, &cursora_wm))
1387 enabled |= 1 << PIPE_A;
1389 if (g4x_compute_wm0(dev, PIPE_B,
1390 &valleyview_wm_info, latency_ns,
1391 &valleyview_cursor_wm_info, latency_ns,
1392 &planeb_wm, &cursorb_wm))
1393 enabled |= 1 << PIPE_B;
1395 if (single_plane_enabled(enabled) &&
1396 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 &valleyview_wm_info,
1399 &valleyview_cursor_wm_info,
1400 &plane_sr, &ignore_cursor_sr) &&
1401 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 &valleyview_wm_info,
1404 &valleyview_cursor_wm_info,
1405 &ignore_plane_sr, &cursor_sr)) {
1406 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1408 I915_WRITE(FW_BLC_SELF_VLV,
1409 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1410 plane_sr = cursor_sr = 0;
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414 planea_wm, cursora_wm,
1415 planeb_wm, cursorb_wm,
1416 plane_sr, cursor_sr);
1419 (plane_sr << DSPFW_SR_SHIFT) |
1420 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1425 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1431 static void g4x_update_wm(struct drm_crtc *crtc)
1433 struct drm_device *dev = crtc->dev;
1434 static const int sr_latency_ns = 12000;
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437 int plane_sr, cursor_sr;
1438 unsigned int enabled = 0;
1440 if (g4x_compute_wm0(dev, PIPE_A,
1441 &g4x_wm_info, latency_ns,
1442 &g4x_cursor_wm_info, latency_ns,
1443 &planea_wm, &cursora_wm))
1444 enabled |= 1 << PIPE_A;
1446 if (g4x_compute_wm0(dev, PIPE_B,
1447 &g4x_wm_info, latency_ns,
1448 &g4x_cursor_wm_info, latency_ns,
1449 &planeb_wm, &cursorb_wm))
1450 enabled |= 1 << PIPE_B;
1452 if (single_plane_enabled(enabled) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1456 &g4x_cursor_wm_info,
1457 &plane_sr, &cursor_sr)) {
1458 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1460 I915_WRITE(FW_BLC_SELF,
1461 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1462 plane_sr = cursor_sr = 0;
1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466 planea_wm, cursora_wm,
1467 planeb_wm, cursorb_wm,
1468 plane_sr, cursor_sr);
1471 (plane_sr << DSPFW_SR_SHIFT) |
1472 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1476 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1477 (cursora_wm << DSPFW_CURSORA_SHIFT));
1478 /* HPLL off in SR has some issues on G4x... disable it */
1480 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1481 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1484 static void i965_update_wm(struct drm_crtc *unused_crtc)
1486 struct drm_device *dev = unused_crtc->dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 struct drm_crtc *crtc;
1492 /* Calc sr entries for one plane configs */
1493 crtc = single_enabled_crtc(dev);
1495 /* self-refresh has much higher latency */
1496 static const int sr_latency_ns = 12000;
1497 const struct drm_display_mode *adjusted_mode =
1498 &to_intel_crtc(crtc)->config.adjusted_mode;
1499 int clock = adjusted_mode->crtc_clock;
1500 int htotal = adjusted_mode->htotal;
1501 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1502 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503 unsigned long line_time_us;
1506 line_time_us = ((htotal * 1000) / clock);
1508 /* Use ns/us then divide to preserve precision */
1509 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510 pixel_size * hdisplay;
1511 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512 srwm = I965_FIFO_SIZE - entries;
1516 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 entries = DIV_ROUND_UP(entries,
1522 i965_cursor_wm_info.cacheline_size);
1523 cursor_sr = i965_cursor_wm_info.fifo_size -
1524 (entries + i965_cursor_wm_info.guard_size);
1526 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527 cursor_sr = i965_cursor_wm_info.max_wm;
1529 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530 "cursor %d\n", srwm, cursor_sr);
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1535 /* Turn off self refresh if both pipes are enabled */
1536 if (IS_CRESTLINE(dev))
1537 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1544 /* 965 has limitations... */
1545 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546 (8 << 16) | (8 << 8) | (8 << 0));
1547 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548 /* update cursor SR watermark */
1549 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1552 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1554 struct drm_device *dev = unused_crtc->dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 const struct intel_watermark_params *wm_info;
1561 int planea_wm, planeb_wm;
1562 struct drm_crtc *crtc, *enabled = NULL;
1565 wm_info = &i945_wm_info;
1566 else if (!IS_GEN2(dev))
1567 wm_info = &i915_wm_info;
1569 wm_info = &i855_wm_info;
1571 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572 crtc = intel_get_crtc_for_plane(dev, 0);
1573 if (intel_crtc_active(crtc)) {
1574 const struct drm_display_mode *adjusted_mode;
1575 int cpp = crtc->fb->bits_per_pixel / 8;
1579 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1581 wm_info, fifo_size, cpp,
1585 planea_wm = fifo_size - wm_info->guard_size;
1587 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588 crtc = intel_get_crtc_for_plane(dev, 1);
1589 if (intel_crtc_active(crtc)) {
1590 const struct drm_display_mode *adjusted_mode;
1591 int cpp = crtc->fb->bits_per_pixel / 8;
1595 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1597 wm_info, fifo_size, cpp,
1599 if (enabled == NULL)
1604 planeb_wm = fifo_size - wm_info->guard_size;
1606 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609 * Overlay gets an aggressive default since video jitter is bad.
1613 /* Play safe and disable self-refresh before adjusting watermarks. */
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616 else if (IS_I915GM(dev))
1617 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1619 /* Calc sr entries for one plane configs */
1620 if (HAS_FW_BLC(dev) && enabled) {
1621 /* self-refresh has much higher latency */
1622 static const int sr_latency_ns = 6000;
1623 const struct drm_display_mode *adjusted_mode =
1624 &to_intel_crtc(enabled)->config.adjusted_mode;
1625 int clock = adjusted_mode->crtc_clock;
1626 int htotal = adjusted_mode->htotal;
1627 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1628 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629 unsigned long line_time_us;
1632 line_time_us = (htotal * 1000) / clock;
1634 /* Use ns/us then divide to preserve precision */
1635 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636 pixel_size * hdisplay;
1637 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639 srwm = wm_info->fifo_size - entries;
1643 if (IS_I945G(dev) || IS_I945GM(dev))
1644 I915_WRITE(FW_BLC_SELF,
1645 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646 else if (IS_I915GM(dev))
1647 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1650 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651 planea_wm, planeb_wm, cwm, srwm);
1653 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654 fwater_hi = (cwm & 0x1f);
1656 /* Set request length to 8 cachelines per fetch */
1657 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658 fwater_hi = fwater_hi | (1 << 8);
1660 I915_WRITE(FW_BLC, fwater_lo);
1661 I915_WRITE(FW_BLC2, fwater_hi);
1663 if (HAS_FW_BLC(dev)) {
1665 if (IS_I945G(dev) || IS_I945GM(dev))
1666 I915_WRITE(FW_BLC_SELF,
1667 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668 else if (IS_I915GM(dev))
1669 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670 DRM_DEBUG_KMS("memory self refresh enabled\n");
1672 DRM_DEBUG_KMS("memory self refresh disabled\n");
1676 static void i830_update_wm(struct drm_crtc *unused_crtc)
1678 struct drm_device *dev = unused_crtc->dev;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
1681 const struct drm_display_mode *adjusted_mode;
1685 crtc = single_enabled_crtc(dev);
1689 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1692 dev_priv->display.get_fifo_size(dev, 0),
1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1699 I915_WRITE(FW_BLC, fwater_lo);
1703 * Check the wm result.
1705 * If any calculated watermark values is larger than the maximum value that
1706 * can be programmed into the associated watermark register, that watermark
1709 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710 int fbc_wm, int display_wm, int cursor_wm,
1711 const struct intel_watermark_params *display,
1712 const struct intel_watermark_params *cursor)
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1716 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1719 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721 fbc_wm, SNB_FBC_MAX_SRWM, level);
1723 /* fbc has it's own way to disable FBC WM */
1724 I915_WRITE(DISP_ARB_CTL,
1725 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1727 } else if (INTEL_INFO(dev)->gen >= 6) {
1728 /* enable FBC WM (except on ILK, where it must remain off) */
1729 I915_WRITE(DISP_ARB_CTL,
1730 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1733 if (display_wm > display->max_wm) {
1734 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1739 if (cursor_wm > cursor->max_wm) {
1740 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1745 if (!(fbc_wm || display_wm || cursor_wm)) {
1746 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1754 * Compute watermark values of WM[1-3],
1756 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1758 const struct intel_watermark_params *display,
1759 const struct intel_watermark_params *cursor,
1760 int *fbc_wm, int *display_wm, int *cursor_wm)
1762 struct drm_crtc *crtc;
1763 const struct drm_display_mode *adjusted_mode;
1764 unsigned long line_time_us;
1765 int hdisplay, htotal, pixel_size, clock;
1766 int line_count, line_size;
1771 *fbc_wm = *display_wm = *cursor_wm = 0;
1775 crtc = intel_get_crtc_for_plane(dev, plane);
1776 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1777 clock = adjusted_mode->crtc_clock;
1778 htotal = adjusted_mode->htotal;
1779 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1780 pixel_size = crtc->fb->bits_per_pixel / 8;
1782 line_time_us = (htotal * 1000) / clock;
1783 line_count = (latency_ns / line_time_us + 1000) / 1000;
1784 line_size = hdisplay * pixel_size;
1786 /* Use the minimum of the small and large buffer method for primary */
1787 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788 large = line_count * line_size;
1790 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791 *display_wm = entries + display->guard_size;
1795 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1797 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1799 /* calculate the self-refresh watermark for display cursor */
1800 entries = line_count * pixel_size * 64;
1801 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802 *cursor_wm = entries + cursor->guard_size;
1804 return ironlake_check_srwm(dev, level,
1805 *fbc_wm, *display_wm, *cursor_wm,
1809 static void ironlake_update_wm(struct drm_crtc *crtc)
1811 struct drm_device *dev = crtc->dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 int fbc_wm, plane_wm, cursor_wm;
1814 unsigned int enabled;
1817 if (g4x_compute_wm0(dev, PIPE_A,
1818 &ironlake_display_wm_info,
1819 dev_priv->wm.pri_latency[0] * 100,
1820 &ironlake_cursor_wm_info,
1821 dev_priv->wm.cur_latency[0] * 100,
1822 &plane_wm, &cursor_wm)) {
1823 I915_WRITE(WM0_PIPEA_ILK,
1824 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826 " plane %d, " "cursor: %d\n",
1827 plane_wm, cursor_wm);
1828 enabled |= 1 << PIPE_A;
1831 if (g4x_compute_wm0(dev, PIPE_B,
1832 &ironlake_display_wm_info,
1833 dev_priv->wm.pri_latency[0] * 100,
1834 &ironlake_cursor_wm_info,
1835 dev_priv->wm.cur_latency[0] * 100,
1836 &plane_wm, &cursor_wm)) {
1837 I915_WRITE(WM0_PIPEB_ILK,
1838 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840 " plane %d, cursor: %d\n",
1841 plane_wm, cursor_wm);
1842 enabled |= 1 << PIPE_B;
1846 * Calculate and update the self-refresh watermark only when one
1847 * display plane is used.
1849 I915_WRITE(WM3_LP_ILK, 0);
1850 I915_WRITE(WM2_LP_ILK, 0);
1851 I915_WRITE(WM1_LP_ILK, 0);
1853 if (!single_plane_enabled(enabled))
1855 enabled = ffs(enabled) - 1;
1858 if (!ironlake_compute_srwm(dev, 1, enabled,
1859 dev_priv->wm.pri_latency[1] * 500,
1860 &ironlake_display_srwm_info,
1861 &ironlake_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1865 I915_WRITE(WM1_LP_ILK,
1867 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1873 if (!ironlake_compute_srwm(dev, 2, enabled,
1874 dev_priv->wm.pri_latency[2] * 500,
1875 &ironlake_display_srwm_info,
1876 &ironlake_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1880 I915_WRITE(WM2_LP_ILK,
1882 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1888 * WM3 is unsupported on ILK, probably because we don't have latency
1889 * data for that power state
1893 static void sandybridge_update_wm(struct drm_crtc *crtc)
1895 struct drm_device *dev = crtc->dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1897 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1899 int fbc_wm, plane_wm, cursor_wm;
1900 unsigned int enabled;
1903 if (g4x_compute_wm0(dev, PIPE_A,
1904 &sandybridge_display_wm_info, latency,
1905 &sandybridge_cursor_wm_info, latency,
1906 &plane_wm, &cursor_wm)) {
1907 val = I915_READ(WM0_PIPEA_ILK);
1908 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909 I915_WRITE(WM0_PIPEA_ILK, val |
1910 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912 " plane %d, " "cursor: %d\n",
1913 plane_wm, cursor_wm);
1914 enabled |= 1 << PIPE_A;
1917 if (g4x_compute_wm0(dev, PIPE_B,
1918 &sandybridge_display_wm_info, latency,
1919 &sandybridge_cursor_wm_info, latency,
1920 &plane_wm, &cursor_wm)) {
1921 val = I915_READ(WM0_PIPEB_ILK);
1922 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923 I915_WRITE(WM0_PIPEB_ILK, val |
1924 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926 " plane %d, cursor: %d\n",
1927 plane_wm, cursor_wm);
1928 enabled |= 1 << PIPE_B;
1932 * Calculate and update the self-refresh watermark only when one
1933 * display plane is used.
1935 * SNB support 3 levels of watermark.
1937 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938 * and disabled in the descending order
1941 I915_WRITE(WM3_LP_ILK, 0);
1942 I915_WRITE(WM2_LP_ILK, 0);
1943 I915_WRITE(WM1_LP_ILK, 0);
1945 if (!single_plane_enabled(enabled) ||
1946 dev_priv->sprite_scaling_enabled)
1948 enabled = ffs(enabled) - 1;
1951 if (!ironlake_compute_srwm(dev, 1, enabled,
1952 dev_priv->wm.pri_latency[1] * 500,
1953 &sandybridge_display_srwm_info,
1954 &sandybridge_cursor_srwm_info,
1955 &fbc_wm, &plane_wm, &cursor_wm))
1958 I915_WRITE(WM1_LP_ILK,
1960 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1961 (fbc_wm << WM1_LP_FBC_SHIFT) |
1962 (plane_wm << WM1_LP_SR_SHIFT) |
1966 if (!ironlake_compute_srwm(dev, 2, enabled,
1967 dev_priv->wm.pri_latency[2] * 500,
1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1973 I915_WRITE(WM2_LP_ILK,
1975 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1981 if (!ironlake_compute_srwm(dev, 3, enabled,
1982 dev_priv->wm.pri_latency[3] * 500,
1983 &sandybridge_display_srwm_info,
1984 &sandybridge_cursor_srwm_info,
1985 &fbc_wm, &plane_wm, &cursor_wm))
1988 I915_WRITE(WM3_LP_ILK,
1990 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1991 (fbc_wm << WM1_LP_FBC_SHIFT) |
1992 (plane_wm << WM1_LP_SR_SHIFT) |
1996 static void ivybridge_update_wm(struct drm_crtc *crtc)
1998 struct drm_device *dev = crtc->dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2002 int fbc_wm, plane_wm, cursor_wm;
2003 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004 unsigned int enabled;
2007 if (g4x_compute_wm0(dev, PIPE_A,
2008 &sandybridge_display_wm_info, latency,
2009 &sandybridge_cursor_wm_info, latency,
2010 &plane_wm, &cursor_wm)) {
2011 val = I915_READ(WM0_PIPEA_ILK);
2012 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013 I915_WRITE(WM0_PIPEA_ILK, val |
2014 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016 " plane %d, " "cursor: %d\n",
2017 plane_wm, cursor_wm);
2018 enabled |= 1 << PIPE_A;
2021 if (g4x_compute_wm0(dev, PIPE_B,
2022 &sandybridge_display_wm_info, latency,
2023 &sandybridge_cursor_wm_info, latency,
2024 &plane_wm, &cursor_wm)) {
2025 val = I915_READ(WM0_PIPEB_ILK);
2026 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027 I915_WRITE(WM0_PIPEB_ILK, val |
2028 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030 " plane %d, cursor: %d\n",
2031 plane_wm, cursor_wm);
2032 enabled |= 1 << PIPE_B;
2035 if (g4x_compute_wm0(dev, PIPE_C,
2036 &sandybridge_display_wm_info, latency,
2037 &sandybridge_cursor_wm_info, latency,
2038 &plane_wm, &cursor_wm)) {
2039 val = I915_READ(WM0_PIPEC_IVB);
2040 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041 I915_WRITE(WM0_PIPEC_IVB, val |
2042 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044 " plane %d, cursor: %d\n",
2045 plane_wm, cursor_wm);
2046 enabled |= 1 << PIPE_C;
2050 * Calculate and update the self-refresh watermark only when one
2051 * display plane is used.
2053 * SNB support 3 levels of watermark.
2055 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056 * and disabled in the descending order
2059 I915_WRITE(WM3_LP_ILK, 0);
2060 I915_WRITE(WM2_LP_ILK, 0);
2061 I915_WRITE(WM1_LP_ILK, 0);
2063 if (!single_plane_enabled(enabled) ||
2064 dev_priv->sprite_scaling_enabled)
2066 enabled = ffs(enabled) - 1;
2069 if (!ironlake_compute_srwm(dev, 1, enabled,
2070 dev_priv->wm.pri_latency[1] * 500,
2071 &sandybridge_display_srwm_info,
2072 &sandybridge_cursor_srwm_info,
2073 &fbc_wm, &plane_wm, &cursor_wm))
2076 I915_WRITE(WM1_LP_ILK,
2078 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2079 (fbc_wm << WM1_LP_FBC_SHIFT) |
2080 (plane_wm << WM1_LP_SR_SHIFT) |
2084 if (!ironlake_compute_srwm(dev, 2, enabled,
2085 dev_priv->wm.pri_latency[2] * 500,
2086 &sandybridge_display_srwm_info,
2087 &sandybridge_cursor_srwm_info,
2088 &fbc_wm, &plane_wm, &cursor_wm))
2091 I915_WRITE(WM2_LP_ILK,
2093 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2094 (fbc_wm << WM1_LP_FBC_SHIFT) |
2095 (plane_wm << WM1_LP_SR_SHIFT) |
2098 /* WM3, note we have to correct the cursor latency */
2099 if (!ironlake_compute_srwm(dev, 3, enabled,
2100 dev_priv->wm.pri_latency[3] * 500,
2101 &sandybridge_display_srwm_info,
2102 &sandybridge_cursor_srwm_info,
2103 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104 !ironlake_compute_srwm(dev, 3, enabled,
2105 dev_priv->wm.cur_latency[3] * 500,
2106 &sandybridge_display_srwm_info,
2107 &sandybridge_cursor_srwm_info,
2108 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2111 I915_WRITE(WM3_LP_ILK,
2113 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2114 (fbc_wm << WM1_LP_FBC_SHIFT) |
2115 (plane_wm << WM1_LP_SR_SHIFT) |
2119 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120 struct drm_crtc *crtc)
2122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123 uint32_t pixel_rate;
2125 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2127 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128 * adjust the pixel_rate here. */
2130 if (intel_crtc->config.pch_pfit.enabled) {
2131 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2132 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2134 pipe_w = intel_crtc->config.pipe_src_w;
2135 pipe_h = intel_crtc->config.pipe_src_h;
2136 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137 pfit_h = pfit_size & 0xFFFF;
2138 if (pipe_w < pfit_w)
2140 if (pipe_h < pfit_h)
2143 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2150 /* latency must be in 0.1us units. */
2151 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2156 if (WARN(latency == 0, "Latency value missing\n"))
2159 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2165 /* latency must be in 0.1us units. */
2166 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2167 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2172 if (WARN(latency == 0, "Latency value missing\n"))
2175 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177 ret = DIV_ROUND_UP(ret, 64) + 2;
2181 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2182 uint8_t bytes_per_pixel)
2184 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2187 struct hsw_pipe_wm_parameters {
2189 uint32_t pipe_htotal;
2190 uint32_t pixel_rate;
2191 struct intel_plane_wm_parameters pri;
2192 struct intel_plane_wm_parameters spr;
2193 struct intel_plane_wm_parameters cur;
2196 struct hsw_wm_maximums {
2203 struct hsw_wm_values {
2204 uint32_t wm_pipe[3];
2206 uint32_t wm_lp_spr[3];
2207 uint32_t wm_linetime[3];
2211 /* used in computing the new watermarks state */
2212 struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
2216 bool fbc_wm_enabled;
2220 * For both WM_PIPE and WM_LP.
2221 * mem_value must be in 0.1us units.
2223 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2227 uint32_t method1, method2;
2229 if (!params->active || !params->pri.enabled)
2232 method1 = ilk_wm_method1(params->pixel_rate,
2233 params->pri.bytes_per_pixel,
2239 method2 = ilk_wm_method2(params->pixel_rate,
2240 params->pipe_htotal,
2241 params->pri.horiz_pixels,
2242 params->pri.bytes_per_pixel,
2245 return min(method1, method2);
2249 * For both WM_PIPE and WM_LP.
2250 * mem_value must be in 0.1us units.
2252 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2255 uint32_t method1, method2;
2257 if (!params->active || !params->spr.enabled)
2260 method1 = ilk_wm_method1(params->pixel_rate,
2261 params->spr.bytes_per_pixel,
2263 method2 = ilk_wm_method2(params->pixel_rate,
2264 params->pipe_htotal,
2265 params->spr.horiz_pixels,
2266 params->spr.bytes_per_pixel,
2268 return min(method1, method2);
2272 * For both WM_PIPE and WM_LP.
2273 * mem_value must be in 0.1us units.
2275 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2278 if (!params->active || !params->cur.enabled)
2281 return ilk_wm_method2(params->pixel_rate,
2282 params->pipe_htotal,
2283 params->cur.horiz_pixels,
2284 params->cur.bytes_per_pixel,
2288 /* Only for WM_LP. */
2289 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2292 if (!params->active || !params->pri.enabled)
2295 return ilk_wm_fbc(pri_val,
2296 params->pri.horiz_pixels,
2297 params->pri.bytes_per_pixel);
2300 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2302 if (INTEL_INFO(dev)->gen >= 7)
2308 /* Calculate the maximum primary/sprite plane watermark */
2309 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2311 const struct intel_wm_config *config,
2312 enum intel_ddb_partitioning ddb_partitioning,
2315 unsigned int fifo_size = ilk_display_fifo_size(dev);
2318 /* if sprites aren't enabled, sprites get nothing */
2319 if (is_sprite && !config->sprites_enabled)
2322 /* HSW allows LP1+ watermarks even with multiple pipes */
2323 if (level == 0 || config->num_pipes_active > 1) {
2324 fifo_size /= INTEL_INFO(dev)->num_pipes;
2327 * For some reason the non self refresh
2328 * FIFO size is only half of the self
2329 * refresh FIFO size on ILK/SNB.
2331 if (INTEL_INFO(dev)->gen <= 6)
2335 if (config->sprites_enabled) {
2336 /* level 0 is always calculated with 1:1 split */
2337 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2346 /* clamp to max that the registers can hold */
2347 if (INTEL_INFO(dev)->gen >= 7)
2348 /* IVB/HSW primary/sprite plane watermarks */
2349 max = level == 0 ? 127 : 1023;
2350 else if (!is_sprite)
2351 /* ILK/SNB primary plane watermarks */
2352 max = level == 0 ? 127 : 511;
2354 /* ILK/SNB sprite plane watermarks */
2355 max = level == 0 ? 63 : 255;
2357 return min(fifo_size, max);
2360 /* Calculate the maximum cursor plane watermark */
2361 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2363 const struct intel_wm_config *config)
2365 /* HSW LP1+ watermarks w/ multiple pipes */
2366 if (level > 0 && config->num_pipes_active > 1)
2369 /* otherwise just report max that registers can hold */
2370 if (INTEL_INFO(dev)->gen >= 7)
2371 return level == 0 ? 63 : 255;
2373 return level == 0 ? 31 : 63;
2376 /* Calculate the maximum FBC watermark */
2377 static unsigned int ilk_fbc_wm_max(void)
2379 /* max that registers can hold */
2383 static void ilk_wm_max(struct drm_device *dev,
2385 const struct intel_wm_config *config,
2386 enum intel_ddb_partitioning ddb_partitioning,
2387 struct hsw_wm_maximums *max)
2389 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2390 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2391 max->cur = ilk_cursor_wm_max(dev, level, config);
2392 max->fbc = ilk_fbc_wm_max();
2395 static bool ilk_check_wm(int level,
2396 const struct hsw_wm_maximums *max,
2397 struct intel_wm_level *result)
2401 /* already determined to be invalid? */
2402 if (!result->enable)
2405 result->enable = result->pri_val <= max->pri &&
2406 result->spr_val <= max->spr &&
2407 result->cur_val <= max->cur;
2409 ret = result->enable;
2412 * HACK until we can pre-compute everything,
2413 * and thus fail gracefully if LP0 watermarks
2416 if (level == 0 && !result->enable) {
2417 if (result->pri_val > max->pri)
2418 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2419 level, result->pri_val, max->pri);
2420 if (result->spr_val > max->spr)
2421 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2422 level, result->spr_val, max->spr);
2423 if (result->cur_val > max->cur)
2424 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2425 level, result->cur_val, max->cur);
2427 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2428 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2429 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2430 result->enable = true;
2433 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2438 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2440 const struct hsw_pipe_wm_parameters *p,
2441 struct intel_wm_level *result)
2443 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2444 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2445 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2447 /* WM1+ latency values stored in 0.5us units */
2454 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2455 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2456 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2457 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2458 result->enable = true;
2462 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2467 u32 linetime, ips_linetime;
2469 if (!intel_crtc_active(crtc))
2472 /* The WM are computed with base on how long it takes to fill a single
2473 * row at the given clock rate, multiplied by 8.
2475 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2476 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2477 intel_ddi_get_cdclk_freq(dev_priv));
2479 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2480 PIPE_WM_LINETIME_TIME(linetime);
2483 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2487 if (IS_HASWELL(dev)) {
2488 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2490 wm[0] = (sskpd >> 56) & 0xFF;
2492 wm[0] = sskpd & 0xF;
2493 wm[1] = (sskpd >> 4) & 0xFF;
2494 wm[2] = (sskpd >> 12) & 0xFF;
2495 wm[3] = (sskpd >> 20) & 0x1FF;
2496 wm[4] = (sskpd >> 32) & 0x1FF;
2497 } else if (INTEL_INFO(dev)->gen >= 6) {
2498 uint32_t sskpd = I915_READ(MCH_SSKPD);
2500 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2501 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2502 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2503 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2504 } else if (INTEL_INFO(dev)->gen >= 5) {
2505 uint32_t mltr = I915_READ(MLTR_ILK);
2507 /* ILK primary LP0 latency is 700 ns */
2509 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2510 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2514 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2516 /* ILK sprite LP0 latency is 1300 ns */
2517 if (INTEL_INFO(dev)->gen == 5)
2521 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2523 /* ILK cursor LP0 latency is 1300 ns */
2524 if (INTEL_INFO(dev)->gen == 5)
2527 /* WaDoubleCursorLP3Latency:ivb */
2528 if (IS_IVYBRIDGE(dev))
2532 static int ilk_wm_max_level(const struct drm_device *dev)
2534 /* how many WM levels are we expecting */
2535 if (IS_HASWELL(dev))
2537 else if (INTEL_INFO(dev)->gen >= 6)
2543 static void intel_print_wm_latency(struct drm_device *dev,
2545 const uint16_t wm[5])
2547 int level, max_level = ilk_wm_max_level(dev);
2549 for (level = 0; level <= max_level; level++) {
2550 unsigned int latency = wm[level];
2553 DRM_ERROR("%s WM%d latency not provided\n",
2558 /* WM1+ latency values in 0.5us units */
2562 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2563 name, level, wm[level],
2564 latency / 10, latency % 10);
2568 static void intel_setup_wm_latency(struct drm_device *dev)
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2572 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2574 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2575 sizeof(dev_priv->wm.pri_latency));
2576 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2577 sizeof(dev_priv->wm.pri_latency));
2579 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2580 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2582 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2583 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2584 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2587 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2588 struct hsw_pipe_wm_parameters *p,
2589 struct intel_wm_config *config)
2591 struct drm_device *dev = crtc->dev;
2592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2593 enum pipe pipe = intel_crtc->pipe;
2594 struct drm_plane *plane;
2596 p->active = intel_crtc_active(crtc);
2598 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2599 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2600 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2601 p->cur.bytes_per_pixel = 4;
2602 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2603 p->cur.horiz_pixels = 64;
2604 /* TODO: for now, assume primary and cursor planes are always enabled. */
2605 p->pri.enabled = true;
2606 p->cur.enabled = true;
2609 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2610 config->num_pipes_active += intel_crtc_active(crtc);
2612 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2613 struct intel_plane *intel_plane = to_intel_plane(plane);
2615 if (intel_plane->pipe == pipe)
2616 p->spr = intel_plane->wm;
2618 config->sprites_enabled |= intel_plane->wm.enabled;
2619 config->sprites_scaled |= intel_plane->wm.scaled;
2623 /* Compute new watermarks for the pipe */
2624 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2625 const struct hsw_pipe_wm_parameters *params,
2626 struct intel_pipe_wm *pipe_wm)
2628 struct drm_device *dev = crtc->dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 int level, max_level = ilk_wm_max_level(dev);
2631 /* LP0 watermark maximums depend on this pipe alone */
2632 struct intel_wm_config config = {
2633 .num_pipes_active = 1,
2634 .sprites_enabled = params->spr.enabled,
2635 .sprites_scaled = params->spr.scaled,
2637 struct hsw_wm_maximums max;
2639 /* LP0 watermarks always use 1/2 DDB partitioning */
2640 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2642 for (level = 0; level <= max_level; level++)
2643 ilk_compute_wm_level(dev_priv, level, params,
2644 &pipe_wm->wm[level]);
2646 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2648 /* At least LP0 must be valid */
2649 return ilk_check_wm(0, &max, &pipe_wm->wm[0]);
2653 * Merge the watermarks from all active pipes for a specific level.
2655 static void ilk_merge_wm_level(struct drm_device *dev,
2657 struct intel_wm_level *ret_wm)
2659 const struct intel_crtc *intel_crtc;
2661 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2662 const struct intel_wm_level *wm =
2663 &intel_crtc->wm.active.wm[level];
2668 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2669 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2670 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2671 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2674 ret_wm->enable = true;
2678 * Merge all low power watermarks for all active pipes.
2680 static void ilk_wm_merge(struct drm_device *dev,
2681 const struct hsw_wm_maximums *max,
2682 struct intel_pipe_wm *merged)
2684 int level, max_level = ilk_wm_max_level(dev);
2686 merged->fbc_wm_enabled = true;
2688 /* merge each WM1+ level */
2689 for (level = 1; level <= max_level; level++) {
2690 struct intel_wm_level *wm = &merged->wm[level];
2692 ilk_merge_wm_level(dev, level, wm);
2694 if (!ilk_check_wm(level, max, wm))
2698 * The spec says it is preferred to disable
2699 * FBC WMs instead of disabling a WM level.
2701 if (wm->fbc_val > max->fbc) {
2702 merged->fbc_wm_enabled = false;
2708 static void hsw_compute_wm_results(struct drm_device *dev,
2709 const struct intel_pipe_wm *merged,
2710 struct hsw_wm_values *results)
2712 struct intel_crtc *intel_crtc;
2715 results->enable_fbc_wm = merged->fbc_wm_enabled;
2717 /* LP1+ register values */
2718 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2719 const struct intel_wm_level *r;
2721 level = wm_lp + (wm_lp >= 2 && merged->wm[4].enable);
2723 r = &merged->wm[level];
2727 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2731 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2734 /* LP0 register values */
2735 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2736 enum pipe pipe = intel_crtc->pipe;
2737 const struct intel_wm_level *r =
2738 &intel_crtc->wm.active.wm[0];
2740 if (WARN_ON(!r->enable))
2743 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2745 results->wm_pipe[pipe] =
2746 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2747 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2752 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2753 * case both are at the same level. Prefer r1 in case they're the same. */
2754 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2755 struct intel_pipe_wm *r1,
2756 struct intel_pipe_wm *r2)
2758 int level, max_level = ilk_wm_max_level(dev);
2759 int level1 = 0, level2 = 0;
2761 for (level = 1; level <= max_level; level++) {
2762 if (r1->wm[level].enable)
2764 if (r2->wm[level].enable)
2768 if (level1 == level2) {
2769 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2773 } else if (level1 > level2) {
2781 * The spec says we shouldn't write when we don't need, because every write
2782 * causes WMs to be re-evaluated, expending some power.
2784 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2785 struct hsw_wm_values *results,
2786 enum intel_ddb_partitioning partitioning)
2788 struct hsw_wm_values previous;
2790 enum intel_ddb_partitioning prev_partitioning;
2791 bool prev_enable_fbc_wm;
2793 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2794 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2795 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2796 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2797 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2798 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2799 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2800 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2801 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2802 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2803 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2804 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2806 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2807 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2809 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2811 if (memcmp(results->wm_pipe, previous.wm_pipe,
2812 sizeof(results->wm_pipe)) == 0 &&
2813 memcmp(results->wm_lp, previous.wm_lp,
2814 sizeof(results->wm_lp)) == 0 &&
2815 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2816 sizeof(results->wm_lp_spr)) == 0 &&
2817 memcmp(results->wm_linetime, previous.wm_linetime,
2818 sizeof(results->wm_linetime)) == 0 &&
2819 partitioning == prev_partitioning &&
2820 results->enable_fbc_wm == prev_enable_fbc_wm)
2823 if (previous.wm_lp[2] != 0)
2824 I915_WRITE(WM3_LP_ILK, 0);
2825 if (previous.wm_lp[1] != 0)
2826 I915_WRITE(WM2_LP_ILK, 0);
2827 if (previous.wm_lp[0] != 0)
2828 I915_WRITE(WM1_LP_ILK, 0);
2830 if (previous.wm_pipe[0] != results->wm_pipe[0])
2831 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2832 if (previous.wm_pipe[1] != results->wm_pipe[1])
2833 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2834 if (previous.wm_pipe[2] != results->wm_pipe[2])
2835 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2837 if (previous.wm_linetime[0] != results->wm_linetime[0])
2838 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2839 if (previous.wm_linetime[1] != results->wm_linetime[1])
2840 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2841 if (previous.wm_linetime[2] != results->wm_linetime[2])
2842 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2844 if (prev_partitioning != partitioning) {
2845 val = I915_READ(WM_MISC);
2846 if (partitioning == INTEL_DDB_PART_1_2)
2847 val &= ~WM_MISC_DATA_PARTITION_5_6;
2849 val |= WM_MISC_DATA_PARTITION_5_6;
2850 I915_WRITE(WM_MISC, val);
2853 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2854 val = I915_READ(DISP_ARB_CTL);
2855 if (results->enable_fbc_wm)
2856 val &= ~DISP_FBC_WM_DIS;
2858 val |= DISP_FBC_WM_DIS;
2859 I915_WRITE(DISP_ARB_CTL, val);
2862 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2863 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2864 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2865 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2866 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2867 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2869 if (results->wm_lp[0] != 0)
2870 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2871 if (results->wm_lp[1] != 0)
2872 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2873 if (results->wm_lp[2] != 0)
2874 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2877 static void haswell_update_wm(struct drm_crtc *crtc)
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 struct drm_device *dev = crtc->dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 struct hsw_wm_maximums max;
2883 struct hsw_pipe_wm_parameters params = {};
2884 struct hsw_wm_values results = {};
2885 enum intel_ddb_partitioning partitioning;
2886 struct intel_pipe_wm pipe_wm = {};
2887 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2888 struct intel_wm_config config = {};
2890 hsw_compute_wm_parameters(crtc, ¶ms, &config);
2892 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
2894 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2897 intel_crtc->wm.active = pipe_wm;
2899 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2900 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2902 /* 5/6 split only in single pipe config on IVB+ */
2903 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1) {
2904 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2905 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2907 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2909 best_lp_wm = &lp_wm_1_2;
2912 hsw_compute_wm_results(dev, best_lp_wm, &results);
2914 partitioning = (best_lp_wm == &lp_wm_1_2) ?
2915 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2917 hsw_write_wm_values(dev_priv, &results, partitioning);
2920 static void haswell_update_sprite_wm(struct drm_plane *plane,
2921 struct drm_crtc *crtc,
2922 uint32_t sprite_width, int pixel_size,
2923 bool enabled, bool scaled)
2925 struct intel_plane *intel_plane = to_intel_plane(plane);
2927 intel_plane->wm.enabled = enabled;
2928 intel_plane->wm.scaled = scaled;
2929 intel_plane->wm.horiz_pixels = sprite_width;
2930 intel_plane->wm.bytes_per_pixel = pixel_size;
2932 haswell_update_wm(crtc);
2936 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2937 uint32_t sprite_width, int pixel_size,
2938 const struct intel_watermark_params *display,
2939 int display_latency_ns, int *sprite_wm)
2941 struct drm_crtc *crtc;
2943 int entries, tlb_miss;
2945 crtc = intel_get_crtc_for_plane(dev, plane);
2946 if (!intel_crtc_active(crtc)) {
2947 *sprite_wm = display->guard_size;
2951 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2953 /* Use the small buffer method to calculate the sprite watermark */
2954 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2955 tlb_miss = display->fifo_size*display->cacheline_size -
2958 entries += tlb_miss;
2959 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2960 *sprite_wm = entries + display->guard_size;
2961 if (*sprite_wm > (int)display->max_wm)
2962 *sprite_wm = display->max_wm;
2968 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2969 uint32_t sprite_width, int pixel_size,
2970 const struct intel_watermark_params *display,
2971 int latency_ns, int *sprite_wm)
2973 struct drm_crtc *crtc;
2974 unsigned long line_time_us;
2976 int line_count, line_size;
2985 crtc = intel_get_crtc_for_plane(dev, plane);
2986 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2992 line_time_us = (sprite_width * 1000) / clock;
2993 if (!line_time_us) {
2998 line_count = (latency_ns / line_time_us + 1000) / 1000;
2999 line_size = sprite_width * pixel_size;
3001 /* Use the minimum of the small and large buffer method for primary */
3002 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3003 large = line_count * line_size;
3005 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3006 *sprite_wm = entries + display->guard_size;
3008 return *sprite_wm > 0x3ff ? false : true;
3011 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3012 struct drm_crtc *crtc,
3013 uint32_t sprite_width, int pixel_size,
3014 bool enabled, bool scaled)
3016 struct drm_device *dev = plane->dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 int pipe = to_intel_plane(plane)->pipe;
3019 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
3029 reg = WM0_PIPEA_ILK;
3032 reg = WM0_PIPEB_ILK;
3035 reg = WM0_PIPEC_IVB;
3038 return; /* bad pipe */
3041 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3042 &sandybridge_display_wm_info,
3043 latency, &sprite_wm);
3045 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3050 val = I915_READ(reg);
3051 val &= ~WM0_PIPE_SPRITE_MASK;
3052 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3053 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3056 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3058 &sandybridge_display_srwm_info,
3059 dev_priv->wm.spr_latency[1] * 500,
3062 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3066 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3068 /* Only IVB has two more LP watermarks for sprite */
3069 if (!IS_IVYBRIDGE(dev))
3072 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3074 &sandybridge_display_srwm_info,
3075 dev_priv->wm.spr_latency[2] * 500,
3078 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3082 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3084 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3086 &sandybridge_display_srwm_info,
3087 dev_priv->wm.spr_latency[3] * 500,
3090 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3094 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3098 * intel_update_watermarks - update FIFO watermark values based on current modes
3100 * Calculate watermark values for the various WM regs based on current mode
3101 * and plane configuration.
3103 * There are several cases to deal with here:
3104 * - normal (i.e. non-self-refresh)
3105 * - self-refresh (SR) mode
3106 * - lines are large relative to FIFO size (buffer can hold up to 2)
3107 * - lines are small relative to FIFO size (buffer can hold more than 2
3108 * lines), so need to account for TLB latency
3110 * The normal calculation is:
3111 * watermark = dotclock * bytes per pixel * latency
3112 * where latency is platform & configuration dependent (we assume pessimal
3115 * The SR calculation is:
3116 * watermark = (trunc(latency/line time)+1) * surface width *
3119 * line time = htotal / dotclock
3120 * surface width = hdisplay for normal plane and 64 for cursor
3121 * and latency is assumed to be high, as above.
3123 * The final value programmed to the register should always be rounded up,
3124 * and include an extra 2 entries to account for clock crossings.
3126 * We don't use the sprite, so we can ignore that. And on Crestline we have
3127 * to set the non-SR watermarks to 8.
3129 void intel_update_watermarks(struct drm_crtc *crtc)
3131 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3133 if (dev_priv->display.update_wm)
3134 dev_priv->display.update_wm(crtc);
3137 void intel_update_sprite_watermarks(struct drm_plane *plane,
3138 struct drm_crtc *crtc,
3139 uint32_t sprite_width, int pixel_size,
3140 bool enabled, bool scaled)
3142 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3144 if (dev_priv->display.update_sprite_wm)
3145 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3146 pixel_size, enabled, scaled);
3149 static struct drm_i915_gem_object *
3150 intel_alloc_context_page(struct drm_device *dev)
3152 struct drm_i915_gem_object *ctx;
3155 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3157 ctx = i915_gem_alloc_object(dev, 4096);
3159 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3163 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3165 DRM_ERROR("failed to pin power context: %d\n", ret);
3169 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3171 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3178 i915_gem_object_unpin(ctx);
3180 drm_gem_object_unreference(&ctx->base);
3185 * Lock protecting IPS related data structures
3187 DEFINE_SPINLOCK(mchdev_lock);
3189 /* Global for IPS driver to get at the current i915 device. Protected by
3191 static struct drm_i915_private *i915_mch_dev;
3193 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3198 assert_spin_locked(&mchdev_lock);
3200 rgvswctl = I915_READ16(MEMSWCTL);
3201 if (rgvswctl & MEMCTL_CMD_STS) {
3202 DRM_DEBUG("gpu busy, RCS change rejected\n");
3203 return false; /* still busy with another command */
3206 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3207 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3208 I915_WRITE16(MEMSWCTL, rgvswctl);
3209 POSTING_READ16(MEMSWCTL);
3211 rgvswctl |= MEMCTL_CMD_STS;
3212 I915_WRITE16(MEMSWCTL, rgvswctl);
3217 static void ironlake_enable_drps(struct drm_device *dev)
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 u32 rgvmodectl = I915_READ(MEMMODECTL);
3221 u8 fmax, fmin, fstart, vstart;
3223 spin_lock_irq(&mchdev_lock);
3225 /* Enable temp reporting */
3226 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3227 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3229 /* 100ms RC evaluation intervals */
3230 I915_WRITE(RCUPEI, 100000);
3231 I915_WRITE(RCDNEI, 100000);
3233 /* Set max/min thresholds to 90ms and 80ms respectively */
3234 I915_WRITE(RCBMAXAVG, 90000);
3235 I915_WRITE(RCBMINAVG, 80000);
3237 I915_WRITE(MEMIHYST, 1);
3239 /* Set up min, max, and cur for interrupt handling */
3240 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3241 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3242 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3243 MEMMODE_FSTART_SHIFT;
3245 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3248 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3249 dev_priv->ips.fstart = fstart;
3251 dev_priv->ips.max_delay = fstart;
3252 dev_priv->ips.min_delay = fmin;
3253 dev_priv->ips.cur_delay = fstart;
3255 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3256 fmax, fmin, fstart);
3258 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3261 * Interrupts will be enabled in ironlake_irq_postinstall
3264 I915_WRITE(VIDSTART, vstart);
3265 POSTING_READ(VIDSTART);
3267 rgvmodectl |= MEMMODE_SWMODE_EN;
3268 I915_WRITE(MEMMODECTL, rgvmodectl);
3270 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3271 DRM_ERROR("stuck trying to change perf mode\n");
3274 ironlake_set_drps(dev, fstart);
3276 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3278 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3279 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3280 getrawmonotonic(&dev_priv->ips.last_time2);
3282 spin_unlock_irq(&mchdev_lock);
3285 static void ironlake_disable_drps(struct drm_device *dev)
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3290 spin_lock_irq(&mchdev_lock);
3292 rgvswctl = I915_READ16(MEMSWCTL);
3294 /* Ack interrupts, disable EFC interrupt */
3295 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3296 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3297 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3298 I915_WRITE(DEIIR, DE_PCU_EVENT);
3299 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3301 /* Go back to the starting frequency */
3302 ironlake_set_drps(dev, dev_priv->ips.fstart);
3304 rgvswctl |= MEMCTL_CMD_STS;
3305 I915_WRITE(MEMSWCTL, rgvswctl);
3308 spin_unlock_irq(&mchdev_lock);
3311 /* There's a funny hw issue where the hw returns all 0 when reading from
3312 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3313 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3314 * all limits and the gpu stuck at whatever frequency it is at atm).
3316 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3322 if (*val >= dev_priv->rps.max_delay)
3323 *val = dev_priv->rps.max_delay;
3324 limits |= dev_priv->rps.max_delay << 24;
3326 /* Only set the down limit when we've reached the lowest level to avoid
3327 * getting more interrupts, otherwise leave this clear. This prevents a
3328 * race in the hw when coming out of rc6: There's a tiny window where
3329 * the hw runs at the minimal clock before selecting the desired
3330 * frequency, if the down threshold expires in that window we will not
3331 * receive a down interrupt. */
3332 if (*val <= dev_priv->rps.min_delay) {
3333 *val = dev_priv->rps.min_delay;
3334 limits |= dev_priv->rps.min_delay << 16;
3340 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3344 new_power = dev_priv->rps.power;
3345 switch (dev_priv->rps.power) {
3347 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3348 new_power = BETWEEN;
3352 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3353 new_power = LOW_POWER;
3354 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3355 new_power = HIGH_POWER;
3359 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3360 new_power = BETWEEN;
3363 /* Max/min bins are special */
3364 if (val == dev_priv->rps.min_delay)
3365 new_power = LOW_POWER;
3366 if (val == dev_priv->rps.max_delay)
3367 new_power = HIGH_POWER;
3368 if (new_power == dev_priv->rps.power)
3371 /* Note the units here are not exactly 1us, but 1280ns. */
3372 switch (new_power) {
3374 /* Upclock if more than 95% busy over 16ms */
3375 I915_WRITE(GEN6_RP_UP_EI, 12500);
3376 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3378 /* Downclock if less than 85% busy over 32ms */
3379 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3380 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3382 I915_WRITE(GEN6_RP_CONTROL,
3383 GEN6_RP_MEDIA_TURBO |
3384 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3385 GEN6_RP_MEDIA_IS_GFX |
3387 GEN6_RP_UP_BUSY_AVG |
3388 GEN6_RP_DOWN_IDLE_AVG);
3392 /* Upclock if more than 90% busy over 13ms */
3393 I915_WRITE(GEN6_RP_UP_EI, 10250);
3394 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3396 /* Downclock if less than 75% busy over 32ms */
3397 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3398 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3400 I915_WRITE(GEN6_RP_CONTROL,
3401 GEN6_RP_MEDIA_TURBO |
3402 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3403 GEN6_RP_MEDIA_IS_GFX |
3405 GEN6_RP_UP_BUSY_AVG |
3406 GEN6_RP_DOWN_IDLE_AVG);
3410 /* Upclock if more than 85% busy over 10ms */
3411 I915_WRITE(GEN6_RP_UP_EI, 8000);
3412 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3414 /* Downclock if less than 60% busy over 32ms */
3415 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3416 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3418 I915_WRITE(GEN6_RP_CONTROL,
3419 GEN6_RP_MEDIA_TURBO |
3420 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3421 GEN6_RP_MEDIA_IS_GFX |
3423 GEN6_RP_UP_BUSY_AVG |
3424 GEN6_RP_DOWN_IDLE_AVG);
3428 dev_priv->rps.power = new_power;
3429 dev_priv->rps.last_adj = 0;
3432 void gen6_set_rps(struct drm_device *dev, u8 val)
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 u32 limits = gen6_rps_limits(dev_priv, &val);
3437 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3438 WARN_ON(val > dev_priv->rps.max_delay);
3439 WARN_ON(val < dev_priv->rps.min_delay);
3441 if (val == dev_priv->rps.cur_delay)
3444 gen6_set_rps_thresholds(dev_priv, val);
3446 if (IS_HASWELL(dev))
3447 I915_WRITE(GEN6_RPNSWREQ,
3448 HSW_FREQUENCY(val));
3450 I915_WRITE(GEN6_RPNSWREQ,
3451 GEN6_FREQUENCY(val) |
3453 GEN6_AGGRESSIVE_TURBO);
3455 /* Make sure we continue to get interrupts
3456 * until we hit the minimum or maximum frequencies.
3458 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3460 POSTING_READ(GEN6_RPNSWREQ);
3462 dev_priv->rps.cur_delay = val;
3464 trace_intel_gpu_freq_change(val * 50);
3467 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3469 mutex_lock(&dev_priv->rps.hw_lock);
3470 if (dev_priv->rps.enabled) {
3471 if (dev_priv->info->is_valleyview)
3472 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3474 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3475 dev_priv->rps.last_adj = 0;
3477 mutex_unlock(&dev_priv->rps.hw_lock);
3480 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3482 mutex_lock(&dev_priv->rps.hw_lock);
3483 if (dev_priv->rps.enabled) {
3484 if (dev_priv->info->is_valleyview)
3485 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3487 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3488 dev_priv->rps.last_adj = 0;
3490 mutex_unlock(&dev_priv->rps.hw_lock);
3494 * Wait until the previous freq change has completed,
3495 * or the timeout elapsed, and then update our notion
3496 * of the current GPU frequency.
3498 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3502 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3504 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3505 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3509 if (pval != dev_priv->rps.cur_delay)
3510 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3511 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3512 dev_priv->rps.cur_delay,
3513 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3515 dev_priv->rps.cur_delay = pval;
3518 void valleyview_set_rps(struct drm_device *dev, u8 val)
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3522 gen6_rps_limits(dev_priv, &val);
3524 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3525 WARN_ON(val > dev_priv->rps.max_delay);
3526 WARN_ON(val < dev_priv->rps.min_delay);
3528 vlv_update_rps_cur_delay(dev_priv);
3530 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3531 vlv_gpu_freq(dev_priv->mem_freq,
3532 dev_priv->rps.cur_delay),
3533 dev_priv->rps.cur_delay,
3534 vlv_gpu_freq(dev_priv->mem_freq, val), val);
3536 if (val == dev_priv->rps.cur_delay)
3539 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3541 dev_priv->rps.cur_delay = val;
3543 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3546 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3548 struct drm_i915_private *dev_priv = dev->dev_private;
3550 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3551 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3552 /* Complete PM interrupt masking here doesn't race with the rps work
3553 * item again unmasking PM interrupts because that is using a different
3554 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3555 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3557 spin_lock_irq(&dev_priv->irq_lock);
3558 dev_priv->rps.pm_iir = 0;
3559 spin_unlock_irq(&dev_priv->irq_lock);
3561 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3564 static void gen6_disable_rps(struct drm_device *dev)
3566 struct drm_i915_private *dev_priv = dev->dev_private;
3568 I915_WRITE(GEN6_RC_CONTROL, 0);
3569 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3571 gen6_disable_rps_interrupts(dev);
3574 static void valleyview_disable_rps(struct drm_device *dev)
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3578 I915_WRITE(GEN6_RC_CONTROL, 0);
3580 gen6_disable_rps_interrupts(dev);
3582 if (dev_priv->vlv_pctx) {
3583 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3584 dev_priv->vlv_pctx = NULL;
3588 int intel_enable_rc6(const struct drm_device *dev)
3590 /* No RC6 before Ironlake */
3591 if (INTEL_INFO(dev)->gen < 5)
3594 /* Respect the kernel parameter if it is set */
3595 if (i915_enable_rc6 >= 0)
3596 return i915_enable_rc6;
3598 /* Disable RC6 on Ironlake */
3599 if (INTEL_INFO(dev)->gen == 5)
3602 if (IS_HASWELL(dev)) {
3603 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3604 return INTEL_RC6_ENABLE;
3607 /* snb/ivb have more than one rc6 state. */
3608 if (INTEL_INFO(dev)->gen == 6) {
3609 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3610 return INTEL_RC6_ENABLE;
3613 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3614 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3617 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3619 struct drm_i915_private *dev_priv = dev->dev_private;
3622 spin_lock_irq(&dev_priv->irq_lock);
3623 WARN_ON(dev_priv->rps.pm_iir);
3624 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3625 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3626 spin_unlock_irq(&dev_priv->irq_lock);
3628 /* only unmask PM interrupts we need. Mask all others. */
3629 enabled_intrs = GEN6_PM_RPS_EVENTS;
3631 /* IVB and SNB hard hangs on looping batchbuffer
3632 * if GEN6_PM_UP_EI_EXPIRED is masked.
3634 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3635 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3637 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3640 static void gen6_enable_rps(struct drm_device *dev)
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_ring_buffer *ring;
3646 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3651 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3653 /* Here begins a magic sequence of register writes to enable
3654 * auto-downclocking.
3656 * Perhaps there might be some value in exposing these to
3659 I915_WRITE(GEN6_RC_STATE, 0);
3661 /* Clear the DBG now so we don't confuse earlier errors */
3662 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3663 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3664 I915_WRITE(GTFIFODBG, gtfifodbg);
3667 gen6_gt_force_wake_get(dev_priv);
3669 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3670 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3672 /* In units of 50MHz */
3673 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3674 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3675 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3676 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3677 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3678 dev_priv->rps.cur_delay = 0;
3680 /* disable the counters and set deterministic thresholds */
3681 I915_WRITE(GEN6_RC_CONTROL, 0);
3683 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3684 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3685 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3686 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3687 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3689 for_each_ring(ring, dev_priv, i)
3690 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3692 I915_WRITE(GEN6_RC_SLEEP, 0);
3693 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3694 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3695 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3697 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3698 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3699 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3701 /* Check if we are enabling RC6 */
3702 rc6_mode = intel_enable_rc6(dev_priv->dev);
3703 if (rc6_mode & INTEL_RC6_ENABLE)
3704 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3706 /* We don't use those on Haswell */
3707 if (!IS_HASWELL(dev)) {
3708 if (rc6_mode & INTEL_RC6p_ENABLE)
3709 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3711 if (rc6_mode & INTEL_RC6pp_ENABLE)
3712 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3715 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3716 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3717 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3718 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3720 I915_WRITE(GEN6_RC_CONTROL,
3722 GEN6_RC_CTL_EI_MODE(1) |
3723 GEN6_RC_CTL_HW_ENABLE);
3725 /* Power down if completely idle for over 50ms */
3726 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3727 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3729 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3732 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3733 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3734 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3735 (dev_priv->rps.max_delay & 0xff) * 50,
3736 (pcu_mbox & 0xff) * 50);
3737 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3740 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3743 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3744 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3746 gen6_enable_rps_interrupts(dev);
3749 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3750 if (IS_GEN6(dev) && ret) {
3751 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3752 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3753 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3754 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3755 rc6vids &= 0xffff00;
3756 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3757 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3759 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3762 gen6_gt_force_wake_put(dev_priv);
3765 void gen6_update_ring_freq(struct drm_device *dev)
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3769 unsigned int gpu_freq;
3770 unsigned int max_ia_freq, min_ring_freq;
3771 int scaling_factor = 180;
3772 struct cpufreq_policy *policy;
3774 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3776 policy = cpufreq_cpu_get(0);
3778 max_ia_freq = policy->cpuinfo.max_freq;
3779 cpufreq_cpu_put(policy);
3782 * Default to measured freq if none found, PCU will ensure we
3785 max_ia_freq = tsc_khz;
3788 /* Convert from kHz to MHz */
3789 max_ia_freq /= 1000;
3791 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3792 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3793 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3796 * For each potential GPU frequency, load a ring frequency we'd like
3797 * to use for memory access. We do this by specifying the IA frequency
3798 * the PCU should use as a reference to determine the ring frequency.
3800 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3802 int diff = dev_priv->rps.max_delay - gpu_freq;
3803 unsigned int ia_freq = 0, ring_freq = 0;
3805 if (IS_HASWELL(dev)) {
3806 ring_freq = mult_frac(gpu_freq, 5, 4);
3807 ring_freq = max(min_ring_freq, ring_freq);
3808 /* leave ia_freq as the default, chosen by cpufreq */
3810 /* On older processors, there is no separate ring
3811 * clock domain, so in order to boost the bandwidth
3812 * of the ring, we need to upclock the CPU (ia_freq).
3814 * For GPU frequencies less than 750MHz,
3815 * just use the lowest ring freq.
3817 if (gpu_freq < min_freq)
3820 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3821 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3824 sandybridge_pcode_write(dev_priv,
3825 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3826 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3827 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3832 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3836 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3838 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3840 rp0 = min_t(u32, rp0, 0xea);
3845 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3849 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3850 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3851 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3852 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3857 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3859 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3862 static void valleyview_setup_pctx(struct drm_device *dev)
3864 struct drm_i915_private *dev_priv = dev->dev_private;
3865 struct drm_i915_gem_object *pctx;
3866 unsigned long pctx_paddr;
3868 int pctx_size = 24*1024;
3870 pcbr = I915_READ(VLV_PCBR);
3872 /* BIOS set it up already, grab the pre-alloc'd space */
3875 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3876 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3878 I915_GTT_OFFSET_NONE,
3884 * From the Gunit register HAS:
3885 * The Gfx driver is expected to program this register and ensure
3886 * proper allocation within Gfx stolen memory. For example, this
3887 * register should be programmed such than the PCBR range does not
3888 * overlap with other ranges, such as the frame buffer, protected
3889 * memory, or any other relevant ranges.
3891 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3893 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3897 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3898 I915_WRITE(VLV_PCBR, pctx_paddr);
3901 dev_priv->vlv_pctx = pctx;
3904 static void valleyview_enable_rps(struct drm_device *dev)
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907 struct intel_ring_buffer *ring;
3908 u32 gtfifodbg, val, rc6_mode = 0;
3911 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3913 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3914 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3916 I915_WRITE(GTFIFODBG, gtfifodbg);
3919 valleyview_setup_pctx(dev);
3921 gen6_gt_force_wake_get(dev_priv);
3923 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3924 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3925 I915_WRITE(GEN6_RP_UP_EI, 66000);
3926 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3928 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3930 I915_WRITE(GEN6_RP_CONTROL,
3931 GEN6_RP_MEDIA_TURBO |
3932 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3933 GEN6_RP_MEDIA_IS_GFX |
3935 GEN6_RP_UP_BUSY_AVG |
3936 GEN6_RP_DOWN_IDLE_CONT);
3938 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3939 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3940 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3942 for_each_ring(ring, dev_priv, i)
3943 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3945 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3947 /* allows RC6 residency counter to work */
3948 I915_WRITE(VLV_COUNTER_CONTROL,
3949 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3950 VLV_MEDIA_RC6_COUNT_EN |
3951 VLV_RENDER_RC6_COUNT_EN));
3952 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3953 rc6_mode = GEN7_RC_CTL_TO_MODE;
3954 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3956 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3957 switch ((val >> 6) & 3) {
3960 dev_priv->mem_freq = 800;
3963 dev_priv->mem_freq = 1066;
3966 dev_priv->mem_freq = 1333;
3969 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3971 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3972 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3974 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3975 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3976 vlv_gpu_freq(dev_priv->mem_freq,
3977 dev_priv->rps.cur_delay),
3978 dev_priv->rps.cur_delay);
3980 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3981 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3982 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3983 vlv_gpu_freq(dev_priv->mem_freq,
3984 dev_priv->rps.max_delay),
3985 dev_priv->rps.max_delay);
3987 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3988 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3989 vlv_gpu_freq(dev_priv->mem_freq,
3990 dev_priv->rps.rpe_delay),
3991 dev_priv->rps.rpe_delay);
3993 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3994 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3995 vlv_gpu_freq(dev_priv->mem_freq,
3996 dev_priv->rps.min_delay),
3997 dev_priv->rps.min_delay);
3999 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4000 vlv_gpu_freq(dev_priv->mem_freq,
4001 dev_priv->rps.rpe_delay),
4002 dev_priv->rps.rpe_delay);
4004 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4006 gen6_enable_rps_interrupts(dev);
4008 gen6_gt_force_wake_put(dev_priv);
4011 void ironlake_teardown_rc6(struct drm_device *dev)
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4015 if (dev_priv->ips.renderctx) {
4016 i915_gem_object_unpin(dev_priv->ips.renderctx);
4017 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4018 dev_priv->ips.renderctx = NULL;
4021 if (dev_priv->ips.pwrctx) {
4022 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4023 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4024 dev_priv->ips.pwrctx = NULL;
4028 static void ironlake_disable_rc6(struct drm_device *dev)
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4032 if (I915_READ(PWRCTXA)) {
4033 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4034 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4035 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4038 I915_WRITE(PWRCTXA, 0);
4039 POSTING_READ(PWRCTXA);
4041 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4042 POSTING_READ(RSTDBYCTL);
4046 static int ironlake_setup_rc6(struct drm_device *dev)
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4050 if (dev_priv->ips.renderctx == NULL)
4051 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4052 if (!dev_priv->ips.renderctx)
4055 if (dev_priv->ips.pwrctx == NULL)
4056 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4057 if (!dev_priv->ips.pwrctx) {
4058 ironlake_teardown_rc6(dev);
4065 static void ironlake_enable_rc6(struct drm_device *dev)
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4069 bool was_interruptible;
4072 /* rc6 disabled by default due to repeated reports of hanging during
4075 if (!intel_enable_rc6(dev))
4078 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4080 ret = ironlake_setup_rc6(dev);
4084 was_interruptible = dev_priv->mm.interruptible;
4085 dev_priv->mm.interruptible = false;
4088 * GPU can automatically power down the render unit if given a page
4091 ret = intel_ring_begin(ring, 6);
4093 ironlake_teardown_rc6(dev);
4094 dev_priv->mm.interruptible = was_interruptible;
4098 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4099 intel_ring_emit(ring, MI_SET_CONTEXT);
4100 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4102 MI_SAVE_EXT_STATE_EN |
4103 MI_RESTORE_EXT_STATE_EN |
4104 MI_RESTORE_INHIBIT);
4105 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4106 intel_ring_emit(ring, MI_NOOP);
4107 intel_ring_emit(ring, MI_FLUSH);
4108 intel_ring_advance(ring);
4111 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4112 * does an implicit flush, combined with MI_FLUSH above, it should be
4113 * safe to assume that renderctx is valid
4115 ret = intel_ring_idle(ring);
4116 dev_priv->mm.interruptible = was_interruptible;
4118 DRM_ERROR("failed to enable ironlake power savings\n");
4119 ironlake_teardown_rc6(dev);
4123 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4124 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4127 static unsigned long intel_pxfreq(u32 vidfreq)
4130 int div = (vidfreq & 0x3f0000) >> 16;
4131 int post = (vidfreq & 0x3000) >> 12;
4132 int pre = (vidfreq & 0x7);
4137 freq = ((div * 133333) / ((1<<post) * pre));
4142 static const struct cparams {
4148 { 1, 1333, 301, 28664 },
4149 { 1, 1066, 294, 24460 },
4150 { 1, 800, 294, 25192 },
4151 { 0, 1333, 276, 27605 },
4152 { 0, 1066, 276, 27605 },
4153 { 0, 800, 231, 23784 },
4156 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4158 u64 total_count, diff, ret;
4159 u32 count1, count2, count3, m = 0, c = 0;
4160 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4163 assert_spin_locked(&mchdev_lock);
4165 diff1 = now - dev_priv->ips.last_time1;
4167 /* Prevent division-by-zero if we are asking too fast.
4168 * Also, we don't get interesting results if we are polling
4169 * faster than once in 10ms, so just return the saved value
4173 return dev_priv->ips.chipset_power;
4175 count1 = I915_READ(DMIEC);
4176 count2 = I915_READ(DDREC);
4177 count3 = I915_READ(CSIEC);
4179 total_count = count1 + count2 + count3;
4181 /* FIXME: handle per-counter overflow */
4182 if (total_count < dev_priv->ips.last_count1) {
4183 diff = ~0UL - dev_priv->ips.last_count1;
4184 diff += total_count;
4186 diff = total_count - dev_priv->ips.last_count1;
4189 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4190 if (cparams[i].i == dev_priv->ips.c_m &&
4191 cparams[i].t == dev_priv->ips.r_t) {
4198 diff = div_u64(diff, diff1);
4199 ret = ((m * diff) + c);
4200 ret = div_u64(ret, 10);
4202 dev_priv->ips.last_count1 = total_count;
4203 dev_priv->ips.last_time1 = now;
4205 dev_priv->ips.chipset_power = ret;
4210 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4214 if (dev_priv->info->gen != 5)
4217 spin_lock_irq(&mchdev_lock);
4219 val = __i915_chipset_val(dev_priv);
4221 spin_unlock_irq(&mchdev_lock);
4226 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4228 unsigned long m, x, b;
4231 tsfs = I915_READ(TSFS);
4233 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4234 x = I915_READ8(TR1);
4236 b = tsfs & TSFS_INTR_MASK;
4238 return ((m * x) / 127) - b;
4241 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4243 static const struct v_table {
4244 u16 vd; /* in .1 mil */
4245 u16 vm; /* in .1 mil */
4376 if (dev_priv->info->is_mobile)
4377 return v_table[pxvid].vm;
4379 return v_table[pxvid].vd;
4382 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4384 struct timespec now, diff1;
4386 unsigned long diffms;
4389 assert_spin_locked(&mchdev_lock);
4391 getrawmonotonic(&now);
4392 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4394 /* Don't divide by 0 */
4395 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4399 count = I915_READ(GFXEC);
4401 if (count < dev_priv->ips.last_count2) {
4402 diff = ~0UL - dev_priv->ips.last_count2;
4405 diff = count - dev_priv->ips.last_count2;
4408 dev_priv->ips.last_count2 = count;
4409 dev_priv->ips.last_time2 = now;
4411 /* More magic constants... */
4413 diff = div_u64(diff, diffms * 10);
4414 dev_priv->ips.gfx_power = diff;
4417 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4419 if (dev_priv->info->gen != 5)
4422 spin_lock_irq(&mchdev_lock);
4424 __i915_update_gfx_val(dev_priv);
4426 spin_unlock_irq(&mchdev_lock);
4429 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4431 unsigned long t, corr, state1, corr2, state2;
4434 assert_spin_locked(&mchdev_lock);
4436 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4437 pxvid = (pxvid >> 24) & 0x7f;
4438 ext_v = pvid_to_extvid(dev_priv, pxvid);
4442 t = i915_mch_val(dev_priv);
4444 /* Revel in the empirically derived constants */
4446 /* Correction factor in 1/100000 units */
4448 corr = ((t * 2349) + 135940);
4450 corr = ((t * 964) + 29317);
4452 corr = ((t * 301) + 1004);
4454 corr = corr * ((150142 * state1) / 10000 - 78642);
4456 corr2 = (corr * dev_priv->ips.corr);
4458 state2 = (corr2 * state1) / 10000;
4459 state2 /= 100; /* convert to mW */
4461 __i915_update_gfx_val(dev_priv);
4463 return dev_priv->ips.gfx_power + state2;
4466 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4470 if (dev_priv->info->gen != 5)
4473 spin_lock_irq(&mchdev_lock);
4475 val = __i915_gfx_val(dev_priv);
4477 spin_unlock_irq(&mchdev_lock);
4483 * i915_read_mch_val - return value for IPS use
4485 * Calculate and return a value for the IPS driver to use when deciding whether
4486 * we have thermal and power headroom to increase CPU or GPU power budget.
4488 unsigned long i915_read_mch_val(void)
4490 struct drm_i915_private *dev_priv;
4491 unsigned long chipset_val, graphics_val, ret = 0;
4493 spin_lock_irq(&mchdev_lock);
4496 dev_priv = i915_mch_dev;
4498 chipset_val = __i915_chipset_val(dev_priv);
4499 graphics_val = __i915_gfx_val(dev_priv);
4501 ret = chipset_val + graphics_val;
4504 spin_unlock_irq(&mchdev_lock);
4508 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4511 * i915_gpu_raise - raise GPU frequency limit
4513 * Raise the limit; IPS indicates we have thermal headroom.
4515 bool i915_gpu_raise(void)
4517 struct drm_i915_private *dev_priv;
4520 spin_lock_irq(&mchdev_lock);
4521 if (!i915_mch_dev) {
4525 dev_priv = i915_mch_dev;
4527 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4528 dev_priv->ips.max_delay--;
4531 spin_unlock_irq(&mchdev_lock);
4535 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4538 * i915_gpu_lower - lower GPU frequency limit
4540 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4541 * frequency maximum.
4543 bool i915_gpu_lower(void)
4545 struct drm_i915_private *dev_priv;
4548 spin_lock_irq(&mchdev_lock);
4549 if (!i915_mch_dev) {
4553 dev_priv = i915_mch_dev;
4555 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4556 dev_priv->ips.max_delay++;
4559 spin_unlock_irq(&mchdev_lock);
4563 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4566 * i915_gpu_busy - indicate GPU business to IPS
4568 * Tell the IPS driver whether or not the GPU is busy.
4570 bool i915_gpu_busy(void)
4572 struct drm_i915_private *dev_priv;
4573 struct intel_ring_buffer *ring;
4577 spin_lock_irq(&mchdev_lock);
4580 dev_priv = i915_mch_dev;
4582 for_each_ring(ring, dev_priv, i)
4583 ret |= !list_empty(&ring->request_list);
4586 spin_unlock_irq(&mchdev_lock);
4590 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4593 * i915_gpu_turbo_disable - disable graphics turbo
4595 * Disable graphics turbo by resetting the max frequency and setting the
4596 * current frequency to the default.
4598 bool i915_gpu_turbo_disable(void)
4600 struct drm_i915_private *dev_priv;
4603 spin_lock_irq(&mchdev_lock);
4604 if (!i915_mch_dev) {
4608 dev_priv = i915_mch_dev;
4610 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4612 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4616 spin_unlock_irq(&mchdev_lock);
4620 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4623 * Tells the intel_ips driver that the i915 driver is now loaded, if
4624 * IPS got loaded first.
4626 * This awkward dance is so that neither module has to depend on the
4627 * other in order for IPS to do the appropriate communication of
4628 * GPU turbo limits to i915.
4631 ips_ping_for_i915_load(void)
4635 link = symbol_get(ips_link_to_i915_driver);
4638 symbol_put(ips_link_to_i915_driver);
4642 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4644 /* We only register the i915 ips part with intel-ips once everything is
4645 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4646 spin_lock_irq(&mchdev_lock);
4647 i915_mch_dev = dev_priv;
4648 spin_unlock_irq(&mchdev_lock);
4650 ips_ping_for_i915_load();
4653 void intel_gpu_ips_teardown(void)
4655 spin_lock_irq(&mchdev_lock);
4656 i915_mch_dev = NULL;
4657 spin_unlock_irq(&mchdev_lock);
4659 static void intel_init_emon(struct drm_device *dev)
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4666 /* Disable to program */
4670 /* Program energy weights for various events */
4671 I915_WRITE(SDEW, 0x15040d00);
4672 I915_WRITE(CSIEW0, 0x007f0000);
4673 I915_WRITE(CSIEW1, 0x1e220004);
4674 I915_WRITE(CSIEW2, 0x04000004);
4676 for (i = 0; i < 5; i++)
4677 I915_WRITE(PEW + (i * 4), 0);
4678 for (i = 0; i < 3; i++)
4679 I915_WRITE(DEW + (i * 4), 0);
4681 /* Program P-state weights to account for frequency power adjustment */
4682 for (i = 0; i < 16; i++) {
4683 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4684 unsigned long freq = intel_pxfreq(pxvidfreq);
4685 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4690 val *= (freq / 1000);
4692 val /= (127*127*900);
4694 DRM_ERROR("bad pxval: %ld\n", val);
4697 /* Render standby states get 0 weight */
4701 for (i = 0; i < 4; i++) {
4702 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4703 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4704 I915_WRITE(PXW + (i * 4), val);
4707 /* Adjust magic regs to magic values (more experimental results) */
4708 I915_WRITE(OGW0, 0);
4709 I915_WRITE(OGW1, 0);
4710 I915_WRITE(EG0, 0x00007f00);
4711 I915_WRITE(EG1, 0x0000000e);
4712 I915_WRITE(EG2, 0x000e0000);
4713 I915_WRITE(EG3, 0x68000300);
4714 I915_WRITE(EG4, 0x42000000);
4715 I915_WRITE(EG5, 0x00140031);
4719 for (i = 0; i < 8; i++)
4720 I915_WRITE(PXWL + (i * 4), 0);
4722 /* Enable PMON + select events */
4723 I915_WRITE(ECR, 0x80000019);
4725 lcfuse = I915_READ(LCFUSE02);
4727 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4730 void intel_disable_gt_powersave(struct drm_device *dev)
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4734 /* Interrupts should be disabled already to avoid re-arming. */
4735 WARN_ON(dev->irq_enabled);
4737 if (IS_IRONLAKE_M(dev)) {
4738 ironlake_disable_drps(dev);
4739 ironlake_disable_rc6(dev);
4740 } else if (INTEL_INFO(dev)->gen >= 6) {
4741 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4742 cancel_work_sync(&dev_priv->rps.work);
4743 mutex_lock(&dev_priv->rps.hw_lock);
4744 if (IS_VALLEYVIEW(dev))
4745 valleyview_disable_rps(dev);
4747 gen6_disable_rps(dev);
4748 dev_priv->rps.enabled = false;
4749 mutex_unlock(&dev_priv->rps.hw_lock);
4753 static void intel_gen6_powersave_work(struct work_struct *work)
4755 struct drm_i915_private *dev_priv =
4756 container_of(work, struct drm_i915_private,
4757 rps.delayed_resume_work.work);
4758 struct drm_device *dev = dev_priv->dev;
4760 mutex_lock(&dev_priv->rps.hw_lock);
4762 if (IS_VALLEYVIEW(dev)) {
4763 valleyview_enable_rps(dev);
4765 gen6_enable_rps(dev);
4766 gen6_update_ring_freq(dev);
4768 dev_priv->rps.enabled = true;
4769 mutex_unlock(&dev_priv->rps.hw_lock);
4772 void intel_enable_gt_powersave(struct drm_device *dev)
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4776 if (IS_IRONLAKE_M(dev)) {
4777 ironlake_enable_drps(dev);
4778 ironlake_enable_rc6(dev);
4779 intel_init_emon(dev);
4780 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4782 * PCU communication is slow and this doesn't need to be
4783 * done at any specific time, so do this out of our fast path
4784 * to make resume and init faster.
4786 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4787 round_jiffies_up_relative(HZ));
4791 static void ibx_init_clock_gating(struct drm_device *dev)
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4796 * On Ibex Peak and Cougar Point, we need to disable clock
4797 * gating for the panel power sequencer or it will fail to
4798 * start up when no ports are active.
4800 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4803 static void g4x_disable_trickle_feed(struct drm_device *dev)
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4808 for_each_pipe(pipe) {
4809 I915_WRITE(DSPCNTR(pipe),
4810 I915_READ(DSPCNTR(pipe)) |
4811 DISPPLANE_TRICKLE_FEED_DISABLE);
4812 intel_flush_primary_plane(dev_priv, pipe);
4816 static void ironlake_init_clock_gating(struct drm_device *dev)
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4823 * WaFbcDisableDpfcClockGating:ilk
4825 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4826 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4827 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4829 I915_WRITE(PCH_3DCGDIS0,
4830 MARIUNIT_CLOCK_GATE_DISABLE |
4831 SVSMUNIT_CLOCK_GATE_DISABLE);
4832 I915_WRITE(PCH_3DCGDIS1,
4833 VFMUNIT_CLOCK_GATE_DISABLE);
4836 * According to the spec the following bits should be set in
4837 * order to enable memory self-refresh
4838 * The bit 22/21 of 0x42004
4839 * The bit 5 of 0x42020
4840 * The bit 15 of 0x45000
4842 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4843 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4844 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4845 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4846 I915_WRITE(DISP_ARB_CTL,
4847 (I915_READ(DISP_ARB_CTL) |
4849 I915_WRITE(WM3_LP_ILK, 0);
4850 I915_WRITE(WM2_LP_ILK, 0);
4851 I915_WRITE(WM1_LP_ILK, 0);
4854 * Based on the document from hardware guys the following bits
4855 * should be set unconditionally in order to enable FBC.
4856 * The bit 22 of 0x42000
4857 * The bit 22 of 0x42004
4858 * The bit 7,8,9 of 0x42020.
4860 if (IS_IRONLAKE_M(dev)) {
4861 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4862 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4863 I915_READ(ILK_DISPLAY_CHICKEN1) |
4865 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4866 I915_READ(ILK_DISPLAY_CHICKEN2) |
4870 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4872 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4873 I915_READ(ILK_DISPLAY_CHICKEN2) |
4874 ILK_ELPIN_409_SELECT);
4875 I915_WRITE(_3D_CHICKEN2,
4876 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4877 _3D_CHICKEN2_WM_READ_PIPELINED);
4879 /* WaDisableRenderCachePipelinedFlush:ilk */
4880 I915_WRITE(CACHE_MODE_0,
4881 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4883 g4x_disable_trickle_feed(dev);
4885 ibx_init_clock_gating(dev);
4888 static void cpt_init_clock_gating(struct drm_device *dev)
4890 struct drm_i915_private *dev_priv = dev->dev_private;
4895 * On Ibex Peak and Cougar Point, we need to disable clock
4896 * gating for the panel power sequencer or it will fail to
4897 * start up when no ports are active.
4899 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4900 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4901 DPLS_EDP_PPS_FIX_DIS);
4902 /* The below fixes the weird display corruption, a few pixels shifted
4903 * downward, on (only) LVDS of some HP laptops with IVY.
4905 for_each_pipe(pipe) {
4906 val = I915_READ(TRANS_CHICKEN2(pipe));
4907 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4908 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4909 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4910 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4911 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4912 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4913 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4914 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4916 /* WADP0ClockGatingDisable */
4917 for_each_pipe(pipe) {
4918 I915_WRITE(TRANS_CHICKEN1(pipe),
4919 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4923 static void gen6_check_mch_setup(struct drm_device *dev)
4925 struct drm_i915_private *dev_priv = dev->dev_private;
4928 tmp = I915_READ(MCH_SSKPD);
4929 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4930 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4931 DRM_INFO("This can cause pipe underruns and display issues.\n");
4932 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4936 static void gen6_init_clock_gating(struct drm_device *dev)
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4939 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4941 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4943 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4944 I915_READ(ILK_DISPLAY_CHICKEN2) |
4945 ILK_ELPIN_409_SELECT);
4947 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4948 I915_WRITE(_3D_CHICKEN,
4949 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4951 /* WaSetupGtModeTdRowDispatch:snb */
4952 if (IS_SNB_GT1(dev))
4953 I915_WRITE(GEN6_GT_MODE,
4954 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4956 I915_WRITE(WM3_LP_ILK, 0);
4957 I915_WRITE(WM2_LP_ILK, 0);
4958 I915_WRITE(WM1_LP_ILK, 0);
4960 I915_WRITE(CACHE_MODE_0,
4961 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4963 I915_WRITE(GEN6_UCGCTL1,
4964 I915_READ(GEN6_UCGCTL1) |
4965 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4966 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4968 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4969 * gating disable must be set. Failure to set it results in
4970 * flickering pixels due to Z write ordering failures after
4971 * some amount of runtime in the Mesa "fire" demo, and Unigine
4972 * Sanctuary and Tropics, and apparently anything else with
4973 * alpha test or pixel discard.
4975 * According to the spec, bit 11 (RCCUNIT) must also be set,
4976 * but we didn't debug actual testcases to find it out.
4978 * Also apply WaDisableVDSUnitClockGating:snb and
4979 * WaDisableRCPBUnitClockGating:snb.
4981 I915_WRITE(GEN6_UCGCTL2,
4982 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4983 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4984 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4986 /* Bspec says we need to always set all mask bits. */
4987 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4988 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4991 * According to the spec the following bits should be
4992 * set in order to enable memory self-refresh and fbc:
4993 * The bit21 and bit22 of 0x42000
4994 * The bit21 and bit22 of 0x42004
4995 * The bit5 and bit7 of 0x42020
4996 * The bit14 of 0x70180
4997 * The bit14 of 0x71180
4999 * WaFbcAsynchFlipDisableFbcQueue:snb
5001 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5002 I915_READ(ILK_DISPLAY_CHICKEN1) |
5003 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5004 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5005 I915_READ(ILK_DISPLAY_CHICKEN2) |
5006 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5007 I915_WRITE(ILK_DSPCLK_GATE_D,
5008 I915_READ(ILK_DSPCLK_GATE_D) |
5009 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5010 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5012 g4x_disable_trickle_feed(dev);
5014 /* The default value should be 0x200 according to docs, but the two
5015 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5016 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5017 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5019 cpt_init_clock_gating(dev);
5021 gen6_check_mch_setup(dev);
5024 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5026 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5028 reg &= ~GEN7_FF_SCHED_MASK;
5029 reg |= GEN7_FF_TS_SCHED_HW;
5030 reg |= GEN7_FF_VS_SCHED_HW;
5031 reg |= GEN7_FF_DS_SCHED_HW;
5033 if (IS_HASWELL(dev_priv->dev))
5034 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5036 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5039 static void lpt_init_clock_gating(struct drm_device *dev)
5041 struct drm_i915_private *dev_priv = dev->dev_private;
5044 * TODO: this bit should only be enabled when really needed, then
5045 * disabled when not needed anymore in order to save power.
5047 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5048 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5049 I915_READ(SOUTH_DSPCLK_GATE_D) |
5050 PCH_LP_PARTITION_LEVEL_DISABLE);
5052 /* WADPOClockGatingDisable:hsw */
5053 I915_WRITE(_TRANSA_CHICKEN1,
5054 I915_READ(_TRANSA_CHICKEN1) |
5055 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5058 static void lpt_suspend_hw(struct drm_device *dev)
5060 struct drm_i915_private *dev_priv = dev->dev_private;
5062 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5063 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5065 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5066 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5070 static void haswell_init_clock_gating(struct drm_device *dev)
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5074 I915_WRITE(WM3_LP_ILK, 0);
5075 I915_WRITE(WM2_LP_ILK, 0);
5076 I915_WRITE(WM1_LP_ILK, 0);
5078 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5079 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5081 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5083 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5084 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5085 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5087 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5088 I915_WRITE(GEN7_L3CNTLREG1,
5089 GEN7_WA_FOR_GEN7_L3_CONTROL);
5090 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5091 GEN7_WA_L3_CHICKEN_MODE);
5093 /* This is required by WaCatErrorRejectionIssue:hsw */
5094 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5095 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5096 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5098 /* WaVSRefCountFullforceMissDisable:hsw */
5099 gen7_setup_fixed_func_scheduler(dev_priv);
5101 /* WaDisable4x2SubspanOptimization:hsw */
5102 I915_WRITE(CACHE_MODE_1,
5103 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5105 /* WaSwitchSolVfFArbitrationPriority:hsw */
5106 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5108 /* WaRsPkgCStateDisplayPMReq:hsw */
5109 I915_WRITE(CHICKEN_PAR1_1,
5110 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5112 lpt_init_clock_gating(dev);
5115 static void ivybridge_init_clock_gating(struct drm_device *dev)
5117 struct drm_i915_private *dev_priv = dev->dev_private;
5120 I915_WRITE(WM3_LP_ILK, 0);
5121 I915_WRITE(WM2_LP_ILK, 0);
5122 I915_WRITE(WM1_LP_ILK, 0);
5124 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5126 /* WaDisableEarlyCull:ivb */
5127 I915_WRITE(_3D_CHICKEN3,
5128 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5130 /* WaDisableBackToBackFlipFix:ivb */
5131 I915_WRITE(IVB_CHICKEN3,
5132 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5133 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5135 /* WaDisablePSDDualDispatchEnable:ivb */
5136 if (IS_IVB_GT1(dev))
5137 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5138 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5140 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5141 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5143 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5144 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5145 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5147 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5148 I915_WRITE(GEN7_L3CNTLREG1,
5149 GEN7_WA_FOR_GEN7_L3_CONTROL);
5150 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5151 GEN7_WA_L3_CHICKEN_MODE);
5152 if (IS_IVB_GT1(dev))
5153 I915_WRITE(GEN7_ROW_CHICKEN2,
5154 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5156 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5157 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5160 /* WaForceL3Serialization:ivb */
5161 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5162 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5164 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5165 * gating disable must be set. Failure to set it results in
5166 * flickering pixels due to Z write ordering failures after
5167 * some amount of runtime in the Mesa "fire" demo, and Unigine
5168 * Sanctuary and Tropics, and apparently anything else with
5169 * alpha test or pixel discard.
5171 * According to the spec, bit 11 (RCCUNIT) must also be set,
5172 * but we didn't debug actual testcases to find it out.
5174 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5175 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5177 I915_WRITE(GEN6_UCGCTL2,
5178 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5179 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5181 /* This is required by WaCatErrorRejectionIssue:ivb */
5182 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5183 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5184 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5186 g4x_disable_trickle_feed(dev);
5188 /* WaVSRefCountFullforceMissDisable:ivb */
5189 gen7_setup_fixed_func_scheduler(dev_priv);
5191 /* WaDisable4x2SubspanOptimization:ivb */
5192 I915_WRITE(CACHE_MODE_1,
5193 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5195 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5196 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5197 snpcr |= GEN6_MBC_SNPCR_MED;
5198 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5200 if (!HAS_PCH_NOP(dev))
5201 cpt_init_clock_gating(dev);
5203 gen6_check_mch_setup(dev);
5206 static void valleyview_init_clock_gating(struct drm_device *dev)
5208 struct drm_i915_private *dev_priv = dev->dev_private;
5210 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5212 /* WaDisableEarlyCull:vlv */
5213 I915_WRITE(_3D_CHICKEN3,
5214 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5216 /* WaDisableBackToBackFlipFix:vlv */
5217 I915_WRITE(IVB_CHICKEN3,
5218 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5219 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5221 /* WaDisablePSDDualDispatchEnable:vlv */
5222 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5223 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5224 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5226 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5227 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5228 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5230 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5231 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5232 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5234 /* WaForceL3Serialization:vlv */
5235 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5236 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5238 /* WaDisableDopClockGating:vlv */
5239 I915_WRITE(GEN7_ROW_CHICKEN2,
5240 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5242 /* This is required by WaCatErrorRejectionIssue:vlv */
5243 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5244 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5245 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5247 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5248 * gating disable must be set. Failure to set it results in
5249 * flickering pixels due to Z write ordering failures after
5250 * some amount of runtime in the Mesa "fire" demo, and Unigine
5251 * Sanctuary and Tropics, and apparently anything else with
5252 * alpha test or pixel discard.
5254 * According to the spec, bit 11 (RCCUNIT) must also be set,
5255 * but we didn't debug actual testcases to find it out.
5257 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5258 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5260 * Also apply WaDisableVDSUnitClockGating:vlv and
5261 * WaDisableRCPBUnitClockGating:vlv.
5263 I915_WRITE(GEN6_UCGCTL2,
5264 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5265 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5266 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5267 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5268 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5270 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5272 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5274 I915_WRITE(CACHE_MODE_1,
5275 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5278 * WaDisableVLVClockGating_VBIIssue:vlv
5279 * Disable clock gating on th GCFG unit to prevent a delay
5280 * in the reporting of vblank events.
5282 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5284 /* Conservative clock gating settings for now */
5285 I915_WRITE(0x9400, 0xffffffff);
5286 I915_WRITE(0x9404, 0xffffffff);
5287 I915_WRITE(0x9408, 0xffffffff);
5288 I915_WRITE(0x940c, 0xffffffff);
5289 I915_WRITE(0x9410, 0xffffffff);
5290 I915_WRITE(0x9414, 0xffffffff);
5291 I915_WRITE(0x9418, 0xffffffff);
5294 static void g4x_init_clock_gating(struct drm_device *dev)
5296 struct drm_i915_private *dev_priv = dev->dev_private;
5297 uint32_t dspclk_gate;
5299 I915_WRITE(RENCLK_GATE_D1, 0);
5300 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5301 GS_UNIT_CLOCK_GATE_DISABLE |
5302 CL_UNIT_CLOCK_GATE_DISABLE);
5303 I915_WRITE(RAMCLK_GATE_D, 0);
5304 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5305 OVRUNIT_CLOCK_GATE_DISABLE |
5306 OVCUNIT_CLOCK_GATE_DISABLE;
5308 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5309 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5311 /* WaDisableRenderCachePipelinedFlush */
5312 I915_WRITE(CACHE_MODE_0,
5313 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5315 g4x_disable_trickle_feed(dev);
5318 static void crestline_init_clock_gating(struct drm_device *dev)
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5322 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5323 I915_WRITE(RENCLK_GATE_D2, 0);
5324 I915_WRITE(DSPCLK_GATE_D, 0);
5325 I915_WRITE(RAMCLK_GATE_D, 0);
5326 I915_WRITE16(DEUC, 0);
5327 I915_WRITE(MI_ARB_STATE,
5328 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5331 static void broadwater_init_clock_gating(struct drm_device *dev)
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5335 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5336 I965_RCC_CLOCK_GATE_DISABLE |
5337 I965_RCPB_CLOCK_GATE_DISABLE |
5338 I965_ISC_CLOCK_GATE_DISABLE |
5339 I965_FBC_CLOCK_GATE_DISABLE);
5340 I915_WRITE(RENCLK_GATE_D2, 0);
5341 I915_WRITE(MI_ARB_STATE,
5342 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5345 static void gen3_init_clock_gating(struct drm_device *dev)
5347 struct drm_i915_private *dev_priv = dev->dev_private;
5348 u32 dstate = I915_READ(D_STATE);
5350 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5351 DSTATE_DOT_CLOCK_GATING;
5352 I915_WRITE(D_STATE, dstate);
5354 if (IS_PINEVIEW(dev))
5355 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5357 /* IIR "flip pending" means done if this bit is set */
5358 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5361 static void i85x_init_clock_gating(struct drm_device *dev)
5363 struct drm_i915_private *dev_priv = dev->dev_private;
5365 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5368 static void i830_init_clock_gating(struct drm_device *dev)
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5372 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5375 void intel_init_clock_gating(struct drm_device *dev)
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5379 dev_priv->display.init_clock_gating(dev);
5382 void intel_suspend_hw(struct drm_device *dev)
5384 if (HAS_PCH_LPT(dev))
5385 lpt_suspend_hw(dev);
5389 * We should only use the power well if we explicitly asked the hardware to
5390 * enable it, so check if it's enabled and also check if we've requested it to
5393 bool intel_display_power_enabled(struct drm_device *dev,
5394 enum intel_display_power_domain domain)
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5398 if (!HAS_POWER_WELL(dev))
5402 case POWER_DOMAIN_PIPE_A:
5403 case POWER_DOMAIN_TRANSCODER_EDP:
5405 case POWER_DOMAIN_VGA:
5406 case POWER_DOMAIN_PIPE_B:
5407 case POWER_DOMAIN_PIPE_C:
5408 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5409 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5410 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5411 case POWER_DOMAIN_TRANSCODER_A:
5412 case POWER_DOMAIN_TRANSCODER_B:
5413 case POWER_DOMAIN_TRANSCODER_C:
5414 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5415 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5421 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5424 bool is_enabled, enable_requested;
5427 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5428 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5429 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5432 if (!enable_requested)
5433 I915_WRITE(HSW_PWR_WELL_DRIVER,
5434 HSW_PWR_WELL_ENABLE_REQUEST);
5437 DRM_DEBUG_KMS("Enabling power well\n");
5438 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5439 HSW_PWR_WELL_STATE_ENABLED), 20))
5440 DRM_ERROR("Timeout enabling power well\n");
5443 if (enable_requested) {
5444 unsigned long irqflags;
5447 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5448 POSTING_READ(HSW_PWR_WELL_DRIVER);
5449 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5452 * After this, the registers on the pipes that are part
5453 * of the power well will become zero, so we have to
5454 * adjust our counters according to that.
5456 * FIXME: Should we do this in general in
5457 * drm_vblank_post_modeset?
5459 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5462 dev->vblank[p].last = 0;
5463 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5468 static void __intel_power_well_get(struct i915_power_well *power_well)
5470 if (!power_well->count++)
5471 __intel_set_power_well(power_well->device, true);
5474 static void __intel_power_well_put(struct i915_power_well *power_well)
5476 WARN_ON(!power_well->count);
5477 if (!--power_well->count)
5478 __intel_set_power_well(power_well->device, false);
5481 void intel_display_power_get(struct drm_device *dev,
5482 enum intel_display_power_domain domain)
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485 struct i915_power_well *power_well = &dev_priv->power_well;
5487 if (!HAS_POWER_WELL(dev))
5491 case POWER_DOMAIN_PIPE_A:
5492 case POWER_DOMAIN_TRANSCODER_EDP:
5494 case POWER_DOMAIN_VGA:
5495 case POWER_DOMAIN_PIPE_B:
5496 case POWER_DOMAIN_PIPE_C:
5497 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5498 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5499 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5500 case POWER_DOMAIN_TRANSCODER_A:
5501 case POWER_DOMAIN_TRANSCODER_B:
5502 case POWER_DOMAIN_TRANSCODER_C:
5503 spin_lock_irq(&power_well->lock);
5504 __intel_power_well_get(power_well);
5505 spin_unlock_irq(&power_well->lock);
5512 void intel_display_power_put(struct drm_device *dev,
5513 enum intel_display_power_domain domain)
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516 struct i915_power_well *power_well = &dev_priv->power_well;
5518 if (!HAS_POWER_WELL(dev))
5522 case POWER_DOMAIN_PIPE_A:
5523 case POWER_DOMAIN_TRANSCODER_EDP:
5525 case POWER_DOMAIN_VGA:
5526 case POWER_DOMAIN_PIPE_B:
5527 case POWER_DOMAIN_PIPE_C:
5528 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5529 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5530 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5531 case POWER_DOMAIN_TRANSCODER_A:
5532 case POWER_DOMAIN_TRANSCODER_B:
5533 case POWER_DOMAIN_TRANSCODER_C:
5534 spin_lock_irq(&power_well->lock);
5535 __intel_power_well_put(power_well);
5536 spin_unlock_irq(&power_well->lock);
5543 static struct i915_power_well *hsw_pwr;
5545 /* Display audio driver power well request */
5546 void i915_request_power_well(void)
5548 if (WARN_ON(!hsw_pwr))
5551 spin_lock_irq(&hsw_pwr->lock);
5552 __intel_power_well_get(hsw_pwr);
5553 spin_unlock_irq(&hsw_pwr->lock);
5555 EXPORT_SYMBOL_GPL(i915_request_power_well);
5557 /* Display audio driver power well release */
5558 void i915_release_power_well(void)
5560 if (WARN_ON(!hsw_pwr))
5563 spin_lock_irq(&hsw_pwr->lock);
5564 __intel_power_well_put(hsw_pwr);
5565 spin_unlock_irq(&hsw_pwr->lock);
5567 EXPORT_SYMBOL_GPL(i915_release_power_well);
5569 int i915_init_power_well(struct drm_device *dev)
5571 struct drm_i915_private *dev_priv = dev->dev_private;
5573 hsw_pwr = &dev_priv->power_well;
5575 hsw_pwr->device = dev;
5576 spin_lock_init(&hsw_pwr->lock);
5582 void i915_remove_power_well(struct drm_device *dev)
5587 void intel_set_power_well(struct drm_device *dev, bool enable)
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 struct i915_power_well *power_well = &dev_priv->power_well;
5592 if (!HAS_POWER_WELL(dev))
5595 if (!i915_disable_power_well && !enable)
5598 spin_lock_irq(&power_well->lock);
5601 * This function will only ever contribute one
5602 * to the power well reference count. i915_request
5603 * is what tracks whether we have or have not
5604 * added the one to the reference count.
5606 if (power_well->i915_request == enable)
5609 power_well->i915_request = enable;
5612 __intel_power_well_get(power_well);
5614 __intel_power_well_put(power_well);
5617 spin_unlock_irq(&power_well->lock);
5620 static void intel_resume_power_well(struct drm_device *dev)
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 struct i915_power_well *power_well = &dev_priv->power_well;
5625 if (!HAS_POWER_WELL(dev))
5628 spin_lock_irq(&power_well->lock);
5629 __intel_set_power_well(dev, power_well->count > 0);
5630 spin_unlock_irq(&power_well->lock);
5634 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5635 * when not needed anymore. We have 4 registers that can request the power well
5636 * to be enabled, and it will only be disabled if none of the registers is
5637 * requesting it to be enabled.
5639 void intel_init_power_well(struct drm_device *dev)
5641 struct drm_i915_private *dev_priv = dev->dev_private;
5643 if (!HAS_POWER_WELL(dev))
5646 /* For now, we need the power well to be always enabled. */
5647 intel_set_power_well(dev, true);
5648 intel_resume_power_well(dev);
5650 /* We're taking over the BIOS, so clear any requests made by it since
5651 * the driver is in charge now. */
5652 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5653 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5656 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5657 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5659 hsw_disable_package_c8(dev_priv);
5662 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5664 hsw_enable_package_c8(dev_priv);
5667 /* Set up chip specific power management-related functions */
5668 void intel_init_pm(struct drm_device *dev)
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5672 if (I915_HAS_FBC(dev)) {
5673 if (HAS_PCH_SPLIT(dev)) {
5674 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5675 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5676 dev_priv->display.enable_fbc =
5679 dev_priv->display.enable_fbc =
5680 ironlake_enable_fbc;
5681 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5682 } else if (IS_GM45(dev)) {
5683 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5684 dev_priv->display.enable_fbc = g4x_enable_fbc;
5685 dev_priv->display.disable_fbc = g4x_disable_fbc;
5686 } else if (IS_CRESTLINE(dev)) {
5687 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5688 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5689 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5691 /* 855GM needs testing */
5695 if (IS_PINEVIEW(dev))
5696 i915_pineview_get_mem_freq(dev);
5697 else if (IS_GEN5(dev))
5698 i915_ironlake_get_mem_freq(dev);
5700 /* For FIFO watermark updates */
5701 if (HAS_PCH_SPLIT(dev)) {
5702 intel_setup_wm_latency(dev);
5705 if (dev_priv->wm.pri_latency[1] &&
5706 dev_priv->wm.spr_latency[1] &&
5707 dev_priv->wm.cur_latency[1])
5708 dev_priv->display.update_wm = ironlake_update_wm;
5710 DRM_DEBUG_KMS("Failed to get proper latency. "
5712 dev_priv->display.update_wm = NULL;
5714 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5715 } else if (IS_GEN6(dev)) {
5716 if (dev_priv->wm.pri_latency[0] &&
5717 dev_priv->wm.spr_latency[0] &&
5718 dev_priv->wm.cur_latency[0]) {
5719 dev_priv->display.update_wm = sandybridge_update_wm;
5720 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5722 DRM_DEBUG_KMS("Failed to read display plane latency. "
5724 dev_priv->display.update_wm = NULL;
5726 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5727 } else if (IS_IVYBRIDGE(dev)) {
5728 if (dev_priv->wm.pri_latency[0] &&
5729 dev_priv->wm.spr_latency[0] &&
5730 dev_priv->wm.cur_latency[0]) {
5731 dev_priv->display.update_wm = ivybridge_update_wm;
5732 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5734 DRM_DEBUG_KMS("Failed to read display plane latency. "
5736 dev_priv->display.update_wm = NULL;
5738 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5739 } else if (IS_HASWELL(dev)) {
5740 if (dev_priv->wm.pri_latency[0] &&
5741 dev_priv->wm.spr_latency[0] &&
5742 dev_priv->wm.cur_latency[0]) {
5743 dev_priv->display.update_wm = haswell_update_wm;
5744 dev_priv->display.update_sprite_wm =
5745 haswell_update_sprite_wm;
5747 DRM_DEBUG_KMS("Failed to read display plane latency. "
5749 dev_priv->display.update_wm = NULL;
5751 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5753 dev_priv->display.update_wm = NULL;
5754 } else if (IS_VALLEYVIEW(dev)) {
5755 dev_priv->display.update_wm = valleyview_update_wm;
5756 dev_priv->display.init_clock_gating =
5757 valleyview_init_clock_gating;
5758 } else if (IS_PINEVIEW(dev)) {
5759 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5762 dev_priv->mem_freq)) {
5763 DRM_INFO("failed to find known CxSR latency "
5764 "(found ddr%s fsb freq %d, mem freq %d), "
5766 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5767 dev_priv->fsb_freq, dev_priv->mem_freq);
5768 /* Disable CxSR and never update its watermark again */
5769 pineview_disable_cxsr(dev);
5770 dev_priv->display.update_wm = NULL;
5772 dev_priv->display.update_wm = pineview_update_wm;
5773 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5774 } else if (IS_G4X(dev)) {
5775 dev_priv->display.update_wm = g4x_update_wm;
5776 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5777 } else if (IS_GEN4(dev)) {
5778 dev_priv->display.update_wm = i965_update_wm;
5779 if (IS_CRESTLINE(dev))
5780 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5781 else if (IS_BROADWATER(dev))
5782 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5783 } else if (IS_GEN3(dev)) {
5784 dev_priv->display.update_wm = i9xx_update_wm;
5785 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5786 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5787 } else if (IS_I865G(dev)) {
5788 dev_priv->display.update_wm = i830_update_wm;
5789 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5790 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5791 } else if (IS_I85X(dev)) {
5792 dev_priv->display.update_wm = i9xx_update_wm;
5793 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5794 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5796 dev_priv->display.update_wm = i830_update_wm;
5797 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5799 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5801 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5805 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5807 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5809 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5810 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5814 I915_WRITE(GEN6_PCODE_DATA, *val);
5815 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5817 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5819 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5823 *val = I915_READ(GEN6_PCODE_DATA);
5824 I915_WRITE(GEN6_PCODE_DATA, 0);
5829 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5831 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5833 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5834 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5838 I915_WRITE(GEN6_PCODE_DATA, val);
5839 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5841 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5843 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5847 I915_WRITE(GEN6_PCODE_DATA, 0);
5852 int vlv_gpu_freq(int ddr_freq, int val)
5873 return ((val - 0xbd) * mult) + base;
5876 int vlv_freq_opcode(int ddr_freq, int val)
5907 void intel_pm_init(struct drm_device *dev)
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5911 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5912 intel_gen6_powersave_work);