drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /* Rough estimate of the typical request size, performing a flush,
  38  * set-context and then emitting the batch.
  39  */
  40 #define LEGACY_REQUEST_SIZE 200
  41
  42 int __intel_ring_space(int head, int tail, int size)
  43 {
  44         int space = head - tail;
  45         if (space <= 0)
  46                 space += size;
  47         return space - I915_RING_FREE_SPACE;
  48 }
  49
  50 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  51 {
  52         if (ringbuf->last_retired_head != -1) {
  53                 ringbuf->head = ringbuf->last_retired_head;
  54                 ringbuf->last_retired_head = -1;
  55         }
  56
  57         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  58                                             ringbuf->tail, ringbuf->size);
  59 }
  60
  61 bool intel_engine_stopped(struct intel_engine_cs *engine)
  62 {
  63         struct drm_i915_private *dev_priv = engine->i915;
  64         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  65 }
  66
  67 static void __intel_ring_advance(struct intel_engine_cs *engine)
  68 {
  69         struct intel_ringbuffer *ringbuf = engine->buffer;
  70         ringbuf->tail &= ringbuf->size - 1;
  71         if (intel_engine_stopped(engine))
  72                 return;
  73         engine->write_tail(engine, ringbuf->tail);
  74 }
  75
  76 static int
  77 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  78                        u32      invalidate_domains,
  79                        u32      flush_domains)
  80 {
  81         struct intel_engine_cs *engine = req->engine;
  82         u32 cmd;
  83         int ret;
  84
  85         cmd = MI_FLUSH;
  86         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  87                 cmd |= MI_NO_WRITE_FLUSH;
  88
  89         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  90                 cmd |= MI_READ_FLUSH;
  91
  92         ret = intel_ring_begin(req, 2);
  93         if (ret)
  94                 return ret;
  95
  96         intel_ring_emit(engine, cmd);
  97         intel_ring_emit(engine, MI_NOOP);
  98         intel_ring_advance(engine);
  99
 100         return 0;
 101 }
 102
 103 static int
 104 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 105                        u32      invalidate_domains,
 106                        u32      flush_domains)
 107 {
 108         struct intel_engine_cs *engine = req->engine;
 109         u32 cmd;
 110         int ret;
 111
 112         /*
 113          * read/write caches:
 114          *
 115          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 116          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 117          * also flushed at 2d versus 3d pipeline switches.
 118          *
 119          * read-only caches:
 120          *
 121          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 122          * MI_READ_FLUSH is set, and is always flushed on 965.
 123          *
 124          * I915_GEM_DOMAIN_COMMAND may not exist?
 125          *
 126          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 127          * invalidated when MI_EXE_FLUSH is set.
 128          *
 129          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 130          * invalidated with every MI_FLUSH.
 131          *
 132          * TLBs:
 133          *
 134          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 135          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 136          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 137          * are flushed at any MI_FLUSH.
 138          */
 139
 140         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 141         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 142                 cmd &= ~MI_NO_WRITE_FLUSH;
 143         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 144                 cmd |= MI_EXE_FLUSH;
 145
 146         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 147             (IS_G4X(req->i915) || IS_GEN5(req->i915)))
 148                 cmd |= MI_INVALIDATE_ISP;
 149
 150         ret = intel_ring_begin(req, 2);
 151         if (ret)
 152                 return ret;
 153
 154         intel_ring_emit(engine, cmd);
 155         intel_ring_emit(engine, MI_NOOP);
 156         intel_ring_advance(engine);
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 163  * implementing two workarounds on gen6.  From section 1.4.7.1
 164  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 165  *
 166  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 167  * produced by non-pipelined state commands), software needs to first
 168  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 169  * 0.
 170  *
 171  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 172  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 173  *
 174  * And the workaround for these two requires this workaround first:
 175  *
 176  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 177  * BEFORE the pipe-control with a post-sync op and no write-cache
 178  * flushes.
 179  *
 180  * And this last workaround is tricky because of the requirements on
 181  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 182  * volume 2 part 1:
 183  *
 184  *     "1 of the following must also be set:
 185  *      - Render Target Cache Flush Enable ([12] of DW1)
 186  *      - Depth Cache Flush Enable ([0] of DW1)
 187  *      - Stall at Pixel Scoreboard ([1] of DW1)
 188  *      - Depth Stall ([13] of DW1)
 189  *      - Post-Sync Operation ([13] of DW1)
 190  *      - Notify Enable ([8] of DW1)"
 191  *
 192  * The cache flushes require the workaround flush that triggered this
 193  * one, so we can't use it.  Depth stall would trigger the same.
 194  * Post-sync nonzero is what triggered this second workaround, so we
 195  * can't use that one either.  Notify enable is IRQs, which aren't
 196  * really our business.  That leaves only stall at scoreboard.
 197  */
 198 static int
 199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 200 {
 201         struct intel_engine_cs *engine = req->engine;
 202         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 203         int ret;
 204
 205         ret = intel_ring_begin(req, 6);
 206         if (ret)
 207                 return ret;
 208
 209         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 210         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 211                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 212         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 213         intel_ring_emit(engine, 0); /* low dword */
 214         intel_ring_emit(engine, 0); /* high dword */
 215         intel_ring_emit(engine, MI_NOOP);
 216         intel_ring_advance(engine);
 217
 218         ret = intel_ring_begin(req, 6);
 219         if (ret)
 220                 return ret;
 221
 222         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 223         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 224         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 225         intel_ring_emit(engine, 0);
 226         intel_ring_emit(engine, 0);
 227         intel_ring_emit(engine, MI_NOOP);
 228         intel_ring_advance(engine);
 229
 230         return 0;
 231 }
 232
 233 static int
 234 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 235                        u32 invalidate_domains, u32 flush_domains)
 236 {
 237         struct intel_engine_cs *engine = req->engine;
 238         u32 flags = 0;
 239         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 240         int ret;
 241
 242         /* Force SNB workarounds for PIPE_CONTROL flushes */
 243         ret = intel_emit_post_sync_nonzero_flush(req);
 244         if (ret)
 245                 return ret;
 246
 247         /* Just flush everything.  Experiments have shown that reducing the
 248          * number of bits based on the write domains has little performance
 249          * impact.
 250          */
 251         if (flush_domains) {
 252                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 253                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 254                 /*
 255                  * Ensure that any following seqno writes only happen
 256                  * when the render cache is indeed flushed.
 257                  */
 258                 flags |= PIPE_CONTROL_CS_STALL;
 259         }
 260         if (invalidate_domains) {
 261                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 262                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 263                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 264                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 265                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 266                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 267                 /*
 268                  * TLB invalidate requires a post-sync write.
 269                  */
 270                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 271         }
 272
 273         ret = intel_ring_begin(req, 4);
 274         if (ret)
 275                 return ret;
 276
 277         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 278         intel_ring_emit(engine, flags);
 279         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 280         intel_ring_emit(engine, 0);
 281         intel_ring_advance(engine);
 282
 283         return 0;
 284 }
 285
 286 static int
 287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 288 {
 289         struct intel_engine_cs *engine = req->engine;
 290         int ret;
 291
 292         ret = intel_ring_begin(req, 4);
 293         if (ret)
 294                 return ret;
 295
 296         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 297         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 298                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 299         intel_ring_emit(engine, 0);
 300         intel_ring_emit(engine, 0);
 301         intel_ring_advance(engine);
 302
 303         return 0;
 304 }
 305
 306 static int
 307 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 308                        u32 invalidate_domains, u32 flush_domains)
 309 {
 310         struct intel_engine_cs *engine = req->engine;
 311         u32 flags = 0;
 312         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 313         int ret;
 314
 315         /*
 316          * Ensure that any following seqno writes only happen when the render
 317          * cache is indeed flushed.
 318          *
 319          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 320          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 321          * don't try to be clever and just set it unconditionally.
 322          */
 323         flags |= PIPE_CONTROL_CS_STALL;
 324
 325         /* Just flush everything.  Experiments have shown that reducing the
 326          * number of bits based on the write domains has little performance
 327          * impact.
 328          */
 329         if (flush_domains) {
 330                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 331                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 332                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 333                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 334         }
 335         if (invalidate_domains) {
 336                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 337                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 339                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 340                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 341                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 342                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 343                 /*
 344                  * TLB invalidate requires a post-sync write.
 345                  */
 346                 flags |= PIPE_CONTROL_QW_WRITE;
 347                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 348
 349                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 350
 351                 /* Workaround: we must issue a pipe_control with CS-stall bit
 352                  * set before a pipe_control command that has the state cache
 353                  * invalidate bit set. */
 354                 gen7_render_ring_cs_stall_wa(req);
 355         }
 356
 357         ret = intel_ring_begin(req, 4);
 358         if (ret)
 359                 return ret;
 360
 361         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 362         intel_ring_emit(engine, flags);
 363         intel_ring_emit(engine, scratch_addr);
 364         intel_ring_emit(engine, 0);
 365         intel_ring_advance(engine);
 366
 367         return 0;
 368 }
 369
 370 static int
 371 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 372                        u32 flags, u32 scratch_addr)
 373 {
 374         struct intel_engine_cs *engine = req->engine;
 375         int ret;
 376
 377         ret = intel_ring_begin(req, 6);
 378         if (ret)
 379                 return ret;
 380
 381         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 382         intel_ring_emit(engine, flags);
 383         intel_ring_emit(engine, scratch_addr);
 384         intel_ring_emit(engine, 0);
 385         intel_ring_emit(engine, 0);
 386         intel_ring_emit(engine, 0);
 387         intel_ring_advance(engine);
 388
 389         return 0;
 390 }
 391
 392 static int
 393 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 394                        u32 invalidate_domains, u32 flush_domains)
 395 {
 396         u32 flags = 0;
 397         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 398         int ret;
 399
 400         flags |= PIPE_CONTROL_CS_STALL;
 401
 402         if (flush_domains) {
 403                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 404                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 405                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 406                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 407         }
 408         if (invalidate_domains) {
 409                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 410                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 412                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 413                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 414                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 415                 flags |= PIPE_CONTROL_QW_WRITE;
 416                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 417
 418                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 419                 ret = gen8_emit_pipe_control(req,
 420                                              PIPE_CONTROL_CS_STALL |
 421                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 422                                              0);
 423                 if (ret)
 424                         return ret;
 425         }
 426
 427         return gen8_emit_pipe_control(req, flags, scratch_addr);
 428 }
 429
 430 static void ring_write_tail(struct intel_engine_cs *engine,
 431                             u32 value)
 432 {
 433         struct drm_i915_private *dev_priv = engine->i915;
 434         I915_WRITE_TAIL(engine, value);
 435 }
 436
 437 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 438 {
 439         struct drm_i915_private *dev_priv = engine->i915;
 440         u64 acthd;
 441
 442         if (INTEL_GEN(dev_priv) >= 8)
 443                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 444                                          RING_ACTHD_UDW(engine->mmio_base));
 445         else if (INTEL_GEN(dev_priv) >= 4)
 446                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 447         else
 448                 acthd = I915_READ(ACTHD);
 449
 450         return acthd;
 451 }
 452
 453 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 454 {
 455         struct drm_i915_private *dev_priv = engine->i915;
 456         u32 addr;
 457
 458         addr = dev_priv->status_page_dmah->busaddr;
 459         if (INTEL_GEN(dev_priv) >= 4)
 460                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 461         I915_WRITE(HWS_PGA, addr);
 462 }
 463
 464 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 465 {
 466         struct drm_i915_private *dev_priv = engine->i915;
 467         i915_reg_t mmio;
 468
 469         /* The ring status page addresses are no longer next to the rest of
 470          * the ring registers as of gen7.
 471          */
 472         if (IS_GEN7(dev_priv)) {
 473                 switch (engine->id) {
 474                 case RCS:
 475                         mmio = RENDER_HWS_PGA_GEN7;
 476                         break;
 477                 case BCS:
 478                         mmio = BLT_HWS_PGA_GEN7;
 479                         break;
 480                 /*
 481                  * VCS2 actually doesn't exist on Gen7. Only shut up
 482                  * gcc switch check warning
 483                  */
 484                 case VCS2:
 485                 case VCS:
 486                         mmio = BSD_HWS_PGA_GEN7;
 487                         break;
 488                 case VECS:
 489                         mmio = VEBOX_HWS_PGA_GEN7;
 490                         break;
 491                 }
 492         } else if (IS_GEN6(dev_priv)) {
 493                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 494         } else {
 495                 /* XXX: gen8 returns to sanity */
 496                 mmio = RING_HWS_PGA(engine->mmio_base);
 497         }
 498
 499         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 500         POSTING_READ(mmio);
 501
 502         /*
 503          * Flush the TLB for this page
 504          *
 505          * FIXME: These two bits have disappeared on gen8, so a question
 506          * arises: do we still need this and if so how should we go about
 507          * invalidating the TLB?
 508          */
 509         if (IS_GEN(dev_priv, 6, 7)) {
 510                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 511
 512                 /* ring should be idle before issuing a sync flush*/
 513                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 514
 515                 I915_WRITE(reg,
 516                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 517                                               INSTPM_SYNC_FLUSH));
 518                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 519                              1000))
 520                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 521                                   engine->name);
 522         }
 523 }
 524
 525 static bool stop_ring(struct intel_engine_cs *engine)
 526 {
 527         struct drm_i915_private *dev_priv = engine->i915;
 528
 529         if (!IS_GEN2(dev_priv)) {
 530                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 531                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 532                         DRM_ERROR("%s : timed out trying to stop ring\n",
 533                                   engine->name);
 534                         /* Sometimes we observe that the idle flag is not
 535                          * set even though the ring is empty. So double
 536                          * check before giving up.
 537                          */
 538                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 539                                 return false;
 540                 }
 541         }
 542
 543         I915_WRITE_CTL(engine, 0);
 544         I915_WRITE_HEAD(engine, 0);
 545         engine->write_tail(engine, 0);
 546
 547         if (!IS_GEN2(dev_priv)) {
 548                 (void)I915_READ_CTL(engine);
 549                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 550         }
 551
 552         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 553 }
 554
 555 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 556 {
 557         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 558 }
 559
 560 static int init_ring_common(struct intel_engine_cs *engine)
 561 {
 562         struct drm_i915_private *dev_priv = engine->i915;
 563         struct intel_ringbuffer *ringbuf = engine->buffer;
 564         struct drm_i915_gem_object *obj = ringbuf->obj;
 565         int ret = 0;
 566
 567         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 568
 569         if (!stop_ring(engine)) {
 570                 /* G45 ring initialization often fails to reset head to zero */
 571                 DRM_DEBUG_KMS("%s head not reset to zero "
 572                               "ctl %08x head %08x tail %08x start %08x\n",
 573                               engine->name,
 574                               I915_READ_CTL(engine),
 575                               I915_READ_HEAD(engine),
 576                               I915_READ_TAIL(engine),
 577                               I915_READ_START(engine));
 578
 579                 if (!stop_ring(engine)) {
 580                         DRM_ERROR("failed to set %s head to zero "
 581                                   "ctl %08x head %08x tail %08x start %08x\n",
 582                                   engine->name,
 583                                   I915_READ_CTL(engine),
 584                                   I915_READ_HEAD(engine),
 585                                   I915_READ_TAIL(engine),
 586                                   I915_READ_START(engine));
 587                         ret = -EIO;
 588                         goto out;
 589                 }
 590         }
 591
 592         if (I915_NEED_GFX_HWS(dev_priv))
 593                 intel_ring_setup_status_page(engine);
 594         else
 595                 ring_setup_phys_status_page(engine);
 596
 597         /* Enforce ordering by reading HEAD register back */
 598         I915_READ_HEAD(engine);
 599
 600         /* Initialize the ring. This must happen _after_ we've cleared the ring
 601          * registers with the above sequence (the readback of the HEAD registers
 602          * also enforces ordering), otherwise the hw might lose the new ring
 603          * register values. */
 604         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 605
 606         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 607         if (I915_READ_HEAD(engine))
 608                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 609                           engine->name, I915_READ_HEAD(engine));
 610         I915_WRITE_HEAD(engine, 0);
 611         (void)I915_READ_HEAD(engine);
 612
 613         I915_WRITE_CTL(engine,
 614                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 615                         | RING_VALID);
 616
 617         /* If the head is still not zero, the ring is dead */
 618         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 619                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 620                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 621                 DRM_ERROR("%s initialization failed "
 622                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 623                           engine->name,
 624                           I915_READ_CTL(engine),
 625                           I915_READ_CTL(engine) & RING_VALID,
 626                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 627                           I915_READ_START(engine),
 628                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 629                 ret = -EIO;
 630                 goto out;
 631         }
 632
 633         ringbuf->last_retired_head = -1;
 634         ringbuf->head = I915_READ_HEAD(engine);
 635         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 636         intel_ring_update_space(ringbuf);
 637
 638         intel_engine_init_hangcheck(engine);
 639
 640 out:
 641         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 642
 643         return ret;
 644 }
 645
 646 void
 647 intel_fini_pipe_control(struct intel_engine_cs *engine)
 648 {
 649         if (engine->scratch.obj == NULL)
 650                 return;
 651
 652         if (INTEL_GEN(engine->i915) >= 5) {
 653                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 654                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 655         }
 656
 657         drm_gem_object_unreference(&engine->scratch.obj->base);
 658         engine->scratch.obj = NULL;
 659 }
 660
 661 int
 662 intel_init_pipe_control(struct intel_engine_cs *engine)
 663 {
 664         int ret;
 665
 666         WARN_ON(engine->scratch.obj);
 667
 668         engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
 669         if (IS_ERR(engine->scratch.obj)) {
 670                 DRM_ERROR("Failed to allocate seqno page\n");
 671                 ret = PTR_ERR(engine->scratch.obj);
 672                 engine->scratch.obj = NULL;
 673                 goto err;
 674         }
 675
 676         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 677                                               I915_CACHE_LLC);
 678         if (ret)
 679                 goto err_unref;
 680
 681         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 682         if (ret)
 683                 goto err_unref;
 684
 685         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 686         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 687         if (engine->scratch.cpu_page == NULL) {
 688                 ret = -ENOMEM;
 689                 goto err_unpin;
 690         }
 691
 692         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 693                          engine->name, engine->scratch.gtt_offset);
 694         return 0;
 695
 696 err_unpin:
 697         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 698 err_unref:
 699         drm_gem_object_unreference(&engine->scratch.obj->base);
 700 err:
 701         return ret;
 702 }
 703
 704 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 705 {
 706         struct intel_engine_cs *engine = req->engine;
 707         struct i915_workarounds *w = &req->i915->workarounds;
 708         int ret, i;
 709
 710         if (w->count == 0)
 711                 return 0;
 712
 713         engine->gpu_caches_dirty = true;
 714         ret = intel_ring_flush_all_caches(req);
 715         if (ret)
 716                 return ret;
 717
 718         ret = intel_ring_begin(req, (w->count * 2 + 2));
 719         if (ret)
 720                 return ret;
 721
 722         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 723         for (i = 0; i < w->count; i++) {
 724                 intel_ring_emit_reg(engine, w->reg[i].addr);
 725                 intel_ring_emit(engine, w->reg[i].value);
 726         }
 727         intel_ring_emit(engine, MI_NOOP);
 728
 729         intel_ring_advance(engine);
 730
 731         engine->gpu_caches_dirty = true;
 732         ret = intel_ring_flush_all_caches(req);
 733         if (ret)
 734                 return ret;
 735
 736         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 737
 738         return 0;
 739 }
 740
 741 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 742 {
 743         int ret;
 744
 745         ret = intel_ring_workarounds_emit(req);
 746         if (ret != 0)
 747                 return ret;
 748
 749         ret = i915_gem_render_state_init(req);
 750         if (ret)
 751                 return ret;
 752
 753         return 0;
 754 }
 755
 756 static int wa_add(struct drm_i915_private *dev_priv,
 757                   i915_reg_t addr,
 758                   const u32 mask, const u32 val)
 759 {
 760         const u32 idx = dev_priv->workarounds.count;
 761
 762         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 763                 return -ENOSPC;
 764
 765         dev_priv->workarounds.reg[idx].addr = addr;
 766         dev_priv->workarounds.reg[idx].value = val;
 767         dev_priv->workarounds.reg[idx].mask = mask;
 768
 769         dev_priv->workarounds.count++;
 770
 771         return 0;
 772 }
 773
 774 #define WA_REG(addr, mask, val) do { \
 775                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 776                 if (r) \
 777                         return r; \
 778         } while (0)
 779
 780 #define WA_SET_BIT_MASKED(addr, mask) \
 781         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 782
 783 #define WA_CLR_BIT_MASKED(addr, mask) \
 784         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 785
 786 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 787         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 788
 789 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 790 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 791
 792 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 793
 794 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 795                                  i915_reg_t reg)
 796 {
 797         struct drm_i915_private *dev_priv = engine->i915;
 798         struct i915_workarounds *wa = &dev_priv->workarounds;
 799         const uint32_t index = wa->hw_whitelist_count[engine->id];
 800
 801         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 802                 return -EINVAL;
 803
 804         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 805                  i915_mmio_reg_offset(reg));
 806         wa->hw_whitelist_count[engine->id]++;
 807
 808         return 0;
 809 }
 810
 811 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 812 {
 813         struct drm_i915_private *dev_priv = engine->i915;
 814
 815         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 816
 817         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 818         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 819
 820         /* WaDisablePartialInstShootdown:bdw,chv */
 821         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 822                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 823
 824         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 825          * workaround for for a possible hang in the unlikely event a TLB
 826          * invalidation occurs during a PSD flush.
 827          */
 828         /* WaForceEnableNonCoherent:bdw,chv */
 829         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 830         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 831                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 832                           HDC_FORCE_NON_COHERENT);
 833
 834         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 835          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 836          *  polygons in the same 8x4 pixel/sample area to be processed without
 837          *  stalling waiting for the earlier ones to write to Hierarchical Z
 838          *  buffer."
 839          *
 840          * This optimization is off by default for BDW and CHV; turn it on.
 841          */
 842         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 843
 844         /* Wa4x4STCOptimizationDisable:bdw,chv */
 845         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 846
 847         /*
 848          * BSpec recommends 8x4 when MSAA is used,
 849          * however in practice 16x4 seems fastest.
 850          *
 851          * Note that PS/WM thread counts depend on the WIZ hashing
 852          * disable bit, which we don't touch here, but it's good
 853          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 854          */
 855         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 856                             GEN6_WIZ_HASHING_MASK,
 857                             GEN6_WIZ_HASHING_16x4);
 858
 859         return 0;
 860 }
 861
 862 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 863 {
 864         struct drm_i915_private *dev_priv = engine->i915;
 865         int ret;
 866
 867         ret = gen8_init_workarounds(engine);
 868         if (ret)
 869                 return ret;
 870
 871         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 872         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 873
 874         /* WaDisableDopClockGating:bdw */
 875         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 876                           DOP_CLOCK_GATING_DISABLE);
 877
 878         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 879                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 880
 881         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 882                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 883                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 884                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 885                           (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 886
 887         return 0;
 888 }
 889
 890 static int chv_init_workarounds(struct intel_engine_cs *engine)
 891 {
 892         struct drm_i915_private *dev_priv = engine->i915;
 893         int ret;
 894
 895         ret = gen8_init_workarounds(engine);
 896         if (ret)
 897                 return ret;
 898
 899         /* WaDisableThreadStallDopClockGating:chv */
 900         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 901
 902         /* Improve HiZ throughput on CHV. */
 903         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 904
 905         return 0;
 906 }
 907
 908 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 909 {
 910         struct drm_i915_private *dev_priv = engine->i915;
 911         uint32_t tmp;
 912         int ret;
 913
 914         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 915         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 916                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 917
 918         /* WaDisableKillLogic:bxt,skl */
 919         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 920                    ECOCHK_DIS_TLB);
 921
 922         /* WaClearFlowControlGpgpuContextSave:skl,bxt */
 923         /* WaDisablePartialInstShootdown:skl,bxt */
 924         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 925                           FLOW_CONTROL_ENABLE |
 926                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 927
 928         /* Syncing dependencies between camera and graphics:skl,bxt */
 929         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 930                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 931
 932         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 933         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 934             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 935                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 936                                   GEN9_DG_MIRROR_FIX_ENABLE);
 937
 938         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 939         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 940             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 941                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 942                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 943                 /*
 944                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 945                  * but we do that in per ctx batchbuffer as there is an issue
 946                  * with this register not getting restored on ctx restore
 947                  */
 948         }
 949
 950         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 951         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
 952         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 953                           GEN9_ENABLE_YV12_BUGFIX |
 954                           GEN9_ENABLE_GPGPU_PREEMPTION);
 955
 956         /* Wa4x4STCOptimizationDisable:skl,bxt */
 957         /* WaDisablePartialResolveInVc:skl,bxt */
 958         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 959                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 960
 961         /* WaCcsTlbPrefetchDisable:skl,bxt */
 962         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 963                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 964
 965         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 966         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
 967             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 968                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 969                                   PIXEL_MASK_CAMMING_DISABLE);
 970
 971         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 972         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 973         if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
 974             IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 975                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 976         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 977
 978         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 979         if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 980                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 981                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 982
 983         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 984         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 985
 986         /* WaOCLCoherentLineFlush:skl,bxt */
 987         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 988                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 989
 990         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
 991         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 992         if (ret)
 993                 return ret;
 994
 995         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
 996         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
 997         if (ret)
 998                 return ret;
 999
1000         return 0;
1001 }
1002
1003 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1004 {
1005         struct drm_i915_private *dev_priv = engine->i915;
1006         u8 vals[3] = { 0, 0, 0 };
1007         unsigned int i;
1008
1009         for (i = 0; i < 3; i++) {
1010                 u8 ss;
1011
1012                 /*
1013                  * Only consider slices where one, and only one, subslice has 7
1014                  * EUs
1015                  */
1016                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1017                         continue;
1018
1019                 /*
1020                  * subslice_7eu[i] != 0 (because of the check above) and
1021                  * ss_max == 4 (maximum number of subslices possible per slice)
1022                  *
1023                  * ->    0 <= ss <= 3;
1024                  */
1025                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1026                 vals[i] = 3 - ss;
1027         }
1028
1029         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1030                 return 0;
1031
1032         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1033         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1034                             GEN9_IZ_HASHING_MASK(2) |
1035                             GEN9_IZ_HASHING_MASK(1) |
1036                             GEN9_IZ_HASHING_MASK(0),
1037                             GEN9_IZ_HASHING(2, vals[2]) |
1038                             GEN9_IZ_HASHING(1, vals[1]) |
1039                             GEN9_IZ_HASHING(0, vals[0]));
1040
1041         return 0;
1042 }
1043
1044 static int skl_init_workarounds(struct intel_engine_cs *engine)
1045 {
1046         struct drm_i915_private *dev_priv = engine->i915;
1047         int ret;
1048
1049         ret = gen9_init_workarounds(engine);
1050         if (ret)
1051                 return ret;
1052
1053         /*
1054          * Actual WA is to disable percontext preemption granularity control
1055          * until D0 which is the default case so this is equivalent to
1056          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1057          */
1058         if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
1059                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1060                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1061         }
1062
1063         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
1064                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1065                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1066                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1067         }
1068
1069         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1070          * involving this register should also be added to WA batch as required.
1071          */
1072         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1073                 /* WaDisableLSQCROPERFforOCL:skl */
1074                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1075                            GEN8_LQSC_RO_PERF_DIS);
1076
1077         /* WaEnableGapsTsvCreditFix:skl */
1078         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1079                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1080                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1081         }
1082
1083         /* WaDisablePowerCompilerClockGating:skl */
1084         if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1085                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1086                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1087
1088         /* This is tied to WaForceContextSaveRestoreNonCoherent */
1089         if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
1090                 /*
1091                  *Use Force Non-Coherent whenever executing a 3D context. This
1092                  * is a workaround for a possible hang in the unlikely event
1093                  * a TLB invalidation occurs during a PSD flush.
1094                  */
1095                 /* WaForceEnableNonCoherent:skl */
1096                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1097                                   HDC_FORCE_NON_COHERENT);
1098
1099                 /* WaDisableHDCInvalidation:skl */
1100                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1101                            BDW_DISABLE_HDC_INVALIDATION);
1102         }
1103
1104         /* WaBarrierPerformanceFixDisable:skl */
1105         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1106                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1107                                   HDC_FENCE_DEST_SLM_DISABLE |
1108                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1109
1110         /* WaDisableSbeCacheDispatchPortSharing:skl */
1111         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1112                 WA_SET_BIT_MASKED(
1113                         GEN7_HALF_SLICE_CHICKEN1,
1114                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1115
1116         /* WaDisableLSQCROPERFforOCL:skl */
1117         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1118         if (ret)
1119                 return ret;
1120
1121         return skl_tune_iz_hashing(engine);
1122 }
1123
1124 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1125 {
1126         struct drm_i915_private *dev_priv = engine->i915;
1127         int ret;
1128
1129         ret = gen9_init_workarounds(engine);
1130         if (ret)
1131                 return ret;
1132
1133         /* WaStoreMultiplePTEenable:bxt */
1134         /* This is a requirement according to Hardware specification */
1135         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1136                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1137
1138         /* WaSetClckGatingDisableMedia:bxt */
1139         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1140                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1141                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1142         }
1143
1144         /* WaDisableThreadStallDopClockGating:bxt */
1145         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1146                           STALL_DOP_GATING_DISABLE);
1147
1148         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1149         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1150                 WA_SET_BIT_MASKED(
1151                         GEN7_HALF_SLICE_CHICKEN1,
1152                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1153         }
1154
1155         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1156         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1157         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1158         /* WaDisableLSQCROPERFforOCL:bxt */
1159         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1160                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1161                 if (ret)
1162                         return ret;
1163
1164                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1165                 if (ret)
1166                         return ret;
1167         }
1168
1169         /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1170         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1171                 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1172                                            L3_HIGH_PRIO_CREDITS(2));
1173
1174         return 0;
1175 }
1176
1177 int init_workarounds_ring(struct intel_engine_cs *engine)
1178 {
1179         struct drm_i915_private *dev_priv = engine->i915;
1180
1181         WARN_ON(engine->id != RCS);
1182
1183         dev_priv->workarounds.count = 0;
1184         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1185
1186         if (IS_BROADWELL(dev_priv))
1187                 return bdw_init_workarounds(engine);
1188
1189         if (IS_CHERRYVIEW(dev_priv))
1190                 return chv_init_workarounds(engine);
1191
1192         if (IS_SKYLAKE(dev_priv))
1193                 return skl_init_workarounds(engine);
1194
1195         if (IS_BROXTON(dev_priv))
1196                 return bxt_init_workarounds(engine);
1197
1198         return 0;
1199 }
1200
1201 static int init_render_ring(struct intel_engine_cs *engine)
1202 {
1203         struct drm_i915_private *dev_priv = engine->i915;
1204         int ret = init_ring_common(engine);
1205         if (ret)
1206                 return ret;
1207
1208         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1209         if (IS_GEN(dev_priv, 4, 6))
1210                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1211
1212         /* We need to disable the AsyncFlip performance optimisations in order
1213          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1214          * programmed to '1' on all products.
1215          *
1216          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1217          */
1218         if (IS_GEN(dev_priv, 6, 7))
1219                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1220
1221         /* Required for the hardware to program scanline values for waiting */
1222         /* WaEnableFlushTlbInvalidationMode:snb */
1223         if (IS_GEN6(dev_priv))
1224                 I915_WRITE(GFX_MODE,
1225                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1226
1227         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1228         if (IS_GEN7(dev_priv))
1229                 I915_WRITE(GFX_MODE_GEN7,
1230                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1231                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1232
1233         if (IS_GEN6(dev_priv)) {
1234                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1235                  * "If this bit is set, STCunit will have LRA as replacement
1236                  *  policy. [...] This bit must be reset.  LRA replacement
1237                  *  policy is not supported."
1238                  */
1239                 I915_WRITE(CACHE_MODE_0,
1240                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1241         }
1242
1243         if (IS_GEN(dev_priv, 6, 7))
1244                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1245
1246         if (HAS_L3_DPF(dev_priv))
1247                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1248
1249         return init_workarounds_ring(engine);
1250 }
1251
1252 static void render_ring_cleanup(struct intel_engine_cs *engine)
1253 {
1254         struct drm_i915_private *dev_priv = engine->i915;
1255
1256         if (dev_priv->semaphore_obj) {
1257                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1258                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1259                 dev_priv->semaphore_obj = NULL;
1260         }
1261
1262         intel_fini_pipe_control(engine);
1263 }
1264
1265 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1266                            unsigned int num_dwords)
1267 {
1268 #define MBOX_UPDATE_DWORDS 8
1269         struct intel_engine_cs *signaller = signaller_req->engine;
1270         struct drm_i915_private *dev_priv = signaller_req->i915;
1271         struct intel_engine_cs *waiter;
1272         enum intel_engine_id id;
1273         int ret, num_rings;
1274
1275         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1276         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1277 #undef MBOX_UPDATE_DWORDS
1278
1279         ret = intel_ring_begin(signaller_req, num_dwords);
1280         if (ret)
1281                 return ret;
1282
1283         for_each_engine_id(waiter, dev_priv, id) {
1284                 u32 seqno;
1285                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1286                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1287                         continue;
1288
1289                 seqno = i915_gem_request_get_seqno(signaller_req);
1290                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1291                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1292                                            PIPE_CONTROL_QW_WRITE |
1293                                            PIPE_CONTROL_CS_STALL);
1294                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1295                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1296                 intel_ring_emit(signaller, seqno);
1297                 intel_ring_emit(signaller, 0);
1298                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1299                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1300                 intel_ring_emit(signaller, 0);
1301         }
1302
1303         return 0;
1304 }
1305
1306 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1307                            unsigned int num_dwords)
1308 {
1309 #define MBOX_UPDATE_DWORDS 6
1310         struct intel_engine_cs *signaller = signaller_req->engine;
1311         struct drm_i915_private *dev_priv = signaller_req->i915;
1312         struct intel_engine_cs *waiter;
1313         enum intel_engine_id id;
1314         int ret, num_rings;
1315
1316         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1317         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1318 #undef MBOX_UPDATE_DWORDS
1319
1320         ret = intel_ring_begin(signaller_req, num_dwords);
1321         if (ret)
1322                 return ret;
1323
1324         for_each_engine_id(waiter, dev_priv, id) {
1325                 u32 seqno;
1326                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1327                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1328                         continue;
1329
1330                 seqno = i915_gem_request_get_seqno(signaller_req);
1331                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1332                                            MI_FLUSH_DW_OP_STOREDW);
1333                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1334                                            MI_FLUSH_DW_USE_GTT);
1335                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1336                 intel_ring_emit(signaller, seqno);
1337                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1338                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1339                 intel_ring_emit(signaller, 0);
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1346                        unsigned int num_dwords)
1347 {
1348         struct intel_engine_cs *signaller = signaller_req->engine;
1349         struct drm_i915_private *dev_priv = signaller_req->i915;
1350         struct intel_engine_cs *useless;
1351         enum intel_engine_id id;
1352         int ret, num_rings;
1353
1354 #define MBOX_UPDATE_DWORDS 3
1355         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1356         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1357 #undef MBOX_UPDATE_DWORDS
1358
1359         ret = intel_ring_begin(signaller_req, num_dwords);
1360         if (ret)
1361                 return ret;
1362
1363         for_each_engine_id(useless, dev_priv, id) {
1364                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1365
1366                 if (i915_mmio_reg_valid(mbox_reg)) {
1367                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1368
1369                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1370                         intel_ring_emit_reg(signaller, mbox_reg);
1371                         intel_ring_emit(signaller, seqno);
1372                 }
1373         }
1374
1375         /* If num_dwords was rounded, make sure the tail pointer is correct */
1376         if (num_rings % 2 == 0)
1377                 intel_ring_emit(signaller, MI_NOOP);
1378
1379         return 0;
1380 }
1381
1382 /**
1383  * gen6_add_request - Update the semaphore mailbox registers
1384  *
1385  * @request - request to write to the ring
1386  *
1387  * Update the mailbox registers in the *other* rings with the current seqno.
1388  * This acts like a signal in the canonical semaphore.
1389  */
1390 static int
1391 gen6_add_request(struct drm_i915_gem_request *req)
1392 {
1393         struct intel_engine_cs *engine = req->engine;
1394         int ret;
1395
1396         if (engine->semaphore.signal)
1397                 ret = engine->semaphore.signal(req, 4);
1398         else
1399                 ret = intel_ring_begin(req, 4);
1400
1401         if (ret)
1402                 return ret;
1403
1404         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1405         intel_ring_emit(engine,
1406                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1407         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1408         intel_ring_emit(engine, MI_USER_INTERRUPT);
1409         __intel_ring_advance(engine);
1410
1411         return 0;
1412 }
1413
1414 static int
1415 gen8_render_add_request(struct drm_i915_gem_request *req)
1416 {
1417         struct intel_engine_cs *engine = req->engine;
1418         int ret;
1419
1420         if (engine->semaphore.signal)
1421                 ret = engine->semaphore.signal(req, 8);
1422         else
1423                 ret = intel_ring_begin(req, 8);
1424         if (ret)
1425                 return ret;
1426
1427         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1428         intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1429                                  PIPE_CONTROL_CS_STALL |
1430                                  PIPE_CONTROL_QW_WRITE));
1431         intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1432         intel_ring_emit(engine, 0);
1433         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1434         /* We're thrashing one dword of HWS. */
1435         intel_ring_emit(engine, 0);
1436         intel_ring_emit(engine, MI_USER_INTERRUPT);
1437         intel_ring_emit(engine, MI_NOOP);
1438         __intel_ring_advance(engine);
1439
1440         return 0;
1441 }
1442
1443 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
1444                                               u32 seqno)
1445 {
1446         return dev_priv->last_seqno < seqno;
1447 }
1448
1449 /**
1450  * intel_ring_sync - sync the waiter to the signaller on seqno
1451  *
1452  * @waiter - ring that is waiting
1453  * @signaller - ring which has, or will signal
1454  * @seqno - seqno which the waiter will block on
1455  */
1456
1457 static int
1458 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1459                struct intel_engine_cs *signaller,
1460                u32 seqno)
1461 {
1462         struct intel_engine_cs *waiter = waiter_req->engine;
1463         struct drm_i915_private *dev_priv = waiter_req->i915;
1464         struct i915_hw_ppgtt *ppgtt;
1465         int ret;
1466
1467         ret = intel_ring_begin(waiter_req, 4);
1468         if (ret)
1469                 return ret;
1470
1471         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1472                                 MI_SEMAPHORE_GLOBAL_GTT |
1473                                 MI_SEMAPHORE_SAD_GTE_SDD);
1474         intel_ring_emit(waiter, seqno);
1475         intel_ring_emit(waiter,
1476                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1477         intel_ring_emit(waiter,
1478                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1479         intel_ring_advance(waiter);
1480
1481         /* When the !RCS engines idle waiting upon a semaphore, they lose their
1482          * pagetables and we must reload them before executing the batch.
1483          * We do this on the i915_switch_context() following the wait and
1484          * before the dispatch.
1485          */
1486         ppgtt = waiter_req->ctx->ppgtt;
1487         if (ppgtt && waiter_req->engine->id != RCS)
1488                 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
1489         return 0;
1490 }
1491
1492 static int
1493 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1494                struct intel_engine_cs *signaller,
1495                u32 seqno)
1496 {
1497         struct intel_engine_cs *waiter = waiter_req->engine;
1498         u32 dw1 = MI_SEMAPHORE_MBOX |
1499                   MI_SEMAPHORE_COMPARE |
1500                   MI_SEMAPHORE_REGISTER;
1501         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1502         int ret;
1503
1504         /* Throughout all of the GEM code, seqno passed implies our current
1505          * seqno is >= the last seqno executed. However for hardware the
1506          * comparison is strictly greater than.
1507          */
1508         seqno -= 1;
1509
1510         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1511
1512         ret = intel_ring_begin(waiter_req, 4);
1513         if (ret)
1514                 return ret;
1515
1516         /* If seqno wrap happened, omit the wait with no-ops */
1517         if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
1518                 intel_ring_emit(waiter, dw1 | wait_mbox);
1519                 intel_ring_emit(waiter, seqno);
1520                 intel_ring_emit(waiter, 0);
1521                 intel_ring_emit(waiter, MI_NOOP);
1522         } else {
1523                 intel_ring_emit(waiter, MI_NOOP);
1524                 intel_ring_emit(waiter, MI_NOOP);
1525                 intel_ring_emit(waiter, MI_NOOP);
1526                 intel_ring_emit(waiter, MI_NOOP);
1527         }
1528         intel_ring_advance(waiter);
1529
1530         return 0;
1531 }
1532
1533 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1534 do {                                                                    \
1535         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1536                  PIPE_CONTROL_DEPTH_STALL);                             \
1537         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1538         intel_ring_emit(ring__, 0);                                                     \
1539         intel_ring_emit(ring__, 0);                                                     \
1540 } while (0)
1541
1542 static int
1543 pc_render_add_request(struct drm_i915_gem_request *req)
1544 {
1545         struct intel_engine_cs *engine = req->engine;
1546         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1547         int ret;
1548
1549         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1550          * incoherent with writes to memory, i.e. completely fubar,
1551          * so we need to use PIPE_NOTIFY instead.
1552          *
1553          * However, we also need to workaround the qword write
1554          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1555          * memory before requesting an interrupt.
1556          */
1557         ret = intel_ring_begin(req, 32);
1558         if (ret)
1559                 return ret;
1560
1561         intel_ring_emit(engine,
1562                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1563                         PIPE_CONTROL_WRITE_FLUSH |
1564                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1565         intel_ring_emit(engine,
1566                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1567         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1568         intel_ring_emit(engine, 0);
1569         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1570         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1571         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1572         scratch_addr += 2 * CACHELINE_BYTES;
1573         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1574         scratch_addr += 2 * CACHELINE_BYTES;
1575         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1576         scratch_addr += 2 * CACHELINE_BYTES;
1577         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1578         scratch_addr += 2 * CACHELINE_BYTES;
1579         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1580
1581         intel_ring_emit(engine,
1582                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1583                         PIPE_CONTROL_WRITE_FLUSH |
1584                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1585                         PIPE_CONTROL_NOTIFY);
1586         intel_ring_emit(engine,
1587                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1588         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1589         intel_ring_emit(engine, 0);
1590         __intel_ring_advance(engine);
1591
1592         return 0;
1593 }
1594
1595 static void
1596 gen6_seqno_barrier(struct intel_engine_cs *engine)
1597 {
1598         struct drm_i915_private *dev_priv = engine->i915;
1599
1600         /* Workaround to force correct ordering between irq and seqno writes on
1601          * ivb (and maybe also on snb) by reading from a CS register (like
1602          * ACTHD) before reading the status page.
1603          *
1604          * Note that this effectively stalls the read by the time it takes to
1605          * do a memory transaction, which more or less ensures that the write
1606          * from the GPU has sufficient time to invalidate the CPU cacheline.
1607          * Alternatively we could delay the interrupt from the CS ring to give
1608          * the write time to land, but that would incur a delay after every
1609          * batch i.e. much more frequent than a delay when waiting for the
1610          * interrupt (with the same net latency).
1611          *
1612          * Also note that to prevent whole machine hangs on gen7, we have to
1613          * take the spinlock to guard against concurrent cacheline access.
1614          */
1615         spin_lock_irq(&dev_priv->uncore.lock);
1616         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1617         spin_unlock_irq(&dev_priv->uncore.lock);
1618 }
1619
1620 static u32
1621 ring_get_seqno(struct intel_engine_cs *engine)
1622 {
1623         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1624 }
1625
1626 static void
1627 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1628 {
1629         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1630 }
1631
1632 static u32
1633 pc_render_get_seqno(struct intel_engine_cs *engine)
1634 {
1635         return engine->scratch.cpu_page[0];
1636 }
1637
1638 static void
1639 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1640 {
1641         engine->scratch.cpu_page[0] = seqno;
1642 }
1643
1644 static bool
1645 gen5_ring_get_irq(struct intel_engine_cs *engine)
1646 {
1647         struct drm_i915_private *dev_priv = engine->i915;
1648         unsigned long flags;
1649
1650         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1651                 return false;
1652
1653         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1654         if (engine->irq_refcount++ == 0)
1655                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1656         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1657
1658         return true;
1659 }
1660
1661 static void
1662 gen5_ring_put_irq(struct intel_engine_cs *engine)
1663 {
1664         struct drm_i915_private *dev_priv = engine->i915;
1665         unsigned long flags;
1666
1667         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1668         if (--engine->irq_refcount == 0)
1669                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1670         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1671 }
1672
1673 static bool
1674 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1675 {
1676         struct drm_i915_private *dev_priv = engine->i915;
1677         unsigned long flags;
1678
1679         if (!intel_irqs_enabled(dev_priv))
1680                 return false;
1681
1682         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1683         if (engine->irq_refcount++ == 0) {
1684                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1685                 I915_WRITE(IMR, dev_priv->irq_mask);
1686                 POSTING_READ(IMR);
1687         }
1688         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1689
1690         return true;
1691 }
1692
1693 static void
1694 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1695 {
1696         struct drm_i915_private *dev_priv = engine->i915;
1697         unsigned long flags;
1698
1699         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1700         if (--engine->irq_refcount == 0) {
1701                 dev_priv->irq_mask |= engine->irq_enable_mask;
1702                 I915_WRITE(IMR, dev_priv->irq_mask);
1703                 POSTING_READ(IMR);
1704         }
1705         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1706 }
1707
1708 static bool
1709 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1710 {
1711         struct drm_i915_private *dev_priv = engine->i915;
1712         unsigned long flags;
1713
1714         if (!intel_irqs_enabled(dev_priv))
1715                 return false;
1716
1717         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1718         if (engine->irq_refcount++ == 0) {
1719                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1720                 I915_WRITE16(IMR, dev_priv->irq_mask);
1721                 POSTING_READ16(IMR);
1722         }
1723         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1724
1725         return true;
1726 }
1727
1728 static void
1729 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1730 {
1731         struct drm_i915_private *dev_priv = engine->i915;
1732         unsigned long flags;
1733
1734         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1735         if (--engine->irq_refcount == 0) {
1736                 dev_priv->irq_mask |= engine->irq_enable_mask;
1737                 I915_WRITE16(IMR, dev_priv->irq_mask);
1738                 POSTING_READ16(IMR);
1739         }
1740         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1741 }
1742
1743 static int
1744 bsd_ring_flush(struct drm_i915_gem_request *req,
1745                u32     invalidate_domains,
1746                u32     flush_domains)
1747 {
1748         struct intel_engine_cs *engine = req->engine;
1749         int ret;
1750
1751         ret = intel_ring_begin(req, 2);
1752         if (ret)
1753                 return ret;
1754
1755         intel_ring_emit(engine, MI_FLUSH);
1756         intel_ring_emit(engine, MI_NOOP);
1757         intel_ring_advance(engine);
1758         return 0;
1759 }
1760
1761 static int
1762 i9xx_add_request(struct drm_i915_gem_request *req)
1763 {
1764         struct intel_engine_cs *engine = req->engine;
1765         int ret;
1766
1767         ret = intel_ring_begin(req, 4);
1768         if (ret)
1769                 return ret;
1770
1771         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1772         intel_ring_emit(engine,
1773                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1774         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1775         intel_ring_emit(engine, MI_USER_INTERRUPT);
1776         __intel_ring_advance(engine);
1777
1778         return 0;
1779 }
1780
1781 static bool
1782 gen6_ring_get_irq(struct intel_engine_cs *engine)
1783 {
1784         struct drm_i915_private *dev_priv = engine->i915;
1785         unsigned long flags;
1786
1787         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1788                 return false;
1789
1790         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1791         if (engine->irq_refcount++ == 0) {
1792                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1793                         I915_WRITE_IMR(engine,
1794                                        ~(engine->irq_enable_mask |
1795                                          GT_PARITY_ERROR(dev_priv)));
1796                 else
1797                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1798                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1799         }
1800         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1801
1802         return true;
1803 }
1804
1805 static void
1806 gen6_ring_put_irq(struct intel_engine_cs *engine)
1807 {
1808         struct drm_i915_private *dev_priv = engine->i915;
1809         unsigned long flags;
1810
1811         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1812         if (--engine->irq_refcount == 0) {
1813                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1814                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1815                 else
1816                         I915_WRITE_IMR(engine, ~0);
1817                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1818         }
1819         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1820 }
1821
1822 static bool
1823 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1824 {
1825         struct drm_i915_private *dev_priv = engine->i915;
1826         unsigned long flags;
1827
1828         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1829                 return false;
1830
1831         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1832         if (engine->irq_refcount++ == 0) {
1833                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1834                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1835         }
1836         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1837
1838         return true;
1839 }
1840
1841 static void
1842 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1843 {
1844         struct drm_i915_private *dev_priv = engine->i915;
1845         unsigned long flags;
1846
1847         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1848         if (--engine->irq_refcount == 0) {
1849                 I915_WRITE_IMR(engine, ~0);
1850                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1851         }
1852         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1853 }
1854
1855 static bool
1856 gen8_ring_get_irq(struct intel_engine_cs *engine)
1857 {
1858         struct drm_i915_private *dev_priv = engine->i915;
1859         unsigned long flags;
1860
1861         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1862                 return false;
1863
1864         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1865         if (engine->irq_refcount++ == 0) {
1866                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1867                         I915_WRITE_IMR(engine,
1868                                        ~(engine->irq_enable_mask |
1869                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1870                 } else {
1871                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1872                 }
1873                 POSTING_READ(RING_IMR(engine->mmio_base));
1874         }
1875         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1876
1877         return true;
1878 }
1879
1880 static void
1881 gen8_ring_put_irq(struct intel_engine_cs *engine)
1882 {
1883         struct drm_i915_private *dev_priv = engine->i915;
1884         unsigned long flags;
1885
1886         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1887         if (--engine->irq_refcount == 0) {
1888                 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1889                         I915_WRITE_IMR(engine,
1890                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1891                 } else {
1892                         I915_WRITE_IMR(engine, ~0);
1893                 }
1894                 POSTING_READ(RING_IMR(engine->mmio_base));
1895         }
1896         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1897 }
1898
1899 static int
1900 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1901                          u64 offset, u32 length,
1902                          unsigned dispatch_flags)
1903 {
1904         struct intel_engine_cs *engine = req->engine;
1905         int ret;
1906
1907         ret = intel_ring_begin(req, 2);
1908         if (ret)
1909                 return ret;
1910
1911         intel_ring_emit(engine,
1912                         MI_BATCH_BUFFER_START |
1913                         MI_BATCH_GTT |
1914                         (dispatch_flags & I915_DISPATCH_SECURE ?
1915                          0 : MI_BATCH_NON_SECURE_I965));
1916         intel_ring_emit(engine, offset);
1917         intel_ring_advance(engine);
1918
1919         return 0;
1920 }
1921
1922 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1923 #define I830_BATCH_LIMIT (256*1024)
1924 #define I830_TLB_ENTRIES (2)
1925 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1926 static int
1927 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1928                          u64 offset, u32 len,
1929                          unsigned dispatch_flags)
1930 {
1931         struct intel_engine_cs *engine = req->engine;
1932         u32 cs_offset = engine->scratch.gtt_offset;
1933         int ret;
1934
1935         ret = intel_ring_begin(req, 6);
1936         if (ret)
1937                 return ret;
1938
1939         /* Evict the invalid PTE TLBs */
1940         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1941         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1942         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1943         intel_ring_emit(engine, cs_offset);
1944         intel_ring_emit(engine, 0xdeadbeef);
1945         intel_ring_emit(engine, MI_NOOP);
1946         intel_ring_advance(engine);
1947
1948         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1949                 if (len > I830_BATCH_LIMIT)
1950                         return -ENOSPC;
1951
1952                 ret = intel_ring_begin(req, 6 + 2);
1953                 if (ret)
1954                         return ret;
1955
1956                 /* Blit the batch (which has now all relocs applied) to the
1957                  * stable batch scratch bo area (so that the CS never
1958                  * stumbles over its tlb invalidation bug) ...
1959                  */
1960                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1961                 intel_ring_emit(engine,
1962                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1963                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1964                 intel_ring_emit(engine, cs_offset);
1965                 intel_ring_emit(engine, 4096);
1966                 intel_ring_emit(engine, offset);
1967
1968                 intel_ring_emit(engine, MI_FLUSH);
1969                 intel_ring_emit(engine, MI_NOOP);
1970                 intel_ring_advance(engine);
1971
1972                 /* ... and execute it. */
1973                 offset = cs_offset;
1974         }
1975
1976         ret = intel_ring_begin(req, 2);
1977         if (ret)
1978                 return ret;
1979
1980         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1981         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1982                                           0 : MI_BATCH_NON_SECURE));
1983         intel_ring_advance(engine);
1984
1985         return 0;
1986 }
1987
1988 static int
1989 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1990                          u64 offset, u32 len,
1991                          unsigned dispatch_flags)
1992 {
1993         struct intel_engine_cs *engine = req->engine;
1994         int ret;
1995
1996         ret = intel_ring_begin(req, 2);
1997         if (ret)
1998                 return ret;
1999
2000         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2001         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2002                                           0 : MI_BATCH_NON_SECURE));
2003         intel_ring_advance(engine);
2004
2005         return 0;
2006 }
2007
2008 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2009 {
2010         struct drm_i915_private *dev_priv = engine->i915;
2011
2012         if (!dev_priv->status_page_dmah)
2013                 return;
2014
2015         drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
2016         engine->status_page.page_addr = NULL;
2017 }
2018
2019 static void cleanup_status_page(struct intel_engine_cs *engine)
2020 {
2021         struct drm_i915_gem_object *obj;
2022
2023         obj = engine->status_page.obj;
2024         if (obj == NULL)
2025                 return;
2026
2027         kunmap(sg_page(obj->pages->sgl));
2028         i915_gem_object_ggtt_unpin(obj);
2029         drm_gem_object_unreference(&obj->base);
2030         engine->status_page.obj = NULL;
2031 }
2032
2033 static int init_status_page(struct intel_engine_cs *engine)
2034 {
2035         struct drm_i915_gem_object *obj = engine->status_page.obj;
2036
2037         if (obj == NULL) {
2038                 unsigned flags;
2039                 int ret;
2040
2041                 obj = i915_gem_object_create(engine->i915->dev, 4096);
2042                 if (IS_ERR(obj)) {
2043                         DRM_ERROR("Failed to allocate status page\n");
2044                         return PTR_ERR(obj);
2045                 }
2046
2047                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2048                 if (ret)
2049                         goto err_unref;
2050
2051                 flags = 0;
2052                 if (!HAS_LLC(engine->i915))
2053                         /* On g33, we cannot place HWS above 256MiB, so
2054                          * restrict its pinning to the low mappable arena.
2055                          * Though this restriction is not documented for
2056                          * gen4, gen5, or byt, they also behave similarly
2057                          * and hang if the HWS is placed at the top of the
2058                          * GTT. To generalise, it appears that all !llc
2059                          * platforms have issues with us placing the HWS
2060                          * above the mappable region (even though we never
2061                          * actualy map it).
2062                          */
2063                         flags |= PIN_MAPPABLE;
2064                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2065                 if (ret) {
2066 err_unref:
2067                         drm_gem_object_unreference(&obj->base);
2068                         return ret;
2069                 }
2070
2071                 engine->status_page.obj = obj;
2072         }
2073
2074         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2075         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2076         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2077
2078         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2079                         engine->name, engine->status_page.gfx_addr);
2080
2081         return 0;
2082 }
2083
2084 static int init_phys_status_page(struct intel_engine_cs *engine)
2085 {
2086         struct drm_i915_private *dev_priv = engine->i915;
2087
2088         if (!dev_priv->status_page_dmah) {
2089                 dev_priv->status_page_dmah =
2090                         drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
2091                 if (!dev_priv->status_page_dmah)
2092                         return -ENOMEM;
2093         }
2094
2095         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2096         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2097
2098         return 0;
2099 }
2100
2101 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2102 {
2103         GEM_BUG_ON(ringbuf->vma == NULL);
2104         GEM_BUG_ON(ringbuf->virtual_start == NULL);
2105
2106         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2107                 i915_gem_object_unpin_map(ringbuf->obj);
2108         else
2109                 i915_vma_unpin_iomap(ringbuf->vma);
2110         ringbuf->virtual_start = NULL;
2111
2112         i915_gem_object_ggtt_unpin(ringbuf->obj);
2113         ringbuf->vma = NULL;
2114 }
2115
2116 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
2117                                      struct intel_ringbuffer *ringbuf)
2118 {
2119         struct drm_i915_gem_object *obj = ringbuf->obj;
2120         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2121         unsigned flags = PIN_OFFSET_BIAS | 4096;
2122         void *addr;
2123         int ret;
2124
2125         if (HAS_LLC(dev_priv) && !obj->stolen) {
2126                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2127                 if (ret)
2128                         return ret;
2129
2130                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2131                 if (ret)
2132                         goto err_unpin;
2133
2134                 addr = i915_gem_object_pin_map(obj);
2135                 if (IS_ERR(addr)) {
2136                         ret = PTR_ERR(addr);
2137                         goto err_unpin;
2138                 }
2139         } else {
2140                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2141                                             flags | PIN_MAPPABLE);
2142                 if (ret)
2143                         return ret;
2144
2145                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2146                 if (ret)
2147                         goto err_unpin;
2148
2149                 /* Access through the GTT requires the device to be awake. */
2150                 assert_rpm_wakelock_held(dev_priv);
2151
2152                 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2153                 if (IS_ERR(addr)) {
2154                         ret = PTR_ERR(addr);
2155                         goto err_unpin;
2156                 }
2157         }
2158
2159         ringbuf->virtual_start = addr;
2160         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2161         return 0;
2162
2163 err_unpin:
2164         i915_gem_object_ggtt_unpin(obj);
2165         return ret;
2166 }
2167
2168 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2169 {
2170         drm_gem_object_unreference(&ringbuf->obj->base);
2171         ringbuf->obj = NULL;
2172 }
2173
2174 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2175                                       struct intel_ringbuffer *ringbuf)
2176 {
2177         struct drm_i915_gem_object *obj;
2178
2179         obj = NULL;
2180         if (!HAS_LLC(dev))
2181                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2182         if (obj == NULL)
2183                 obj = i915_gem_object_create(dev, ringbuf->size);
2184         if (IS_ERR(obj))
2185                 return PTR_ERR(obj);
2186
2187         /* mark ring buffers as read-only from GPU side by default */
2188         obj->gt_ro = 1;
2189
2190         ringbuf->obj = obj;
2191
2192         return 0;
2193 }
2194
2195 struct intel_ringbuffer *
2196 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2197 {
2198         struct intel_ringbuffer *ring;
2199         int ret;
2200
2201         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2202         if (ring == NULL) {
2203                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2204                                  engine->name);
2205                 return ERR_PTR(-ENOMEM);
2206         }
2207
2208         ring->engine = engine;
2209         list_add(&ring->link, &engine->buffers);
2210
2211         ring->size = size;
2212         /* Workaround an erratum on the i830 which causes a hang if
2213          * the TAIL pointer points to within the last 2 cachelines
2214          * of the buffer.
2215          */
2216         ring->effective_size = size;
2217         if (IS_I830(engine->i915) || IS_845G(engine->i915))
2218                 ring->effective_size -= 2 * CACHELINE_BYTES;
2219
2220         ring->last_retired_head = -1;
2221         intel_ring_update_space(ring);
2222
2223         ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
2224         if (ret) {
2225                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2226                                  engine->name, ret);
2227                 list_del(&ring->link);
2228                 kfree(ring);
2229                 return ERR_PTR(ret);
2230         }
2231
2232         return ring;
2233 }
2234
2235 void
2236 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2237 {
2238         intel_destroy_ringbuffer_obj(ring);
2239         list_del(&ring->link);
2240         kfree(ring);
2241 }
2242
2243 static int intel_init_ring_buffer(struct drm_device *dev,
2244                                   struct intel_engine_cs *engine)
2245 {
2246         struct drm_i915_private *dev_priv = to_i915(dev);
2247         struct intel_ringbuffer *ringbuf;
2248         int ret;
2249
2250         WARN_ON(engine->buffer);
2251
2252         engine->i915 = dev_priv;
2253         INIT_LIST_HEAD(&engine->active_list);
2254         INIT_LIST_HEAD(&engine->request_list);
2255         INIT_LIST_HEAD(&engine->execlist_queue);
2256         INIT_LIST_HEAD(&engine->buffers);
2257         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2258         memset(engine->semaphore.sync_seqno, 0,
2259                sizeof(engine->semaphore.sync_seqno));
2260
2261         init_waitqueue_head(&engine->irq_queue);
2262
2263         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2264         if (IS_ERR(ringbuf)) {
2265                 ret = PTR_ERR(ringbuf);
2266                 goto error;
2267         }
2268         engine->buffer = ringbuf;
2269
2270         if (I915_NEED_GFX_HWS(dev_priv)) {
2271                 ret = init_status_page(engine);
2272                 if (ret)
2273                         goto error;
2274         } else {
2275                 WARN_ON(engine->id != RCS);
2276                 ret = init_phys_status_page(engine);
2277                 if (ret)
2278                         goto error;
2279         }
2280
2281         ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
2282         if (ret) {
2283                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2284                                 engine->name, ret);
2285                 intel_destroy_ringbuffer_obj(ringbuf);
2286                 goto error;
2287         }
2288
2289         ret = i915_cmd_parser_init_ring(engine);
2290         if (ret)
2291                 goto error;
2292
2293         return 0;
2294
2295 error:
2296         intel_cleanup_engine(engine);
2297         return ret;
2298 }
2299
2300 void intel_cleanup_engine(struct intel_engine_cs *engine)
2301 {
2302         struct drm_i915_private *dev_priv;
2303
2304         if (!intel_engine_initialized(engine))
2305                 return;
2306
2307         dev_priv = engine->i915;
2308
2309         if (engine->buffer) {
2310                 intel_stop_engine(engine);
2311                 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2312
2313                 intel_unpin_ringbuffer_obj(engine->buffer);
2314                 intel_ringbuffer_free(engine->buffer);
2315                 engine->buffer = NULL;
2316         }
2317
2318         if (engine->cleanup)
2319                 engine->cleanup(engine);
2320
2321         if (I915_NEED_GFX_HWS(dev_priv)) {
2322                 cleanup_status_page(engine);
2323         } else {
2324                 WARN_ON(engine->id != RCS);
2325                 cleanup_phys_status_page(engine);
2326         }
2327
2328         i915_cmd_parser_fini_ring(engine);
2329         i915_gem_batch_pool_fini(&engine->batch_pool);
2330         engine->i915 = NULL;
2331 }
2332
2333 int intel_engine_idle(struct intel_engine_cs *engine)
2334 {
2335         struct drm_i915_gem_request *req;
2336
2337         /* Wait upon the last request to be completed */
2338         if (list_empty(&engine->request_list))
2339                 return 0;
2340
2341         req = list_entry(engine->request_list.prev,
2342                          struct drm_i915_gem_request,
2343                          list);
2344
2345         /* Make sure we do not trigger any retires */
2346         return __i915_wait_request(req,
2347                                    req->i915->mm.interruptible,
2348                                    NULL, NULL);
2349 }
2350
2351 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2352 {
2353         int ret;
2354
2355         /* Flush enough space to reduce the likelihood of waiting after
2356          * we start building the request - in which case we will just
2357          * have to repeat work.
2358          */
2359         request->reserved_space += LEGACY_REQUEST_SIZE;
2360
2361         request->ringbuf = request->engine->buffer;
2362
2363         ret = intel_ring_begin(request, 0);
2364         if (ret)
2365                 return ret;
2366
2367         request->reserved_space -= LEGACY_REQUEST_SIZE;
2368         return 0;
2369 }
2370
2371 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2372 {
2373         struct intel_ringbuffer *ringbuf = req->ringbuf;
2374         struct intel_engine_cs *engine = req->engine;
2375         struct drm_i915_gem_request *target;
2376
2377         intel_ring_update_space(ringbuf);
2378         if (ringbuf->space >= bytes)
2379                 return 0;
2380
2381         /*
2382          * Space is reserved in the ringbuffer for finalising the request,
2383          * as that cannot be allowed to fail. During request finalisation,
2384          * reserved_space is set to 0 to stop the overallocation and the
2385          * assumption is that then we never need to wait (which has the
2386          * risk of failing with EINTR).
2387          *
2388          * See also i915_gem_request_alloc() and i915_add_request().
2389          */
2390         GEM_BUG_ON(!req->reserved_space);
2391
2392         list_for_each_entry(target, &engine->request_list, list) {
2393                 unsigned space;
2394
2395                 /*
2396                  * The request queue is per-engine, so can contain requests
2397                  * from multiple ringbuffers. Here, we must ignore any that
2398                  * aren't from the ringbuffer we're considering.
2399                  */
2400                 if (target->ringbuf != ringbuf)
2401                         continue;
2402
2403                 /* Would completion of this request free enough space? */
2404                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2405                                            ringbuf->size);
2406                 if (space >= bytes)
2407                         break;
2408         }
2409
2410         if (WARN_ON(&target->list == &engine->request_list))
2411                 return -ENOSPC;
2412
2413         return i915_wait_request(target);
2414 }
2415
2416 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2417 {
2418         struct intel_ringbuffer *ringbuf = req->ringbuf;
2419         int remain_actual = ringbuf->size - ringbuf->tail;
2420         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2421         int bytes = num_dwords * sizeof(u32);
2422         int total_bytes, wait_bytes;
2423         bool need_wrap = false;
2424
2425         total_bytes = bytes + req->reserved_space;
2426
2427         if (unlikely(bytes > remain_usable)) {
2428                 /*
2429                  * Not enough space for the basic request. So need to flush
2430                  * out the remainder and then wait for base + reserved.
2431                  */
2432                 wait_bytes = remain_actual + total_bytes;
2433                 need_wrap = true;
2434         } else if (unlikely(total_bytes > remain_usable)) {
2435                 /*
2436                  * The base request will fit but the reserved space
2437                  * falls off the end. So we don't need an immediate wrap
2438                  * and only need to effectively wait for the reserved
2439                  * size space from the start of ringbuffer.
2440                  */
2441                 wait_bytes = remain_actual + req->reserved_space;
2442         } else {
2443                 /* No wrapping required, just waiting. */
2444                 wait_bytes = total_bytes;
2445         }
2446
2447         if (wait_bytes > ringbuf->space) {
2448                 int ret = wait_for_space(req, wait_bytes);
2449                 if (unlikely(ret))
2450                         return ret;
2451
2452                 intel_ring_update_space(ringbuf);
2453                 if (unlikely(ringbuf->space < wait_bytes))
2454                         return -EAGAIN;
2455         }
2456
2457         if (unlikely(need_wrap)) {
2458                 GEM_BUG_ON(remain_actual > ringbuf->space);
2459                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2460
2461                 /* Fill the tail with MI_NOOP */
2462                 memset(ringbuf->virtual_start + ringbuf->tail,
2463                        0, remain_actual);
2464                 ringbuf->tail = 0;
2465                 ringbuf->space -= remain_actual;
2466         }
2467
2468         ringbuf->space -= bytes;
2469         GEM_BUG_ON(ringbuf->space < 0);
2470         return 0;
2471 }
2472
2473 /* Align the ring tail to a cacheline boundary */
2474 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2475 {
2476         struct intel_engine_cs *engine = req->engine;
2477         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2478         int ret;
2479
2480         if (num_dwords == 0)
2481                 return 0;
2482
2483         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2484         ret = intel_ring_begin(req, num_dwords);
2485         if (ret)
2486                 return ret;
2487
2488         while (num_dwords--)
2489                 intel_ring_emit(engine, MI_NOOP);
2490
2491         intel_ring_advance(engine);
2492
2493         return 0;
2494 }
2495
2496 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2497 {
2498         struct drm_i915_private *dev_priv = engine->i915;
2499
2500         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2501          * so long as the semaphore value in the register/page is greater
2502          * than the sync value), so whenever we reset the seqno,
2503          * so long as we reset the tracking semaphore value to 0, it will
2504          * always be before the next request's seqno. If we don't reset
2505          * the semaphore value, then when the seqno moves backwards all
2506          * future waits will complete instantly (causing rendering corruption).
2507          */
2508         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
2509                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2510                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2511                 if (HAS_VEBOX(dev_priv))
2512                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2513         }
2514         if (dev_priv->semaphore_obj) {
2515                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2516                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2517                 void *semaphores = kmap(page);
2518                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2519                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2520                 kunmap(page);
2521         }
2522         memset(engine->semaphore.sync_seqno, 0,
2523                sizeof(engine->semaphore.sync_seqno));
2524
2525         engine->set_seqno(engine, seqno);
2526         engine->last_submitted_seqno = seqno;
2527
2528         engine->hangcheck.seqno = seqno;
2529 }
2530
2531 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2532                                      u32 value)
2533 {
2534         struct drm_i915_private *dev_priv = engine->i915;
2535
2536        /* Every tail move must follow the sequence below */
2537
2538         /* Disable notification that the ring is IDLE. The GT
2539          * will then assume that it is busy and bring it out of rc6.
2540          */
2541         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2542                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2543
2544         /* Clear the context id. Here be magic! */
2545         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2546
2547         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2548         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2549                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2550                      50))
2551                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2552
2553         /* Now that the ring is fully powered up, update the tail */
2554         I915_WRITE_TAIL(engine, value);
2555         POSTING_READ(RING_TAIL(engine->mmio_base));
2556
2557         /* Let the ring send IDLE messages to the GT again,
2558          * and so let it sleep to conserve power when idle.
2559          */
2560         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2561                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2562 }
2563
2564 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2565                                u32 invalidate, u32 flush)
2566 {
2567         struct intel_engine_cs *engine = req->engine;
2568         uint32_t cmd;
2569         int ret;
2570
2571         ret = intel_ring_begin(req, 4);
2572         if (ret)
2573                 return ret;
2574
2575         cmd = MI_FLUSH_DW;
2576         if (INTEL_GEN(req->i915) >= 8)
2577                 cmd += 1;
2578
2579         /* We always require a command barrier so that subsequent
2580          * commands, such as breadcrumb interrupts, are strictly ordered
2581          * wrt the contents of the write cache being flushed to memory
2582          * (and thus being coherent from the CPU).
2583          */
2584         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2585
2586         /*
2587          * Bspec vol 1c.5 - video engine command streamer:
2588          * "If ENABLED, all TLBs will be invalidated once the flush
2589          * operation is complete. This bit is only valid when the
2590          * Post-Sync Operation field is a value of 1h or 3h."
2591          */
2592         if (invalidate & I915_GEM_GPU_DOMAINS)
2593                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2594
2595         intel_ring_emit(engine, cmd);
2596         intel_ring_emit(engine,
2597                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2598         if (INTEL_GEN(req->i915) >= 8) {
2599                 intel_ring_emit(engine, 0); /* upper addr */
2600                 intel_ring_emit(engine, 0); /* value */
2601         } else  {
2602                 intel_ring_emit(engine, 0);
2603                 intel_ring_emit(engine, MI_NOOP);
2604         }
2605         intel_ring_advance(engine);
2606         return 0;
2607 }
2608
2609 static int
2610 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2611                               u64 offset, u32 len,
2612                               unsigned dispatch_flags)
2613 {
2614         struct intel_engine_cs *engine = req->engine;
2615         bool ppgtt = USES_PPGTT(engine->dev) &&
2616                         !(dispatch_flags & I915_DISPATCH_SECURE);
2617         int ret;
2618
2619         ret = intel_ring_begin(req, 4);
2620         if (ret)
2621                 return ret;
2622
2623         /* FIXME(BDW): Address space and security selectors. */
2624         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2625                         (dispatch_flags & I915_DISPATCH_RS ?
2626                          MI_BATCH_RESOURCE_STREAMER : 0));
2627         intel_ring_emit(engine, lower_32_bits(offset));
2628         intel_ring_emit(engine, upper_32_bits(offset));
2629         intel_ring_emit(engine, MI_NOOP);
2630         intel_ring_advance(engine);
2631
2632         return 0;
2633 }
2634
2635 static int
2636 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2637                              u64 offset, u32 len,
2638                              unsigned dispatch_flags)
2639 {
2640         struct intel_engine_cs *engine = req->engine;
2641         int ret;
2642
2643         ret = intel_ring_begin(req, 2);
2644         if (ret)
2645                 return ret;
2646
2647         intel_ring_emit(engine,
2648                         MI_BATCH_BUFFER_START |
2649                         (dispatch_flags & I915_DISPATCH_SECURE ?
2650                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2651                         (dispatch_flags & I915_DISPATCH_RS ?
2652                          MI_BATCH_RESOURCE_STREAMER : 0));
2653         /* bit0-7 is the length on GEN6+ */
2654         intel_ring_emit(engine, offset);
2655         intel_ring_advance(engine);
2656
2657         return 0;
2658 }
2659
2660 static int
2661 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2662                               u64 offset, u32 len,
2663                               unsigned dispatch_flags)
2664 {
2665         struct intel_engine_cs *engine = req->engine;
2666         int ret;
2667
2668         ret = intel_ring_begin(req, 2);
2669         if (ret)
2670                 return ret;
2671
2672         intel_ring_emit(engine,
2673                         MI_BATCH_BUFFER_START |
2674                         (dispatch_flags & I915_DISPATCH_SECURE ?
2675                          0 : MI_BATCH_NON_SECURE_I965));
2676         /* bit0-7 is the length on GEN6+ */
2677         intel_ring_emit(engine, offset);
2678         intel_ring_advance(engine);
2679
2680         return 0;
2681 }
2682
2683 /* Blitter support (SandyBridge+) */
2684
2685 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2686                            u32 invalidate, u32 flush)
2687 {
2688         struct intel_engine_cs *engine = req->engine;
2689         uint32_t cmd;
2690         int ret;
2691
2692         ret = intel_ring_begin(req, 4);
2693         if (ret)
2694                 return ret;
2695
2696         cmd = MI_FLUSH_DW;
2697         if (INTEL_GEN(req->i915) >= 8)
2698                 cmd += 1;
2699
2700         /* We always require a command barrier so that subsequent
2701          * commands, such as breadcrumb interrupts, are strictly ordered
2702          * wrt the contents of the write cache being flushed to memory
2703          * (and thus being coherent from the CPU).
2704          */
2705         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2706
2707         /*
2708          * Bspec vol 1c.3 - blitter engine command streamer:
2709          * "If ENABLED, all TLBs will be invalidated once the flush
2710          * operation is complete. This bit is only valid when the
2711          * Post-Sync Operation field is a value of 1h or 3h."
2712          */
2713         if (invalidate & I915_GEM_DOMAIN_RENDER)
2714                 cmd |= MI_INVALIDATE_TLB;
2715         intel_ring_emit(engine, cmd);
2716         intel_ring_emit(engine,
2717                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2718         if (INTEL_GEN(req->i915) >= 8) {
2719                 intel_ring_emit(engine, 0); /* upper addr */
2720                 intel_ring_emit(engine, 0); /* value */
2721         } else  {
2722                 intel_ring_emit(engine, 0);
2723                 intel_ring_emit(engine, MI_NOOP);
2724         }
2725         intel_ring_advance(engine);
2726
2727         return 0;
2728 }
2729
2730 int intel_init_render_ring_buffer(struct drm_device *dev)
2731 {
2732         struct drm_i915_private *dev_priv = dev->dev_private;
2733         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2734         struct drm_i915_gem_object *obj;
2735         int ret;
2736
2737         engine->name = "render ring";
2738         engine->id = RCS;
2739         engine->exec_id = I915_EXEC_RENDER;
2740         engine->hw_id = 0;
2741         engine->mmio_base = RENDER_RING_BASE;
2742
2743         if (INTEL_GEN(dev_priv) >= 8) {
2744                 if (i915_semaphore_is_enabled(dev_priv)) {
2745                         obj = i915_gem_object_create(dev, 4096);
2746                         if (IS_ERR(obj)) {
2747                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2748                                 i915.semaphores = 0;
2749                         } else {
2750                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2751                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2752                                 if (ret != 0) {
2753                                         drm_gem_object_unreference(&obj->base);
2754                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2755                                         i915.semaphores = 0;
2756                                 } else
2757                                         dev_priv->semaphore_obj = obj;
2758                         }
2759                 }
2760
2761                 engine->init_context = intel_rcs_ctx_init;
2762                 engine->add_request = gen8_render_add_request;
2763                 engine->flush = gen8_render_ring_flush;
2764                 engine->irq_get = gen8_ring_get_irq;
2765                 engine->irq_put = gen8_ring_put_irq;
2766                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2767                 engine->get_seqno = ring_get_seqno;
2768                 engine->set_seqno = ring_set_seqno;
2769                 if (i915_semaphore_is_enabled(dev_priv)) {
2770                         WARN_ON(!dev_priv->semaphore_obj);
2771                         engine->semaphore.sync_to = gen8_ring_sync;
2772                         engine->semaphore.signal = gen8_rcs_signal;
2773                         GEN8_RING_SEMAPHORE_INIT(engine);
2774                 }
2775         } else if (INTEL_GEN(dev_priv) >= 6) {
2776                 engine->init_context = intel_rcs_ctx_init;
2777                 engine->add_request = gen6_add_request;
2778                 engine->flush = gen7_render_ring_flush;
2779                 if (IS_GEN6(dev_priv))
2780                         engine->flush = gen6_render_ring_flush;
2781                 engine->irq_get = gen6_ring_get_irq;
2782                 engine->irq_put = gen6_ring_put_irq;
2783                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2784                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2785                 engine->get_seqno = ring_get_seqno;
2786                 engine->set_seqno = ring_set_seqno;
2787                 if (i915_semaphore_is_enabled(dev_priv)) {
2788                         engine->semaphore.sync_to = gen6_ring_sync;
2789                         engine->semaphore.signal = gen6_signal;
2790                         /*
2791                          * The current semaphore is only applied on pre-gen8
2792                          * platform.  And there is no VCS2 ring on the pre-gen8
2793                          * platform. So the semaphore between RCS and VCS2 is
2794                          * initialized as INVALID.  Gen8 will initialize the
2795                          * sema between VCS2 and RCS later.
2796                          */
2797                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2798                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2799                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2800                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2801                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2802                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2803                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2804                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2805                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2806                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2807                 }
2808         } else if (IS_GEN5(dev_priv)) {
2809                 engine->add_request = pc_render_add_request;
2810                 engine->flush = gen4_render_ring_flush;
2811                 engine->get_seqno = pc_render_get_seqno;
2812                 engine->set_seqno = pc_render_set_seqno;
2813                 engine->irq_get = gen5_ring_get_irq;
2814                 engine->irq_put = gen5_ring_put_irq;
2815                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2816                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2817         } else {
2818                 engine->add_request = i9xx_add_request;
2819                 if (INTEL_GEN(dev_priv) < 4)
2820                         engine->flush = gen2_render_ring_flush;
2821                 else
2822                         engine->flush = gen4_render_ring_flush;
2823                 engine->get_seqno = ring_get_seqno;
2824                 engine->set_seqno = ring_set_seqno;
2825                 if (IS_GEN2(dev_priv)) {
2826                         engine->irq_get = i8xx_ring_get_irq;
2827                         engine->irq_put = i8xx_ring_put_irq;
2828                 } else {
2829                         engine->irq_get = i9xx_ring_get_irq;
2830                         engine->irq_put = i9xx_ring_put_irq;
2831                 }
2832                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2833         }
2834         engine->write_tail = ring_write_tail;
2835
2836         if (IS_HASWELL(dev_priv))
2837                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2838         else if (IS_GEN8(dev_priv))
2839                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2840         else if (INTEL_GEN(dev_priv) >= 6)
2841                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2842         else if (INTEL_GEN(dev_priv) >= 4)
2843                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2844         else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2845                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2846         else
2847                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2848         engine->init_hw = init_render_ring;
2849         engine->cleanup = render_ring_cleanup;
2850
2851         /* Workaround batchbuffer to combat CS tlb bug. */
2852         if (HAS_BROKEN_CS_TLB(dev_priv)) {
2853                 obj = i915_gem_object_create(dev, I830_WA_SIZE);
2854                 if (IS_ERR(obj)) {
2855                         DRM_ERROR("Failed to allocate batch bo\n");
2856                         return PTR_ERR(obj);
2857                 }
2858
2859                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2860                 if (ret != 0) {
2861                         drm_gem_object_unreference(&obj->base);
2862                         DRM_ERROR("Failed to ping batch bo\n");
2863                         return ret;
2864                 }
2865
2866                 engine->scratch.obj = obj;
2867                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2868         }
2869
2870         ret = intel_init_ring_buffer(dev, engine);
2871         if (ret)
2872                 return ret;
2873
2874         if (INTEL_GEN(dev_priv) >= 5) {
2875                 ret = intel_init_pipe_control(engine);
2876                 if (ret)
2877                         return ret;
2878         }
2879
2880         return 0;
2881 }
2882
2883 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2884 {
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2887
2888         engine->name = "bsd ring";
2889         engine->id = VCS;
2890         engine->exec_id = I915_EXEC_BSD;
2891         engine->hw_id = 1;
2892
2893         engine->write_tail = ring_write_tail;
2894         if (INTEL_GEN(dev_priv) >= 6) {
2895                 engine->mmio_base = GEN6_BSD_RING_BASE;
2896                 /* gen6 bsd needs a special wa for tail updates */
2897                 if (IS_GEN6(dev_priv))
2898                         engine->write_tail = gen6_bsd_ring_write_tail;
2899                 engine->flush = gen6_bsd_ring_flush;
2900                 engine->add_request = gen6_add_request;
2901                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2902                 engine->get_seqno = ring_get_seqno;
2903                 engine->set_seqno = ring_set_seqno;
2904                 if (INTEL_GEN(dev_priv) >= 8) {
2905                         engine->irq_enable_mask =
2906                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2907                         engine->irq_get = gen8_ring_get_irq;
2908                         engine->irq_put = gen8_ring_put_irq;
2909                         engine->dispatch_execbuffer =
2910                                 gen8_ring_dispatch_execbuffer;
2911                         if (i915_semaphore_is_enabled(dev_priv)) {
2912                                 engine->semaphore.sync_to = gen8_ring_sync;
2913                                 engine->semaphore.signal = gen8_xcs_signal;
2914                                 GEN8_RING_SEMAPHORE_INIT(engine);
2915                         }
2916                 } else {
2917                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2918                         engine->irq_get = gen6_ring_get_irq;
2919                         engine->irq_put = gen6_ring_put_irq;
2920                         engine->dispatch_execbuffer =
2921                                 gen6_ring_dispatch_execbuffer;
2922                         if (i915_semaphore_is_enabled(dev_priv)) {
2923                                 engine->semaphore.sync_to = gen6_ring_sync;
2924                                 engine->semaphore.signal = gen6_signal;
2925                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2926                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2927                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2928                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2929                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2930                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2931                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2932                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2933                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2934                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2935                         }
2936                 }
2937         } else {
2938                 engine->mmio_base = BSD_RING_BASE;
2939                 engine->flush = bsd_ring_flush;
2940                 engine->add_request = i9xx_add_request;
2941                 engine->get_seqno = ring_get_seqno;
2942                 engine->set_seqno = ring_set_seqno;
2943                 if (IS_GEN5(dev_priv)) {
2944                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2945                         engine->irq_get = gen5_ring_get_irq;
2946                         engine->irq_put = gen5_ring_put_irq;
2947                 } else {
2948                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2949                         engine->irq_get = i9xx_ring_get_irq;
2950                         engine->irq_put = i9xx_ring_put_irq;
2951                 }
2952                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2953         }
2954         engine->init_hw = init_ring_common;
2955
2956         return intel_init_ring_buffer(dev, engine);
2957 }
2958
2959 /**
2960  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2961  */
2962 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2963 {
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2966
2967         engine->name = "bsd2 ring";
2968         engine->id = VCS2;
2969         engine->exec_id = I915_EXEC_BSD;
2970         engine->hw_id = 4;
2971
2972         engine->write_tail = ring_write_tail;
2973         engine->mmio_base = GEN8_BSD2_RING_BASE;
2974         engine->flush = gen6_bsd_ring_flush;
2975         engine->add_request = gen6_add_request;
2976         engine->irq_seqno_barrier = gen6_seqno_barrier;
2977         engine->get_seqno = ring_get_seqno;
2978         engine->set_seqno = ring_set_seqno;
2979         engine->irq_enable_mask =
2980                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2981         engine->irq_get = gen8_ring_get_irq;
2982         engine->irq_put = gen8_ring_put_irq;
2983         engine->dispatch_execbuffer =
2984                         gen8_ring_dispatch_execbuffer;
2985         if (i915_semaphore_is_enabled(dev_priv)) {
2986                 engine->semaphore.sync_to = gen8_ring_sync;
2987                 engine->semaphore.signal = gen8_xcs_signal;
2988                 GEN8_RING_SEMAPHORE_INIT(engine);
2989         }
2990         engine->init_hw = init_ring_common;
2991
2992         return intel_init_ring_buffer(dev, engine);
2993 }
2994
2995 int intel_init_blt_ring_buffer(struct drm_device *dev)
2996 {
2997         struct drm_i915_private *dev_priv = dev->dev_private;
2998         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2999
3000         engine->name = "blitter ring";
3001         engine->id = BCS;
3002         engine->exec_id = I915_EXEC_BLT;
3003         engine->hw_id = 2;
3004
3005         engine->mmio_base = BLT_RING_BASE;
3006         engine->write_tail = ring_write_tail;
3007         engine->flush = gen6_ring_flush;
3008         engine->add_request = gen6_add_request;
3009         engine->irq_seqno_barrier = gen6_seqno_barrier;
3010         engine->get_seqno = ring_get_seqno;
3011         engine->set_seqno = ring_set_seqno;
3012         if (INTEL_GEN(dev_priv) >= 8) {
3013                 engine->irq_enable_mask =
3014                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3015                 engine->irq_get = gen8_ring_get_irq;
3016                 engine->irq_put = gen8_ring_put_irq;
3017                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3018                 if (i915_semaphore_is_enabled(dev_priv)) {
3019                         engine->semaphore.sync_to = gen8_ring_sync;
3020                         engine->semaphore.signal = gen8_xcs_signal;
3021                         GEN8_RING_SEMAPHORE_INIT(engine);
3022                 }
3023         } else {
3024                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3025                 engine->irq_get = gen6_ring_get_irq;
3026                 engine->irq_put = gen6_ring_put_irq;
3027                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3028                 if (i915_semaphore_is_enabled(dev_priv)) {
3029                         engine->semaphore.signal = gen6_signal;
3030                         engine->semaphore.sync_to = gen6_ring_sync;
3031                         /*
3032                          * The current semaphore is only applied on pre-gen8
3033                          * platform.  And there is no VCS2 ring on the pre-gen8
3034                          * platform. So the semaphore between BCS and VCS2 is
3035                          * initialized as INVALID.  Gen8 will initialize the
3036                          * sema between BCS and VCS2 later.
3037                          */
3038                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3039                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3040                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3041                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3042                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3043                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3044                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3045                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3046                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3047                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3048                 }
3049         }
3050         engine->init_hw = init_ring_common;
3051
3052         return intel_init_ring_buffer(dev, engine);
3053 }
3054
3055 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3056 {
3057         struct drm_i915_private *dev_priv = dev->dev_private;
3058         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3059
3060         engine->name = "video enhancement ring";
3061         engine->id = VECS;
3062         engine->exec_id = I915_EXEC_VEBOX;
3063         engine->hw_id = 3;
3064
3065         engine->mmio_base = VEBOX_RING_BASE;
3066         engine->write_tail = ring_write_tail;
3067         engine->flush = gen6_ring_flush;
3068         engine->add_request = gen6_add_request;
3069         engine->irq_seqno_barrier = gen6_seqno_barrier;
3070         engine->get_seqno = ring_get_seqno;
3071         engine->set_seqno = ring_set_seqno;
3072
3073         if (INTEL_GEN(dev_priv) >= 8) {
3074                 engine->irq_enable_mask =
3075                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3076                 engine->irq_get = gen8_ring_get_irq;
3077                 engine->irq_put = gen8_ring_put_irq;
3078                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3079                 if (i915_semaphore_is_enabled(dev_priv)) {
3080                         engine->semaphore.sync_to = gen8_ring_sync;
3081                         engine->semaphore.signal = gen8_xcs_signal;
3082                         GEN8_RING_SEMAPHORE_INIT(engine);
3083                 }
3084         } else {
3085                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3086                 engine->irq_get = hsw_vebox_get_irq;
3087                 engine->irq_put = hsw_vebox_put_irq;
3088                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3089                 if (i915_semaphore_is_enabled(dev_priv)) {
3090                         engine->semaphore.sync_to = gen6_ring_sync;
3091                         engine->semaphore.signal = gen6_signal;
3092                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3093                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3094                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3095                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3096                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3097                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3098                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3099                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3100                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3101                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3102                 }
3103         }
3104         engine->init_hw = init_ring_common;
3105
3106         return intel_init_ring_buffer(dev, engine);
3107 }
3108
3109 int
3110 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3111 {
3112         struct intel_engine_cs *engine = req->engine;
3113         int ret;
3114
3115         if (!engine->gpu_caches_dirty)
3116                 return 0;
3117
3118         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3119         if (ret)
3120                 return ret;
3121
3122         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3123
3124         engine->gpu_caches_dirty = false;
3125         return 0;
3126 }
3127
3128 int
3129 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3130 {
3131         struct intel_engine_cs *engine = req->engine;
3132         uint32_t flush_domains;
3133         int ret;
3134
3135         flush_domains = 0;
3136         if (engine->gpu_caches_dirty)
3137                 flush_domains = I915_GEM_GPU_DOMAINS;
3138
3139         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3140         if (ret)
3141                 return ret;
3142
3143         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3144
3145         engine->gpu_caches_dirty = false;
3146         return 0;
3147 }
3148
3149 void
3150 intel_stop_engine(struct intel_engine_cs *engine)
3151 {
3152         int ret;
3153
3154         if (!intel_engine_initialized(engine))
3155                 return;
3156
3157         ret = intel_engine_idle(engine);
3158         if (ret)
3159                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3160                           engine->name, ret);
3161
3162         stop_ring(engine);
3163 }