drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  57 {
  58         intel_ring_update_space(ringbuf);
  59         return ringbuf->space;
  60 }
  61
  62 bool intel_engine_stopped(struct intel_engine_cs *engine)
  63 {
  64         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  65         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  66 }
  67
  68 static void __intel_ring_advance(struct intel_engine_cs *engine)
  69 {
  70         struct intel_ringbuffer *ringbuf = engine->buffer;
  71         ringbuf->tail &= ringbuf->size - 1;
  72         if (intel_engine_stopped(engine))
  73                 return;
  74         engine->write_tail(engine, ringbuf->tail);
  75 }
  76
  77 static int
  78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  79                        u32      invalidate_domains,
  80                        u32      flush_domains)
  81 {
  82         struct intel_engine_cs *engine = req->engine;
  83         u32 cmd;
  84         int ret;
  85
  86         cmd = MI_FLUSH;
  87         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  88                 cmd |= MI_NO_WRITE_FLUSH;
  89
  90         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  91                 cmd |= MI_READ_FLUSH;
  92
  93         ret = intel_ring_begin(req, 2);
  94         if (ret)
  95                 return ret;
  96
  97         intel_ring_emit(engine, cmd);
  98         intel_ring_emit(engine, MI_NOOP);
  99         intel_ring_advance(engine);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 106                        u32      invalidate_domains,
 107                        u32      flush_domains)
 108 {
 109         struct intel_engine_cs *engine = req->engine;
 110         struct drm_device *dev = engine->dev;
 111         u32 cmd;
 112         int ret;
 113
 114         /*
 115          * read/write caches:
 116          *
 117          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 118          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 119          * also flushed at 2d versus 3d pipeline switches.
 120          *
 121          * read-only caches:
 122          *
 123          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 124          * MI_READ_FLUSH is set, and is always flushed on 965.
 125          *
 126          * I915_GEM_DOMAIN_COMMAND may not exist?
 127          *
 128          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 129          * invalidated when MI_EXE_FLUSH is set.
 130          *
 131          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 132          * invalidated with every MI_FLUSH.
 133          *
 134          * TLBs:
 135          *
 136          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 137          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 138          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 139          * are flushed at any MI_FLUSH.
 140          */
 141
 142         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 143         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 144                 cmd &= ~MI_NO_WRITE_FLUSH;
 145         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 146                 cmd |= MI_EXE_FLUSH;
 147
 148         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 149             (IS_G4X(dev) || IS_GEN5(dev)))
 150                 cmd |= MI_INVALIDATE_ISP;
 151
 152         ret = intel_ring_begin(req, 2);
 153         if (ret)
 154                 return ret;
 155
 156         intel_ring_emit(engine, cmd);
 157         intel_ring_emit(engine, MI_NOOP);
 158         intel_ring_advance(engine);
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 165  * implementing two workarounds on gen6.  From section 1.4.7.1
 166  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 167  *
 168  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 169  * produced by non-pipelined state commands), software needs to first
 170  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 171  * 0.
 172  *
 173  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 174  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 175  *
 176  * And the workaround for these two requires this workaround first:
 177  *
 178  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 179  * BEFORE the pipe-control with a post-sync op and no write-cache
 180  * flushes.
 181  *
 182  * And this last workaround is tricky because of the requirements on
 183  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 184  * volume 2 part 1:
 185  *
 186  *     "1 of the following must also be set:
 187  *      - Render Target Cache Flush Enable ([12] of DW1)
 188  *      - Depth Cache Flush Enable ([0] of DW1)
 189  *      - Stall at Pixel Scoreboard ([1] of DW1)
 190  *      - Depth Stall ([13] of DW1)
 191  *      - Post-Sync Operation ([13] of DW1)
 192  *      - Notify Enable ([8] of DW1)"
 193  *
 194  * The cache flushes require the workaround flush that triggered this
 195  * one, so we can't use it.  Depth stall would trigger the same.
 196  * Post-sync nonzero is what triggered this second workaround, so we
 197  * can't use that one either.  Notify enable is IRQs, which aren't
 198  * really our business.  That leaves only stall at scoreboard.
 199  */
 200 static int
 201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 202 {
 203         struct intel_engine_cs *engine = req->engine;
 204         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 205         int ret;
 206
 207         ret = intel_ring_begin(req, 6);
 208         if (ret)
 209                 return ret;
 210
 211         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 212         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 213                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 214         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 215         intel_ring_emit(engine, 0); /* low dword */
 216         intel_ring_emit(engine, 0); /* high dword */
 217         intel_ring_emit(engine, MI_NOOP);
 218         intel_ring_advance(engine);
 219
 220         ret = intel_ring_begin(req, 6);
 221         if (ret)
 222                 return ret;
 223
 224         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 225         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 226         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 227         intel_ring_emit(engine, 0);
 228         intel_ring_emit(engine, 0);
 229         intel_ring_emit(engine, MI_NOOP);
 230         intel_ring_advance(engine);
 231
 232         return 0;
 233 }
 234
 235 static int
 236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 237                        u32 invalidate_domains, u32 flush_domains)
 238 {
 239         struct intel_engine_cs *engine = req->engine;
 240         u32 flags = 0;
 241         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 242         int ret;
 243
 244         /* Force SNB workarounds for PIPE_CONTROL flushes */
 245         ret = intel_emit_post_sync_nonzero_flush(req);
 246         if (ret)
 247                 return ret;
 248
 249         /* Just flush everything.  Experiments have shown that reducing the
 250          * number of bits based on the write domains has little performance
 251          * impact.
 252          */
 253         if (flush_domains) {
 254                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 255                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 256                 /*
 257                  * Ensure that any following seqno writes only happen
 258                  * when the render cache is indeed flushed.
 259                  */
 260                 flags |= PIPE_CONTROL_CS_STALL;
 261         }
 262         if (invalidate_domains) {
 263                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 264                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 265                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 266                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 267                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 268                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 269                 /*
 270                  * TLB invalidate requires a post-sync write.
 271                  */
 272                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 273         }
 274
 275         ret = intel_ring_begin(req, 4);
 276         if (ret)
 277                 return ret;
 278
 279         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 280         intel_ring_emit(engine, flags);
 281         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 282         intel_ring_emit(engine, 0);
 283         intel_ring_advance(engine);
 284
 285         return 0;
 286 }
 287
 288 static int
 289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 290 {
 291         struct intel_engine_cs *engine = req->engine;
 292         int ret;
 293
 294         ret = intel_ring_begin(req, 4);
 295         if (ret)
 296                 return ret;
 297
 298         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 299         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 300                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 301         intel_ring_emit(engine, 0);
 302         intel_ring_emit(engine, 0);
 303         intel_ring_advance(engine);
 304
 305         return 0;
 306 }
 307
 308 static int
 309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 310                        u32 invalidate_domains, u32 flush_domains)
 311 {
 312         struct intel_engine_cs *engine = req->engine;
 313         u32 flags = 0;
 314         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 315         int ret;
 316
 317         /*
 318          * Ensure that any following seqno writes only happen when the render
 319          * cache is indeed flushed.
 320          *
 321          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 322          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 323          * don't try to be clever and just set it unconditionally.
 324          */
 325         flags |= PIPE_CONTROL_CS_STALL;
 326
 327         /* Just flush everything.  Experiments have shown that reducing the
 328          * number of bits based on the write domains has little performance
 329          * impact.
 330          */
 331         if (flush_domains) {
 332                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 333                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 334                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 335                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 336         }
 337         if (invalidate_domains) {
 338                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 339                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 340                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 341                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 342                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 343                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 344                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 345                 /*
 346                  * TLB invalidate requires a post-sync write.
 347                  */
 348                 flags |= PIPE_CONTROL_QW_WRITE;
 349                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 350
 351                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 352
 353                 /* Workaround: we must issue a pipe_control with CS-stall bit
 354                  * set before a pipe_control command that has the state cache
 355                  * invalidate bit set. */
 356                 gen7_render_ring_cs_stall_wa(req);
 357         }
 358
 359         ret = intel_ring_begin(req, 4);
 360         if (ret)
 361                 return ret;
 362
 363         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 364         intel_ring_emit(engine, flags);
 365         intel_ring_emit(engine, scratch_addr);
 366         intel_ring_emit(engine, 0);
 367         intel_ring_advance(engine);
 368
 369         return 0;
 370 }
 371
 372 static int
 373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 374                        u32 flags, u32 scratch_addr)
 375 {
 376         struct intel_engine_cs *engine = req->engine;
 377         int ret;
 378
 379         ret = intel_ring_begin(req, 6);
 380         if (ret)
 381                 return ret;
 382
 383         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 384         intel_ring_emit(engine, flags);
 385         intel_ring_emit(engine, scratch_addr);
 386         intel_ring_emit(engine, 0);
 387         intel_ring_emit(engine, 0);
 388         intel_ring_emit(engine, 0);
 389         intel_ring_advance(engine);
 390
 391         return 0;
 392 }
 393
 394 static int
 395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 396                        u32 invalidate_domains, u32 flush_domains)
 397 {
 398         u32 flags = 0;
 399         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 400         int ret;
 401
 402         flags |= PIPE_CONTROL_CS_STALL;
 403
 404         if (flush_domains) {
 405                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 406                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 407                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 408                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 409         }
 410         if (invalidate_domains) {
 411                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 412                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 413                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 414                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 415                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 416                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 417                 flags |= PIPE_CONTROL_QW_WRITE;
 418                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 419
 420                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 421                 ret = gen8_emit_pipe_control(req,
 422                                              PIPE_CONTROL_CS_STALL |
 423                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 424                                              0);
 425                 if (ret)
 426                         return ret;
 427         }
 428
 429         return gen8_emit_pipe_control(req, flags, scratch_addr);
 430 }
 431
 432 static void ring_write_tail(struct intel_engine_cs *engine,
 433                             u32 value)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         I915_WRITE_TAIL(engine, value);
 437 }
 438
 439 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 440 {
 441         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 442         u64 acthd;
 443
 444         if (INTEL_INFO(engine->dev)->gen >= 8)
 445                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 446                                          RING_ACTHD_UDW(engine->mmio_base));
 447         else if (INTEL_INFO(engine->dev)->gen >= 4)
 448                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 449         else
 450                 acthd = I915_READ(ACTHD);
 451
 452         return acthd;
 453 }
 454
 455 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 456 {
 457         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 458         u32 addr;
 459
 460         addr = dev_priv->status_page_dmah->busaddr;
 461         if (INTEL_INFO(engine->dev)->gen >= 4)
 462                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 463         I915_WRITE(HWS_PGA, addr);
 464 }
 465
 466 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 467 {
 468         struct drm_device *dev = engine->dev;
 469         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 470         i915_reg_t mmio;
 471
 472         /* The ring status page addresses are no longer next to the rest of
 473          * the ring registers as of gen7.
 474          */
 475         if (IS_GEN7(dev)) {
 476                 switch (engine->id) {
 477                 case RCS:
 478                         mmio = RENDER_HWS_PGA_GEN7;
 479                         break;
 480                 case BCS:
 481                         mmio = BLT_HWS_PGA_GEN7;
 482                         break;
 483                 /*
 484                  * VCS2 actually doesn't exist on Gen7. Only shut up
 485                  * gcc switch check warning
 486                  */
 487                 case VCS2:
 488                 case VCS:
 489                         mmio = BSD_HWS_PGA_GEN7;
 490                         break;
 491                 case VECS:
 492                         mmio = VEBOX_HWS_PGA_GEN7;
 493                         break;
 494                 }
 495         } else if (IS_GEN6(engine->dev)) {
 496                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 497         } else {
 498                 /* XXX: gen8 returns to sanity */
 499                 mmio = RING_HWS_PGA(engine->mmio_base);
 500         }
 501
 502         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 503         POSTING_READ(mmio);
 504
 505         /*
 506          * Flush the TLB for this page
 507          *
 508          * FIXME: These two bits have disappeared on gen8, so a question
 509          * arises: do we still need this and if so how should we go about
 510          * invalidating the TLB?
 511          */
 512         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 513                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 514
 515                 /* ring should be idle before issuing a sync flush*/
 516                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 517
 518                 I915_WRITE(reg,
 519                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 520                                               INSTPM_SYNC_FLUSH));
 521                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 522                              1000))
 523                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 524                                   engine->name);
 525         }
 526 }
 527
 528 static bool stop_ring(struct intel_engine_cs *engine)
 529 {
 530         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 531
 532         if (!IS_GEN2(engine->dev)) {
 533                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 534                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 535                         DRM_ERROR("%s : timed out trying to stop ring\n",
 536                                   engine->name);
 537                         /* Sometimes we observe that the idle flag is not
 538                          * set even though the ring is empty. So double
 539                          * check before giving up.
 540                          */
 541                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 542                                 return false;
 543                 }
 544         }
 545
 546         I915_WRITE_CTL(engine, 0);
 547         I915_WRITE_HEAD(engine, 0);
 548         engine->write_tail(engine, 0);
 549
 550         if (!IS_GEN2(engine->dev)) {
 551                 (void)I915_READ_CTL(engine);
 552                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 553         }
 554
 555         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 556 }
 557
 558 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 559 {
 560         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 561 }
 562
 563 static int init_ring_common(struct intel_engine_cs *engine)
 564 {
 565         struct drm_device *dev = engine->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_ringbuffer *ringbuf = engine->buffer;
 568         struct drm_i915_gem_object *obj = ringbuf->obj;
 569         int ret = 0;
 570
 571         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 572
 573         if (!stop_ring(engine)) {
 574                 /* G45 ring initialization often fails to reset head to zero */
 575                 DRM_DEBUG_KMS("%s head not reset to zero "
 576                               "ctl %08x head %08x tail %08x start %08x\n",
 577                               engine->name,
 578                               I915_READ_CTL(engine),
 579                               I915_READ_HEAD(engine),
 580                               I915_READ_TAIL(engine),
 581                               I915_READ_START(engine));
 582
 583                 if (!stop_ring(engine)) {
 584                         DRM_ERROR("failed to set %s head to zero "
 585                                   "ctl %08x head %08x tail %08x start %08x\n",
 586                                   engine->name,
 587                                   I915_READ_CTL(engine),
 588                                   I915_READ_HEAD(engine),
 589                                   I915_READ_TAIL(engine),
 590                                   I915_READ_START(engine));
 591                         ret = -EIO;
 592                         goto out;
 593                 }
 594         }
 595
 596         if (I915_NEED_GFX_HWS(dev))
 597                 intel_ring_setup_status_page(engine);
 598         else
 599                 ring_setup_phys_status_page(engine);
 600
 601         /* Enforce ordering by reading HEAD register back */
 602         I915_READ_HEAD(engine);
 603
 604         /* Initialize the ring. This must happen _after_ we've cleared the ring
 605          * registers with the above sequence (the readback of the HEAD registers
 606          * also enforces ordering), otherwise the hw might lose the new ring
 607          * register values. */
 608         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 609
 610         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 611         if (I915_READ_HEAD(engine))
 612                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 613                           engine->name, I915_READ_HEAD(engine));
 614         I915_WRITE_HEAD(engine, 0);
 615         (void)I915_READ_HEAD(engine);
 616
 617         I915_WRITE_CTL(engine,
 618                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 619                         | RING_VALID);
 620
 621         /* If the head is still not zero, the ring is dead */
 622         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 623                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 624                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 625                 DRM_ERROR("%s initialization failed "
 626                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 627                           engine->name,
 628                           I915_READ_CTL(engine),
 629                           I915_READ_CTL(engine) & RING_VALID,
 630                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 631                           I915_READ_START(engine),
 632                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 633                 ret = -EIO;
 634                 goto out;
 635         }
 636
 637         ringbuf->last_retired_head = -1;
 638         ringbuf->head = I915_READ_HEAD(engine);
 639         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 640         intel_ring_update_space(ringbuf);
 641
 642         intel_engine_init_hangcheck(engine);
 643
 644 out:
 645         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 646
 647         return ret;
 648 }
 649
 650 void
 651 intel_fini_pipe_control(struct intel_engine_cs *engine)
 652 {
 653         struct drm_device *dev = engine->dev;
 654
 655         if (engine->scratch.obj == NULL)
 656                 return;
 657
 658         if (INTEL_INFO(dev)->gen >= 5) {
 659                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 660                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 661         }
 662
 663         drm_gem_object_unreference(&engine->scratch.obj->base);
 664         engine->scratch.obj = NULL;
 665 }
 666
 667 int
 668 intel_init_pipe_control(struct intel_engine_cs *engine)
 669 {
 670         int ret;
 671
 672         WARN_ON(engine->scratch.obj);
 673
 674         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 675         if (engine->scratch.obj == NULL) {
 676                 DRM_ERROR("Failed to allocate seqno page\n");
 677                 ret = -ENOMEM;
 678                 goto err;
 679         }
 680
 681         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 682                                               I915_CACHE_LLC);
 683         if (ret)
 684                 goto err_unref;
 685
 686         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 687         if (ret)
 688                 goto err_unref;
 689
 690         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 691         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 692         if (engine->scratch.cpu_page == NULL) {
 693                 ret = -ENOMEM;
 694                 goto err_unpin;
 695         }
 696
 697         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 698                          engine->name, engine->scratch.gtt_offset);
 699         return 0;
 700
 701 err_unpin:
 702         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 703 err_unref:
 704         drm_gem_object_unreference(&engine->scratch.obj->base);
 705 err:
 706         return ret;
 707 }
 708
 709 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 710 {
 711         int ret, i;
 712         struct intel_engine_cs *engine = req->engine;
 713         struct drm_device *dev = engine->dev;
 714         struct drm_i915_private *dev_priv = dev->dev_private;
 715         struct i915_workarounds *w = &dev_priv->workarounds;
 716
 717         if (w->count == 0)
 718                 return 0;
 719
 720         engine->gpu_caches_dirty = true;
 721         ret = intel_ring_flush_all_caches(req);
 722         if (ret)
 723                 return ret;
 724
 725         ret = intel_ring_begin(req, (w->count * 2 + 2));
 726         if (ret)
 727                 return ret;
 728
 729         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 730         for (i = 0; i < w->count; i++) {
 731                 intel_ring_emit_reg(engine, w->reg[i].addr);
 732                 intel_ring_emit(engine, w->reg[i].value);
 733         }
 734         intel_ring_emit(engine, MI_NOOP);
 735
 736         intel_ring_advance(engine);
 737
 738         engine->gpu_caches_dirty = true;
 739         ret = intel_ring_flush_all_caches(req);
 740         if (ret)
 741                 return ret;
 742
 743         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 744
 745         return 0;
 746 }
 747
 748 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 749 {
 750         int ret;
 751
 752         ret = intel_ring_workarounds_emit(req);
 753         if (ret != 0)
 754                 return ret;
 755
 756         ret = i915_gem_render_state_init(req);
 757         if (ret)
 758                 return ret;
 759
 760         return 0;
 761 }
 762
 763 static int wa_add(struct drm_i915_private *dev_priv,
 764                   i915_reg_t addr,
 765                   const u32 mask, const u32 val)
 766 {
 767         const u32 idx = dev_priv->workarounds.count;
 768
 769         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 770                 return -ENOSPC;
 771
 772         dev_priv->workarounds.reg[idx].addr = addr;
 773         dev_priv->workarounds.reg[idx].value = val;
 774         dev_priv->workarounds.reg[idx].mask = mask;
 775
 776         dev_priv->workarounds.count++;
 777
 778         return 0;
 779 }
 780
 781 #define WA_REG(addr, mask, val) do { \
 782                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 783                 if (r) \
 784                         return r; \
 785         } while (0)
 786
 787 #define WA_SET_BIT_MASKED(addr, mask) \
 788         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 789
 790 #define WA_CLR_BIT_MASKED(addr, mask) \
 791         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 792
 793 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 794         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 795
 796 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 797 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 798
 799 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 800
 801 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 802                                  i915_reg_t reg)
 803 {
 804         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 805         struct i915_workarounds *wa = &dev_priv->workarounds;
 806         const uint32_t index = wa->hw_whitelist_count[engine->id];
 807
 808         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 809                 return -EINVAL;
 810
 811         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 812                  i915_mmio_reg_offset(reg));
 813         wa->hw_whitelist_count[engine->id]++;
 814
 815         return 0;
 816 }
 817
 818 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 819 {
 820         struct drm_device *dev = engine->dev;
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822
 823         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 824
 825         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 826         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 827
 828         /* WaDisablePartialInstShootdown:bdw,chv */
 829         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 830                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 831
 832         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 833          * workaround for for a possible hang in the unlikely event a TLB
 834          * invalidation occurs during a PSD flush.
 835          */
 836         /* WaForceEnableNonCoherent:bdw,chv */
 837         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 838         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 839                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 840                           HDC_FORCE_NON_COHERENT);
 841
 842         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 843          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 844          *  polygons in the same 8x4 pixel/sample area to be processed without
 845          *  stalling waiting for the earlier ones to write to Hierarchical Z
 846          *  buffer."
 847          *
 848          * This optimization is off by default for BDW and CHV; turn it on.
 849          */
 850         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 851
 852         /* Wa4x4STCOptimizationDisable:bdw,chv */
 853         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 854
 855         /*
 856          * BSpec recommends 8x4 when MSAA is used,
 857          * however in practice 16x4 seems fastest.
 858          *
 859          * Note that PS/WM thread counts depend on the WIZ hashing
 860          * disable bit, which we don't touch here, but it's good
 861          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 862          */
 863         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 864                             GEN6_WIZ_HASHING_MASK,
 865                             GEN6_WIZ_HASHING_16x4);
 866
 867         return 0;
 868 }
 869
 870 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 871 {
 872         int ret;
 873         struct drm_device *dev = engine->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875
 876         ret = gen8_init_workarounds(engine);
 877         if (ret)
 878                 return ret;
 879
 880         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 881         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 882
 883         /* WaDisableDopClockGating:bdw */
 884         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 885                           DOP_CLOCK_GATING_DISABLE);
 886
 887         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 888                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 889
 890         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 891                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 892                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 893                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 894                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 895
 896         return 0;
 897 }
 898
 899 static int chv_init_workarounds(struct intel_engine_cs *engine)
 900 {
 901         int ret;
 902         struct drm_device *dev = engine->dev;
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904
 905         ret = gen8_init_workarounds(engine);
 906         if (ret)
 907                 return ret;
 908
 909         /* WaDisableThreadStallDopClockGating:chv */
 910         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 911
 912         /* Improve HiZ throughput on CHV. */
 913         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 914
 915         return 0;
 916 }
 917
 918 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 919 {
 920         struct drm_device *dev = engine->dev;
 921         struct drm_i915_private *dev_priv = dev->dev_private;
 922         uint32_t tmp;
 923         int ret;
 924
 925         /* WaEnableLbsSlaRetryTimerDecrement:skl */
 926         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 927                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 928
 929         /* WaDisableKillLogic:bxt,skl */
 930         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 931                    ECOCHK_DIS_TLB);
 932
 933         /* WaClearFlowControlGpgpuContextSave:skl,bxt */
 934         /* WaDisablePartialInstShootdown:skl,bxt */
 935         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 936                           FLOW_CONTROL_ENABLE |
 937                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 938
 939         /* Syncing dependencies between camera and graphics:skl,bxt */
 940         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 941                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 942
 943         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 944         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 945             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 946                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 947                                   GEN9_DG_MIRROR_FIX_ENABLE);
 948
 949         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 950         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 951             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 952                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 953                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 954                 /*
 955                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 956                  * but we do that in per ctx batchbuffer as there is an issue
 957                  * with this register not getting restored on ctx restore
 958                  */
 959         }
 960
 961         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 962         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
 963                 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 964                                   GEN9_ENABLE_YV12_BUGFIX);
 965
 966         /* Wa4x4STCOptimizationDisable:skl,bxt */
 967         /* WaDisablePartialResolveInVc:skl,bxt */
 968         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 969                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 970
 971         /* WaCcsTlbPrefetchDisable:skl,bxt */
 972         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 973                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 974
 975         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 976         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 977             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 978                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 979                                   PIXEL_MASK_CAMMING_DISABLE);
 980
 981         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
 982         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
 983         if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
 984             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
 985                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 986         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 987
 988         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
 989         if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
 990                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 991                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 992
 993         /* WaDisableSTUnitPowerOptimization:skl,bxt */
 994         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 995
 996         /* WaOCLCoherentLineFlush:skl,bxt */
 997         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 998                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 999
1000         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
1001         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1002         if (ret)
1003                 return ret;
1004
1005         /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1006         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1007         if (ret)
1008                 return ret;
1009
1010         return 0;
1011 }
1012
1013 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1014 {
1015         struct drm_device *dev = engine->dev;
1016         struct drm_i915_private *dev_priv = dev->dev_private;
1017         u8 vals[3] = { 0, 0, 0 };
1018         unsigned int i;
1019
1020         for (i = 0; i < 3; i++) {
1021                 u8 ss;
1022
1023                 /*
1024                  * Only consider slices where one, and only one, subslice has 7
1025                  * EUs
1026                  */
1027                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1028                         continue;
1029
1030                 /*
1031                  * subslice_7eu[i] != 0 (because of the check above) and
1032                  * ss_max == 4 (maximum number of subslices possible per slice)
1033                  *
1034                  * ->    0 <= ss <= 3;
1035                  */
1036                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1037                 vals[i] = 3 - ss;
1038         }
1039
1040         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1041                 return 0;
1042
1043         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1044         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1045                             GEN9_IZ_HASHING_MASK(2) |
1046                             GEN9_IZ_HASHING_MASK(1) |
1047                             GEN9_IZ_HASHING_MASK(0),
1048                             GEN9_IZ_HASHING(2, vals[2]) |
1049                             GEN9_IZ_HASHING(1, vals[1]) |
1050                             GEN9_IZ_HASHING(0, vals[0]));
1051
1052         return 0;
1053 }
1054
1055 static int skl_init_workarounds(struct intel_engine_cs *engine)
1056 {
1057         int ret;
1058         struct drm_device *dev = engine->dev;
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060
1061         ret = gen9_init_workarounds(engine);
1062         if (ret)
1063                 return ret;
1064
1065         /*
1066          * Actual WA is to disable percontext preemption granularity control
1067          * until D0 which is the default case so this is equivalent to
1068          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1069          */
1070         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1071                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1072                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1073         }
1074
1075         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1076                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1077                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1078                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1079         }
1080
1081         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1082          * involving this register should also be added to WA batch as required.
1083          */
1084         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1085                 /* WaDisableLSQCROPERFforOCL:skl */
1086                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1087                            GEN8_LQSC_RO_PERF_DIS);
1088
1089         /* WaEnableGapsTsvCreditFix:skl */
1090         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1091                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1092                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1093         }
1094
1095         /* WaDisablePowerCompilerClockGating:skl */
1096         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1097                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1098                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1099
1100         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
1101                 /*
1102                  *Use Force Non-Coherent whenever executing a 3D context. This
1103                  * is a workaround for a possible hang in the unlikely event
1104                  * a TLB invalidation occurs during a PSD flush.
1105                  */
1106                 /* WaForceEnableNonCoherent:skl */
1107                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1108                                   HDC_FORCE_NON_COHERENT);
1109
1110                 /* WaDisableHDCInvalidation:skl */
1111                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1112                            BDW_DISABLE_HDC_INVALIDATION);
1113         }
1114
1115         /* WaBarrierPerformanceFixDisable:skl */
1116         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1117                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1118                                   HDC_FENCE_DEST_SLM_DISABLE |
1119                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1120
1121         /* WaDisableSbeCacheDispatchPortSharing:skl */
1122         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1123                 WA_SET_BIT_MASKED(
1124                         GEN7_HALF_SLICE_CHICKEN1,
1125                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1126
1127         /* WaDisableLSQCROPERFforOCL:skl */
1128         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1129         if (ret)
1130                 return ret;
1131
1132         return skl_tune_iz_hashing(engine);
1133 }
1134
1135 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1136 {
1137         int ret;
1138         struct drm_device *dev = engine->dev;
1139         struct drm_i915_private *dev_priv = dev->dev_private;
1140
1141         ret = gen9_init_workarounds(engine);
1142         if (ret)
1143                 return ret;
1144
1145         /* WaStoreMultiplePTEenable:bxt */
1146         /* This is a requirement according to Hardware specification */
1147         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1148                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1149
1150         /* WaSetClckGatingDisableMedia:bxt */
1151         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1152                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1153                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1154         }
1155
1156         /* WaDisableThreadStallDopClockGating:bxt */
1157         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1158                           STALL_DOP_GATING_DISABLE);
1159
1160         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1161         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1162                 WA_SET_BIT_MASKED(
1163                         GEN7_HALF_SLICE_CHICKEN1,
1164                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1165         }
1166
1167         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1168         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1169         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1170         /* WaDisableLSQCROPERFforOCL:bxt */
1171         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1172                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1173                 if (ret)
1174                         return ret;
1175
1176                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1177                 if (ret)
1178                         return ret;
1179         }
1180
1181         return 0;
1182 }
1183
1184 int init_workarounds_ring(struct intel_engine_cs *engine)
1185 {
1186         struct drm_device *dev = engine->dev;
1187         struct drm_i915_private *dev_priv = dev->dev_private;
1188
1189         WARN_ON(engine->id != RCS);
1190
1191         dev_priv->workarounds.count = 0;
1192         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1193
1194         if (IS_BROADWELL(dev))
1195                 return bdw_init_workarounds(engine);
1196
1197         if (IS_CHERRYVIEW(dev))
1198                 return chv_init_workarounds(engine);
1199
1200         if (IS_SKYLAKE(dev))
1201                 return skl_init_workarounds(engine);
1202
1203         if (IS_BROXTON(dev))
1204                 return bxt_init_workarounds(engine);
1205
1206         return 0;
1207 }
1208
1209 static int init_render_ring(struct intel_engine_cs *engine)
1210 {
1211         struct drm_device *dev = engine->dev;
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213         int ret = init_ring_common(engine);
1214         if (ret)
1215                 return ret;
1216
1217         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1218         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1219                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1220
1221         /* We need to disable the AsyncFlip performance optimisations in order
1222          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1223          * programmed to '1' on all products.
1224          *
1225          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1226          */
1227         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1228                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1229
1230         /* Required for the hardware to program scanline values for waiting */
1231         /* WaEnableFlushTlbInvalidationMode:snb */
1232         if (INTEL_INFO(dev)->gen == 6)
1233                 I915_WRITE(GFX_MODE,
1234                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1235
1236         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1237         if (IS_GEN7(dev))
1238                 I915_WRITE(GFX_MODE_GEN7,
1239                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1240                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1241
1242         if (IS_GEN6(dev)) {
1243                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1244                  * "If this bit is set, STCunit will have LRA as replacement
1245                  *  policy. [...] This bit must be reset.  LRA replacement
1246                  *  policy is not supported."
1247                  */
1248                 I915_WRITE(CACHE_MODE_0,
1249                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1250         }
1251
1252         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1253                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1254
1255         if (HAS_L3_DPF(dev))
1256                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1257
1258         return init_workarounds_ring(engine);
1259 }
1260
1261 static void render_ring_cleanup(struct intel_engine_cs *engine)
1262 {
1263         struct drm_device *dev = engine->dev;
1264         struct drm_i915_private *dev_priv = dev->dev_private;
1265
1266         if (dev_priv->semaphore_obj) {
1267                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1268                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1269                 dev_priv->semaphore_obj = NULL;
1270         }
1271
1272         intel_fini_pipe_control(engine);
1273 }
1274
1275 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1276                            unsigned int num_dwords)
1277 {
1278 #define MBOX_UPDATE_DWORDS 8
1279         struct intel_engine_cs *signaller = signaller_req->engine;
1280         struct drm_device *dev = signaller->dev;
1281         struct drm_i915_private *dev_priv = dev->dev_private;
1282         struct intel_engine_cs *waiter;
1283         enum intel_engine_id id;
1284         int ret, num_rings;
1285
1286         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1287         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1288 #undef MBOX_UPDATE_DWORDS
1289
1290         ret = intel_ring_begin(signaller_req, num_dwords);
1291         if (ret)
1292                 return ret;
1293
1294         for_each_engine_id(waiter, dev_priv, id) {
1295                 u32 seqno;
1296                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1297                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1298                         continue;
1299
1300                 seqno = i915_gem_request_get_seqno(signaller_req);
1301                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1302                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1303                                            PIPE_CONTROL_QW_WRITE |
1304                                            PIPE_CONTROL_FLUSH_ENABLE);
1305                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1306                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1307                 intel_ring_emit(signaller, seqno);
1308                 intel_ring_emit(signaller, 0);
1309                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1310                                            MI_SEMAPHORE_TARGET(waiter->id));
1311                 intel_ring_emit(signaller, 0);
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1318                            unsigned int num_dwords)
1319 {
1320 #define MBOX_UPDATE_DWORDS 6
1321         struct intel_engine_cs *signaller = signaller_req->engine;
1322         struct drm_device *dev = signaller->dev;
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         struct intel_engine_cs *waiter;
1325         enum intel_engine_id id;
1326         int ret, num_rings;
1327
1328         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1329         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1330 #undef MBOX_UPDATE_DWORDS
1331
1332         ret = intel_ring_begin(signaller_req, num_dwords);
1333         if (ret)
1334                 return ret;
1335
1336         for_each_engine_id(waiter, dev_priv, id) {
1337                 u32 seqno;
1338                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1339                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1340                         continue;
1341
1342                 seqno = i915_gem_request_get_seqno(signaller_req);
1343                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1344                                            MI_FLUSH_DW_OP_STOREDW);
1345                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1346                                            MI_FLUSH_DW_USE_GTT);
1347                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1348                 intel_ring_emit(signaller, seqno);
1349                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1350                                            MI_SEMAPHORE_TARGET(waiter->id));
1351                 intel_ring_emit(signaller, 0);
1352         }
1353
1354         return 0;
1355 }
1356
1357 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1358                        unsigned int num_dwords)
1359 {
1360         struct intel_engine_cs *signaller = signaller_req->engine;
1361         struct drm_device *dev = signaller->dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         struct intel_engine_cs *useless;
1364         enum intel_engine_id id;
1365         int ret, num_rings;
1366
1367 #define MBOX_UPDATE_DWORDS 3
1368         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1369         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1370 #undef MBOX_UPDATE_DWORDS
1371
1372         ret = intel_ring_begin(signaller_req, num_dwords);
1373         if (ret)
1374                 return ret;
1375
1376         for_each_engine_id(useless, dev_priv, id) {
1377                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1378
1379                 if (i915_mmio_reg_valid(mbox_reg)) {
1380                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1381
1382                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1383                         intel_ring_emit_reg(signaller, mbox_reg);
1384                         intel_ring_emit(signaller, seqno);
1385                 }
1386         }
1387
1388         /* If num_dwords was rounded, make sure the tail pointer is correct */
1389         if (num_rings % 2 == 0)
1390                 intel_ring_emit(signaller, MI_NOOP);
1391
1392         return 0;
1393 }
1394
1395 /**
1396  * gen6_add_request - Update the semaphore mailbox registers
1397  *
1398  * @request - request to write to the ring
1399  *
1400  * Update the mailbox registers in the *other* rings with the current seqno.
1401  * This acts like a signal in the canonical semaphore.
1402  */
1403 static int
1404 gen6_add_request(struct drm_i915_gem_request *req)
1405 {
1406         struct intel_engine_cs *engine = req->engine;
1407         int ret;
1408
1409         if (engine->semaphore.signal)
1410                 ret = engine->semaphore.signal(req, 4);
1411         else
1412                 ret = intel_ring_begin(req, 4);
1413
1414         if (ret)
1415                 return ret;
1416
1417         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1418         intel_ring_emit(engine,
1419                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1420         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1421         intel_ring_emit(engine, MI_USER_INTERRUPT);
1422         __intel_ring_advance(engine);
1423
1424         return 0;
1425 }
1426
1427 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1428                                               u32 seqno)
1429 {
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         return dev_priv->last_seqno < seqno;
1432 }
1433
1434 /**
1435  * intel_ring_sync - sync the waiter to the signaller on seqno
1436  *
1437  * @waiter - ring that is waiting
1438  * @signaller - ring which has, or will signal
1439  * @seqno - seqno which the waiter will block on
1440  */
1441
1442 static int
1443 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1444                struct intel_engine_cs *signaller,
1445                u32 seqno)
1446 {
1447         struct intel_engine_cs *waiter = waiter_req->engine;
1448         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1449         int ret;
1450
1451         ret = intel_ring_begin(waiter_req, 4);
1452         if (ret)
1453                 return ret;
1454
1455         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1456                                 MI_SEMAPHORE_GLOBAL_GTT |
1457                                 MI_SEMAPHORE_POLL |
1458                                 MI_SEMAPHORE_SAD_GTE_SDD);
1459         intel_ring_emit(waiter, seqno);
1460         intel_ring_emit(waiter,
1461                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1462         intel_ring_emit(waiter,
1463                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1464         intel_ring_advance(waiter);
1465         return 0;
1466 }
1467
1468 static int
1469 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1470                struct intel_engine_cs *signaller,
1471                u32 seqno)
1472 {
1473         struct intel_engine_cs *waiter = waiter_req->engine;
1474         u32 dw1 = MI_SEMAPHORE_MBOX |
1475                   MI_SEMAPHORE_COMPARE |
1476                   MI_SEMAPHORE_REGISTER;
1477         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1478         int ret;
1479
1480         /* Throughout all of the GEM code, seqno passed implies our current
1481          * seqno is >= the last seqno executed. However for hardware the
1482          * comparison is strictly greater than.
1483          */
1484         seqno -= 1;
1485
1486         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1487
1488         ret = intel_ring_begin(waiter_req, 4);
1489         if (ret)
1490                 return ret;
1491
1492         /* If seqno wrap happened, omit the wait with no-ops */
1493         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1494                 intel_ring_emit(waiter, dw1 | wait_mbox);
1495                 intel_ring_emit(waiter, seqno);
1496                 intel_ring_emit(waiter, 0);
1497                 intel_ring_emit(waiter, MI_NOOP);
1498         } else {
1499                 intel_ring_emit(waiter, MI_NOOP);
1500                 intel_ring_emit(waiter, MI_NOOP);
1501                 intel_ring_emit(waiter, MI_NOOP);
1502                 intel_ring_emit(waiter, MI_NOOP);
1503         }
1504         intel_ring_advance(waiter);
1505
1506         return 0;
1507 }
1508
1509 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1510 do {                                                                    \
1511         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1512                  PIPE_CONTROL_DEPTH_STALL);                             \
1513         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1514         intel_ring_emit(ring__, 0);                                                     \
1515         intel_ring_emit(ring__, 0);                                                     \
1516 } while (0)
1517
1518 static int
1519 pc_render_add_request(struct drm_i915_gem_request *req)
1520 {
1521         struct intel_engine_cs *engine = req->engine;
1522         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1523         int ret;
1524
1525         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1526          * incoherent with writes to memory, i.e. completely fubar,
1527          * so we need to use PIPE_NOTIFY instead.
1528          *
1529          * However, we also need to workaround the qword write
1530          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1531          * memory before requesting an interrupt.
1532          */
1533         ret = intel_ring_begin(req, 32);
1534         if (ret)
1535                 return ret;
1536
1537         intel_ring_emit(engine,
1538                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1539                         PIPE_CONTROL_WRITE_FLUSH |
1540                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1541         intel_ring_emit(engine,
1542                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1543         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1544         intel_ring_emit(engine, 0);
1545         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1546         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1547         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1548         scratch_addr += 2 * CACHELINE_BYTES;
1549         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1550         scratch_addr += 2 * CACHELINE_BYTES;
1551         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1552         scratch_addr += 2 * CACHELINE_BYTES;
1553         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1554         scratch_addr += 2 * CACHELINE_BYTES;
1555         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1556
1557         intel_ring_emit(engine,
1558                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1559                         PIPE_CONTROL_WRITE_FLUSH |
1560                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1561                         PIPE_CONTROL_NOTIFY);
1562         intel_ring_emit(engine,
1563                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1564         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1565         intel_ring_emit(engine, 0);
1566         __intel_ring_advance(engine);
1567
1568         return 0;
1569 }
1570
1571 static void
1572 gen6_seqno_barrier(struct intel_engine_cs *engine)
1573 {
1574         /* Workaround to force correct ordering between irq and seqno writes on
1575          * ivb (and maybe also on snb) by reading from a CS register (like
1576          * ACTHD) before reading the status page.
1577          *
1578          * Note that this effectively stalls the read by the time it takes to
1579          * do a memory transaction, which more or less ensures that the write
1580          * from the GPU has sufficient time to invalidate the CPU cacheline.
1581          * Alternatively we could delay the interrupt from the CS ring to give
1582          * the write time to land, but that would incur a delay after every
1583          * batch i.e. much more frequent than a delay when waiting for the
1584          * interrupt (with the same net latency).
1585          */
1586         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1587         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1588 }
1589
1590 static u32
1591 ring_get_seqno(struct intel_engine_cs *engine)
1592 {
1593         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1594 }
1595
1596 static void
1597 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1598 {
1599         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1600 }
1601
1602 static u32
1603 pc_render_get_seqno(struct intel_engine_cs *engine)
1604 {
1605         return engine->scratch.cpu_page[0];
1606 }
1607
1608 static void
1609 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1610 {
1611         engine->scratch.cpu_page[0] = seqno;
1612 }
1613
1614 static bool
1615 gen5_ring_get_irq(struct intel_engine_cs *engine)
1616 {
1617         struct drm_device *dev = engine->dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         unsigned long flags;
1620
1621         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1622                 return false;
1623
1624         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1625         if (engine->irq_refcount++ == 0)
1626                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1627         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1628
1629         return true;
1630 }
1631
1632 static void
1633 gen5_ring_put_irq(struct intel_engine_cs *engine)
1634 {
1635         struct drm_device *dev = engine->dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         unsigned long flags;
1638
1639         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1640         if (--engine->irq_refcount == 0)
1641                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1642         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1643 }
1644
1645 static bool
1646 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1647 {
1648         struct drm_device *dev = engine->dev;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         unsigned long flags;
1651
1652         if (!intel_irqs_enabled(dev_priv))
1653                 return false;
1654
1655         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1656         if (engine->irq_refcount++ == 0) {
1657                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1658                 I915_WRITE(IMR, dev_priv->irq_mask);
1659                 POSTING_READ(IMR);
1660         }
1661         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1662
1663         return true;
1664 }
1665
1666 static void
1667 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1668 {
1669         struct drm_device *dev = engine->dev;
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         unsigned long flags;
1672
1673         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1674         if (--engine->irq_refcount == 0) {
1675                 dev_priv->irq_mask |= engine->irq_enable_mask;
1676                 I915_WRITE(IMR, dev_priv->irq_mask);
1677                 POSTING_READ(IMR);
1678         }
1679         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1680 }
1681
1682 static bool
1683 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1684 {
1685         struct drm_device *dev = engine->dev;
1686         struct drm_i915_private *dev_priv = dev->dev_private;
1687         unsigned long flags;
1688
1689         if (!intel_irqs_enabled(dev_priv))
1690                 return false;
1691
1692         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1693         if (engine->irq_refcount++ == 0) {
1694                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1695                 I915_WRITE16(IMR, dev_priv->irq_mask);
1696                 POSTING_READ16(IMR);
1697         }
1698         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1699
1700         return true;
1701 }
1702
1703 static void
1704 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1705 {
1706         struct drm_device *dev = engine->dev;
1707         struct drm_i915_private *dev_priv = dev->dev_private;
1708         unsigned long flags;
1709
1710         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1711         if (--engine->irq_refcount == 0) {
1712                 dev_priv->irq_mask |= engine->irq_enable_mask;
1713                 I915_WRITE16(IMR, dev_priv->irq_mask);
1714                 POSTING_READ16(IMR);
1715         }
1716         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1717 }
1718
1719 static int
1720 bsd_ring_flush(struct drm_i915_gem_request *req,
1721                u32     invalidate_domains,
1722                u32     flush_domains)
1723 {
1724         struct intel_engine_cs *engine = req->engine;
1725         int ret;
1726
1727         ret = intel_ring_begin(req, 2);
1728         if (ret)
1729                 return ret;
1730
1731         intel_ring_emit(engine, MI_FLUSH);
1732         intel_ring_emit(engine, MI_NOOP);
1733         intel_ring_advance(engine);
1734         return 0;
1735 }
1736
1737 static int
1738 i9xx_add_request(struct drm_i915_gem_request *req)
1739 {
1740         struct intel_engine_cs *engine = req->engine;
1741         int ret;
1742
1743         ret = intel_ring_begin(req, 4);
1744         if (ret)
1745                 return ret;
1746
1747         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1748         intel_ring_emit(engine,
1749                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1750         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1751         intel_ring_emit(engine, MI_USER_INTERRUPT);
1752         __intel_ring_advance(engine);
1753
1754         return 0;
1755 }
1756
1757 static bool
1758 gen6_ring_get_irq(struct intel_engine_cs *engine)
1759 {
1760         struct drm_device *dev = engine->dev;
1761         struct drm_i915_private *dev_priv = dev->dev_private;
1762         unsigned long flags;
1763
1764         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1765                 return false;
1766
1767         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1768         if (engine->irq_refcount++ == 0) {
1769                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1770                         I915_WRITE_IMR(engine,
1771                                        ~(engine->irq_enable_mask |
1772                                          GT_PARITY_ERROR(dev)));
1773                 else
1774                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1775                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1776         }
1777         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1778
1779         return true;
1780 }
1781
1782 static void
1783 gen6_ring_put_irq(struct intel_engine_cs *engine)
1784 {
1785         struct drm_device *dev = engine->dev;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         unsigned long flags;
1788
1789         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1790         if (--engine->irq_refcount == 0) {
1791                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1792                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1793                 else
1794                         I915_WRITE_IMR(engine, ~0);
1795                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1796         }
1797         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1798 }
1799
1800 static bool
1801 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1802 {
1803         struct drm_device *dev = engine->dev;
1804         struct drm_i915_private *dev_priv = dev->dev_private;
1805         unsigned long flags;
1806
1807         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1808                 return false;
1809
1810         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1811         if (engine->irq_refcount++ == 0) {
1812                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1813                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1814         }
1815         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1816
1817         return true;
1818 }
1819
1820 static void
1821 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1822 {
1823         struct drm_device *dev = engine->dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         unsigned long flags;
1826
1827         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1828         if (--engine->irq_refcount == 0) {
1829                 I915_WRITE_IMR(engine, ~0);
1830                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1831         }
1832         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1833 }
1834
1835 static bool
1836 gen8_ring_get_irq(struct intel_engine_cs *engine)
1837 {
1838         struct drm_device *dev = engine->dev;
1839         struct drm_i915_private *dev_priv = dev->dev_private;
1840         unsigned long flags;
1841
1842         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1843                 return false;
1844
1845         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1846         if (engine->irq_refcount++ == 0) {
1847                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1848                         I915_WRITE_IMR(engine,
1849                                        ~(engine->irq_enable_mask |
1850                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1851                 } else {
1852                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1853                 }
1854                 POSTING_READ(RING_IMR(engine->mmio_base));
1855         }
1856         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1857
1858         return true;
1859 }
1860
1861 static void
1862 gen8_ring_put_irq(struct intel_engine_cs *engine)
1863 {
1864         struct drm_device *dev = engine->dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         unsigned long flags;
1867
1868         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1869         if (--engine->irq_refcount == 0) {
1870                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1871                         I915_WRITE_IMR(engine,
1872                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1873                 } else {
1874                         I915_WRITE_IMR(engine, ~0);
1875                 }
1876                 POSTING_READ(RING_IMR(engine->mmio_base));
1877         }
1878         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1879 }
1880
1881 static int
1882 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1883                          u64 offset, u32 length,
1884                          unsigned dispatch_flags)
1885 {
1886         struct intel_engine_cs *engine = req->engine;
1887         int ret;
1888
1889         ret = intel_ring_begin(req, 2);
1890         if (ret)
1891                 return ret;
1892
1893         intel_ring_emit(engine,
1894                         MI_BATCH_BUFFER_START |
1895                         MI_BATCH_GTT |
1896                         (dispatch_flags & I915_DISPATCH_SECURE ?
1897                          0 : MI_BATCH_NON_SECURE_I965));
1898         intel_ring_emit(engine, offset);
1899         intel_ring_advance(engine);
1900
1901         return 0;
1902 }
1903
1904 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1905 #define I830_BATCH_LIMIT (256*1024)
1906 #define I830_TLB_ENTRIES (2)
1907 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1908 static int
1909 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1910                          u64 offset, u32 len,
1911                          unsigned dispatch_flags)
1912 {
1913         struct intel_engine_cs *engine = req->engine;
1914         u32 cs_offset = engine->scratch.gtt_offset;
1915         int ret;
1916
1917         ret = intel_ring_begin(req, 6);
1918         if (ret)
1919                 return ret;
1920
1921         /* Evict the invalid PTE TLBs */
1922         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1923         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1924         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1925         intel_ring_emit(engine, cs_offset);
1926         intel_ring_emit(engine, 0xdeadbeef);
1927         intel_ring_emit(engine, MI_NOOP);
1928         intel_ring_advance(engine);
1929
1930         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1931                 if (len > I830_BATCH_LIMIT)
1932                         return -ENOSPC;
1933
1934                 ret = intel_ring_begin(req, 6 + 2);
1935                 if (ret)
1936                         return ret;
1937
1938                 /* Blit the batch (which has now all relocs applied) to the
1939                  * stable batch scratch bo area (so that the CS never
1940                  * stumbles over its tlb invalidation bug) ...
1941                  */
1942                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1943                 intel_ring_emit(engine,
1944                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1945                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1946                 intel_ring_emit(engine, cs_offset);
1947                 intel_ring_emit(engine, 4096);
1948                 intel_ring_emit(engine, offset);
1949
1950                 intel_ring_emit(engine, MI_FLUSH);
1951                 intel_ring_emit(engine, MI_NOOP);
1952                 intel_ring_advance(engine);
1953
1954                 /* ... and execute it. */
1955                 offset = cs_offset;
1956         }
1957
1958         ret = intel_ring_begin(req, 2);
1959         if (ret)
1960                 return ret;
1961
1962         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1963         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1964                                           0 : MI_BATCH_NON_SECURE));
1965         intel_ring_advance(engine);
1966
1967         return 0;
1968 }
1969
1970 static int
1971 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1972                          u64 offset, u32 len,
1973                          unsigned dispatch_flags)
1974 {
1975         struct intel_engine_cs *engine = req->engine;
1976         int ret;
1977
1978         ret = intel_ring_begin(req, 2);
1979         if (ret)
1980                 return ret;
1981
1982         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1983         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1984                                           0 : MI_BATCH_NON_SECURE));
1985         intel_ring_advance(engine);
1986
1987         return 0;
1988 }
1989
1990 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1991 {
1992         struct drm_i915_private *dev_priv = to_i915(engine->dev);
1993
1994         if (!dev_priv->status_page_dmah)
1995                 return;
1996
1997         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
1998         engine->status_page.page_addr = NULL;
1999 }
2000
2001 static void cleanup_status_page(struct intel_engine_cs *engine)
2002 {
2003         struct drm_i915_gem_object *obj;
2004
2005         obj = engine->status_page.obj;
2006         if (obj == NULL)
2007                 return;
2008
2009         kunmap(sg_page(obj->pages->sgl));
2010         i915_gem_object_ggtt_unpin(obj);
2011         drm_gem_object_unreference(&obj->base);
2012         engine->status_page.obj = NULL;
2013 }
2014
2015 static int init_status_page(struct intel_engine_cs *engine)
2016 {
2017         struct drm_i915_gem_object *obj = engine->status_page.obj;
2018
2019         if (obj == NULL) {
2020                 unsigned flags;
2021                 int ret;
2022
2023                 obj = i915_gem_alloc_object(engine->dev, 4096);
2024                 if (obj == NULL) {
2025                         DRM_ERROR("Failed to allocate status page\n");
2026                         return -ENOMEM;
2027                 }
2028
2029                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2030                 if (ret)
2031                         goto err_unref;
2032
2033                 flags = 0;
2034                 if (!HAS_LLC(engine->dev))
2035                         /* On g33, we cannot place HWS above 256MiB, so
2036                          * restrict its pinning to the low mappable arena.
2037                          * Though this restriction is not documented for
2038                          * gen4, gen5, or byt, they also behave similarly
2039                          * and hang if the HWS is placed at the top of the
2040                          * GTT. To generalise, it appears that all !llc
2041                          * platforms have issues with us placing the HWS
2042                          * above the mappable region (even though we never
2043                          * actualy map it).
2044                          */
2045                         flags |= PIN_MAPPABLE;
2046                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2047                 if (ret) {
2048 err_unref:
2049                         drm_gem_object_unreference(&obj->base);
2050                         return ret;
2051                 }
2052
2053                 engine->status_page.obj = obj;
2054         }
2055
2056         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2057         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2058         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2059
2060         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2061                         engine->name, engine->status_page.gfx_addr);
2062
2063         return 0;
2064 }
2065
2066 static int init_phys_status_page(struct intel_engine_cs *engine)
2067 {
2068         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2069
2070         if (!dev_priv->status_page_dmah) {
2071                 dev_priv->status_page_dmah =
2072                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2073                 if (!dev_priv->status_page_dmah)
2074                         return -ENOMEM;
2075         }
2076
2077         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2078         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2079
2080         return 0;
2081 }
2082
2083 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2084 {
2085         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2086                 vunmap(ringbuf->virtual_start);
2087         else
2088                 iounmap(ringbuf->virtual_start);
2089         ringbuf->virtual_start = NULL;
2090         ringbuf->vma = NULL;
2091         i915_gem_object_ggtt_unpin(ringbuf->obj);
2092 }
2093
2094 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2095 {
2096         struct sg_page_iter sg_iter;
2097         struct page **pages;
2098         void *addr;
2099         int i;
2100
2101         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2102         if (pages == NULL)
2103                 return NULL;
2104
2105         i = 0;
2106         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2107                 pages[i++] = sg_page_iter_page(&sg_iter);
2108
2109         addr = vmap(pages, i, 0, PAGE_KERNEL);
2110         drm_free_large(pages);
2111
2112         return addr;
2113 }
2114
2115 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2116                                      struct intel_ringbuffer *ringbuf)
2117 {
2118         struct drm_i915_private *dev_priv = to_i915(dev);
2119         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2120         struct drm_i915_gem_object *obj = ringbuf->obj;
2121         int ret;
2122
2123         if (HAS_LLC(dev_priv) && !obj->stolen) {
2124                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2125                 if (ret)
2126                         return ret;
2127
2128                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2129                 if (ret)
2130                         goto err_unpin;
2131
2132                 ringbuf->virtual_start = vmap_obj(obj);
2133                 if (ringbuf->virtual_start == NULL) {
2134                         ret = -ENOMEM;
2135                         goto err_unpin;
2136                 }
2137         } else {
2138                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2139                 if (ret)
2140                         return ret;
2141
2142                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2143                 if (ret)
2144                         goto err_unpin;
2145
2146                 /* Access through the GTT requires the device to be awake. */
2147                 assert_rpm_wakelock_held(dev_priv);
2148
2149                 ringbuf->virtual_start = ioremap_wc(ggtt->mappable_base +
2150                                                     i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2151                 if (ringbuf->virtual_start == NULL) {
2152                         ret = -ENOMEM;
2153                         goto err_unpin;
2154                 }
2155         }
2156
2157         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2158         return 0;
2159
2160 err_unpin:
2161         i915_gem_object_ggtt_unpin(obj);
2162         return ret;
2163 }
2164
2165 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2166 {
2167         drm_gem_object_unreference(&ringbuf->obj->base);
2168         ringbuf->obj = NULL;
2169 }
2170
2171 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2172                                       struct intel_ringbuffer *ringbuf)
2173 {
2174         struct drm_i915_gem_object *obj;
2175
2176         obj = NULL;
2177         if (!HAS_LLC(dev))
2178                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2179         if (obj == NULL)
2180                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2181         if (obj == NULL)
2182                 return -ENOMEM;
2183
2184         /* mark ring buffers as read-only from GPU side by default */
2185         obj->gt_ro = 1;
2186
2187         ringbuf->obj = obj;
2188
2189         return 0;
2190 }
2191
2192 struct intel_ringbuffer *
2193 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2194 {
2195         struct intel_ringbuffer *ring;
2196         int ret;
2197
2198         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2199         if (ring == NULL) {
2200                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2201                                  engine->name);
2202                 return ERR_PTR(-ENOMEM);
2203         }
2204
2205         ring->engine = engine;
2206         list_add(&ring->link, &engine->buffers);
2207
2208         ring->size = size;
2209         /* Workaround an erratum on the i830 which causes a hang if
2210          * the TAIL pointer points to within the last 2 cachelines
2211          * of the buffer.
2212          */
2213         ring->effective_size = size;
2214         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2215                 ring->effective_size -= 2 * CACHELINE_BYTES;
2216
2217         ring->last_retired_head = -1;
2218         intel_ring_update_space(ring);
2219
2220         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2221         if (ret) {
2222                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2223                                  engine->name, ret);
2224                 list_del(&ring->link);
2225                 kfree(ring);
2226                 return ERR_PTR(ret);
2227         }
2228
2229         return ring;
2230 }
2231
2232 void
2233 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2234 {
2235         intel_destroy_ringbuffer_obj(ring);
2236         list_del(&ring->link);
2237         kfree(ring);
2238 }
2239
2240 static int intel_init_ring_buffer(struct drm_device *dev,
2241                                   struct intel_engine_cs *engine)
2242 {
2243         struct intel_ringbuffer *ringbuf;
2244         int ret;
2245
2246         WARN_ON(engine->buffer);
2247
2248         engine->dev = dev;
2249         INIT_LIST_HEAD(&engine->active_list);
2250         INIT_LIST_HEAD(&engine->request_list);
2251         INIT_LIST_HEAD(&engine->execlist_queue);
2252         INIT_LIST_HEAD(&engine->buffers);
2253         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2254         memset(engine->semaphore.sync_seqno, 0,
2255                sizeof(engine->semaphore.sync_seqno));
2256
2257         init_waitqueue_head(&engine->irq_queue);
2258
2259         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2260         if (IS_ERR(ringbuf)) {
2261                 ret = PTR_ERR(ringbuf);
2262                 goto error;
2263         }
2264         engine->buffer = ringbuf;
2265
2266         if (I915_NEED_GFX_HWS(dev)) {
2267                 ret = init_status_page(engine);
2268                 if (ret)
2269                         goto error;
2270         } else {
2271                 WARN_ON(engine->id != RCS);
2272                 ret = init_phys_status_page(engine);
2273                 if (ret)
2274                         goto error;
2275         }
2276
2277         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2278         if (ret) {
2279                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2280                                 engine->name, ret);
2281                 intel_destroy_ringbuffer_obj(ringbuf);
2282                 goto error;
2283         }
2284
2285         ret = i915_cmd_parser_init_ring(engine);
2286         if (ret)
2287                 goto error;
2288
2289         return 0;
2290
2291 error:
2292         intel_cleanup_engine(engine);
2293         return ret;
2294 }
2295
2296 void intel_cleanup_engine(struct intel_engine_cs *engine)
2297 {
2298         struct drm_i915_private *dev_priv;
2299
2300         if (!intel_engine_initialized(engine))
2301                 return;
2302
2303         dev_priv = to_i915(engine->dev);
2304
2305         if (engine->buffer) {
2306                 intel_stop_engine(engine);
2307                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2308
2309                 intel_unpin_ringbuffer_obj(engine->buffer);
2310                 intel_ringbuffer_free(engine->buffer);
2311                 engine->buffer = NULL;
2312         }
2313
2314         if (engine->cleanup)
2315                 engine->cleanup(engine);
2316
2317         if (I915_NEED_GFX_HWS(engine->dev)) {
2318                 cleanup_status_page(engine);
2319         } else {
2320                 WARN_ON(engine->id != RCS);
2321                 cleanup_phys_status_page(engine);
2322         }
2323
2324         i915_cmd_parser_fini_ring(engine);
2325         i915_gem_batch_pool_fini(&engine->batch_pool);
2326         engine->dev = NULL;
2327 }
2328
2329 static int ring_wait_for_space(struct intel_engine_cs *engine, int n)
2330 {
2331         struct intel_ringbuffer *ringbuf = engine->buffer;
2332         struct drm_i915_gem_request *request;
2333         unsigned space;
2334         int ret;
2335
2336         if (intel_ring_space(ringbuf) >= n)
2337                 return 0;
2338
2339         /* The whole point of reserving space is to not wait! */
2340         WARN_ON(ringbuf->reserved_in_use);
2341
2342         list_for_each_entry(request, &engine->request_list, list) {
2343                 space = __intel_ring_space(request->postfix, ringbuf->tail,
2344                                            ringbuf->size);
2345                 if (space >= n)
2346                         break;
2347         }
2348
2349         if (WARN_ON(&request->list == &engine->request_list))
2350                 return -ENOSPC;
2351
2352         ret = i915_wait_request(request);
2353         if (ret)
2354                 return ret;
2355
2356         ringbuf->space = space;
2357         return 0;
2358 }
2359
2360 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2361 {
2362         uint32_t __iomem *virt;
2363         int rem = ringbuf->size - ringbuf->tail;
2364
2365         virt = ringbuf->virtual_start + ringbuf->tail;
2366         rem /= 4;
2367         while (rem--)
2368                 iowrite32(MI_NOOP, virt++);
2369
2370         ringbuf->tail = 0;
2371         intel_ring_update_space(ringbuf);
2372 }
2373
2374 int intel_engine_idle(struct intel_engine_cs *engine)
2375 {
2376         struct drm_i915_gem_request *req;
2377
2378         /* Wait upon the last request to be completed */
2379         if (list_empty(&engine->request_list))
2380                 return 0;
2381
2382         req = list_entry(engine->request_list.prev,
2383                          struct drm_i915_gem_request,
2384                          list);
2385
2386         /* Make sure we do not trigger any retires */
2387         return __i915_wait_request(req,
2388                                    atomic_read(&to_i915(engine->dev)->gpu_error.reset_counter),
2389                                    to_i915(engine->dev)->mm.interruptible,
2390                                    NULL, NULL);
2391 }
2392
2393 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2394 {
2395         request->ringbuf = request->engine->buffer;
2396         return 0;
2397 }
2398
2399 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2400 {
2401         /*
2402          * The first call merely notes the reserve request and is common for
2403          * all back ends. The subsequent localised _begin() call actually
2404          * ensures that the reservation is available. Without the begin, if
2405          * the request creator immediately submitted the request without
2406          * adding any commands to it then there might not actually be
2407          * sufficient room for the submission commands.
2408          */
2409         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2410
2411         return intel_ring_begin(request, 0);
2412 }
2413
2414 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2415 {
2416         WARN_ON(ringbuf->reserved_size);
2417         WARN_ON(ringbuf->reserved_in_use);
2418
2419         ringbuf->reserved_size = size;
2420 }
2421
2422 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2423 {
2424         WARN_ON(ringbuf->reserved_in_use);
2425
2426         ringbuf->reserved_size   = 0;
2427         ringbuf->reserved_in_use = false;
2428 }
2429
2430 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2431 {
2432         WARN_ON(ringbuf->reserved_in_use);
2433
2434         ringbuf->reserved_in_use = true;
2435         ringbuf->reserved_tail   = ringbuf->tail;
2436 }
2437
2438 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2439 {
2440         WARN_ON(!ringbuf->reserved_in_use);
2441         if (ringbuf->tail > ringbuf->reserved_tail) {
2442                 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2443                      "request reserved size too small: %d vs %d!\n",
2444                      ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2445         } else {
2446                 /*
2447                  * The ring was wrapped while the reserved space was in use.
2448                  * That means that some unknown amount of the ring tail was
2449                  * no-op filled and skipped. Thus simply adding the ring size
2450                  * to the tail and doing the above space check will not work.
2451                  * Rather than attempt to track how much tail was skipped,
2452                  * it is much simpler to say that also skipping the sanity
2453                  * check every once in a while is not a big issue.
2454                  */
2455         }
2456
2457         ringbuf->reserved_size   = 0;
2458         ringbuf->reserved_in_use = false;
2459 }
2460
2461 static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes)
2462 {
2463         struct intel_ringbuffer *ringbuf = engine->buffer;
2464         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2465         int remain_actual = ringbuf->size - ringbuf->tail;
2466         int ret, total_bytes, wait_bytes = 0;
2467         bool need_wrap = false;
2468
2469         if (ringbuf->reserved_in_use)
2470                 total_bytes = bytes;
2471         else
2472                 total_bytes = bytes + ringbuf->reserved_size;
2473
2474         if (unlikely(bytes > remain_usable)) {
2475                 /*
2476                  * Not enough space for the basic request. So need to flush
2477                  * out the remainder and then wait for base + reserved.
2478                  */
2479                 wait_bytes = remain_actual + total_bytes;
2480                 need_wrap = true;
2481         } else {
2482                 if (unlikely(total_bytes > remain_usable)) {
2483                         /*
2484                          * The base request will fit but the reserved space
2485                          * falls off the end. So don't need an immediate wrap
2486                          * and only need to effectively wait for the reserved
2487                          * size space from the start of ringbuffer.
2488                          */
2489                         wait_bytes = remain_actual + ringbuf->reserved_size;
2490                 } else if (total_bytes > ringbuf->space) {
2491                         /* No wrapping required, just waiting. */
2492                         wait_bytes = total_bytes;
2493                 }
2494         }
2495
2496         if (wait_bytes) {
2497                 ret = ring_wait_for_space(engine, wait_bytes);
2498                 if (unlikely(ret))
2499                         return ret;
2500
2501                 if (need_wrap)
2502                         __wrap_ring_buffer(ringbuf);
2503         }
2504
2505         return 0;
2506 }
2507
2508 int intel_ring_begin(struct drm_i915_gem_request *req,
2509                      int num_dwords)
2510 {
2511         struct intel_engine_cs *engine;
2512         struct drm_i915_private *dev_priv;
2513         int ret;
2514
2515         WARN_ON(req == NULL);
2516         engine = req->engine;
2517         dev_priv = req->i915;
2518
2519         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2520                                    dev_priv->mm.interruptible);
2521         if (ret)
2522                 return ret;
2523
2524         ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
2525         if (ret)
2526                 return ret;
2527
2528         engine->buffer->space -= num_dwords * sizeof(uint32_t);
2529         return 0;
2530 }
2531
2532 /* Align the ring tail to a cacheline boundary */
2533 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2534 {
2535         struct intel_engine_cs *engine = req->engine;
2536         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2537         int ret;
2538
2539         if (num_dwords == 0)
2540                 return 0;
2541
2542         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2543         ret = intel_ring_begin(req, num_dwords);
2544         if (ret)
2545                 return ret;
2546
2547         while (num_dwords--)
2548                 intel_ring_emit(engine, MI_NOOP);
2549
2550         intel_ring_advance(engine);
2551
2552         return 0;
2553 }
2554
2555 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2556 {
2557         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2558
2559         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2560          * so long as the semaphore value in the register/page is greater
2561          * than the sync value), so whenever we reset the seqno,
2562          * so long as we reset the tracking semaphore value to 0, it will
2563          * always be before the next request's seqno. If we don't reset
2564          * the semaphore value, then when the seqno moves backwards all
2565          * future waits will complete instantly (causing rendering corruption).
2566          */
2567         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2568                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2569                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2570                 if (HAS_VEBOX(dev_priv))
2571                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2572         }
2573         if (dev_priv->semaphore_obj) {
2574                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2575                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2576                 void *semaphores = kmap(page);
2577                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2578                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2579                 kunmap(page);
2580         }
2581         memset(engine->semaphore.sync_seqno, 0,
2582                sizeof(engine->semaphore.sync_seqno));
2583
2584         engine->set_seqno(engine, seqno);
2585         engine->last_submitted_seqno = seqno;
2586
2587         engine->hangcheck.seqno = seqno;
2588 }
2589
2590 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2591                                      u32 value)
2592 {
2593         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2594
2595        /* Every tail move must follow the sequence below */
2596
2597         /* Disable notification that the ring is IDLE. The GT
2598          * will then assume that it is busy and bring it out of rc6.
2599          */
2600         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2601                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2602
2603         /* Clear the context id. Here be magic! */
2604         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2605
2606         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2607         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2608                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2609                      50))
2610                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2611
2612         /* Now that the ring is fully powered up, update the tail */
2613         I915_WRITE_TAIL(engine, value);
2614         POSTING_READ(RING_TAIL(engine->mmio_base));
2615
2616         /* Let the ring send IDLE messages to the GT again,
2617          * and so let it sleep to conserve power when idle.
2618          */
2619         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2620                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2621 }
2622
2623 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2624                                u32 invalidate, u32 flush)
2625 {
2626         struct intel_engine_cs *engine = req->engine;
2627         uint32_t cmd;
2628         int ret;
2629
2630         ret = intel_ring_begin(req, 4);
2631         if (ret)
2632                 return ret;
2633
2634         cmd = MI_FLUSH_DW;
2635         if (INTEL_INFO(engine->dev)->gen >= 8)
2636                 cmd += 1;
2637
2638         /* We always require a command barrier so that subsequent
2639          * commands, such as breadcrumb interrupts, are strictly ordered
2640          * wrt the contents of the write cache being flushed to memory
2641          * (and thus being coherent from the CPU).
2642          */
2643         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2644
2645         /*
2646          * Bspec vol 1c.5 - video engine command streamer:
2647          * "If ENABLED, all TLBs will be invalidated once the flush
2648          * operation is complete. This bit is only valid when the
2649          * Post-Sync Operation field is a value of 1h or 3h."
2650          */
2651         if (invalidate & I915_GEM_GPU_DOMAINS)
2652                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2653
2654         intel_ring_emit(engine, cmd);
2655         intel_ring_emit(engine,
2656                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2657         if (INTEL_INFO(engine->dev)->gen >= 8) {
2658                 intel_ring_emit(engine, 0); /* upper addr */
2659                 intel_ring_emit(engine, 0); /* value */
2660         } else  {
2661                 intel_ring_emit(engine, 0);
2662                 intel_ring_emit(engine, MI_NOOP);
2663         }
2664         intel_ring_advance(engine);
2665         return 0;
2666 }
2667
2668 static int
2669 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2670                               u64 offset, u32 len,
2671                               unsigned dispatch_flags)
2672 {
2673         struct intel_engine_cs *engine = req->engine;
2674         bool ppgtt = USES_PPGTT(engine->dev) &&
2675                         !(dispatch_flags & I915_DISPATCH_SECURE);
2676         int ret;
2677
2678         ret = intel_ring_begin(req, 4);
2679         if (ret)
2680                 return ret;
2681
2682         /* FIXME(BDW): Address space and security selectors. */
2683         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2684                         (dispatch_flags & I915_DISPATCH_RS ?
2685                          MI_BATCH_RESOURCE_STREAMER : 0));
2686         intel_ring_emit(engine, lower_32_bits(offset));
2687         intel_ring_emit(engine, upper_32_bits(offset));
2688         intel_ring_emit(engine, MI_NOOP);
2689         intel_ring_advance(engine);
2690
2691         return 0;
2692 }
2693
2694 static int
2695 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2696                              u64 offset, u32 len,
2697                              unsigned dispatch_flags)
2698 {
2699         struct intel_engine_cs *engine = req->engine;
2700         int ret;
2701
2702         ret = intel_ring_begin(req, 2);
2703         if (ret)
2704                 return ret;
2705
2706         intel_ring_emit(engine,
2707                         MI_BATCH_BUFFER_START |
2708                         (dispatch_flags & I915_DISPATCH_SECURE ?
2709                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2710                         (dispatch_flags & I915_DISPATCH_RS ?
2711                          MI_BATCH_RESOURCE_STREAMER : 0));
2712         /* bit0-7 is the length on GEN6+ */
2713         intel_ring_emit(engine, offset);
2714         intel_ring_advance(engine);
2715
2716         return 0;
2717 }
2718
2719 static int
2720 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2721                               u64 offset, u32 len,
2722                               unsigned dispatch_flags)
2723 {
2724         struct intel_engine_cs *engine = req->engine;
2725         int ret;
2726
2727         ret = intel_ring_begin(req, 2);
2728         if (ret)
2729                 return ret;
2730
2731         intel_ring_emit(engine,
2732                         MI_BATCH_BUFFER_START |
2733                         (dispatch_flags & I915_DISPATCH_SECURE ?
2734                          0 : MI_BATCH_NON_SECURE_I965));
2735         /* bit0-7 is the length on GEN6+ */
2736         intel_ring_emit(engine, offset);
2737         intel_ring_advance(engine);
2738
2739         return 0;
2740 }
2741
2742 /* Blitter support (SandyBridge+) */
2743
2744 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2745                            u32 invalidate, u32 flush)
2746 {
2747         struct intel_engine_cs *engine = req->engine;
2748         struct drm_device *dev = engine->dev;
2749         uint32_t cmd;
2750         int ret;
2751
2752         ret = intel_ring_begin(req, 4);
2753         if (ret)
2754                 return ret;
2755
2756         cmd = MI_FLUSH_DW;
2757         if (INTEL_INFO(dev)->gen >= 8)
2758                 cmd += 1;
2759
2760         /* We always require a command barrier so that subsequent
2761          * commands, such as breadcrumb interrupts, are strictly ordered
2762          * wrt the contents of the write cache being flushed to memory
2763          * (and thus being coherent from the CPU).
2764          */
2765         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2766
2767         /*
2768          * Bspec vol 1c.3 - blitter engine command streamer:
2769          * "If ENABLED, all TLBs will be invalidated once the flush
2770          * operation is complete. This bit is only valid when the
2771          * Post-Sync Operation field is a value of 1h or 3h."
2772          */
2773         if (invalidate & I915_GEM_DOMAIN_RENDER)
2774                 cmd |= MI_INVALIDATE_TLB;
2775         intel_ring_emit(engine, cmd);
2776         intel_ring_emit(engine,
2777                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2778         if (INTEL_INFO(dev)->gen >= 8) {
2779                 intel_ring_emit(engine, 0); /* upper addr */
2780                 intel_ring_emit(engine, 0); /* value */
2781         } else  {
2782                 intel_ring_emit(engine, 0);
2783                 intel_ring_emit(engine, MI_NOOP);
2784         }
2785         intel_ring_advance(engine);
2786
2787         return 0;
2788 }
2789
2790 int intel_init_render_ring_buffer(struct drm_device *dev)
2791 {
2792         struct drm_i915_private *dev_priv = dev->dev_private;
2793         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2794         struct drm_i915_gem_object *obj;
2795         int ret;
2796
2797         engine->name = "render ring";
2798         engine->id = RCS;
2799         engine->exec_id = I915_EXEC_RENDER;
2800         engine->mmio_base = RENDER_RING_BASE;
2801
2802         if (INTEL_INFO(dev)->gen >= 8) {
2803                 if (i915_semaphore_is_enabled(dev)) {
2804                         obj = i915_gem_alloc_object(dev, 4096);
2805                         if (obj == NULL) {
2806                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2807                                 i915.semaphores = 0;
2808                         } else {
2809                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2810                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2811                                 if (ret != 0) {
2812                                         drm_gem_object_unreference(&obj->base);
2813                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2814                                         i915.semaphores = 0;
2815                                 } else
2816                                         dev_priv->semaphore_obj = obj;
2817                         }
2818                 }
2819
2820                 engine->init_context = intel_rcs_ctx_init;
2821                 engine->add_request = gen6_add_request;
2822                 engine->flush = gen8_render_ring_flush;
2823                 engine->irq_get = gen8_ring_get_irq;
2824                 engine->irq_put = gen8_ring_put_irq;
2825                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2826                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2827                 engine->get_seqno = ring_get_seqno;
2828                 engine->set_seqno = ring_set_seqno;
2829                 if (i915_semaphore_is_enabled(dev)) {
2830                         WARN_ON(!dev_priv->semaphore_obj);
2831                         engine->semaphore.sync_to = gen8_ring_sync;
2832                         engine->semaphore.signal = gen8_rcs_signal;
2833                         GEN8_RING_SEMAPHORE_INIT(engine);
2834                 }
2835         } else if (INTEL_INFO(dev)->gen >= 6) {
2836                 engine->init_context = intel_rcs_ctx_init;
2837                 engine->add_request = gen6_add_request;
2838                 engine->flush = gen7_render_ring_flush;
2839                 if (INTEL_INFO(dev)->gen == 6)
2840                         engine->flush = gen6_render_ring_flush;
2841                 engine->irq_get = gen6_ring_get_irq;
2842                 engine->irq_put = gen6_ring_put_irq;
2843                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2844                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2845                 engine->get_seqno = ring_get_seqno;
2846                 engine->set_seqno = ring_set_seqno;
2847                 if (i915_semaphore_is_enabled(dev)) {
2848                         engine->semaphore.sync_to = gen6_ring_sync;
2849                         engine->semaphore.signal = gen6_signal;
2850                         /*
2851                          * The current semaphore is only applied on pre-gen8
2852                          * platform.  And there is no VCS2 ring on the pre-gen8
2853                          * platform. So the semaphore between RCS and VCS2 is
2854                          * initialized as INVALID.  Gen8 will initialize the
2855                          * sema between VCS2 and RCS later.
2856                          */
2857                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2858                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2859                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2860                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2861                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2862                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2863                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2864                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2865                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2866                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2867                 }
2868         } else if (IS_GEN5(dev)) {
2869                 engine->add_request = pc_render_add_request;
2870                 engine->flush = gen4_render_ring_flush;
2871                 engine->get_seqno = pc_render_get_seqno;
2872                 engine->set_seqno = pc_render_set_seqno;
2873                 engine->irq_get = gen5_ring_get_irq;
2874                 engine->irq_put = gen5_ring_put_irq;
2875                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2876                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2877         } else {
2878                 engine->add_request = i9xx_add_request;
2879                 if (INTEL_INFO(dev)->gen < 4)
2880                         engine->flush = gen2_render_ring_flush;
2881                 else
2882                         engine->flush = gen4_render_ring_flush;
2883                 engine->get_seqno = ring_get_seqno;
2884                 engine->set_seqno = ring_set_seqno;
2885                 if (IS_GEN2(dev)) {
2886                         engine->irq_get = i8xx_ring_get_irq;
2887                         engine->irq_put = i8xx_ring_put_irq;
2888                 } else {
2889                         engine->irq_get = i9xx_ring_get_irq;
2890                         engine->irq_put = i9xx_ring_put_irq;
2891                 }
2892                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2893         }
2894         engine->write_tail = ring_write_tail;
2895
2896         if (IS_HASWELL(dev))
2897                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2898         else if (IS_GEN8(dev))
2899                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2900         else if (INTEL_INFO(dev)->gen >= 6)
2901                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2902         else if (INTEL_INFO(dev)->gen >= 4)
2903                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2904         else if (IS_I830(dev) || IS_845G(dev))
2905                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2906         else
2907                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2908         engine->init_hw = init_render_ring;
2909         engine->cleanup = render_ring_cleanup;
2910
2911         /* Workaround batchbuffer to combat CS tlb bug. */
2912         if (HAS_BROKEN_CS_TLB(dev)) {
2913                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2914                 if (obj == NULL) {
2915                         DRM_ERROR("Failed to allocate batch bo\n");
2916                         return -ENOMEM;
2917                 }
2918
2919                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2920                 if (ret != 0) {
2921                         drm_gem_object_unreference(&obj->base);
2922                         DRM_ERROR("Failed to ping batch bo\n");
2923                         return ret;
2924                 }
2925
2926                 engine->scratch.obj = obj;
2927                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2928         }
2929
2930         ret = intel_init_ring_buffer(dev, engine);
2931         if (ret)
2932                 return ret;
2933
2934         if (INTEL_INFO(dev)->gen >= 5) {
2935                 ret = intel_init_pipe_control(engine);
2936                 if (ret)
2937                         return ret;
2938         }
2939
2940         return 0;
2941 }
2942
2943 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2944 {
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2947
2948         engine->name = "bsd ring";
2949         engine->id = VCS;
2950         engine->exec_id = I915_EXEC_BSD;
2951
2952         engine->write_tail = ring_write_tail;
2953         if (INTEL_INFO(dev)->gen >= 6) {
2954                 engine->mmio_base = GEN6_BSD_RING_BASE;
2955                 /* gen6 bsd needs a special wa for tail updates */
2956                 if (IS_GEN6(dev))
2957                         engine->write_tail = gen6_bsd_ring_write_tail;
2958                 engine->flush = gen6_bsd_ring_flush;
2959                 engine->add_request = gen6_add_request;
2960                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2961                 engine->get_seqno = ring_get_seqno;
2962                 engine->set_seqno = ring_set_seqno;
2963                 if (INTEL_INFO(dev)->gen >= 8) {
2964                         engine->irq_enable_mask =
2965                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2966                         engine->irq_get = gen8_ring_get_irq;
2967                         engine->irq_put = gen8_ring_put_irq;
2968                         engine->dispatch_execbuffer =
2969                                 gen8_ring_dispatch_execbuffer;
2970                         if (i915_semaphore_is_enabled(dev)) {
2971                                 engine->semaphore.sync_to = gen8_ring_sync;
2972                                 engine->semaphore.signal = gen8_xcs_signal;
2973                                 GEN8_RING_SEMAPHORE_INIT(engine);
2974                         }
2975                 } else {
2976                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2977                         engine->irq_get = gen6_ring_get_irq;
2978                         engine->irq_put = gen6_ring_put_irq;
2979                         engine->dispatch_execbuffer =
2980                                 gen6_ring_dispatch_execbuffer;
2981                         if (i915_semaphore_is_enabled(dev)) {
2982                                 engine->semaphore.sync_to = gen6_ring_sync;
2983                                 engine->semaphore.signal = gen6_signal;
2984                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2985                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2986                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2987                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2988                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2989                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2990                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2991                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2992                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2993                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2994                         }
2995                 }
2996         } else {
2997                 engine->mmio_base = BSD_RING_BASE;
2998                 engine->flush = bsd_ring_flush;
2999                 engine->add_request = i9xx_add_request;
3000                 engine->get_seqno = ring_get_seqno;
3001                 engine->set_seqno = ring_set_seqno;
3002                 if (IS_GEN5(dev)) {
3003                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3004                         engine->irq_get = gen5_ring_get_irq;
3005                         engine->irq_put = gen5_ring_put_irq;
3006                 } else {
3007                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3008                         engine->irq_get = i9xx_ring_get_irq;
3009                         engine->irq_put = i9xx_ring_put_irq;
3010                 }
3011                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
3012         }
3013         engine->init_hw = init_ring_common;
3014
3015         return intel_init_ring_buffer(dev, engine);
3016 }
3017
3018 /**
3019  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3020  */
3021 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3022 {
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3025
3026         engine->name = "bsd2 ring";
3027         engine->id = VCS2;
3028         engine->exec_id = I915_EXEC_BSD;
3029
3030         engine->write_tail = ring_write_tail;
3031         engine->mmio_base = GEN8_BSD2_RING_BASE;
3032         engine->flush = gen6_bsd_ring_flush;
3033         engine->add_request = gen6_add_request;
3034         engine->irq_seqno_barrier = gen6_seqno_barrier;
3035         engine->get_seqno = ring_get_seqno;
3036         engine->set_seqno = ring_set_seqno;
3037         engine->irq_enable_mask =
3038                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3039         engine->irq_get = gen8_ring_get_irq;
3040         engine->irq_put = gen8_ring_put_irq;
3041         engine->dispatch_execbuffer =
3042                         gen8_ring_dispatch_execbuffer;
3043         if (i915_semaphore_is_enabled(dev)) {
3044                 engine->semaphore.sync_to = gen8_ring_sync;
3045                 engine->semaphore.signal = gen8_xcs_signal;
3046                 GEN8_RING_SEMAPHORE_INIT(engine);
3047         }
3048         engine->init_hw = init_ring_common;
3049
3050         return intel_init_ring_buffer(dev, engine);
3051 }
3052
3053 int intel_init_blt_ring_buffer(struct drm_device *dev)
3054 {
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3057
3058         engine->name = "blitter ring";
3059         engine->id = BCS;
3060         engine->exec_id = I915_EXEC_BLT;
3061
3062         engine->mmio_base = BLT_RING_BASE;
3063         engine->write_tail = ring_write_tail;
3064         engine->flush = gen6_ring_flush;
3065         engine->add_request = gen6_add_request;
3066         engine->irq_seqno_barrier = gen6_seqno_barrier;
3067         engine->get_seqno = ring_get_seqno;
3068         engine->set_seqno = ring_set_seqno;
3069         if (INTEL_INFO(dev)->gen >= 8) {
3070                 engine->irq_enable_mask =
3071                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3072                 engine->irq_get = gen8_ring_get_irq;
3073                 engine->irq_put = gen8_ring_put_irq;
3074                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3075                 if (i915_semaphore_is_enabled(dev)) {
3076                         engine->semaphore.sync_to = gen8_ring_sync;
3077                         engine->semaphore.signal = gen8_xcs_signal;
3078                         GEN8_RING_SEMAPHORE_INIT(engine);
3079                 }
3080         } else {
3081                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3082                 engine->irq_get = gen6_ring_get_irq;
3083                 engine->irq_put = gen6_ring_put_irq;
3084                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3085                 if (i915_semaphore_is_enabled(dev)) {
3086                         engine->semaphore.signal = gen6_signal;
3087                         engine->semaphore.sync_to = gen6_ring_sync;
3088                         /*
3089                          * The current semaphore is only applied on pre-gen8
3090                          * platform.  And there is no VCS2 ring on the pre-gen8
3091                          * platform. So the semaphore between BCS and VCS2 is
3092                          * initialized as INVALID.  Gen8 will initialize the
3093                          * sema between BCS and VCS2 later.
3094                          */
3095                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3096                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3097                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3098                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3099                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3100                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3101                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3102                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3103                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3104                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3105                 }
3106         }
3107         engine->init_hw = init_ring_common;
3108
3109         return intel_init_ring_buffer(dev, engine);
3110 }
3111
3112 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3116
3117         engine->name = "video enhancement ring";
3118         engine->id = VECS;
3119         engine->exec_id = I915_EXEC_VEBOX;
3120
3121         engine->mmio_base = VEBOX_RING_BASE;
3122         engine->write_tail = ring_write_tail;
3123         engine->flush = gen6_ring_flush;
3124         engine->add_request = gen6_add_request;
3125         engine->irq_seqno_barrier = gen6_seqno_barrier;
3126         engine->get_seqno = ring_get_seqno;
3127         engine->set_seqno = ring_set_seqno;
3128
3129         if (INTEL_INFO(dev)->gen >= 8) {
3130                 engine->irq_enable_mask =
3131                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3132                 engine->irq_get = gen8_ring_get_irq;
3133                 engine->irq_put = gen8_ring_put_irq;
3134                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3135                 if (i915_semaphore_is_enabled(dev)) {
3136                         engine->semaphore.sync_to = gen8_ring_sync;
3137                         engine->semaphore.signal = gen8_xcs_signal;
3138                         GEN8_RING_SEMAPHORE_INIT(engine);
3139                 }
3140         } else {
3141                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3142                 engine->irq_get = hsw_vebox_get_irq;
3143                 engine->irq_put = hsw_vebox_put_irq;
3144                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3145                 if (i915_semaphore_is_enabled(dev)) {
3146                         engine->semaphore.sync_to = gen6_ring_sync;
3147                         engine->semaphore.signal = gen6_signal;
3148                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3149                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3150                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3151                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3152                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3153                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3154                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3155                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3156                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3157                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3158                 }
3159         }
3160         engine->init_hw = init_ring_common;
3161
3162         return intel_init_ring_buffer(dev, engine);
3163 }
3164
3165 int
3166 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3167 {
3168         struct intel_engine_cs *engine = req->engine;
3169         int ret;
3170
3171         if (!engine->gpu_caches_dirty)
3172                 return 0;
3173
3174         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3175         if (ret)
3176                 return ret;
3177
3178         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3179
3180         engine->gpu_caches_dirty = false;
3181         return 0;
3182 }
3183
3184 int
3185 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3186 {
3187         struct intel_engine_cs *engine = req->engine;
3188         uint32_t flush_domains;
3189         int ret;
3190
3191         flush_domains = 0;
3192         if (engine->gpu_caches_dirty)
3193                 flush_domains = I915_GEM_GPU_DOMAINS;
3194
3195         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3196         if (ret)
3197                 return ret;
3198
3199         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3200
3201         engine->gpu_caches_dirty = false;
3202         return 0;
3203 }
3204
3205 void
3206 intel_stop_engine(struct intel_engine_cs *engine)
3207 {
3208         int ret;
3209
3210         if (!intel_engine_initialized(engine))
3211                 return;
3212
3213         ret = intel_engine_idle(engine);
3214         if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
3215                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3216                           engine->name, ret);
3217
3218         stop_ring(engine);
3219 }